From 2f7c68cb55ecb7331f2381deb497c27155f32faf Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 03 Jan 2024 09:43:39 +0000
Subject: [PATCH] update kernel to 5.10.198
---
kernel/drivers/media/platform/rockchip/ispp/hw.c | 152 +++++++++++++++++++++++++++++++++++---------------
1 files changed, 106 insertions(+), 46 deletions(-)
diff --git a/kernel/drivers/media/platform/rockchip/ispp/hw.c b/kernel/drivers/media/platform/rockchip/ispp/hw.c
index ef4b8c3..10545fd 100644
--- a/kernel/drivers/media/platform/rockchip/ispp/hw.c
+++ b/kernel/drivers/media/platform/rockchip/ispp/hw.c
@@ -14,7 +14,7 @@
#include <linux/pinctrl/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
-#include <media/videobuf2-dma-contig.h>
+#include <media/videobuf2-cma-sg.h>
#include <media/videobuf2-dma-sg.h>
#include <soc/rockchip/rockchip_iommu.h>
@@ -43,6 +43,7 @@
{
writel(GLB_SOFT_RST_ALL, hw->base_addr + RKISPP_CTRL_RESET);
udelay(10);
+ writel(~GLB_SOFT_RST_ALL, hw->base_addr + RKISPP_CTRL_RESET);
if (hw->reset) {
reset_control_assert(hw->reset);
udelay(20);
@@ -55,43 +56,63 @@
rockchip_iommu_disable(hw->dev);
rockchip_iommu_enable(hw->dev);
}
-
- writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL0_CTRL);
- writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL1_CTRL);
- writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL2_CTRL);
- writel(OTHER_FORCE_UPD, hw->base_addr + RKISPP_CTRL_UPDATE);
- writel(GATE_DIS_ALL, hw->base_addr + RKISPP_CTRL_CLKGATE);
- writel(SW_FEC2DDR_DIS, hw->base_addr + RKISPP_FEC_CORE_CTRL);
- writel(NR_LOST_ERR | TNR_LOST_ERR | FBCH_EMPTY_NR |
+ if (hw->ispp_ver == ISPP_V10) {
+ writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL0_CTRL);
+ writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL1_CTRL);
+ writel(SW_SCL_BYPASS, hw->base_addr + RKISPP_SCL2_CTRL);
+ writel(OTHER_FORCE_UPD, hw->base_addr + RKISPP_CTRL_UPDATE);
+ writel(GATE_DIS_ALL, hw->base_addr + RKISPP_CTRL_CLKGATE);
+ writel(SW_FEC2DDR_DIS, hw->base_addr + RKISPP_FEC_CORE_CTRL);
+ writel(NR_LOST_ERR | TNR_LOST_ERR | FBCH_EMPTY_NR |
FBCH_EMPTY_TNR | FBCD_DEC_ERR_NR | FBCD_DEC_ERR_TNR |
BUS_ERR_NR | BUS_ERR_TNR | SCL2_INT | SCL1_INT |
SCL0_INT | FEC_INT | ORB_INT | SHP_INT | NR_INT | TNR_INT,
hw->base_addr + RKISPP_CTRL_INT_MSK);
- writel(GATE_DIS_NR, hw->base_addr + RKISPP_CTRL_CLKGATE);
+ writel(GATE_DIS_NR, hw->base_addr + RKISPP_CTRL_CLKGATE);
+ } else if (hw->ispp_ver == ISPP_V20) {
+ writel(GATE_DIS_ALL, hw->base_addr + RKISPP_CTRL_CLKGATE);
+ writel(SW_FEC2DDR_DIS, hw->base_addr + RKISPP_FEC_CORE_CTRL);
+ writel(FEC_INT, hw->base_addr + RKISPP_CTRL_INT_MSK);
+ writel(GATE_DIS_FEC, hw->base_addr + RKISPP_CTRL_CLKGATE);
+ }
+
}
/* using default value if reg no write for multi device */
static void default_sw_reg_flag(struct rkispp_device *dev)
{
- u32 reg[] = {
- RKISPP_TNR_CTRL,
- RKISPP_TNR_CORE_CTRL,
- RKISPP_NR_CTRL,
- RKISPP_NR_UVNR_CTRL_PARA,
- RKISPP_SHARP_CTRL,
- RKISPP_SHARP_CORE_CTRL,
- RKISPP_SCL0_CTRL,
- RKISPP_SCL1_CTRL,
- RKISPP_SCL2_CTRL,
- RKISPP_ORB_CORE_CTRL,
- RKISPP_FEC_CTRL,
- RKISPP_FEC_CORE_CTRL
- };
- u32 i, *flag;
+ if (dev->hw_dev->ispp_ver == ISPP_V10) {
+ u32 reg[] = {
+ RKISPP_TNR_CTRL,
+ RKISPP_TNR_CORE_CTRL,
+ RKISPP_NR_CTRL,
+ RKISPP_NR_UVNR_CTRL_PARA,
+ RKISPP_SHARP_CTRL,
+ RKISPP_SHARP_CORE_CTRL,
+ RKISPP_SCL0_CTRL,
+ RKISPP_SCL1_CTRL,
+ RKISPP_SCL2_CTRL,
+ RKISPP_ORB_CORE_CTRL,
+ RKISPP_FEC_CTRL,
+ RKISPP_FEC_CORE_CTRL
+ };
+ u32 i, *flag;
- for (i = 0; i < ARRAY_SIZE(reg); i++) {
- flag = dev->sw_base_addr + reg[i] + RKISP_ISPP_SW_REG_SIZE;
- *flag = 0xffffffff;
+ for (i = 0; i < ARRAY_SIZE(reg); i++) {
+ flag = dev->sw_base_addr + reg[i] + RKISP_ISPP_SW_REG_SIZE;
+ *flag = 0xffffffff;
+ }
+ } else if (dev->hw_dev->ispp_ver == ISPP_V20) {
+ u32 reg[] = {
+ RKISPP_FEC_CTRL,
+ RKISPP_FEC_CORE_CTRL
+ };
+ u32 i, *flag;
+
+ for (i = 0; i < ARRAY_SIZE(reg); i++) {
+ flag = dev->sw_base_addr + reg[i] + RKISP_ISPP_SW_REG_SIZE;
+ *flag = 0xffffffff;
+ }
}
}
@@ -124,14 +145,18 @@
static int enable_sys_clk(struct rkispp_hw_dev *dev)
{
struct rkispp_device *ispp = dev->ispp[dev->cur_dev_id];
- u32 w = dev->max_in.w ? dev->max_in.w : ispp->ispp_sdev.in_fmt.width;
- int i, ret = -EINVAL;
+ int w, i, ret = -EINVAL;
for (i = 0; i < dev->clks_num; i++) {
ret = clk_prepare_enable(dev->clks[i]);
if (ret < 0)
goto err;
}
+
+ if (!ispp)
+ return ret;
+
+ w = dev->max_in.w ? dev->max_in.w : ispp->ispp_sdev.in_fmt.width;
for (i = 0; i < dev->clk_rate_tbl_num; i++)
if (w <= dev->clk_rate_tbl[i].refer_data)
@@ -181,6 +206,12 @@
"hclk_ispp",
};
+static const char * const rk3588_ispp_clks[] = {
+ "clk_ispp",
+ "aclk_ispp",
+ "hclk_ispp",
+};
+
static const struct ispp_clk_info rv1126_ispp_clk_rate[] = {
{
.clk_rate = 150,
@@ -200,8 +231,31 @@
}
};
+static const struct ispp_clk_info rk3588_ispp_clk_rate[] = {
+ {
+ .clk_rate = 300,
+ .refer_data = 1920, //width
+ }, {
+ .clk_rate = 400,
+ .refer_data = 2688,
+ }, {
+ .clk_rate = 500,
+ .refer_data = 3072,
+ }, {
+ .clk_rate = 600,
+ .refer_data = 3840,
+ }, {
+ .clk_rate = 702,
+ .refer_data = 4672,
+ }
+};
+
static struct irqs_data rv1126_ispp_irqs[] = {
{"ispp_irq", irq_hdl},
+ {"fec_irq", irq_hdl},
+};
+
+static struct irqs_data rk3588_ispp_irqs[] = {
{"fec_irq", irq_hdl},
};
@@ -215,10 +269,23 @@
.ispp_ver = ISPP_V10,
};
+static const struct ispp_match_data rk3588_ispp_match_data = {
+ .clks = rk3588_ispp_clks,
+ .clks_num = ARRAY_SIZE(rk3588_ispp_clks),
+ .clk_rate_tbl = rk3588_ispp_clk_rate,
+ .clk_rate_tbl_num = ARRAY_SIZE(rk3588_ispp_clk_rate),
+ .irqs = rk3588_ispp_irqs,
+ .num_irqs = ARRAY_SIZE(rk3588_ispp_irqs),
+ .ispp_ver = ISPP_V20,
+};
+
static const struct of_device_id rkispp_hw_of_match[] = {
{
.compatible = "rockchip,rv1126-rkispp",
.data = &rv1126_ispp_match_data,
+ }, {
+ .compatible = "rockchip,rk3588-rkispp",
+ .data = &rk3588_ispp_match_data,
},
{},
};
@@ -328,10 +395,13 @@
atomic_set(&hw_dev->refcnt, 0);
INIT_LIST_HEAD(&hw_dev->list);
hw_dev->is_idle = true;
- hw_dev->is_single = false;
+ hw_dev->is_single = true;
+ /* for frame end reset and config reg */
+ if (hw_dev->ispp_ver == ISPP_V10)
+ hw_dev->is_single = false;
hw_dev->is_fec_ext = false;
hw_dev->is_dma_contig = true;
- hw_dev->is_dma_sg_ops = false;
+ hw_dev->is_dma_sg_ops = true;
hw_dev->is_shutdown = false;
hw_dev->is_first = true;
hw_dev->is_mmu = is_iommu_enable(dev);
@@ -340,19 +410,10 @@
is_mem_reserved = false;
if (!hw_dev->is_mmu)
dev_info(dev, "No reserved memory region. default cma area!\n");
- else
- hw_dev->is_dma_contig = false;
}
- if (is_mem_reserved) {
- /* reserved memory using rdma_sg */
- hw_dev->mem_ops = &vb2_rdma_sg_memops;
- hw_dev->is_dma_sg_ops = true;
- } else if (hw_dev->is_mmu) {
- hw_dev->mem_ops = &vb2_dma_sg_memops;
- hw_dev->is_dma_sg_ops = true;
- } else {
- hw_dev->mem_ops = &vb2_dma_contig_memops;
- }
+ if (hw_dev->is_mmu && !is_mem_reserved)
+ hw_dev->is_dma_contig = false;
+ hw_dev->mem_ops = &vb2_cma_sg_memops;
rkispp_register_fec(hw_dev);
pm_runtime_enable(&pdev->dev);
@@ -380,6 +441,7 @@
if (pm_runtime_active(&pdev->dev)) {
writel(0, hw_dev->base_addr + RKISPP_CTRL_INT_MSK);
writel(GLB_SOFT_RST_ALL, hw_dev->base_addr + RKISPP_CTRL_RESET);
+ writel(~GLB_SOFT_RST_ALL, hw_dev->base_addr + RKISPP_CTRL_RESET);
}
dev_info(&pdev->dev, "%s\n", __func__);
}
@@ -414,8 +476,6 @@
}
static const struct dev_pm_ops rkispp_hw_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
- pm_runtime_force_resume)
SET_RUNTIME_PM_OPS(rkispp_runtime_suspend,
rkispp_runtime_resume, NULL)
};
--
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