From 2f7c68cb55ecb7331f2381deb497c27155f32faf Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 03 Jan 2024 09:43:39 +0000
Subject: [PATCH] update kernel to 5.10.198
---
kernel/drivers/media/platform/rockchip/isp/regs.h | 93 +++++++++++++++++++++++++---------------------
1 files changed, 51 insertions(+), 42 deletions(-)
diff --git a/kernel/drivers/media/platform/rockchip/isp/regs.h b/kernel/drivers/media/platform/rockchip/isp/regs.h
index bdf1be5..d263a64 100644
--- a/kernel/drivers/media/platform/rockchip/isp/regs.h
+++ b/kernel/drivers/media/platform/rockchip/isp/regs.h
@@ -36,6 +36,7 @@
#define _RKISP_REGS_H
#include "dev.h"
#include "regs_v2x.h"
+#include "regs_v3x.h"
#define CIF_ISP_PACK_4BYTE(a, b, c, d) \
(((a) & 0xFF) << 0 | ((b) & 0xFF) << 8 | \
@@ -181,7 +182,8 @@
#define MI_CTRL_SP_OUTPUT_YUV444 (3 << 28)
#define MI_CTRL_SP_OUTPUT_RGB565 (4 << 28)
#define MI_CTRL_SP_OUTPUT_RGB666 (5 << 28)
-#define MI_CTRL_SP_OUTPUT_RGB888 (6 << 28)
+#define MI_CTRL_SP_OUTPUT_ARGB888 (6 << 28)
+#define MI_CTRL_SP_OUTPUT_RGB888 (7 << 28)
#define MI_CTRL_MP_FMT_MASK GENMASK(23, 22)
#define MI_CTRL_SP_FMT_MASK GENMASK(30, 24)
@@ -1642,17 +1644,33 @@
writel(reg | CIF_MI_CTRL_INIT_OFFSET_EN, addr);
}
-static inline bool mp_is_stream_stopped(void __iomem *base)
+static inline bool mp_is_stream_stopped(struct rkisp_stream *stream)
{
- int en;
+ u32 en = CIF_MI_CTRL_SHD_MP_OUT_ENABLED | CIF_MI_CTRL_SHD_RAW_OUT_ENABLED;
+ u32 reg = CIF_MI_CTRL_SHD;
+ bool is_direct = true;
- en = CIF_MI_CTRL_SHD_MP_IN_ENABLED | CIF_MI_CTRL_SHD_RAW_OUT_ENABLED;
- return !(readl(base + CIF_MI_CTRL_SHD) & en);
+ if (!stream->ispdev->hw_dev->is_single) {
+ is_direct = false;
+ reg = CIF_MI_CTRL;
+ en = CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE;
+ }
+
+ return !(rkisp_read(stream->ispdev, reg, is_direct) & en);
}
-static inline bool sp_is_stream_stopped(void __iomem *base)
+static inline bool sp_is_stream_stopped(struct rkisp_stream *stream)
{
- return !(readl(base + CIF_MI_CTRL_SHD) & CIF_MI_CTRL_SHD_SP_IN_ENABLED);
+ u32 reg = CIF_MI_CTRL_SHD, en = CIF_MI_CTRL_SHD_SP_OUT_ENABLED;
+ bool is_direct = true;
+
+ if (!stream->ispdev->hw_dev->is_single) {
+ is_direct = false;
+ reg = CIF_MI_CTRL;
+ en = CIF_MI_CTRL_SP_ENABLE;
+ }
+
+ return !(rkisp_read(stream->ispdev, reg, is_direct) & en);
}
static inline void isp_set_bits(void __iomem *addr, u32 bit_mask, u32 val)
@@ -1734,7 +1752,9 @@
static inline void mi_frame_end_int_enable(struct rkisp_stream *stream)
{
- void __iomem *base = stream->ispdev->base_addr;
+ struct rkisp_hw_dev *hw = stream->ispdev->hw_dev;
+ void __iomem *base = hw->unite != ISP_UNITE_TWO ?
+ hw->base_addr : hw->base_next_addr;
void __iomem *addr = base + CIF_MI_IMSC;
writel(CIF_MI_FRAME(stream) | readl(addr), addr);
@@ -1742,7 +1762,9 @@
static inline void mi_frame_end_int_disable(struct rkisp_stream *stream)
{
- void __iomem *base = stream->ispdev->base_addr;
+ struct rkisp_hw_dev *hw = stream->ispdev->hw_dev;
+ void __iomem *base = hw->unite != ISP_UNITE_TWO ?
+ hw->base_addr : hw->base_next_addr;
void __iomem *addr = base + CIF_MI_IMSC;
writel(~CIF_MI_FRAME(stream) & readl(addr), addr);
@@ -1750,42 +1772,26 @@
static inline void mi_frame_end_int_clear(struct rkisp_stream *stream)
{
- void __iomem *base = stream->ispdev->base_addr;
+ struct rkisp_hw_dev *hw = stream->ispdev->hw_dev;
+ void __iomem *base = hw->unite != ISP_UNITE_TWO ?
+ hw->base_addr : hw->base_next_addr;
void __iomem *addr = base + CIF_MI_ICR;
writel(CIF_MI_FRAME(stream), addr);
}
-static inline void mp_set_chain_mode(void __iomem *base)
+static inline void stream_data_path(struct rkisp_stream *stream)
{
- u32 dpcl = readl(base + CIF_VI_DPCL);
+ struct rkisp_device *dev = stream->ispdev;
+ u32 dpcl = 0;
- dpcl |= CIF_VI_DPCL_CHAN_MODE_MP;
- writel(dpcl, base + CIF_VI_DPCL);
-}
+ if (stream->id == RKISP_STREAM_MP)
+ dpcl |= CIF_VI_DPCL_CHAN_MODE_MP | CIF_VI_DPCL_MP_MUX_MRSZ_MI;
+ else if (stream->id == RKISP_STREAM_SP)
+ dpcl |= CIF_VI_DPCL_CHAN_MODE_SP;
-static inline void sp_set_chain_mode(void __iomem *base)
-{
- u32 dpcl = readl(base + CIF_VI_DPCL);
-
- dpcl |= CIF_VI_DPCL_CHAN_MODE_SP;
- writel(dpcl, base + CIF_VI_DPCL);
-}
-
-static inline void mp_set_data_path(void __iomem *base)
-{
- u32 dpcl = readl(base + CIF_VI_DPCL);
-
- dpcl = dpcl | CIF_VI_DPCL_CHAN_MODE_MP | CIF_VI_DPCL_MP_MUX_MRSZ_MI;
- writel(dpcl, base + CIF_VI_DPCL);
-}
-
-static inline void sp_set_data_path(void __iomem *base)
-{
- u32 dpcl = readl(base + CIF_VI_DPCL);
-
- dpcl |= CIF_VI_DPCL_CHAN_MODE_SP;
- writel(dpcl, base + CIF_VI_DPCL);
+ if (dpcl)
+ rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true);
}
static inline void mp_set_uv_swap(void __iomem *base)
@@ -1906,13 +1912,16 @@
static inline void force_cfg_update(struct rkisp_device *dev)
{
- void __iomem *base = dev->base_addr;
- u32 val = readl(base + CIF_MI_CTRL);
+ u32 val = CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_CTRL_INIT_BASE_EN;
+ if (dev->isp_ver == ISP_V21) {
+ val |= rkisp_read_reg_cache(dev, CIF_MI_CTRL);
+ rkisp_write(dev, CIF_MI_CTRL, val, true);
+ }
dev->hw_dev->is_mi_update = true;
- val |= CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_CTRL_INIT_BASE_EN;
- writel(val, base + CIF_MI_CTRL);
- writel(CIF_MI_INIT_SOFT_UPD, base + CIF_MI_INIT);
+ rkisp_unite_set_bits(dev, CIF_MI_CTRL, 0, val, false);
+ val = CIF_MI_INIT_SOFT_UPD;
+ rkisp_unite_write(dev, CIF_MI_INIT, val, true);
}
static inline void dmatx0_ctrl(void __iomem *base, u32 val)
--
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