From 2f7c68cb55ecb7331f2381deb497c27155f32faf Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 03 Jan 2024 09:43:39 +0000
Subject: [PATCH] update kernel to 5.10.198
---
kernel/arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1673 +++++++++++++++++++++++++++++++----------------------------
1 files changed, 875 insertions(+), 798 deletions(-)
diff --git a/kernel/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/kernel/arch/arm64/boot/dts/rockchip/rk3308.dtsi
index dd50c25..fe3ab33 100644
--- a/kernel/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+++ b/kernel/arch/arm64/boot/dts/rockchip/rk3308.dtsi
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
*
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
*/
#include <dt-bindings/clock/rk3308-cru.h>
@@ -23,6 +23,11 @@
aliases {
ethernet0 = &mac;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -43,13 +48,13 @@
cpu0: cpu@0 {
device_type = "cpu";
- compatible = "arm,cortex-a35", "arm,armv8";
+ compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
dynamic-power-coefficient = <83>;
- operating-points-v2 = <&cpu0_opp_table>;
+ operating-points-v2 = <&cpu0_opp_table>, <&rk3308bs_cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
next-level-cache = <&l2>;
power-model {
@@ -64,30 +69,30 @@
cpu1: cpu@1 {
device_type = "cpu";
- compatible = "arm,cortex-a35", "arm,armv8";
+ compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
+ operating-points-v2 = <&cpu0_opp_table>, <&rk3308bs_cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
- compatible = "arm,cortex-a35", "arm,armv8";
+ compatible = "arm,cortex-a35";
reg = <0x0 0x2>;
enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
+ operating-points-v2 = <&cpu0_opp_table>, <&rk3308bs_cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
- compatible = "arm,cortex-a35", "arm,armv8";
+ compatible = "arm,cortex-a35";
reg = <0x0 0x3>;
enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
+ operating-points-v2 = <&cpu0_opp_table>, <&rk3308bs_cpu0_opp_table>;
cpu-idle-states = <&CPU_SLEEP>;
next-level-cache = <&l2>;
};
@@ -117,7 +122,7 @@
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <0>;
rockchip,low-temp-min-volt = <1000000>;
- rockchip,max-volt = <1340000>;
+ rockchip,max-volt = <1325000>;
rockchip,low-temp-adjust-volt = <
/* MHz MHz uV */
0 1296 50000
@@ -147,65 +152,112 @@
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <950000 950000 1340000>;
+ opp-microvolt = <950000 950000 1325000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <950000 950000 1340000>;
+ opp-microvolt = <950000 950000 1325000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1025000 1025000 1340000>;
- opp-microvolt-L0 = <1025000 1025000 1340000>;
- opp-microvolt-L1 = <1025000 1025000 1340000>;
- opp-microvolt-L2 = <1025000 1025000 1340000>;
- opp-microvolt-L3 = <1000000 1000000 1340000>;
- opp-microvolt-L4 = <975000 975000 1340000>;
- opp-microvolt-L5 = <950000 950000 1340000>;
+ opp-microvolt = <1025000 1025000 1325000>;
+ opp-microvolt-L0 = <1025000 1025000 1325000>;
+ opp-microvolt-L1 = <1025000 1025000 1325000>;
+ opp-microvolt-L2 = <1025000 1025000 1325000>;
+ opp-microvolt-L3 = <1000000 1000000 1325000>;
+ opp-microvolt-L4 = <975000 975000 1325000>;
+ opp-microvolt-L5 = <950000 950000 1325000>;
clock-latency-ns = <40000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1125000 1125000 1340000>;
- opp-microvolt-L0 = <1125000 1125000 1340000>;
- opp-microvolt-L1 = <1100000 1100000 1340000>;
- opp-microvolt-L2 = <1100000 1100000 1340000>;
- opp-microvolt-L3 = <1075000 1075000 1340000>;
- opp-microvolt-L4 = <1050000 1050000 1340000>;
- opp-microvolt-L5 = <1025000 1025000 1340000>;
+ opp-microvolt = <1125000 1125000 1325000>;
+ opp-microvolt-L0 = <1125000 1125000 1325000>;
+ opp-microvolt-L1 = <1100000 1100000 1325000>;
+ opp-microvolt-L2 = <1100000 1100000 1325000>;
+ opp-microvolt-L3 = <1075000 1075000 1325000>;
+ opp-microvolt-L4 = <1050000 1050000 1325000>;
+ opp-microvolt-L5 = <1025000 1025000 1325000>;
clock-latency-ns = <40000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1250000 1250000 1340000>;
- opp-microvolt-L0 = <1250000 1250000 1340000>;
- opp-microvolt-L1 = <1225000 1225000 1340000>;
- opp-microvolt-L2 = <1200000 1200000 1340000>;
- opp-microvolt-L3 = <1175000 1175000 1340000>;
- opp-microvolt-L4 = <1150000 1150000 1340000>;
- opp-microvolt-L5 = <1125000 1125000 1340000>;
+ opp-microvolt = <1250000 1250000 1325000>;
+ opp-microvolt-L0 = <1250000 1250000 1325000>;
+ opp-microvolt-L1 = <1225000 1225000 1325000>;
+ opp-microvolt-L2 = <1200000 1200000 1325000>;
+ opp-microvolt-L3 = <1175000 1175000 1325000>;
+ opp-microvolt-L4 = <1150000 1150000 1325000>;
+ opp-microvolt-L5 = <1125000 1125000 1325000>;
clock-latency-ns = <40000>;
status = "disabled";
};
opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
- opp-microvolt = <1300000 1300000 1340000>;
- opp-microvolt-L0 = <1300000 1300000 1340000>;
- opp-microvolt-L1 = <1275000 1275000 1340000>;
- opp-microvolt-L2 = <1250000 1250000 1340000>;
- opp-microvolt-L3 = <1225000 1225000 1340000>;
- opp-microvolt-L4 = <1200000 1200000 1340000>;
- opp-microvolt-L5 = <1175000 1175000 1340000>;
+ opp-microvolt = <1300000 1300000 1325000>;
+ opp-microvolt-L0 = <1300000 1300000 1325000>;
+ opp-microvolt-L1 = <1275000 1275000 1325000>;
+ opp-microvolt-L2 = <1250000 1250000 1325000>;
+ opp-microvolt-L3 = <1225000 1225000 1325000>;
+ opp-microvolt-L4 = <1200000 1200000 1325000>;
+ opp-microvolt-L5 = <1175000 1175000 1325000>;
+ clock-latency-ns = <40000>;
+ status = "disabled";
+ };
+ };
+
+ rk3308bs_cpu0_opp_table: rk3308bs-cpu0-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ rockchip,temp-hysteresis = <5000>;
+ rockchip,low-temp = <0>;
+ rockchip,low-temp-min-volt = <900000>;
+ rockchip,max-volt = <1200000>;
+ rockchip,low-temp-adjust-volt = <
+ /* MHz MHz uV */
+ 0 1200 50000
+ >;
+
+ rockchip,evb-irdrop = <25000>;
+ nvmem-cells = <&cpu_leakage>;
+ nvmem-cell-names = "leakage";
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <850000 850000 1200000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <900000 900000 1200000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000 1000000 1200000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1125000 1125000 1200000>;
+ clock-latency-ns = <40000>;
+ status = "disabled";
+ };
+ opp-1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <1200000 1200000 1200000>;
clock-latency-ns = <40000>;
status = "disabled";
};
};
arm-pmu {
- compatible = "arm,cortex-a53-pmu";
+ compatible = "arm,cortex-a35-pmu";
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
@@ -229,7 +281,7 @@
route_rgb: route-rgb {
status = "disabled";
logo,uboot = "logo.bmp";
- /* logo,kernel = "logo_kernel.bmp"; */
+ logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vop_out_rgb>;
@@ -241,7 +293,7 @@
compatible = "rockchip,rk3308-dmc";
clocks = <&cru SCLK_DDRCLK>;
clock-names = "dmc_clk";
- operating-points-v2 = <&dmc_opp_table>;
+ operating-points-v2 = <&dmc_opp_table>, <&rk3308bs_dmc_opp_table>;
status = "disabled";
};
@@ -264,22 +316,31 @@
};
};
+ rk3308bs_dmc_opp_table: rk3308bs-dmc-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-394000000 {
+ opp-hz = /bits/ 64 <394000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-452000000 {
+ opp-hz = /bits/ 64 <452000000>;
+ opp-microvolt = <900000>;
+ };
+ opp-590000000 {
+ opp-hz = /bits/ 64 <590000000>;
+ opp-microvolt = <900000>;
+ };
+ };
+
fiq_debugger: fiq-debugger {
compatible = "rockchip,fiq-debugger";
rockchip,serial-id = <2>;
rockchip,wake-irq = <0>;
- rockchip,irq-mode-enable = <0>;
+ rockchip,irq-mode-enable = <1>;
rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
- };
-
- firmware {
- optee: optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- status = "disabled";
- };
};
mac_clkin: external-mac-clock {
@@ -292,6 +353,20 @@
psci {
compatible = "arm,psci-1.0";
method = "smc";
+ };
+
+ ramoops_mem: ramoops_mem {
+ reg = <0x0 0x110000 0x0 0xf0000>;
+ reg-names = "ramoops_mem";
+ };
+
+ ramoops: ramoops {
+ compatible = "ramoops";
+ record-size = <0x0 0x30000>;
+ console-size = <0x0 0xc0000>;
+ ftrace-size = <0x0 0x00000>;
+ pmsg-size = <0x0 0x00000>;
+ memory-region = <&ramoops_mem>;
};
rgb: rgb {
@@ -327,15 +402,6 @@
drm_logo: drm-logo@00000000 {
compatible = "rockchip,drm-logo";
reg = <0x0 0x0 0x0 0x0>;
- };
-
- ramoops: ramoops@110000 {
- compatible = "ramoops";
- reg = <0x0 0x110000 0x0 0xf0000>;
- record-size = <0x30000>;
- console-size = <0xc0000>;
- ftrace-size = <0x00000>;
- pmsg-size = <0x00000>;
};
};
@@ -380,14 +446,8 @@
pmu_pvtm: pmu-pvtm {
compatible = "rockchip,rk3308-pmu-pvtm";
- #address-cells = <1>;
- #size-cells = <0>;
-
- pvtm@1 {
- reg = <1>;
- clocks = <&cru SCLK_PVTM_PMU>;
- clock-names = "clk";
- };
+ clocks = <&cru SCLK_PVTM_PMU>;
+ clock-names = "pmu";
};
reboot-mode {
@@ -398,37 +458,69 @@
mode-normal = <BOOT_NORMAL>;
mode-recovery = <BOOT_RECOVERY>;
mode-fastboot = <BOOT_FASTBOOT>;
+ mode-panic = <BOOT_PANIC>;
+ mode-watchdog = <BOOT_WATCHDOG>;
+ };
+ };
+
+ usb2phy_grf: syscon@ff008000 {
+ compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xff008000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy: usb2phy@100 {
+ compatible = "rockchip,rk3308-usb2phy";
+ reg = <0x100 0x10>;
+ assigned-clocks = <&cru USB480M>;
+ assigned-clock-parents = <&u2phy>;
+ clocks = <&cru SCLK_USBPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
};
};
detect_grf: syscon@ff00b000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
reg = <0x0 0xff00b000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
};
core_grf: syscon@ff00c000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
reg = <0x0 0xff00c000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
pvtm: pvtm {
compatible = "rockchip,rk3308-pvtm";
- #address-cells = <1>;
- #size-cells = <0>;
-
- pvtm@0 {
- reg = <0>;
- clocks = <&cru SCLK_PVTM_CORE>;
- clock-names = "clk";
- };
+ clocks = <&cru SCLK_PVTM_CORE>;
+ clock-names = "core";
};
};
i2c0: i2c@ff040000 {
- compatible = "rockchip,rk3399-i2c";
+ compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xff040000 0x0 0x1000>;
clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
clock-names = "i2c", "pclk";
@@ -441,7 +533,7 @@
};
i2c1: i2c@ff050000 {
- compatible = "rockchip,rk3399-i2c";
+ compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xff050000 0x0 0x1000>;
clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
clock-names = "i2c", "pclk";
@@ -454,7 +546,7 @@
};
i2c2: i2c@ff060000 {
- compatible = "rockchip,rk3399-i2c";
+ compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xff060000 0x0 0x1000>;
clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
clock-names = "i2c", "pclk";
@@ -467,7 +559,7 @@
};
i2c3: i2c@ff070000 {
- compatible = "rockchip,rk3399-i2c";
+ compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xff070000 0x0 0x1000>;
clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
clock-names = "i2c", "pclk";
@@ -479,45 +571,8 @@
status = "disabled";
};
- usb2phy_grf: syscon@ff008000 {
- compatible = "rockchip,rk3308-usb2phy-grf", "syscon",
- "simple-mfd";
- reg = <0x0 0xff008000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- u2phy: usb2-phy@100 {
- compatible = "rockchip,rk3308-usb2phy";
- reg = <0x100 0x10>;
- clocks = <&cru SCLK_USBPHY_REF>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- assigned-clocks = <&cru USB480M>;
- assigned-clock-parents = <&u2phy>;
- clock-output-names = "usb480m_phy";
- status = "disabled";
-
- u2phy_otg: otg-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "otg-bvalid", "otg-id",
- "linestate";
- status = "disabled";
- };
-
- u2phy_host: host-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "linestate";
- status = "disabled";
- };
- };
- };
-
wdt: watchdog@ff080000 {
- compatible = "snps,dw-wdt";
+ compatible = "rockchip,rk3308-wdt", "snps,dw-wdt";
reg = <0x0 0xff080000 0x0 0x100>;
clocks = <&cru PCLK_WDT>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
@@ -650,132 +705,144 @@
pwm8: pwm@ff160000 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff160000 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm8_pin>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm8_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm9: pwm@ff160010 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff160010 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm9_pin>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm9_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm10: pwm@ff160020 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff160020 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm10_pin>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm10_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm11: pwm@ff160030 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff160030 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm11_pin>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm11_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm4: pwm@ff170000 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff170000 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm4_pin>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm4_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm5: pwm@ff170010 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff170010 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm5_pin>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm5_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm6: pwm@ff170020 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff170020 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm6_pin>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm6_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm7: pwm@ff170030 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff170030 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm7_pin>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm7_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm0: pwm@ff180000 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff180000 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm0_pin>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm0_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm1: pwm@ff180010 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff180010 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm1_pin>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm1_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm2: pwm@ff180020 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff180020 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm2_pin>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm2_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm3: pwm@ff180030 {
compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff180030 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm3_pin>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm3_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -800,9 +867,9 @@
compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
reg = <0x0 0xff1e0000 0x0 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- #io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
+ #io-channel-cells = <1>;
resets = <&cru SRST_SARADC_P>;
reset-names = "saradc-apb";
status = "disabled";
@@ -818,12 +885,12 @@
thermal-sensors = <&tsadc 0>;
trips {
- threshold: trip-point-0 {
+ threshold: trip-point@0 {
temperature = <70000>;
hysteresis = <2000>;
type = "passive";
};
- target: trip-point-1 {
+ target: trip-point@1 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
@@ -842,10 +909,9 @@
contribution = <4096>;
};
};
-
};
- logic_thermal: logic-thermal {
+ gpu_thermal: gpu-thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <1000>; /* milliseconds */
@@ -865,7 +931,7 @@
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "gpio", "otpout";
- pinctrl-0 = <&tsadc_otp_gpio>;
+ pinctrl-0 = <&tsadc_otp_pin>;
pinctrl-1 = <&tsadc_otp_out>;
#thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <120000>;
@@ -895,33 +961,26 @@
};
};
- amba {
- compatible = "arm,amba-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ dmac0: dma-controller@ff2c0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff2c0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC0>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
- dmac0: dma-controller@ff2c0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xff2c0000 0x0 0x4000>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- clocks = <&cru ACLK_DMAC0>;
- clock-names = "apb_pclk";
- arm,pl330-periph-burst;
- };
-
- dmac1: dma-controller@ff2d0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0xff2d0000 0x0 0x4000>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- clocks = <&cru ACLK_DMAC1>;
- clock-names = "apb_pclk";
- arm,pl330-periph-burst;
- };
+ dmac1: dma-controller@ff2d0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff2d0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC1>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
};
vop: vop@ff2e0000 {
@@ -945,17 +1004,17 @@
};
};
- rng: rng@ff2f0000 {
+ rng: rng@ff2f0400 {
compatible = "rockchip,cryptov2-rng";
- reg = <0x0 0xff2f0000 0x0 0x4000>;
+ reg = <0x0 0xff2f0400 0x0 0x80>;
clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
- <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
+ <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
clock-names = "clk_crypto", "clk_crypto_apk",
- "aclk_crypto", "hclk_crypto";
+ "aclk_crypto", "hclk_crypto";
assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
- <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
+ <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
assigned-clock-rates = <150000000>, <150000000>,
- <200000000>, <100000000>;
+ <200000000>, <100000000>;
resets = <&cru SRST_CRYPTO>;
reset-names = "reset";
status = "disabled";
@@ -1016,6 +1075,7 @@
rockchip,cru = <&cru>;
rockchip,grf = <&grf>;
rockchip,mclk-calibrate;
+ rockchip,io-multiplex;
status = "disabled";
};
@@ -1096,7 +1156,7 @@
};
pdm_8ch: pdm@ff380000 {
- compatible = "rockchip,rk3308-pdm";
+ compatible = "rockchip,rk3308-pdm", "rockchip,pdm";
reg = <0x0 0xff380000 0x0 0x1000>;
clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
clock-names = "pdm_clk", "pdm_hclk";
@@ -1114,7 +1174,7 @@
};
spdif_tx: spdif-tx@ff3a0000 {
- compatible = "rockchip,rk3308-spdif", "rockchip,rk3328-spdif";
+ compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif";
reg = <0x0 0xff3a0000 0x0 0x1000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
@@ -1156,7 +1216,8 @@
};
usb20_otg: usb@ff400000 {
- compatible = "rockchip,rk3066-usb", "snps,dwc2";
+ compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
reg = <0x0 0xff400000 0x0 0x40000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG>;
@@ -1165,7 +1226,6 @@
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <280>;
g-tx-fifo-size = <256 128 128 64 32 16>;
- g-use-dma;
phys = <&u2phy_otg>;
phy-names = "usb2-phy";
status = "disabled";
@@ -1193,46 +1253,61 @@
status = "disabled";
};
- sdmmc: dwmmc@ff480000 {
+ sdmmc: mmc@ff480000 {
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff480000 0x0 0x4000>;
- max-frequency = <150000000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <4>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
status = "disabled";
};
- emmc: dwmmc@ff490000 {
+ emmc: mmc@ff490000 {
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff490000 0x0 0x4000>;
- max-frequency = <150000000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
status = "disabled";
};
- sdio: dwmmc@ff4a0000 {
+ sdio: mmc@ff4a0000 {
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff4a0000 0x0 0x4000>;
- max-frequency = <150000000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <4>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
+ status = "disabled";
+ };
+
+ nfc: nand-controller@ff4b0000 {
+ compatible = "rockchip,rk3308-nfc",
+ "rockchip,rv1108-nfc";
+ reg = <0x0 0xff4b0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
+ clock-names = "ahb", "nfc";
+ assigned-clocks = <&cru SCLK_NANDC>;
+ assigned-clock-rates = <150000000>;
+ pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0
+ &flash_rdn &flash_rdy &flash_wrn>;
+ pinctrl-names = "default";
status = "disabled";
};
@@ -1246,21 +1321,9 @@
status = "disabled";
};
- sfc: sfc@ff4c0000 {
- compatible = "rockchip,sfc";
- reg = <0x0 0xff4c0000 0x0 0x4000>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
- clock-names = "clk_sfc", "hclk_sfc";
- assigned-clocks = <&cru SCLK_SFC>;
- assigned-clock-rates = <100000000>;
- status = "disabled";
- };
-
mac: ethernet@ff4e0000 {
compatible = "rockchip,rk3308-mac";
reg = <0x0 0xff4e0000 0x0 0x10000>;
- rockchip,grf = <&grf>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
@@ -1276,6 +1339,18 @@
pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
resets = <&cru SRST_MAC_A>;
reset-names = "stmmaceth";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+ sfc: spi@ff4c0000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xff4c0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ assigned-clocks = <&cru SCLK_SFC>;
+ assigned-clock-rates = <100000000>;
status = "disabled";
};
@@ -1286,7 +1361,6 @@
rockchip,boost = <&cpu_boost>;
#clock-cells = <1>;
#reset-cells = <1>;
-
assigned-clocks = <&cru SCLK_RTC32K>;
assigned-clock-rates = <32768>;
};
@@ -1309,32 +1383,34 @@
clock-names = "acodec", "mclk_tx", "mclk_rx";
resets = <&cru SRST_ACODEC_P>;
reset-names = "acodec-reset";
+ spk_ctl-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
gic: interrupt-controller@ff580000 {
compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
-
reg = <0x0 0xff581000 0x0 0x1000>,
<0x0 0xff582000 0x0 0x2000>,
<0x0 0xff584000 0x0 0x2000>,
<0x0 0xff586000 0x0 0x2000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #address-cells = <0>;
};
sram: sram@fff80000 {
compatible = "mmio-sram";
reg = <0x0 0xfff80000 0x0 0x40000>;
+ ranges = <0 0x0 0xfff80000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0x0 0xfff80000 0x40000>;
+
/* reserved for ddr dvfs and system suspend/resume */
ddr-sram@0 {
reg = <0x0 0x8000>;
};
+
/* reserved for vad audio buffer */
vad_sram: vad-sram@8000 {
reg = <0x8000 0x38000>;
@@ -1362,7 +1438,6 @@
clocks = <&cru PCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
-
interrupt-controller;
#interrupt-cells = <2>;
};
@@ -1374,7 +1449,6 @@
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
-
interrupt-controller;
#interrupt-cells = <2>;
};
@@ -1386,7 +1460,6 @@
clocks = <&cru PCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
-
interrupt-controller;
#interrupt-cells = <2>;
};
@@ -1398,7 +1471,6 @@
clocks = <&cru PCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
-
interrupt-controller;
#interrupt-cells = <2>;
};
@@ -1410,7 +1482,6 @@
clocks = <&cru PCLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
-
interrupt-controller;
#interrupt-cells = <2>;
};
@@ -1494,6 +1565,202 @@
input-enable;
};
+ can-m0 {
+ canm0_pins: canm0-pins {
+ rockchip,pins =
+ /* can_rxd_m0 */
+ <0 RK_PB3 2 &pcfg_pull_none>,
+ /* can_txd_m0 */
+ <0 RK_PB4 2 &pcfg_pull_none>;
+ };
+ };
+
+ can-m1 {
+ canm1_pins: canm1-pins {
+ rockchip,pins =
+ /* can_rxd_m1 */
+ <1 RK_PC6 5 &pcfg_pull_none>,
+ /* can_txd_m1 */
+ <1 RK_PC7 5 &pcfg_pull_none>;
+ };
+ };
+
+ can-m2 {
+ canm2_pins: canm2-pins {
+ rockchip,pins =
+ /* can_rxd_m2 */
+ <2 RK_PA2 4 &pcfg_pull_none>,
+ /* can_txd_m2 */
+ <2 RK_PA3 4 &pcfg_pull_none>;
+ };
+ };
+
+ emmc {
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ <3 RK_PB1 2 &pcfg_pull_none_8ma>;
+ };
+
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ <3 RK_PB0 2 &pcfg_pull_up_8ma>;
+ };
+
+ emmc_pwren: emmc-pwren {
+ rockchip,pins =
+ <3 RK_PB3 2 &pcfg_pull_none>;
+ };
+
+ emmc_rstn: emmc-rstn {
+ rockchip,pins =
+ <3 RK_PB2 2 &pcfg_pull_none>;
+ };
+
+ emmc_bus1: emmc-bus1 {
+ rockchip,pins =
+ <3 RK_PA0 2 &pcfg_pull_up_8ma>;
+ };
+
+ emmc_bus4: emmc-bus4 {
+ rockchip,pins =
+ <3 RK_PA0 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA1 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA2 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA3 2 &pcfg_pull_up_8ma>;
+ };
+
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ <3 RK_PA0 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA1 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA2 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA3 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA4 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA5 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA6 2 &pcfg_pull_up_8ma>,
+ <3 RK_PA7 2 &pcfg_pull_up_8ma>;
+ };
+ };
+
+ ext_micbias {
+ ext_micbias_en: ext-micbias-en {
+ rockchip,pins =
+ <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+
+ flash {
+ flash_csn0: flash-csn0 {
+ rockchip,pins =
+ <3 RK_PB5 1 &pcfg_pull_none>;
+ };
+
+ flash_rdy: flash-rdy {
+ rockchip,pins =
+ <3 RK_PB4 1 &pcfg_pull_none>;
+ };
+
+ flash_ale: flash-ale {
+ rockchip,pins =
+ <3 RK_PB3 1 &pcfg_pull_none>;
+ };
+
+ flash_cle: flash-cle {
+ rockchip,pins =
+ <3 RK_PB1 1 &pcfg_pull_none>;
+ };
+
+ flash_wrn: flash-wrn {
+ rockchip,pins =
+ <3 RK_PB0 1 &pcfg_pull_none>;
+ };
+
+ flash_rdn: flash-rdn {
+ rockchip,pins =
+ <3 RK_PB2 1 &pcfg_pull_none>;
+ };
+
+ flash_bus8: flash-bus8 {
+ rockchip,pins =
+ <3 RK_PA0 1 &pcfg_pull_up_12ma>,
+ <3 RK_PA1 1 &pcfg_pull_up_12ma>,
+ <3 RK_PA2 1 &pcfg_pull_up_12ma>,
+ <3 RK_PA3 1 &pcfg_pull_up_12ma>,
+ <3 RK_PA4 1 &pcfg_pull_up_12ma>,
+ <3 RK_PA5 1 &pcfg_pull_up_12ma>,
+ <3 RK_PA6 1 &pcfg_pull_up_12ma>,
+ <3 RK_PA7 1 &pcfg_pull_up_12ma>;
+ };
+ };
+
+ gmac {
+ rmii_pins: rmii-pins {
+ rockchip,pins =
+ /* mac_txen */
+ <1 RK_PC1 3 &pcfg_pull_none_12ma>,
+ /* mac_txd1 */
+ <1 RK_PC3 3 &pcfg_pull_none_12ma>,
+ /* mac_txd0 */
+ <1 RK_PC2 3 &pcfg_pull_none_12ma>,
+ /* mac_rxd0 */
+ <1 RK_PC4 3 &pcfg_pull_none>,
+ /* mac_rxd1 */
+ <1 RK_PC5 3 &pcfg_pull_none>,
+ /* mac_rxer */
+ <1 RK_PB7 3 &pcfg_pull_none>,
+ /* mac_rxdv */
+ <1 RK_PC0 3 &pcfg_pull_none>,
+ /* mac_mdio */
+ <1 RK_PB6 3 &pcfg_pull_none>,
+ /* mac_mdc */
+ <1 RK_PB5 3 &pcfg_pull_none>;
+ };
+
+ mac_refclk_12ma: mac-refclk-12ma {
+ rockchip,pins =
+ <1 RK_PB4 3 &pcfg_pull_none_12ma>;
+ };
+
+ mac_refclk: mac-refclk {
+ rockchip,pins =
+ <1 RK_PB4 3 &pcfg_pull_none>;
+ };
+ };
+
+ gmac-m1 {
+ rmiim1_pins: rmiim1-pins {
+ rockchip,pins =
+ /* mac_txen */
+ <4 RK_PB7 2 &pcfg_pull_none_12ma>,
+ /* mac_txd1 */
+ <4 RK_PA5 2 &pcfg_pull_none_12ma>,
+ /* mac_txd0 */
+ <4 RK_PA4 2 &pcfg_pull_none_12ma>,
+ /* mac_rxd0 */
+ <4 RK_PA2 2 &pcfg_pull_none>,
+ /* mac_rxd1 */
+ <4 RK_PA3 2 &pcfg_pull_none>,
+ /* mac_rxer */
+ <4 RK_PA0 2 &pcfg_pull_none>,
+ /* mac_rxdv */
+ <4 RK_PA1 2 &pcfg_pull_none>,
+ /* mac_mdio */
+ <4 RK_PB6 2 &pcfg_pull_none>,
+ /* mac_mdc */
+ <4 RK_PB5 2 &pcfg_pull_none>;
+ };
+
+ macm1_refclk_12ma: macm1-refclk-12ma {
+ rockchip,pins =
+ <4 RK_PB4 2 &pcfg_pull_none_12ma>;
+ };
+
+ macm1_refclk: macm1-refclk {
+ rockchip,pins =
+ <4 RK_PB4 2 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins =
@@ -1545,17 +1812,17 @@
i2s_2ch_0 {
i2s_2ch_0_mclk: i2s-2ch-0-mclk {
rockchip,pins =
- <4 RK_PB4 1 &pcfg_pull_none>;
+ <4 RK_PB4 1 &pcfg_pull_none_smt>;
};
i2s_2ch_0_sclk: i2s-2ch-0-sclk {
rockchip,pins =
- <4 RK_PB5 1 &pcfg_pull_none>;
+ <4 RK_PB5 1 &pcfg_pull_none_smt>;
};
i2s_2ch_0_lrck: i2s-2ch-0-lrck {
rockchip,pins =
- <4 RK_PB6 1 &pcfg_pull_none>;
+ <4 RK_PB6 1 &pcfg_pull_none_smt>;
};
i2s_2ch_0_sdo: i2s-2ch-0-sdo {
@@ -1572,27 +1839,27 @@
i2s_8ch_0 {
i2s_8ch_0_mclk: i2s-8ch-0-mclk {
rockchip,pins =
- <2 RK_PA4 1 &pcfg_pull_none>;
+ <2 RK_PA4 1 &pcfg_pull_none_smt>;
};
i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
rockchip,pins =
- <2 RK_PA5 1 &pcfg_pull_none>;
+ <2 RK_PA5 1 &pcfg_pull_none_smt>;
};
i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
rockchip,pins =
- <2 RK_PA6 1 &pcfg_pull_none>;
+ <2 RK_PA6 1 &pcfg_pull_none_smt>;
};
i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
rockchip,pins =
- <2 RK_PA7 1 &pcfg_pull_none>;
+ <2 RK_PA7 1 &pcfg_pull_none_smt>;
};
i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
rockchip,pins =
- <2 RK_PB0 1 &pcfg_pull_none>;
+ <2 RK_PB0 1 &pcfg_pull_none_smt>;
};
i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
@@ -1639,27 +1906,27 @@
i2s_8ch_1_m0 {
i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
rockchip,pins =
- <1 RK_PA2 2 &pcfg_pull_none>;
+ <1 RK_PA2 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
rockchip,pins =
- <1 RK_PA3 2 &pcfg_pull_none>;
+ <1 RK_PA3 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
rockchip,pins =
- <1 RK_PA4 2 &pcfg_pull_none>;
+ <1 RK_PA4 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
rockchip,pins =
- <1 RK_PA5 2 &pcfg_pull_none>;
+ <1 RK_PA5 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
rockchip,pins =
- <1 RK_PA6 2 &pcfg_pull_none>;
+ <1 RK_PA6 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
@@ -1691,27 +1958,27 @@
i2s_8ch_1_m1 {
i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
rockchip,pins =
- <1 RK_PB4 2 &pcfg_pull_none>;
+ <1 RK_PB4 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
rockchip,pins =
- <1 RK_PB5 2 &pcfg_pull_none>;
+ <1 RK_PB5 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
rockchip,pins =
- <1 RK_PB6 2 &pcfg_pull_none>;
+ <1 RK_PB6 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
rockchip,pins =
- <1 RK_PB7 2 &pcfg_pull_none>;
+ <1 RK_PB7 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
rockchip,pins =
- <1 RK_PC0 2 &pcfg_pull_none>;
+ <1 RK_PC0 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
@@ -1744,81 +2011,105 @@
lcdc_ctl: lcdc-ctl {
rockchip,pins =
/* dclk */
- <1 RK_PA0 1 &pcfg_pull_none>,
+ <1 RK_PA0 1 &pcfg_pull_none_4ma>,
/* hsync */
- <1 RK_PA1 1 &pcfg_pull_none>,
+ <1 RK_PA1 1 &pcfg_pull_none_4ma>,
/* vsync */
- <1 RK_PA2 1 &pcfg_pull_none>,
+ <1 RK_PA2 1 &pcfg_pull_none_4ma>,
/* den */
- <1 RK_PA3 1 &pcfg_pull_none>,
+ <1 RK_PA3 1 &pcfg_pull_none_4ma>,
/* d0 */
- <1 RK_PA4 1 &pcfg_pull_none>,
+ <1 RK_PA4 1 &pcfg_pull_none_4ma>,
/* d1 */
- <1 RK_PA5 1 &pcfg_pull_none>,
+ <1 RK_PA5 1 &pcfg_pull_none_4ma>,
/* d2 */
- <1 RK_PA6 1 &pcfg_pull_none>,
+ <1 RK_PA6 1 &pcfg_pull_none_4ma>,
/* d3 */
- <1 RK_PA7 1 &pcfg_pull_none>,
+ <1 RK_PA7 1 &pcfg_pull_none_4ma>,
/* d4 */
- <1 RK_PB0 1 &pcfg_pull_none>,
+ <1 RK_PB0 1 &pcfg_pull_none_4ma>,
/* d5 */
- <1 RK_PB1 1 &pcfg_pull_none>,
+ <1 RK_PB1 1 &pcfg_pull_none_4ma>,
/* d6 */
- <1 RK_PB2 1 &pcfg_pull_none>,
+ <1 RK_PB2 1 &pcfg_pull_none_4ma>,
/* d7 */
- <1 RK_PB3 1 &pcfg_pull_none>,
+ <1 RK_PB3 1 &pcfg_pull_none_4ma>,
/* d8 */
- <1 RK_PB4 1 &pcfg_pull_none>,
+ <1 RK_PB4 1 &pcfg_pull_none_4ma>,
/* d9 */
- <1 RK_PB5 1 &pcfg_pull_none>,
+ <1 RK_PB5 1 &pcfg_pull_none_4ma>,
/* d10 */
- <1 RK_PB6 1 &pcfg_pull_none>,
+ <1 RK_PB6 1 &pcfg_pull_none_4ma>,
/* d11 */
- <1 RK_PB7 1 &pcfg_pull_none>,
+ <1 RK_PB7 1 &pcfg_pull_none_4ma>,
/* d12 */
- <1 RK_PC0 1 &pcfg_pull_none>,
+ <1 RK_PC0 1 &pcfg_pull_none_4ma>,
/* d13 */
- <1 RK_PC1 1 &pcfg_pull_none>,
+ <1 RK_PC1 1 &pcfg_pull_none_4ma>,
/* d14 */
- <1 RK_PC2 1 &pcfg_pull_none>,
+ <1 RK_PC2 1 &pcfg_pull_none_4ma>,
/* d15 */
- <1 RK_PC3 1 &pcfg_pull_none>,
+ <1 RK_PC3 1 &pcfg_pull_none_4ma>,
/* d16 */
- <1 RK_PC4 1 &pcfg_pull_none>,
+ <1 RK_PC4 1 &pcfg_pull_none_4ma>,
/* d17 */
- <1 RK_PC5 1 &pcfg_pull_none>;
+ <1 RK_PC5 1 &pcfg_pull_none_4ma>;
};
lcdc_rgb888_m0: lcdc-rgb888-m0 {
rockchip,pins =
/* d18 */
- <1 RK_PC6 6 &pcfg_pull_none>,
+ <1 RK_PC6 6 &pcfg_pull_none_4ma>,
/* d19 */
- <1 RK_PC7 6 &pcfg_pull_none>,
+ <1 RK_PC7 6 &pcfg_pull_none_4ma>,
/* d20 */
- <2 RK_PB1 3 &pcfg_pull_none>,
+ <2 RK_PB1 3 &pcfg_pull_none_4ma>,
/* d21 */
- <2 RK_PB2 3 &pcfg_pull_none>,
+ <2 RK_PB2 3 &pcfg_pull_none_4ma>,
/* d22 */
- <2 RK_PB7 3 &pcfg_pull_none>,
+ <2 RK_PB7 3 &pcfg_pull_none_4ma>,
/* d23 */
- <2 RK_PC0 3 &pcfg_pull_none>;
+ <2 RK_PC0 3 &pcfg_pull_none_4ma>;
};
lcdc_rgb888_m1: lcdc-rgb888-m1 {
rockchip,pins =
/* d18 */
- <3 RK_PA6 3 &pcfg_pull_none>,
+ <3 RK_PA6 3 &pcfg_pull_none_4ma>,
/* d19 */
- <3 RK_PA7 3 &pcfg_pull_none>,
+ <3 RK_PA7 3 &pcfg_pull_none_4ma>,
/* d20 */
- <3 RK_PB0 3 &pcfg_pull_none>,
+ <3 RK_PB0 3 &pcfg_pull_none_4ma>,
/* d21 */
- <3 RK_PB1 3 &pcfg_pull_none>,
+ <3 RK_PB1 3 &pcfg_pull_none_4ma>,
/* d22 */
- <3 RK_PB2 4 &pcfg_pull_none>,
+ <3 RK_PB2 4 &pcfg_pull_none_4ma>,
/* d23 */
- <3 RK_PB3 4 &pcfg_pull_none>;
+ <3 RK_PB3 4 &pcfg_pull_none_4ma>;
+ };
+ };
+
+ owire-m0 {
+ owirem0_pins: owirem0-pins {
+ rockchip,pins =
+ /* owire_m0 */
+ <0 RK_PB3 3 &pcfg_pull_none>;
+ };
+ };
+
+ owire-m1 {
+ owirem1_pins: owirem1-pins {
+ rockchip,pins =
+ /* owire_m1 */
+ <1 RK_PC6 7 &pcfg_pull_none>;
+ };
+ };
+
+ owire-m2 {
+ owirem2_pins: owirem2-pins {
+ rockchip,pins =
+ /* owire_m2 */
+ <2 RK_PA2 5 &pcfg_pull_none>;
};
};
@@ -1908,6 +2199,253 @@
};
};
+ pwm0 {
+ pwm0_pin: pwm0-pin {
+ rockchip,pins =
+ <0 RK_PB5 1 &pcfg_pull_none>;
+ };
+
+ pwm0_pin_pull_down: pwm0-pin-pull-down {
+ rockchip,pins =
+ <0 RK_PB5 1 &pcfg_pull_down>;
+ };
+ };
+
+ pwm1 {
+ pwm1_pin: pwm1-pin {
+ rockchip,pins =
+ <0 RK_PB6 1 &pcfg_pull_none>;
+ };
+
+ pwm1_pin_pull_down: pwm1-pin-pull-down {
+ rockchip,pins =
+ <0 RK_PB6 1 &pcfg_pull_down>;
+ };
+ };
+
+ pwm2 {
+ pwm2_pin: pwm2-pin {
+ rockchip,pins =
+ <0 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ pwm2_pin_pull_down: pwm2-pin-pull-down {
+ rockchip,pins =
+ <0 RK_PB7 1 &pcfg_pull_down>;
+ };
+ };
+
+ pwm3 {
+ pwm3_pin: pwm3-pin {
+ rockchip,pins =
+ <0 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ pwm3_pin_pull_down: pwm3-pin-pull-down {
+ rockchip,pins =
+ <0 RK_PC0 1 &pcfg_pull_down>;
+ };
+ };
+
+ pwm4 {
+ pwm4_pin: pwm4-pin {
+ rockchip,pins =
+ <0 RK_PA1 2 &pcfg_pull_none>;
+ };
+
+ pwm4_pin_pull_down: pwm4-pin-pull-down {
+ rockchip,pins =
+ <0 RK_PA1 2 &pcfg_pull_down>;
+ };
+ };
+
+ pwm5 {
+ pwm5_pin: pwm5-pin {
+ rockchip,pins =
+ <0 RK_PC1 2 &pcfg_pull_none>;
+ };
+
+ pwm5_pin_pull_down: pwm5-pin-pull-down {
+ rockchip,pins =
+ <0 RK_PC1 2 &pcfg_pull_down>;
+ };
+ };
+
+ pwm6 {
+ pwm6_pin: pwm6-pin {
+ rockchip,pins =
+ <0 RK_PC2 2 &pcfg_pull_none>;
+ };
+
+ pwm6_pin_pull_down: pwm6-pin-pull-down {
+ rockchip,pins =
+ <0 RK_PC2 2 &pcfg_pull_down>;
+ };
+ };
+
+ pwm7 {
+ pwm7_pin: pwm7-pin {
+ rockchip,pins =
+ <2 RK_PB0 2 &pcfg_pull_none>;
+ };
+
+ pwm7_pin_pull_down: pwm7-pin-pull-down {
+ rockchip,pins =
+ <2 RK_PB0 2 &pcfg_pull_down>;
+ };
+ };
+
+ pwm8 {
+ pwm8_pin: pwm8-pin {
+ rockchip,pins =
+ <2 RK_PB2 2 &pcfg_pull_none>;
+ };
+
+ pwm8_pin_pull_down: pwm8-pin-pull-down {
+ rockchip,pins =
+ <2 RK_PB2 2 &pcfg_pull_down>;
+ };
+ };
+
+ pwm9 {
+ pwm9_pin: pwm9-pin {
+ rockchip,pins =
+ <2 RK_PB3 2 &pcfg_pull_none>;
+ };
+
+ pwm9_pin_pull_down: pwm9-pin-pull-down {
+ rockchip,pins =
+ <2 RK_PB3 2 &pcfg_pull_down>;
+ };
+ };
+
+ pwm10 {
+ pwm10_pin: pwm10-pin {
+ rockchip,pins =
+ <2 RK_PB4 2 &pcfg_pull_none>;
+ };
+
+ pwm10_pin_pull_down: pwm10-pin-pull-down {
+ rockchip,pins =
+ <2 RK_PB4 2 &pcfg_pull_down>;
+ };
+ };
+
+ pwm11 {
+ pwm11_pin: pwm11-pin {
+ rockchip,pins =
+ <2 RK_PC0 4 &pcfg_pull_none>;
+ };
+
+ pwm11_pin_pull_down: pwm11-pin-pull-down {
+ rockchip,pins =
+ <2 RK_PC0 4 &pcfg_pull_down>;
+ };
+ };
+
+ rtc {
+ rtc_32k: rtc-32k {
+ rockchip,pins =
+ <0 RK_PC3 1 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc {
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins =
+ <4 RK_PD5 1 &pcfg_pull_none_4ma>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins =
+ <4 RK_PD4 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc_det: sdmmc-det {
+ rockchip,pins =
+ <0 RK_PA3 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc_pwren: sdmmc-pwren {
+ rockchip,pins =
+ <4 RK_PD6 1 &pcfg_pull_none_4ma>;
+ };
+
+ sdmmc_bus1: sdmmc-bus1 {
+ rockchip,pins =
+ <4 RK_PD0 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins =
+ <4 RK_PD0 1 &pcfg_pull_up_4ma>,
+ <4 RK_PD1 1 &pcfg_pull_up_4ma>,
+ <4 RK_PD2 1 &pcfg_pull_up_4ma>,
+ <4 RK_PD3 1 &pcfg_pull_up_4ma>;
+ };
+
+ sdmmc_gpio: sdmmc-gpio {
+ rockchip,pins =
+ <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
+ };
+ };
+
+ sdio {
+ sdio_clk: sdio-clk {
+ rockchip,pins =
+ <4 RK_PA5 1 &pcfg_pull_none_8ma>;
+ };
+
+ sdio_cmd: sdio-cmd {
+ rockchip,pins =
+ <4 RK_PA4 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdio_pwren: sdio-pwren {
+ rockchip,pins =
+ <0 RK_PA2 1 &pcfg_pull_none_8ma>;
+ };
+
+ sdio_wrpt: sdio-wrpt {
+ rockchip,pins =
+ <0 RK_PA1 1 &pcfg_pull_none_8ma>;
+ };
+
+ sdio_intn: sdio-intn {
+ rockchip,pins =
+ <0 RK_PA0 1 &pcfg_pull_none_8ma>;
+ };
+
+ sdio_bus1: sdio-bus1 {
+ rockchip,pins =
+ <4 RK_PA0 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdio_bus4: sdio-bus4 {
+ rockchip,pins =
+ <4 RK_PA0 1 &pcfg_pull_up_8ma>,
+ <4 RK_PA1 1 &pcfg_pull_up_8ma>,
+ <4 RK_PA2 1 &pcfg_pull_up_8ma>,
+ <4 RK_PA3 1 &pcfg_pull_up_8ma>;
+ };
+
+ sdio_gpio: sdio-gpio {
+ rockchip,pins =
+ <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
+ <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
+ };
+ };
+
spdif_in {
spdif_in: spdif-in {
rockchip,pins =
@@ -1919,116 +2457,6 @@
spdif_out: spdif-out {
rockchip,pins =
<0 RK_PC1 1 &pcfg_pull_none>;
- };
- };
-
- tsadc {
- tsadc_otp_gpio: tsadc-otp-gpio {
- rockchip,pins =
- <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- tsadc_otp_out: tsadc-otp-out {
- rockchip,pins =
- <0 RK_PB2 1 &pcfg_pull_none>;
- };
- };
-
- uart0 {
- uart0_xfer: uart0-xfer {
- rockchip,pins =
- <2 RK_PA1 1 &pcfg_pull_up>,
- <2 RK_PA0 1 &pcfg_pull_up>;
- };
-
- uart0_cts: uart0-cts {
- rockchip,pins =
- <2 RK_PA2 1 &pcfg_pull_none>;
- };
-
- uart0_rts: uart0-rts {
- rockchip,pins =
- <2 RK_PA3 1 &pcfg_pull_none>;
- };
-
- uart0_rts_gpio: uart0-rts-gpio {
- rockchip,pins =
- <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
- uart1 {
- uart1_xfer: uart1-xfer {
- rockchip,pins =
- <1 RK_PD1 1 &pcfg_pull_up>,
- <1 RK_PD0 1 &pcfg_pull_up>;
- };
-
- uart1_cts: uart1-cts {
- rockchip,pins =
- <1 RK_PC6 1 &pcfg_pull_none>;
- };
-
- uart1_rts: uart1-rts {
- rockchip,pins =
- <1 RK_PC7 1 &pcfg_pull_none>;
- };
- };
-
- uart2-m0 {
- uart2m0_xfer: uart2m0-xfer {
- rockchip,pins =
- <1 RK_PC7 2 &pcfg_pull_up>,
- <1 RK_PC6 2 &pcfg_pull_up>;
- };
- };
-
- uart2-m1 {
- uart2m1_xfer: uart2m1-xfer {
- rockchip,pins =
- <4 RK_PD3 2 &pcfg_pull_up>,
- <4 RK_PD2 2 &pcfg_pull_up>;
- };
- };
-
- uart3 {
- uart3_xfer: uart3-xfer {
- rockchip,pins =
- <3 RK_PB5 4 &pcfg_pull_up>,
- <3 RK_PB4 4 &pcfg_pull_up>;
- };
- };
-
- uart3-m1 {
- uart3m1_xfer: uart3m1-xfer {
- rockchip,pins =
- <0 RK_PC2 3 &pcfg_pull_up>,
- <0 RK_PC1 3 &pcfg_pull_up>;
- };
- };
-
- uart4 {
-
- uart4_xfer: uart4-xfer {
- rockchip,pins =
- <4 RK_PB1 1 &pcfg_pull_up>,
- <4 RK_PB0 1 &pcfg_pull_up>;
- };
-
- uart4_cts: uart4-cts {
- rockchip,pins =
- <4 RK_PA6 1 &pcfg_pull_none>;
-
- };
-
- uart4_rts: uart4-rts {
- rockchip,pins =
- <4 RK_PA7 1 &pcfg_pull_none>;
- };
-
- uart4_rts_gpio: uart4-rts-gpio {
- rockchip,pins =
- <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -2186,464 +2614,113 @@
};
};
- sdmmc {
- sdmmc_clk: sdmmc-clk {
+ tsadc {
+ tsadc_otp_pin: tsadc-otp-pin {
rockchip,pins =
- <4 RK_PD5 1 &pcfg_pull_none_4ma>;
+ <0 RK_PB2 0 &pcfg_pull_none>;
};
- sdmmc_cmd: sdmmc-cmd {
+ tsadc_otp_out: tsadc-otp-out {
rockchip,pins =
- <4 RK_PD4 1 &pcfg_pull_up_4ma>;
- };
-
- sdmmc_det: sdmmc-det {
- rockchip,pins =
- <0 RK_PA3 1 &pcfg_pull_up_4ma>;
- };
-
- sdmmc_pwren: sdmmc-pwren {
- rockchip,pins =
- <4 RK_PD6 1 &pcfg_pull_none_4ma>;
- };
-
- sdmmc_bus1: sdmmc-bus1 {
- rockchip,pins =
- <4 RK_PD0 1 &pcfg_pull_up_4ma>;
- };
-
- sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins =
- <4 RK_PD0 1 &pcfg_pull_up_4ma>,
- <4 RK_PD1 1 &pcfg_pull_up_4ma>,
- <4 RK_PD2 1 &pcfg_pull_up_4ma>,
- <4 RK_PD3 1 &pcfg_pull_up_4ma>;
- };
-
- sdmmc_gpio: sdmmc-gpio {
- rockchip,pins =
- <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
+ <0 RK_PB2 1 &pcfg_pull_none>;
};
};
- sdio {
- sdio_clk: sdio-clk {
+ uart0 {
+ uart0_xfer: uart0-xfer {
rockchip,pins =
- <4 RK_PA5 1 &pcfg_pull_none_8ma>;
+ <2 RK_PA1 1 &pcfg_pull_up>,
+ <2 RK_PA0 1 &pcfg_pull_up>;
};
- sdio_cmd: sdio-cmd {
+ uart0_cts: uart0-cts {
rockchip,pins =
- <4 RK_PA4 1 &pcfg_pull_up_8ma>;
+ <2 RK_PA2 1 &pcfg_pull_none>;
};
- sdio_pwren: sdio-pwren {
+ uart0_rts: uart0-rts {
rockchip,pins =
- <0 RK_PA2 1 &pcfg_pull_none_8ma>;
+ <2 RK_PA3 1 &pcfg_pull_none>;
};
- sdio_wrpt: sdio-wrpt {
+ uart0_rts_pin: uart0-rts-pin {
rockchip,pins =
- <0 RK_PA1 1 &pcfg_pull_none_8ma>;
- };
-
- sdio_intn: sdio-intn {
- rockchip,pins =
- <0 RK_PA0 1 &pcfg_pull_none_8ma>;
- };
-
- sdio_bus1: sdio-bus1 {
- rockchip,pins =
- <4 RK_PA0 1 &pcfg_pull_up_8ma>;
- };
-
- sdio_bus4: sdio-bus4 {
- rockchip,pins =
- <4 RK_PA0 1 &pcfg_pull_up_8ma>,
- <4 RK_PA1 1 &pcfg_pull_up_8ma>,
- <4 RK_PA2 1 &pcfg_pull_up_8ma>,
- <4 RK_PA3 1 &pcfg_pull_up_8ma>;
- };
-
- sdio_gpio: sdio-gpio {
- rockchip,pins =
- <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
+ <2 RK_PA3 0 &pcfg_pull_none>;
};
};
- emmc {
- emmc_clk: emmc-clk {
+ uart1 {
+ uart1_xfer: uart1-xfer {
rockchip,pins =
- <3 RK_PB1 2 &pcfg_pull_none_8ma>;
+ <1 RK_PD1 1 &pcfg_pull_up>,
+ <1 RK_PD0 1 &pcfg_pull_up>;
};
- emmc_cmd: emmc-cmd {
+ uart1_cts: uart1-cts {
rockchip,pins =
- <3 RK_PB0 2 &pcfg_pull_up_8ma>;
+ <1 RK_PC6 1 &pcfg_pull_none>;
};
- emmc_pwren: emmc-pwren {
+ uart1_rts: uart1-rts {
rockchip,pins =
- <3 RK_PB3 2 &pcfg_pull_none>;
- };
-
- emmc_rstn: emmc-rstn {
- rockchip,pins =
- <3 RK_PB2 2 &pcfg_pull_none>;
- };
-
- emmc_bus1: emmc-bus1 {
- rockchip,pins =
- <3 RK_PA0 2 &pcfg_pull_up_8ma>;
- };
-
- emmc_bus4: emmc-bus4 {
- rockchip,pins =
- <3 RK_PA0 2 &pcfg_pull_up_8ma>,
- <3 RK_PA1 2 &pcfg_pull_up_8ma>,
- <3 RK_PA2 2 &pcfg_pull_up_8ma>,
- <3 RK_PA3 2 &pcfg_pull_up_8ma>;
- };
-
- emmc_bus8: emmc-bus8 {
- rockchip,pins =
- <3 RK_PA0 2 &pcfg_pull_up_8ma>,
- <3 RK_PA1 2 &pcfg_pull_up_8ma>,
- <3 RK_PA2 2 &pcfg_pull_up_8ma>,
- <3 RK_PA3 2 &pcfg_pull_up_8ma>,
- <3 RK_PA4 2 &pcfg_pull_up_8ma>,
- <3 RK_PA5 2 &pcfg_pull_up_8ma>,
- <3 RK_PA6 2 &pcfg_pull_up_8ma>,
- <3 RK_PA7 2 &pcfg_pull_up_8ma>;
+ <1 RK_PC7 1 &pcfg_pull_none>;
};
};
- flash {
- flash_csn0: flash-csn0 {
+ uart2-m0 {
+ uart2m0_xfer: uart2m0-xfer {
rockchip,pins =
- <3 RK_PB5 1 &pcfg_pull_none>;
- };
-
- flash_rdy: flash-rdy {
- rockchip,pins =
- <3 RK_PB4 1 &pcfg_pull_none>;
- };
-
- flash_ale: flash-ale {
- rockchip,pins =
- <3 RK_PB3 1 &pcfg_pull_none>;
- };
-
- flash_cle: flash-cle {
- rockchip,pins =
- <3 RK_PB1 1 &pcfg_pull_none>;
- };
-
- flash_wrn: flash-wrn {
- rockchip,pins =
- <3 RK_PB0 1 &pcfg_pull_none>;
- };
-
- flash_rdn: flash-rdn {
- rockchip,pins =
- <3 RK_PB2 1 &pcfg_pull_none>;
- };
-
- flash_bus8: flash-bus8 {
- rockchip,pins =
- <3 RK_PA0 1 &pcfg_pull_up_12ma>,
- <3 RK_PA1 1 &pcfg_pull_up_12ma>,
- <3 RK_PA2 1 &pcfg_pull_up_12ma>,
- <3 RK_PA3 1 &pcfg_pull_up_12ma>,
- <3 RK_PA4 1 &pcfg_pull_up_12ma>,
- <3 RK_PA5 1 &pcfg_pull_up_12ma>,
- <3 RK_PA6 1 &pcfg_pull_up_12ma>,
- <3 RK_PA7 1 &pcfg_pull_up_12ma>;
+ <1 RK_PC7 2 &pcfg_pull_up>,
+ <1 RK_PC6 2 &pcfg_pull_up>;
};
};
- pwm0 {
- pwm0_pin: pwm0-pin {
+ uart2-m1 {
+ uart2m1_xfer: uart2m1-xfer {
rockchip,pins =
- <0 RK_PB5 1 &pcfg_pull_none>;
- };
-
- pwm0_pin_pull_down: pwm0-pin-pull-down {
- rockchip,pins =
- <0 RK_PB5 1 &pcfg_pull_down>;
+ <4 RK_PD3 2 &pcfg_pull_up>,
+ <4 RK_PD2 2 &pcfg_pull_up>;
};
};
- pwm1 {
- pwm1_pin: pwm1-pin {
+ uart3 {
+ uart3_xfer: uart3-xfer {
rockchip,pins =
- <0 RK_PB6 1 &pcfg_pull_none>;
- };
-
- pwm1_pin_pull_down: pwm1-pin-pull-down {
- rockchip,pins =
- <0 RK_PB6 1 &pcfg_pull_down>;
+ <3 RK_PB5 4 &pcfg_pull_up>,
+ <3 RK_PB4 4 &pcfg_pull_up>;
};
};
- pwm2 {
- pwm2_pin: pwm2-pin {
+ uart3-m1 {
+ uart3m1_xfer: uart3m1-xfer {
rockchip,pins =
- <0 RK_PB7 1 &pcfg_pull_none>;
- };
-
- pwm2_pin_pull_down: pwm2-pin-pull-down {
- rockchip,pins =
- <0 RK_PB7 1 &pcfg_pull_down>;
+ <0 RK_PC2 3 &pcfg_pull_up>,
+ <0 RK_PC1 3 &pcfg_pull_up>;
};
};
- pwm3 {
- pwm3_pin: pwm3-pin {
+ uart4 {
+ uart4_xfer: uart4-xfer {
rockchip,pins =
- <0 RK_PC0 1 &pcfg_pull_none>;
+ <4 RK_PB1 1 &pcfg_pull_up>,
+ <4 RK_PB0 1 &pcfg_pull_up>;
};
- pwm3_pin_pull_down: pwm3-pin-pull-down {
+ uart4_cts: uart4-cts {
rockchip,pins =
- <0 RK_PC0 1 &pcfg_pull_down>;
- };
- };
-
- pwm4 {
- pwm4_pin: pwm4-pin {
- rockchip,pins =
- <0 RK_PA1 2 &pcfg_pull_none>;
+ <4 RK_PA6 1 &pcfg_pull_none>;
};
- pwm4_pin_pull_down: pwm4-pin-pull-down {
+ uart4_rts: uart4-rts {
rockchip,pins =
- <0 RK_PA1 2 &pcfg_pull_down>;
- };
- };
-
- pwm5 {
- pwm5_pin: pwm5-pin {
- rockchip,pins =
- <0 RK_PC1 2 &pcfg_pull_none>;
+ <4 RK_PA7 1 &pcfg_pull_none>;
};
- pwm5_pin_pull_down: pwm5-pin-pull-down {
+ uart4_rts_pin: uart4-rts-pin {
rockchip,pins =
- <0 RK_PC1 2 &pcfg_pull_down>;
- };
- };
-
- pwm6 {
- pwm6_pin: pwm6-pin {
- rockchip,pins =
- <0 RK_PC2 2 &pcfg_pull_none>;
- };
-
- pwm6_pin_pull_down: pwm6-pin-pull-down {
- rockchip,pins =
- <0 RK_PC2 2 &pcfg_pull_down>;
- };
- };
-
- pwm7 {
- pwm7_pin: pwm7-pin {
- rockchip,pins =
- <2 RK_PB0 2 &pcfg_pull_none>;
- };
-
- pwm7_pin_pull_down: pwm7-pin-pull-down {
- rockchip,pins =
- <2 RK_PB0 2 &pcfg_pull_down>;
- };
- };
-
- pwm8 {
- pwm8_pin: pwm8-pin {
- rockchip,pins =
- <2 RK_PB2 2 &pcfg_pull_none>;
- };
-
- pwm8_pin_pull_down: pwm8-pin-pull-down {
- rockchip,pins =
- <2 RK_PB2 2 &pcfg_pull_down>;
- };
- };
-
- pwm9 {
- pwm9_pin: pwm9-pin {
- rockchip,pins =
- <2 RK_PB3 2 &pcfg_pull_none>;
- };
-
- pwm9_pin_pull_down: pwm9-pin-pull-down {
- rockchip,pins =
- <2 RK_PB3 2 &pcfg_pull_down>;
- };
- };
-
- pwm10 {
- pwm10_pin: pwm10-pin {
- rockchip,pins =
- <2 RK_PB4 2 &pcfg_pull_none>;
- };
-
- pwm10_pin_pull_down: pwm10-pin-pull-down {
- rockchip,pins =
- <2 RK_PB4 2 &pcfg_pull_down>;
- };
- };
-
- pwm11 {
- pwm11_pin: pwm11-pin {
- rockchip,pins =
- <2 RK_PC0 4 &pcfg_pull_none>;
- };
-
- pwm11_pin_pull_down: pwm11-pin-pull-down {
- rockchip,pins =
- <2 RK_PC0 4 &pcfg_pull_down>;
- };
- };
-
- gmac {
- rmii_pins: rmii-pins {
- rockchip,pins =
- /* mac_txen */
- <1 RK_PC1 3 &pcfg_pull_none_12ma>,
- /* mac_txd1 */
- <1 RK_PC3 3 &pcfg_pull_none_12ma>,
- /* mac_txd0 */
- <1 RK_PC2 3 &pcfg_pull_none_12ma>,
- /* mac_rxd0 */
- <1 RK_PC4 3 &pcfg_pull_none>,
- /* mac_rxd1 */
- <1 RK_PC5 3 &pcfg_pull_none>,
- /* mac_rxer */
- <1 RK_PB7 3 &pcfg_pull_none>,
- /* mac_rxdv */
- <1 RK_PC0 3 &pcfg_pull_none>,
- /* mac_mdio */
- <1 RK_PB6 3 &pcfg_pull_none>,
- /* mac_mdc */
- <1 RK_PB5 3 &pcfg_pull_none>;
- };
-
- mac_refclk_12ma: mac-refclk-12ma {
- rockchip,pins =
- <1 RK_PB4 3 &pcfg_pull_none_12ma>;
- };
-
- mac_refclk: mac-refclk {
- rockchip,pins =
- <1 RK_PB4 3 &pcfg_pull_none>;
- };
- };
-
- gmac-m1 {
- rmiim1_pins: rmiim1-pins {
- rockchip,pins =
- /* mac_txen */
- <4 RK_PB7 2 &pcfg_pull_none_12ma>,
- /* mac_txd1 */
- <4 RK_PA5 2 &pcfg_pull_none_12ma>,
- /* mac_txd0 */
- <4 RK_PA4 2 &pcfg_pull_none_12ma>,
- /* mac_rxd0 */
- <4 RK_PA2 2 &pcfg_pull_none>,
- /* mac_rxd1 */
- <4 RK_PA3 2 &pcfg_pull_none>,
- /* mac_rxer */
- <4 RK_PA0 2 &pcfg_pull_none>,
- /* mac_rxdv */
- <4 RK_PA1 2 &pcfg_pull_none>,
- /* mac_mdio */
- <4 RK_PB6 2 &pcfg_pull_none>,
- /* mac_mdc */
- <4 RK_PB5 2 &pcfg_pull_none>;
- };
-
- macm1_refclk_12ma: macm1-refclk-12ma {
- rockchip,pins =
- <4 RK_PB4 2 &pcfg_pull_none_12ma>;
- };
-
- macm1_refclk: macm1-refclk {
- rockchip,pins =
- <4 RK_PB4 2 &pcfg_pull_none>;
- };
- };
-
- rtc {
- rtc_32k: rtc-32k {
- rockchip,pins =
- <0 RK_PC3 1 &pcfg_pull_none>;
- };
- };
-
- can-m0 {
- canm0_pins: canm0-pins {
- rockchip,pins =
- /* can_rxd_m0 */
- <0 RK_PB3 2 &pcfg_pull_none>,
- /* can_txd_m0 */
- <0 RK_PB4 2 &pcfg_pull_none>;
- };
- };
-
- can-m1 {
- canm1_pins: canm1-pins {
- rockchip,pins =
- /* can_rxd_m1 */
- <1 RK_PC6 5 &pcfg_pull_none>,
- /* can_txd_m1 */
- <1 RK_PC7 5 &pcfg_pull_none>;
- };
- };
-
- can-m2 {
- canm2_pins: canm2-pins {
- rockchip,pins =
- /* can_rxd_m2 */
- <2 RK_PA2 4 &pcfg_pull_none>,
- /* can_txd_m2 */
- <2 RK_PA3 4 &pcfg_pull_none>;
- };
- };
-
- owire-m0 {
- owirem0_pins: owirem0-pins {
- rockchip,pins =
- /* owire_m0 */
- <0 RK_PB3 3 &pcfg_pull_none>;
- };
- };
-
- owire-m1 {
- owirem1_pins: owirem1-pins {
- rockchip,pins =
- /* owire_m1 */
- <1 RK_PC6 7 &pcfg_pull_none>;
- };
- };
-
- owire-m2 {
- owirem2_pins: owirem2-pins {
- rockchip,pins =
- /* owire_m2 */
- <2 RK_PA2 5 &pcfg_pull_none>;
+ <4 RK_PA7 0 &pcfg_pull_none>;
};
};
};
};
+#include "rk3308bs-pinctrl.dtsi"
--
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