From 297b60346df8beafee954a0fd7c2d64f33f3b9bc Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Sat, 11 May 2024 01:44:05 +0000
Subject: [PATCH] rtl8211F_led_control
---
rkbin/doc/release/RK3308_EN.md | 28 +++++++++++++++++++++++++++-
1 files changed, 27 insertions(+), 1 deletions(-)
diff --git a/rkbin/doc/release/RK3308_EN.md b/rkbin/doc/release/RK3308_EN.md
index 3fb6383..3df7a9c 100644
--- a/rkbin/doc/release/RK3308_EN.md
+++ b/rkbin/doc/release/RK3308_EN.md
@@ -1,5 +1,31 @@
# RK3308 Release Note
+## rk3308_bl31_cpu3_v1.00.elf
+
+| Date | File | Build commit | Severity |
+| ---------- | :------------------------- | ------------ | -------- |
+| 2023-03-16 | rk3308_bl31_cpu3_v1.00.elf | 5fb7b7229 | moderate |
+
+### New
+
+1. Support boot from CPU3.
+
+------
+
+## rk3308_ddr_{589 ... 393}MHz_{uart2_m1, uart4_m0}_v2.07.bin
+
+| Date | File | Build commit | Severity |
+| ---------- | :--------------------------------------------------------- | ------------ | -------- |
+| 2022-11-29 | rk3308_ddr_{589 ... 393}MHz_{uart2_m1, uart4_m0}_v2.07.bin | 6ede97a868 | moderate |
+
+### Fixed
+
+| Index | Severity | Update | Issue description | Issue source |
+| ----- | -------- | -------------------------------------------------------- | ------------------------------------------------------------ | ------------ |
+| 1 | moderate | Improve the stability of some DDR in RK3308B/H at 393MHz | When RK3308B/H is less than 451MHz, the value of read DQS DLL delay is inaccurately configured. As a result, some DDR may be unstable at 393MHz. | - |
+
+------
+
## rk3308_bl31_{aarch32}_v2.26.elf
| Date | File | Build commit | Severity |
@@ -36,4 +62,4 @@
### New
-1. Check ftl super block 2nd page spare data
\ No newline at end of file
+1. Check ftl super block 2nd page spare data.
--
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