From 244b2c5ca8b14627e4a17755e5922221e121c771 Mon Sep 17 00:00:00 2001 From: hc <hc@nodka.com> Date: Wed, 09 Oct 2024 06:15:07 +0000 Subject: [PATCH] change system file --- kernel/Documentation/devicetree/bindings/display/msm/dsi.txt | 9 +++++++-- 1 files changed, 7 insertions(+), 2 deletions(-) diff --git a/kernel/Documentation/devicetree/bindings/display/msm/dsi.txt b/kernel/Documentation/devicetree/bindings/display/msm/dsi.txt index dfc7432..b9a64d3 100644 --- a/kernel/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/kernel/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -87,7 +87,11 @@ * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" * "qcom,dsi-phy-14nm" + * "qcom,dsi-phy-14nm-660" * "qcom,dsi-phy-10nm" + * "qcom,dsi-phy-10nm-8998" + * "qcom,dsi-phy-7nm" + * "qcom,dsi-phy-7nm-8150" - reg: Physical base address and length of the registers of PLL, PHY. Some revisions require the PHY regulator base address, whereas others require the PHY lane base address. See below for each PHY revision. @@ -96,7 +100,7 @@ * "dsi_pll" * "dsi_phy" * "dsi_phy_regulator" - For DSI 14nm and 10nm PHYs: + For DSI 14nm, 10nm and 7nm PHYs: * "dsi_pll" * "dsi_phy" * "dsi_phy_lane" @@ -106,6 +110,7 @@ - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: * "iface" + * "ref" (only required for new DTS files/entries) For 28nm HPM/LP, 28nm 8960 PHYs: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: @@ -113,7 +118,7 @@ - vcca-supply: phandle to vcca regulator device node For 14nm PHY: - vcca-supply: phandle to vcca regulator device node - For 10nm PHY: + For 10nm and 7nm PHY: - vdds-supply: phandle to vdds regulator device node Optional properties: -- Gitblit v1.6.2