From 23fa18eaa71266feff7ba8d83022d9e1cc83c65a Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Fri, 10 May 2024 07:42:03 +0000
Subject: [PATCH] disable pwm7
---
kernel/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json | 74 ++++++++++++++++++------------------
1 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/kernel/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/kernel/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
index 752e47e..3a87d35 100644
--- a/kernel/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
+++ b/kernel/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
@@ -1,113 +1,113 @@
[
{
- "ArchStdEvent": "L1D_CACHE_RD",
+ "ArchStdEvent": "L1D_CACHE_RD"
},
{
- "ArchStdEvent": "L1D_CACHE_WR",
+ "ArchStdEvent": "L1D_CACHE_WR"
},
{
- "ArchStdEvent": "L1D_CACHE_REFILL_RD",
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD"
},
{
- "ArchStdEvent": "L1D_CACHE_REFILL_WR",
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR"
},
{
- "ArchStdEvent": "L1D_CACHE_REFILL_INNER",
+ "ArchStdEvent": "L1D_CACHE_REFILL_INNER"
},
{
- "ArchStdEvent": "L1D_CACHE_REFILL_OUTER",
+ "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
},
{
- "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
+ "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
},
{
- "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
+ "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
},
{
- "ArchStdEvent": "L1D_CACHE_INVAL",
+ "ArchStdEvent": "L1D_CACHE_INVAL"
},
{
- "ArchStdEvent": "L1D_TLB_REFILL_RD",
+ "ArchStdEvent": "L1D_TLB_REFILL_RD"
},
{
- "ArchStdEvent": "L1D_TLB_REFILL_WR",
+ "ArchStdEvent": "L1D_TLB_REFILL_WR"
},
{
- "ArchStdEvent": "L1D_TLB_RD",
+ "ArchStdEvent": "L1D_TLB_RD"
},
{
- "ArchStdEvent": "L1D_TLB_WR",
+ "ArchStdEvent": "L1D_TLB_WR"
},
{
- "ArchStdEvent": "L2D_TLB_REFILL_RD",
+ "ArchStdEvent": "L2D_TLB_REFILL_RD"
},
{
- "ArchStdEvent": "L2D_TLB_REFILL_WR",
+ "ArchStdEvent": "L2D_TLB_REFILL_WR"
},
{
- "ArchStdEvent": "L2D_TLB_RD",
+ "ArchStdEvent": "L2D_TLB_RD"
},
{
- "ArchStdEvent": "L2D_TLB_WR",
+ "ArchStdEvent": "L2D_TLB_WR"
},
{
- "ArchStdEvent": "BUS_ACCESS_RD",
+ "ArchStdEvent": "BUS_ACCESS_RD"
},
{
- "ArchStdEvent": "BUS_ACCESS_WR",
+ "ArchStdEvent": "BUS_ACCESS_WR"
},
{
- "ArchStdEvent": "MEM_ACCESS_RD",
+ "ArchStdEvent": "MEM_ACCESS_RD"
},
{
- "ArchStdEvent": "MEM_ACCESS_WR",
+ "ArchStdEvent": "MEM_ACCESS_WR"
},
{
- "ArchStdEvent": "UNALIGNED_LD_SPEC",
+ "ArchStdEvent": "UNALIGNED_LD_SPEC"
},
{
- "ArchStdEvent": "UNALIGNED_ST_SPEC",
+ "ArchStdEvent": "UNALIGNED_ST_SPEC"
},
{
- "ArchStdEvent": "UNALIGNED_LDST_SPEC",
+ "ArchStdEvent": "UNALIGNED_LDST_SPEC"
},
{
- "ArchStdEvent": "EXC_UNDEF",
+ "ArchStdEvent": "EXC_UNDEF"
},
{
- "ArchStdEvent": "EXC_SVC",
+ "ArchStdEvent": "EXC_SVC"
},
{
- "ArchStdEvent": "EXC_PABORT",
+ "ArchStdEvent": "EXC_PABORT"
},
{
- "ArchStdEvent": "EXC_DABORT",
+ "ArchStdEvent": "EXC_DABORT"
},
{
- "ArchStdEvent": "EXC_IRQ",
+ "ArchStdEvent": "EXC_IRQ"
},
{
- "ArchStdEvent": "EXC_FIQ",
+ "ArchStdEvent": "EXC_FIQ"
},
{
- "ArchStdEvent": "EXC_SMC",
+ "ArchStdEvent": "EXC_SMC"
},
{
- "ArchStdEvent": "EXC_HVC",
+ "ArchStdEvent": "EXC_HVC"
},
{
- "ArchStdEvent": "EXC_TRAP_PABORT",
+ "ArchStdEvent": "EXC_TRAP_PABORT"
},
{
- "ArchStdEvent": "EXC_TRAP_DABORT",
+ "ArchStdEvent": "EXC_TRAP_DABORT"
},
{
- "ArchStdEvent": "EXC_TRAP_OTHER",
+ "ArchStdEvent": "EXC_TRAP_OTHER"
},
{
- "ArchStdEvent": "EXC_TRAP_IRQ",
+ "ArchStdEvent": "EXC_TRAP_IRQ"
},
{
- "ArchStdEvent": "EXC_TRAP_FIQ",
+ "ArchStdEvent": "EXC_TRAP_FIQ"
}
]
--
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