From 23fa18eaa71266feff7ba8d83022d9e1cc83c65a Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Fri, 10 May 2024 07:42:03 +0000
Subject: [PATCH] disable pwm7
---
kernel/arch/arm64/boot/dts/nvidia/tegra210.dtsi | 591 ++++++++++++++++++++++++++++++++++++++++++++++++++++------
1 files changed, 529 insertions(+), 62 deletions(-)
diff --git a/kernel/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/kernel/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 4eecf3b..7fd47d8 100644
--- a/kernel/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/kernel/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -3,8 +3,11 @@
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/memory/tegra210-mc.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
+#include <dt-bindings/reset/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/tegra124-soctherm.h>
+#include <dt-bindings/soc/tegra-pmc.h>
/ {
compatible = "nvidia,tegra210";
@@ -15,9 +18,9 @@
pcie@1003000 {
compatible = "nvidia,tegra210-pcie";
device_type = "pci";
- reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
- 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
- 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
+ reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
+ <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
+ <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
reg-names = "pads", "afi", "cs";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
@@ -31,11 +34,11 @@
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
- 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
- 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
- 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
- 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
+ ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
+ <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
+ <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
+ <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
+ <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
clocks = <&tegra_car TEGRA210_CLK_PCIE>,
<&tegra_car TEGRA210_CLK_AFI>,
@@ -46,6 +49,11 @@
<&tegra_car 72>,
<&tegra_car 74>;
reset-names = "pex", "afi", "pcie_x";
+
+ pinctrl-names = "default", "idle";
+ pinctrl-0 = <&pex_dpd_disable>;
+ pinctrl-1 = <&pex_dpd_enable>;
+
status = "disabled";
pci@1,0 {
@@ -78,10 +86,11 @@
};
host1x@50000000 {
- compatible = "nvidia,tegra210-host1x", "simple-bus";
+ compatible = "nvidia,tegra210-host1x";
reg = <0x0 0x50000000 0x0 0x00034000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+ interrupt-names = "syncpt", "host1x";
clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
clock-names = "host1x";
resets = <&tegra_car 28>;
@@ -129,9 +138,44 @@
vi@54080000 {
compatible = "nvidia,tegra210-vi";
- reg = <0x0 0x54080000 0x0 0x00040000>;
+ reg = <0x0 0x54080000 0x0 0x700>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
+ assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+
+ clocks = <&tegra_car TEGRA210_CLK_VI>;
+ power-domains = <&pd_venc>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0x0 0x0 0x54080000 0x2000>;
+
+ csi@838 {
+ compatible = "nvidia,tegra210-csi";
+ reg = <0x838 0x1300>;
+ status = "disabled";
+ assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
+ <&tegra_car TEGRA210_CLK_CILCD>,
+ <&tegra_car TEGRA210_CLK_CILE>,
+ <&tegra_car TEGRA210_CLK_CSI_TPG>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
+ <&tegra_car TEGRA210_CLK_PLL_P>,
+ <&tegra_car TEGRA210_CLK_PLL_P>;
+ assigned-clock-rates = <102000000>,
+ <102000000>,
+ <102000000>,
+ <972000000>;
+
+ clocks = <&tegra_car TEGRA210_CLK_CSI>,
+ <&tegra_car TEGRA210_CLK_CILAB>,
+ <&tegra_car TEGRA210_CLK_CILCD>,
+ <&tegra_car TEGRA210_CLK_CILE>,
+ <&tegra_car TEGRA210_CLK_CSI_TPG>;
+ clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
+ power-domains = <&pd_sor>;
+ };
};
tsec@54100000 {
@@ -143,14 +187,14 @@
compatible = "nvidia,tegra210-dc";
reg = <0x0 0x54200000 0x0 0x00040000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_DISP1>,
- <&tegra_car TEGRA210_CLK_PLL_P>;
- clock-names = "dc", "parent";
+ clocks = <&tegra_car TEGRA210_CLK_DISP1>;
+ clock-names = "dc";
resets = <&tegra_car 27>;
reset-names = "dc";
iommus = <&mc TEGRA_SWGROUP_DC>;
+ nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
nvidia,head = <0>;
};
@@ -158,18 +202,18 @@
compatible = "nvidia,tegra210-dc";
reg = <0x0 0x54240000 0x0 0x00040000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_DISP2>,
- <&tegra_car TEGRA210_CLK_PLL_P>;
- clock-names = "dc", "parent";
+ clocks = <&tegra_car TEGRA210_CLK_DISP2>;
+ clock-names = "dc";
resets = <&tegra_car 26>;
reset-names = "dc";
iommus = <&mc TEGRA_SWGROUP_DCB>;
+ nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
nvidia,head = <1>;
};
- dsi@54300000 {
+ dsia: dsi@54300000 {
compatible = "nvidia,tegra210-dsi";
reg = <0x0 0x54300000 0x0 0x00040000>;
clocks = <&tegra_car TEGRA210_CLK_DSIA>,
@@ -206,7 +250,7 @@
status = "disabled";
};
- dsi@54400000 {
+ dsib: dsi@54400000 {
compatible = "nvidia,tegra210-dsi";
reg = <0x0 0x54400000 0x0 0x00040000>;
clocks = <&tegra_car TEGRA210_CLK_DSIB>,
@@ -242,15 +286,16 @@
status = "disabled";
};
- sor@54540000 {
+ sor0: sor@54540000 {
compatible = "nvidia,tegra210-sor";
reg = <0x0 0x54540000 0x0 0x00040000>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_SOR0>,
+ <&tegra_car TEGRA210_CLK_SOR0_OUT>,
<&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
<&tegra_car TEGRA210_CLK_PLL_DP>,
<&tegra_car TEGRA210_CLK_SOR_SAFE>;
- clock-names = "sor", "parent", "dp", "safe";
+ clock-names = "sor", "out", "parent", "dp", "safe";
resets = <&tegra_car 182>;
reset-names = "sor";
pinctrl-0 = <&state_dpaux_aux>;
@@ -261,7 +306,7 @@
status = "disabled";
};
- sor@54580000 {
+ sor1: sor@54580000 {
compatible = "nvidia,tegra210-sor1";
reg = <0x0 0x54580000 0x0 0x00040000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -282,7 +327,7 @@
};
dpaux: dpaux@545c0000 {
- compatible = "nvidia,tegra124-dpaux";
+ compatible = "nvidia,tegra210-dpaux";
reg = <0x0 0x545c0000 0x0 0x00040000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
@@ -318,6 +363,9 @@
compatible = "nvidia,tegra210-isp";
reg = <0x0 0x54600000 0x0 0x00040000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_ISPA>;
+ resets = <&tegra_car 23>;
+ reset-names = "isp";
status = "disabled";
};
@@ -325,6 +373,9 @@
compatible = "nvidia,tegra210-isp";
reg = <0x0 0x54680000 0x0 0x00040000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_ISPB>;
+ resets = <&tegra_car 3>;
+ reset-names = "isp";
status = "disabled";
};
@@ -332,7 +383,16 @@
compatible = "nvidia,tegra210-i2c-vi";
reg = <0x0 0x546c0000 0x0 0x00040000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_VI_I2C>,
+ <&tegra_car TEGRA210_CLK_I2CSLOW>;
+ clock-names = "div-clk", "slow";
+ resets = <&tegra_car 208>;
+ reset-names = "i2c";
+ power-domains = <&pd_venc>;
status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
@@ -382,14 +442,22 @@
};
timer@60005000 {
- compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
+ compatible = "nvidia,tegra210-timer";
reg = <0x0 0x60005000 0x0 0x400>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_TIMER>;
clock-names = "timer";
};
@@ -468,13 +536,55 @@
apbmisc@70000800 {
compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
- <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
+ <0x0 0x70000008 0x0 0x04>; /* Strapping options */
};
pinmux: pinmux@700008d4 {
compatible = "nvidia,tegra210-pinmux";
reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
<0x0 0x70003000 0x0 0x294>; /* Mux registers */
+ sdmmc1_3v3_drv: sdmmc1-3v3-drv {
+ sdmmc1 {
+ nvidia,pins = "drive_sdmmc1";
+ nvidia,pull-down-strength = <0x8>;
+ nvidia,pull-up-strength = <0x8>;
+ };
+ };
+ sdmmc1_1v8_drv: sdmmc1-1v8-drv {
+ sdmmc1 {
+ nvidia,pins = "drive_sdmmc1";
+ nvidia,pull-down-strength = <0x4>;
+ nvidia,pull-up-strength = <0x3>;
+ };
+ };
+ sdmmc2_1v8_drv: sdmmc2-1v8-drv {
+ sdmmc2 {
+ nvidia,pins = "drive_sdmmc2";
+ nvidia,pull-down-strength = <0x10>;
+ nvidia,pull-up-strength = <0x10>;
+ };
+ };
+ sdmmc3_3v3_drv: sdmmc3-3v3-drv {
+ sdmmc3 {
+ nvidia,pins = "drive_sdmmc3";
+ nvidia,pull-down-strength = <0x8>;
+ nvidia,pull-up-strength = <0x8>;
+ };
+ };
+ sdmmc3_1v8_drv: sdmmc3-1v8-drv {
+ sdmmc3 {
+ nvidia,pins = "drive_sdmmc3";
+ nvidia,pull-down-strength = <0x4>;
+ nvidia,pull-up-strength = <0x3>;
+ };
+ };
+ sdmmc4_1v8_drv: sdmmc4-1v8-drv {
+ sdmmc4 {
+ nvidia,pins = "drive_sdmmc4";
+ nvidia,pull-down-strength = <0x10>;
+ nvidia,pull-up-strength = <0x10>;
+ };
+ };
};
/*
@@ -553,7 +663,7 @@
};
i2c@7000c000 {
- compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+ compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
reg = <0x0 0x7000c000 0x0 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -568,7 +678,7 @@
};
i2c@7000c400 {
- compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+ compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
reg = <0x0 0x7000c400 0x0 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -583,7 +693,7 @@
};
i2c@7000c500 {
- compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+ compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
reg = <0x0 0x7000c500 0x0 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -598,7 +708,7 @@
};
i2c@7000c700 {
- compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+ compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
reg = <0x0 0x7000c700 0x0 0x100>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -616,7 +726,7 @@
};
i2c@7000d000 {
- compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+ compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
reg = <0x0 0x7000d000 0x0 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -631,7 +741,7 @@
};
i2c@7000d100 {
- compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
+ compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
reg = <0x0 0x7000d100 0x0 0x100>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
@@ -711,16 +821,20 @@
rtc@7000e000 {
compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
reg = <0x0 0x7000e000 0x0 0x100>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&tegra_pmc>;
clocks = <&tegra_car TEGRA210_CLK_RTC>;
clock-names = "rtc";
};
- pmc: pmc@7000e400 {
+ tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra210-pmc";
reg = <0x0 0x7000e400 0x0 0x400>;
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
+ #clock-cells = <1>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
powergates {
pd_audio: aud {
@@ -733,7 +847,9 @@
pd_sor: sor {
clocks = <&tegra_car TEGRA210_CLK_SOR0>,
<&tegra_car TEGRA210_CLK_SOR1>,
- <&tegra_car TEGRA210_CLK_CSI>,
+ <&tegra_car TEGRA210_CLK_CILAB>,
+ <&tegra_car TEGRA210_CLK_CILCD>,
+ <&tegra_car TEGRA210_CLK_CILE>,
<&tegra_car TEGRA210_CLK_DSIA>,
<&tegra_car TEGRA210_CLK_DSIB>,
<&tegra_car TEGRA210_CLK_DPAUX>,
@@ -741,7 +857,6 @@
<&tegra_car TEGRA210_CLK_MIPI_CAL>;
resets = <&tegra_car TEGRA210_CLK_SOR0>,
<&tegra_car TEGRA210_CLK_SOR1>,
- <&tegra_car TEGRA210_CLK_CSI>,
<&tegra_car TEGRA210_CLK_DSIA>,
<&tegra_car TEGRA210_CLK_DSIB>,
<&tegra_car TEGRA210_CLK_DPAUX>,
@@ -775,6 +890,49 @@
reset-names = "vic";
#power-domain-cells = <0>;
};
+
+ pd_venc: venc {
+ clocks = <&tegra_car TEGRA210_CLK_VI>,
+ <&tegra_car TEGRA210_CLK_CSI>;
+ resets = <&mc TEGRA210_MC_RESET_VI>,
+ <&tegra_car 20>,
+ <&tegra_car 52>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ sdmmc1_3v3: sdmmc1-3v3 {
+ pins = "sdmmc1";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+ };
+
+ sdmmc1_1v8: sdmmc1-1v8 {
+ pins = "sdmmc1";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+ };
+
+ sdmmc3_3v3: sdmmc3-3v3 {
+ pins = "sdmmc3";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
+ };
+
+ sdmmc3_1v8: sdmmc3-1v8 {
+ pins = "sdmmc3";
+ power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
+ };
+
+ pex_dpd_disable: pex_en {
+ pex-dpd-disable {
+ pins = "pex-bias", "pex-clk1", "pex-clk2";
+ low-power-disable;
+ };
+ };
+
+ pex_dpd_enable: pex_dis {
+ pex-dpd-enable {
+ pins = "pex-bias", "pex-clk1", "pex-clk2";
+ low-power-enable;
+ };
};
};
@@ -796,6 +954,19 @@
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ emc: external-memory-controller@7001b000 {
+ compatible = "nvidia,tegra210-emc";
+ reg = <0x0 0x7001b000 0x0 0x1000>,
+ <0x0 0x7001e000 0x0 0x1000>,
+ <0x0 0x7001f000 0x0 0x1000>;
+ clocks = <&tegra_car TEGRA210_CLK_EMC>;
+ clock-names = "emc";
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ nvidia,memory-controller = <&mc>;
+ #cooling-cells = <2>;
};
sata@70020000 {
@@ -844,8 +1015,8 @@
<&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_SS>,
- <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
<&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
+ <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
<&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
<&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
<&tegra_car TEGRA210_CLK_PLL_U_480M>,
@@ -853,12 +1024,14 @@
<&tegra_car TEGRA210_CLK_PLL_E>;
clock-names = "xusb_host", "xusb_host_src",
"xusb_falcon_src", "xusb_ss",
- "xusb_ss_div2", "xusb_ss_src",
+ "xusb_ss_src", "xusb_ss_div2",
"xusb_hs_src", "xusb_fs_src",
"pll_u_480m", "clk_m", "pll_e";
resets = <&tegra_car 89>, <&tegra_car 156>,
<&tegra_car 143>;
reset-names = "xusb_host", "xusb_ss", "xusb_src";
+ power-domains = <&pd_xusbhost>, <&pd_xusbss>;
+ power-domain-names = "xusb_host", "xusb_ss";
nvidia,xusb-padctl = <&padctl>;
@@ -1020,47 +1193,117 @@
};
};
- sdhci@700b0000 {
- compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
+ mmc@700b0000 {
+ compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
- clock-names = "sdhci";
+ clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
+ <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+ clock-names = "sdhci", "tmclk";
resets = <&tegra_car 14>;
reset-names = "sdhci";
+ pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
+ "sdmmc-3v3-drv", "sdmmc-1v8-drv";
+ pinctrl-0 = <&sdmmc1_3v3>;
+ pinctrl-1 = <&sdmmc1_1v8>;
+ pinctrl-2 = <&sdmmc1_3v3_drv>;
+ pinctrl-3 = <&sdmmc1_1v8_drv>;
+ nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
+ nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
+ nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
+ nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
+ nvidia,default-tap = <0x2>;
+ nvidia,default-trim = <0x4>;
+ assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
+ <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
+ <&tegra_car TEGRA210_CLK_PLL_C4>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+ assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
status = "disabled";
};
- sdhci@700b0200 {
- compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
+ mmc@700b0200 {
+ compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0200 0x0 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
- clock-names = "sdhci";
+ clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
+ <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+ clock-names = "sdhci", "tmclk";
resets = <&tegra_car 9>;
reset-names = "sdhci";
+ pinctrl-names = "sdmmc-1v8-drv";
+ pinctrl-0 = <&sdmmc2_1v8_drv>;
+ nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
+ nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
+ nvidia,default-tap = <0x8>;
+ nvidia,default-trim = <0x0>;
status = "disabled";
};
- sdhci@700b0400 {
- compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
+ mmc@700b0400 {
+ compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0400 0x0 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
- clock-names = "sdhci";
+ clocks = <&tegra_car TEGRA210_CLK_SDMMC3>,
+ <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+ clock-names = "sdhci", "tmclk";
resets = <&tegra_car 69>;
reset-names = "sdhci";
+ pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
+ "sdmmc-3v3-drv", "sdmmc-1v8-drv";
+ pinctrl-0 = <&sdmmc3_3v3>;
+ pinctrl-1 = <&sdmmc3_1v8>;
+ pinctrl-2 = <&sdmmc3_3v3_drv>;
+ pinctrl-3 = <&sdmmc3_1v8_drv>;
+ nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
+ nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
+ nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
+ nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
+ nvidia,default-tap = <0x3>;
+ nvidia,default-trim = <0x3>;
status = "disabled";
};
- sdhci@700b0600 {
- compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
+ mmc@700b0600 {
+ compatible = "nvidia,tegra210-sdhci";
reg = <0x0 0x700b0600 0x0 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
- clock-names = "sdhci";
+ clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
+ <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+ clock-names = "sdhci", "tmclk";
resets = <&tegra_car 15>;
reset-names = "sdhci";
+ pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
+ pinctrl-0 = <&sdmmc4_1v8_drv>;
+ pinctrl-1 = <&sdmmc4_1v8_drv>;
+ nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
+ nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
+ nvidia,default-tap = <0x8>;
+ nvidia,default-trim = <0x0>;
+ assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
+ <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
+ nvidia,dqs-trim = <40>;
+ mmc-hs400-1_8v;
+ status = "disabled";
+ };
+
+ usb@700d0000 {
+ compatible = "nvidia,tegra210-xudc";
+ reg = <0x0 0x700d0000 0x0 0x8000>,
+ <0x0 0x700d8000 0x0 0x1000>,
+ <0x0 0x700d9000 0x0 0x1000>;
+ reg-names = "base", "fpci", "ipfs";
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>,
+ <&tegra_car TEGRA210_CLK_XUSB_SS>,
+ <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>,
+ <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
+ <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>;
+ clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src";
+ power-domains = <&pd_xusbdev>, <&pd_xusbss>;
+ power-domain-names = "dev", "ss";
+ nvidia,xusb-padctl = <&padctl>;
status = "disabled";
};
@@ -1071,6 +1314,24 @@
clock-names = "mipi-cal";
power-domains = <&pd_sor>;
#nvidia,mipi-calibrate-cells = <1>;
+ };
+
+ dfll: clock@70110000 {
+ compatible = "nvidia,tegra210-dfll";
+ reg = <0 0x70110000 0 0x100>, /* DFLL control */
+ <0 0x70110000 0 0x100>, /* I2C output control */
+ <0 0x70110100 0 0x100>, /* Integrated I2C controller */
+ <0 0x70110200 0 0x100>; /* Look-up table RAM */
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
+ <&tegra_car TEGRA210_CLK_DFLL_REF>,
+ <&tegra_car TEGRA210_CLK_I2C5>;
+ clock-names = "soc", "ref", "i2c";
+ resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
+ reset-names = "dvco";
+ #clock-cells = <0>;
+ clock-output-names = "dfllCPU_out";
+ status = "disabled";
};
aconnect@702c0000 {
@@ -1116,7 +1377,7 @@
status = "disabled";
};
- agic: agic@702f9000 {
+ agic: interrupt-controller@702f9000 {
compatible = "nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
@@ -1126,6 +1387,146 @@
clocks = <&tegra_car TEGRA210_CLK_APE>;
clock-names = "clk";
status = "disabled";
+ };
+
+ tegra_ahub: ahub@702d0800 {
+ compatible = "nvidia,tegra210-ahub";
+ reg = <0x702d0800 0x800>;
+ clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
+ clock-names = "ahub";
+ assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x702d0000 0x702d0000 0x0000e400>;
+ status = "disabled";
+
+ tegra_admaif: admaif@702d0000 {
+ compatible = "nvidia,tegra210-admaif";
+ reg = <0x702d0000 0x800>;
+ dmas = <&adma 1>, <&adma 1>,
+ <&adma 2>, <&adma 2>,
+ <&adma 3>, <&adma 3>,
+ <&adma 4>, <&adma 4>,
+ <&adma 5>, <&adma 5>,
+ <&adma 6>, <&adma 6>,
+ <&adma 7>, <&adma 7>,
+ <&adma 8>, <&adma 8>,
+ <&adma 9>, <&adma 9>,
+ <&adma 10>, <&adma 10>;
+ dma-names = "rx1", "tx1",
+ "rx2", "tx2",
+ "rx3", "tx3",
+ "rx4", "tx4",
+ "rx5", "tx5",
+ "rx6", "tx6",
+ "rx7", "tx7",
+ "rx8", "tx8",
+ "rx9", "tx9",
+ "rx10", "tx10";
+ status = "disabled";
+ };
+
+ tegra_i2s1: i2s@702d1000 {
+ compatible = "nvidia,tegra210-i2s";
+ reg = <0x702d1000 0x100>;
+ clocks = <&tegra_car TEGRA210_CLK_I2S0>,
+ <&tegra_car TEGRA210_CLK_I2S0_SYNC>;
+ clock-names = "i2s", "sync_input";
+ assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+ assigned-clock-rates = <1536000>;
+ sound-name-prefix = "I2S1";
+ status = "disabled";
+ };
+
+ tegra_i2s2: i2s@702d1100 {
+ compatible = "nvidia,tegra210-i2s";
+ reg = <0x702d1100 0x100>;
+ clocks = <&tegra_car TEGRA210_CLK_I2S1>,
+ <&tegra_car TEGRA210_CLK_I2S1_SYNC>;
+ clock-names = "i2s", "sync_input";
+ assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+ assigned-clock-rates = <1536000>;
+ sound-name-prefix = "I2S2";
+ status = "disabled";
+ };
+
+ tegra_i2s3: i2s@702d1200 {
+ compatible = "nvidia,tegra210-i2s";
+ reg = <0x702d1200 0x100>;
+ clocks = <&tegra_car TEGRA210_CLK_I2S2>,
+ <&tegra_car TEGRA210_CLK_I2S2_SYNC>;
+ clock-names = "i2s", "sync_input";
+ assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+ assigned-clock-rates = <1536000>;
+ sound-name-prefix = "I2S3";
+ status = "disabled";
+ };
+
+ tegra_i2s4: i2s@702d1300 {
+ compatible = "nvidia,tegra210-i2s";
+ reg = <0x702d1300 0x100>;
+ clocks = <&tegra_car TEGRA210_CLK_I2S3>,
+ <&tegra_car TEGRA210_CLK_I2S3_SYNC>;
+ clock-names = "i2s", "sync_input";
+ assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+ assigned-clock-rates = <1536000>;
+ sound-name-prefix = "I2S4";
+ status = "disabled";
+ };
+
+ tegra_i2s5: i2s@702d1400 {
+ compatible = "nvidia,tegra210-i2s";
+ reg = <0x702d1400 0x100>;
+ clocks = <&tegra_car TEGRA210_CLK_I2S4>,
+ <&tegra_car TEGRA210_CLK_I2S4_SYNC>;
+ clock-names = "i2s", "sync_input";
+ assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+ assigned-clock-rates = <1536000>;
+ sound-name-prefix = "I2S5";
+ status = "disabled";
+ };
+
+ tegra_dmic1: dmic@702d4000 {
+ compatible = "nvidia,tegra210-dmic";
+ reg = <0x702d4000 0x100>;
+ clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
+ clock-names = "dmic";
+ assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+ assigned-clock-rates = <3072000>;
+ sound-name-prefix = "DMIC1";
+ status = "disabled";
+ };
+
+ tegra_dmic2: dmic@702d4100 {
+ compatible = "nvidia,tegra210-dmic";
+ reg = <0x702d4100 0x100>;
+ clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
+ clock-names = "dmic";
+ assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+ assigned-clock-rates = <3072000>;
+ sound-name-prefix = "DMIC2";
+ status = "disabled";
+ };
+
+ tegra_dmic3: dmic@702d4200 {
+ compatible = "nvidia,tegra210-dmic";
+ reg = <0x702d4200 0x100>;
+ clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
+ clock-names = "dmic";
+ assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
+ assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
+ assigned-clock-rates = <3072000>;
+ sound-name-prefix = "DMIC3";
+ status = "disabled";
+ };
};
};
@@ -1227,25 +1628,68 @@
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0>;
+ clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
+ <&tegra_car TEGRA210_CLK_PLL_X>,
+ <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
+ <&dfll>;
+ clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
+ clock-latency = <300000>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ next-level-cache = <&L2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <1>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ next-level-cache = <&L2>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <2>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ next-level-cache = <&L2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <3>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ next-level-cache = <&L2>;
};
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x40000007>;
+ entry-latency-us = <100>;
+ exit-latency-us = <30>;
+ min-residency-us = <1000>;
+ wakeup-latency-us = <130>;
+ idle-state-name = "cpu-sleep";
+ status = "disabled";
+ };
+ };
+
+ L2: l2-cache {
+ compatible = "cache";
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
+ &{/cpus/cpu@2} &{/cpus/cpu@3}>;
};
timer {
@@ -1259,14 +1703,17 @@
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
+ arm,no-tick-in-suspend;
};
soctherm: thermal-sensor@700e2000 {
compatible = "nvidia,tegra210-soctherm";
- reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
- 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
+ reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
+ <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
reg-names = "soctherm-reg", "car-reg";
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "thermal", "edp";
clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
<&tegra_car TEGRA210_CLK_SOC_THERM>;
clock-names = "tsensor", "soctherm";
@@ -1313,6 +1760,7 @@
};
};
};
+
mem {
polling-delay-passive = <0>;
polling-delay = <0>;
@@ -1321,6 +1769,18 @@
<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
trips {
+ dram_nominal: mem-nominal-trip {
+ temperature = <50000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ dram_throttle: mem-throttle-trip {
+ temperature = <70000>;
+ hysteresis = <1000>;
+ type = "active";
+ };
+
mem-shutdown-trip {
temperature = <103000>;
hysteresis = <0>;
@@ -1329,12 +1789,18 @@
};
cooling-maps {
- /*
- * There are currently no cooling maps,
- * because there are no cooling devices.
- */
+ dram-passive {
+ cooling-device = <&emc 0 0>;
+ trip = <&dram_nominal>;
+ };
+
+ dram-active {
+ cooling-device = <&emc 1 1>;
+ trip = <&dram_throttle>;
+ };
};
};
+
gpu {
polling-delay-passive = <1000>;
polling-delay = <0>;
@@ -1363,6 +1829,7 @@
};
};
};
+
pllx {
polling-delay-passive = <0>;
polling-delay = <0>;
--
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