From 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 02:46:07 +0000
Subject: [PATCH] add audio
---
kernel/sound/soc/rockchip/rockchip_i2s.c | 348 ++++++++++++++++++++++++++++++---------------------------
1 files changed, 183 insertions(+), 165 deletions(-)
diff --git a/kernel/sound/soc/rockchip/rockchip_i2s.c b/kernel/sound/soc/rockchip/rockchip_i2s.c
index 262a954..1262a91 100644
--- a/kernel/sound/soc/rockchip/rockchip_i2s.c
+++ b/kernel/sound/soc/rockchip/rockchip_i2s.c
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
/* sound/soc/rockchip/rockchip_i2s.c
*
* ALSA SoC Audio Layer - Rockchip I2S Controller driver
*
* Copyright (c) 2014 Rockchip Electronics Co. Ltd.
* Author: Jianqun <jay.xu@rock-chips.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
#include <linux/module.h>
@@ -19,7 +16,6 @@
#include <linux/clk/rockchip.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
-#include <linux/reset.h>
#include <linux/spinlock.h>
#include <sound/pcm_params.h>
#include <sound/dmaengine_pcm.h>
@@ -48,8 +44,9 @@
struct regmap *regmap;
struct regmap *grf;
- struct reset_control *reset_m;
- struct reset_control *reset_h;
+
+ bool has_capture;
+ bool has_playback;
/*
* Used to indicate the tx/rx status.
@@ -60,7 +57,8 @@
bool rx_start;
bool is_master_mode;
const struct rk_i2s_pins *pins;
- unsigned int bclk_fs;
+ unsigned int bclk_ratio;
+ spinlock_t lock; /* tx/rx lock */
unsigned int clk_trcm;
unsigned int mclk_root_rate;
@@ -69,9 +67,6 @@
bool mclk_calibrate;
};
-
-/* txctrl/rxctrl lock */
-static DEFINE_SPINLOCK(lock);
static int i2s_runtime_suspend(struct device *dev)
{
@@ -109,27 +104,44 @@
return snd_soc_dai_get_drvdata(dai);
}
-static void rockchip_i2s_reset(struct rk_i2s_dev *i2s)
+static int rockchip_i2s_clear(struct rk_i2s_dev *i2s)
{
- if (!IS_ERR(i2s->reset_m))
- reset_control_assert(i2s->reset_m);
- if (!IS_ERR(i2s->reset_h))
- reset_control_assert(i2s->reset_h);
- udelay(1);
- if (!IS_ERR(i2s->reset_m))
- reset_control_deassert(i2s->reset_m);
- if (!IS_ERR(i2s->reset_h))
- reset_control_deassert(i2s->reset_h);
- regcache_mark_dirty(i2s->regmap);
- regcache_sync(i2s->regmap);
+ unsigned int clr = I2S_CLR_TXC | I2S_CLR_RXC;
+ unsigned int val = 0;
+ int ret;
+
+ /*
+ * Workaround for FIFO clear on SLAVE mode:
+ *
+ * A Suggest to do reset hclk domain and then do mclk
+ * domain, especially for SLAVE mode without CLK in.
+ * at last, recovery regmap config.
+ *
+ * B Suggest to switch to MASTER, and then do FIFO clr,
+ * at last, bring back to SLAVE.
+ *
+ * Now we choose plan B here.
+ */
+ if (!i2s->is_master_mode)
+ regmap_update_bits(i2s->regmap, I2S_CKR,
+ I2S_CKR_MSS_MASK, I2S_CKR_MSS_MASTER);
+ regmap_update_bits(i2s->regmap, I2S_CLR, clr, clr);
+
+ ret = regmap_read_poll_timeout_atomic(i2s->regmap, I2S_CLR, val,
+ !(val & clr), 10, 100);
+ if (!i2s->is_master_mode)
+ regmap_update_bits(i2s->regmap, I2S_CKR,
+ I2S_CKR_MSS_MASK, I2S_CKR_MSS_SLAVE);
+ if (ret < 0)
+ dev_warn(i2s->dev, "failed to clear fifo on %s mode\n",
+ i2s->is_master_mode ? "master" : "slave");
+
+ return ret;
}
static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
{
- unsigned int val = 0;
- int retry = 10;
-
- spin_lock(&lock);
+ spin_lock(&i2s->lock);
if (on) {
regmap_update_bits(i2s->regmap, I2S_DMACR,
I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
@@ -153,33 +165,15 @@
I2S_XFER_RXS_STOP);
udelay(150);
- regmap_update_bits(i2s->regmap, I2S_CLR,
- I2S_CLR_TXC | I2S_CLR_RXC,
- I2S_CLR_TXC | I2S_CLR_RXC);
-
- regmap_read(i2s->regmap, I2S_CLR, &val);
-
- /* Should wait for clear operation to finish */
- while (val) {
- regmap_read(i2s->regmap, I2S_CLR, &val);
- retry--;
- if (!retry) {
- dev_warn(i2s->dev, "reset\n");
- rockchip_i2s_reset(i2s);
- break;
- }
- }
+ rockchip_i2s_clear(i2s);
}
}
- spin_unlock(&lock);
+ spin_unlock(&i2s->lock);
}
static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
{
- unsigned int val = 0;
- int retry = 10;
-
- spin_lock(&lock);
+ spin_lock(&i2s->lock);
if (on) {
regmap_update_bits(i2s->regmap, I2S_DMACR,
I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
@@ -203,25 +197,10 @@
I2S_XFER_RXS_STOP);
udelay(150);
- regmap_update_bits(i2s->regmap, I2S_CLR,
- I2S_CLR_TXC | I2S_CLR_RXC,
- I2S_CLR_TXC | I2S_CLR_RXC);
-
- regmap_read(i2s->regmap, I2S_CLR, &val);
-
- /* Should wait for clear operation to finish */
- while (val) {
- regmap_read(i2s->regmap, I2S_CLR, &val);
- retry--;
- if (!retry) {
- dev_warn(i2s->dev, "reset\n");
- rockchip_i2s_reset(i2s);
- break;
- }
- }
+ rockchip_i2s_clear(i2s);
}
}
- spin_unlock(&lock);
+ spin_unlock(&i2s->lock);
}
static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
@@ -343,7 +322,7 @@
if (i2s->is_master_mode) {
mclk_rate = clk_get_rate(i2s->mclk);
- bclk_rate = i2s->bclk_fs * params_rate(params);
+ bclk_rate = i2s->bclk_ratio * params_rate(params);
if (!bclk_rate)
return -EINVAL;
@@ -471,6 +450,16 @@
return ret;
}
+static int rockchip_i2s_set_bclk_ratio(struct snd_soc_dai *dai,
+ unsigned int ratio)
+{
+ struct rk_i2s_dev *i2s = to_info(dai);
+
+ i2s->bclk_ratio = ratio;
+
+ return 0;
+}
+
static int rockchip_i2s_clk_set_rate(struct rk_i2s_dev *i2s,
struct clk *clk, unsigned long rate,
int ppm)
@@ -510,6 +499,9 @@
unsigned int root_rate, div, delta;
uint64_t ppm;
int ret;
+
+ if (rate == 0)
+ return 0;
if (i2s->mclk_calibrate) {
ret = rockchip_i2s_clk_set_rate(i2s, i2s->mclk_root,
@@ -591,8 +583,9 @@
{
struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
- dai->capture_dma_data = &i2s->capture_dma_data;
- dai->playback_dma_data = &i2s->playback_dma_data;
+ snd_soc_dai_init_dma_data(dai,
+ i2s->has_playback ? &i2s->playback_dma_data : NULL,
+ i2s->has_capture ? &i2s->capture_dma_data : NULL);
if (i2s->mclk_calibrate)
snd_soc_add_dai_controls(dai, &rockchip_i2s_compensation_control, 1);
@@ -602,6 +595,7 @@
static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
.hw_params = rockchip_i2s_hw_params,
+ .set_bclk_ratio = rockchip_i2s_set_bclk_ratio,
.set_sysclk = rockchip_i2s_set_sysclk,
.set_fmt = rockchip_i2s_set_fmt,
.trigger = rockchip_i2s_trigger,
@@ -609,28 +603,6 @@
static struct snd_soc_dai_driver rockchip_i2s_dai = {
.probe = rockchip_i2s_dai_probe,
- .playback = {
- .stream_name = "Playback",
- .channels_min = 2,
- .channels_max = 8,
- .rates = SNDRV_PCM_RATE_8000_192000,
- .formats = (SNDRV_PCM_FMTBIT_S8 |
- SNDRV_PCM_FMTBIT_S16_LE |
- SNDRV_PCM_FMTBIT_S20_3LE |
- SNDRV_PCM_FMTBIT_S24_LE |
- SNDRV_PCM_FMTBIT_S32_LE),
- },
- .capture = {
- .stream_name = "Capture",
- .channels_min = 2,
- .channels_max = 2,
- .rates = SNDRV_PCM_RATE_8000_192000,
- .formats = (SNDRV_PCM_FMTBIT_S8 |
- SNDRV_PCM_FMTBIT_S16_LE |
- SNDRV_PCM_FMTBIT_S20_3LE |
- SNDRV_PCM_FMTBIT_S24_LE |
- SNDRV_PCM_FMTBIT_S32_LE),
- },
.ops = &rockchip_i2s_dai_ops,
};
@@ -726,7 +698,7 @@
.shift = 11,
};
-static const struct of_device_id rockchip_i2s_match[] = {
+static const struct of_device_id rockchip_i2s_match[] __maybe_unused = {
#ifdef CONFIG_CPU_PX30
{ .compatible = "rockchip,px30-i2s", },
#endif
@@ -743,6 +715,9 @@
#ifdef CONFIG_CPU_RK3188
{ .compatible = "rockchip,rk3188-i2s", },
#endif
+#ifdef CONFIG_CPU_RK322X
+ { .compatible = "rockchip,rk3228-i2s", },
+#endif
#ifdef CONFIG_CPU_RK3288
{ .compatible = "rockchip,rk3288-i2s", },
#endif
@@ -751,6 +726,9 @@
#endif
#ifdef CONFIG_CPU_RK3328
{ .compatible = "rockchip,rk3328-i2s", },
+#endif
+#ifdef CONFIG_CPU_RK3366
+ { .compatible = "rockchip,rk3366-i2s", },
#endif
#ifdef CONFIG_CPU_RK3368
{ .compatible = "rockchip,rk3368-i2s", },
@@ -764,21 +742,102 @@
{},
};
+static int rockchip_i2s_init_dai(struct rk_i2s_dev *i2s, struct resource *res,
+ struct snd_soc_dai_driver **dp)
+{
+ struct device_node *node = i2s->dev->of_node;
+ struct snd_soc_dai_driver *dai;
+ struct property *dma_names;
+ const char *dma_name;
+ unsigned int val;
+
+ of_property_for_each_string(node, "dma-names", dma_names, dma_name) {
+ if (!strcmp(dma_name, "tx"))
+ i2s->has_playback = true;
+ if (!strcmp(dma_name, "rx"))
+ i2s->has_capture = true;
+ }
+
+ dai = devm_kmemdup(i2s->dev, &rockchip_i2s_dai,
+ sizeof(*dai), GFP_KERNEL);
+ if (!dai)
+ return -ENOMEM;
+
+ if (i2s->has_playback) {
+ dai->playback.stream_name = "Playback";
+ dai->playback.channels_min = 2;
+ dai->playback.channels_max = 8;
+ dai->playback.rates = SNDRV_PCM_RATE_8000_192000;
+ dai->playback.formats = SNDRV_PCM_FMTBIT_S8 |
+ SNDRV_PCM_FMTBIT_S16_LE |
+ SNDRV_PCM_FMTBIT_S20_3LE |
+ SNDRV_PCM_FMTBIT_S24_LE |
+ SNDRV_PCM_FMTBIT_S32_LE;
+
+ i2s->playback_dma_data.addr = res->start + I2S_TXDR;
+ i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ i2s->playback_dma_data.maxburst = 8;
+
+ if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
+ if (val >= 2 && val <= 8)
+ dai->playback.channels_max = val;
+ }
+ }
+
+ if (i2s->has_capture) {
+ dai->capture.stream_name = "Capture";
+ dai->capture.channels_min = 2;
+ dai->capture.channels_max = 8;
+ dai->capture.rates = SNDRV_PCM_RATE_8000_192000;
+ dai->capture.formats = SNDRV_PCM_FMTBIT_S8 |
+ SNDRV_PCM_FMTBIT_S16_LE |
+ SNDRV_PCM_FMTBIT_S20_3LE |
+ SNDRV_PCM_FMTBIT_S24_LE |
+ SNDRV_PCM_FMTBIT_S32_LE;
+
+ i2s->capture_dma_data.addr = res->start + I2S_RXDR;
+ i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ i2s->capture_dma_data.maxburst = 8;
+
+ if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
+ if (val >= 2 && val <= 8)
+ dai->capture.channels_max = val;
+ }
+ }
+
+ i2s->clk_trcm = I2S_CKR_TRCM_TXRX;
+ if (!of_property_read_u32(node, "rockchip,clk-trcm", &val)) {
+ if (val >= 0 && val <= 2) {
+ i2s->clk_trcm = val << I2S_CKR_TRCM_SHIFT;
+ if (i2s->clk_trcm)
+ dai->symmetric_rates = 1;
+ }
+ }
+
+ regmap_update_bits(i2s->regmap, I2S_CKR,
+ I2S_CKR_TRCM_MASK, i2s->clk_trcm);
+
+ if (dp)
+ *dp = dai;
+
+ return 0;
+}
+
static int rockchip_i2s_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
const struct of_device_id *of_id;
struct rk_i2s_dev *i2s;
- struct snd_soc_dai_driver *soc_dai;
+ struct snd_soc_dai_driver *dai;
struct resource *res;
void __iomem *regs;
int ret;
- int val;
i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
if (!i2s)
return -ENOMEM;
+ spin_lock_init(&i2s->lock);
i2s->dev = &pdev->dev;
i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
@@ -790,8 +849,21 @@
i2s->pins = of_id->data;
}
- i2s->reset_m = devm_reset_control_get(&pdev->dev, "reset-m");
- i2s->reset_h = devm_reset_control_get(&pdev->dev, "reset-h");
+ regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
+ &rockchip_i2s_regmap_config);
+ if (IS_ERR(i2s->regmap)) {
+ dev_err(&pdev->dev,
+ "Failed to initialise managed register map\n");
+ return PTR_ERR(i2s->regmap);
+ }
+
+ i2s->bclk_ratio = 64;
+
+ dev_set_drvdata(&pdev->dev, i2s);
i2s->mclk_calibrate =
of_property_read_bool(node, "rockchip,mclk-calibrate");
@@ -802,6 +874,12 @@
i2s->mclk_root_initial_rate = clk_get_rate(i2s->mclk_root);
i2s->mclk_root_rate = i2s->mclk_root_initial_rate;
+ }
+
+ i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
+ if (IS_ERR(i2s->mclk)) {
+ dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
+ return PTR_ERR(i2s->mclk);
}
/* try to prepare related clocks */
@@ -816,35 +894,6 @@
return ret;
}
- i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
- if (IS_ERR(i2s->mclk)) {
- dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
- return PTR_ERR(i2s->mclk);
- }
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- regs = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(regs))
- return PTR_ERR(regs);
-
- i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
- &rockchip_i2s_regmap_config);
- if (IS_ERR(i2s->regmap)) {
- dev_err(&pdev->dev,
- "Failed to initialise managed register map\n");
- return PTR_ERR(i2s->regmap);
- }
-
- i2s->playback_dma_data.addr = res->start + I2S_TXDR;
- i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
- i2s->playback_dma_data.maxburst = 8;
-
- i2s->capture_dma_data.addr = res->start + I2S_RXDR;
- i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
- i2s->capture_dma_data.maxburst = 8;
-
- dev_set_drvdata(&pdev->dev, i2s);
-
pm_runtime_enable(&pdev->dev);
if (!pm_runtime_enabled(&pdev->dev)) {
ret = i2s_runtime_resume(&pdev->dev);
@@ -852,57 +901,24 @@
goto err_pm_disable;
}
- soc_dai = devm_kmemdup(&pdev->dev, &rockchip_i2s_dai,
- sizeof(*soc_dai), GFP_KERNEL);
- if (!soc_dai) {
- ret = -ENOMEM;
+ ret = rockchip_i2s_init_dai(i2s, res, &dai);
+ if (ret)
goto err_pm_disable;
- }
-
- if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
- if (val >= 2 && val <= 8)
- soc_dai->playback.channels_max = val;
- }
-
- if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
- if (val >= 2 && val <= 8)
- soc_dai->capture.channels_max = val;
- }
-
- if (of_property_read_bool(node, "rockchip,playback-only"))
- soc_dai->capture.channels_min = 0;
- else if (of_property_read_bool(node, "rockchip,capture-only"))
- soc_dai->playback.channels_min = 0;
-
- i2s->bclk_fs = 64;
- if (!of_property_read_u32(node, "rockchip,bclk-fs", &val)) {
- if ((val >= 32) && (val % 2 == 0))
- i2s->bclk_fs = val;
- }
-
- i2s->clk_trcm = I2S_CKR_TRCM_TXRX;
- if (!of_property_read_u32(node, "rockchip,clk-trcm", &val)) {
- if (val >= 0 && val <= 2) {
- i2s->clk_trcm = val << I2S_CKR_TRCM_SHIFT;
- if (i2s->clk_trcm)
- soc_dai->symmetric_rates = 1;
- }
- }
-
- regmap_update_bits(i2s->regmap, I2S_CKR,
- I2S_CKR_TRCM_MASK, i2s->clk_trcm);
ret = devm_snd_soc_register_component(&pdev->dev,
&rockchip_i2s_component,
- soc_dai, 1);
+ dai, 1);
if (ret) {
dev_err(&pdev->dev, "Could not register DAI\n");
goto err_suspend;
}
- if (of_property_read_bool(node, "rockchip,no-dmaengine"))
- return ret;
+ if (of_property_read_bool(node, "rockchip,no-dmaengine")) {
+ dev_info(&pdev->dev, "Used for Multi-DAI\n");
+ return 0;
+ }
+
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
if (ret) {
dev_err(&pdev->dev, "Could not register PCM\n");
@@ -917,6 +933,8 @@
err_pm_disable:
pm_runtime_disable(&pdev->dev);
+ clk_disable_unprepare(i2s->hclk);
+
return ret;
}
--
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