From 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 02:46:07 +0000
Subject: [PATCH] add audio
---
kernel/arch/xtensa/kernel/hw_breakpoint.c | 23 ++++++++++++-----------
1 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/kernel/arch/xtensa/kernel/hw_breakpoint.c b/kernel/arch/xtensa/kernel/hw_breakpoint.c
index c2e387c..285fb29 100644
--- a/kernel/arch/xtensa/kernel/hw_breakpoint.c
+++ b/kernel/arch/xtensa/kernel/hw_breakpoint.c
@@ -12,7 +12,7 @@
#include <linux/log2.h>
#include <linux/percpu.h>
#include <linux/perf_event.h>
-#include <variant/core.h>
+#include <asm/core.h>
/* Breakpoint currently in use for each IBREAKA. */
static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[XCHAL_NUM_IBREAK]);
@@ -101,30 +101,30 @@
switch (sr) {
#if XCHAL_NUM_IBREAK > 0
case SREG_IBREAKA + 0:
- WSR(v, SREG_IBREAKA + 0);
+ xtensa_set_sr(v, SREG_IBREAKA + 0);
break;
#endif
#if XCHAL_NUM_IBREAK > 1
case SREG_IBREAKA + 1:
- WSR(v, SREG_IBREAKA + 1);
+ xtensa_set_sr(v, SREG_IBREAKA + 1);
break;
#endif
#if XCHAL_NUM_DBREAK > 0
case SREG_DBREAKA + 0:
- WSR(v, SREG_DBREAKA + 0);
+ xtensa_set_sr(v, SREG_DBREAKA + 0);
break;
case SREG_DBREAKC + 0:
- WSR(v, SREG_DBREAKC + 0);
+ xtensa_set_sr(v, SREG_DBREAKC + 0);
break;
#endif
#if XCHAL_NUM_DBREAK > 1
case SREG_DBREAKA + 1:
- WSR(v, SREG_DBREAKA + 1);
+ xtensa_set_sr(v, SREG_DBREAKA + 1);
break;
case SREG_DBREAKC + 1:
- WSR(v, SREG_DBREAKC + 1);
+ xtensa_set_sr(v, SREG_DBREAKC + 1);
break;
#endif
}
@@ -150,8 +150,8 @@
unsigned long ibreakenable;
xtensa_wsr(info->address, SREG_IBREAKA + reg);
- RSR(ibreakenable, SREG_IBREAKENABLE);
- WSR(ibreakenable | (1 << reg), SREG_IBREAKENABLE);
+ ibreakenable = xtensa_get_sr(SREG_IBREAKENABLE);
+ xtensa_set_sr(ibreakenable | (1 << reg), SREG_IBREAKENABLE);
}
static void set_dbreak_regs(int reg, struct perf_event *bp)
@@ -214,8 +214,9 @@
/* Breakpoint */
i = free_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
if (i >= 0) {
- RSR(ibreakenable, SREG_IBREAKENABLE);
- WSR(ibreakenable & ~(1 << i), SREG_IBREAKENABLE);
+ ibreakenable = xtensa_get_sr(SREG_IBREAKENABLE);
+ xtensa_set_sr(ibreakenable & ~(1 << i),
+ SREG_IBREAKENABLE);
}
} else {
/* Watchpoint */
--
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