From 1f93a7dfd1f8d5ff7a5c53246c7534fe2332d6f4 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 02:46:07 +0000
Subject: [PATCH] add audio
---
kernel/arch/arm64/boot/dts/rockchip/rk3568.dtsi | 277 +++++++++++++++++++++++++++++++++++++++++++------------
1 files changed, 216 insertions(+), 61 deletions(-)
diff --git a/kernel/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/kernel/arch/arm64/boot/dts/rockchip/rk3568.dtsi
old mode 100644
new mode 100755
index 32a4478..8a3e1fe
--- a/kernel/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/kernel/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -59,7 +59,8 @@
spi1 = &spi1;
spi2 = &spi2;
spi3 = &spi3;
- spi4 = &sfc; // for U-Boot
+ lvds0 = &lvds;
+ lvds1 = &lvds1;
};
cpus {
@@ -126,8 +127,11 @@
opp-shared;
mbist-vmin = <825000 900000 950000>;
- nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>;
- nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
+ nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>,
+ <&specification_serial_number>, <&remark_spec_serial_number>;
+ nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
+ "specification_serial_number", "remark_spec_serial_number";
+ rockchip,supported-hw;
rockchip,max-volt = <1150000>;
rockchip,pvtm-voltage-sel = <
0 84000 0
@@ -151,23 +155,28 @@
0 1992 75000
>;
+ /* RK3568 && RK3568M cpu OPPs */
opp-408000000 {
+ opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <850000 850000 1150000>;
clock-latency-ns = <40000>;
};
opp-600000000 {
+ opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <850000 850000 1150000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
+ opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <850000 850000 1150000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-1104000000 {
+ opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt = <900000 900000 1150000>;
opp-microvolt-L0 = <900000 900000 1150000>;
@@ -177,6 +186,7 @@
clock-latency-ns = <40000>;
};
opp-1416000000 {
+ opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1025000 1025000 1150000>;
opp-microvolt-L0 = <1025000 1025000 1150000>;
@@ -186,6 +196,7 @@
clock-latency-ns = <40000>;
};
opp-1608000000 {
+ opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <1100000 1100000 1150000>;
opp-microvolt-L0 = <1100000 1100000 1150000>;
@@ -195,6 +206,7 @@
clock-latency-ns = <40000>;
};
opp-1800000000 {
+ opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1150000 1150000 1150000>;
opp-microvolt-L0 = <1150000 1150000 1150000>;
@@ -204,6 +216,7 @@
clock-latency-ns = <40000>;
};
opp-1992000000 {
+ opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1992000000>;
opp-microvolt = <1150000 1150000 1150000>;
opp-microvolt-L0 = <1150000 1150000 1150000>;
@@ -212,9 +225,31 @@
opp-microvolt-L3 = <1100000 1100000 1150000>;
clock-latency-ns = <40000>;
};
+
+ /* RK3568J cpu OPPs */
+ opp-j-1008000000 {
+ opp-supported-hw = <0x04 0xffff>;
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <850000 850000 1150000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-j-1416000000 {
+ opp-supported-hw = <0x04 0xffff>;
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <900000 900000 1150000>;
+ clock-latency-ns = <40000>;
+ };
+
+ /* RK3568M cpu OPPs */
+ opp-m-1608000000 {
+ opp-supported-hw = <0x02 0xffff>;
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1000000 1000000 1150000>;
+ clock-latency-ns = <40000>;
+ };
};
- arm-pmu {
+ arm_pmu: arm-pmu {
compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3";
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
@@ -251,7 +286,7 @@
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
- connect = <&vp0_out_dsi1>;
+ connect = <&vp1_out_dsi1>;
};
route_edp: route-edp {
status = "disabled";
@@ -259,7 +294,7 @@
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
- connect = <&vp0_out_edp>;
+ connect = <&vp1_out_edp>;
};
route_hdmi: route-hdmi {
status = "disabled";
@@ -267,7 +302,7 @@
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
- connect = <&vp1_out_hdmi>;
+ connect = <&vp0_out_hdmi>;
};
route_lvds: route-lvds {
status = "disabled";
@@ -288,12 +323,15 @@
};
};
- firmware {
- optee: optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
+ edac: edac {
+ compatible = "rockchip,rk3568-edac";
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ce", "ue";
+ status = "disabled";
+ };
+ firmware {
scmi: scmi {
compatible = "arm,scmi-smc";
shmem = <&scmi_shmem>;
@@ -313,6 +351,12 @@
compatible = "arm,sdei-1.0";
method = "smc";
};
+ };
+
+ mipi_csi2: mipi-csi2 {
+ compatible = "rockchip,rk3568-mipi-csi2";
+ rockchip,hw = <&mipi_csi2_hw>;
+ status = "disabled";
};
mpp_srv: mpp-srv {
@@ -580,12 +624,15 @@
resets = <&cru SRST_USB3OTG0>;
reset-names = "usb3-otg";
snps,dis_enblslpm_quirk;
- snps,dis-u1u2-quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,dis_rxdet_inp3_quirk;
snps,xhci-trb-ent-quirk;
+ snps,parkmode-disable-hs-quirk;
+ snps,parkmode-disable-ss-quirk;
quirk-skip-phy-init;
status = "disabled";
};
@@ -619,6 +666,8 @@
snps,dis-tx-ipgap-linecheck-quirk;
snps,dis_rxdet_inp3_quirk;
snps,xhci-trb-ent-quirk;
+ snps,parkmode-disable-hs-quirk;
+ snps,parkmode-disable-ss-quirk;
status = "disabled";
};
};
@@ -759,6 +808,34 @@
reg = <2>;
remote-endpoint = <&vp2_out_lvds>;
status = "disabled";
+ };
+ };
+ };
+ };
+
+ lvds1: lvds1 {
+ compatible = "rockchip,rk3568-lvds";
+ phys = <&video_phy1>;
+ phy-names = "phy";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lvds1_in_vp1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vp1_out_lvds1>;
+ };
+
+ lvds1_in_vp2: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vp2_out_lvds1>;
};
};
};
@@ -1107,8 +1184,11 @@
compatible = "operating-points-v2";
mbist-vmin = <825000 900000 950000>;
- nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>;
- nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
+ nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>,
+ <&specification_serial_number>, <&remark_spec_serial_number>;
+ nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
+ "specification_serial_number", "remark_spec_serial_number";
+ rockchip,supported-hw;
rockchip,max-volt = <1000000>;
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <0>;
@@ -1124,23 +1204,29 @@
>;
rockchip,pvtm-ch = <0 5>;
+ /* RK3568 && RK3568M npu OPPs */
opp-200000000 {
+ opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <850000 850000 1000000>;
};
opp-300000000 {
+ opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <297000000>;
opp-microvolt = <850000 850000 1000000>;
};
opp-400000000 {
+ opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <850000 850000 1000000>;
};
opp-600000000 {
+ opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <850000 850000 1000000>;
};
opp-700000000 {
+ opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <875000 875000 1000000>;
opp-microvolt-L0 = <875000 875000 1000000>;
@@ -1149,6 +1235,7 @@
opp-microvolt-L3 = <850000 850000 1000000>;
};
opp-800000000 {
+ opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <925000 925000 1000000>;
opp-microvolt-L0 = <925000 925000 1000000>;
@@ -1157,6 +1244,7 @@
opp-microvolt-L3 = <875000 875000 1000000>;
};
opp-900000000 {
+ opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <975000 975000 1000000>;
opp-microvolt-L0 = <975000 975000 1000000>;
@@ -1165,6 +1253,7 @@
opp-microvolt-L3 = <900000 900000 1000000>;
};
opp-1000000000 {
+ opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1000000 1000000 1000000>;
opp-microvolt-L0 = <1000000 1000000 1000000>;
@@ -1172,6 +1261,20 @@
opp-microvolt-L2 = <950000 950000 1000000>;
opp-microvolt-L3 = <925000 925000 1000000>;
status = "disabled";
+ };
+
+ /* RK3568J npu OPPs */
+ opp-j-600000000 {
+ opp-supported-hw = <0x04 0xffff>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <900000 900000 1000000>;
+ };
+
+ /* RK3568M npu OPPs */
+ opp-m-900000000 {
+ opp-supported-hw = <0x02 0xffff>;
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <925000 925000 1000000>;
};
};
@@ -1263,8 +1366,11 @@
compatible = "operating-points-v2";
mbist-vmin = <825000 900000 950000>;
- nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>;
- nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
+ nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>,
+ <&specification_serial_number>, <&remark_spec_serial_number>;
+ nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
+ "specification_serial_number", "remark_spec_serial_number";
+ rockchip,supported-hw;
rockchip,max-volt = <1000000>;
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <0>;
@@ -1280,19 +1386,24 @@
>;
rockchip,pvtm-ch = <0 5>;
+ /* RK3568 && RK3568M gpu OPPs */
opp-200000000 {
+ opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <850000 850000 1000000>;
};
opp-300000000 {
+ opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <850000 850000 1000000>;
};
opp-400000000 {
+ opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <850000 850000 1000000>;
};
opp-600000000 {
+ opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <900000 900000 1000000>;
opp-microvolt-L0 = <900000 900000 1000000>;
@@ -1301,6 +1412,7 @@
opp-microvolt-L3 = <850000 850000 1000000>;
};
opp-700000000 {
+ opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <950000 950000 1000000>;
opp-microvolt-L0 = <950000 950000 1000000>;
@@ -1309,6 +1421,7 @@
opp-microvolt-L3 = <875000 875000 1000000>;
};
opp-800000000 {
+ opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1000000 1000000 1000000>;
opp-microvolt-L0 = <1000000 1000000 1000000>;
@@ -1316,6 +1429,21 @@
opp-microvolt-L2 = <950000 950000 1000000>;
opp-microvolt-L3 = <925000 925000 1000000>;
};
+
+ /* RK3568J gpu OPPs */
+ opp-j-600000000 {
+ opp-supported-hw = <0x04 0xffff>;
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <900000 900000 1000000>;
+ };
+
+ /* RK3568M gpu OPPs */
+ opp-m-800000000 {
+ opp-supported-hw = <0x02 0xffff>;
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <950000 950000 1000000>;
+ };
+
};
pvtm@fde80000 {
@@ -1374,7 +1502,6 @@
clock-names = "aclk", "iface";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
power-domains = <&power RK3568_PD_VPU>;
- rockchip,shootdown-entire;
#iommu-cells = <0>;
status = "disabled";
};
@@ -1427,7 +1554,6 @@
clock-names = "aclk", "iface";
clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
power-domains = <&power RK3568_PD_RGA>;
- rockchip,shootdown-entire;
#iommu-cells = <0>;
status = "disabled";
};
@@ -1457,7 +1583,6 @@
clock-names = "aclk", "iface";
clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
power-domains = <&power RK3568_PD_RGA>;
- rockchip,shootdown-entire;
#iommu-cells = <0>;
status = "disabled";
};
@@ -1488,7 +1613,6 @@
clock-names = "aclk", "iface";
#iommu-cells = <0>;
power-domains = <&power RK3568_PD_RGA>;
- rockchip,shootdown-entire;
//rockchip,disable-device-link-resume;
status = "disabled";
};
@@ -1564,7 +1688,6 @@
clock-names = "aclk", "iface";
rockchip,disable-mmu-reset;
rockchip,enable-cmd-retry;
- rockchip,shootdown-entire;
#iommu-cells = <0>;
power-domains = <&power RK3568_PD_RKVENC>;
status = "disabled";
@@ -1644,13 +1767,12 @@
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
power-domains = <&power RK3568_PD_RKVDEC>;
- rockchip,shootdown-entire;
#iommu-cells = <0>;
status = "disabled";
};
- mipi_csi2: mipi-csi2@fdfb0000 {
- compatible = "rockchip,rk3568-mipi-csi2";
+ mipi_csi2_hw: mipi-csi2-hw@fdfb0000 {
+ compatible = "rockchip,rk3568-mipi-csi2-hw";
reg = <0x0 0xfdfb0000 0x0 0x10000>;
reg-names = "csihost_regs";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
@@ -1897,6 +2019,11 @@
reg = <4>;
remote-endpoint = <&lvds_in_vp1>;
};
+
+ vp1_out_lvds1: endpoint@5 {
+ reg = <5>;
+ remote-endpoint = <&lvds1_in_vp1>;
+ };
};
vp2: port@2 {
@@ -1914,6 +2041,11 @@
reg = <1>;
remote-endpoint = <&rgb_in_vp2>;
};
+
+ vp2_out_lvds1: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&lvds1_in_vp2>;
+ };
};
};
};
@@ -1926,6 +2058,7 @@
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
+ rockchip,disable-device-link-resume;
status = "disabled";
};
@@ -1933,12 +2066,12 @@
compatible = "rockchip,rk3568-mipi-dsi";
reg = <0x0 0xfe060000 0x0 0x10000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>, <&video_phy0>;
- clock-names = "pclk", "hclk", "hs_clk";
+ clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
+ clock-names = "pclk", "hclk";
resets = <&cru SRST_P_DSITX_0>;
reset-names = "apb";
phys = <&video_phy0>;
- phy-names = "mipi_dphy";
+ phy-names = "dphy";
power-domains = <&power RK3568_PD_VO>;
rockchip,grf = <&grf>;
#address-cells = <1>;
@@ -1973,12 +2106,12 @@
compatible = "rockchip,rk3568-mipi-dsi";
reg = <0x0 0xfe070000 0x0 0x10000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>, <&video_phy1>;
- clock-names = "pclk", "hclk", "hs_clk";
+ clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
+ clock-names = "pclk", "hclk";
resets = <&cru SRST_P_DSITX_1>;
reset-names = "apb";
phys = <&video_phy1>;
- phy-names = "mipi_dphy";
+ phy-names = "dphy";
power-domains = <&power RK3568_PD_VO>;
rockchip,grf = <&grf>;
#address-cells = <1>;
@@ -2012,8 +2145,7 @@
hdmi: hdmi@fe0a0000 {
compatible = "rockchip,rk3568-dw-hdmi";
reg = <0x0 0xfe0a0000 0x0 0x20000>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hdmi", "hdmi_wakeup";
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI_HOST>,
<&cru CLK_HDMI_SFR>,
<&cru CLK_HDMI_CEC>,
@@ -2032,7 +2164,7 @@
#address-cells = <1>;
#size-cells = <0>;
- hdmi_in: port {
+ port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
@@ -2042,6 +2174,7 @@
remote-endpoint = <&vp0_out_hdmi>;
status = "disabled";
};
+
hdmi_in_vp1: endpoint@1 {
reg = <1>;
remote-endpoint = <&vp1_out_hdmi>;
@@ -2332,8 +2465,11 @@
compatible = "operating-points-v2";
mbist-vmin = <825000 900000 950000>;
- nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>;
- nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
+ nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>,
+ <&specification_serial_number>, <&remark_spec_serial_number>;
+ nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info",
+ "specification_serial_number", "remark_spec_serial_number";
+ rockchip,supported-hw;
rockchip,max-volt = <1000000>;
rockchip,temp-hysteresis = <5000>;
rockchip,low-temp = <0>;
@@ -2351,17 +2487,21 @@
>;
rockchip,pvtm-ch = <0 5>;
+ /* RK3568 dmc OPPs */
opp-1560000000 {
+ opp-supported-hw = <0xf9 0xffff>;
opp-hz = /bits/ 64 <1560000000>;
opp-microvolt = <900000 900000 1000000>;
opp-microvolt-L0 = <900000 900000 1000000>;
opp-microvolt-L1 = <875000 875000 1000000>;
};
- };
- dmcdbg: dmcdbg {
- compatible = "rockchip,rk3568-dmcdbg";
- status = "disabled";
+ /* RK3568J/M dmc OPPs */
+ opp-j-m-1560000000 {
+ opp-supported-hw = <0x06 0xffff>;
+ opp-hz = /bits/ 64 <1560000000>;
+ opp-microvolt = <875000 875000 1000000>;
+ };
};
pcie2x1: pcie@fe260000 {
@@ -2613,7 +2753,7 @@
status = "disabled";
};
- sfc: sfc@fe300000 {
+ sfc: spi@fe300000 {
compatible = "rockchip,sfc";
reg = <0x0 0xfe300000 0x0 0x4000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
@@ -2621,11 +2761,13 @@
clock-names = "clk_sfc", "hclk_sfc";
assigned-clocks = <&cru SCLK_SFC>;
assigned-clock-rates = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
sdhci: sdhci@fe310000 {
- compatible = "rockchip,dwcmshc-sdhci", "snps,dwcmshc-sdhci";
+ compatible = "rockchip,rk3568-dwcmshc", "rockchip,dwcmshc-sdhci";
reg = <0x0 0xfe310000 0x0 0x10000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
@@ -2635,6 +2777,10 @@
<&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
<&cru TCLK_EMMC>;
clock-names = "core", "bus", "axi", "block", "timer";
+ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
+ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
+ <&cru SRST_T_EMMC>;
+ reset-names = "core", "bus", "axi", "block", "timer";
status = "disabled";
};
@@ -2686,6 +2832,10 @@
/* Data cells */
cpu_code: cpu-code@2 {
reg = <0x02 0x2>;
+ };
+ specification_serial_number: specification-serial-number@7 {
+ reg = <0x07 0x1>;
+ bits = <0 5>;
};
otp_cpu_version: cpu-version@8 {
reg = <0x08 0x1>;
@@ -2745,6 +2895,10 @@
};
dmc_opp_info: dmc-opp-info@48 {
reg = <0x48 0x6>;
+ };
+ remark_spec_serial_number: remark-spec-serial-number@56 {
+ reg = <0x56 0x1>;
+ bits = <0 5>;
};
};
@@ -2837,7 +2991,7 @@
};
pdm: pdm@fe440000 {
- compatible = "rockchip,rk3568-pdm";
+ compatible = "rockchip,rk3568-pdm", "rockchip,pdm";
reg = <0x0 0xfe440000 0x0 0x1000>;
clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
clock-names = "pdm_clk", "pdm_hclk";
@@ -3077,6 +3231,7 @@
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>;
+ num-cs = <2>;
status = "disabled";
};
@@ -3093,6 +3248,7 @@
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
pinctrl-1 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins_hs>;
+ num-cs = <2>;
status = "disabled";
};
@@ -3109,6 +3265,7 @@
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>;
+ num-cs = <2>;
status = "disabled";
};
@@ -3125,6 +3282,7 @@
pinctrl-names = "default", "high_speed";
pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
pinctrl-1 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins_hs>;
+ num-cs = <2>;
status = "disabled";
};
@@ -3503,31 +3661,33 @@
status = "disabled";
};
- video_phy0: video-phy@fe850000 {
- compatible = "rockchip,rk3568-video-phy";
+ video_phy0: phy@fe850000 {
+ compatible = "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy";
reg = <0x0 0xfe850000 0x0 0x10000>,
<0x0 0xfe060000 0x0 0x10000>;
+ reg-names = "phy", "host";
clocks = <&pmucru CLK_MIPIDSIPHY0_REF>,
<&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>;
- clock-names = "ref", "pclk_phy", "pclk_host";
+ clock-names = "ref", "pclk", "pclk_host";
#clock-cells = <0>;
resets = <&cru SRST_P_MIPIDSIPHY0>;
- reset-names = "rst";
+ reset-names = "apb";
power-domains = <&power RK3568_PD_VO>;
#phy-cells = <0>;
status = "disabled";
};
- video_phy1: video-phy@fe860000 {
- compatible = "rockchip,rk3568-video-phy";
+ video_phy1: phy@fe860000 {
+ compatible = "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy";
reg = <0x0 0xfe860000 0x0 0x10000>,
<0x0 0xfe070000 0x0 0x10000>;
+ reg-names = "phy", "host";
clocks = <&pmucru CLK_MIPIDSIPHY1_REF>,
<&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>;
- clock-names = "ref", "pclk_phy", "pclk_host";
+ clock-names = "ref", "pclk", "pclk_host";
#clock-cells = <0>;
resets = <&cru SRST_P_MIPIDSIPHY1>;
- reset-names = "rst";
+ reset-names = "apb";
power-domains = <&power RK3568_PD_VO>;
#phy-cells = <0>;
status = "disabled";
@@ -3637,7 +3797,7 @@
#size-cells = <2>;
ranges;
- gpio0: gpio@fdd60000 {
+ gpio0: gpio0@fdd60000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfdd60000 0x0 0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
@@ -3645,12 +3805,11 @@
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 0 32>;
interrupt-controller;
#interrupt-cells = <2>;
};
- gpio1: gpio@fe740000 {
+ gpio1: gpio1@fe740000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe740000 0x0 0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
@@ -3658,12 +3817,11 @@
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 32 32>;
interrupt-controller;
#interrupt-cells = <2>;
};
- gpio2: gpio@fe750000 {
+ gpio2: gpio2@fe750000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe750000 0x0 0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
@@ -3671,12 +3829,11 @@
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 64 32>;
interrupt-controller;
#interrupt-cells = <2>;
};
- gpio3: gpio@fe760000 {
+ gpio3: gpio3@fe760000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe760000 0x0 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
@@ -3684,12 +3841,11 @@
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 96 32>;
interrupt-controller;
#interrupt-cells = <2>;
};
- gpio4: gpio@fe770000 {
+ gpio4: gpio4@fe770000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe770000 0x0 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
@@ -3697,7 +3853,6 @@
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&pinctrl 0 128 32>;
interrupt-controller;
#interrupt-cells = <2>;
};
--
Gitblit v1.6.2