From 1c055e55a242a33e574e48be530e06770a210dcd Mon Sep 17 00:00:00 2001 From: hc <hc@nodka.com> Date: Mon, 19 Feb 2024 03:26:26 +0000 Subject: [PATCH] add r8169 read mac form eeprom --- kernel/include/dt-bindings/clock/exynos4.h | 38 +++----------------------------------- 1 files changed, 3 insertions(+), 35 deletions(-) diff --git a/kernel/include/dt-bindings/clock/exynos4.h b/kernel/include/dt-bindings/clock/exynos4.h index e9f9d40..88ec396 100644 --- a/kernel/include/dt-bindings/clock/exynos4.h +++ b/kernel/include/dt-bindings/clock/exynos4.h @@ -1,13 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2013 Samsung Electronics Co., Ltd. * Author: Andrzej Hajda <a.hajda@samsung.com> * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * * Device Tree binding constants for Exynos4 clock controller. -*/ + */ #ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H #define _DT_BINDINGS_CLOCK_EXYNOS_4_H @@ -190,32 +187,7 @@ #define CLK_MIPI_HSI 349 /* Exynos4210 only */ #define CLK_PIXELASYNCM0 351 #define CLK_PIXELASYNCM1 352 -#define CLK_FIMC_LITE0 353 /* Exynos4x12 only */ -#define CLK_FIMC_LITE1 354 /* Exynos4x12 only */ -#define CLK_PPMUISPX 355 /* Exynos4x12 only */ -#define CLK_PPMUISPMX 356 /* Exynos4x12 only */ -#define CLK_FIMC_ISP 357 /* Exynos4x12 only */ -#define CLK_FIMC_DRC 358 /* Exynos4x12 only */ -#define CLK_FIMC_FD 359 /* Exynos4x12 only */ -#define CLK_MCUISP 360 /* Exynos4x12 only */ -#define CLK_GICISP 361 /* Exynos4x12 only */ -#define CLK_SMMU_ISP 362 /* Exynos4x12 only */ -#define CLK_SMMU_DRC 363 /* Exynos4x12 only */ -#define CLK_SMMU_FD 364 /* Exynos4x12 only */ -#define CLK_SMMU_LITE0 365 /* Exynos4x12 only */ -#define CLK_SMMU_LITE1 366 /* Exynos4x12 only */ -#define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */ -#define CLK_MPWM_ISP 368 /* Exynos4x12 only */ -#define CLK_I2C0_ISP 369 /* Exynos4x12 only */ -#define CLK_I2C1_ISP 370 /* Exynos4x12 only */ -#define CLK_MTCADC_ISP 371 /* Exynos4x12 only */ -#define CLK_PWM_ISP 372 /* Exynos4x12 only */ -#define CLK_WDT_ISP 373 /* Exynos4x12 only */ -#define CLK_UART_ISP 374 /* Exynos4x12 only */ -#define CLK_ASYNCAXIM 375 /* Exynos4x12 only */ -#define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */ -#define CLK_SPI0_ISP 377 /* Exynos4x12 only */ -#define CLK_SPI1_ISP 378 /* Exynos4x12 only */ +#define CLK_ASYNC_G3D 353 /* Exynos4x12 only */ #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ @@ -257,10 +229,6 @@ #define CLK_PPMUACP 415 /* div clocks */ -#define CLK_DIV_ISP0 450 /* Exynos4x12 only */ -#define CLK_DIV_ISP1 451 /* Exynos4x12 only */ -#define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */ -#define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */ #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ #define CLK_DIV_ACP 456 -- Gitblit v1.6.2