From 1c055e55a242a33e574e48be530e06770a210dcd Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 19 Feb 2024 03:26:26 +0000
Subject: [PATCH] add r8169 read mac form eeprom
---
kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/sbutils.c | 102 ++++++++++++++++++++++-----------------------------
1 files changed, 44 insertions(+), 58 deletions(-)
diff --git a/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/sbutils.c b/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/sbutils.c
index 1fde440..ecdb2c8 100644
--- a/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/sbutils.c
+++ b/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/sbutils.c
@@ -1,16 +1,17 @@
-/* SPDX-License-Identifier: GPL-2.0 */
/*
* Misc utility routines for accessing chip-specific features
* of the SiliconBackplane-based Broadcom chips.
*
- * Copyright (C) 1999-2019, Broadcom Corporation
- *
+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
+ *
+ * Copyright (C) 1999-2017, Broadcom Corporation
+ *
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
- *
+ *
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
@@ -18,7 +19,7 @@
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
- *
+ *
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
@@ -26,7 +27,7 @@
*
* <<Broadcom-WL-IPTag/Open:>>
*
- * $Id: sbutils.c 514727 2014-11-12 03:02:48Z $
+ * $Id: sbutils.c 700323 2017-05-18 16:12:11Z $
*/
#include <bcm_cfg.h>
@@ -43,16 +44,15 @@
#include "siutils_priv.h"
-
/* local prototypes */
static uint _sb_coreidx(si_info_t *sii, uint32 sba);
-static uint _sb_scan(si_info_t *sii, uint32 sba, void *regs, uint bus, uint32 sbba,
- uint ncores);
+static uint _sb_scan(si_info_t *sii, uint32 sba, volatile void *regs, uint bus, uint32 sbba,
+ uint ncores, uint devid);
static uint32 _sb_coresba(si_info_t *sii);
-static void *_sb_setcoreidx(si_info_t *sii, uint coreidx);
+static volatile void *_sb_setcoreidx(si_info_t *sii, uint coreidx);
#define SET_SBREG(sii, r, mask, val) \
W_SBREG((sii), (r), ((R_SBREG((sii), (r)) & ~(mask)) | (val)))
-#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
+#define REGS2SB(va) (sbconfig_t*) ((volatile int8*)(va) + SBCONFIGOFF)
/* sonicsrev */
#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
@@ -66,10 +66,8 @@
static uint32
sb_read_sbreg(si_info_t *sii, volatile uint32 *sbr)
{
- si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
uint8 tmp;
uint32 val, intr_val = 0;
-
/*
* compact flash only has 11 bits address, while we needs 12 bits address.
@@ -98,11 +96,9 @@
static void
sb_write_sbreg(si_info_t *sii, volatile uint32 *sbr, uint32 v)
{
- si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
uint8 tmp;
volatile uint32 dummy;
uint32 intr_val = 0;
-
/*
* compact flash only has 11 bits address, while we needs 12 bits address.
@@ -150,8 +146,7 @@
sb_intflag(si_t *sih)
{
si_info_t *sii = SI_INFO(sih);
- si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
- void *corereg;
+ volatile void *corereg;
sbconfig_t *sb;
uint origidx, intflag, intr_val = 0;
@@ -215,7 +210,6 @@
{
uint32 sbaddr;
-
switch (BUSTYPE(sii->pub.bustype)) {
case SI_BUS: {
sbconfig_t *sb = REGS2SB(sii->curmap);
@@ -243,8 +237,7 @@
case SDIO_BUS:
sbaddr = (uint32)(uintptr)sii->curmap;
break;
-#endif
-
+#endif // endif
default:
sbaddr = BADCOREADDR;
@@ -377,7 +370,7 @@
sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
{
uint origidx = 0;
- uint32 *r = NULL;
+ volatile uint32 *r = NULL;
uint w;
uint intr_val = 0;
bool fast = FALSE;
@@ -400,7 +393,7 @@
SI_CORE_SIZE);
ASSERT(GOODREGS(cores_info->regs[coreidx]));
}
- r = (uint32 *)((uchar *)cores_info->regs[coreidx] + regoff);
+ r = (volatile uint32 *)((volatile uchar *)cores_info->regs[coreidx] + regoff);
} else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
@@ -408,17 +401,18 @@
/* Chipc registers are mapped at 12KB */
fast = TRUE;
- r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
+ r = (volatile uint32 *)((volatile char *)sii->curmap +
+ PCI_16KB0_CCREGS_OFFSET + regoff);
} else if (sii->pub.buscoreidx == coreidx) {
/* pci registers are at either in the last 2KB of an 8KB window
* or, in pcie and pci rev 13 at 8KB
*/
fast = TRUE;
if (SI_FAST(sii))
- r = (uint32 *)((char *)sii->curmap +
+ r = (volatile uint32 *)((volatile char *)sii->curmap +
PCI_16KB0_PCIREGS_OFFSET + regoff);
else
- r = (uint32 *)((char *)sii->curmap +
+ r = (volatile uint32 *)((volatile char *)sii->curmap +
((regoff >= SBCONFIGOFF) ?
PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
regoff);
@@ -432,7 +426,8 @@
origidx = si_coreidx(&sii->pub);
/* switch core */
- r = (uint32*) ((uchar*)sb_setcoreidx(&sii->pub, coreidx) + regoff);
+ r = (volatile uint32*) ((volatile uchar*)sb_setcoreidx(&sii->pub, coreidx) +
+ regoff);
}
ASSERT(r != NULL);
@@ -451,12 +446,7 @@
if (regoff >= SBCONFIGOFF)
w = R_SBREG(sii, r);
else {
- if ((CHIPID(sii->pub.chip) == BCM5354_CHIP_ID) &&
- (coreidx == SI_CC_IDX) &&
- (regoff == OFFSETOF(chipcregs_t, watchdog))) {
- w = val;
- } else
- w = R_REG(sii->osh, r);
+ w = R_REG(sii->osh, r);
}
if (!fast) {
@@ -479,10 +469,10 @@
* For accessing registers that would need a core switch, this function will return
* NULL.
*/
-uint32 *
+volatile uint32 *
sb_corereg_addr(si_t *sih, uint coreidx, uint regoff)
{
- uint32 *r = NULL;
+ volatile uint32 *r = NULL;
bool fast = FALSE;
si_info_t *sii = SI_INFO(sih);
si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
@@ -502,7 +492,7 @@
SI_CORE_SIZE);
ASSERT(GOODREGS(cores_info->regs[coreidx]));
}
- r = (uint32 *)((uchar *)cores_info->regs[coreidx] + regoff);
+ r = (volatile uint32 *)((volatile uchar *)cores_info->regs[coreidx] + regoff);
} else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
@@ -510,17 +500,18 @@
/* Chipc registers are mapped at 12KB */
fast = TRUE;
- r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
+ r = (volatile uint32 *)((volatile char *)sii->curmap +
+ PCI_16KB0_CCREGS_OFFSET + regoff);
} else if (sii->pub.buscoreidx == coreidx) {
/* pci registers are at either in the last 2KB of an 8KB window
* or, in pcie and pci rev 13 at 8KB
*/
fast = TRUE;
if (SI_FAST(sii))
- r = (uint32 *)((char *)sii->curmap +
+ r = (volatile uint32 *)((volatile char *)sii->curmap +
PCI_16KB0_PCIREGS_OFFSET + regoff);
else
- r = (uint32 *)((char *)sii->curmap +
+ r = (volatile uint32 *)((volatile char *)sii->curmap +
((regoff >= SBCONFIGOFF) ?
PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
regoff);
@@ -542,7 +533,8 @@
*/
#define SB_MAXBUSES 2
static uint
-_sb_scan(si_info_t *sii, uint32 sba, void *regs, uint bus, uint32 sbba, uint numcores)
+_sb_scan(si_info_t *sii, uint32 sba, volatile void *regs, uint bus,
+ uint32 sbba, uint numcores, uint devid)
{
uint next;
uint ncc = 0;
@@ -588,9 +580,7 @@
/* Older chips */
uint chip = CHIPID(sii->pub.chip);
- if (chip == BCM4306_CHIP_ID) /* < 4306c0 */
- numcores = 6;
- else if (chip == BCM4704_CHIP_ID)
+ if (chip == BCM4704_CHIP_ID)
numcores = 9;
else if (chip == BCM5365_CHIP_ID)
numcores = 7;
@@ -612,15 +602,15 @@
sii->numcores = next + 1;
- if ((nsbba & 0xfff00000) != SI_ENUM_BASE)
+ if ((nsbba & 0xfff00000) != si_enum_base(devid))
continue;
nsbba &= 0xfffff000;
if (_sb_coreidx(sii, nsbba) != BADIDX)
continue;
nsbcc = (R_SBREG(sii, &sb->sbtmstatehigh) & 0x000f0000) >> 16;
- nsbcc = _sb_scan(sii, sba, regs, bus + 1, nsbba, nsbcc);
- if (sbba == SI_ENUM_BASE)
+ nsbcc = _sb_scan(sii, sba, regs, bus + 1, nsbba, nsbcc, devid);
+ if (sbba == si_enum_base(devid))
numcores -= nsbcc;
ncc += nsbcc;
}
@@ -634,11 +624,12 @@
/* scan the sb enumerated space to identify all cores */
void
-sb_scan(si_t *sih, void *regs, uint devid)
+sb_scan(si_t *sih, volatile void *regs, uint devid)
{
uint32 origsba;
sbconfig_t *sb;
si_info_t *sii = SI_INFO(sih);
+ BCM_REFERENCE(devid);
sb = REGS2SB(sii->curmap);
@@ -649,8 +640,8 @@
*/
origsba = _sb_coresba(sii);
- /* scan all SB(s) starting from SI_ENUM_BASE */
- sii->numcores = _sb_scan(sii, origsba, regs, 0, SI_ENUM_BASE, 1);
+ /* scan all SB(s) starting from SI_ENUM_BASE_DEFAULT */
+ sii->numcores = _sb_scan(sii, origsba, regs, 0, si_enum_base(devid), 1, devid);
}
/*
@@ -658,7 +649,7 @@
* must be called with interrupts off.
* Moreover, callers should keep interrupts off during switching out of and back to d11 core
*/
-void *
+volatile void *
sb_setcoreidx(si_t *sih, uint coreidx)
{
si_info_t *sii = SI_INFO(sih);
@@ -681,12 +672,12 @@
/* This function changes the logical "focus" to the indicated core.
* Return the current core's virtual address.
*/
-static void *
+static volatile void *
_sb_setcoreidx(si_info_t *sii, uint coreidx)
{
si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
uint32 sbaddr = cores_info->coresba[coreidx];
- void *regs;
+ volatile void *regs;
switch (BUSTYPE(sii->pub.bustype)) {
case SI_BUS:
@@ -725,7 +716,6 @@
regs = cores_info->regs[coreidx];
break;
#endif /* BCMSDIO */
-
default:
ASSERT(0);
@@ -806,13 +796,11 @@
return (sb_size(R_SBREG(sii, sb_admatch(sii, asidx))));
}
-
/* do buffered registers update */
void
sb_commit(si_t *sih)
{
si_info_t *sii = SI_INFO(sih);
- si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
uint origidx;
uint intr_val = 0;
@@ -974,12 +962,10 @@
sb_set_initiator_to(si_t *sih, uint32 to, uint idx)
{
si_info_t *sii = SI_INFO(sih);
- si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
uint origidx;
uint intr_val = 0;
uint32 tmp, ret = 0xffffffff;
sbconfig_t *sb;
-
if ((to & ~TO_MASK) != 0)
return ret;
@@ -996,7 +982,7 @@
case PCMCIA_BUS:
#ifdef BCMSDIO
case SDIO_BUS:
-#endif
+#endif // endif
idx = si_findcoreidx(sih, PCMCIA_CORE_ID, 0);
break;
case SI_BUS:
@@ -1106,4 +1092,4 @@
sb_setcoreidx(sih, origidx);
INTR_RESTORE(sii, intr_val);
}
-#endif
+#endif // endif
--
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