From 1543e317f1da31b75942316931e8f491a8920811 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 04 Jan 2024 10:08:02 +0000
Subject: [PATCH] disable FB
---
kernel/drivers/phy/marvell/phy-pxa-28nm-usb2.c | 44 ++++++++++++++++----------------------------
1 files changed, 16 insertions(+), 28 deletions(-)
diff --git a/kernel/drivers/phy/marvell/phy-pxa-28nm-usb2.c b/kernel/drivers/phy/marvell/phy-pxa-28nm-usb2.c
index 37e9c8c..a175ae9 100644
--- a/kernel/drivers/phy/marvell/phy-pxa-28nm-usb2.c
+++ b/kernel/drivers/phy/marvell/phy-pxa-28nm-usb2.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 Linaro, Ltd.
* Rob Herring <robh@kernel.org>
@@ -5,16 +6,6 @@
* Based on vendor driver:
* Copyright (C) 2013 Marvell Inc.
* Author: Chao Xie <xiechao.mail@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
*/
#include <linux/delay.h>
@@ -22,6 +13,7 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/module.h>
@@ -147,15 +139,12 @@
struct clk *clk;
};
-static bool wait_for_reg(void __iomem *reg, u32 mask, unsigned long timeout)
+static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms)
{
- timeout += jiffies;
- while (time_is_after_eq_jiffies(timeout)) {
- if ((readl(reg) & mask) == mask)
- return true;
- msleep(1);
- }
- return false;
+ u32 val;
+
+ return readl_poll_timeout(reg, val, ((val & mask) == mask),
+ 1000, 1000 * ms);
}
static int mv_usb2_phy_28nm_init(struct phy *phy)
@@ -217,24 +206,23 @@
*/
/* Make sure PHY Calibration is ready */
- if (!wait_for_reg(base + PHY_28NM_CAL_REG,
- PHY_28NM_PLL_PLLCAL_DONE | PHY_28NM_PLL_IMPCAL_DONE,
- HZ / 10)) {
+ ret = wait_for_reg(base + PHY_28NM_CAL_REG,
+ PHY_28NM_PLL_PLLCAL_DONE | PHY_28NM_PLL_IMPCAL_DONE,
+ 100);
+ if (ret) {
dev_warn(&pdev->dev, "USB PHY PLL calibrate not done after 100mS.");
- ret = -ETIMEDOUT;
goto err_clk;
}
- if (!wait_for_reg(base + PHY_28NM_RX_REG1,
- PHY_28NM_RX_SQCAL_DONE, HZ / 10)) {
+ ret = wait_for_reg(base + PHY_28NM_RX_REG1,
+ PHY_28NM_RX_SQCAL_DONE, 100);
+ if (ret) {
dev_warn(&pdev->dev, "USB PHY RX SQ calibrate not done after 100mS.");
- ret = -ETIMEDOUT;
goto err_clk;
}
/* Make sure PHY PLL is ready */
- if (!wait_for_reg(base + PHY_28NM_PLL_REG0,
- PHY_28NM_PLL_READY, HZ / 10)) {
+ ret = wait_for_reg(base + PHY_28NM_PLL_REG0, PHY_28NM_PLL_READY, 100);
+ if (ret) {
dev_warn(&pdev->dev, "PLL_READY not set after 100mS.");
- ret = -ETIMEDOUT;
goto err_clk;
}
--
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