From 1543e317f1da31b75942316931e8f491a8920811 Mon Sep 17 00:00:00 2001 From: hc <hc@nodka.com> Date: Thu, 04 Jan 2024 10:08:02 +0000 Subject: [PATCH] disable FB --- kernel/drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 354 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 files changed, 339 insertions(+), 15 deletions(-) diff --git a/kernel/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/kernel/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index 7fb5abb..a33f6fc 100644 --- a/kernel/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/kernel/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -1,15 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd * Author:Mark Yao <mark.yao@rock-chips.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _ROCKCHIP_VOP_REG_H @@ -1043,7 +1035,11 @@ #define PX30_GRF_PD_VO_CON1 0x00438 /* px30 register definition end */ +#define RV1106_VENC_GRF_VOP_IO_WRAPPER 0x1000c + #define RV1126_GRF_IOFUNC_CON3 0x1026c + +#define RK3562_GRF_IOC_VO_IO_CON 0x10500 /* rk3568 vop registers definition */ @@ -1058,16 +1054,22 @@ #define RK3568_DSP_IF_EN 0x028 #define RK3568_DSP_IF_CTRL 0x02c #define RK3568_DSP_IF_POL 0x030 +#define RK3568_SYS_PD_CTRL 0x034 +#define RK3588_SYS_VAR_FREQ_CTRL 0x038 #define RK3568_WB_CTRL 0x40 #define RK3568_WB_XSCAL_FACTOR 0x44 #define RK3568_WB_YRGB_MST 0x48 #define RK3568_WB_CBR_MST 0x4C -#define RK3568_OTP_WIN_EN 0x050 -#define RK3568_LUT_PORT_SEL 0x058 -#define RK3568_SYS_STATUS0 0x060 +#define RK3568_OTP_WIN_EN 0x50 +#define RK3568_LUT_PORT_SEL 0x58 +#define RK3568_SYS_STATUS0 0x60 +#define RK3568_SYS_STATUS1 0x64 +#define RK3568_SYS_STATUS2 0x68 +#define RK3568_SYS_STATUS3 0x6C #define RK3568_VP0_LINE_FLAG 0x70 #define RK3568_VP1_LINE_FLAG 0x74 #define RK3568_VP2_LINE_FLAG 0x78 +#define RK3588_VP3_LINE_FLAG 0x7C #define RK3568_SYS0_INT_EN 0x80 #define RK3568_SYS0_INT_CLR 0x84 #define RK3568_SYS0_INT_STATUS 0x88 @@ -1086,11 +1088,34 @@ #define RK3568_VP2_INT_CLR 0xC4 #define RK3568_VP2_INT_STATUS 0xC8 #define RK3568_VP2_INT_RAW_STATUS 0xCC +#define RK3588_VP3_INT_EN 0xD0 +#define RK3588_VP3_INT_CLR 0xD4 +#define RK3588_VP3_INT_STATUS 0xD8 + +#define RK3588_DSC_8K_SYS_CTRL 0x200 +#define RK3588_DSC_8K_RST 0x204 +#define RK3588_DSC_8K_CFG_DONE 0x208 +#define RK3588_DSC_8K_INIT_DLY 0x20C +#define RK3588_DSC_8K_HTOTAL_HS_END 0x210 +#define RK3588_DSC_8K_HACT_ST_END 0x214 +#define RK3588_DSC_8K_VTOTAL_VS_END 0x218 +#define RK3588_DSC_8K_VACT_ST_END 0x21C +#define RK3588_DSC_8K_STATUS 0x220 +#define RK3588_DSC_4K_SYS_CTRL 0x230 +#define RK3588_DSC_4K_RST 0x234 +#define RK3588_DSC_4K_CFG_DONE 0x238 +#define RK3588_DSC_4K_INIT_DLY 0x23C +#define RK3588_DSC_4K_HTOTAL_HS_END 0x240 +#define RK3588_DSC_4K_HACT_ST_END 0x244 +#define RK3588_DSC_4K_VTOTAL_VS_END 0x248 +#define RK3588_DSC_4K_VACT_ST_END 0x24C +#define RK3588_DSC_4K_STATUS 0x250 /* Video Port registers definition */ #define RK3568_VP0_DSP_CTRL 0xC00 -#define RK3568_VP0_MIPI_CTRL 0xC04 +#define RK3568_VP0_DUAL_CHANNEL_CTRL 0xC04 #define RK3568_VP0_COLOR_BAR_CTRL 0xC08 +#define RK3568_VP0_CLK_CTRL 0xC0C #define RK3568_VP0_3D_LUT_CTRL 0xC10 #define RK3568_VP0_3D_LUT_MST 0xC20 #define RK3568_VP0_DSP_BG 0xC2C @@ -1110,10 +1135,26 @@ #define RK3568_VP0_BCSH_BCS 0xC64 #define RK3568_VP0_BCSH_H 0xC68 #define RK3568_VP0_BCSH_COLOR_BAR 0xC6C +#define RK3562_VP0_MCU_CTRL 0xCF8 +#define RK3562_VP0_MCU_RW_BYPASS_PORT 0xCFC + +#define RK3528_VP0_ACM_CTRL 0xCD0 +#define RK3528_VP0_CSC_COE01_02 0xCD4 +#define RK3528_VP0_CSC_COE10_11 0xCD8 +#define RK3528_VP0_CSC_COE12_20 0xCDC +#define RK3528_VP0_CSC_COE21_22 0xCE0 +#define RK3528_VP0_CSC_OFFSET0 0xCE4 +#define RK3528_VP0_CSC_OFFSET1 0xCE8 +#define RK3528_VP0_CSC_OFFSET2 0xCEC +#define RK3528_VP0_MCU_CTRL 0xCF8 +#define RK3528_VP0_MCU_RW_BYPASS_PORT 0xCFC #define RK3568_VP1_DSP_CTRL 0xD00 -#define RK3568_VP1_MIPI_CTRL 0xD04 +#define RK3568_VP1_DUAL_CHANNEL_CTRL 0xD04 #define RK3568_VP1_COLOR_BAR_CTRL 0xD08 +#define RK3568_VP1_CLK_CTRL 0xD0C +#define RK3588_VP1_3D_LUT_CTRL 0xD10 +#define RK3588_VP1_3D_LUT_MST 0xD20 #define RK3568_VP1_DSP_BG 0xD2C #define RK3568_VP1_PRE_SCAN_HTIMING 0xD30 #define RK3568_VP1_POST_DSP_HACT_INFO 0xD34 @@ -1133,10 +1174,15 @@ #define RK3568_VP1_BCSH_BCS 0xD64 #define RK3568_VP1_BCSH_H 0xD68 #define RK3568_VP1_BCSH_COLOR_BAR 0xD6C +#define RK3562_VP1_MCU_CTRL 0xDF8 +#define RK3562_VP1_MCU_RW_BYPASS_PORT 0xDFC #define RK3568_VP2_DSP_CTRL 0xE00 -#define RK3568_VP2_MIPI_CTRL 0xE04 +#define RK3568_VP2_DUAL_CHANNEL_CTRL 0xE04 #define RK3568_VP2_COLOR_BAR_CTRL 0xE08 +#define RK3568_VP2_CLK_CTRL 0xE0C +#define RK3588_VP2_3D_LUT_CTRL 0xE10 +#define RK3588_VP2_3D_LUT_MST 0xE20 #define RK3568_VP2_DSP_BG 0xE2C #define RK3568_VP2_PRE_SCAN_HTIMING 0xE30 #define RK3568_VP2_POST_DSP_HACT_INFO 0xE34 @@ -1157,6 +1203,76 @@ #define RK3568_VP2_BCSH_H 0xE68 #define RK3568_VP2_BCSH_COLOR_BAR 0xE6C +#define RK3588_VP3_DSP_CTRL 0xF00 +#define RK3588_VP3_DUAL_CHANNEL_CTRL 0xF04 +#define RK3588_VP3_COLOR_BAR_CTRL 0xF08 +#define RK3568_VP3_CLK_CTRL 0xF0C +#define RK3588_VP3_DSP_BG 0xF2C +#define RK3588_VP3_PRE_SCAN_HTIMING 0xF30 +#define RK3588_VP3_POST_DSP_HACT_INFO 0xF34 +#define RK3588_VP3_POST_DSP_VACT_INFO 0xF38 +#define RK3588_VP3_POST_SCL_FACTOR_YRGB 0xF3C +#define RK3588_VP3_POST_SCL_CTRL 0xF40 +#define RK3588_VP3_DSP_HACT_INFO 0xF34 +#define RK3588_VP3_DSP_VACT_INFO 0xF38 +#define RK3588_VP3_POST_DSP_VACT_INFO_F1 0xF44 +#define RK3588_VP3_DSP_HTOTAL_HS_END 0xF48 +#define RK3588_VP3_DSP_HACT_ST_END 0xF4C +#define RK3588_VP3_DSP_VTOTAL_VS_END 0xF50 +#define RK3588_VP3_DSP_VACT_ST_END 0xF54 +#define RK3588_VP3_DSP_VS_ST_END_F1 0xF58 +#define RK3588_VP3_DSP_VACT_ST_END_F1 0xF5C +#define RK3588_VP3_BCSH_CTRL 0xF60 +#define RK3588_VP3_BCSH_BCS 0xF64 +#define RK3588_VP3_BCSH_H 0xF68 +#define RK3588_VP3_BCSH_COLOR_BAR 0xF6C +#define RK3528_OVL_SYS 0x500 +#define RK3528_OVL_SYS_PORT_SEL_IMD 0x504 +#define RK3528_OVL_SYS_GATING_EN_IMD 0x508 +#define RK3528_OVL_SYS_CLUSTER0_CTRL 0x510 +#define RK3528_OVL_SYS_ESMART0_CTRL 0x520 +#define RK3528_OVL_SYS_ESMART1_CTRL 0x524 +#define RK3528_OVL_SYS_ESMART2_CTRL 0x528 +#define RK3528_OVL_SYS_ESMART3_CTRL 0x52C +#define RK3528_CLUSTER0_MIX_SRC_COLOR_CTRL 0x530 +#define RK3528_CLUSTER0_MIX_DST_COLOR_CTRL 0x534 +#define RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x538 +#define RK3528_CLUSTER0_MIX_DST_ALPHA_CTRL 0x53c +#define RK3528_OVL_PORT0_CTRL 0x600 +#define RK3528_OVL_PORT0_LAYER_SEL 0x604 +#define RK3528_OVL_PORT0_MIX0_SRC_COLOR_CTRL 0x620 +#define RK3528_OVL_PORT0_MIX0_DST_COLOR_CTRL 0x624 +#define RK3528_OVL_PORT0_MIX0_SRC_ALPHA_CTRL 0x628 +#define RK3528_OVL_PORT0_MIX0_DST_ALPHA_CTRL 0x62C +#define RK3528_OVL_PORT0_MIX1_SRC_COLOR_CTRL 0x630 +#define RK3528_OVL_PORT0_MIX1_DST_COLOR_CTRL 0x634 +#define RK3528_OVL_PORT0_MIX1_SRC_ALPHA_CTRL 0x638 +#define RK3528_OVL_PORT0_MIX1_DST_ALPHA_CTRL 0x63C +#define RK3528_OVL_PORT0_MIX2_SRC_COLOR_CTRL 0x640 +#define RK3528_OVL_PORT0_MIX2_DST_COLOR_CTRL 0x644 +#define RK3528_OVL_PORT0_MIX2_SRC_ALPHA_CTRL 0x648 +#define RK3528_OVL_PORT0_MIX2_DST_ALPHA_CTRL 0x64C +#define RK3528_HDR_SRC_COLOR_CTRL 0x660 +#define RK3528_HDR_DST_COLOR_CTRL 0x664 +#define RK3528_HDR_SRC_ALPHA_CTRL 0x668 +#define RK3528_HDR_DST_ALPHA_CTRL 0x66C +#define RK3528_OVL_PORT0_BG_MIX_CTRL 0x670 +#define RK3528_OVL_PORT1_CTRL 0x700 +#define RK3528_OVL_PORT1_LAYER_SEL 0x704 +#define RK3528_OVL_PORT1_MIX0_SRC_COLOR_CTRL 0x720 +#define RK3528_OVL_PORT1_MIX0_DST_COLOR_CTRL 0x724 +#define RK3528_OVL_PORT1_MIX0_SRC_ALPHA_CTRL 0x728 +#define RK3528_OVL_PORT1_MIX0_DST_ALPHA_CTRL 0x72C +#define RK3528_OVL_PORT1_MIX1_SRC_COLOR_CTRL 0x730 +#define RK3528_OVL_PORT1_MIX1_DST_COLOR_CTRL 0x734 +#define RK3528_OVL_PORT1_MIX1_SRC_ALPHA_CTRL 0x738 +#define RK3528_OVL_PORT1_MIX1_DST_ALPHA_CTRL 0x73C +#define RK3528_OVL_PORT1_MIX2_SRC_COLOR_CTRL 0x740 +#define RK3528_OVL_PORT1_MIX2_DST_COLOR_CTRL 0x744 +#define RK3528_OVL_PORT1_MIX2_SRC_ALPHA_CTRL 0x748 +#define RK3528_OVL_PORT1_MIX2_DST_ALPHA_CTRL 0x74C +#define RK3528_OVL_PORT1_BG_MIX_CTRL 0x770 + /* Overlay registers definition */ #define RK3568_OVL_CTRL 0x600 #define RK3568_OVL_LAYER_SEL 0x604 @@ -1169,6 +1285,14 @@ #define RK3568_CLUSTER1_MIX_DST_COLOR_CTRL 0x624 #define RK3568_CLUSTER1_MIX_SRC_ALPHA_CTRL 0x628 #define RK3568_CLUSTER1_MIX_DST_ALPHA_CTRL 0x62C +#define RK3588_CLUSTER2_MIX_SRC_COLOR_CTRL 0x630 +#define RK3588_CLUSTER2_MIX_DST_COLOR_CTRL 0x634 +#define RK3588_CLUSTER2_MIX_SRC_ALPHA_CTRL 0x638 +#define RK3588_CLUSTER2_MIX_DST_ALPHA_CTRL 0x63C +#define RK3588_CLUSTER3_MIX_SRC_COLOR_CTRL 0x640 +#define RK3588_CLUSTER3_MIX_DST_COLOR_CTRL 0x644 +#define RK3588_CLUSTER3_MIX_SRC_ALPHA_CTRL 0x648 +#define RK3588_CLUSTER3_MIX_DST_ALPHA_CTRL 0x64C #define RK3568_MIX0_SRC_COLOR_CTRL 0x650 #define RK3568_MIX0_DST_COLOR_CTRL 0x654 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 @@ -1177,15 +1301,24 @@ #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC +#define RK3568_HDR1_SRC_COLOR_CTRL 0x6D0 +#define RK3568_HDR1_DST_COLOR_CTRL 0x6D4 +#define RK3568_HDR1_SRC_ALPHA_CTRL 0x6D8 +#define RK3568_HDR1_DST_ALPHA_CTRL 0x6DC #define RK3568_VP0_BG_MIX_CTRL 0x6E0 #define RK3568_VP1_BG_MIX_CTRL 0x6E4 #define RK3568_VP2_BG_MIX_CTRL 0x6E8 +#define RK3588_VP3_BG_MIX_CTRL 0x6EC #define RK3568_CLUSTER_DLY_NUM 0x6F0 +#define RK3568_CLUSTER_DLY_NUM1 0x6F4 #define RK3568_SMART_DLY_NUM 0x6F8 /* Cluster0 register definition */ #define RK3568_CLUSTER0_WIN0_CTRL0 0x1000 #define RK3568_CLUSTER0_WIN0_CTRL1 0x1004 +#define RK3528_CLUSTER0_WIN0_CTRL1 0x1004 +#define RK3528_CLUSTER0_WIN0_CTRL2 0x1008 +#define RK3568_CLUSTER0_WIN0_CTRL2 0x1008 #define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010 #define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014 #define RK3568_CLUSTER0_WIN0_VIR 0x1018 @@ -1205,6 +1338,8 @@ #define RK3568_CLUSTER0_WIN1_CTRL0 0x1080 #define RK3568_CLUSTER0_WIN1_CTRL1 0x1084 +#define RK3528_CLUSTER0_WIN1_CTRL1 0x1084 +#define RK3528_CLUSTER0_WIN1_CTRL2 0x1088 #define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090 #define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094 #define RK3568_CLUSTER0_WIN1_VIR 0x1098 @@ -1225,6 +1360,7 @@ #define RK3568_CLUSTER1_WIN0_CTRL0 0x1200 #define RK3568_CLUSTER1_WIN0_CTRL1 0x1204 +#define RK3568_CLUSTER1_WIN0_CTRL2 0x1208 #define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210 #define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214 #define RK3568_CLUSTER1_WIN0_VIR 0x1218 @@ -1262,9 +1398,90 @@ #define RK3568_CLUSTER1_CTRL 0x1300 +#define RK3588_CLUSTER2_WIN0_CTRL0 0x1400 +#define RK3588_CLUSTER2_WIN0_CTRL1 0x1404 +#define RK3588_CLUSTER2_WIN0_CTRL2 0x1408 +#define RK3588_CLUSTER2_WIN0_YRGB_MST 0x1410 +#define RK3588_CLUSTER2_WIN0_CBR_MST 0x1414 +#define RK3588_CLUSTER2_WIN0_VIR 0x1418 +#define RK3588_CLUSTER2_WIN0_ACT_INFO 0x1420 +#define RK3588_CLUSTER2_WIN0_DSP_INFO 0x1424 +#define RK3588_CLUSTER2_WIN0_DSP_ST 0x1428 +#define RK3588_CLUSTER2_WIN0_SCL_FACTOR_YRGB 0x1430 +#define RK3588_CLUSTER2_WIN0_AFBCD_TRANSFORM_OFFSET 0x143C +#define RK3588_CLUSTER2_WIN0_AFBCD_OUTPUT_CTRL 0x1450 +#define RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE 0x1454 +#define RK3588_CLUSTER2_WIN0_AFBCD_HDR_PTR 0x1458 +#define RK3588_CLUSTER2_WIN0_AFBCD_VIR_WIDTH 0x145C +#define RK3588_CLUSTER2_WIN0_AFBCD_PIC_SIZE 0x1460 +#define RK3588_CLUSTER2_WIN0_AFBCD_PIC_OFFSET 0x1464 +#define RK3588_CLUSTER2_WIN0_AFBCD_DSP_OFFSET 0x1468 +#define RK3588_CLUSTER2_WIN0_AFBCD_CTRL 0x146C + +#define RK3588_CLUSTER2_WIN1_CTRL0 0x1480 +#define RK3588_CLUSTER2_WIN1_CTRL1 0x1484 +#define RK3588_CLUSTER2_WIN1_YRGB_MST 0x1490 +#define RK3588_CLUSTER2_WIN1_CBR_MST 0x1494 +#define RK3588_CLUSTER2_WIN1_VIR 0x1498 +#define RK3588_CLUSTER2_WIN1_ACT_INFO 0x14A0 +#define RK3588_CLUSTER2_WIN1_DSP_INFO 0x14A4 +#define RK3588_CLUSTER2_WIN1_DSP_ST 0x14A8 +#define RK3588_CLUSTER2_WIN1_SCL_FACTOR_YRGB 0x14B0 +#define RK3588_CLUSTER2_WIN1_AFBCD_OUTPUT_CTRL 0x14D0 +#define RK3588_CLUSTER2_WIN1_AFBCD_ROTATE_MODE 0x14D4 +#define RK3588_CLUSTER2_WIN1_AFBCD_HDR_PTR 0x14D8 +#define RK3588_CLUSTER2_WIN1_AFBCD_VIR_WIDTH 0x14DC +#define RK3588_CLUSTER2_WIN1_AFBCD_PIC_SIZE 0x14E0 +#define RK3588_CLUSTER2_WIN1_AFBCD_PIC_OFFSET 0x14E4 +#define RK3588_CLUSTER2_WIN1_AFBCD_DSP_OFFSET 0x14E8 +#define RK3588_CLUSTER2_WIN1_AFBCD_CTRL 0x14EC + +#define RK3588_CLUSTER2_CTRL 0x1500 + +#define RK3588_CLUSTER3_WIN0_CTRL0 0x1600 +#define RK3588_CLUSTER3_WIN0_CTRL1 0x1604 +#define RK3588_CLUSTER3_WIN0_CTRL2 0x1608 +#define RK3588_CLUSTER3_WIN0_YRGB_MST 0x1610 +#define RK3588_CLUSTER3_WIN0_CBR_MST 0x1614 +#define RK3588_CLUSTER3_WIN0_VIR 0x1618 +#define RK3588_CLUSTER3_WIN0_ACT_INFO 0x1620 +#define RK3588_CLUSTER3_WIN0_DSP_INFO 0x1624 +#define RK3588_CLUSTER3_WIN0_DSP_ST 0x1628 +#define RK3588_CLUSTER3_WIN0_SCL_FACTOR_YRGB 0x1630 +#define RK3588_CLUSTER3_WIN0_AFBCD_TRANSFORM_OFFSET 0x163C +#define RK3588_CLUSTER3_WIN0_AFBCD_OUTPUT_CTRL 0x1650 +#define RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE 0x1654 +#define RK3588_CLUSTER3_WIN0_AFBCD_HDR_PTR 0x1658 +#define RK3588_CLUSTER3_WIN0_AFBCD_VIR_WIDTH 0x165C +#define RK3588_CLUSTER3_WIN0_AFBCD_PIC_SIZE 0x1660 +#define RK3588_CLUSTER3_WIN0_AFBCD_PIC_OFFSET 0x1664 +#define RK3588_CLUSTER3_WIN0_AFBCD_DSP_OFFSET 0x1668 +#define RK3588_CLUSTER3_WIN0_AFBCD_CTRL 0x166C + +#define RK3588_CLUSTER3_WIN1_CTRL0 0x1680 +#define RK3588_CLUSTER3_WIN1_CTRL1 0x1684 +#define RK3588_CLUSTER3_WIN1_YRGB_MST 0x1690 +#define RK3588_CLUSTER3_WIN1_CBR_MST 0x1694 +#define RK3588_CLUSTER3_WIN1_VIR 0x1698 +#define RK3588_CLUSTER3_WIN1_ACT_INFO 0x16A0 +#define RK3588_CLUSTER3_WIN1_DSP_INFO 0x16A4 +#define RK3588_CLUSTER3_WIN1_DSP_ST 0x16A8 +#define RK3588_CLUSTER3_WIN1_SCL_FACTOR_YRGB 0x16B0 +#define RK3588_CLUSTER3_WIN1_AFBCD_OUTPUT_CTRL 0x16D0 +#define RK3588_CLUSTER3_WIN1_AFBCD_ROTATE_MODE 0x16D4 +#define RK3588_CLUSTER3_WIN1_AFBCD_HDR_PTR 0x16D8 +#define RK3588_CLUSTER3_WIN1_AFBCD_VIR_WIDTH 0x16DC +#define RK3588_CLUSTER3_WIN1_AFBCD_PIC_SIZE 0x16E0 +#define RK3588_CLUSTER3_WIN1_AFBCD_PIC_OFFSET 0x16E4 +#define RK3588_CLUSTER3_WIN1_AFBCD_DSP_OFFSET 0x16E8 +#define RK3588_CLUSTER3_WIN1_AFBCD_CTRL 0x16EC + +#define RK3588_CLUSTER3_CTRL 0x1700 + /* Esmart register definition */ #define RK3568_ESMART0_CTRL0 0x1800 #define RK3568_ESMART0_CTRL1 0x1804 +#define RK3568_ESMART0_AXI_CTRL 0x1808 #define RK3568_ESMART0_REGION0_CTRL 0x1810 #define RK3568_ESMART0_REGION0_YRGB_MST 0x1814 #define RK3568_ESMART0_REGION0_CBR_MST 0x1818 @@ -1456,6 +1673,9 @@ #define RK3568_HDR_LUT_CTRL 0x2000 #define RK3568_HDR_LUT_MST 0x2004 #define RK3568_SDR2HDR_CTRL 0x2010 +/* for HDR10 controller1 */ +#define RK3568_SDR2HDR_CTRL1 0x2018 +#define RK3568_HDR2SDR_CTRL1 0x201C #define RK3568_HDR2SDR_CTRL 0x2020 #define RK3568_HDR2SDR_SRC_RANGE 0x2024 #define RK3568_HDR2SDR_NORMFACEETF 0x2028 @@ -1466,4 +1686,108 @@ #define RK3568_HDR_EOTF_OETF_Y0 0x20F0 #define RK3568_HDR_OETF_DX_POW1 0x2200 #define RK3568_HDR_OETF_XN1 0x2300 + +/* DSC register definition */ +#define RK3588_DSC_8K_PPS0_3 0x4000 +#define RK3588_DSC_8K_CTRL0 0x40A0 +#define RK3588_DSC_8K_CTRL1 0x40A4 +#define RK3588_DSC_8K_STS0 0x40A8 +#define RK3588_DSC_8K_ERS 0x40C4 + +#define RK3588_DSC_4K_PPS0_3 0x4100 +#define RK3588_DSC_4K_CTRL0 0x41A0 +#define RK3588_DSC_4K_CTRL1 0x41A4 +#define RK3588_DSC_4K_STS0 0x41A8 +#define RK3588_DSC_4K_ERS 0x41C4 + +#define RK3588_GRF_SOC_CON1 0x0304 +#define RK3588_GRF_VOP_CON2 0x08 +#define RK3588_GRF_VO1_CON0 0x00 + + +#define RK3588_PMU_PWR_GATE_CON1 0x150 +#define RK3588_PMU_SUBMEM_PWR_GATE_CON1 0x1B4 +#define RK3588_PMU_SUBMEM_PWR_GATE_CON2 0x1B8 +#define RK3588_PMU_SUBMEM_PWR_GATE_STATUS 0x1BC +#define RK3588_PMU_BISR_CON3 0x20C +#define RK3588_PMU_BISR_STATUS5 0x294 + +/* RK3528 HDR register definition */ +#define RK3528_HDR_LUT_CTRL 0x2000 +#define RK3528_HDR_LUT_MST 0x2004 +#define RK3528_HDR_LUT_STATUS 0x2008 +#define RK3528_SDR2HDR_CTRL 0x2010 +#define RK3528_SDR_CFG_COE0 0x2014 +#define RK3528_SDR_CFG_COE1 0x2018 +#define RK3528_SDR_CSC_COE00_01 0x201C +#define RK3528_SDR_CSC_COE02_10 0x2020 +#define RK3528_SDR_CSC_COE11_12 0x2024 +#define RK3528_SDR_CSC_COE20_21 0x2028 +#define RK3528_SDR_CSC_COE22 0x202C +#define RK3528_HDRVIVID_CTRL 0x2040 +#define RK3528_HDR_PQ_GAMMA 0x2044 +#define RK3528_HLG_RFIX_SCALEFAC 0x2048 +#define RK3528_HLG_MAXLUMA 0x204C +#define RK3528_HLG_R_TM_LIN2NON 0x2050 +#define RK3528_HDR_CSC_COE00_01 0x2054 +#define RK3528_HDR_CSC_COE02_10 0x2058 +#define RK3528_HDR_CSC_COE11_12 0x205C +#define RK3528_HDR_CSC_COE20_21 0x2060 +#define RK3528_HDR_CSC_COE22 0x2064 +#define RK3528_INK_CFG 0x2080 +#define RK3528_INK_POINT0_CFG 0x2084 +#define RK3528_INK_POINT1_CFG 0x2088 +#define RK3528_INK_POINT0_R0 0x208C +#define RK3528_INK_POINT0_G0 0x2090 +#define RK3528_INK_POINT0_B0 0x2094 +#define RK3528_INK_POINT0_R1 0x2098 +#define RK3528_INK_POINT0_G1 0x209C +#define RK3528_INK_POINT0_B1 0x20A0 +#define RK3528_INK_POINT1_R0 0x20A4 +#define RK3528_INK_POINT1_G0 0x20A8 +#define RK3528_INK_POINT1_B0 0x20AC +#define RK3528_INK_POINT1_R1 0x20B0 +#define RK3528_INK_POINT1_G1 0x20B4 +#define RK3528_INK_POINT1_B1 0x20B8 +#define RK3528_HDR_TONE_SCA 0x213C +#define RK3528_HDRGAMMA_CURVE 0x2540 +#define RK3528_HDRGAMMA_MDFVALUE 0x2690 +#define RK3528_SDRINVGAMMA_CURVE 0x2700 +#define RK3528_SDRINVGAMMA_STARTIDX 0x2820 +#define RK3528_SDRINVGAMMA_CHANGEIDX 0x2840 +#define RK3528_SDR_SMGAIN 0x2900 + +/* RK3588 ACM register definition */ +#define RK3528_ACM_CTRL 0x0000 +#define RK3528_ACM_ENABLE BIT(0) +#define RK3528_ACM_BYPASS BIT(1) +#define RK3528_ACM_DELTA_RANGE 0x0004 +#define RK3528_ACM_FETCH_START 0x0008 +#define RK3528_ACM_DEBUG_POINT0 0x0010 +#define RK3528_ACM_DEBUG_POINT1 0x0014 +#define RK3528_ACM_DEBUG_POINT2 0x0018 +#define RK3528_ACM_DEBUG_POINT3 0x001c +#define RK3528_ACM_FETCH_DONE 0x0020 +#define RK3528_ACM_DEBUG0_DATA0 0x0030 +#define RK3528_ACM_DEBUG0_DATA1 0x0034 +#define RK3528_ACM_DEBUG0_DATA2 0x0038 +#define RK3528_ACM_DEBUG0_DATA3 0x003c +#define RK3528_ACM_DEBUG1_DATA0 0x0040 +#define RK3528_ACM_DEBUG1_DATA1 0x0044 +#define RK3528_ACM_DEBUG1_DATA2 0x0048 +#define RK3528_ACM_DEBUG1_DATA3 0x004c +#define RK3528_ACM_DEBUG2_DATA0 0x0050 +#define RK3528_ACM_DEBUG2_DATA1 0x0054 +#define RK3528_ACM_DEBUG2_DATA2 0x0058 +#define RK3528_ACM_DEBUG2_DATA3 0x005c +#define RK3528_ACM_DEBUG3_DATA0 0x0060 +#define RK3528_ACM_DEBUG3_DATA1 0x0064 +#define RK3528_ACM_DEBUG3_DATA2 0x0068 +#define RK3528_ACM_DEBUG3_DATA3 0x006c +#define RK3528_ACM_YHS_DEL_HY_SEG0 0x0100 +#define RK3528_ACM_YHS_DEL_HY_SEG152 0x0360 +#define RK3528_ACM_YHS_DEL_HS_SEG0 0x0364 +#define RK3528_ACM_YHS_DEL_HS_SEG220 0x06d4 +#define RK3528_ACM_YHS_DEL_HGAIN_SEG0 0x06d8 +#define RK3528_ACM_YHS_DEL_HGAIN_SEG64 0x07d8 #endif /* _ROCKCHIP_VOP_REG_H */ -- Gitblit v1.6.2