From 1543e317f1da31b75942316931e8f491a8920811 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 04 Jan 2024 10:08:02 +0000
Subject: [PATCH] disable FB
---
kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 77 ++++++++++++++++++++------------------
1 files changed, 40 insertions(+), 37 deletions(-)
diff --git a/kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 296c866..b80ef0c 100644
--- a/kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -39,7 +39,6 @@
#ifdef CONFIG_DRM_ANALOGIX_DP
#include <drm/bridge/analogix_dp.h>
#endif
-#include <dt-bindings/soc/rockchip-system-status.h>
#include <soc/rockchip/rockchip_dmc.h>
#include <soc/rockchip/rockchip-system-status.h>
@@ -223,7 +222,6 @@
struct dentry *debugfs;
struct drm_info_list *debugfs_files;
struct drm_property *plane_feature_prop;
- struct drm_property *plane_mask_prop;
struct drm_property *feature_prop;
bool is_iommu_enabled;
@@ -238,7 +236,6 @@
u32 background;
u32 line_flag;
u8 id;
- u8 plane_mask;
u64 soc_id;
struct drm_prop_enum_list *plane_name_list;
@@ -318,6 +315,8 @@
{ MEDIA_BUS_FMT_UYYVYY8_0_5X24, "UYYVYY8_0_5X24" },
{ MEDIA_BUS_FMT_YUV10_1X30, "YUV10_1X30" },
{ MEDIA_BUS_FMT_UYYVYY10_0_5X30, "UYYVYY10_0_5X30" },
+ { MEDIA_BUS_FMT_RGB565_2X8_LE, "RGB565_2X8_LE" },
+ { MEDIA_BUS_FMT_RGB666_3X6, "RGB666_3X6" },
{ MEDIA_BUS_FMT_RGB888_3X8, "RGB888_3X8" },
{ MEDIA_BUS_FMT_RGB888_DUMMY_4X8, "RGB888_DUMMY_4X8" },
{ MEDIA_BUS_FMT_RGB888_1X24, "RGB888_1X24" },
@@ -463,6 +462,11 @@
const struct vop_hdr_table *table = vop->data->hdr_table;
uint32_t sdr2hdr_eotf_oetf_yn[65];
uint32_t sdr2hdr_oetf_dx_dxpow[64];
+
+ if (cmd != SDR2HDR_FOR_BT2020 && cmd != SDR2HDR_FOR_HDR && cmd != SDR2HDR_FOR_HLG_HDR) {
+ DRM_WARN("unknown sdr2hdr oetf: %d\n", cmd);
+ return;
+ }
for (i = 0; i < 65; i++) {
if (cmd == SDR2HDR_FOR_BT2020)
@@ -666,11 +670,13 @@
static bool is_rb_swap(uint32_t bus_format, uint32_t output_mode)
{
/*
- * The default component order of serial rgb3x8 formats
+ * The default component order of serial formats
* is BGR. So it is needed to enable RB swap.
*/
if (bus_format == MEDIA_BUS_FMT_RGB888_3X8 ||
- bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8)
+ bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8 ||
+ bus_format == MEDIA_BUS_FMT_RGB666_3X6 ||
+ bus_format == MEDIA_BUS_FMT_RGB565_2X8_LE)
return true;
else
return false;
@@ -1874,6 +1880,9 @@
if (!old_state->crtc)
return;
+ rockchip_drm_dbg(vop->dev, VOP_DEBUG_PLANE, "disable win%d-area%d by %s\n",
+ win->win_id, win->area_id, current->comm);
+
spin_lock(&vop->reg_lock);
vop_win_disable(vop, win);
@@ -1980,6 +1989,7 @@
uint32_t val;
bool rb_swap, global_alpha_en;
int is_yuv = fb->format->is_yuv;
+ struct drm_format_name_buf format_name;
#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
bool AFBC_flag = false;
@@ -2144,6 +2154,13 @@
VOP_WIN_SET(vop, win, enable, 1);
VOP_WIN_SET(vop, win, gate, 1);
spin_unlock(&vop->reg_lock);
+
+ drm_get_format_name(fb->format->format, &format_name);
+ rockchip_drm_dbg(vop->dev, VOP_DEBUG_PLANE,
+ "update win%d-area%d [%dx%d->%dx%d@(%d, %d)] zpos:%d fmt[%s%s] addr[%pad] by %s\n",
+ win->win_id, win->area_id, actual_w, actual_h,
+ dsp_w, dsp_h, dsp_stx, dsp_sty, vop_plane_state->zpos, format_name.str,
+ fb->modifier ? "[AFBC]" : "", &vop_plane_state->yrgb_mst, current->comm);
/*
* spi interface(vop_plane_state->yrgb_kvaddr, fb->pixel_format,
* actual_w, actual_h)
@@ -2325,7 +2342,7 @@
return;
__drm_atomic_helper_plane_reset(plane, &vop_plane_state->base);
- win->state.zpos = win->zpos;
+ vop_plane_state->base.zpos = win->zpos;
vop_plane_state->global_alpha = 0xff;
}
@@ -2514,7 +2531,7 @@
spin_unlock_irqrestore(&drm->event_lock, flags);
}
-static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
+static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on, void *data)
{
struct rockchip_drm_private *private = crtc->dev->dev_private;
struct vop *vop = to_vop(crtc);
@@ -3078,8 +3095,8 @@
{
struct vop *vop = to_vop(crtc);
const struct vop_data *vop_data = vop->data;
- struct rockchip_crtc_state *s =
- to_rockchip_crtc_state(crtc->state);
+ struct drm_crtc_state *new_crtc_state = container_of(mode, struct drm_crtc_state, mode);
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(new_crtc_state);
if (mode->hdisplay > vop_data->max_output.width)
return false;
@@ -3094,6 +3111,10 @@
(VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) >= 12 &&
s->output_if & VOP_OUTPUT_IF_BT656))
adj_mode->crtc_clock *= 2;
+
+ if (vop->mcu_timing.mcu_pix_total)
+ adj_mode->crtc_clock *= rockchip_drm_get_cycles_per_pixel(s->bus_format) *
+ (vop->mcu_timing.mcu_pix_total + 1);
adj_mode->crtc_clock =
DIV_ROUND_UP(clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000),
@@ -3118,12 +3139,14 @@
switch (s->bus_format) {
case MEDIA_BUS_FMT_RGB565_1X16:
+ case MEDIA_BUS_FMT_RGB565_2X8_LE:
VOP_CTRL_SET(vop, dither_down_en, 1);
VOP_CTRL_SET(vop, dither_down_mode, RGB888_TO_RGB565);
break;
case MEDIA_BUS_FMT_RGB666_1X18:
case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
+ case MEDIA_BUS_FMT_RGB666_3X6:
VOP_CTRL_SET(vop, dither_down_en, 1);
VOP_CTRL_SET(vop, dither_down_mode, RGB888_TO_RGB666);
break;
@@ -3239,6 +3262,12 @@
{
struct vop *vop = to_vop(crtc);
+ /*
+ * If mcu_hold_mode is 1, set 1 to mcu_frame_st will
+ * refresh one frame from ddr. So mcu_frame_st is needed
+ * to be initialized as 0.
+ */
+ VOP_CTRL_SET(vop, mcu_frame_st, 0);
VOP_CTRL_SET(vop, mcu_clk_sel, 1);
VOP_CTRL_SET(vop, mcu_type, 1);
@@ -4023,6 +4052,7 @@
spin_lock_irqsave(&vop->irq_lock, flags);
vop->pre_overlay = s->hdr.pre_overlay;
vop_cfg_done(vop);
+ rockchip_drm_dbg(vop->dev, VOP_DEBUG_CFG_DONE, "cfg_done\n\n");
/*
* rk322x and rk332x odd-even field will mistake when in interlace mode.
* we must switch to frame effect before switch screen and switch to
@@ -4388,6 +4418,7 @@
* frame effective, but actually it's effective immediately, so
* we config this register at frame start.
*/
+ rockchip_drm_dbg(vop->dev, VOP_DEBUG_VSYNC, "vsync\n");
spin_lock_irqsave(&vop->irq_lock, flags);
VOP_CTRL_SET(vop, level2_overlay_en, vop->pre_overlay);
VOP_CTRL_SET(vop, alpha_hard_calc, vop->pre_overlay);
@@ -4606,32 +4637,6 @@
return 0;
}
-static int vop_crtc_create_plane_mask_property(struct vop *vop, struct drm_crtc *crtc)
-{
- struct drm_property *prop;
-
- static const struct drm_prop_enum_list props[] = {
- { ROCKCHIP_VOP_WIN0, "Win0" },
- { ROCKCHIP_VOP_WIN1, "Win1" },
- { ROCKCHIP_VOP_WIN2, "Win2" },
- { ROCKCHIP_VOP_WIN3, "Win3" },
- };
-
- prop = drm_property_create_bitmask(vop->drm_dev,
- DRM_MODE_PROP_IMMUTABLE, "PLANE_MASK",
- props, ARRAY_SIZE(props),
- 0xffffffff);
- if (!prop) {
- DRM_DEV_ERROR(vop->dev, "create plane_mask prop for vp%d failed\n", vop->id);
- return -ENOMEM;
- }
-
- vop->plane_mask_prop = prop;
- drm_object_attach_property(&crtc->base, vop->plane_mask_prop, vop->plane_mask);
-
- return 0;
-}
-
static int vop_crtc_create_feature_property(struct vop *vop, struct drm_crtc *crtc)
{
const struct vop_data *vop_data = vop->data;
@@ -4759,7 +4764,6 @@
VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
#undef VOP_ATTACH_MODE_CONFIG_PROP
- vop_crtc_create_plane_mask_property(vop, crtc);
vop_crtc_create_feature_property(vop, crtc);
ret = drm_self_refresh_helper_init(crtc);
if (ret)
@@ -4928,7 +4932,6 @@
vop_area->name = devm_kstrdup(vop->dev, name, GFP_KERNEL);
num_wins++;
}
- vop->plane_mask |= BIT(vop_win->win_id);
}
vop->num_wins = num_wins;
--
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