From 1543e317f1da31b75942316931e8f491a8920811 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 04 Jan 2024 10:08:02 +0000
Subject: [PATCH] disable FB
---
kernel/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c | 31 +++++++++++++++----------------
1 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/kernel/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c b/kernel/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c
index d46c4e8..cbe7923 100644
--- a/kernel/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c
+++ b/kernel/drivers/gpu/drm/rockchip/rk628/rk628_combtxphy.c
@@ -90,7 +90,6 @@
struct clk *pclk;
struct clk *ref_clk;
struct reset_control *rstc;
- enum phy_mode mode;
unsigned int flags;
u16 frac_div;
@@ -229,10 +228,12 @@
return 0;
}
+EXPORT_SYMBOL(rk628_combtxphy_set_gvi_division_mode);
static int rk628_combtxphy_power_on(struct phy *phy)
{
struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
+ enum phy_mode mode = phy_get_mode(phy);
clk_prepare_enable(combtxphy->pclk);
reset_control_assert(combtxphy->rstc);
@@ -247,24 +248,22 @@
SW_TX_IDLE_MASK | SW_TX_PD_MASK | SW_PD_PLL_MASK,
SW_TX_IDLE(0x3ff) | SW_TX_PD(0x3ff) | SW_PD_PLL);
- switch (combtxphy->mode) {
- case PHY_MODE_VIDEO_MIPI:
+ switch (mode) {
+ case PHY_MODE_MIPI_DPHY:
regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
SW_TXPHY_REFCLK_SEL_MASK,
SW_TXPHY_REFCLK_SEL(0));
return rk628_combtxphy_dsi_power_on(combtxphy);
- case PHY_MODE_VIDEO_LVDS:
+ case PHY_MODE_LVDS:
regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
SW_TXPHY_REFCLK_SEL_MASK,
SW_TXPHY_REFCLK_SEL(1));
return rk628_combtxphy_lvds_power_on(combtxphy);
- case PHY_MODE_GVI:
+ default:
regmap_update_bits(combtxphy->grf, GRF_POST_PROC_CON,
SW_TXPHY_REFCLK_SEL_MASK,
SW_TXPHY_REFCLK_SEL(2));
return rk628_combtxphy_gvi_power_on(combtxphy);
- default:
- return -EINVAL;
}
return 0;
@@ -284,7 +283,8 @@
return 0;
}
-static int rk628_combtxphy_set_mode(struct phy *phy, enum phy_mode mode)
+static int rk628_combtxphy_set_mode(struct phy *phy, enum phy_mode mode,
+ int submode)
{
struct rk628_combtxphy *combtxphy = phy_get_drvdata(phy);
unsigned int bus_width = phy_get_bus_width(phy);
@@ -292,7 +292,7 @@
unsigned long fvco, fpfd;
switch (mode) {
- case PHY_MODE_VIDEO_MIPI:
+ case PHY_MODE_MIPI_DPHY:
{
unsigned int fhsc = bus_width >> 8;
unsigned int flags = bus_width & 0xff;
@@ -330,7 +330,7 @@
phy_set_bus_width(phy, fhsc);
break;
}
- case PHY_MODE_VIDEO_LVDS:
+ case PHY_MODE_LVDS:
{
unsigned int flags = bus_width & 0xff;
unsigned int rate = (bus_width >> 8) * 7;
@@ -348,7 +348,7 @@
combtxphy->rate_div = 1;
break;
}
- case PHY_MODE_GVI:
+ default:
{
unsigned int i, delta_freq, best_delta_freq, fb_div;
unsigned long ref_clk;
@@ -366,6 +366,10 @@
ref_clk = clk_get_rate(combtxphy->ref_clk) / 1000; /* khz */
if (combtxphy->division_mode)
ref_clk /= 2;
+
+ if (!ref_clk)
+ return -EINVAL;
+
/*
* the reference clock at PFD(FPFD = ref_clk / ref_div) about
* 25MHz is recommende, FPFD must range from 16MHz to 35MHz,
@@ -399,14 +403,9 @@
combtxphy->fb_div = fb_div;
phy_set_bus_width(phy, bus_width);
-
break;
}
- default:
- return -EINVAL;
}
-
- combtxphy->mode = mode;
return 0;
}
--
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