From 1543e317f1da31b75942316931e8f491a8920811 Mon Sep 17 00:00:00 2001 From: hc <hc@nodka.com> Date: Thu, 04 Jan 2024 10:08:02 +0000 Subject: [PATCH] disable FB --- kernel/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 117 ++++++++++++++++++++++------------------------------------ 1 files changed, 45 insertions(+), 72 deletions(-) diff --git a/kernel/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/kernel/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h index b7d3137..71e476b 100644 --- a/kernel/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h +++ b/kernel/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h @@ -1,10 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (C) 2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. */ #ifndef __DW_HDMI_H__ @@ -162,13 +158,6 @@ #define HDMI_FC_SPDDEVICEINF 0x1062 #define HDMI_FC_AUDSCONF 0x1063 #define HDMI_FC_AUDSSTAT 0x1064 -#define HDMI_FC_AUDSCHNLS0 0x1067 -#define HDMI_FC_AUDSCHNLS1 0x1068 -#define HDMI_FC_AUDSCHNLS2 0x1069 -#define HDMI_FC_AUDSCHNLS3 0x106a -#define HDMI_FC_AUDSCHNLS4 0x106b -#define HDMI_FC_AUDSCHNLS5 0x106c -#define HDMI_FC_AUDSCHNLS6 0x106d #define HDMI_FC_AUDSCHNLS7 0x106e #define HDMI_FC_AUDSCHNLS8 0x106f #define HDMI_FC_DATACH0FILL 0x1070 @@ -265,7 +254,7 @@ #define HDMI_FC_POL2 0x10DB #define HDMI_FC_PRCONF 0x10E0 #define HDMI_FC_SCRAMBLER_CTRL 0x10E1 -#define HDMI_FC_PACKET_TX_EN 0x10E3 +#define HDMI_FC_PACKET_TX_EN 0x10E3 #define HDMI_FC_GMD_STAT 0x1100 #define HDMI_FC_GMD_EN 0x1101 @@ -301,36 +290,36 @@ #define HDMI_FC_GMD_PB26 0x111F #define HDMI_FC_GMD_PB27 0x1120 -#define HDMI_FC_DRM_UP 0x1167 -#define HDMI_FC_DRM_HB0 0x1168 -#define HDMI_FC_DRM_HB1 0x1169 -#define HDMI_FC_DRM_PB0 0x116a -#define HDMI_FC_DRM_PB1 0x116b -#define HDMI_FC_DRM_PB2 0x116c -#define HDMI_FC_DRM_PB3 0x116d -#define HDMI_FC_DRM_PB4 0x116e -#define HDMI_FC_DRM_PB5 0x116f -#define HDMI_FC_DRM_PB6 0x1170 -#define HDMI_FC_DRM_PB7 0x1171 -#define HDMI_FC_DRM_PB8 0x1172 -#define HDMI_FC_DRM_PB9 0x1173 -#define HDMI_FC_DRM_PB10 0x1174 -#define HDMI_FC_DRM_PB11 0x1175 -#define HDMI_FC_DRM_PB12 0x1176 -#define HDMI_FC_DRM_PB13 0x1177 -#define HDMI_FC_DRM_PB14 0x1178 -#define HDMI_FC_DRM_PB15 0x1179 -#define HDMI_FC_DRM_PB16 0x117a -#define HDMI_FC_DRM_PB17 0x117b -#define HDMI_FC_DRM_PB18 0x117c -#define HDMI_FC_DRM_PB19 0x117d -#define HDMI_FC_DRM_PB20 0x117e -#define HDMI_FC_DRM_PB21 0x117f -#define HDMI_FC_DRM_PB22 0x1180 -#define HDMI_FC_DRM_PB23 0x1181 -#define HDMI_FC_DRM_PB24 0x1182 -#define HDMI_FC_DRM_PB25 0x1183 -#define HDMI_FC_DRM_PB26 0x1184 +#define HDMI_FC_DRM_UP 0x1167 +#define HDMI_FC_DRM_HB0 0x1168 +#define HDMI_FC_DRM_HB1 0x1169 +#define HDMI_FC_DRM_PB0 0x116A +#define HDMI_FC_DRM_PB1 0x116B +#define HDMI_FC_DRM_PB2 0x116C +#define HDMI_FC_DRM_PB3 0x116D +#define HDMI_FC_DRM_PB4 0x116E +#define HDMI_FC_DRM_PB5 0x116F +#define HDMI_FC_DRM_PB6 0x1170 +#define HDMI_FC_DRM_PB7 0x1171 +#define HDMI_FC_DRM_PB8 0x1172 +#define HDMI_FC_DRM_PB9 0x1173 +#define HDMI_FC_DRM_PB10 0x1174 +#define HDMI_FC_DRM_PB11 0x1175 +#define HDMI_FC_DRM_PB12 0x1176 +#define HDMI_FC_DRM_PB13 0x1177 +#define HDMI_FC_DRM_PB14 0x1178 +#define HDMI_FC_DRM_PB15 0x1179 +#define HDMI_FC_DRM_PB16 0x117A +#define HDMI_FC_DRM_PB17 0x117B +#define HDMI_FC_DRM_PB18 0x117C +#define HDMI_FC_DRM_PB19 0x117D +#define HDMI_FC_DRM_PB20 0x117E +#define HDMI_FC_DRM_PB21 0x117F +#define HDMI_FC_DRM_PB22 0x1180 +#define HDMI_FC_DRM_PB23 0x1181 +#define HDMI_FC_DRM_PB24 0x1182 +#define HDMI_FC_DRM_PB25 0x1183 +#define HDMI_FC_DRM_PB26 0x1184 #define HDMI_FC_DBGFORCE 0x1200 #define HDMI_FC_DBGAUD0CH0 0x1201 @@ -807,23 +796,12 @@ /* HDMI_FC_AUDSCHNLS7 field values */ HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30, - HDMI_FC_AUDSCHNLS7_SAMPFREQ_OFFSET = 0, - HDMI_FC_AUDSCHNLS7_SAMPFREQ_MASK = 0x0f, /* HDMI_FC_AUDSCHNLS8 field values */ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4, HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f, HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0, - -/* HDMI_FC_AUDSCHNLS Sample Rate */ - HDMI_FC_AUDSCHNLS_32K = 0x3, - HDMI_FC_AUDSCHNLS_441K = 0x0, - HDMI_FC_AUDSCHNLS_48K = 0x2, - HDMI_FC_AUDSCHNLS_882K = 0x8, - HDMI_FC_AUDSCHNLS_96K = 0xa, - HDMI_FC_AUDSCHNLS_1764K = 0xc, - HDMI_FC_AUDSCHNLS_192K = 0xe, /* FC_AUDSCONF field values */ HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0, @@ -855,9 +833,9 @@ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0, /* FC_PACKET_TX_EN field values */ - HDMI_FC_PACKET_DRM_TX_EN_MASK = 0x80, - HDMI_FC_PACKET_DRM_TX_EN = 0x80, - HDMI_FC_PACKET_DRM_TX_DEN = 0x00, + HDMI_FC_PACKET_TX_EN_DRM_MASK = 0x80, + HDMI_FC_PACKET_TX_EN_DRM_ENABLE = 0x80, + HDMI_FC_PACKET_TX_EN_DRM_DISABLE = 0x00, /* FC_AVICONF0-FC_AVICONF3 field values */ HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, @@ -986,21 +964,18 @@ /* AUD_CONF0 field values */ HDMI_AUD_CONF0_SW_RESET = 0x80, - HDMI_AUD_CONF0_I2S_SELECT_MASK = 0x20, - HDMI_AUD_CONF0_I2S_2CHANNEL_ENABLE = 0x21, - HDMI_AUD_CONF0_I2S_4CHANNEL_ENABLE = 0x23, - HDMI_AUD_CONF0_I2S_6CHANNEL_ENABLE = 0x27, - HDMI_AUD_CONF0_I2S_8CHANNEL_ENABLE = 0x2F, - HDMI_AUD_CONF0_I2S_ALL_ENABLE = 0x2F, - -/* AUD_INT field values */ - HDMI_AUD_INT_FIFO_EMPTY_MSK = BIT(3), - HDMI_AUD_INT_FIFO_FULL_MSK = BIT(2), + HDMI_AUD_CONF0_I2S_SELECT = 0x20, + HDMI_AUD_CONF0_I2S_EN3 = 0x08, + HDMI_AUD_CONF0_I2S_EN2 = 0x04, + HDMI_AUD_CONF0_I2S_EN1 = 0x02, + HDMI_AUD_CONF0_I2S_EN0 = 0x01, /* AUD_CONF1 field values */ HDMI_AUD_CONF1_MODE_I2S = 0x00, - HDMI_AUD_CONF1_MODE_RIGHT_J = 0x02, - HDMI_AUD_CONF1_MODE_LEFT_J = 0x04, + HDMI_AUD_CONF1_MODE_RIGHT_J = 0x20, + HDMI_AUD_CONF1_MODE_LEFT_J = 0x40, + HDMI_AUD_CONF1_MODE_BURST_1 = 0x60, + HDMI_AUD_CONF1_MODE_BURST_2 = 0x80, HDMI_AUD_CONF1_WIDTH_16 = 0x10, HDMI_AUD_CONF1_WIDTH_21 = 0x15, HDMI_AUD_CONF1_WIDTH_24 = 0x18, @@ -1074,6 +1049,7 @@ HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, /* MC_SWRSTZ field values */ + HDMI_MC_SWRSTZ_I2SSWRST_REQ = 0x08, HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, /* MC_FLOWCTRL field values */ @@ -1183,9 +1159,6 @@ HDMI_I2CM_DIV_FAST_STD_MODE = 0x8, HDMI_I2CM_DIV_FAST_MODE = 0x8, HDMI_I2CM_DIV_STD_MODE = 0, - -/* HDMI_MC_SWRSTZ filed values */ - HDMI_MC_SWRSTZ_I2S_RESET_MSK = BIT(3), }; /* -- Gitblit v1.6.2