From 1543e317f1da31b75942316931e8f491a8920811 Mon Sep 17 00:00:00 2001 From: hc <hc@nodka.com> Date: Thu, 04 Jan 2024 10:08:02 +0000 Subject: [PATCH] disable FB --- kernel/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h | 17 ++++++++++++++++- 1 files changed, 16 insertions(+), 1 deletions(-) diff --git a/kernel/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h b/kernel/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h index 225bfaa..e9b5e19 100644 --- a/kernel/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h +++ b/kernel/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h @@ -13,6 +13,7 @@ #define CONFIG_REG 0xc #define CONFIG_CEC BIT(28) #define CONFIG_AUD_UD BIT(23) +#define CONFIG_HDCP14 BIT(8) #define CORE_TIMESTAMP_HHMM 0x14 #define CORE_TIMESTAMP_MMDD 0x18 #define CORE_TIMESTAMP_YYYY 0x1c @@ -139,7 +140,7 @@ #define FRAME_COMPOSER_CONFIG8 0x860 #define FRAME_COMPOSER_CONFIG9 0x864 #define KEEPOUT_REKEY_CFG GENMASK(9, 8) -#define KEEPOUT_REKEY_ALWAYS 0x2 +#define KEEPOUT_REKEY_ALWAYS (0x2 << 8) #define FRAME_COMPOSER_CONTROL0 0x86c /* Video Monitor Registers */ #define VIDEO_MONITOR_CONFIG0 0x880 @@ -155,9 +156,13 @@ #define HDCP2_BYPASS BIT(0) #define HDCP2LOGIC_ESM_GPIO_IN 0x8e4 #define HDCP2LOGIC_ESM_GPIO_OUT 0x8e8 +#define HDCP2_AUTHENTICATION_SUCCESS BIT(6) /* HDCP14 Registers */ #define HDCP14_CONFIG0 0x900 +#define HDCP14_OESS_ESSS_OVR_VALUE BIT(14) +#define HDCP14_OESS_ESSS_OVR_EN BIT(13) #define HDCP14_CONFIG1 0x904 +#define HDCP14_SHA1_MSG_CORRECT_P BIT(3) #define HDCP14_CONFIG2 0x908 #define HDCP14_CONFIG3 0x90c #define HDCP14_KEY_SEED 0x914 @@ -169,7 +174,10 @@ #define HDCP14_AN_H 0x92c #define HDCP14_AN_L 0x930 #define HDCP14_STATUS0 0x934 +#define HDCP14_RPT_DEVICE_COUNT 0xFE00 #define HDCP14_STATUS1 0x938 +#define HDCP14_RCV_REPEATER BIT(6) +#define HDCP14_RCV_KSV_FIFO_READY BIT(5) /* Scrambler Registers */ #define SCRAMB_CONFIG0 0x960 /* Video Configuration Registers */ @@ -792,6 +800,7 @@ #define AVP_1_INT_STATUS 0x3820 #define AVP_1_INT_MASK_N 0x3824 #define HDCP14_AUTH_CHG_MASK_N BIT(6) +#define HDCP14_KSV_LIST_DONE_MASK_N BIT(1) #define AVP_1_INT_CLEAR 0x3828 #define AVP_1_INT_FORCE 0x382c #define AVP_2_INT_STATUS 0x3830 @@ -802,6 +811,7 @@ #define AVP_3_INT_MASK_N 0x3844 #define AVP_3_INT_CLEAR 0x3848 #define AVP_3_INT_FORCE 0x384c +#define HDCP2_ESM_P0_GPIO_OUT_2_CHG_IRQ BIT(17) #define AVP_4_INT_STATUS 0x3850 #define AVP_4_INT_MASK_N 0x3854 #define AVP_4_INT_CLEAR 0x3858 @@ -832,4 +842,9 @@ #define EARCRX_1_INT_CLEAR 0x4828 #define EARCRX_1_INT_FORCE 0x482c +#define HDMI_HDCP14_MEM_KSV0 0x4f08 +#define HDMI_HDCP14_MEM_BSTATUS0 0x5958 +#define HDMI_HDCP14_MEM_M0_1 0x5960 +#define HDMI_HDCP14_MEM_M0_7 0x597c + #endif /* __DW_HDMI_QP_H__ */ -- Gitblit v1.6.2