From 1543e317f1da31b75942316931e8f491a8920811 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 04 Jan 2024 10:08:02 +0000
Subject: [PATCH] disable FB
---
kernel/drivers/gpu/drm/armada/armada_crtc.c | 249 +++++++++++++++++++++++++++++++++++++++++++------
1 files changed, 217 insertions(+), 32 deletions(-)
diff --git a/kernel/drivers/gpu/drm/armada/armada_crtc.c b/kernel/drivers/gpu/drm/armada/armada_crtc.c
index da93606..a887b6a 100644
--- a/kernel/drivers/gpu/drm/armada/armada_crtc.c
+++ b/kernel/drivers/gpu/drm/armada/armada_crtc.c
@@ -1,20 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Russell King
* Rewritten from the dovefb driver, and Armada510 manuals.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
+
#include <linux/clk.h>
#include <linux/component.h>
+#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
-#include <drm/drmP.h>
+
#include <drm/drm_atomic.h>
-#include <drm/drm_crtc_helper.h>
-#include <drm/drm_plane_helper.h>
#include <drm/drm_atomic_helper.h>
+#include <drm/drm_plane_helper.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_vblank.h>
+
#include "armada_crtc.h"
#include "armada_drm.h"
#include "armada_fb.h"
@@ -130,6 +131,70 @@
}
}
+static void armada_drm_update_gamma(struct drm_crtc *crtc)
+{
+ struct drm_property_blob *blob = crtc->state->gamma_lut;
+ void __iomem *base = drm_to_armada_crtc(crtc)->base;
+ int i;
+
+ if (blob) {
+ struct drm_color_lut *lut = blob->data;
+
+ armada_updatel(CFG_CSB_256x8, CFG_CSB_256x8 | CFG_PDWN256x8,
+ base + LCD_SPU_SRAM_PARA1);
+
+ for (i = 0; i < 256; i++) {
+ writel_relaxed(drm_color_lut_extract(lut[i].red, 8),
+ base + LCD_SPU_SRAM_WRDAT);
+ writel_relaxed(i | SRAM_WRITE | SRAM_GAMMA_YR,
+ base + LCD_SPU_SRAM_CTRL);
+ readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
+ writel_relaxed(drm_color_lut_extract(lut[i].green, 8),
+ base + LCD_SPU_SRAM_WRDAT);
+ writel_relaxed(i | SRAM_WRITE | SRAM_GAMMA_UG,
+ base + LCD_SPU_SRAM_CTRL);
+ readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
+ writel_relaxed(drm_color_lut_extract(lut[i].blue, 8),
+ base + LCD_SPU_SRAM_WRDAT);
+ writel_relaxed(i | SRAM_WRITE | SRAM_GAMMA_VB,
+ base + LCD_SPU_SRAM_CTRL);
+ readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
+ }
+ armada_updatel(CFG_GAMMA_ENA, CFG_GAMMA_ENA,
+ base + LCD_SPU_DMA_CTRL0);
+ } else {
+ armada_updatel(0, CFG_GAMMA_ENA, base + LCD_SPU_DMA_CTRL0);
+ armada_updatel(CFG_PDWN256x8, CFG_CSB_256x8 | CFG_PDWN256x8,
+ base + LCD_SPU_SRAM_PARA1);
+ }
+}
+
+static enum drm_mode_status armada_drm_crtc_mode_valid(struct drm_crtc *crtc,
+ const struct drm_display_mode *mode)
+{
+ struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
+
+ if (mode->vscan > 1)
+ return MODE_NO_VSCAN;
+
+ if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
+ return MODE_NO_DBLESCAN;
+
+ if (mode->flags & DRM_MODE_FLAG_HSKEW)
+ return MODE_H_ILLEGAL;
+
+ /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
+ if (!dcrtc->variant->has_spu_adv_reg &&
+ mode->flags & DRM_MODE_FLAG_INTERLACE)
+ return MODE_NO_INTERLACE;
+
+ if (mode->flags & (DRM_MODE_FLAG_BCAST | DRM_MODE_FLAG_PIXMUX |
+ DRM_MODE_FLAG_CLKDIV2))
+ return MODE_BAD;
+
+ return MODE_OK;
+}
+
/* The mode_config.mutex will be held for this call */
static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
const struct drm_display_mode *mode, struct drm_display_mode *adj)
@@ -137,9 +202,18 @@
struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
int ret;
- /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
- if (!dcrtc->variant->has_spu_adv_reg &&
- adj->flags & DRM_MODE_FLAG_INTERLACE)
+ /*
+ * Set CRTC modesetting parameters for the adjusted mode. This is
+ * applied after the connectors, bridges, and encoders have fixed up
+ * this mode, as described above drm_atomic_helper_check_modeset().
+ */
+ drm_mode_set_crtcinfo(adj, CRTC_INTERLACE_HALVE_V);
+
+ /*
+ * Validate the adjusted mode in case an encoder/bridge has set
+ * something we don't support.
+ */
+ if (armada_drm_crtc_mode_valid(crtc, adj) != MODE_OK)
return false;
/* Check whether the display mode is possible */
@@ -270,13 +344,7 @@
tm = adj->crtc_vtotal - adj->crtc_vsync_end;
DRM_DEBUG_KMS("[CRTC:%d:%s] mode " DRM_MODE_FMT "\n",
- crtc->base.id, crtc->name,
- adj->base.id, adj->name, adj->vrefresh, adj->clock,
- adj->crtc_hdisplay, adj->crtc_hsync_start,
- adj->crtc_hsync_end, adj->crtc_htotal,
- adj->crtc_vdisplay, adj->crtc_vsync_start,
- adj->crtc_vsync_end, adj->crtc_vtotal,
- adj->type, adj->flags);
+ crtc->base.id, crtc->name, DRM_MODE_ARG(adj));
DRM_DEBUG_KMS("lm %d rm %d tm %d bm %d\n", lm, rm, tm, bm);
/* Now compute the divider for real */
@@ -284,16 +352,9 @@
armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
- if (interlaced ^ dcrtc->interlaced) {
- if (adj->flags & DRM_MODE_FLAG_INTERLACE)
- drm_crtc_vblank_get(&dcrtc->crtc);
- else
- drm_crtc_vblank_put(&dcrtc->crtc);
- dcrtc->interlaced = interlaced;
- }
-
spin_lock_irqsave(&dcrtc->irq_lock, flags);
+ dcrtc->interlaced = interlaced;
/* Even interlaced/progressive frame */
dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
adj->crtc_htotal;
@@ -351,12 +412,29 @@
spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
}
+static int armada_drm_crtc_atomic_check(struct drm_crtc *crtc,
+ struct drm_crtc_state *state)
+{
+ DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
+
+ if (state->gamma_lut && drm_color_lut_size(state->gamma_lut) != 256)
+ return -EINVAL;
+
+ if (state->color_mgmt_changed)
+ state->planes_changed = true;
+
+ return 0;
+}
+
static void armada_drm_crtc_atomic_begin(struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state)
{
struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
+
+ if (crtc->state->color_mgmt_changed)
+ armada_drm_update_gamma(crtc);
dcrtc->regs_idx = 0;
dcrtc->regs = dcrtc->atomic_regs;
@@ -395,6 +473,9 @@
struct drm_pending_vblank_event *event;
DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
+
+ if (old_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ drm_crtc_vblank_put(crtc);
drm_crtc_vblank_off(crtc);
armada_drm_crtc_update(dcrtc, false);
@@ -440,12 +521,17 @@
armada_drm_crtc_update(dcrtc, true);
drm_crtc_vblank_on(crtc);
+ if (crtc->state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ WARN_ON(drm_crtc_vblank_get(crtc));
+
armada_drm_crtc_queue_state_event(crtc);
}
static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
+ .mode_valid = armada_drm_crtc_mode_valid,
.mode_fixup = armada_drm_crtc_mode_fixup,
.mode_set_nofb = armada_drm_crtc_mode_set_nofb,
+ .atomic_check = armada_drm_crtc_atomic_check,
.atomic_begin = armada_drm_crtc_atomic_begin,
.atomic_flush = armada_drm_crtc_atomic_flush,
.atomic_disable = armada_drm_crtc_atomic_disable,
@@ -466,6 +552,13 @@
for (x = 0; x < width; x++, p++) {
uint32_t val = *p;
+ /*
+ * In "ARGB888" (HWC32) mode, writing to the SRAM
+ * requires these bits to contain:
+ * 31:24 = alpha 23:16 = blue 15:8 = green 7:0 = red
+ * So, it's actually ABGR8888. This is independent
+ * of the SWAPRB bits in DMA control register 0.
+ */
val = (val & 0xff00ff00) |
(val & 0x000000ff) << 16 |
(val & 0x00ff0000) >> 16;
@@ -617,13 +710,13 @@
/* Must be a kernel-mapped object */
if (!obj->addr) {
- drm_gem_object_put_unlocked(&obj->obj);
+ drm_gem_object_put(&obj->obj);
return -EINVAL;
}
if (obj->obj.size < w * h * 4) {
DRM_ERROR("buffer is too small\n");
- drm_gem_object_put_unlocked(&obj->obj);
+ drm_gem_object_put(&obj->obj);
return -ENOMEM;
}
}
@@ -631,7 +724,7 @@
if (dcrtc->cursor_obj) {
dcrtc->cursor_obj->update = NULL;
dcrtc->cursor_obj->update_data = NULL;
- drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj);
+ drm_gem_object_put(&dcrtc->cursor_obj->obj);
}
dcrtc->cursor_obj = obj;
dcrtc->cursor_w = w;
@@ -664,10 +757,10 @@
static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
{
struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
- struct armada_private *priv = crtc->dev->dev_private;
+ struct armada_private *priv = drm_to_armada_dev(crtc->dev);
if (dcrtc->cursor_obj)
- drm_gem_object_put_unlocked(&dcrtc->cursor_obj->obj);
+ drm_gem_object_put(&dcrtc->cursor_obj->obj);
priv->dcrtc[dcrtc->num] = NULL;
drm_crtc_cleanup(&dcrtc->crtc);
@@ -680,6 +773,14 @@
of_node_put(dcrtc->crtc.port);
kfree(dcrtc);
+}
+
+static int armada_drm_crtc_late_register(struct drm_crtc *crtc)
+{
+ if (IS_ENABLED(CONFIG_DEBUG_FS))
+ armada_drm_crtc_debugfs_init(drm_to_armada_crtc(crtc));
+
+ return 0;
}
/* These are called under the vbl_lock. */
@@ -709,19 +810,98 @@
.cursor_set = armada_drm_crtc_cursor_set,
.cursor_move = armada_drm_crtc_cursor_move,
.destroy = armada_drm_crtc_destroy,
+ .gamma_set = drm_atomic_helper_legacy_gamma_set,
.set_config = drm_atomic_helper_set_config,
.page_flip = drm_atomic_helper_page_flip,
.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
+ .late_register = armada_drm_crtc_late_register,
.enable_vblank = armada_drm_crtc_enable_vblank,
.disable_vblank = armada_drm_crtc_disable_vblank,
};
+
+int armada_crtc_select_clock(struct armada_crtc *dcrtc,
+ struct armada_clk_result *res,
+ const struct armada_clocking_params *params,
+ struct clk *clks[], size_t num_clks,
+ unsigned long desired_khz)
+{
+ unsigned long desired_hz = desired_khz * 1000;
+ unsigned long desired_clk_hz; // requested clk input
+ unsigned long real_clk_hz; // actual clk input
+ unsigned long real_hz; // actual pixel clk
+ unsigned long permillage;
+ struct clk *clk;
+ u32 div;
+ int i;
+
+ DRM_DEBUG_KMS("[CRTC:%u:%s] desired clock=%luHz\n",
+ dcrtc->crtc.base.id, dcrtc->crtc.name, desired_hz);
+
+ for (i = 0; i < num_clks; i++) {
+ clk = clks[i];
+ if (!clk)
+ continue;
+
+ if (params->settable & BIT(i)) {
+ real_clk_hz = clk_round_rate(clk, desired_hz);
+ desired_clk_hz = desired_hz;
+ } else {
+ real_clk_hz = clk_get_rate(clk);
+ desired_clk_hz = real_clk_hz;
+ }
+
+ /* If the clock can do exactly the desired rate, we're done */
+ if (real_clk_hz == desired_hz) {
+ real_hz = real_clk_hz;
+ div = 1;
+ goto found;
+ }
+
+ /* Calculate the divider - if invalid, we can't do this rate */
+ div = DIV_ROUND_CLOSEST(real_clk_hz, desired_hz);
+ if (div == 0 || div > params->div_max)
+ continue;
+
+ /* Calculate the actual rate - HDMI requires -0.6%..+0.5% */
+ real_hz = DIV_ROUND_CLOSEST(real_clk_hz, div);
+
+ DRM_DEBUG_KMS("[CRTC:%u:%s] clk=%u %luHz div=%u real=%luHz\n",
+ dcrtc->crtc.base.id, dcrtc->crtc.name,
+ i, real_clk_hz, div, real_hz);
+
+ /* Avoid repeated division */
+ if (real_hz < desired_hz) {
+ permillage = real_hz / desired_khz;
+ if (permillage < params->permillage_min)
+ continue;
+ } else {
+ permillage = DIV_ROUND_UP(real_hz, desired_khz);
+ if (permillage > params->permillage_max)
+ continue;
+ }
+ goto found;
+ }
+
+ return -ERANGE;
+
+found:
+ DRM_DEBUG_KMS("[CRTC:%u:%s] selected clk=%u %luHz div=%u real=%luHz\n",
+ dcrtc->crtc.base.id, dcrtc->crtc.name,
+ i, real_clk_hz, div, real_hz);
+
+ res->desired_clk_hz = desired_clk_hz;
+ res->clk = clk;
+ res->div = div;
+
+ return i;
+}
static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
struct resource *res, int irq, const struct armada_variant *variant,
struct device_node *port)
{
- struct armada_private *priv = drm->dev_private;
+ struct armada_private *priv = drm_to_armada_dev(drm);
struct armada_crtc *dcrtc;
struct drm_plane *primary;
void __iomem *base;
@@ -743,7 +923,6 @@
dcrtc->variant = variant;
dcrtc->base = base;
dcrtc->num = drm->mode_config.num_crtc;
- dcrtc->clk = ERR_PTR(-EINVAL);
dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
spin_lock_init(&dcrtc->irq_lock);
@@ -800,6 +979,12 @@
drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
+ ret = drm_mode_crtc_set_gamma_size(&dcrtc->crtc, 256);
+ if (ret)
+ return ret;
+
+ drm_crtc_enable_color_mgmt(&dcrtc->crtc, 0, false, 256);
+
return armada_overlay_plane_create(drm, 1 << dcrtc->num);
err_crtc_init:
--
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