From 1543e317f1da31b75942316931e8f491a8920811 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 04 Jan 2024 10:08:02 +0000
Subject: [PATCH] disable FB
---
kernel/drivers/gpu/arm/bifrost/device/backend/mali_kbase_device_hw_csf.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 93 insertions(+), 3 deletions(-)
diff --git a/kernel/drivers/gpu/arm/bifrost/device/backend/mali_kbase_device_hw_csf.c b/kernel/drivers/gpu/arm/bifrost/device/backend/mali_kbase_device_hw_csf.c
index 8427edb..2abd62a 100644
--- a/kernel/drivers/gpu/arm/bifrost/device/backend/mali_kbase_device_hw_csf.c
+++ b/kernel/drivers/gpu/arm/bifrost/device/backend/mali_kbase_device_hw_csf.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
/*
*
- * (C) COPYRIGHT 2020-2021 ARM Limited. All rights reserved.
+ * (C) COPYRIGHT 2020-2022 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -24,6 +24,7 @@
#include <backend/gpu/mali_kbase_instr_internal.h>
#include <backend/gpu/mali_kbase_pm_internal.h>
#include <device/mali_kbase_device.h>
+#include <device/mali_kbase_device_internal.h>
#include <mali_kbase_reset_gpu.h>
#include <mmu/mali_kbase_mmu.h>
#include <mali_kbase_ctx_sched.h>
@@ -80,6 +81,7 @@
}
} else
kbase_report_gpu_fault(kbdev, status, as_nr, as_valid);
+
}
void kbase_gpu_interrupt(struct kbase_device *kbdev, u32 val)
@@ -114,6 +116,9 @@
GPU_EXCEPTION_TYPE_SW_FAULT_0,
} } };
+ kbase_debug_csf_fault_notify(kbdev, scheduler->active_protm_grp->kctx,
+ DF_GPU_PROTECTED_FAULT);
+
scheduler->active_protm_grp->faulted = true;
kbase_csf_add_group_fatal_error(
scheduler->active_protm_grp, &err_payload);
@@ -124,13 +129,33 @@
if (kbase_prepare_to_reset_gpu(
kbdev, RESET_FLAGS_HWC_UNRECOVERABLE_ERROR))
kbase_reset_gpu(kbdev);
+
+ /* Defer the clearing to the GPU reset sequence */
+ val &= ~GPU_PROTECTED_FAULT;
}
if (val & RESET_COMPLETED)
kbase_pm_reset_done(kbdev);
- KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_CLEAR, NULL, val);
- kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val);
+ /* Defer clearing CLEAN_CACHES_COMPLETED to kbase_clean_caches_done.
+ * We need to acquire hwaccess_lock to avoid a race condition with
+ * kbase_gpu_cache_flush_and_busy_wait
+ */
+ KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_CLEAR, NULL, val & ~CLEAN_CACHES_COMPLETED);
+ kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_CLEAR), val & ~CLEAN_CACHES_COMPLETED);
+
+#ifdef KBASE_PM_RUNTIME
+ if (val & DOORBELL_MIRROR) {
+ unsigned long flags;
+
+ dev_dbg(kbdev->dev, "Doorbell mirror interrupt received");
+ spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
+ kbase_pm_disable_db_mirror_interrupt(kbdev);
+ kbdev->pm.backend.exit_gpu_sleep_mode = true;
+ kbase_csf_scheduler_invoke_tick(kbdev);
+ spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
+ }
+#endif
/* kbase_pm_check_transitions (called by kbase_pm_power_changed) must
* be called after the IRQ has been cleared. This is because it might
@@ -160,3 +185,68 @@
KBASE_KTRACE_ADD(kbdev, CORE_GPU_IRQ_DONE, NULL, val);
}
+
+#if !IS_ENABLED(CONFIG_MALI_BIFROST_NO_MALI)
+bool kbase_is_register_accessible(u32 offset)
+{
+#ifdef CONFIG_MALI_BIFROST_DEBUG
+ if (((offset >= MCU_SUBSYSTEM_BASE) && (offset < IPA_CONTROL_BASE)) ||
+ ((offset >= GPU_CONTROL_MCU_BASE) && (offset < USER_BASE))) {
+ WARN(1, "Invalid register offset 0x%x", offset);
+ return false;
+ }
+#endif
+
+ return true;
+}
+#endif /* !IS_ENABLED(CONFIG_MALI_BIFROST_NO_MALI) */
+
+#if IS_ENABLED(CONFIG_MALI_REAL_HW)
+void kbase_reg_write(struct kbase_device *kbdev, u32 offset, u32 value)
+{
+ if (WARN_ON(!kbdev->pm.backend.gpu_powered))
+ return;
+
+ if (WARN_ON(kbdev->dev == NULL))
+ return;
+
+ if (!kbase_is_register_accessible(offset))
+ return;
+
+ writel(value, kbdev->reg + offset);
+
+#if IS_ENABLED(CONFIG_DEBUG_FS)
+ if (unlikely(kbdev->io_history.enabled))
+ kbase_io_history_add(&kbdev->io_history, kbdev->reg + offset,
+ value, 1);
+#endif /* CONFIG_DEBUG_FS */
+ dev_dbg(kbdev->dev, "w: reg %08x val %08x", offset, value);
+}
+KBASE_EXPORT_TEST_API(kbase_reg_write);
+
+u32 kbase_reg_read(struct kbase_device *kbdev, u32 offset)
+{
+ u32 val;
+
+ if (WARN_ON(!kbdev->pm.backend.gpu_powered))
+ return 0;
+
+ if (WARN_ON(kbdev->dev == NULL))
+ return 0;
+
+ if (!kbase_is_register_accessible(offset))
+ return 0;
+
+ val = readl(kbdev->reg + offset);
+
+#if IS_ENABLED(CONFIG_DEBUG_FS)
+ if (unlikely(kbdev->io_history.enabled))
+ kbase_io_history_add(&kbdev->io_history, kbdev->reg + offset,
+ val, 0);
+#endif /* CONFIG_DEBUG_FS */
+ dev_dbg(kbdev->dev, "r: reg %08x val %08x", offset, val);
+
+ return val;
+}
+KBASE_EXPORT_TEST_API(kbase_reg_read);
+#endif /* !IS_ENABLED(CONFIG_MALI_BIFROST_NO_MALI) */
--
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