From 10ebd8556b7990499c896a550e3d416b444211e6 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Fri, 10 May 2024 02:23:07 +0000
Subject: [PATCH] add led
---
kernel/arch/arm64/boot/dts/rockchip/px30.dtsi | 715 ++++++++++++++++++++++++++++-------------------------------
1 files changed, 340 insertions(+), 375 deletions(-)
diff --git a/kernel/arch/arm64/boot/dts/rockchip/px30.dtsi b/kernel/arch/arm64/boot/dts/rockchip/px30.dtsi
index 917a0e6..ce921f6 100644
--- a/kernel/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/kernel/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
*/
#include <dt-bindings/clock/px30-cru.h>
@@ -27,6 +26,10 @@
aliases {
ethernet0 = &gmac;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -42,6 +45,7 @@
serial5 = &uart5;
spi0 = &spi0;
spi1 = &spi1;
+ spi2 = &sfc;
};
cpus {
@@ -50,39 +54,50 @@
cpu0: cpu@0 {
device_type = "cpu";
- compatible = "arm,cortex-a35", "arm,armv8";
+ compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
dynamic-power-coefficient = <90>;
operating-points-v2 = <&cpu0_opp_table>;
- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu1: cpu@1 {
device_type = "cpu";
- compatible = "arm,cortex-a35", "arm,armv8";
+ compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
+ clocks = <&cru ARMCLK>;
+ #cooling-cells = <2>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ dynamic-power-coefficient = <90>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
+
cpu2: cpu@2 {
device_type = "cpu";
- compatible = "arm,cortex-a35", "arm,armv8";
+ compatible = "arm,cortex-a35";
reg = <0x0 0x2>;
enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
+ clocks = <&cru ARMCLK>;
+ #cooling-cells = <2>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ dynamic-power-coefficient = <90>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
+
cpu3: cpu@3 {
device_type = "cpu";
- compatible = "arm,cortex-a35", "arm,armv8";
+ compatible = "arm,cortex-a35";
reg = <0x0 0x3>;
enable-method = "psci";
- operating-points-v2 = <&cpu0_opp_table>;
+ clocks = <&cru ARMCLK>;
+ #cooling-cells = <2>;
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ dynamic-power-coefficient = <90>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
idle-states {
@@ -335,12 +350,34 @@
};
arm-pmu {
- compatible = "arm,cortex-a53-pmu";
+ compatible = "arm,cortex-a35-pmu";
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ bus_soc: bus-soc {
+ compatible = "rockchip,px30-bus";
+ rockchip,busfreq-policy = "autocs";
+ soc-bus0 {
+ bus-id = <0>;
+ timer-us = <20>;
+ enable-msk = <0x40f7>;
+ };
+ soc-bus1 {
+ bus-id = <1>;
+ timer-us = <200>;
+ enable-msk = <0x40bf>;
+ status = "disabled";
+ };
+ soc-bus2 {
+ bus-id = <2>;
+ timer-us = <200>;
+ enable-msk = <0x4007>;
+ status = "disabled";
+ };
};
bus_apll: bus-apll {
@@ -368,7 +405,7 @@
cpuinfo {
compatible = "rockchip,cpuinfo";
- nvmem-cells = <&otp_id>;
+ nvmem-cells = <&cpu_id>;
nvmem-cell-names = "id";
};
@@ -445,6 +482,55 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ thermal_zones: thermal-zones {
+ soc_thermal: soc-thermal {
+ polling-delay-passive = <20>;
+ polling-delay = <1000>;
+ sustainable-power = <750>;
+ thermal-sensors = <&tsadc 0>;
+
+ trips {
+ threshold: trip-point-0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ target: trip-point-1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ soc_crit: soc-crit {
+ temperature = <115000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ contribution = <4096>;
+ };
+
+ map1 {
+ trip = <&target>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ contribution = <4096>;
+ };
+ };
+ };
+
+ gpu_thermal: gpu-thermal {
+ polling-delay-passive = <100>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+ thermal-sensors = <&tsadc 1>;
+ };
+ };
+
xin24m: xin24m {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -475,20 +561,20 @@
#size-cells = <0>;
/* These power domains are grouped by VD_LOGIC */
- pd_usb@PX30_PD_USB {
+ power-domain@PX30_PD_USB {
reg = <PX30_PD_USB>;
clocks = <&cru HCLK_HOST>,
<&cru HCLK_OTG>,
<&cru SCLK_OTG_ADP>;
pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
};
- pd_sdcard@PX30_PD_SDCARD {
+ power-domain@PX30_PD_SDCARD {
reg = <PX30_PD_SDCARD>;
clocks = <&cru HCLK_SDMMC>,
<&cru SCLK_SDMMC>;
pm_qos = <&qos_sdmmc>;
};
- pd_gmac@PX30_PD_GMAC {
+ power-domain@PX30_PD_GMAC {
reg = <PX30_PD_GMAC>;
clocks = <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>,
@@ -496,7 +582,7 @@
<&cru SCLK_GMAC_RX_TX>;
pm_qos = <&qos_gmac>;
};
- pd_mmc_nand@PX30_PD_MMC_NAND {
+ power-domain@PX30_PD_MMC_NAND {
reg = <PX30_PD_MMC_NAND>;
clocks = <&cru HCLK_NANDC>,
<&cru HCLK_EMMC>,
@@ -509,14 +595,14 @@
pm_qos = <&qos_emmc>, <&qos_nand>,
<&qos_sdio>, <&qos_sfc>;
};
- pd_vpu@PX30_PD_VPU {
+ power-domain@PX30_PD_VPU {
reg = <PX30_PD_VPU>;
clocks = <&cru ACLK_VPU>,
<&cru HCLK_VPU>,
<&cru SCLK_CORE_VPU>;
pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
};
- pd_vo@PX30_PD_VO {
+ power-domain@PX30_PD_VO {
reg = <PX30_PD_VO>;
clocks = <&cru ACLK_RGA>,
<&cru ACLK_VOPB>,
@@ -532,7 +618,7 @@
pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
<&qos_vop_m0>, <&qos_vop_m1>;
};
- pd_vi@PX30_PD_VI {
+ power-domain@PX30_PD_VI {
reg = <PX30_PD_VI>;
clocks = <&cru ACLK_CIF>,
<&cru ACLK_ISP>,
@@ -543,7 +629,7 @@
<&qos_isp_wr>, <&qos_isp_m1>,
<&qos_vip>;
};
- pd_gpu@PX30_PD_GPU {
+ power-domain@PX30_PD_GPU {
reg = <PX30_PD_GPU>;
clocks = <&cru SCLK_GPU>;
pm_qos = <&qos_gpu>;
@@ -566,12 +652,10 @@
compatible = "syscon-reboot-mode";
offset = <0x200>;
mode-bootloader = <BOOT_BL_DOWNLOAD>;
- mode-charge = <BOOT_CHARGING>;
mode-fastboot = <BOOT_FASTBOOT>;
mode-loader = <BOOT_BL_DOWNLOAD>;
mode-normal = <BOOT_NORMAL>;
mode-recovery = <BOOT_RECOVERY>;
- mode-ums = <BOOT_UMS>;
};
pmu_pvtm: pmu-pvtm {
@@ -594,9 +678,11 @@
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 0>, <&dmac 1>;
+ /*You can add it to enable dma*/
+ /*dma-names = "tx", "rx";*/
reg-shift = <2>;
reg-io-width = <4>;
- dmas = <&dmac 0>, <&dmac 1>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "disabled";
@@ -638,13 +724,10 @@
clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac 18>, <&dmac 19>;
dma-names = "tx", "rx";
- resets = <&cru SRST_I2S1>, <&cru SRST_I2S1_H>;
- reset-names = "reset-m", "reset-h";
pinctrl-names = "default";
- pinctrl-0 = <&i2s1_2ch_sclk
- &i2s1_2ch_lrck
- &i2s1_2ch_sdi
- &i2s1_2ch_sdo>;
+ pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
+ &i2s1_2ch_sdi &i2s1_2ch_sdo>;
+ #sound-dai-cells = <0>;
status = "disabled";
};
@@ -656,32 +739,10 @@
clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac 20>, <&dmac 21>;
dma-names = "tx", "rx";
- resets = <&cru SRST_I2S2>, <&cru SRST_I2S2_H>;
- reset-names = "reset-m", "reset-h";
pinctrl-names = "default";
- pinctrl-0 = <&i2s2_2ch_sclk
- &i2s2_2ch_lrck
- &i2s2_2ch_sdi
- &i2s2_2ch_sdo>;
- status = "disabled";
- };
-
- pdm: pdm@ff0a0000 {
- compatible = "rockchip,px30-pdm";
- reg = <0x0 0xff0a0000 0x0 0x1000>;
- clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
- clock-names = "pdm_clk", "pdm_hclk";
- dmas = <&dmac 24>;
- dma-names = "rx";
- resets = <&cru SRST_PDM>;
- reset-names = "pdm-m";
- pinctrl-names = "default";
- pinctrl-0 = <&pdm_clk0m0
- &pdm_clk1
- &pdm_sdi0m0
- &pdm_sdi1
- &pdm_sdi2
- &pdm_sdi3>;
+ pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
+ &i2s2_2ch_sdi &i2s2_2ch_sdo>;
+ #sound-dai-cells = <0>;
status = "disabled";
};
@@ -690,7 +751,7 @@
reg = <0x0 0xff0b0000 0x0 0x400>, <0x0 0xff0b0480 0x0 0x3B80>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_CRYPTO >, <&cru HCLK_CRYPTO >,
- <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>;
+ <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>;
clock-names = "aclk", "hclk", "sclk", "apb_pclk";
resets = <&cru SRST_CRYPTO>;
reset-names = "crypto-rst";
@@ -701,13 +762,13 @@
compatible = "rockchip,cryptov2-rng";
reg = <0x0 0xff0b0400 0x0 0x80>;
clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
- <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
+ <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
clock-names = "clk_crypto", "clk_crypto_apk",
- "aclk_crypto", "hclk_crypto";
+ "aclk_crypto", "hclk_crypto";
assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
- <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
+ <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
assigned-clock-rates = <150000000>, <150000000>,
- <200000000>, <200000000>;
+ <200000000>, <200000000>;
resets = <&cru SRST_CRYPTO>;
reset-names = "reset";
status = "disabled";
@@ -752,12 +813,12 @@
#address-cells = <1>;
#size-cells = <0>;
- lvds_in_vopb: endpoint@0 {
+ lvds_vopb_in: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_lvds>;
};
- lvds_in_vopl: endpoint@1 {
+ lvds_vopl_in: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_lvds>;
};
@@ -821,9 +882,11 @@
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 2>, <&dmac 3>;
+ /*You can add it to enable dma*/
+ /*dma-names = "tx", "rx";*/
reg-shift = <2>;
reg-io-width = <4>;
- dmas = <&dmac 2>, <&dmac 3>;
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
status = "disabled";
@@ -835,9 +898,11 @@
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 4>, <&dmac 5>;
+ /*You can add it to enable dma*/
+ /*dma-names = "tx", "rx";*/
reg-shift = <2>;
reg-io-width = <4>;
- dmas = <&dmac 4>, <&dmac 5>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer>;
status = "disabled";
@@ -849,9 +914,11 @@
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 6>, <&dmac 7>;
+ /*You can add it to enable dma*/
+ /*dma-names = "tx", "rx";*/
reg-shift = <2>;
reg-io-width = <4>;
- dmas = <&dmac 6>, <&dmac 7>;
pinctrl-names = "default";
pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
status = "disabled";
@@ -863,9 +930,11 @@
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 8>, <&dmac 9>;
+ /*You can add it to enable dma*/
+ /*dma-names = "tx", "rx";*/
reg-shift = <2>;
reg-io-width = <4>;
- dmas = <&dmac 8>, <&dmac 9>;
pinctrl-names = "default";
pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
status = "disabled";
@@ -877,16 +946,18 @@
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 10>, <&dmac 11>;
+ /*You can add it to enable dma*/
+ /*dma-names = "tx", "rx";*/
reg-shift = <2>;
reg-io-width = <4>;
- dmas = <&dmac 10>, <&dmac 11>;
pinctrl-names = "default";
pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
status = "disabled";
};
i2c0: i2c@ff180000 {
- compatible = "rockchip,rk3399-i2c";
+ compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xff180000 0x0 0x1000>;
clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
clock-names = "i2c", "pclk";
@@ -899,7 +970,7 @@
};
i2c1: i2c@ff190000 {
- compatible = "rockchip,rk3399-i2c";
+ compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xff190000 0x0 0x1000>;
clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
clock-names = "i2c", "pclk";
@@ -912,7 +983,7 @@
};
i2c2: i2c@ff1a0000 {
- compatible = "rockchip,rk3399-i2c";
+ compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xff1a0000 0x0 0x1000>;
clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
clock-names = "i2c", "pclk";
@@ -925,7 +996,7 @@
};
i2c3: i2c@ff1b0000 {
- compatible = "rockchip,rk3399-i2c";
+ compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xff1b0000 0x0 0x1000>;
clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
clock-names = "i2c", "pclk";
@@ -941,15 +1012,14 @@
compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
reg = <0x0 0xff1d0000 0x0 0x1000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac 12>, <&dmac 13>;
dma-names = "tx", "rx";
- pinctrl-names = "default", "high_speed";
+ pinctrl-names = "default";
pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
- pinctrl-1 = <&spi0_clk_hs &spi0_csn &spi0_miso_hs &spi0_mosi_hs>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
@@ -957,15 +1027,14 @@
compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
reg = <0x0 0xff1d8000 0x0 0x1000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
clock-names = "spiclk", "apb_pclk";
dmas = <&dmac 14>, <&dmac 15>;
dma-names = "tx", "rx";
- pinctrl-names = "default", "high_speed";
+ pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
- pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_csn1 &spi1_miso_hs &spi1_mosi_hs>;
+ #address-cells = <1>;
+ #size-cells = <0>;
status = "disabled";
};
@@ -974,108 +1043,116 @@
reg = <0x0 0xff1e0000 0x0 0x100>;
clocks = <&cru PCLK_WDT_NS>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&cru SRST_WDT_NS_P>;
- reset-names = "reset";
status = "disabled";
};
pwm0: pwm@ff200000 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff200000 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm0_pin>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm0_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm1: pwm@ff200010 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff200010 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm1_pin>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm1_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm2: pwm@ff200020 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff200020 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm2_pin>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm2_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm3: pwm@ff200030 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff200030 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm3_pin>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm3_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm4: pwm@ff208000 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff208000 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm4_pin>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm4_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm5: pwm@ff208010 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff208010 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm5_pin>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm5_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm6: pwm@ff208020 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff208020 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm6_pin>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm6_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
pwm7: pwm@ff208030 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff208030 0x0 0x10>;
- #pwm-cells = <3>;
- pinctrl-names = "active";
- pinctrl-0 = <&pwm7_pin>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm7_pin>;
+ #pwm-cells = <3>;
status = "disabled";
};
- rktimer: rktimer@ff210000 {
- compatible = "rockchip,rk3288-timer";
+ rktimer: timer@ff210000 {
+ compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
reg = <0x0 0xff210000 0x0 0x1000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
clock-names = "pclk", "timer";
};
- amba {
+ amba: bus {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -1086,59 +1163,10 @@
reg = <0x0 0xff240000 0x0 0x4000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMAC>;
clock-names = "apb_pclk";
#dma-cells = <1>;
- arm,pl330-periph-burst;
- };
- };
-
- thermal_zones: thermal-zones {
-
- soc_thermal: soc-thermal {
- polling-delay-passive = <20>;
- polling-delay = <1000>;
- sustainable-power = <750>;
-
- thermal-sensors = <&tsadc 0>;
-
- trips {
- threshold: trip-point-0 {
- temperature = <70000>;
- hysteresis = <2000>;
- type = "passive";
- };
- target: trip-point-1 {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
- soc_crit: soc-crit {
- temperature = <115000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&target>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- contribution = <4096>;
- };
- map1 {
- trip = <&target>;
- cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- contribution = <4096>;
- };
- };
- };
-
- gpu_thermal: gpu-thermal {
- polling-delay-passive = <100>; /* milliseconds */
- polling-delay = <1000>; /* milliseconds */
-
- thermal-sensors = <&tsadc 1>;
};
};
@@ -1146,15 +1174,19 @@
compatible = "rockchip,px30-tsadc";
reg = <0x0 0xff280000 0x0 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- rockchip,grf = <&grf>;
- clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
- clock-names = "tsadc", "apb_pclk";
assigned-clocks = <&cru SCLK_TSADC>;
assigned-clock-rates = <50000>;
+ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+ clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- #thermal-sensor-cells = <1>;
+ rockchip,grf = <&grf>;
rockchip,hw-tshut-temp = <120000>;
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&tsadc_otp_pin>;
+ pinctrl-1 = <&tsadc_otp_out>;
+ pinctrl-2 = <&tsadc_otp_pin>;
+ #thermal-sensor-cells = <1>;
status = "disabled";
};
@@ -1170,19 +1202,19 @@
status = "disabled";
};
- otp: otp@ff290000 {
+ otp: nvmem@ff290000 {
compatible = "rockchip,px30-otp";
reg = <0x0 0xff290000 0x0 0x4000>;
- #address-cells = <1>;
- #size-cells = <1>;
clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
<&cru PCLK_OTP_PHY>;
clock-names = "otp", "apb_pclk", "phy";
resets = <&cru SRST_OTP_PHY>;
- reset-names = "otp_phy";
+ reset-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <1>;
/* Data cells */
- otp_id: id@7 {
+ cpu_id: id@7 {
reg = <0x07 0x10>;
};
cpu_leakage: cpu-leakage@17 {
@@ -1198,27 +1230,14 @@
compatible = "rockchip,px30-cru";
reg = <0x0 0xff2b0000 0x0 0x1000>;
rockchip,grf = <&grf>;
- rockchip,boost = <&cpu_boost>;
#clock-cells = <1>;
#reset-cells = <1>;
+
+ assigned-clocks = <&cru PLL_NPLL>;
+ assigned-clock-rates = <1188000000>;
};
- cpu_boost: cpu-boost@ff2b8000 {
- compatible = "syscon";
- reg = <0x0 0xff2b8000 0x0 0x1000>;
- rockchip,boost-low-con0 = <0x1032>;
- rockchip,boost-low-con1 = <0x1441>;
- rockchip,boost-high-con0 = <0x1036>;
- rockchip,boost-high-con1 = <0x1441>;
- rockchip,boost-backup-pll = <1>;
- rockchip,boost-backup-pll-usage = <0>;
- rockchip,boost-switch-threshold = <0x249f00>;
- rockchip,boost-statis-threshold = <0x100>;
- rockchip,boost-statis-enable = <0>;
- rockchip,boost-enable = <0>;
- };
-
- pmucru: pmu-clock-controller@ff2bc000 {
+ pmucru: clock-controller@ff2bc000 {
compatible = "rockchip,px30-pmucru";
reg = <0x0 0xff2bc000 0x0 0x1000>;
rockchip,grf = <&grf>;
@@ -1247,9 +1266,8 @@
#size-cells = <1>;
u2phy: usb2-phy@100 {
- compatible = "rockchip,px30-usb2phy",
- "rockchip,rk3328-usb2phy";
- reg = <0x100 0x10>;
+ compatible = "rockchip,px30-usb2phy";
+ reg = <0x100 0x20>;
clocks = <&pmucru SCLK_USBPHY_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
@@ -1277,18 +1295,18 @@
};
};
- video_phy: video-phy@ff2e0000 {
- compatible = "rockchip,px30-video-phy";
+ video_phy: dsi_dphy: phy@ff2e0000 {
+ compatible = "rockchip,px30-dsi-dphy", "rockchip,px30-video-phy";
reg = <0x0 0xff2e0000 0x0 0x10000>,
<0x0 0xff450000 0x0 0x10000>;
+ reg-names = "phy", "host";
clocks = <&pmucru SCLK_MIPIDSIPHY_REF>,
<&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>;
- clock-names = "ref", "pclk_phy", "pclk_host";
- #clock-cells = <0>;
+ clock-names = "ref", "pclk", "pclk_host";
resets = <&cru SRST_MIPIDSIPHY_P>;
- reset-names = "rst";
- power-domains = <&power PX30_PD_VO>;
+ reset-names = "apb";
#phy-cells = <0>;
+ power-domains = <&power PX30_PD_VO>;
status = "disabled";
};
@@ -1309,14 +1327,13 @@
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG>;
clock-names = "otg";
- power-domains = <&power PX30_PD_USB>;
dr_mode = "otg";
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <280>;
g-tx-fifo-size = <256 128 128 64 32 16>;
- g-use-dma;
phys = <&u2phy_otg>;
phy-names = "usb2-phy";
+ power-domains = <&power PX30_PD_USB>;
status = "disabled";
};
@@ -1326,9 +1343,9 @@
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST>, <&u2phy>;
clock-names = "usbhost", "utmi";
- power-domains = <&power PX30_PD_USB>;
phys = <&u2phy_host>;
phy-names = "usb";
+ power-domains = <&power PX30_PD_USB>;
status = "disabled";
};
@@ -1338,16 +1355,15 @@
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST>, <&u2phy>;
clock-names = "usbhost", "utmi";
- power-domains = <&power PX30_PD_USB>;
phys = <&u2phy_host>;
phy-names = "usb";
+ power-domains = <&power PX30_PD_USB>;
status = "disabled";
};
gmac: ethernet@ff360000 {
compatible = "rockchip,px30-gmac";
reg = <0x0 0xff360000 0x0 0x10000>;
- rockchip,grf = <&grf>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
@@ -1358,61 +1374,72 @@
"mac_clk_tx", "clk_mac_ref",
"clk_mac_refout", "aclk_mac",
"pclk_mac", "clk_mac_speed";
+ rockchip,grf = <&grf>;
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
+ power-domains = <&power PX30_PD_GMAC>;
resets = <&cru SRST_GMAC_A>;
reset-names = "stmmaceth";
- power-domains = <&power PX30_PD_GMAC>;
status = "disabled";
};
sdmmc: dwmmc@ff370000 {
compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff370000 0x0 0x4000>;
- max-frequency = <150000000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
- assigned-clocks = <&cru SCLK_SDMMC>;
- assigned-clock-parents = <&cru SCLK_SDMMC_DIV50>;
- power-domains = <&power PX30_PD_SDCARD>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ bus-width = <4>;
fifo-depth = <0x100>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
+ power-domains = <&power PX30_PD_SDCARD>;
status = "disabled";
};
sdio: dwmmc@ff380000 {
compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff380000 0x0 0x4000>;
- max-frequency = <150000000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
- assigned-clocks = <&cru SCLK_SDIO>;
- assigned-clock-parents = <&cru SCLK_SDIO_DIV50>;
- power-domains = <&power PX30_PD_MMC_NAND>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ bus-width = <4>;
fifo-depth = <0x100>;
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
+ power-domains = <&power PX30_PD_MMC_NAND>;
status = "disabled";
};
emmc: dwmmc@ff390000 {
compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff390000 0x0 0x4000>;
- max-frequency = <150000000>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
- assigned-clocks = <&cru SCLK_EMMC>;
- assigned-clock-parents = <&cru SCLK_EMMC_DIV50>;
- power-domains = <&power PX30_PD_MMC_NAND>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ bus-width = <8>;
fifo-depth = <0x100>;
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ power-domains = <&power PX30_PD_MMC_NAND>;
+ status = "disabled";
+ };
+
+ sfc: spi@ff3a0000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xff3a0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ assigned-clocks = <&cru SCLK_SFC>;
+ assigned-clock-rates = <100000000>;
status = "disabled";
};
@@ -1430,23 +1457,18 @@
};
gpu: gpu@ff400000 {
- compatible = "arm,mali-bifrost";
+ compatible = "rockchip,px30-mali", "arm,mali-bifrost";
reg = <0x0 0xff400000 0x0 0x4000>;
-
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "GPU", "MMU", "JOB";
-
+ clocks = <&cru SCLK_GPU>;
+ #cooling-cells = <2>;
+ power-domains = <&power PX30_PD_GPU>;
+ operating-points-v2 = <&gpu_opp_table>;
upthreshold = <40>;
downdifferential = <10>;
-
- clocks = <&cru SCLK_GPU>;
- clock-names = "clk_mali";
- power-domains = <&power PX30_PD_GPU>;
- #cooling-cells = <2>;
- operating-points-v2 = <&gpu_opp_table>;
-
status = "disabled";
power_model {
compatible = "arm,mali-simple-power-model";
@@ -1455,7 +1477,6 @@
ts = <32000 4700 (-80) 2>;
thermal-zone = "gpu-thermal";
};
-
};
gpu_opp_table: gpu-opp-table {
@@ -1586,6 +1607,7 @@
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VPU>;
+ rockchip,shootdown-entire;
#iommu-cells = <0>;
status = "disabled";
};
@@ -1615,10 +1637,11 @@
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>;
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>,
- <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>,
- <&cru SRST_VPU_CORE>;
+ <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>,
+ <&cru SRST_VPU_CORE>;
reset-names = "shared_video_a", "shared_video_h",
- "niu_a", "niu_h", "video_core";
+ "niu_a", "niu_h",
+ "video_core";
iommus = <&hevc_mmu>;
rockchip,srv = <&mpp_srv>;
rockchip,taskqueue-node = <0>;
@@ -1635,6 +1658,7 @@
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VPU>;
+ rockchip,shootdown-entire;
#iommu-cells = <0>;
status = "disabled";
};
@@ -1643,13 +1667,13 @@
compatible = "rockchip,px30-mipi-dsi";
reg = <0x0 0xff450000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_MIPI_DSI>, <&video_phy>;
- clock-names = "pclk", "hs_clk";
+ clocks = <&cru PCLK_MIPI_DSI>;
+ clock-names = "pclk";
+ phys = <&video_phy>;
+ phy-names = "dphy";
+ power-domains = <&power PX30_PD_VO>;
resets = <&cru SRST_MIPIDSI_HOST_P>;
reset-names = "apb";
- phys = <&video_phy>;
- phy-names = "mipi_dphy";
- power-domains = <&power PX30_PD_VO>;
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1679,29 +1703,31 @@
vopb: vop@ff460000 {
compatible = "rockchip,px30-vop-big";
- reg = <0x0 0xff460000 0x0 0x1fc>, <0x0 0xff460a00 0x0 0x400>;
+ reg = <0x0 0xff460000 0x0 0x260>, <0x0 0xff460a00 0x0 0x400>;
rockchip,grf = <&grf>;
reg-names = "regs", "gamma_lut";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
<&cru HCLK_VOPB>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
- power-domains = <&power PX30_PD_VO>;
+ resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
+ reset-names = "axi", "ahb", "dclk";
iommus = <&vopb_mmu>;
+ power-domains = <&power PX30_PD_VO>;
status = "disabled";
vopb_out: port {
#address-cells = <1>;
#size-cells = <0>;
- vopb_out_lvds: endpoint@0 {
+ vopb_out_dsi: endpoint@0 {
reg = <0>;
- remote-endpoint = <&lvds_in_vopb>;
+ remote-endpoint = <&dsi_in_vopb>;
};
- vopb_out_dsi: endpoint@1 {
+ vopb_out_lvds: endpoint@1 {
reg = <1>;
- remote-endpoint = <&dsi_in_vopb>;
+ remote-endpoint = <&lvds_vopb_in>;
};
vopb_out_rgb: endpoint@2 {
@@ -1733,22 +1759,24 @@
clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
<&cru HCLK_VOPL>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
- power-domains = <&power PX30_PD_VO>;
+ resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
+ reset-names = "axi", "ahb", "dclk";
iommus = <&vopl_mmu>;
+ power-domains = <&power PX30_PD_VO>;
status = "disabled";
vopl_out: port {
#address-cells = <1>;
#size-cells = <0>;
- vopl_out_lvds: endpoint@0 {
+ vopl_out_dsi: endpoint@0 {
reg = <0>;
- remote-endpoint = <&lvds_in_vopl>;
+ remote-endpoint = <&dsi_in_vopl>;
};
- vopl_out_dsi: endpoint@1 {
+ vopl_out_lvds: endpoint@1 {
reg = <1>;
- remote-endpoint = <&dsi_in_vopl>;
+ remote-endpoint = <&lvds_vopl_in>;
};
vopl_out_rgb: endpoint@2 {
@@ -1828,9 +1856,9 @@
reg = <0x0 0xff4a0000 0x0 0x8000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>,
- <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>;
+ <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>;
clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe",
- "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx";
+ "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx";
resets = <&cru SRST_ISP>, <&cru SRST_MIPICSIPHY_P>;
reset-names = "rst_isp", "rst_mipicsiphy";
power-domains = <&power PX30_PD_VI>;
@@ -1856,9 +1884,9 @@
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
- <&cru SCLK_ISP>, <&cru PCLK_ISP>;
+ <&cru SCLK_ISP>, <&cru PCLK_ISP>;
clock-names = "aclk_isp", "hclk_isp",
- "clk_isp", "pclk_isp";
+ "clk_isp", "pclk_isp";
devfreq = <&dmc>;
power-domains = <&power PX30_PD_VI>;
iommus = <&isp_mmu>;
@@ -1999,11 +2027,11 @@
downdifferential = <20>;
system-status-freq = <
/*system status freq(KHz)*/
- SYS_STATUS_NORMAL 528000
+ SYS_STATUS_NORMAL 666000
SYS_STATUS_REBOOT 450000
SYS_STATUS_SUSPEND 194000
SYS_STATUS_VIDEO_1080P 450000
- SYS_STATUS_BOOST 528000
+ SYS_STATUS_BOOST 666000
SYS_STATUS_ISP 666000
SYS_STATUS_PERFORMANCE 1056000
>;
@@ -2073,14 +2101,6 @@
opp-microvolt-L2 = <950000>;
opp-microvolt-L3 = <950000>;
};
- opp-528000000 {
- opp-hz = /bits/ 64 <528000000>;
- opp-microvolt = <975000>;
- opp-microvolt-L0 = <975000>;
- opp-microvolt-L1 = <975000>;
- opp-microvolt-L2 = <950000>;
- opp-microvolt-L3 = <950000>;
- };
opp-666000000 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <1050000>;
@@ -2110,11 +2130,6 @@
opp-328000000 {
opp-hz = /bits/ 64 <328000000>;
opp-microvolt = <950000>;
- };
- opp-528000000 {
- opp-hz = /bits/ 64 <528000000>;
- opp-microvolt = <950000>;
- status = "disabled";
};
opp-666000000 {
opp-hz = /bits/ 64 <666000000>;
@@ -2318,7 +2333,7 @@
};
tsadc {
- tsadc_otp_gpio: tsadc-otp-gpio {
+ tsadc_otp_gpio: tsadc_otp_pin: tsadc-otp-pin {
rockchip,pins =
<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
@@ -2344,11 +2359,6 @@
uart0_rts: uart0-rts {
rockchip,pins =
<0 RK_PB5 1 &pcfg_pull_none>;
- };
-
- uart0_rts_gpio: uart0-rts-gpio {
- rockchip,pins =
- <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -2407,11 +2417,6 @@
rockchip,pins =
<0 RK_PC3 2 &pcfg_pull_none>;
};
-
- uart3m0_rts_gpio: uart3m0-rts-gpio {
- rockchip,pins =
- <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
};
uart3-m1 {
@@ -2430,15 +2435,9 @@
rockchip,pins =
<1 RK_PB5 2 &pcfg_pull_none>;
};
-
- uart3m1_rts_gpio: uart3m1-rts-gpio {
- rockchip,pins =
- <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
};
uart4 {
-
uart4_xfer: uart4-xfer {
rockchip,pins =
<1 RK_PD4 2 &pcfg_pull_up>,
@@ -2448,7 +2447,6 @@
uart4_cts: uart4-cts {
rockchip,pins =
<1 RK_PD6 2 &pcfg_pull_none>;
-
};
uart4_rts: uart4-rts {
@@ -2458,7 +2456,6 @@
};
uart5 {
-
uart5_xfer: uart5-xfer {
rockchip,pins =
<3 RK_PA2 4 &pcfg_pull_up>,
@@ -2468,7 +2465,6 @@
uart5_cts: uart5-cts {
rockchip,pins =
<3 RK_PA3 4 &pcfg_pull_none>;
-
};
uart5_rts: uart5-rts {
@@ -2641,27 +2637,27 @@
i2s0 {
i2s0_8ch_mclk: i2s0-8ch-mclk {
rockchip,pins =
- <3 RK_PC1 2 &pcfg_pull_none>;
+ <3 RK_PC1 2 &pcfg_pull_none_smt>;
};
i2s0_8ch_sclktx: i2s0-8ch-sclktx {
rockchip,pins =
- <3 RK_PC3 2 &pcfg_pull_none>;
+ <3 RK_PC3 2 &pcfg_pull_none_smt>;
};
i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
rockchip,pins =
- <3 RK_PB4 2 &pcfg_pull_none>;
+ <3 RK_PB4 2 &pcfg_pull_none_smt>;
};
i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
rockchip,pins =
- <3 RK_PC2 2 &pcfg_pull_none>;
+ <3 RK_PC2 2 &pcfg_pull_none_smt>;
};
i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
rockchip,pins =
- <3 RK_PB5 2 &pcfg_pull_none>;
+ <3 RK_PB5 2 &pcfg_pull_none_smt>;
};
i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
@@ -2708,17 +2704,17 @@
i2s1 {
i2s1_2ch_mclk: i2s1-2ch-mclk {
rockchip,pins =
- <2 RK_PC3 1 &pcfg_pull_none>;
+ <2 RK_PC3 1 &pcfg_pull_none_smt>;
};
i2s1_2ch_sclk: i2s1-2ch-sclk {
rockchip,pins =
- <2 RK_PC2 1 &pcfg_pull_none>;
+ <2 RK_PC2 1 &pcfg_pull_none_smt>;
};
i2s1_2ch_lrck: i2s1-2ch-lrck {
rockchip,pins =
- <2 RK_PC1 1 &pcfg_pull_none>;
+ <2 RK_PC1 1 &pcfg_pull_none_smt>;
};
i2s1_2ch_sdi: i2s1-2ch-sdi {
@@ -2735,17 +2731,17 @@
i2s2 {
i2s2_2ch_mclk: i2s2-2ch-mclk {
rockchip,pins =
- <3 RK_PA1 2 &pcfg_pull_none>;
+ <3 RK_PA1 2 &pcfg_pull_none_smt>;
};
i2s2_2ch_sclk: i2s2-2ch-sclk {
rockchip,pins =
- <3 RK_PA2 2 &pcfg_pull_none>;
+ <3 RK_PA2 2 &pcfg_pull_none_smt>;
};
i2s2_2ch_lrck: i2s2-2ch-lrck {
rockchip,pins =
- <3 RK_PA3 2 &pcfg_pull_none>;
+ <3 RK_PA3 2 &pcfg_pull_none_smt>;
};
i2s2_2ch_sdi: i2s2-2ch-sdi {
@@ -2787,16 +2783,6 @@
<1 RK_PD4 1 &pcfg_pull_up_8ma>,
<1 RK_PD5 1 &pcfg_pull_up_8ma>;
};
-
- sdmmc_gpio: sdmmc-gpio {
- rockchip,pins =
- <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
- <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
- };
};
sdio {
@@ -2817,16 +2803,6 @@
<1 RK_PD0 1 &pcfg_pull_up>,
<1 RK_PD1 1 &pcfg_pull_up>;
};
-
- sdio_gpio: sdio-gpio {
- rockchip,pins =
- <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>,
- <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
- };
};
emmc {
@@ -2838,11 +2814,6 @@
emmc_cmd: emmc-cmd {
rockchip,pins =
<1 RK_PB2 2 &pcfg_pull_up_8ma>;
- };
-
- emmc_pwren: emmc-pwren {
- rockchip,pins =
- <1 RK_PB0 2 &pcfg_pull_none>;
};
emmc_rstnout: emmc-rstnout {
@@ -3055,24 +3026,15 @@
gmac {
rmii_pins: rmii-pins {
rockchip,pins =
- /* mac_txen */
- <2 RK_PA0 2 &pcfg_pull_none_12ma>,
- /* mac_txd1 */
- <2 RK_PA1 2 &pcfg_pull_none_12ma>,
- /* mac_txd0 */
- <2 RK_PA2 2 &pcfg_pull_none_12ma>,
- /* mac_rxd0 */
- <2 RK_PA3 2 &pcfg_pull_none>,
- /* mac_rxd1 */
- <2 RK_PA4 2 &pcfg_pull_none>,
- /* mac_rxer */
- <2 RK_PA5 2 &pcfg_pull_none>,
- /* mac_rxdv */
- <2 RK_PA6 2 &pcfg_pull_none>,
- /* mac_mdio */
- <2 RK_PA7 2 &pcfg_pull_none>,
- /* mac_mdc */
- <2 RK_PB1 2 &pcfg_pull_none>;
+ <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
+ <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
+ <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
+ <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
+ <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
+ <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
+ <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
+ <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
+ <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
};
mac_refclk_12ma: mac-refclk-12ma {
@@ -3088,75 +3050,78 @@
cif-m0 {
cif_clkout_m0: cif-clkout-m0 {
- rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none_12ma>;/* cif_clkout */
+ rockchip,pins =
+ <2 RK_PB3 1 &pcfg_pull_none_12ma>;/* cif_clkout */
};
dvp_d2d9_m0: dvp-d2d9-m0 {
rockchip,pins =
- <2 RK_PA0 1 &pcfg_pull_none>,/* cif_data2 */
- <2 RK_PA1 1 &pcfg_pull_none>,/* cif_data3 */
- <2 RK_PA2 1 &pcfg_pull_none>,/* cif_data4 */
- <2 RK_PA3 1 &pcfg_pull_none>,/* cif_data5 */
- <2 RK_PA4 1 &pcfg_pull_none>,/* cif_data6 */
- <2 RK_PA5 1 &pcfg_pull_none>,/* cif_data7 */
- <2 RK_PA6 1 &pcfg_pull_none>,/* cif_data8 */
- <2 RK_PA7 1 &pcfg_pull_none>,/* cif_data9 */
- <2 RK_PB0 1 &pcfg_pull_none>,/* cif_sync */
- <2 RK_PB1 1 &pcfg_pull_none>,/* cif_href */
- <2 RK_PB2 1 &pcfg_pull_none>,/* cif_clkin */
- <2 RK_PB3 1 &pcfg_pull_none>;/* cif_clkout */
+ <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
+ <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
+ <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
+ <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
+ <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
+ <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
+ <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
+ <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
+ <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
+ <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
+ <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
+ <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
};
dvp_d0d1_m0: dvp-d0d1-m0 {
rockchip,pins =
- <2 RK_PB4 1 &pcfg_pull_none>,/* cif_data0 */
- <2 RK_PB6 1 &pcfg_pull_none>;/* cif_data1 */
+ <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
+ <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
};
dvp_d10d11_m0:d10-d11-m0 {
rockchip,pins =
- <2 RK_PB7 1 &pcfg_pull_none>,/* cif_data10 */
- <2 RK_PC0 1 &pcfg_pull_none>;/* cif_data11 */
+ <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
+ <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
};
};
cif-m1 {
cif_clkout_m1: cif-clkout-m1 {
- rockchip,pins = <3 RK_PD0 3 &pcfg_pull_none>;/* cif_clkout */
+ rockchip,pins =
+ <3 RK_PD0 3 &pcfg_pull_none>;
};
dvp_d2d9_m1: dvp-d2d9-m1 {
rockchip,pins =
- <3 RK_PA3 3 &pcfg_pull_none>,/* cif_data2 */
- <3 RK_PA5 3 &pcfg_pull_none>,/* cif_data3 */
- <3 RK_PA7 3 &pcfg_pull_none>,/* cif_data4 */
- <3 RK_PB0 3 &pcfg_pull_none>,/* cif_data5 */
- <3 RK_PB1 3 &pcfg_pull_none>,/* cif_data6 */
- <3 RK_PB4 3 &pcfg_pull_none>,/* cif_data7 */
- <3 RK_PB6 3 &pcfg_pull_none>,/* cif_data8 */
- <3 RK_PB7 3 &pcfg_pull_none>,/* cif_data9 */
- <3 RK_PD1 3 &pcfg_pull_none>,/* cif_sync */
- <3 RK_PD2 3 &pcfg_pull_none>,/* cif_href */
- <3 RK_PD3 3 &pcfg_pull_none>,/* cif_clkin */
- <3 RK_PD0 3 &pcfg_pull_none>;/* cif_clkout */
+ <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
+ <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
+ <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
+ <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
+ <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
+ <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
+ <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
+ <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
+ <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
+ <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
+ <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
+ <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
};
dvp_d0d1_m1: dvp-d0d1-m1 {
rockchip,pins =
- <3 RK_PA1 3 &pcfg_pull_none>,/* cif_data0 */
- <3 RK_PA2 3 &pcfg_pull_none>;/* cif_data1 */
+ <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
+ <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
};
dvp_d10d11_m1:d10-d11-m1 {
rockchip,pins =
- <3 RK_PC6 3 &pcfg_pull_none>,/* cif_data10 */
- <3 RK_PC7 3 &pcfg_pull_none>;/* cif_data11 */
+ <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
+ <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
};
};
isp {
isp_prelight: isp-prelight {
- rockchip,pins = <3 RK_PD1 4 &pcfg_pull_none>;/* ISP_PRELIGHTTRIG */
+ rockchip,pins =
+ <3 RK_PD1 4 &pcfg_pull_none>;
};
};
};
--
Gitblit v1.6.2