From 102a0743326a03cd1a1202ceda21e175b7d3575c Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Tue, 20 Feb 2024 01:20:52 +0000
Subject: [PATCH] add new system file
---
kernel/drivers/phy/phy-xgene.c | 18 +++---------------
1 files changed, 3 insertions(+), 15 deletions(-)
diff --git a/kernel/drivers/phy/phy-xgene.c b/kernel/drivers/phy/phy-xgene.c
index ae266e0..b88922e 100644
--- a/kernel/drivers/phy/phy-xgene.c
+++ b/kernel/drivers/phy/phy-xgene.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* AppliedMicro X-Gene Multi-purpose PHY driver
*
@@ -5,19 +6,6 @@
* Author: Loc Ho <lho@apm.com>
* Tuan Phan <tphan@apm.com>
* Suman Tripathi <stripathi@apm.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
* The first PLL clock macro is used for internal reference clock. The second
@@ -1354,7 +1342,7 @@
static void xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx *ctx, int lane)
{
int i;
- struct {
+ static const struct {
u32 reg;
u32 val;
} serdes_reg[] = {
@@ -1627,7 +1615,7 @@
if (args->args_count <= 0)
return ERR_PTR(-EINVAL);
- if (args->args[0] < MODE_SATA || args->args[0] >= MODE_MAX)
+ if (args->args[0] >= MODE_MAX)
return ERR_PTR(-EINVAL);
ctx->mode = args->args[0];
--
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