From 102a0743326a03cd1a1202ceda21e175b7d3575c Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Tue, 20 Feb 2024 01:20:52 +0000
Subject: [PATCH] add new system file
---
kernel/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt | 27 +++++++++++++++++++--------
1 files changed, 19 insertions(+), 8 deletions(-)
diff --git a/kernel/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/kernel/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt
index 7d60a50..e553282 100644
--- a/kernel/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt
+++ b/kernel/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt
@@ -1,26 +1,37 @@
NVIDIA Tegra20 MC(Memory Controller)
Required properties:
-- compatible : "nvidia,tegra20-mc"
-- reg : Should contain 2 register ranges(address and length); see the
- example below. Note that the MC registers are interleaved with the
- GART registers, and hence must be represented as multiple ranges.
+- compatible : "nvidia,tegra20-mc-gart"
+- reg : Should contain 2 register ranges: physical base address and length of
+ the controller's registers and the GART aperture respectively.
+- clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+ - mc: the module's clock input
- interrupts : Should contain MC General interrupt.
- #reset-cells : Should be 1. This cell represents memory client module ID.
The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>
or in the TRM documentation.
+- #iommu-cells: Should be 0. This cell represents the number of cells in an
+ IOMMU specifier needed to encode an address. GART supports only a single
+ address space that is shared by all devices, therefore no additional
+ information needed for the address encoding.
Example:
mc: memory-controller@7000f000 {
- compatible = "nvidia,tegra20-mc";
- reg = <0x7000f000 0x024
- 0x7000f03c 0x3c4>;
- interrupts = <0 77 0x04>;
+ compatible = "nvidia,tegra20-mc-gart";
+ reg = <0x7000f000 0x400 /* controller registers */
+ 0x58000000 0x02000000>; /* GART aperture */
+ clocks = <&tegra_car TEGRA20_CLK_MC>;
+ clock-names = "mc";
+ interrupts = <GIC_SPI 77 0x04>;
#reset-cells = <1>;
+ #iommu-cells = <0>;
};
video-codec@6001a000 {
compatible = "nvidia,tegra20-vde";
...
resets = <&mc TEGRA20_MC_RESET_VDE>;
+ iommus = <&mc>;
};
--
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