From 08f87f769b595151be1afeff53e144f543faa614 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 06 Dec 2023 09:51:13 +0000
Subject: [PATCH] add dts config
---
kernel/drivers/gpu/drm/nouveau/dispnv50/head907d.c | 474 +++++++++++++++++++++++++++++++++++++++--------------------
1 files changed, 312 insertions(+), 162 deletions(-)
diff --git a/kernel/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/kernel/drivers/gpu/drm/nouveau/dispnv50/head907d.c
index 6339071..8f860e9 100644
--- a/kernel/drivers/gpu/drm/nouveau/dispnv50/head907d.c
+++ b/kernel/drivers/gpu/drm/nouveau/dispnv50/head907d.c
@@ -19,247 +19,396 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include <drm/drm_connector.h>
+#include <drm/drm_mode_config.h>
+#include <drm/drm_vblank.h>
+#include "nouveau_drv.h"
+#include "nouveau_bios.h"
+#include "nouveau_connector.h"
#include "head.h"
#include "core.h"
+#include "crc.h"
-void
+#include <nvif/push507c.h>
+
+#include <nvhw/class/cl907d.h>
+
+int
head907d_or(struct nv50_head *head, struct nv50_head_atom *asyh)
{
- struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
- u32 *push;
- if ((push = evo_wait(core, 3))) {
- evo_mthd(push, 0x0404 + (head->base.index * 0x300), 2);
- evo_data(push, 0x00000001 | asyh->or.depth << 6 |
- asyh->or.nvsync << 4 |
- asyh->or.nhsync << 3);
- evo_data(push, 0x31ec6000 | head->base.index << 25 |
- asyh->mode.interlace);
- evo_kick(push, core);
- }
+ struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
+ const int i = head->base.index;
+ int ret;
+
+ if ((ret = PUSH_WAIT(push, 3)))
+ return ret;
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i),
+ NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, CRC_MODE, asyh->or.crc_raster) |
+ NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, HSYNC_POLARITY, asyh->or.nhsync) |
+ NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, VSYNC_POLARITY, asyh->or.nvsync) |
+ NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, PIXEL_DEPTH, asyh->or.depth),
+
+ HEAD_SET_CONTROL(i), 0x31ec6000 | head->base.index << 25 |
+ NVVAL(NV907D, HEAD_SET_CONTROL, STRUCTURE, asyh->mode.interlace));
+ return 0;
}
-void
+int
head907d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
{
- struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
- u32 *push;
- if ((push = evo_wait(core, 2))) {
- evo_mthd(push, 0x0498 + (head->base.index * 0x300), 1);
- evo_data(push, asyh->procamp.sat.sin << 20 |
- asyh->procamp.sat.cos << 8);
- evo_kick(push, core);
- }
+ struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
+ const int i = head->base.index;
+ int ret;
+
+ if ((ret = PUSH_WAIT(push, 2)))
+ return ret;
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_PROCAMP(i),
+ NVDEF(NV907D, HEAD_SET_PROCAMP, COLOR_SPACE, RGB) |
+ NVDEF(NV907D, HEAD_SET_PROCAMP, CHROMA_LPF, AUTO) |
+ NVVAL(NV907D, HEAD_SET_PROCAMP, SAT_COS, asyh->procamp.sat.cos) |
+ NVVAL(NV907D, HEAD_SET_PROCAMP, SAT_SINE, asyh->procamp.sat.sin) |
+ NVDEF(NV907D, HEAD_SET_PROCAMP, DYNAMIC_RANGE, VESA) |
+ NVDEF(NV907D, HEAD_SET_PROCAMP, RANGE_COMPRESSION, DISABLE));
+ return 0;
}
-static void
+static int
head907d_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
{
- struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
- u32 *push;
- if ((push = evo_wait(core, 2))) {
- evo_mthd(push, 0x0490 + (head->base.index * 0x0300), 1);
- evo_data(push, asyh->dither.mode << 3 |
- asyh->dither.bits << 1 |
- asyh->dither.enable);
- evo_kick(push, core);
- }
+ struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
+ const int i = head->base.index;
+ int ret;
+
+ if ((ret = PUSH_WAIT(push, 2)))
+ return ret;
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_DITHER_CONTROL(i),
+ NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) |
+ NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) |
+ NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) |
+ NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, PHASE, 0));
+ return 0;
}
-void
+int
head907d_ovly(struct nv50_head *head, struct nv50_head_atom *asyh)
{
- struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
+ struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
+ const int i = head->base.index;
u32 bounds = 0;
- u32 *push;
+ int ret;
if (asyh->ovly.cpp) {
switch (asyh->ovly.cpp) {
- case 8: bounds |= 0x00000500; break;
- case 4: bounds |= 0x00000300; break;
- case 2: bounds |= 0x00000100; break;
+ case 8: bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, PIXEL_DEPTH, BPP_64); break;
+ case 4: bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break;
+ case 2: bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break;
default:
WARN_ON(1);
break;
}
- bounds |= 0x00000001;
+ bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, USABLE, TRUE);
} else {
- bounds |= 0x00000100;
+ bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16);
}
- if ((push = evo_wait(core, 2))) {
- evo_mthd(push, 0x04d4 + head->base.index * 0x300, 1);
- evo_data(push, bounds);
- evo_kick(push, core);
- }
+ if ((ret = PUSH_WAIT(push, 2)))
+ return ret;
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS(i), bounds);
+ return 0;
}
-static void
+static int
head907d_base(struct nv50_head *head, struct nv50_head_atom *asyh)
{
- struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
+ struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
+ const int i = head->base.index;
u32 bounds = 0;
- u32 *push;
+ int ret;
if (asyh->base.cpp) {
switch (asyh->base.cpp) {
- case 8: bounds |= 0x00000500; break;
- case 4: bounds |= 0x00000300; break;
- case 2: bounds |= 0x00000100; break;
- case 1: bounds |= 0x00000000; break;
+ case 8: bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_64); break;
+ case 4: bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break;
+ case 2: bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break;
+ case 1: bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_8); break;
default:
WARN_ON(1);
break;
}
- bounds |= 0x00000001;
+ bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, USABLE, TRUE);
}
- if ((push = evo_wait(core, 2))) {
- evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1);
- evo_data(push, bounds);
- evo_kick(push, core);
- }
+ if ((ret = PUSH_WAIT(push, 2)))
+ return ret;
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds);
+ return 0;
}
-void
+int
head907d_curs_clr(struct nv50_head *head)
{
- struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
- u32 *push;
- if ((push = evo_wait(core, 4))) {
- evo_mthd(push, 0x0480 + head->base.index * 0x300, 1);
- evo_data(push, 0x05000000);
- evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
- evo_data(push, 0x00000000);
- evo_kick(push, core);
- }
+ struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
+ const int i = head->base.index;
+ int ret;
+
+ if ((ret = PUSH_WAIT(push, 4)))
+ return ret;
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i),
+ NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |
+ NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8) |
+ NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, SIZE, W64_H64));
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000);
+ return 0;
}
-void
+int
head907d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
{
- struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
- u32 *push;
- if ((push = evo_wait(core, 5))) {
- evo_mthd(push, 0x0480 + head->base.index * 0x300, 2);
- evo_data(push, 0x80000000 | asyh->curs.layout << 26 |
- asyh->curs.format << 24);
- evo_data(push, asyh->curs.offset >> 8);
- evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
- evo_data(push, asyh->curs.handle);
- evo_kick(push, core);
- }
+ struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
+ const int i = head->base.index;
+ int ret;
+
+ if ((ret = PUSH_WAIT(push, 5)))
+ return ret;
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i),
+ NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |
+ NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) |
+ NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) |
+ NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) |
+ NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) |
+ NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND),
+
+ HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8);
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle);
+ return 0;
}
-void
+int
head907d_core_clr(struct nv50_head *head)
{
- struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
- u32 *push;
- if ((push = evo_wait(core, 2))) {
- evo_mthd(push, 0x0474 + head->base.index * 0x300, 1);
- evo_data(push, 0x00000000);
- evo_kick(push, core);
- }
+ struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
+ const int i = head->base.index;
+ int ret;
+
+ if ((ret = PUSH_WAIT(push, 2)))
+ return ret;
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMAS_ISO(i), 0x00000000);
+ return 0;
}
-void
+int
head907d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
{
- struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
- u32 *push;
- if ((push = evo_wait(core, 9))) {
- evo_mthd(push, 0x0460 + head->base.index * 0x300, 1);
- evo_data(push, asyh->core.offset >> 8);
- evo_mthd(push, 0x0468 + head->base.index * 0x300, 4);
- evo_data(push, asyh->core.h << 16 | asyh->core.w);
- evo_data(push, asyh->core.layout << 24 |
- (asyh->core.pitch >> 8) << 8 |
- asyh->core.blocks << 8 |
- asyh->core.blockh);
- evo_data(push, asyh->core.format << 8);
- evo_data(push, asyh->core.handle);
- evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1);
- evo_data(push, asyh->core.y << 16 | asyh->core.x);
- evo_kick(push, core);
- }
+ struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
+ const int i = head->base.index;
+ int ret;
+
+ if ((ret = PUSH_WAIT(push, 9)))
+ return ret;
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_OFFSET(i),
+ NVVAL(NV907D, HEAD_SET_OFFSET, ORIGIN, asyh->core.offset >> 8));
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_SIZE(i),
+ NVVAL(NV907D, HEAD_SET_SIZE, WIDTH, asyh->core.w) |
+ NVVAL(NV907D, HEAD_SET_SIZE, HEIGHT, asyh->core.h),
+
+ HEAD_SET_STORAGE(i),
+ NVVAL(NV907D, HEAD_SET_STORAGE, BLOCK_HEIGHT, asyh->core.blockh) |
+ NVVAL(NV907D, HEAD_SET_STORAGE, PITCH, asyh->core.pitch >> 8) |
+ NVVAL(NV907D, HEAD_SET_STORAGE, PITCH, asyh->core.blocks) |
+ NVVAL(NV907D, HEAD_SET_STORAGE, MEMORY_LAYOUT, asyh->core.layout),
+
+ HEAD_SET_PARAMS(i),
+ NVVAL(NV907D, HEAD_SET_PARAMS, FORMAT, asyh->core.format) |
+ NVDEF(NV907D, HEAD_SET_PARAMS, SUPER_SAMPLE, X1_AA) |
+ NVDEF(NV907D, HEAD_SET_PARAMS, GAMMA, LINEAR),
+
+ HEAD_SET_CONTEXT_DMAS_ISO(i),
+ NVVAL(NV907D, HEAD_SET_CONTEXT_DMAS_ISO, HANDLE, asyh->core.handle));
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_POINT_IN(i),
+ NVVAL(NV907D, HEAD_SET_VIEWPORT_POINT_IN, X, asyh->core.x) |
+ NVVAL(NV907D, HEAD_SET_VIEWPORT_POINT_IN, Y, asyh->core.y));
+ return 0;
}
-void
+int
head907d_olut_clr(struct nv50_head *head)
{
- struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
- u32 *push;
- if ((push = evo_wait(core, 4))) {
- evo_mthd(push, 0x0448 + (head->base.index * 0x300), 1);
- evo_data(push, 0x00000000);
- evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
- evo_data(push, 0x00000000);
- evo_kick(push, core);
- }
+ struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
+ const int i = head->base.index;
+ int ret;
+
+ if ((ret = PUSH_WAIT(push, 4)))
+ return ret;
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
+ NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, ENABLE, DISABLE));
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), 0x00000000);
+ return 0;
}
-void
+int
head907d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
{
- struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
- u32 *push;
- if ((push = evo_wait(core, 5))) {
- evo_mthd(push, 0x0448 + (head->base.index * 0x300), 2);
- evo_data(push, 0x80000000 | asyh->olut.mode << 24);
- evo_data(push, asyh->olut.offset >> 8);
- evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
- evo_data(push, asyh->olut.handle);
- evo_kick(push, core);
- }
+ struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
+ const int i = head->base.index;
+ int ret;
+
+ if ((ret = PUSH_WAIT(push, 5)))
+ return ret;
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i),
+ NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, ENABLE, ENABLE) |
+ NVVAL(NV907D, HEAD_SET_OUTPUT_LUT_LO, MODE, asyh->olut.mode) |
+ NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, NEVER_YIELD_TO_BASE, DISABLE),
+
+ HEAD_SET_OUTPUT_LUT_HI(i),
+ NVVAL(NV907D, HEAD_SET_OUTPUT_LUT_HI, ORIGIN, asyh->olut.offset >> 8));
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle);
+ return 0;
}
void
-head907d_olut(struct nv50_head *head, struct nv50_head_atom *asyh)
+head907d_olut_load(struct drm_color_lut *in, int size, void __iomem *mem)
{
- asyh->olut.mode = 7;
+ for (; size--; in++, mem += 8) {
+ writew(drm_color_lut_extract(in-> red, 14) + 0x6000, mem + 0);
+ writew(drm_color_lut_extract(in->green, 14) + 0x6000, mem + 2);
+ writew(drm_color_lut_extract(in-> blue, 14) + 0x6000, mem + 4);
+ }
+
+ /* INTERPOLATE modes require a "next" entry to interpolate with,
+ * so we replicate the last entry to deal with this for now.
+ */
+ writew(readw(mem - 8), mem + 0);
+ writew(readw(mem - 6), mem + 2);
+ writew(readw(mem - 4), mem + 4);
}
-void
+bool
+head907d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size)
+{
+ if (size != 256 && size != 1024)
+ return false;
+
+ if (size == 1024)
+ asyh->olut.mode = NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE;
+ else
+ asyh->olut.mode = NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE;
+
+ asyh->olut.load = head907d_olut_load;
+ return true;
+}
+
+int
head907d_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
{
- struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
+ struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
struct nv50_head_mode *m = &asyh->mode;
- u32 *push;
- if ((push = evo_wait(core, 14))) {
- evo_mthd(push, 0x0410 + (head->base.index * 0x300), 6);
- evo_data(push, 0x00000000);
- evo_data(push, m->v.active << 16 | m->h.active );
- evo_data(push, m->v.synce << 16 | m->h.synce );
- evo_data(push, m->v.blanke << 16 | m->h.blanke );
- evo_data(push, m->v.blanks << 16 | m->h.blanks );
- evo_data(push, m->v.blank2e << 16 | m->v.blank2s);
- evo_mthd(push, 0x042c + (head->base.index * 0x300), 2);
- evo_data(push, 0x00000000); /* ??? */
- evo_data(push, 0xffffff00);
- evo_mthd(push, 0x0450 + (head->base.index * 0x300), 3);
- evo_data(push, m->clock * 1000);
- evo_data(push, 0x00200000); /* ??? */
- evo_data(push, m->clock * 1000);
- evo_kick(push, core);
- }
+ const int i = head->base.index;
+ int ret;
+
+ if ((ret = PUSH_WAIT(push, 14)))
+ return ret;
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_OVERSCAN_COLOR(i),
+ NVVAL(NV907D, HEAD_SET_OVERSCAN_COLOR, RED, 0) |
+ NVVAL(NV907D, HEAD_SET_OVERSCAN_COLOR, GRN, 0) |
+ NVVAL(NV907D, HEAD_SET_OVERSCAN_COLOR, BLU, 0),
+
+ HEAD_SET_RASTER_SIZE(i),
+ NVVAL(NV907D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) |
+ NVVAL(NV907D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active),
+
+ HEAD_SET_RASTER_SYNC_END(i),
+ NVVAL(NV907D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) |
+ NVVAL(NV907D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce),
+
+ HEAD_SET_RASTER_BLANK_END(i),
+ NVVAL(NV907D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) |
+ NVVAL(NV907D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke),
+
+ HEAD_SET_RASTER_BLANK_START(i),
+ NVVAL(NV907D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) |
+ NVVAL(NV907D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks),
+
+ HEAD_SET_RASTER_VERT_BLANK2(i),
+ NVVAL(NV907D, HEAD_SET_RASTER_VERT_BLANK2, YSTART, m->v.blank2s) |
+ NVVAL(NV907D, HEAD_SET_RASTER_VERT_BLANK2, YEND, m->v.blank2e));
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_DEFAULT_BASE_COLOR(i),
+ NVVAL(NV907D, HEAD_SET_DEFAULT_BASE_COLOR, RED, 0) |
+ NVVAL(NV907D, HEAD_SET_DEFAULT_BASE_COLOR, GREEN, 0) |
+ NVVAL(NV907D, HEAD_SET_DEFAULT_BASE_COLOR, BLUE, 0),
+
+ HEAD_SET_CRC_CONTROL(i),
+ NVDEF(NV907D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) |
+ NVDEF(NV907D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) |
+ NVDEF(NV907D, HEAD_SET_CRC_CONTROL, TIMESTAMP_MODE, FALSE) |
+ NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, NONE) |
+ NVDEF(NV907D, HEAD_SET_CRC_CONTROL, SECONDARY_OUTPUT, NONE));
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),
+ NVVAL(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000) |
+ NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, ADJ1000DIV1001, FALSE),
+
+ HEAD_SET_PIXEL_CLOCK_CONFIGURATION(i),
+ NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, MODE, CLK_CUSTOM) |
+ NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, NOT_DRIVER, FALSE) |
+ NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, ENABLE_HOPPING, FALSE),
+
+ HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),
+ NVVAL(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 1000) |
+ NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, ADJ1000DIV1001, FALSE));
+ return 0;
}
-void
+int
head907d_view(struct nv50_head *head, struct nv50_head_atom *asyh)
{
- struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan;
- u32 *push;
- if ((push = evo_wait(core, 8))) {
- evo_mthd(push, 0x0494 + (head->base.index * 0x300), 1);
- evo_data(push, 0x00000000);
- evo_mthd(push, 0x04b8 + (head->base.index * 0x300), 1);
- evo_data(push, asyh->view.iH << 16 | asyh->view.iW);
- evo_mthd(push, 0x04c0 + (head->base.index * 0x300), 3);
- evo_data(push, asyh->view.oH << 16 | asyh->view.oW);
- evo_data(push, asyh->view.oH << 16 | asyh->view.oW);
- evo_data(push, asyh->view.oH << 16 | asyh->view.oW);
- evo_kick(push, core);
- }
+ struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push;
+ const int i = head->base.index;
+ int ret;
+
+ if ((ret = PUSH_WAIT(push, 8)))
+ return ret;
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER(i),
+ NVDEF(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, VERTICAL_TAPS, TAPS_1) |
+ NVDEF(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, HORIZONTAL_TAPS, TAPS_1) |
+ NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, HRESPONSE_BIAS, 0) |
+ NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, VRESPONSE_BIAS, 0));
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_IN(i),
+ NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) |
+ NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH));
+
+ PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_OUT(i),
+ NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) |
+ NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH),
+
+ HEAD_SET_VIEWPORT_SIZE_OUT_MIN(i),
+ NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, WIDTH, asyh->view.oW) |
+ NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, HEIGHT, asyh->view.oH),
+
+ HEAD_SET_VIEWPORT_SIZE_OUT_MAX(i),
+ NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MAX, WIDTH, asyh->view.oW) |
+ NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MAX, HEIGHT, asyh->view.oH));
+ return 0;
}
const struct nv50_head_func
@@ -267,6 +416,7 @@
.view = head907d_view,
.mode = head907d_mode,
.olut = head907d_olut,
+ .olut_size = 1024,
.olut_set = head907d_olut_set,
.olut_clr = head907d_olut_clr,
.core_calc = head507d_core_calc,
--
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