From 08f87f769b595151be1afeff53e144f543faa614 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 06 Dec 2023 09:51:13 +0000
Subject: [PATCH] add dts config
---
kernel/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/kernel/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c b/kernel/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c
index ddd2953..4a8af80 100644
--- a/kernel/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c
+++ b/kernel/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c
@@ -1,12 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* MPC85xx PM operators
*
* Copyright 2015 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
*/
#define pr_fmt(fmt) "%s: " fmt, __func__
@@ -21,6 +17,7 @@
static struct ccsr_guts __iomem *guts;
+#ifdef CONFIG_FSL_PMC
static void mpc85xx_irq_mask(int cpu)
{
@@ -53,6 +50,7 @@
{
}
+#endif
static void mpc85xx_freeze_time_base(bool freeze)
{
@@ -80,10 +78,12 @@
static const struct fsl_pm_ops mpc85xx_pm_ops = {
.freeze_time_base = mpc85xx_freeze_time_base,
+#ifdef CONFIG_FSL_PMC
.irq_mask = mpc85xx_irq_mask,
.irq_unmask = mpc85xx_irq_unmask,
.cpu_die = mpc85xx_cpu_die,
.cpu_up_prepare = mpc85xx_cpu_up_prepare,
+#endif
};
int __init mpc85xx_setup_pmc(void)
--
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