From 072de836f53be56a70cecf70b43ae43b7ce17376 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 10:08:36 +0000
Subject: [PATCH] mk-rootfs.sh
---
kernel/arch/nds32/Kconfig.cpu | 44 +++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 43 insertions(+), 1 deletions(-)
diff --git a/kernel/arch/nds32/Kconfig.cpu b/kernel/arch/nds32/Kconfig.cpu
index b8c8984..f88a12f 100644
--- a/kernel/arch/nds32/Kconfig.cpu
+++ b/kernel/arch/nds32/Kconfig.cpu
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
comment "Processor Features"
config CPU_BIG_ENDIAN
@@ -6,6 +7,40 @@
config CPU_LITTLE_ENDIAN
bool "Little endian"
default y
+
+config FPU
+ bool "FPU support"
+ default n
+ help
+ If FPU ISA is used in user space, this configuration shall be Y to
+ enable required support in kernel such as fpu context switch and
+ fpu exception handler.
+
+ If no FPU ISA is used in user space, say N.
+
+config LAZY_FPU
+ bool "lazy FPU support"
+ depends on FPU
+ default y
+ help
+ Say Y here to enable the lazy FPU scheme. The lazy FPU scheme can
+ enhance system performance by reducing the context switch
+ frequency of the FPU register.
+
+ For normal case, say Y.
+
+config SUPPORT_DENORMAL_ARITHMETIC
+ bool "Denormal arithmetic support"
+ depends on FPU
+ default n
+ help
+ Say Y here to enable arithmetic of denormalized number. Enabling
+ this feature can enhance the precision for tininess number.
+ However, performance loss in float point calculations is
+ possibly significant due to additional FPU exception.
+
+ If the calculated tolerance for tininess number is not critical,
+ say N to prevent performance loss.
config HWZOL
bool "hardware zero overhead loop support"
@@ -38,7 +73,7 @@
the cache aliasing issue. The rest cpus(N13, N10 and D10) are
implemented as VIPT data cache. It may cause the cache aliasing issue
if its cache way size is larger than page size. You can specify the
- CPU type direcly or choose CPU_V3 if unsure.
+ CPU type directly or choose CPU_V3 if unsure.
A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
A kernel built for N15 is able to run on N15 or D15.
@@ -143,6 +178,13 @@
Say Y here to enable L2 cache if your SoC are integrated with L2CC.
If unsure, say N.
+config HW_PRE
+ bool "Enable hardware prefetcher"
+ default y
+ help
+ Say Y here to enable hardware prefetcher feature.
+ Only when CPU_VER.REV >= 0x09 can support.
+
menu "Memory configuration"
choice
--
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