From 071106ecf68c401173c58808b1cf5f68cc50d390 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Fri, 05 Jan 2024 08:39:27 +0000
Subject: [PATCH] change wifi driver to cypress
---
u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c | 89 +++++++++++++++++++++++++++++++-------------
1 files changed, 63 insertions(+), 26 deletions(-)
diff --git a/u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c b/u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c
index 7323d96..678d558 100644
--- a/u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -19,20 +19,31 @@
#define FIREWALL_DDR_BASE 0xfe030000
#define FW_DDR_MST5_REG 0x54
#define FW_DDR_MST13_REG 0x74
+#define FW_DDR_MST19_REG 0x8c
#define FW_DDR_MST21_REG 0x94
#define FW_DDR_MST26_REG 0xa8
#define FW_DDR_MST27_REG 0xac
#define FIREWALL_SYSMEM_BASE 0xfe038000
#define FW_SYSM_MST5_REG 0x54
#define FW_SYSM_MST13_REG 0x74
+#define FW_SYSM_MST19_REG 0x8c
#define FW_SYSM_MST21_REG 0x94
#define FW_SYSM_MST26_REG 0xa8
#define FW_SYSM_MST27_REG 0xac
+#define PMU1_SGRF_BASE 0xfd582000
+#define PMU1_SGRF_SOC_CON0 0x0
+#define PMU1_SGRF_SOC_CON6 0x18
+#define PMU1_SGRF_SOC_CON7 0x1c
+#define PMU1_SGRF_SOC_CON8 0x20
+#define PMU1_SGRF_SOC_CON9 0x24
+#define PMU1_SGRF_SOC_CON10 0x28
+#define PMU1_SGRF_SOC_CON13 0x34
#define SYS_GRF_BASE 0xfd58c000
#define SYS_GRF_SOC_CON6 0x0318
#define USBGRF_BASE 0xfd5ac000
#define USB_GRF_USB3OTG0_CON1 0x001c
#define BUS_SGRF_BASE 0xfd586000
+#define BUS_SGRF_SOC_CON2 0x08
#define BUS_SGRF_FIREWALL_CON18 0x288
#define PMU_BASE 0xfd8d0000
#define PMU_PWR_GATE_SFTCON1 0x8150
@@ -66,14 +77,21 @@
#define EMMC_IOC_GPIO2D_DS_H 0x5c
#define CRU_BASE 0xfd7c0000
+#define CRU_GPLL_CON1 0x01c4
#define CRU_SOFTRST_CON77 0x0b34
+#define CRU_GLB_RST_CON 0x0c10
#define PMU1CRU_BASE 0xfd7f0000
+#define PMU1CRU_SOFTRST_CON00 0x0a00
#define PMU1CRU_SOFTRST_CON03 0x0a0c
#define PMU1CRU_SOFTRST_CON04 0x0a10
#define HDMIRX_NODE_FDT_PATH "/hdmirx-controller@fdee0000"
#define RK3588_PHY_CONFIG 0xfdee00c0
+
+#define VOP_M0_PRIORITY_REG 0xfdf82008
+#define VOP_M1_PRIORITY_REG 0xfdf82208
+#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7))
#ifdef CONFIG_ARM64
#include <asm/armv8/mmu.h>
@@ -865,8 +883,15 @@
secure_reg &= 0xffff0000;
writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
- /* Select clk_tx source as default for i2s2/i2s3 */
- writel(0x03400340, SYS_GRF_BASE + SYS_GRF_SOC_CON6);
+ /*
+ * Select clk_tx source as default for i2s2/i2s3
+ * Set I2Sx_MCLK as input default
+ *
+ * It's safe to set mclk as input default to avoid high freq glitch
+ * which may make devices work unexpected. And then enabled by
+ * kernel stage or any state where user use it.
+ */
+ writel(0x03c703c7, SYS_GRF_BASE + SYS_GRF_SOC_CON6);
if (readl(BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L) == 0x2222) {
/* Set the fspi m0 io ds level to 55ohm */
@@ -922,7 +947,14 @@
writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L);
writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_H);
#endif
-
+ /*
+ * set VOP M0 and VOP M1 to priority 0x303,then
+ * Peri > VOP/MCU > ISP/VICAP > other
+ * Note: VOP priority can only be modified during the u-boot stage,
+ * as VOP default power down, and power up after trust.
+ */
+ writel(QOS_PRIORITY_LEVEL(3, 3), VOP_M0_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(3, 3), VOP_M1_PRIORITY_REG);
#endif
/* Select usb otg0 phy status to 0 that make rockusb can work at high-speed */
@@ -1245,31 +1277,36 @@
#ifdef CONFIG_SPL_BUILD
int spl_fit_standalone_release(char *id, uintptr_t entry_point)
{
- /* gpll enable */
- writel(0x00f00042, 0xfd7c01c4);
+ u32 val;
+
+ /* pmu m0 configuration: */
+ /* set gpll */
+ writel(0x00f00042, CRU_BASE + CRU_GPLL_CON1);
+ /* set pmu mcu to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST19_REG);
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST19_REG);
+ /* set pmu mcu to access system memory */
+ val = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST19_REG);
+ writel(val & 0x000000ff, FIREWALL_SYSMEM_BASE + FW_SYSM_MST19_REG);
+ /* set pmu mcu to secure */
+ writel(0x00080000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON0);
/* set start addr, pmu_mcu_code_addr_start */
- writel(0xFFFF0000 | (entry_point >> 16), 0xFD582024);
- /* pmu_mcu_sram_addr_start */
- writel(0xFFFF2000, 0xFD582028);
- /* pmu_mcu_tcm_addr_start */
- writel(0xFFFF2000, 0xFD582034);
- /* set mcu secure */
- writel(0x00080000, 0xFD582000);
+ writel(0xFFFF0000 | (entry_point >> 16), PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON9);
+ /* set pmu_mcu_sram_addr_start */
+ writel(0xFFFF2000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON10);
+ /* set pmu_mcu_tcm_addr_start */
+ writel(0xFFFF2000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON13);
/* set cache cache_peripheral_addr */
- writel(0xffff0000, 0xFD582018);
- writel(0xffffee00, 0xFD58201c);
- writel(0x00ff00ff, 0xFD582020); /* 0xf0000000 ~ 0xfee00000 */
- /* mcupmu access DDR secure control, each bit for a region. */
- writel(0x0000ffff, 0xFE03008C);
- /* mcupmu access DDR secure control, each bit for a region. */
- writel(0x000000ff, 0xFE03808C);
- /* PMU WDT reset system enable */
- writel(0x02000200, 0xFD586008);
- /* WDT trigger global reset. */
- writel(0x08400840, 0xFD7C0C10);
- /* Spl helps to load the mcu image, but not need to release
- * mcu for rk3588.
- */
+ /* 0xf0000000 ~ 0xfee00000 */
+ writel(0xffff0000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON6);
+ writel(0xffffee00, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON7);
+ writel(0x00ff00ff, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON8);
+ /* enable PMU WDT reset system */
+ writel(0x02000200, BUS_SGRF_BASE + BUS_SGRF_SOC_CON2);
+ /* select WDT trigger global reset. */
+ writel(0x08400840, CRU_BASE + CRU_GLB_RST_CON);
+ /* release pmu mcu */
+ /* writel(0x20000000, PMU1CRU_BASE + PMU1CRU_SOFTRST_CON00); */
return 0;
}
--
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