From 04dd17822334871b23ea2862f7798fb0e0007777 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Sat, 11 May 2024 08:53:19 +0000
Subject: [PATCH] change otg to host mode
---
kernel/drivers/staging/mt7621-dts/mt7621.dtsi | 199 ++++++++++++++++++++++++++++++++++++++++---------
1 files changed, 163 insertions(+), 36 deletions(-)
diff --git a/kernel/drivers/staging/mt7621-dts/mt7621.dtsi b/kernel/drivers/staging/mt7621-dts/mt7621.dtsi
index 9891e53..91a7fa7 100644
--- a/kernel/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/kernel/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -1,4 +1,5 @@
#include <dt-bindings/interrupt-controller/mips-gic.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
@@ -40,6 +41,30 @@
/* This is normally 1/4 of cpuclock */
clock-frequency = <220000000>;
+ };
+
+ mmc_clock: mmc_clock@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <48000000>;
+ };
+
+ mmc_fixed_3v3: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_power";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ mmc_fixed_1v8_io: fixedregulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ enable-active-high;
+ regulator-always-on;
};
palmbus: palmbus@1E000000 {
@@ -113,7 +138,7 @@
memc: memc@5000 {
compatible = "mtk,mt7621-memc";
- reg = <0x300 0x100>;
+ reg = <0x5000 0x1000>;
};
cpc: cpc@1fbf0000 {
@@ -202,84 +227,84 @@
state_default: pinctrl0 {
};
- i2c_pins: i2c {
- i2c {
- group = "i2c";
+ i2c_pins: i2c0 {
+ i2c0 {
+ groups = "i2c";
function = "i2c";
};
};
- spi_pins: spi {
- spi {
- group = "spi";
+ spi_pins: spi0 {
+ spi0 {
+ groups = "spi";
function = "spi";
};
};
uart1_pins: uart1 {
uart1 {
- group = "uart1";
+ groups = "uart1";
function = "uart1";
};
};
uart2_pins: uart2 {
uart2 {
- group = "uart2";
+ groups = "uart2";
function = "uart2";
};
};
uart3_pins: uart3 {
uart3 {
- group = "uart3";
+ groups = "uart3";
function = "uart3";
};
};
rgmii1_pins: rgmii1 {
rgmii1 {
- group = "rgmii1";
+ groups = "rgmii1";
function = "rgmii1";
};
};
rgmii2_pins: rgmii2 {
rgmii2 {
- group = "rgmii2";
+ groups = "rgmii2";
function = "rgmii2";
};
};
- mdio_pins: mdio {
- mdio {
- group = "mdio";
+ mdio_pins: mdio0 {
+ mdio0 {
+ groups = "mdio";
function = "mdio";
};
};
- pcie_pins: pcie {
- pcie {
- group = "pcie";
- function = "pcie rst";
+ pcie_pins: pcie0 {
+ pcie0 {
+ groups = "pcie";
+ function = "gpio";
};
};
- nand_pins: nand {
+ nand_pins: nand0 {
spi-nand {
- group = "spi";
+ groups = "spi";
function = "nand1";
};
sdhci-nand {
- group = "sdhci";
+ groups = "sdhci";
function = "nand2";
};
};
- sdhci_pins: sdhci {
- sdhci {
- group = "sdhci";
+ sdhci_pins: sdhci0 {
+ sdhci0 {
+ groups = "sdhci";
function = "sdhci";
};
};
@@ -298,8 +323,23 @@
sdhci: sdhci@1E130000 {
status = "disabled";
- compatible = "ralink,mt7620-sdhci";
+ compatible = "mediatek,mt7620-mmc";
reg = <0x1E130000 0x4000>;
+
+ bus-width = <4>;
+ max-frequency = <48000000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ vmmc-supply = <&mmc_fixed_3v3>;
+ vqmmc-supply = <&mmc_fixed_1v8_io>;
+ disable-wp;
+
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&sdhci_pins>;
+ pinctrl-1 = <&sdhci_pins>;
+
+ clocks = <&mmc_clock &mmc_clock>;
+ clock-names = "source", "hclk";
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
@@ -372,15 +412,88 @@
mediatek,ethsys = <ðsys>;
- mediatek,switch = <&gsw>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ status = "off";
+ phy-mode = "rgmii-rxid";
+ };
mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
- phy1f: ethernet-phy@1f {
- reg = <0x1f>;
- phy-mode = "rgmii";
+ switch0: switch0@0 {
+ compatible = "mediatek,mt7621";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ mediatek,mcm;
+ resets = <&rstctrl 2>;
+ reset-names = "mcm";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ port@0 {
+ status = "off";
+ reg = <0>;
+ label = "lan0";
+ };
+
+ port@1 {
+ status = "off";
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ status = "off";
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ status = "off";
+ reg = <3>;
+ label = "lan3";
+ };
+
+ port@4 {
+ status = "off";
+ reg = <4>;
+ label = "lan4";
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "trgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
};
};
};
@@ -398,7 +511,6 @@
0x1e142000 0x100 /* pcie port 0 RC control registers */
0x1e143000 0x100 /* pcie port 1 RC control registers */
0x1e144000 0x100>; /* pcie port 2 RC control registers */
-
#address-cells = <3>;
#size-cells = <2>;
@@ -413,11 +525,10 @@
0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
>;
- #interrupt-cells = <1>;
- interrupt-map-mask = <0xF0000 0 0 1>;
- interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
- <0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
- <0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
+ GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
+ GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -425,6 +536,10 @@
reset-names = "pcie0", "pcie1", "pcie2";
clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
clock-names = "pcie0", "pcie1", "pcie2";
+ phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
+ phy-names = "pcie-phy0", "pcie-phy2";
+
+ reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
@@ -450,4 +565,16 @@
bus-range = <0x00 0xff>;
};
};
+
+ pcie0_phy: pcie-phy@1e149000 {
+ compatible = "mediatek,mt7621-pci-phy";
+ reg = <0x1e149000 0x0700>;
+ #phy-cells = <1>;
+ };
+
+ pcie2_phy: pcie-phy@1e14a000 {
+ compatible = "mediatek,mt7621-pci-phy";
+ reg = <0x1e14a000 0x0700>;
+ #phy-cells = <1>;
+ };
};
--
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