From 04dd17822334871b23ea2862f7798fb0e0007777 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Sat, 11 May 2024 08:53:19 +0000
Subject: [PATCH] change otg to host mode
---
kernel/arch/arm64/boot/dts/rockchip/rk3368.dtsi | 1544 +++++-----------------------------------------------------
1 files changed, 150 insertions(+), 1,394 deletions(-)
diff --git a/kernel/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/kernel/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 04fd195..cf6b66e 100644
--- a/kernel/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/kernel/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -8,16 +8,8 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/power/rk3368-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
-#include <dt-bindings/soc/rockchip-system-status.h>
-#include <dt-bindings/suspend/rockchip-rk3368.h>
#include <dt-bindings/thermal/thermal.h>
-#include <dt-bindings/display/mipi_dsi.h>
-#include <dt-bindings/display/drm_mipi_dsi.h>
-#include <dt-bindings/display/media-bus-format.h>
-
-#include "rk3368-dram-default-timing.dtsi"
/ {
compatible = "rockchip,rk3368";
@@ -27,15 +19,16 @@
aliases {
ethernet0 = &gmac;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
- mmc0 = &sdmmc;
- mmc1 = &sdio0;
- mmc2 = &emmc;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -53,21 +46,6 @@
cpu-map {
cluster0 {
core0 {
- cpu = <&cpu_l0>;
- };
- core1 {
- cpu = <&cpu_l1>;
- };
- core2 {
- cpu = <&cpu_l2>;
- };
- core3 {
- cpu = <&cpu_l3>;
- };
- };
-
- cluster1 {
- core0 {
cpu = <&cpu_b0>;
};
core1 {
@@ -80,333 +58,89 @@
cpu = <&cpu_b3>;
};
};
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu_l0>;
+ };
+ core1 {
+ cpu = <&cpu_l1>;
+ };
+ core2 {
+ cpu = <&cpu_l2>;
+ };
+ core3 {
+ cpu = <&cpu_l3>;
+ };
+ };
};
cpu_l0: cpu@0 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
- clocks = <&cru ARMCLKL>;
- next-level-cache = <&cluster0_l2>;
- operating-points-v2 = <&cluster0_opp>;
- sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
#cooling-cells = <2>; /* min followed by max */
- dynamic-power-coefficient = <149>;
};
cpu_l1: cpu@1 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
- clocks = <&cru ARMCLKL>;
- next-level-cache = <&cluster0_l2>;
- operating-points-v2 = <&cluster0_opp>;
- sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_l2: cpu@2 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
- clocks = <&cru ARMCLKL>;
- next-level-cache = <&cluster0_l2>;
- operating-points-v2 = <&cluster0_opp>;
- sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_l3: cpu@3 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
- clocks = <&cru ARMCLKL>;
- next-level-cache = <&cluster0_l2>;
- operating-points-v2 = <&cluster0_opp>;
- sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_b0: cpu@100 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
enable-method = "psci";
- clocks = <&cru ARMCLKB>;
- next-level-cache = <&cluster1_l2>;
- operating-points-v2 = <&cluster1_opp>;
- sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
#cooling-cells = <2>; /* min followed by max */
- dynamic-power-coefficient = <160>;
};
cpu_b1: cpu@101 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
enable-method = "psci";
- clocks = <&cru ARMCLKB>;
- next-level-cache = <&cluster1_l2>;
- operating-points-v2 = <&cluster1_opp>;
- sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_b2: cpu@102 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
enable-method = "psci";
- clocks = <&cru ARMCLKB>;
- next-level-cache = <&cluster1_l2>;
- operating-points-v2 = <&cluster1_opp>;
- sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
+ #cooling-cells = <2>; /* min followed by max */
};
cpu_b3: cpu@103 {
device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
+ compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
enable-method = "psci";
- clocks = <&cru ARMCLKB>;
- next-level-cache = <&cluster1_l2>;
- operating-points-v2 = <&cluster1_opp>;
- sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
- };
-
- cluster0_l2: l2-cache0 {
- compatible = "cache";
- };
-
- cluster1_l2: l2-cache1 {
- compatible = "cache";
+ #cooling-cells = <2>; /* min followed by max */
};
};
- cluster0_opp: opp_table0 {
- compatible = "operating-points-v2";
- opp-shared;
- rockchip,leakage-voltage-sel = <
- 1 24 0
- 25 254 1
- >;
- nvmem-cells = <&cpu_leakage>, <&leakage_temp>, <&leakage_volt>;
- nvmem-cell-names = "cpu_leakage", "leakage_temp",
- "leakage_volt";
- rockchip,reboot-freq = <816000>;
-
- opp-216000000 {
- opp-hz = /bits/ 64 <216000000>;
- opp-microvolt = <950000 950000 1350000>;
- opp-microvolt-L0 = <1050000 1050000 1350000>;
- opp-microvolt-L1 = <950000 950000 1350000>;
- clock-latency-ns = <40000>;
- opp-suspend;
- };
- opp-408000000 {
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <950000 950000 1350000>;
- opp-microvolt-L0 = <1050000 1050000 1350000>;
- opp-microvolt-L1 = <950000 950000 1350000>;
- clock-latency-ns = <40000>;
- };
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <950000 950000 1350000>;
- opp-microvolt-L0 = <1050000 1050000 1350000>;
- opp-microvolt-L1 = <950000 950000 1350000>;
- clock-latency-ns = <40000>;
- };
- opp-816000000 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <1025000 1025000 1350000>;
- opp-microvolt-L0 = <1125000 1125000 1350000>;
- opp-microvolt-L1 = <1025000 1025000 1350000>;
- clock-latency-ns = <40000>;
- };
- opp-1008000000 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1125000 1125000 1350000>;
- opp-microvolt-L0 = <1225000 1225000 1350000>;
- opp-microvolt-L1 = <1125000 1125000 1350000>;
- clock-latency-ns = <40000>;
- };
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1225000 1225000 1350000>;
- opp-microvolt-L0 = <1325000 1325000 1350000>;
- opp-microvolt-L1 = <1225000 1225000 1350000>;
- clock-latency-ns = <40000>;
- };
- };
-
- cluster1_opp: opp_table1 {
- compatible = "operating-points-v2";
- opp-shared;
- rockchip,avs-sclae = <36>;
- rockchip,leakage-scaling-sel = <
- 1 24 36
- 25 254 0
- >;
- clocks = <&cru PLL_APLLB>;
- rockchip,leakage-voltage-sel = <
- 1 24 0
- 25 50 1
- 51 254 2
- >;
- nvmem-cells = <&cpu_leakage>, <&leakage_temp>, <&leakage_volt>;
- nvmem-cell-names = "cpu_leakage", "leakage_temp",
- "leakage_volt";
- rockchip,reboot-freq = <816000>;
-
- opp-216000000 {
- opp-hz = /bits/ 64 <216000000>;
- opp-microvolt = <950000 950000 1350000>;
- opp-microvolt-L0 = <1050000 1050000 1350000>;
- opp-microvolt-L1 = <950000 950000 1350000>;
- opp-microvolt-L2 = <950000 950000 1350000>;
- clock-latency-ns = <40000>;
- opp-suspend;
- };
- opp-408000000 {
- opp-hz = /bits/ 64 <408000000>;
- opp-microvolt = <950000 950000 1350000>;
- opp-microvolt-L0 = <1050000 1050000 1350000>;
- opp-microvolt-L1 = <950000 950000 1350000>;
- opp-microvolt-L2 = <950000 950000 1350000>;
- clock-latency-ns = <40000>;
- };
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <950000 950000 1350000>;
- opp-microvolt-L0 = <1050000 1050000 1350000>;
- opp-microvolt-L1 = <950000 950000 1350000>;
- opp-microvolt-L2 = <950000 950000 1350000>;
- clock-latency-ns = <40000>;
- };
- opp-816000000 {
- opp-hz = /bits/ 64 <816000000>;
- opp-microvolt = <975000 975000 1350000>;
- opp-microvolt-L0 = <1075000 1075000 1350000>;
- opp-microvolt-L1 = <975000 975000 1350000>;
- opp-microvolt-L2 = <975000 975000 1350000>;
- clock-latency-ns = <40000>;
- };
- opp-1008000000 {
- opp-hz = /bits/ 64 <1008000000>;
- opp-microvolt = <1050000 1050000 1350000>;
- opp-microvolt-L0 = <1150000 1150000 1350000>;
- opp-microvolt-L1 = <1050000 1050000 1350000>;
- opp-microvolt-L2 = <1025000 1025000 1350000>;
- clock-latency-ns = <40000>;
- };
- opp-1200000000 {
- opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1150000 1150000 1350000>;
- opp-microvolt-L0 = <1250000 1250000 1350000>;
- opp-microvolt-L1 = <1150000 1150000 1350000>;
- opp-microvolt-L2 = <1125000 1125000 1350000>;
- clock-latency-ns = <40000>;
- };
- opp-1296000000 {
- opp-hz = /bits/ 64 <1296000000>;
- opp-microvolt = <1225000 1225000 1350000>;
- opp-microvolt-L0 = <1350000 1350000 1350000>;
- opp-microvolt-L1 = <1225000 1225000 1350000>;
- opp-microvolt-L2 = <1200000 1200000 1350000>;
- clock-latency-ns = <40000>;
- };
- opp-1416000000 {
- opp-hz = /bits/ 64 <1416000000>;
- opp-microvolt = <1300000 1300000 1350000>;
- opp-microvolt-L0 = <1350000 1350000 1350000>;
- opp-microvolt-L1 = <1300000 1300000 1350000>;
- opp-microvolt-L2 = <1275000 1275000 1350000>;
- clock-latency-ns = <40000>;
- };
- opp-1512000000 {
- opp-hz = /bits/ 64 <1512000000>;
- opp-microvolt = <1350000 1350000 1350000>;
- opp-microvolt-L0 = <1350000 1350000 1350000>;
- opp-microvolt-L1 = <1350000 1350000 1350000>;
- opp-microvolt-L2 = <1325000 1325000 1350000>;
- clock-latency-ns = <40000>;
- };
- };
-
- energy-costs {
- RK3368_CPU_COST_0: rk3368-core-cost0 {
- busy-cost-data = <
- 146 44 /* 216M */
- 276 72 /* 408M */
- 406 99 /* 600M */
- 552 147 /* 816M */
- 682 200 /* 1008M */
- 812 255 /* 1200M */
- >;
- idle-cost-data = <
- 6
- 6
- 0
- >;
- };
-
- RK3368_CPU_COST_1: rk3368-core-cost1 {
- busy-cost-data = <
- 146 53 /* 216M */
- 276 86 /* 408M */
- 406 118 /* 600M */
- 552 166 /* 816M */
- 682 226 /* 1008M */
- 812 309 /* 1200M */
- 878 371 /* 1200M */
- 959 446 /* 1416M */
- 1024 513 /* 1512M */
- >;
- idle-cost-data = <
- 6
- 6
- 0
- >;
- };
-
- RK3368_CLUSTER_COST_0: rk3368-cluster-cost0 {
- busy-cost-data = <
- 146 9 /* 216M */
- 276 14 /* 408M */
- 406 20 /* 600M */
- 552 29 /* 816M */
- 682 40 /* 1008M */
- 812 51 /* 1200M */
- >;
- idle-cost-data = <
- 56
- 56
- 56
- >;
- };
-
- RK3368_CLUSTER_COST_1: rk3368-cluster-cost1 {
- busy-cost-data = <
- 146 11 /* 216M */
- 276 17 /* 408M */
- 406 24 /* 600M */
- 552 33 /* 816M */
- 682 45 /* 1008M */
- 812 62 /* 1200M */
- 878 74 /* 1200M */
- 959 89 /* 1416M */
- 1024 103 /* 1512M */
- >;
- idle-cost-data = <
- 56
- 56
- 56
- >;
- };
- };
-
- amba {
+ amba: bus {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
@@ -452,13 +186,6 @@
<&cpu_b2>, <&cpu_b3>;
};
- firmware {
- optee: optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
-
psci {
compatible = "arm,psci-0.2";
method = "smc";
@@ -483,7 +210,7 @@
#clock-cells = <0>;
};
- sdmmc: dwmmc@ff0c0000 {
+ sdmmc: mmc@ff0c0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0c0000 0x0 0x4000>;
max-frequency = <150000000>;
@@ -497,7 +224,7 @@
status = "disabled";
};
- sdio0: dwmmc@ff0d0000 {
+ sdio0: mmc@ff0d0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0d0000 0x0 0x4000>;
max-frequency = <150000000>;
@@ -511,7 +238,7 @@
status = "disabled";
};
- emmc: dwmmc@ff0f0000 {
+ emmc: mmc@ff0f0000 {
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff0f0000 0x0 0x4000>;
max-frequency = <150000000>;
@@ -571,19 +298,6 @@
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c0: i2c@ff650000 {
- compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
- reg = <0x0 0xff650000 0x0 0x1000>;
- clocks = <&cru PCLK_I2C0>;
- clock-names = "i2c";
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_xfer>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -689,25 +403,64 @@
status = "disabled";
};
- thermal_zones: thermal-zones {
- soc_thermal: soc-thermal {
- polling-delay-passive = <200>; /* milliseconds */
- polling-delay = <200>; /* milliseconds */
- sustainable-power = <600>; /* milliwatts */
+ thermal-zones {
+ cpu {
+ polling-delay-passive = <100>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
thermal-sensors = <&tsadc 0>;
+
trips {
- threshold: trip-point-0 {
- temperature = <70000>; /* millicelsius */
+ cpu_alert0: cpu_alert0 {
+ temperature = <75000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
- target: trip-point-1 {
+ cpu_alert1: cpu_alert1 {
temperature = <80000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
- soc_crit: soc-crit {
+ cpu_crit: cpu_crit {
+ temperature = <95000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu_alert1>;
+ cooling-device =
+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu {
+ polling-delay-passive = <100>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 1>;
+
+ trips {
+ gpu_alert0: gpu_alert0 {
+ temperature = <80000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ gpu_crit: gpu_crit {
temperature = <115000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
@@ -716,46 +469,31 @@
cooling-maps {
map0 {
- trip = <&target>;
+ trip = <&gpu_alert0>;
cooling-device =
- <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- contribution = <1024>;
- };
- map1 {
- trip = <&target>;
- cooling-device =
- <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- contribution = <1024>;
- };
- map2 {
- trip = <&target>;
- cooling-device =
- <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- contribution = <1024>;
+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
- };
-
- gpu_thermal: gpu-thermal {
- polling-delay-passive = <200>; /* milliseconds */
- polling-delay = <200>; /* milliseconds */
- thermal-sensors = <&tsadc 1>;
};
};
tsadc: tsadc@ff280000 {
- compatible = "rockchip,rk3368-tsadc-legacy";
+ compatible = "rockchip,rk3368-tsadc";
reg = <0x0 0xff280000 0x0 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
- clock-frequency = <32768>;
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
- nvmem-cells = <&temp_adjust>;
- nvmem-cell-names = "temp_adjust";
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&otp_pin>;
+ pinctrl-1 = <&otp_out>;
+ pinctrl-2 = <&otp_pin>;
#thermal-sensor-cells = <1>;
- hw-shut-temp = <95000>;
+ rockchip,hw-tshut-temp = <95000>;
status = "disabled";
};
@@ -776,35 +514,11 @@
status = "disabled";
};
- nandc0: nandc@ff400000 {
- compatible = "rockchip,rk-nandc";
- reg = <0x0 0xff400000 0x0 0x4000>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- nandc_id = <0>;
- clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
- clock-names = "clk_nandc", "hclk_nandc";
- status = "disabled";
- };
-
usb_host0_ehci: usb@ff500000 {
compatible = "generic-ehci";
- reg = <0x0 0xff500000 0x0 0x20000>;
+ reg = <0x0 0xff500000 0x0 0x100>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST0>, <&u2phy>;
- clock-names = "usbhost", "utmi";
- phys = <&u2phy_host>;
- phy-names = "usb";
- status = "disabled";
- };
-
- usb_host0_ohci: usb@ff520000 {
- compatible = "generic-ohci";
- reg = <0x0 0xff520000 0x0 0x20000>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST0>, <&u2phy>;
- clock-names = "usbhost", "utmi";
- phys = <&u2phy_host>;
- phy-names = "usb";
+ clocks = <&cru HCLK_HOST0>;
status = "disabled";
};
@@ -817,17 +531,22 @@
clock-names = "otg";
dr_mode = "otg";
g-np-tx-fifo-size = <16>;
- g-rx-fifo-size = <280>;
- g-tx-fifo-size = <256 128 128 64 32 16>;
- g-use-dma;
- phys = <&u2phy_otg>;
- phy-names = "usb2-phy";
+ g-rx-fifo-size = <275>;
+ g-tx-fifo-size = <256 128 128 64 64 32>;
status = "disabled";
};
- ddrpctl: syscon@ff610000 {
- compatible = "rockchip,rk3368-ddrpctl", "syscon";
- reg = <0x0 0xff610000 0x0 0x400>;
+ i2c0: i2c@ff650000 {
+ compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
+ reg = <0x0 0xff650000 0x0 0x1000>;
+ clocks = <&cru PCLK_I2C0>;
+ clock-names = "i2c";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
};
i2c1: i2c@ff660000 {
@@ -911,196 +630,6 @@
status = "disabled";
};
- mailbox: mailbox@ff6b0000 {
- compatible = "rockchip,rk3368-mbox-legacy";
- reg = <0x0 0xff6b0000 0x0 0x1000>,
- <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
- interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_MAILBOX>;
- clock-names = "pclk_mailbox";
- #mbox-cells = <1>;
- status = "disabled";
- };
-
- mailbox_scpi: mailbox-scpi {
- compatible = "rockchip,rk3368-scpi-legacy";
- mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
- chan-nums = <3>;
- status = "disabled";
- };
-
- qos_iep: qos@ffad0000 {
- compatible = "syscon";
- reg = <0x0 0xffad0000 0x0 0x20>;
- };
-
- qos_isp_r0: qos@ffad0080 {
- compatible = "syscon";
- reg = <0x0 0xffad0080 0x0 0x20>;
- };
-
- qos_isp_r1: qos@ffad0100 {
- compatible = "syscon";
- reg = <0x0 0xffad0100 0x0 0x20>;
- };
-
- qos_isp_w0: qos@ffad0180 {
- compatible = "syscon";
- reg = <0x0 0xffad0180 0x0 0x20>;
- };
-
- qos_isp_w1: qos@ffad0200 {
- compatible = "syscon";
- reg = <0x0 0xffad0200 0x0 0x20>;
- };
-
- qos_vip: qos@ffad0280 {
- compatible = "syscon";
- reg = <0x0 0xffad0280 0x0 0x20>;
- };
-
- qos_vop: qos@ffad0300 {
- compatible = "syscon";
- reg = <0x0 0xffad0300 0x0 0x20>;
- };
-
- qos_rga_r: qos@ffad0380 {
- compatible = "syscon";
- reg = <0x0 0xffad0380 0x0 0x20>;
- };
-
- qos_rga_w: qos@ffad0400 {
- compatible = "syscon";
- reg = <0x0 0xffad0400 0x0 0x20>;
- };
-
- qos_hevc_r: qos@ffae0000 {
- compatible = "syscon";
- reg = <0x0 0xffae0000 0x0 0x20>;
- };
-
- qos_vpu_r: qos@ffae0100 {
- compatible = "syscon";
- reg = <0x0 0xffae0100 0x0 0x20>;
- };
-
- qos_vpu_w: qos@ffae0180 {
- compatible = "syscon";
- reg = <0x0 0xffae0180 0x0 0x20>;
- };
-
- qos_gpu: qos@ffaf0000 {
- compatible = "syscon";
- reg = <0x0 0xffaf0000 0x0 0x20>;
- };
-
- pmu: power-management@ff730000 {
- compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
- reg = <0x0 0xff730000 0x0 0x1000>;
-
- power: power-controller {
- compatible = "rockchip,rk3368-power-controller";
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /*
- * Note: Although SCLK_* are the working clocks
- * of device without including on the NOC, needed for
- * synchronous reset.
- *
- * The clocks on the which NOC:
- * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
- * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
- * ACLK_RGA is on ACLK_RGA_NIU.
- * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
- *
- * Which clock are device clocks:
- * clocks devices
- * *_IEP IEP:Image Enhancement Processor
- * *_ISP ISP:Image Signal Processing
- * *_VIP VIP:Video Input Processor
- * *_VOP* VOP:Visual Output Processor
- * *_RGA RGA
- * *_EDP* EDP
- * *_DPHY* LVDS
- * *_HDMI HDMI
- * *_MIPI_* MIPI
- */
- pd_vio@RK3368_PD_VIO {
- reg = <RK3368_PD_VIO>;
- clocks = <&cru ACLK_IEP>,
- <&cru ACLK_ISP>,
- <&cru ACLK_VIP>,
- <&cru ACLK_RGA>,
- <&cru ACLK_VOP>,
- <&cru ACLK_VOP_IEP>,
- <&cru DCLK_VOP>,
- <&cru HCLK_IEP>,
- <&cru HCLK_ISP>,
- <&cru HCLK_RGA>,
- <&cru HCLK_VIP>,
- <&cru HCLK_VOP>,
- <&cru HCLK_VIO_HDCPMMU>,
- <&cru PCLK_EDP_CTRL>,
- <&cru PCLK_HDMI_CTRL>,
- <&cru PCLK_HDCP>,
- <&cru PCLK_ISP>,
- <&cru PCLK_VIP>,
- <&cru PCLK_DPHYRX>,
- <&cru PCLK_DPHYTX0>,
- <&cru PCLK_MIPI_CSI>,
- <&cru PCLK_MIPI_DSI0>,
- <&cru SCLK_VOP0_PWM>,
- <&cru SCLK_EDP_24M>,
- <&cru SCLK_EDP>,
- <&cru SCLK_HDCP>,
- <&cru SCLK_ISP>,
- <&cru SCLK_RGA>,
- <&cru SCLK_HDMI_CEC>,
- <&cru SCLK_HDMI_HDCP>;
- pm_qos = <&qos_iep>,
- <&qos_isp_r0>,
- <&qos_isp_r1>,
- <&qos_isp_w0>,
- <&qos_isp_w1>,
- <&qos_vip>,
- <&qos_vop>,
- <&qos_rga_r>,
- <&qos_rga_w>;
- };
- /*
- * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
- * (video endecoder & decoder) clocks that on the
- * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
- */
- pd_video@RK3368_PD_VIDEO {
- reg = <RK3368_PD_VIDEO>;
- clocks = <&cru ACLK_VIDEO>,
- <&cru HCLK_VIDEO>,
- <&cru SCLK_HEVC_CABAC>,
- <&cru SCLK_HEVC_CORE>;
- pm_qos = <&qos_hevc_r>,
- <&qos_vpu_r>,
- <&qos_vpu_w>;
- };
- /*
- * Note: ACLK_GPU is the GPU clock,
- * and on the ACLK_GPU_NIU (NOC).
- */
- pd_gpu_1@RK3368_PD_GPU_1 {
- reg = <RK3368_PD_GPU_1>;
- clocks = <&cru ACLK_GPU_CFG>,
- <&cru ACLK_GPU_MEM>,
- <&cru SCLK_GPU_CORE>;
- pm_qos = <&qos_gpu>;
- };
- };
- };
-
pmugrf: syscon@ff738000 {
compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff738000 0x0 0x1000>;
@@ -1110,16 +639,7 @@
status = "disabled";
};
- pvtm_clock: pvtm-clock {
- compatible = "rockchip,rk3368-pvtm-clock";
- #clock-cells = <0>;
- clocks = <&cru SCLK_PVTM_PMU>;
- clock-names = "pvtm_pmu_clk";
- clock-output-names = "xin32k_pvtm";
- status = "okay";
- };
-
- reboot_mode: reboot-mode {
+ reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x200>;
mode-normal = <BOOT_NORMAL>;
@@ -1135,167 +655,15 @@
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
- assigned-clocks =
- <&cru ARMCLKL>, <&cru ARMCLKB>,
- <&cru PLL_GPLL>, <&cru PLL_CPLL>,
- <&cru ACLK_BUS>, <&cru ACLK_PERI>,
- <&cru HCLK_BUS>, <&cru HCLK_PERI>,
- <&cru PCLK_BUS>, <&cru PCLK_PERI>,
- <&cru ACLK_CCI_PRE>;
- assigned-clock-rates =
- <600000000>, <600000000>,
- <576000000>, <400000000>,
- <300000000>, <300000000>,
- <150000000>, <150000000>,
- <75000000>, <75000000>,
- <576000000>;
};
grf: syscon@ff770000 {
compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
reg = <0x0 0xff770000 0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
io_domains: io-domains {
compatible = "rockchip,rk3368-io-voltage-domain";
status = "disabled";
- };
-
- lvds: lvds {
- compatible = "rockchip,rk3368-lvds";
- phys = <&video_phy>;
- phy-names = "phy";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- lvds_in_vop: endpoint {
- remote-endpoint = <&vop_out_lvds>;
- };
- };
- };
- };
-
- rgb: rgb {
- compatible = "rockchip,rk3368-rgb";
- phys = <&video_phy>;
- phy-names = "phy";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&lcdc_rgb_pins>;
- pinctrl-1 = <&lcdc_sleep_pins>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- rgb_in_vop: endpoint {
- remote-endpoint = <&vop_out_rgb>;
- };
- };
- };
- };
-
- u2phy: usb2-phy@700 {
- compatible = "rockchip,rk3368-usb2phy";
- reg = <0x700 0x2c>;
- clocks = <&cru SCLK_OTGPHY0>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- clock-output-names = "usbotg_out";
- assigned-clocks = <&cru SCLK_USBPHY480M>;
- assigned-clock-parents = <&u2phy>;
- status = "disabled";
-
- u2phy_otg: otg-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "otg-bvalid", "otg-id",
- "linestate";
- status = "disabled";
- };
-
- u2phy_host: host-port {
- #phy-cells = <0>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "linestate";
- status = "disabled";
- };
- };
-
- dfi: dfi {
- compatible = "rockchip,rk3368-dfi";
- status = "disabled";
- };
- };
-
- dmc: dmc {
- compatible = "rockchip,rk3368-dmc";
- devfreq-events = <&dfi>;
- clocks = <&cru SCLK_DDRCLK>, <&cru PCLK_DDRPHY>,
- <&cru PCLK_DDRUPCTL>;
- clock-names = "dmc_clk", "pclk_phy", "pclk_upctl";
- ddr_timing = <&ddr_timing>;
- upthreshold = <50>;
- downdifferential = <20>;
- operating-points-v2 = <&dmc_opp_table>;
- vop-dclk-mode = <0>;
- system-status-freq = <
- /*system status freq(KHz)*/
- SYS_STATUS_NORMAL 600000
- SYS_STATUS_REBOOT 600000
- SYS_STATUS_SUSPEND 192000
- SYS_STATUS_VIDEO_1080P 300000
- SYS_STATUS_VIDEO_4K 600000
- SYS_STATUS_PERFORMANCE 600000
- SYS_STATUS_BOOST 396000
- SYS_STATUS_DUALVIEW 600000
- SYS_STATUS_ISP 528000
- >;
- auto-min-freq = <396000>;
- auto-freq-en = <0>;
- status = "disabled";
- };
-
- dmc_opp_table: opp_table2 {
- compatible = "operating-points-v2";
-
- opp-192000000 {
- opp-hz = /bits/ 64 <192000000>;
- opp-microvolt = <1100000>;
- };
-
- opp-240000000 {
- opp-hz = /bits/ 64 <240000000>;
- opp-microvolt = <1100000>;
- };
-
- opp-300000000 {
- opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <1100000>;
- };
- opp-396000000 {
- opp-hz = /bits/ 64 <396000000>;
- opp-microvolt = <1100000>;
- };
- opp-528000000 {
- opp-hz = /bits/ 64 <528000000>;
- opp-microvolt = <1100000>;
- };
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <1100000>;
};
};
@@ -1322,7 +690,7 @@
dmas = <&dmac_bus 3>;
dma-names = "tx";
pinctrl-names = "default";
- pinctrl-0 = <&spdif_bus>;
+ pinctrl-0 = <&spdif_tx>;
status = "disabled";
};
@@ -1334,8 +702,6 @@
clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
dmas = <&dmac_bus 6>, <&dmac_bus 7>;
dma-names = "tx", "rx";
- resets = <&cru SRST_I2S2CH>;
- reset-names = "reset-m";
status = "disabled";
};
@@ -1347,35 +713,8 @@
clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
dmas = <&dmac_bus 0>, <&dmac_bus 1>;
dma-names = "tx", "rx";
- resets = <&cru SRST_I2S8CH>;
- reset-names = "reset-m";
pinctrl-names = "default";
pinctrl-0 = <&i2s_8ch_bus>;
- status = "disabled";
- };
-
- rng: rng@ff8a0000 {
- compatible = "rockchip,cryptov1-rng";
- reg = <0x0 0xff8a0000 0x0 0x4000>;
-
- clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
- clock-names = "clk_crypto", "hclk_crypto";
- assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
- assigned-clock-rates = <150000000>, <100000000>;
- status = "disabled";
- };
-
- iep: iep@ff900000 {
- compatible = "rockchip,iep";
- iommu_enabled = <1>;
- iommus = <&iep_mmu>;
- reg = <0x0 0xff900000 0x0 0x800>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
- clock-names = "aclk_iep", "hclk_iep";
- power-domains = <&power RK3368_PD_VIO>;
- allocator = <1>;
- version = <2>;
status = "disabled";
};
@@ -1386,66 +725,7 @@
interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
- power-domains = <&power RK3368_PD_VIO>;
#iommu-cells = <0>;
- status = "disabled";
- };
-
- isp: isp@ff910000 {
- compatible = "rockchip,rk3368-isp", "rockchip,isp";
- reg = <0x0 0xff910000 0x0 0x4000>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&power RK3368_PD_VIO>;
- clocks =
- <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
- <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
- <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
- <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
- clock-names =
- "aclk_isp", "hclk_isp", "clk_isp",
- "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
- "clk_cif_pll", "hclk_mipiphy1",
- "pclk_dphyrx", "clk_vio0_noc";
-
- pinctrl-names =
- "default", "isp_dvp8bit2", "isp_dvp10bit",
- "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
- "isp_mipi_fl", "isp_mipi_fl_prefl",
- "isp_flash_as_gpio", "isp_flash_as_trigger_out";
- pinctrl-0 = <&cif_clkout>;
- pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
- pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
- pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
- pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
- pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
- pinctrl-6 = <&cif_clkout>;
- pinctrl-7 = <&cif_clkout &isp_prelight>;
- pinctrl-8 = <&isp_flash_trigger_as_gpio>;
- pinctrl-9 = <&isp_flash_trigger>;
- rockchip,isp,mipiphy = <2>;
- rockchip,isp,cifphy = <1>;
- rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
- rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
- rockchip,grf = <&grf>;
- rockchip,cru = <&cru>;
- rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
- rockchip,isp,iommu-enable = <1>;
- iommus = <&isp_mmu>;
- status = "disabled";
- };
-
- rkisp1: rkisp1@ff910000 {
- compatible = "rockchip,rk3368-rkisp1";
- reg = <0x0 0xff910000 0x0 0x4000>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "isp_irq";
- clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
- <&cru SCLK_ISP>, <&cru PCLK_ISP>;
- clock-names = "aclk_isp", "hclk_isp",
- "clk_isp", "pclk_isp";
- devfreq = <&dmc>;
- power-domains = <&power RK3368_PD_VIO>;
- iommus = <&isp_mmu>;
status = "disabled";
};
@@ -1458,62 +738,7 @@
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
- power-domains = <&power RK3368_PD_VIO>;
rockchip,disable-mmu-reset;
- status = "disabled";
- };
-
- vop: vop@ff930000 {
- compatible = "rockchip,rk3368-vop";
- rockchip,grf = <&grf>;
- reg = <0x0 0xff930000 0x0 0x2fc>, <0x0 0xff931000 0x0 0x400>;
- reg-names = "regs", "gamma_lut";
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
- clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
- assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
- assigned-clock-rates = <400000000>, <200000000>;
- resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
- reset-names = "axi", "ahb", "dclk";
- power-domains = <&power RK3368_PD_VIO>;
- iommus = <&vop_mmu>;
- status = "disabled";
-
- vop_out: port {
- #address-cells = <1>;
- #size-cells = <0>;
-
- vop_out_dsi: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&dsi_in_vop>;
- };
-
- vop_out_edp: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&edp_in_vop>;
- };
-
- vop_out_hdmi: endpoint@2 {
- reg = <2>;
- remote-endpoint = <&hdmi_in_vop>;
- };
-
- vop_out_lvds: endpoint@3 {
- reg = <3>;
- remote-endpoint = <&lvds_in_vop>;
- };
-
- vop_out_rgb: endpoint@4 {
- reg = <4>;
- remote-endpoint = <&rgb_in_vop>;
- };
- };
- };
-
- display_subsystem: display-subsystem {
- compatible = "rockchip,display-subsystem";
- ports = <&vop_out>;
- devfreq = <&dmc>;
status = "disabled";
};
@@ -1524,228 +749,7 @@
interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
- power-domains = <&power RK3368_PD_VIO>;
#iommu-cells = <0>;
- status = "disabled";
- };
-
- cif: cif@ff950000 {
- compatible = "rockchip,cif";
- reg = <0x0 0xff950000 0x0 0x400>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_VIP>, <&cru ACLK_VIP>, <&cru HCLK_VIP>,
- <&cru SCLK_VIP_SRC>, <&cru SCLK_VIP_OUT>;
- clock-names = "pclk_cif", "aclk_cif0", "hclk_cif0",
- "cif0_in", "cif0_out";
- resets = <&cru SRST_VIP>;
- reset-names = "rst_cif";
- pinctrl-names = "cif_pin_all";
- pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
- rockchip,grf = <&grf>;
- power-domains = <&power RK3368_PD_VIO>;
- iommus = <&vip_mmu>;
- status = "disabled";
- };
-
- cif_new: cif-new@ff950000 {
- compatible = "rockchip,rk3368-cif";
- reg = <0x0 0xff950000 0x0 0x400>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_VIP>, <&cru ACLK_VIP>, <&cru HCLK_VIP>,
- <&cru SCLK_VIP_SRC>, <&cru SCLK_VIP_OUT>;
- clock-names = "pclk_cif", "aclk_cif0", "hclk_cif0",
- "cif0_in", "cif0_out";
- resets = <&cru SRST_VIP>;
- reset-names = "rst_cif";
- rockchip,grf = <&grf>;
- power-domains = <&power RK3368_PD_VIO>;
- iommus = <&vip_mmu>;
- status = "disabled";
- };
-
- vip_mmu: iommu@ff950800{
- compatible = "rockchip,iommu";
- reg = <0x0 0xff950800 0x0 0x100>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vip_mmu";
- clocks = <&cru ACLK_VIP>, <&cru HCLK_VIP>;
- clock-names = "aclk", "hclk";
- rk_iommu,disable_reset_quirk;
- #iommu-cells = <0>;
- power-domains = <&power RK3368_PD_VIO>;
- status = "disabled";
- };
-
- dsi: dsi@ff960000 {
- compatible = "rockchip,rk3368-mipi-dsi";
- reg = <0x0 0xff960000 0x0 0x4000>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_MIPI_DSI0>, <&video_phy>;
- clock-names = "pclk", "hs_clk";
- resets = <&cru SRST_MIPIDSI0>;
- reset-names = "apb";
- phys = <&video_phy>;
- phy-names = "mipi_dphy";
- rockchip,grf = <&grf>;
- power-domains = <&power RK3368_PD_VIO>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- ports {
- port {
- dsi_in_vop: endpoint {
- remote-endpoint = <&vop_out_dsi>;
- };
- };
- };
- };
-
- video_phy: video-phy@ff968000 {
- compatible = "rockchip,rk3368-video-phy";
- reg = <0x0 0xff968000 0x0 0x4000>,
- <0x0 0xff960000 0x0 0x4000>;
- clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>,
- <&cru PCLK_MIPI_DSI0>;
- clock-names = "ref", "pclk_phy", "pclk_host";
- #clock-cells = <0>;
- resets = <&cru SRST_MIPIDPHYTX>;
- reset-names = "rst";
- power-domains = <&power RK3368_PD_VIO>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- mipi_dphy_rx0: mipi-dphy-rx0@ff96C000 {
- compatible = "rockchip,rk3368-mipi-dphy";
- reg = <0x0 0xff96C000 0x0 0x4000>;
- clocks = <&cru PCLK_DPHYRX>;
- clock-names = "pclk_dphyrx";
- power-domains = <&power RK3368_PD_VIO>;
- rockchip,grf = <&grf>;
- status = "disabled";
- };
-
- edp: edp@ff970000 {
- compatible = "rockchip,rk3368-edp";
- reg = <0x0 0xff970000 0x0 0x8000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
- clock-names = "dp", "pclk";
- assigned-clocks = <&cru SCLK_EDP_24M>;
- assigned-clock-parents = <&xin24m>;
- resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
- reset-names = "dp", "apb";
- power-domains = <&power RK3368_PD_VIO>;
- rockchip,grf = <&grf>;
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- edp_in_vop: endpoint {
- remote-endpoint = <&vop_out_edp>;
- };
- };
- };
- };
-
- hdmi: hdmi@ff980000 {
- compatible = "rockchip,rk3368-dw-hdmi";
- reg = <0x0 0xff980000 0x0 0x20000>;
- reg-io-width = <4>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
- clock-names = "iahb", "isfr", "cec";
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_i2c_xfer>, <&hdmi_cec>;
- resets = <&cru SRST_HDMI>;
- reset-names = "hdmi";
- power-domains = <&power RK3368_PD_VIO>;
- rockchip,grf = <&grf>;
- status = "disabled";
-
- ports {
- port {
- hdmi_in_vop: endpoint {
- remote-endpoint = <&vop_out_hdmi>;
- };
- };
- };
- };
-
- mpp_srv: mpp-srv {
- compatible = "rockchip,mpp-service";
- rockchip,taskqueue-count = <1>;
- rockchip,resetgroup-count = <1>;
- rockchip,grf = <&grf>;
- rockchip,grf-offset = <0x0418>;
- rockchip,grf-values = <0x10001000>, <0x10000000>, <0x10000000>;
- rockchip,grf-names = "grf_rkvdec", "grf_vdpu1", "grf_vepu1";
- status = "disabled";
- };
-
- hevc: hevc_service@ff9a0000 {
- compatible = "rockchip,hevc-decoder-rk3368";
- reg = <0x0 0xff9a0000 0x0 0x400>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_dec";
- clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
- <&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
- clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
- "clk_cabac";
- rockchip,normal-rates = <300000000>, <0>, <200000000>,
- <200000000>;
- rockchip,advanced-rates = <500000000>, <0>, <400000000>,
- <400000000>;
- resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
- <&cru SRST_VIDEO>;
- reset-names = "shared_video_a", "shared_video_h", "video_core";
- iommus = <&hevc_mmu>;
- rockchip,srv = <&mpp_srv>;
- rockchip,taskqueue-node = <0>;
- rockchip,resetgroup-node = <0>;
- power-domains = <&power RK3368_PD_VIDEO>;
- status = "disabled";
- };
-
- vepu: vepu@ff9a0000 {
- compatible = "rockchip,vpu-encoder-v1";
- reg = <0x0 0xff9a0000 0x0 0x400>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_enc";
- clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>;
- reset-names = "shared_video_a", "shared_video_h";
- iommus = <&vpu_mmu>;
- power-domains = <&power RK3368_PD_VIDEO>;
- rockchip,srv = <&mpp_srv>;
- rockchip,taskqueue-node = <0>;
- rockchip,resetgroup-node = <0>;
- status = "disabled";
- };
-
- vdpu: vdpu@ff9a0400 {
- compatible = "rockchip,vpu-decoder-rk3368";
- reg = <0x0 0xff9a0400 0x0 0x400>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "irq_dec";
- clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
- clock-names = "aclk_vcodec", "hclk_vcodec";
- rockchip,normal-rates = <300000000>, <0>;
- rockchip,advanced-rates = <600000000>, <0>;
- resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>;
- reset-names = "shared_video_a", "shared_video_h";
- iommus = <&vpu_mmu>;
- power-domains = <&power RK3368_PD_VIDEO>;
- rockchip,srv = <&mpp_srv>;
- rockchip,taskqueue-node = <0>;
- rockchip,resetgroup-node = <0>;
status = "disabled";
};
@@ -1757,7 +761,6 @@
interrupt-names = "hevc_mmu";
clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
clock-names = "aclk", "iface";
- power-domains = <&power RK3368_PD_VIDEO>;
#iommu-cells = <0>;
status = "disabled";
};
@@ -1765,14 +768,29 @@
vpu_mmu: iommu@ff9a0800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9a0800 0x0 0x100>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu_mmu", "vdpu_mmu";
clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
clock-names = "aclk", "iface";
- power-domains = <&power RK3368_PD_VIDEO>;
#iommu-cells = <0>;
status = "disabled";
+ };
+
+ efuse256: efuse@ffb00000 {
+ compatible = "rockchip,rk3368-efuse";
+ reg = <0x0 0xffb00000 0x0 0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru PCLK_EFUSE256>;
+ clock-names = "pclk_efuse";
+
+ cpu_leakage: cpu-leakage@17 {
+ reg = <0x17 0x1>;
+ };
+ temp_adjust: temp-adjust@1f {
+ reg = <0x1f 0x1>;
+ };
};
gic: interrupt-controller@ffb71000 {
@@ -1787,114 +805,6 @@
<0x0 0xffb76000 0x0 0x2000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- gpu: rogue-g6110@ffa30000 {
- compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
- reg = <0x0 0xffa30000 0x0 0x10000>;
- clocks =
- <&cru SCLK_GPU_CORE>,
- <&cru ACLK_GPU_MEM>,
- <&cru ACLK_GPU_CFG>;
- clock-names =
- "sclk_gpu_core",
- "aclk_gpu_mem",
- "aclk_gpu_cfg";
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "rogue-g6110-irq";
- power-domains = <&power RK3368_PD_GPU_1>;
- operating-points-v2 = <&gpu_opp_table>;
- #cooling-cells = <2>; /* min followed by max */
- gpu_power_model: power_model {
- compatible = "arm,mali-simple-power-model";
- voltage = <900>;
- frequency = <500>;
- static-power = <300>;
- dynamic-power = <396>;
- ts = <32000 4700 (-80) 2>;
- thermal-zone = "gpu-thermal";
- };
- };
-
- gpu_opp_table: gpu_opp_table {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-200000000 {
- opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <1100000>;
- };
- opp-288000000 {
- opp-hz = /bits/ 64 <288000000>;
- opp-microvolt = <1100000>;
- };
- opp-400000000 {
- opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <1100000>;
- };
- opp-576000000 {
- opp-hz = /bits/ 64 <576000000>;
- opp-microvolt = <1200000>;
- };
- };
-
- nocp_peri: nocp-peri@ffac1000 {
- compatible = "rockchip,rk3368-nocp";
- reg = <0x0 0xffac1000 0x0 0x400>;
- };
-
- nocp_core: nocp-core@ffac1400 {
- compatible = "rockchip,rk3368-nocp";
- reg = <0x0 0xffac1400 0x0 0x400>;
- };
-
- nocp_gpu: nocp-gpu@ffac1800 {
- compatible = "rockchip,rk3368-nocp";
- reg = <0x0 0xffac1800 0x0 0x400>;
- };
-
- nocp_vpu: nocp-vpu@ffac2000 {
- compatible = "rockchip,rk3368-nocp";
- reg = <0x0 0xffac2000 0x0 0x400>;
- };
-
- nocp_vop: nocp-vop@ffac2400 {
- compatible = "rockchip,rk3368-nocp";
- reg = <0x0 0xffac2400 0x0 0x400>;
- };
-
- nocp_rga: nocp-rga@ffac2800 {
- compatible = "rockchip,rk3368-nocp";
- reg = <0x0 0xffac2800 0x0 0x400>;
- };
-
- efuse: efuse@ffb00000 {
- compatible = "rockchip,rk3368-efuse";
- reg = <0x0 0xffb00000 0x0 0x20>;
- #address-cells = <1>;
- #size-cells = <1>;
- clocks = <&cru PCLK_EFUSE256>;
- clock-names = "pclk_efuse";
-
- /* Data cells */
- cpu_leakage: cpu-leakage@17 {
- reg = <0x17 0x1>;
- };
- leakage_volt: leakage-volt@1a {
- reg = <0x1a 0x1>;
- bits = <7 1>;
- };
- leakage_temp: leakage-temp@1e {
- reg = <0x1e 0x1>;
- bits = <1 7>;
- };
- temp_adjust: temp-adjust@1f {
- reg = <0x1f 0x1>;
- };
- };
-
- rockchip_system_monitor: rockchip-system-monitor {
- compatible = "rockchip,system-monitor";
};
pinctrl: pinctrl {
@@ -1974,12 +884,6 @@
drive-strength = <12>;
};
- edp {
- edp_hpd: edp-hpd {
- rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
- };
- };
-
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
@@ -2049,17 +953,6 @@
};
};
- hdmi {
- hdmi_cec: hdmi-cec {
- rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>;
- };
-
- hdmi_i2c_xfer: hdmi-i2c-xfer {
- rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>,
- <3 RK_PD3 1 &pcfg_pull_none>;
- };
- };
-
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
@@ -2111,11 +1004,8 @@
<2 RK_PC0 1 &pcfg_pull_none>,
<2 RK_PC1 1 &pcfg_pull_none>,
<2 RK_PC2 1 &pcfg_pull_none>,
- <2 RK_PC3 1 &pcfg_pull_none>;
- };
-
- i2s_8ch_mclk: i2s-8ch-mclk {
- rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
+ <2 RK_PC3 1 &pcfg_pull_none>,
+ <2 RK_PC4 1 &pcfg_pull_none>;
};
};
@@ -2220,8 +1110,8 @@
};
spdif {
- spdif_bus: spdif-bus {
- rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
+ spdif_tx: spdif-tx {
+ rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
};
};
@@ -2276,10 +1166,20 @@
};
};
+ tsadc {
+ otp_pin: otp-pin {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ otp_out: otp-out {
+ rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
+ };
+ };
+
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
- <2 RK_PD1 1 &pcfg_pull_up>;
+ <2 RK_PD1 1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
@@ -2294,7 +1194,7 @@
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
- <0 RK_PC5 3 &pcfg_pull_up>;
+ <0 RK_PC5 3 &pcfg_pull_none>;
};
uart1_cts: uart1-cts {
@@ -2309,7 +1209,7 @@
uart2 {
uart2_xfer: uart2-xfer {
rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
- <2 RK_PA5 2 &pcfg_pull_up>;
+ <2 RK_PA5 2 &pcfg_pull_none>;
};
/* no rts / cts for uart2 */
};
@@ -2317,7 +1217,7 @@
uart3 {
uart3_xfer: uart3-xfer {
rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
- <3 RK_PD6 2 &pcfg_pull_up>;
+ <3 RK_PD6 3 &pcfg_pull_none>;
};
uart3_cts: uart3-cts {
@@ -2332,7 +1232,7 @@
uart4 {
uart4_xfer: uart4-xfer {
rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
- <0 RK_PD2 3 &pcfg_pull_up>;
+ <0 RK_PD2 3 &pcfg_pull_none>;
};
uart4_cts: uart4-cts {
@@ -2343,149 +1243,5 @@
rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
};
};
-
- isp {
- cif_clkout: cif-clkout {
- rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;//cif_clkout
- };
-
- isp_dvp_d2d9: isp-dvp-d2d9 {
- rockchip,pins =
- <1 RK_PA0 1 &pcfg_pull_none>,//cif_data2
- <1 RK_PA1 1 &pcfg_pull_none>,//cif_data3
- <1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
- <1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
- <1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
- <1 RK_PA5 1 &pcfg_pull_none>,//cif_data7
- <1 RK_PA6 1 &pcfg_pull_none>,//cif_data8
- <1 RK_PA7 1 &pcfg_pull_none>,//cif_data9
- <1 RK_PB0 1 &pcfg_pull_none>,//cif_sync
- <1 RK_PB1 1 &pcfg_pull_none>,//cif_href
- <1 RK_PB2 1 &pcfg_pull_none>,//cif_clkin
- <1 RK_PB3 1 &pcfg_pull_none>;//cif_clkout
- };
-
- isp_dvp_d0d1: isp-dvp-d0d1 {
- rockchip,pins =
- <1 RK_PB4 1 &pcfg_pull_none>,//cif_data0
- <1 RK_PB5 1 &pcfg_pull_none>;//cif_data1
- };
-
- isp_dvp_d10d11:isp_d10d11 {
- rockchip,pins =
- <1 RK_PB6 1 &pcfg_pull_none>,//cif_data10
- <1 RK_PB7 1 &pcfg_pull_none>;//cif_data11
- };
-
- isp_dvp_d0d7: isp-dvp-d0d7 {
- rockchip,pins =
- <1 RK_PB4 1 &pcfg_pull_none>,//cif_data0
- <1 RK_PB5 1 &pcfg_pull_none>,//cif_data1
- <1 RK_PA0 1 &pcfg_pull_none>,//cif_data2
- <1 RK_PA1 1 &pcfg_pull_none>,//cif_data3
- <1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
- <1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
- <1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
- <1 RK_PA5 1 &pcfg_pull_none>;//cif_data7
- };
-
- isp_dvp_d4d11: isp-dvp-d4d11 {
- rockchip,pins =
- <1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
- <1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
- <1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
- <1 RK_PA5 1 &pcfg_pull_none>,//cif_data7
- <1 RK_PA6 1 &pcfg_pull_none>,//cif_data8
- <1 RK_PA7 1 &pcfg_pull_none>,//cif_data9
- <1 RK_PB6 1 &pcfg_pull_none>,//cif_data10
- <1 RK_PC1 1 &pcfg_pull_none>;//cif_data11
- };
-
- isp_shutter: isp-shutter {
- rockchip,pins =
- <3 RK_PC3 2 &pcfg_pull_none>, //SHUTTEREN
- <3 RK_PC6 2 &pcfg_pull_none>;//SHUTTERTRIG
- };
-
- isp_flash_trigger: isp-flash-trigger {
- rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
- };
-
- isp_prelight: isp-prelight {
- rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
- };
-
- isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
- rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
- };
- };
-
- lcdc {
- lcdc_rgb_pins: lcdc-rgb-pins {
- rockchip,pins =
- <0 RK_PB6 1 &pcfg_pull_none>, /* LCDC_D10 */
- <0 RK_PB7 1 &pcfg_pull_none>, /* LCDC_D11 */
- <0 RK_PC0 1 &pcfg_pull_none>, /* LCDC_D12 */
- <0 RK_PC1 1 &pcfg_pull_none>, /* LCDC_D13 */
- <0 RK_PC2 1 &pcfg_pull_none>, /* LCDC_D14 */
- <0 RK_PC3 1 &pcfg_pull_none>, /* LCDC_D15 */
- <0 RK_PC4 1 &pcfg_pull_none>, /* LCDC_D16 */
- <0 RK_PC5 1 &pcfg_pull_none>, /* LCDC_D17 */
- <0 RK_PC6 1 &pcfg_pull_none>, /* LCDC_D18 */
- <0 RK_PC7 1 &pcfg_pull_none>, /* LCDC_D19 */
- <0 RK_PD0 1 &pcfg_pull_none>, /* LCDC_D20 */
- <0 RK_PD1 1 &pcfg_pull_none>, /* LCDC_D21 */
- <0 RK_PD2 1 &pcfg_pull_none>, /* LCDC_D22 */
- <0 RK_PD3 1 &pcfg_pull_none>, /* LCDC_D23 */
- <0 RK_PD7 1 &pcfg_pull_none>, /* DCLK */
- <0 RK_PD6 1 &pcfg_pull_none>, /* DEN */
- <0 RK_PD4 1 &pcfg_pull_none>, /* HSYNC */
- <0 RK_PD5 1 &pcfg_pull_none>; /* VSYNC */
- };
-
- lcdc_sleep_pins: lcdc-sleep-pins {
- rockchip,pins =
- <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
- <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
- <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
- <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
- <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
- <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
- <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
- <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
- <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
- <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
- <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
- <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
- <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
- <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
- <0 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>, /* DCLK */
- <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
- <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
- <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; /* VSYNC */
- };
- };
- };
-
- rockchip_suspend: rockchip-suspend {
- compatible = "rockchip,pm-rk3368";
- status = "disabled";
- rockchip,sleep-debug-en = <0>;
- rockchip,sleep-mode-config = <
- (0
- | RKPM_SLP_ARMOFF
- | RKPM_SLP_PMU_PLLS_PWRDN
- | RKPM_SLP_PMU_PMUALIVE_32K
- | RKPM_SLP_SFT_PLLS_DEEP
- | RKPM_SLP_PMU_DIS_OSC
- | RKPM_SLP_SFT_PD_NBSCUS
- )
- >;
- rockchip,wakeup-config = <
- (0
- | RKPM_GPIO_WKUP_EN
- | RKPM_USB_WKUP_EN
- )
- >;
};
};
--
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