From 04dd17822334871b23ea2862f7798fb0e0007777 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Sat, 11 May 2024 08:53:19 +0000
Subject: [PATCH] change otg to host mode
---
kernel/arch/arm/mach-davinci/dm365.c | 131 ++++++++++++++++++++++++++-----------------
1 files changed, 79 insertions(+), 52 deletions(-)
diff --git a/kernel/arch/arm/mach-davinci/dm365.c b/kernel/arch/arm/mach-davinci/dm365.c
index 83ca89a..c1e0d46 100644
--- a/kernel/arch/arm/mach-davinci/dm365.c
+++ b/kernel/arch/arm/mach-davinci/dm365.c
@@ -19,6 +19,8 @@
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irqchip/irq-davinci-aintc.h>
#include <linux/platform_data/edma.h>
#include <linux/platform_data/gpio-davinci.h>
#include <linux/platform_data/keyscan-davinci.h>
@@ -31,13 +33,14 @@
#include <mach/common.h>
#include <mach/cputype.h>
-#include <mach/irqs.h>
#include <mach/mux.h>
#include <mach/serial.h>
-#include <mach/time.h>
+
+#include <clocksource/timer-davinci.h>
#include "asp.h"
#include "davinci.h"
+#include "irqs.h"
#include "mux.h"
#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
@@ -224,7 +227,7 @@
.flags = IORESOURCE_MEM,
},
{
- .start = IRQ_DM365_SPIINT0_0,
+ .start = DAVINCI_INTC_IRQ(IRQ_DM365_SPIINT0_0),
.flags = IORESOURCE_IRQ,
},
};
@@ -266,48 +269,50 @@
.flags = IORESOURCE_MEM,
},
{ /* interrupt */
- .start = IRQ_DM365_GPIO0,
- .end = IRQ_DM365_GPIO0,
+ .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
+ .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
.flags = IORESOURCE_IRQ,
},
{
- .start = IRQ_DM365_GPIO1,
- .end = IRQ_DM365_GPIO1,
+ .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
+ .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
.flags = IORESOURCE_IRQ,
},
{
- .start = IRQ_DM365_GPIO2,
- .end = IRQ_DM365_GPIO2,
+ .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
+ .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
.flags = IORESOURCE_IRQ,
},
{
- .start = IRQ_DM365_GPIO3,
- .end = IRQ_DM365_GPIO3,
+ .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
+ .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
.flags = IORESOURCE_IRQ,
},
{
- .start = IRQ_DM365_GPIO4,
- .end = IRQ_DM365_GPIO4,
+ .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
+ .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
.flags = IORESOURCE_IRQ,
},
{
- .start = IRQ_DM365_GPIO5,
- .end = IRQ_DM365_GPIO5,
+ .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
+ .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
.flags = IORESOURCE_IRQ,
},
{
- .start = IRQ_DM365_GPIO6,
- .end = IRQ_DM365_GPIO6,
+ .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
+ .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
.flags = IORESOURCE_IRQ,
},
{
- .start = IRQ_DM365_GPIO7,
- .end = IRQ_DM365_GPIO7,
+ .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
+ .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
.flags = IORESOURCE_IRQ,
},
};
static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
+ .no_auto_base = true,
+ .base = 0,
.ngpio = 104,
.gpio_unbanked = 8,
};
@@ -334,23 +339,23 @@
.flags = IORESOURCE_MEM,
},
{
- .start = IRQ_DM365_EMAC_RXTHRESH,
- .end = IRQ_DM365_EMAC_RXTHRESH,
+ .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
+ .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
.flags = IORESOURCE_IRQ,
},
{
- .start = IRQ_DM365_EMAC_RXPULSE,
- .end = IRQ_DM365_EMAC_RXPULSE,
+ .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
+ .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
.flags = IORESOURCE_IRQ,
},
{
- .start = IRQ_DM365_EMAC_TXPULSE,
- .end = IRQ_DM365_EMAC_TXPULSE,
+ .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
+ .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
.flags = IORESOURCE_IRQ,
},
{
- .start = IRQ_DM365_EMAC_MISCPULSE,
- .end = IRQ_DM365_EMAC_MISCPULSE,
+ .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
+ .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
.flags = IORESOURCE_IRQ,
},
};
@@ -516,12 +521,12 @@
},
{
.name = "edma3_ccint",
- .start = IRQ_CCINT0,
+ .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
.flags = IORESOURCE_IRQ,
},
{
.name = "edma3_ccerrint",
- .start = IRQ_CCERRINT,
+ .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
.flags = IORESOURCE_IRQ,
},
/* not using TC*_ERR */
@@ -595,7 +600,7 @@
.flags = IORESOURCE_MEM,
},
{
- .start = IRQ_DM365_RTCINT,
+ .start = DAVINCI_INTC_IRQ(IRQ_DM365_RTCINT),
.flags = IORESOURCE_IRQ,
},
};
@@ -625,8 +630,8 @@
},
{
/* interrupt */
- .start = IRQ_DM365_KEYINT,
- .end = IRQ_DM365_KEYINT,
+ .start = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
+ .end = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
.flags = IORESOURCE_IRQ,
},
};
@@ -656,10 +661,16 @@
},
};
-static struct davinci_timer_info dm365_timer_info = {
- .timers = davinci_timer_instance,
- .clockevent_id = T0_BOT,
- .clocksource_id = T0_TOP,
+/*
+ * Bottom half of timer0 is used for clockevent, top half is used for
+ * clocksource.
+ */
+static const struct davinci_timer_cfg dm365_timer_cfg = {
+ .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_128),
+ .irq = {
+ DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
+ DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
+ },
};
#define DM365_UART1_BASE (IO_PHYS + 0x106000)
@@ -667,7 +678,7 @@
static struct plat_serial8250_port dm365_serial0_platform_data[] = {
{
.mapbase = DAVINCI_UART0_BASE,
- .irq = IRQ_UARTINT0,
+ .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
@@ -680,7 +691,7 @@
static struct plat_serial8250_port dm365_serial1_platform_data[] = {
{
.mapbase = DM365_UART1_BASE,
- .irq = IRQ_UARTINT1,
+ .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
UPF_IOREMAP,
.iotype = UPIO_MEM,
@@ -719,11 +730,6 @@
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
.pinmux_pins = dm365_pins,
.pinmux_pins_num = ARRAY_SIZE(dm365_pins),
- .intc_base = DAVINCI_ARM_INTC_BASE,
- .intc_type = DAVINCI_INTC_TYPE_AINTC,
- .intc_irq_prios = dm365_default_priorities,
- .intc_irq_num = DAVINCI_N_AINTC_IRQ,
- .timer_info = &dm365_timer_info,
.emac_pdata = &dm365_emac_pdata,
.sram_dma = 0x00010000,
.sram_len = SZ_32K,
@@ -771,6 +777,7 @@
{
void __iomem *pll1, *pll2, *psc;
struct clk *clk;
+ int rv;
clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
@@ -784,8 +791,13 @@
dm365_psc_init(NULL, psc);
clk = clk_get(NULL, "timer0");
+ if (WARN_ON(IS_ERR(clk))) {
+ pr_err("Unable to get the timer clock\n");
+ return;
+ }
- davinci_timer_init(clk);
+ rv = davinci_timer_register(clk, &dm365_timer_cfg);
+ WARN(rv, "Unable to register the timer: %d\n", rv);
}
void __init dm365_register_clocks(void)
@@ -820,13 +832,13 @@
static struct resource vpfe_resources[] = {
{
- .start = IRQ_VDINT0,
- .end = IRQ_VDINT0,
+ .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
+ .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
.flags = IORESOURCE_IRQ,
},
{
- .start = IRQ_VDINT1,
- .end = IRQ_VDINT1,
+ .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
+ .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
.flags = IORESOURCE_IRQ,
},
};
@@ -907,8 +919,8 @@
static struct resource dm365_venc_resources[] = {
{
- .start = IRQ_VENCINT,
- .end = IRQ_VENCINT,
+ .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
+ .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
.flags = IORESOURCE_IRQ,
},
/* venc registers io space */
@@ -927,8 +939,8 @@
static struct resource dm365_v4l2_disp_resources[] = {
{
- .start = IRQ_VENCINT,
- .end = IRQ_VENCINT,
+ .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
+ .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
.flags = IORESOURCE_IRQ,
},
/* venc registers io space */
@@ -1050,6 +1062,21 @@
return 0;
}
+static const struct davinci_aintc_config dm365_aintc_config = {
+ .reg = {
+ .start = DAVINCI_ARM_INTC_BASE,
+ .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .num_irqs = 64,
+ .prios = dm365_default_priorities,
+};
+
+void __init dm365_init_irq(void)
+{
+ davinci_aintc_init(&dm365_aintc_config);
+}
+
static int __init dm365_init_devices(void)
{
struct platform_device *edma_pdev;
--
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