add boot dts

ronnie

2022-10-23 5a83b14855e763445ac36672c35ddb68300e4b42

add boot dts

 longan/kernel/linux-4.9/arch/arm64/boot/dts/sunxi/sun50iw10p1-pinctrl.dtsi
..
..
@@ -151,9 +151,10 @@
151
151
 			};
152
152
 
153
153
 			uart2_pins_a: uart2@0 {
154
-				allwinner,pins = "PB0", "PB1", "PB2", "PB3";
155
-				allwinner,pname = "uart2_tx", "uart2_rx",
156
-						  "uart2_rts", "uart2_cts";
154
+				//allwinner,pins = "PB0", "PB1", "PB2", "PB3";
155
+				allwinner,pins = "PB0", "PB1";
156
+				allwinner,pname = "uart2_tx", "uart2_rx";
157
+				//		  "uart2_rts", "uart2_cts";
157
158
 				allwinner,function = "uart2";
158
159
 				allwinner,muxsel = <2>;
159
160
 				allwinner,drive = <1>;
..
..
@@ -161,7 +162,8 @@
161
162
 			};
162
163
 
163
164
 			uart2_pins_b: uart2@1 {
164
-				allwinner,pins = "PB0", "PB1", "PB2", "PB3";
165
+				//allwinner,pins = "PB0", "PB1", "PB2", "PB3";
166
+				allwinner,pins = "PB0", "PB1";
165
167
 				allwinner,function = "io_disabled";
166
168
 				allwinner,muxsel = <7>;
167
169
 				allwinner,drive = <1>;
..
..
@@ -169,9 +171,9 @@
169
171
 			};
170
172
 
171
173
 			uart3_pins_a: uart3@0 {
172
-				allwinner,pins = "PH4", "PH5", "PH6", "PH7";
173
-				allwinner,pname = "uart3_tx", "uart3_rx",
174
-						  "uart3_rts", "uart3_cts";
174
+				//allwinner,pins = "PH4", "PH5", "PH6", "PH7";
175
+				allwinner,pname = "uart3_tx", "uart3_rx";
176
+						  //"uart3_rts", "uart3_cts";
175
177
 				allwinner,function = "uart3";
176
178
 				allwinner,muxsel = <2>;
177
179
 				allwinner,drive = <1>;
..
..
@@ -179,7 +181,8 @@
179
181
 			};
180
182
 
181
183
 			uart3_pins_b: uart3@1 {
182
-				allwinner,pins = "PH4", "PH5", "PH6", "PH7";
184
+				//allwinner,pins = "PH4", "PH5", "PH6", "PH7";
185
+				//allwinner,pins = "PH4", "PH5";
183
186
 				allwinner,function = "io_disabled";
184
187
 				allwinner,muxsel = <7>;
185
188
 				allwinner,drive = <1>;
..
..
@@ -187,9 +190,9 @@
187
190
 			};
188
191
 
189
192
 			uart4_pins_a: uart4@0 {
190
-				allwinner,pins = "PD18", "PD19", "PD20", "PD21";
191
-				allwinner,pname = "uart4_tx", "uart4_rx",
192
-						  "uart4_rts", "uart4_cts";
193
+				//allwinner,pins = "PD18", "PD19", "PD20", "PD21";
194
+				allwinner,pname = "uart4_tx", "uart4_rx";
195
+						  //"uart4_rts", "uart4_cts";
193
196
 				allwinner,function = "uart4";
194
197
 				allwinner,muxsel = <4>;
195
198
 				allwinner,drive = <1>;
..
..
@@ -197,7 +200,8 @@
197
200
 			};
198
201
 
199
202
 			uart4_pins_b: uart4@1 {
200
-				allwinner,pins = "PD18", "PD19", "PD20", "PD21";
203
+				//allwinner,pins = "PD18", "PD19", "PD20", "PD21";
204
+				allwinner,pins = "PD18", "PD19";
201
205
 				allwinner,function = "io_disabled";
202
206
 				allwinner,muxsel = <7>;
203
207
 				allwinner,drive = <1>;
..
..
@@ -241,7 +245,7 @@
241
245
 			};
242
246
 
243
247
 			ir0_pins_a: ir0@0 {
244
-				allwinner,pins = "PH3";
248
+				//allwinner,pins = "PH3";
245
249
 				allwinner,pname = "it-tx";
246
250
 				allwinner,function = "ir0";
247
251
 				allwinner,muxsel = <3>;
..
..
@@ -250,7 +254,7 @@
250
254
 			};
251
255
 
252
256
 			ir0_pins_b: ir0@1 {
253
-				allwinner,pins = "PH3";
257
+				//allwinner,pins = "PH3";
254
258
 				allwinner,pname = "io_disabled";
255
259
 				allwinner,function = "io_disabled";
256
260
 				allwinner,muxsel = <7>;
..
..
@@ -259,16 +263,19 @@
259
263
 			};
260
264
 
261
265
 			twi0_pins_a: twi0@0 {
262
-				allwinner,pins = "PB9", "PB10";
266
+				allwinner,pins = "PH0", "PH1";
267
+				//allwinner,pins = "PD22", "PD23";
263
268
 				allwinner,pname = "twi0_scl", "twi0_sda";
264
269
 				allwinner,function = "twi0";
265
-				allwinner,muxsel = <3>;
270
+				//allwinner,muxsel = <3>;
271
+				allwinner,muxsel = <2>;
266
272
 				allwinner,drive = <1>;
267
273
 				allwinner,pull = <0>;
268
274
 			};
269
275
 
270
276
 			twi0_pins_b: twi0@1 {
271
-				allwinner,pins = "PB9", "PB10";
277
+				allwinner,pins = "PH0", "PH1";
278
+				//allwinner,pins = "PD22", "PD23";
272
279
 				allwinner,function = "io_disabled";
273
280
 				allwinner,muxsel = <7>;
274
281
 				allwinner,drive = <1>;
..
..
@@ -391,11 +398,14 @@
391
398
 				allwinner,drive = <1>;
392
399
 				allwinner,pull = <0>;
393
400
 			};
394
-
401
+/*
395
402
 			spi0_pins_a: spi0@0 {
396
-				allwinner,pins = "PC2", "PC4", "PC12", "PC15", "PC16";
403
+				//allwinner,pins = "PC2", "PC4", "PC12", "PC15", "PC16";
404
+				//allwinner,pname = "spi0_mosi", "spi0_miso",
405
+				//		  "spi0_sclk", "spi0_wp", "spi0_hold";
406
+				allwinner,pins = "PC2", "PC4", "PC12";
397
407
 				allwinner,pname = "spi0_mosi", "spi0_miso",
398
-						  "spi0_sclk", "spi0_wp", "spi0_hold";
408
+						  "spi0_sclk";
399
409
 				allwinner,function = "spi0";
400
410
 				allwinner,muxsel = <4>;
401
411
 				allwinner,drive = <1>;
..
..
@@ -403,22 +413,23 @@
403
413
 			};
404
414
 
405
415
 			spi0_pins_b: spi0@1 {
406
-				allwinner,pins = "PC3", "PC7";
407
-				allwinner,pname = "spi0_cs0", "spi0_cs1";
416
+				allwinner,pins = "PC3";
417
+				allwinner,pname = "spi0_cs0";
408
418
 				allwinner,function = "spi0";
409
419
 				allwinner,muxsel = <4>;
410
420
 				allwinner,drive = <1>;
411
-				allwinner,pull = <1>;	/* only CS should be pulled up */
421
+				allwinner,pull = <1>;
412
422
 			};
413
423
 
414
424
 			spi0_pins_c: spi0@2 {
415
-				allwinner,pins = "PC2", "PC3", "PC4", "PC7", "PC12", "PC15", "PC16";
425
+				//allwinner,pins = "PC2", "PC3", "PC4", "PC7", "PC12", "PC15", "PC16";
426
+				allwinner,pins = "PC2", "PC3", "PC4", "PC12";
416
427
 				allwinner,function = "io_disabled";
417
428
 				allwinner,muxsel = <7>;
418
429
 				allwinner,drive = <1>;
419
430
 				allwinner,pull = <0>;
420
431
 			};
421
-
432
+*/
422
433
 			spi1_pins_a: spi1@0 {
423
434
 				allwinner,pins = "PD11", "PD12", "PD13";
424
435
 				allwinner,pname = "spi1_sclk", "spi1_mosi",
..
..
@@ -447,11 +458,11 @@
447
458
 			};
448
459
 
449
460
 			spi2_pins_a: spi2@0 {
450
-				allwinner,pins = "PB1", "PB2", "PB3";
461
+				//allwinner,pins = "PB1", "PB2", "PB3";
451
462
 				allwinner,pname = "spi2_sclk", "spi2_mosi",
452
463
 						  "spi2_miso";
453
464
 				allwinner,function = "spi2";
454
-				allwinner,muxsel = <3>;
465
+				//allwinner,muxsel = <3>;
455
466
 				allwinner,drive = <1>;
456
467
 				allwinner,pull = <0>;
457
468
 			};
..
..
@@ -466,7 +477,7 @@
466
477
 			};
467
478
 
468
479
 			spi2_pins_c: spi2@2 {
469
-				allwinner,pins = "PB0", "PB1", "PB2", "PB3";
480
+				//allwinner,pins = "PB0", "PB1", "PB2", "PB3";
470
481
 				allwinner,function = "io_disabled";
471
482
 				allwinner,muxsel = <7>;
472
483
 				allwinner,drive = <1>;
..
..
@@ -613,7 +624,7 @@
613
624
 			};
614
625
 
615
626
 			daudio3_pins_a: daudio3@0 {
616
-				allwinner,pins = "PH13", "PH14", "PH15", "PH16", "PH17", "PH18", "PH19";
627
+				//allwinner,pins = "PH13", "PH14", "PH15", "PH16", "PH17", "PH18", "PH19";
617
628
 				allwinner,function = "h_i2s3";
618
629
 				allwinner,muxsel = <4>;
619
630
 				allwinner,drive = <1>;
..
..
@@ -621,7 +632,7 @@
621
632
 			};
622
633
 
623
634
 			daudio3_pins_b: daudio3_sleep@0 {
624
-				allwinner,pins = "PH13", "PH14", "PH15", "PH16", "PH17", "PH18", "PH19";
635
+				//allwinner,pins = "PH13", "PH14", "PH15", "PH16", "PH17", "PH18", "PH19";
625
636
 				allwinner,function = "io_disabled";
626
637
 				allwinner,muxsel = <7>;
627
638
 				allwinner,drive = <1>;
..
..
@@ -629,7 +640,7 @@
629
640
 			};
630
641
 
631
642
 			spdif_pins_a: spdif@0 {
632
-				allwinner,pins = "PH6", "PH7";
643
+				//allwinner,pins = "PH6", "PH7";
633
644
 				allwinner,function = "spdif";
634
645
 				allwinner,muxsel = <4>;
635
646
 				allwinner,drive = <1>;
..
..
@@ -637,7 +648,7 @@
637
648
 			};
638
649
 
639
650
 			spdif_pins_b: spdif_sleep@0 {
640
-				allwinner,pins = "PH6", "PH7";
651
+				//allwinner,pins = "PH6", "PH7";
641
652
 				allwinner,function = "io_disabled";
642
653
 				allwinner,muxsel = <7>;
643
654
 				allwinner,drive = <1>;
..
..
@@ -645,7 +656,8 @@
645
656
 			};
646
657
 
647
658
 			dmic_pins_a: dmic@0 {
648
-				allwinner,pins = "PH8", "PH9", "PH10", "PH11", "PH12";
659
+				//allwinner,pins = "PH8", "PH9", "PH10", "PH11", "PH12";
660
+				allwinner,pins = "PH8", "PH11", "PH12";
649
661
 				allwinner,function = "dmic";
650
662
 				allwinner,muxsel = <2>;
651
663
 				allwinner,drive = <1>;
..
..
@@ -653,7 +665,8 @@
653
665
 			};
654
666
 
655
667
 			dmic_pins_b: dmic_sleep@0 {
656
-				allwinner,pins = "PH8", "PH9", "PH10", "PH11", "PH12";
668
+				//allwinner,pins = "PH8", "PH9", "PH10", "PH11", "PH12";
669
+				allwinner,pins = "PH8", "PH11", "PH12";
657
670
 				allwinner,function = "io_disabled";
658
671
 				allwinner,muxsel = <7>;
659
672
 				allwinner,drive = <1>;
..
..
@@ -720,8 +733,8 @@
720
733
 			};
721
734
 
722
735
 			scr1_pins_a: scr1@0 {
723
-				allwinner,pins = "PH5", "PH6", "PH2",
724
-						 "PH3", "PH4";
736
+				//allwinner,pins = "PH5", "PH6", "PH2",
737
+				//		 "PH3", "PH4";
725
738
 				allwinner,pname = "scr1_rst", "scr1_det",
726
739
 						  "scr1_vccen", "scr1_sck",
727
740
 						  "scr1_sda";
..
..
@@ -732,7 +745,7 @@
732
745
 			};
733
746
 
734
747
 			scr1_pins_b: scr1@1 {
735
-				allwinner,pins = "PH0", "PH1";
748
+				//allwinner,pins = "PH0", "PH1";
736
749
 				allwinner,pname = "scr1_vppen", "scr1_vppp";
737
750
 				allwinner,function = "sim1";
738
751
 				allwinner,muxsel = <5>;
..
..
@@ -741,9 +754,9 @@
741
754
 			};
742
755
 
743
756
 			scr1_pins_c: scr1@2 {
744
-				allwinner,pins = "PH0", "PH1", "PH2",
745
-						 "PH3", "PH4", "PH5",
746
-						 "PH6";
757
+				//allwinner,pins = "PH0", "PH1", "PH2",
758
+				//		 "PH3", "PH4", "PH5",
759
+				//		 "PH6";
747
760
 				allwinner,function = "io_disabled";
748
761
 				allwinner,muxsel = <7>;
749
762
 				allwinner,drive = <1>;
..
..
@@ -801,23 +814,29 @@
801
814
 				allwinner,drive = <1>;
802
815
 				allwinner,pull = <0>;
803
816
 			};
804
-
805
817
 			gmac_pins_a: gmac@0 {
818
+				//allwinner,pins = "PH0", "PH1", "PH2", "PH3",
819
+				//		 "PH4", "PH5", "PH6", "PH7",
820
+				//		 "PH9", "PH10", "PH13", "PH14",
821
+				//		 "PH15", "PH16", "PH17", "PH18";
806
822
 				allwinner,pins = "PH0", "PH1", "PH2", "PH3",
807
823
 						 "PH4", "PH5", "PH6", "PH7",
808
-						 "PH9", "PH10", "PH13", "PH14",
809
-						 "PH15", "PH16", "PH17", "PH18";
824
+						 "PH9", "PH10";
810
825
 				allwinner,function = "gmac0";
811
826
 				allwinner,muxsel = <5>;
812
827
 				allwinner,drive = <3>;
813
-				allwinner,pull = <0>;
828
+				allwinner,pull = <0xffffffff>;
829
+				allwinner,data = <0xffffffff>;
814
830
 			};
815
831
 
816
832
 			gmac_pins_b: gmac@1 {
833
+				//allwinner,pins = "PH0", "PH1", "PH2", "PH3",
834
+				//		 "PH4", "PH5", "PH6", "PH7",
835
+				//		 "PH9", "PH10", "PH13", "PH14",
836
+				//		 "PH15", "PH16", "PH17", "PH18";
817
837
 				allwinner,pins = "PH0", "PH1", "PH2", "PH3",
818
838
 						 "PH4", "PH5", "PH6", "PH7",
819
-						 "PH9", "PH10", "PH13", "PH14",
820
-						 "PH15", "PH16", "PH17", "PH18";
839
+						 "PH9", "PH10";
821
840
 				allwinner,function = "io_disabled";
822
841
 				allwinner,muxsel = <7>;
823
842
 				allwinner,drive = <3>;
..
..
@@ -861,6 +880,7 @@
861
880
 				allwinner,drive = <1>;
862
881
 				allwinner,pull = <0>;
863
882
 			};
883
+
864
884
 			lvds0_pins_a: lvds0@0 {
865
885
 				allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD8", "PD9", "PD6", "PD7";
866
886
 				allwinner,pname = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD8", "PD9", "PD6", "PD7";
..
..
@@ -962,6 +982,7 @@
962
982
 				allwinner,drive = <3>;
963
983
 				allwinner,pull = <0>;
964
984
 			};
985
+
965
986
 			lvds2link_pins_b: lvds2link@1 {
966
987
 				allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD8", "PD9", "PD6", "PD7", \
967
988
 				"PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD18", "PD19", "PD16", "PD17";
..
..
@@ -1022,6 +1043,31 @@
1022
1043
 				allwinner,pull = <0>;
1023
1044
 			};
1024
1045
 
1046
+			rgb16_pins_a: rgb16@0 {
1047
+				allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", \
1048
+				"PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \
1049
+				"PD20", "PD21";
1050
+				allwinner,pname = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", \
1051
+				"PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \
1052
+				"PD20", "PD21";
1053
+				allwinner,function = "rgb16";
1054
+				allwinner,muxsel = <2>;
1055
+				allwinner,drive = <3>;
1056
+				allwinner,pull = <0>;
1057
+			};
1058
+			rgb16_pins_b: rgb16@1 {
1059
+				allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", \
1060
+				"PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \
1061
+				"PD20", "PD21";
1062
+				allwinner,pname = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", \
1063
+				"PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \
1064
+				"PD20", "PD21";
1065
+				allwinner,function = "rgb16_suspend";
1066
+				allwinner,muxsel = <7>;
1067
+				allwinner,drive = <1>;
1068
+				allwinner,pull = <0>;
1069
+			};
1070
+
1025
1071
 			eink_pins_a: eink@0 {
1026
1072
 				allwinner,pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", "PD8", "PD9", \
1027
1073
 				"PD10", "PD11", "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", "PD18", "PD19", \
 longan/kernel/linux-4.9/arch/arm64/boot/dts/sunxi/sun50iw10p1.dtsi
..
..
@@ -12,6 +12,11 @@
12
12
 #include "sun50iw10p1-clk.dtsi"
13
13
 #include "sun50iw10p1-pinctrl.dtsi"
14
14
 #include <dt-bindings/thermal/thermal.h>
15
+
16
+#define V1A 0
17
+#define V1B 1
18
+
19
+
15
20
 / {
16
21
 	model = "sun50iw10";
17
22
 	compatible = "arm,sun50iw10p1";
..
..
@@ -178,28 +183,39 @@
178
183
 
179
184
 	cpu_opp_l_table: opp_l_table {
180
185
 		compatible = "allwinner,sun50i-operating-points";
181
-		nvmem-cells = <&speedbin_efuse>, <&cpubin_efuse>;
182
-		nvmem-cell-names = "speed", "bin";
186
+		nvmem-cells = <&speedbin_efuse>, <&cpubin_efuse>, <&cpubin_extend>;
187
+		nvmem-cell-names = "speed", "bin", "bin_ext";
183
188
 		opp-shared;
184
189
 
185
-		opp@408000000 {
190
+		opp@408000000-0 {
186
191
 			opp-hz = /bits/ 64 <408000000>;
187
192
 			clock-latency-ns = <244144>; /* 8 32k periods */
188
193
 			opp-microvolt-a0 = <900000>;
189
194
 			opp-microvolt-a1 = <900000>;
190
195
 			opp-microvolt-a2 = <900000>;
196
+			opp-microvolt-a3 = <940000>;
197
+			opp-microvolt-a4 = <940000>;
198
+			opp-microvolt-a5 = <920000>;
199
+			opp-microvolt-a6 = <920000>;
191
200
 			opp-microvolt-b0 = <900000>;
192
201
 			opp-microvolt-b1 = <900000>;
202
+			opp-microvolt-b2 = <940000>;
203
+			opp-microvolt-b3 = <920000>;
193
204
 		};
194
-
195
205
 		opp@600000000 {
196
206
 			opp-hz = /bits/ 64 <600000000>;
197
207
 			clock-latency-ns = <244144>; /* 8 32k periods */
198
208
 			opp-microvolt-a0 = <900000>;
199
209
 			opp-microvolt-a1 = <900000>;
200
210
 			opp-microvolt-a2 = <900000>;
211
+			opp-microvolt-a3 = <940000>;
212
+			opp-microvolt-a4 = <940000>;
213
+			opp-microvolt-a5 = <920000>;
214
+			opp-microvolt-a6 = <920000>;
201
215
 			opp-microvolt-b0 = <900000>;
202
216
 			opp-microvolt-b1 = <900000>;
217
+			opp-microvolt-b2 = <940000>;
218
+			opp-microvolt-b3 = <920000>;
203
219
 		};
204
220
 
205
221
 		opp@816000000 {
..
..
@@ -208,8 +224,14 @@
208
224
 			opp-microvolt-a0 = <940000>;
209
225
 			opp-microvolt-a1 = <900000>;
210
226
 			opp-microvolt-a2 = <900000>;
227
+			opp-microvolt-a3 = <940000>;
228
+			opp-microvolt-a4 = <940000>;
229
+			opp-microvolt-a5 = <920000>;
230
+			opp-microvolt-a6 = <920000>;
211
231
 			opp-microvolt-b0 = <900000>;
212
232
 			opp-microvolt-b1 = <900000>;
233
+			opp-microvolt-b2 = <940000>;
234
+			opp-microvolt-b3 = <920000>;
213
235
 		};
214
236
 
215
237
 		opp@1008000000 {
..
..
@@ -218,8 +240,14 @@
218
240
 			opp-microvolt-a0 = <1020000>;
219
241
 			opp-microvolt-a1 = <980000>;
220
242
 			opp-microvolt-a2 = <950000>;
243
+			opp-microvolt-a3 = <1020000>;
244
+			opp-microvolt-a4 = <960000>;
245
+			opp-microvolt-a5 = <940000>;
246
+			opp-microvolt-a6 = <940000>;
221
247
 			opp-microvolt-b0 = <980000>;
222
248
 			opp-microvolt-b1 = <950000>;
249
+			opp-microvolt-b2 = <960000>;
250
+			opp-microvolt-b3 = <940000>;
223
251
 		};
224
252
 
225
253
 		opp@1200000000 {
..
..
@@ -228,8 +256,14 @@
228
256
 			opp-microvolt-a0 = <1100000>;
229
257
 			opp-microvolt-a1 = <1020000>;
230
258
 			opp-microvolt-a2 = <1000000>;
259
+			opp-microvolt-a3 = <1100000>;
260
+			opp-microvolt-a4 = <980000>;
261
+			opp-microvolt-a5 = <960000>;
262
+			opp-microvolt-a6 = <960000>;
231
263
 			opp-microvolt-b0 = <1020000>;
232
264
 			opp-microvolt-b1 = <1000000>;
265
+			opp-microvolt-b2 = <980000>;
266
+			opp-microvolt-b3 = <960000>;
233
267
 		};
234
268
 
235
269
 		opp@1320000000 {
..
..
@@ -238,23 +272,38 @@
238
272
 			opp-microvolt-a0 = <1160000>;
239
273
 			opp-microvolt-a1 = <1060000>;
240
274
 			opp-microvolt-a2 = <1030000>;
275
+			opp-microvolt-a3 = <1160000>;
276
+			opp-microvolt-a4 = <1020000>;
277
+			opp-microvolt-a5 = <1000000>;
278
+			opp-microvolt-a6 = <1000000>;
241
279
 			opp-microvolt-b0 = <1060000>;
242
280
 			opp-microvolt-b1 = <1030000>;
281
+			opp-microvolt-b2 = <1020000>;
282
+			opp-microvolt-b3 = <1000000>;
243
283
 		};
244
284
 
245
285
 		opp@1416000000 {
246
286
 			opp-hz = /bits/ 64 <1416000000>;
247
287
 			clock-latency-ns = <244144>; /* 8 32k periods */
288
+			opp-microvolt-a0 = <1180000>;
289
+			opp-microvolt-a1 = <1180000>;
290
+			opp-microvolt-a2 = <1130000>;
248
291
 			opp-microvolt-b0 = <1100000>;
249
292
 			opp-microvolt-b1 = <1070000>;
293
+			opp-microvolt-b2 = <1060000>;
294
+			opp-microvolt-b3 = <1040000>;
250
295
 		};
251
296
 
252
297
 		opp@1464000000 {
253
298
 			opp-hz = /bits/ 64 <1464000000>;
254
-			clock-latency-ns = <244144>; /* 8 32k periods */
299
+			clock-latency-ns = <244144>; 
255
300
 			opp-microvolt-a0 = <1180000>;
256
301
 			opp-microvolt-a1 = <1180000>;
257
302
 			opp-microvolt-a2 = <1130000>;
303
+			opp-microvolt-a3 = <1180000>;
304
+			opp-microvolt-a4 = <1100000>;
305
+			opp-microvolt-a5 = <1080000>;
306
+			opp-microvolt-a6 = <1080000>;
258
307
 		};
259
308
 
260
309
 		opp@1512000000 {
..
..
@@ -262,14 +311,15 @@
262
311
 			clock-latency-ns = <244144>; /* 8 32k periods */
263
312
 			opp-microvolt-b0 = <1180000>;
264
313
 			opp-microvolt-b1 = <1130000 1130000 1140000>;
314
+			opp-microvolt-b2 = <1100000>;
315
+			opp-microvolt-b3 = <1080000>;
265
316
 		};
266
-
267
317
 		opp@1608000000 {
268
-			opp-hz = /bits/ 64 <1608000000>;
269
-			clock-latency-ns = <244144>; /* 8 32k periods */
318
+ 			opp-hz = /bits/ 64 <1608000000>;
319
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
270
320
 			opp-microvolt-b0 = <1180000>;
271
321
 			opp-microvolt-b1 = <1130000 1130000 1140000>;
272
-		};
322
+ 		};
273
323
 	};
274
324
 
275
325
 	psci {
..
..
@@ -438,6 +488,9 @@
438
488
 		cpubin_efuse: calib@1c {
439
489
 			reg = <0x1c 2>;
440
490
 		};
491
+	 	cpubin_extend: calib@28 {
492
+			reg = <0x28 4>;
493
+ 		};
441
494
 	};
442
495
 
443
496
 	chipid: sunxi-chipid@03006200 {
..
..
@@ -603,7 +656,7 @@
603
656
 			pinctrl-names = "default";
604
657
 			pinctrl-0 = <&s_cir0_pins_a>;
605
658
 			clocks = <&clk_hosc>,<&clk_cpurcir>;
606
-			status = "okay";
659
+			status = "disabled";
607
660
 		};
608
661
 
609
662
 		ir1: ir@0x05071000 {
..
..
@@ -701,7 +754,7 @@
701
754
 			pinctrl-1 = <&uart2_pins_b>;
702
755
 			uart2_port = <2>;
703
756
 			uart2_type = <4>;
704
-			status = "disabled";
757
+			status = "okay";
705
758
 		};
706
759
 
707
760
 		uart3: uart@05000c00 {
..
..
@@ -813,7 +866,7 @@
813
866
 			pinctrl-names = "default", "sleep";
814
867
 			pinctrl-0 = <&twi0_pins_a>;
815
868
 			pinctrl-1 = <&twi0_pins_b>;
816
-			status = "disabled";
869
+			status = "okay";
817
870
 		};
818
871
 
819
872
 		twi1: twi@0x05002400{
..
..
@@ -843,7 +896,7 @@
843
896
 			pinctrl-names = "default", "sleep";
844
897
 			pinctrl-0 = <&twi2_pins_a>;
845
898
 			pinctrl-1 = <&twi2_pins_b>;
846
-			status = "disabled";
899
+			status = "ok";
847
900
 		};
848
901
 
849
902
 		twi3: twi@0x05002c00{
..
..
@@ -858,7 +911,7 @@
858
911
 			pinctrl-names = "default", "sleep";
859
912
 			pinctrl-0 = <&twi3_pins_a>;
860
913
 			pinctrl-1 = <&twi3_pins_b>;
861
-			status = "disabled";
914
+			status = "ok";
862
915
 		};
863
916
 
864
917
 		twi4: twi@0x05003000{
..
..
@@ -1001,9 +1054,9 @@
1001
1054
 			compatible = "allwinner,sunxi-codec-machine";
1002
1055
 			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1003
1056
 			sunxi,audio-codec = <&codec>;
1004
-			hp_detect_case = <0x00>;
1057
+			hp_detect_case = <0x01>;
1005
1058
 			device_type = "sndcodec";
1006
-			status = "disabled";
1059
+			status = "okay";
1007
1060
 		};
1008
1061
 
1009
1062
 		spdif:spdif-controller@0x05094000{
..
..
@@ -1032,14 +1085,14 @@
1032
1085
 			pinctrl-0 = <&dmic_pins_a>;
1033
1086
 			pinctrl-1 = <&dmic_pins_b>;
1034
1087
 			device_type = "dmic";
1035
-			status = "disabled";
1088
+			status = "okay";
1036
1089
 		};
1037
1090
 
1038
1091
 		snddmic:sound@2{
1039
1092
 			compatible = "allwinner,sunxi-dmic-machine";
1040
1093
 			sunxi,dmic-controller = <&dmic>;
1041
1094
 			device_type = "snddmic";
1042
-			status = "disabled";
1095
+			status = "okay";
1043
1096
 		};
1044
1097
 
1045
1098
 
..
..
@@ -1118,7 +1171,7 @@
1118
1171
 			device_type = "snddaudio3";
1119
1172
 			status = "disabled";
1120
1173
 		};
1121
-
1174
+/*
1122
1175
 		spi0: spi@05010000 {
1123
1176
 			#address-cells = <1>;
1124
1177
 			#size-cells = <0>;
..
..
@@ -1135,7 +1188,7 @@
1135
1188
 			spi0_cs_bitmap = <1>;
1136
1189
 			status = "disabled";
1137
1190
 		};
1138
-
1191
+*/
1139
1192
 		spi1: spi@05011000 {
1140
1193
 			#address-cells = <1>;
1141
1194
 			#size-cells = <0>;
..
..
@@ -1457,7 +1510,7 @@
1457
1510
 				 <&clk_lvds>,
1458
1511
 				 <&clk_lvds1>,
1459
1512
 				 <&clk_mipi_host>;
1460
-			boot_disp = <0>;
1513
+			boot_disp = <1>;
1461
1514
 			boot_disp1 = <0>;
1462
1515
 			boot_disp2 = <0>;
1463
1516
 			fb_base = <0>;
..
..
@@ -1768,9 +1821,9 @@
1768
1821
 			sensor0:sensor@0 {
1769
1822
 				device_type = "sensor0";
1770
1823
 				compatible = "allwinner,sunxi-sensor";
1771
-				sensor0_mname = "ov5640";
1824
+				sensor0_mname = "ov8858_r2a_4lane";
1772
1825
 				sensor0_twi_cci_id = <2>;
1773
-				sensor0_twi_addr = <0x78>;
1826
+				sensor0_twi_addr = <0x6C>;
1774
1827
 				sensor0_mclk_id = <0>;
1775
1828
 				sensor0_pos = "rear";
1776
1829
 				sensor0_isp_used = <0>;
..
..
@@ -1779,14 +1832,14 @@
1779
1832
 				sensor0_vflip = <0>;
1780
1833
 				sensor0_hflip = <0>;
1781
1834
 				sensor0_iovdd-supply = <>;
1782
-				sensor0_iovdd_vol = <2800000>;
1835
+				sensor0_iovdd_vol = <1800000>;
1783
1836
 				sensor0_avdd-supply = <>;
1784
1837
 				sensor0_avdd_vol = <2800000>;
1785
1838
 				sensor0_dvdd-supply = <>;
1786
-				sensor0_dvdd_vol = <1500000>;
1839
+				sensor0_dvdd_vol = <1200000>;
1787
1840
 				sensor0_power_en = <>;
1788
-				sensor0_reset = <&pio PE 14 1 0 1 0>;
1789
-				sensor0_pwdn = <&pio PE 16 1 0 1 0>;
1841
+				sensor0_reset = <&pio PE 6 1 0 1 0>;
1842
+				sensor0_pwdn = <&pio PE 7 1 0 1 0>;
1790
1843
 				sensor0_sm_vs = <>;
1791
1844
 				flash_handle = <&flash0>;
1792
1845
 				act_handle = <&actuator0>;
..
..
@@ -1796,7 +1849,7 @@
1796
1849
 			sensor1:sensor@1 {
1797
1850
 				device_type = "sensor1";
1798
1851
 				compatible = "allwinner,sunxi-sensor";
1799
-				sensor1_mname = "ov5647";
1852
+				sensor1_mname = "ov5648_mipi";
1800
1853
 				sensor1_twi_cci_id = <3>;
1801
1854
 				sensor1_twi_addr = <0x6c>;
1802
1855
 				sensor1_mclk_id = <1>;
..
..
@@ -1813,8 +1866,8 @@
1813
1866
 				sensor1_dvdd-supply = <>;
1814
1867
 				sensor1_dvdd_vol = <1500000>;
1815
1868
 				sensor1_power_en = <>;
1816
-				sensor1_reset = <&pio PE 14 1 0 1 0>;
1817
-				sensor1_pwdn = <&pio PE 15 1 0 1 0>;
1869
+				sensor1_reset = <&pio PE 8 1 0 1 0>;
1870
+				sensor1_pwdn = <&pio PE 9 1 0 1 0>;
1818
1871
 				sensor1_sm_vs = <>;
1819
1872
 				flash_handle = <>;
1820
1873
 				act_handle = <>;
..
..
@@ -2032,7 +2085,17 @@
2032
2085
 			key3 = <750 28>;
2033
2086
 			key4 = <880 102>;
2034
2087
 		};
2035
-
2088
+/*
2089
+                gpio-keys {
2090
+                        compatible = "gpio-keys";
2091
+                        status = "okay";
2092
+                        power {
2093
+                                gpios = <&pio PB 2 0 0xffffffff 0xffffffff 0>;
2094
+                                label = "KEY1";
2095
+                                linux,code = <100>;
2096
+                        };
2097
+                };
2098
+*/
2036
2099
 		gmac0: eth@05020000 {
2037
2100
 			compatible = "allwinner,sunxi-gmac";
2038
2101
 			reg = <0x0 0x05020000 0x0 0x10000>,
..
..
@@ -2045,14 +2108,25 @@
2045
2108
 			pinctrl-0 = <&gmac_pins_a>;
2046
2109
 			pinctrl-1 = <&gmac_pins_b>;
2047
2110
 			pinctrl-names = "default", "sleep";
2048
-			phy-mode;
2111
+			//phy-mode;
2112
+			phy-mode = "rmii";
2049
2113
 			tx-delay = <7>;
2050
-			rx-delay = <31>;
2051
-			phy-rst;
2052
-			gmac-power0;
2053
-			gmac-power1;
2054
-			gmac-power2;
2055
-			status = "disable";
2114
+			rx-delay = <10>;
2115
+			//phy-rst;
2116
+		#if V1A
2117
+			phy-rst = <&pio PH 12 1 0 1 0>;
2118
+		#elif V1B
2119
+			phy-rst = <&pio PB 7 1 0 1 0>;
2120
+		#endif
2121
+			gmac-power0 = <&reg_aldo3>;
2122
+			gmac-power1 = <&reg_fldo1>;
2123
+			gmac-power2 = <&reg_eldo2>;
2124
+			
2125
+			gmac-power0-vol = <3300000>;
2126
+			gmac-power1-vol = <1200000>;
2127
+			gmac-power2-vol = <1800000>;
2128
+
2129
+			status = "okay";
2056
2130
 		};
2057
2131
 
2058
2132
 		gmac1: eth@05030000 {
..
..
@@ -2074,7 +2148,7 @@
2074
2148
 			gmac-power0;
2075
2149
 			gmac-power1;
2076
2150
 			gmac-power2;
2077
-			status = "disable";
2151
+			status = "disabled";
2078
2152
 		};
2079
2153
 	};
2080
2154