forked from ~ljy/RK356X_SDK_RELEASE

parent: 796a7ef0 | patch | commit
hc
2023-02-14 b625cdcd68479b3d540a915785b6d9809b52a2f8 
stmmac read mac form eeprom
2 files added
21 files modified
851 ■■■■■ changed files
README.MD patch | view | raw | blame | history
kernel/drivers/misc/eeprom/at24.c 148 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/Kconfig 29 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/Makefile 22 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/common.h 2 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c 1 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c 20 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk-tool.c 25 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk-tool.h 13 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c 380 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h 8 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c 4 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c 26 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c 4 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/hwif.c 30 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/stmmac.h 17 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c 17 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c 74 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c 8 ●●●●● patch | view | raw | blame | history
kernel/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c 7 ●●●●● patch | view | raw | blame | history
kernel/include/linux/device.h 11 ●●●●● patch | view | raw | blame | history
kernel/include/linux/platform_device.h 4 ●●●●● patch | view | raw | blame | history
rockdev/parameter.txt 1 ●●●●● patch | view | raw | blame | history 
 README.MD


 kernel/drivers/misc/eeprom/at24.c
....@@ -6,6 +6,7 @@
66  * Copyright (C) 2008 Wolfram Sang, Pengutronix
77  */
88 
9
+#define DEBUG
910 #include <linux/kernel.h>
1011 #include <linux/init.h>
1112 #include <linux/module.h>
....@@ -106,6 +107,8 @@
106107 module_param_named(write_timeout, at24_write_timeout, uint, 0);
107108 MODULE_PARM_DESC(at24_write_timeout, "Time (in ms) to try writes (default 25)");
108109 
110
+//Ben
111
+struct at24_data *at24_private=NULL;
109112 struct at24_chip_data {
110113 	/*
111114 	 * these fields mirror their equivalents in
....@@ -421,6 +424,146 @@
421424 	return 0;
422425 }
423426 
427
+//add ben
428
+static ssize_t at24_read_private(struct at24_data *at24,
429
+		char *buf, loff_t off, size_t count)
430
+{
431
+	ssize_t retval = 0;
432
+
433
+	if (unlikely(!count))
434
+		return count;
435
+
436
+	if (off + count > at24->byte_len)
437
+		return -EINVAL;
438
+	
439
+	/*
440
+	 * Read data from chip, protecting against concurrent updates
441
+	 * from this host, but not from other I2C masters.
442
+	 */
443
+	mutex_lock(&at24->lock);
444
+
445
+	while (count) {
446
+		ssize_t	status;
447
+
448
+		//status = at24_eeprom_read_i2c(at24, buf, off, count);
449
+		status = at24_regmap_read(at24, buf, off, count);
450
+		if (status <= 0) {
451
+			if (retval == 0)
452
+				retval = status;
453
+			break;
454
+		}
455
+		buf += status;
456
+		off += status;
457
+		count -= status;
458
+		retval += status;
459
+	}
460
+
461
+	mutex_unlock(&at24->lock);
462
+
463
+	return retval;
464
+}
465
+
466
+#if 0
467
+static unsigned char AscToHex(unsigned char aChar)
468
+{
469
+    if((aChar>=0x30)&&(aChar<=0x39))
470
+        aChar -= 0x30;
471
+    else if((aChar>=0x41)&&(aChar<=0x46))
472
+        aChar -= 0x37;
473
+    else if((aChar>=0x61)&&(aChar<=0x66))
474
+        aChar -= 0x57;
475
+    else aChar = 0xff;
476
+
477
+    return aChar; 
478
+}
479
+#endif
480
+
481
+#if 0
482
+ssize_t at24_mac_read(unsigned char* addr)
483
+{
484
+	char buf[20];
485
+	char buf_tmp[12];
486
+	int i;
487
+	ssize_t ret;	
488
+	if (at24_private == NULL)
489
+	{
490
+		printk("ben %s: at24_private==null error\n", __func__);
491
+		return 0;
492
+	}
493
+	memset(buf, 0x00, 20);
494
+	memset(buf_tmp, 0x00, 12);
495
+	ret = at24_read(at24_private, 0, buf, 12);
496
+	if (ret > 0)
497
+	{	
498
+		for(i=0; i<12; i++)
499
+		{
500
+			buf_tmp[i] = AscToHex(buf[i]);
501
+		}
502
+		addr[0] = (buf_tmp[0] << 4) | buf_tmp[1];
503
+		addr[1] = (buf_tmp[2] << 4) | buf_tmp[3];
504
+		addr[2] = (buf_tmp[4] << 4) | buf_tmp[5];
505
+		addr[3] = (buf_tmp[6] << 4) | buf_tmp[7];
506
+		addr[4] = (buf_tmp[8] << 4) | buf_tmp[9];
507
+		addr[5] = (buf_tmp[10] << 4) | buf_tmp[11]; 	
508
+	}
509
+	return ret;
510
+}
511
+#endif
512
+
513
+ssize_t at24_mac_read(unsigned char* addr)
514
+{
515
+	char buf[20];
516
+	char buf_tmp[12];
517
+	ssize_t ret;	
518
+	if (at24_private == NULL)
519
+	{
520
+		printk("ben: at24_mac_read at24_private==null error");
521
+		return 0;
522
+	}
523
+	memset(buf, 0x00, 20);
524
+	memset(buf_tmp, 0x00, 12);
525
+	ret = at24_read_private(at24_private, buf, 0, 6);
526
+	if (ret > 0)
527
+	{	
528
+		addr[0] = buf[0];
529
+		addr[1] = buf[1];
530
+		addr[2] = buf[2];
531
+		addr[3] = buf[3];
532
+		addr[4] = buf[4];
533
+		addr[5] = buf[5];	
534
+	}
535
+	printk("at24_mac_read ...............\n");
536
+	return ret;
537
+}
538
+EXPORT_SYMBOL(at24_mac_read);
539
+
540
+ssize_t at24_mac1_read(unsigned char* mac)
541
+{
542
+	char buf[20];
543
+	char buf_tmp[12];
544
+	ssize_t ret;
545
+	if (at24_private == NULL)
546
+	{
547
+		printk("zcl: at24_mac_read at24_private==null error");
548
+		return 0;
549
+	}
550
+	memset(buf, 0x00, 20);
551
+	memset(buf_tmp, 0x00, 12);
552
+	ret = at24_read_private(at24_private, buf, 0x10, 6);
553
+	if (ret > 0)
554
+	{
555
+		*mac = buf[0];
556
+		*(mac + 1) = buf[1];
557
+		*(mac + 2) = buf[2];
558
+		*(mac + 3) = buf[3];
559
+		*(mac + 4) = buf[4];
560
+		*(mac + 5) = buf[5];
561
+	}
562
+	printk("at24_mac1_read ...............\n");
563
+	return ret;
564
+}
565
+EXPORT_SYMBOL(at24_mac1_read);
566
+
424567 static int at24_write(void *priv, unsigned int off, void *val, size_t count)
425568 {
426569 	struct at24_data *at24;
....@@ -630,6 +773,7 @@
630773 	u8 test_byte;
631774 	int err;
632775 
776
+	printk("ben %s ...\n", __func__);
633777 	i2c_fn_i2c = i2c_check_functionality(client->adapter, I2C_FUNC_I2C);
634778 	i2c_fn_block = i2c_check_functionality(client->adapter,
635779 					       I2C_FUNC_SMBUS_WRITE_I2C_BLOCK);
....@@ -674,6 +818,7 @@
674818 	if (!at24)
675819 		return -ENOMEM;
676820 
821
+	at24_private = at24;
677822 	mutex_init(&at24->lock);
678823 	at24->byte_len = pdata.byte_len;
679824 	at24->page_size = pdata.page_size;
....@@ -792,7 +937,8 @@
792937 	at24_io_limit = rounddown_pow_of_two(at24_io_limit);
793938 	return i2c_add_driver(&at24_driver);
794939 }
795
-module_init(at24_init);
940
+//module_init(at24_init);
941
+postcore_initcall_sync(at24_init);
796942 
797943 static void __exit at24_exit(void)
798944 {


 kernel/drivers/net/ethernet/stmicro/stmmac/Kconfig
....@@ -12,25 +12,6 @@
1212 
1313 if STMMAC_ETH
1414 
15
-config STMMAC_ETHTOOL
16
-	bool "Ethtool feature for STMMAC"
17
-	default STMMAC_ETH
18
-	help
19
-	  This selects the ethtool function, default is Y.
20
-
21
-config STMMAC_FULL
22
-	bool "Support full driver for STMMAC"
23
-	default STMMAC_ETH
24
-	help
25
-	  This selects the full function, default is Y, full-featured version
26
-	  includes 4.10 and other versions, if it is N, only 4.10 core working.
27
-
28
-config STMMAC_PTP
29
-	bool "PTP feature for STMMAC"
30
-	default STMMAC_ETH
31
-	help
32
-	  This selects the ptp timestamp function, default is Y.
33
-
3415 config STMMAC_PLATFORM
3516 	tristate "STMMAC Platform bus support"
3617 	depends on STMMAC_ETH
....@@ -126,16 +107,6 @@
126107 
127108 	  This selects the Rockchip RK3288 SoC glue layer support for
128109 	  the stmmac device driver.
129
-
130
-config DWMAC_ROCKCHIP_TOOL
131
-	bool "Rockchip dwmac tool support"
132
-	depends on DWMAC_ROCKCHIP
133
-	default DWMAC_ROCKCHIP
134
-	help
135
-	  Support for Ethernet functions on Rockchip SoCs.
136
-
137
-	  This selects the features for Rockchip's Ethernet, include PHY loopback,
138
-	  MAC loopback, and delayline scanning of RGMII mode.
139110 
140111 config DWMAC_SOCFPGA
141112 	tristate "SOCFPGA dwmac support"


 kernel/drivers/net/ethernet/stmicro/stmmac/Makefile
....@@ -1,19 +1,12 @@
11 # SPDX-License-Identifier: GPL-2.0
22 obj-$(CONFIG_STMMAC_ETH) += stmmac.o
3
-
4
-stmmac-objs:= stmmac_main.o stmmac_mdio.o dwmac_lib.o	\
5
-	      mmc_core.o dwmac4_descs.o dwmac4_dma.o	\
6
-	      dwmac4_lib.o dwmac4_core.o hwif.o	\
3
+stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o	\
4
+	      chain_mode.o dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o	\
5
+	      dwmac100_core.o dwmac100_dma.o enh_desc.o norm_desc.o	\
6
+	      mmc_core.o stmmac_hwtstamp.o stmmac_ptp.o dwmac4_descs.o	\
7
+	      dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o hwif.o \
8
+	      stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o dwxgmac2_descs.o \
79 	      $(stmmac-y)
8
-
9
-stmmac-$(CONFIG_STMMAC_FULL) += ring_mode.o chain_mode.o dwmac1000_core.o	\
10
-				dwmac1000_dma.o dwmac100_core.o dwmac100_dma.o	\
11
-				enh_desc.o norm_desc.o dwmac5.o stmmac_tc.o	\
12
-				dwxgmac2_core.o dwxgmac2_dma.o dwxgmac2_descs.o
13
-
14
-stmmac-$(CONFIG_STMMAC_ETHTOOL) += stmmac_ethtool.o
15
-
16
-stmmac-$(CONFIG_STMMAC_PTP) += stmmac_hwtstamp.o stmmac_ptp.o
1710 
1811 # Ordering matters. Generic driver must be last.
1912 obj-$(CONFIG_STMMAC_PLATFORM)	+= stmmac-platform.o
....@@ -23,8 +16,7 @@
2316 obj-$(CONFIG_DWMAC_MESON)	+= dwmac-meson.o dwmac-meson8b.o
2417 obj-$(CONFIG_DWMAC_OXNAS)	+= dwmac-oxnas.o
2518 obj-$(CONFIG_DWMAC_ROCKCHIP)	+= dwmac-rockchip.o
26
-dwmac-rockchip-objs := dwmac-rk.o
27
-dwmac-rockchip-$(CONFIG_DWMAC_ROCKCHIP_TOOL) += dwmac-rk-tool.o
19
+dwmac-rockchip-objs := dwmac-rk.o dwmac-rk-tool.o
2820 obj-$(CONFIG_DWMAC_SOCFPGA)	+= dwmac-altr-socfpga.o
2921 obj-$(CONFIG_DWMAC_STI)		+= dwmac-sti.o
3022 obj-$(CONFIG_DWMAC_STM32)	+= dwmac-stm32.o


 kernel/drivers/net/ethernet/stmicro/stmmac/common.h
....@@ -261,7 +261,7 @@
261261 #define STMMAC_COAL_TX_TIMER	1000
262262 #define STMMAC_MAX_COAL_TX_TICK	100000
263263 #define STMMAC_TX_MAX_FRAMES	256
264
-#define STMMAC_TX_FRAMES	25
264
+#define STMMAC_TX_FRAMES	1
265265 
266266 /* Packets types */
267267 enum packets_types {


 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-generic.c
....@@ -71,7 +71,6 @@
7171 
7272 static const struct of_device_id dwmac_generic_match[] = {
7373 	{ .compatible = "st,spear600-gmac"},
74
-	{ .compatible = "snps,dwmac-3.40a"},
7574 	{ .compatible = "snps,dwmac-3.50a"},
7675 	{ .compatible = "snps,dwmac-3.610"},
7776 	{ .compatible = "snps,dwmac-3.70a"},


 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
....@@ -288,7 +288,10 @@
288288 		val &= ~NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
289289 		break;
290290 	default:
291
-		goto err_unsupported_phy;
291
+		dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n",
292
+			phy_modes(gmac->phy_mode));
293
+		err = -EINVAL;
294
+		goto err_remove_config_dt;
292295 	}
293296 	regmap_write(gmac->nss_common, NSS_COMMON_GMAC_CTL(gmac->id), val);
294297 
....@@ -305,7 +308,10 @@
305308 			NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
306309 		break;
307310 	default:
308
-		goto err_unsupported_phy;
311
+		dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n",
312
+			phy_modes(gmac->phy_mode));
313
+		err = -EINVAL;
314
+		goto err_remove_config_dt;
309315 	}
310316 	regmap_write(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, val);
311317 
....@@ -322,7 +328,8 @@
322328 				NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id);
323329 		break;
324330 	default:
325
-		goto err_unsupported_phy;
331
+		/* We don't get here; the switch above will have errored out */
332
+		unreachable();
326333 	}
327334 	regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
328335 
....@@ -344,19 +351,12 @@
344351 	plat_dat->bsp_priv = gmac;
345352 	plat_dat->fix_mac_speed = ipq806x_gmac_fix_mac_speed;
346353 	plat_dat->multicast_filter_bins = 0;
347
-	plat_dat->tx_fifo_size = 8192;
348
-	plat_dat->rx_fifo_size = 8192;
349354 
350355 	err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
351356 	if (err)
352357 		goto err_remove_config_dt;
353358 
354359 	return 0;
355
-
356
-err_unsupported_phy:
357
-	dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n",
358
-		phy_modes(gmac->phy_mode));
359
-	err = -EINVAL;
360360 
361361 err_remove_config_dt:
362362 	stmmac_remove_config_dt(pdev, plat_dat);


 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk-tool.c
....@@ -545,15 +545,15 @@
545545 static void dwmac_rk_rx_clean(struct stmmac_priv *priv,
546546 			      struct dwmac_rk_lb_priv *lb_priv)
547547 {
548
-	if (likely(lb_priv->rx_skbuff_dma)) {
548
+	struct sk_buff *skb;
549
+
550
+	skb = lb_priv->rx_skbuff;
551
+
552
+	if (likely(lb_priv->rx_skbuff)) {
549553 		dma_unmap_single(priv->device,
550554 				 lb_priv->rx_skbuff_dma,
551555 				 lb_priv->dma_buf_sz, DMA_FROM_DEVICE);
552
-		lb_priv->rx_skbuff_dma = 0;
553
-	}
554
-
555
-	if (likely(lb_priv->rx_skbuff)) {
556
-		dev_consume_skb_any(lb_priv->rx_skbuff);
556
+		dev_kfree_skb(skb);
557557 		lb_priv->rx_skbuff = NULL;
558558 	}
559559 }
....@@ -582,12 +582,7 @@
582582 	}
583583 
584584 	frame_len -= ETH_FCS_LEN;
585
-	prefetch(skb->data - NET_IP_ALIGN);
586585 	skb_put(skb, frame_len);
587
-	dma_unmap_single(priv->device,
588
-			 lb_priv->rx_skbuff_dma,
589
-			 lb_priv->dma_buf_sz,
590
-			 DMA_FROM_DEVICE);
591586 
592587 	return dwmac_rk_loopback_validate(priv, lb_priv, skb);
593588 }
....@@ -621,9 +616,10 @@
621616 static void dwmac_rk_tx_clean(struct stmmac_priv *priv,
622617 			      struct dwmac_rk_lb_priv *lb_priv)
623618 {
624
-	struct sk_buff *skb = lb_priv->tx_skbuff;
619
+	struct sk_buff *skb;
625620 	struct dma_desc *p;
626621 
622
+	skb = lb_priv->tx_skbuff;
627623 	p = lb_priv->dma_tx;
628624 
629625 	if (likely(lb_priv->tx_skbuff_dma)) {
....@@ -635,7 +631,7 @@
635631 	}
636632 
637633 	if (likely(skb)) {
638
-		dev_consume_skb_any(skb);
634
+		dev_kfree_skb(skb);
639635 		lb_priv->tx_skbuff = NULL;
640636 	}
641637 
....@@ -659,10 +655,9 @@
659655 	lb_priv->tx_skbuff = skb;
660656 
661657 	des = dma_map_single(priv->device, skb->data,
662
-			     nopaged_len, DMA_TO_DEVICE);
658
+				    nopaged_len, DMA_TO_DEVICE);
663659 	if (dma_mapping_error(priv->device, des))
664660 		goto dma_map_err;
665
-	lb_priv->tx_skbuff_dma = des;
666661 
667662 	stmmac_set_desc_addr(priv, desc, des);
668663 	lb_priv->tx_skbuff_dma_len = nopaged_len;


 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk-tool.h
....@@ -13,20 +13,8 @@
1313 void dwmac_rk_get_rgmii_delayline(struct stmmac_priv *priv, int *tx_delay, int *rx_delay);
1414 int dwmac_rk_get_phy_interface(struct stmmac_priv *priv);
1515 
16
-#ifdef CONFIG_DWMAC_ROCKCHIP_TOOL
1716 int dwmac_rk_create_loopback_sysfs(struct device *dev);
1817 int dwmac_rk_remove_loopback_sysfs(struct device *device);
19
-#else
20
-static inline int dwmac_rk_create_loopback_sysfs(struct device *dev)
21
-{
22
-	return 0;
23
-}
24
-
25
-static inline int dwmac_rk_remove_loopback_sysfs(struct device *device)
26
-{
27
-	return 0;
28
-}
29
-#endif
3018 
3119 #ifdef CONFIG_DWMAC_RK_AUTO_DELAYLINE
3220 int dwmac_rk_get_rgmii_delayline_from_vendor(struct stmmac_priv *priv);
....@@ -34,3 +22,4 @@
3422 #endif
3523 
3624 #endif /* __DWMAC_RK_TOOL_H__ */
25
+


 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
....@@ -47,10 +47,7 @@
4747 	void (*set_to_qsgmii)(struct rk_priv_data *bsp_priv);
4848 	void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
4949 	void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
50
-	void (*set_sgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
51
-	void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
52
-				    bool enable);
53
-	void (*integrated_phy_power)(struct rk_priv_data *bsp_priv, bool up);
50
+	void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
5451 };
5552 
5653 struct rk_priv_data {
....@@ -64,7 +61,6 @@
6461 	bool clk_enabled;
6562 	bool clock_input;
6663 	bool integrated_phy;
67
-	struct phy *comphy;
6864 
6965 	struct clk *clk_mac;
7066 	struct clk *gmac_clkin;
....@@ -169,10 +165,10 @@
169165 	int ret, i, id = bsp_priv->bus_id;
170166 	u32 val;
171167 
172
-	if (mode == PHY_INTERFACE_MODE_QSGMII && !id)
168
+	if (mode == PHY_INTERFACE_MODE_QSGMII && id > 0)
173169 		return 0;
174170 
175
-	ret = xpcs_soft_reset(bsp_priv, 0);
171
+	ret = xpcs_soft_reset(bsp_priv, id);
176172 	if (ret) {
177173 		dev_err(&bsp_priv->pdev->dev, "xpcs_soft_reset fail %d\n", ret);
178174 		return ret;
....@@ -199,10 +195,10 @@
199195 				   SR_MII_CTRL_AN_ENABLE);
200196 		}
201197 	} else {
202
-		val = xpcs_read(bsp_priv, SR_MII_OFFSET(0) + VR_MII_DIG_CTRL1);
203
-		xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_DIG_CTRL1,
198
+		val = xpcs_read(bsp_priv, SR_MII_OFFSET(id) + VR_MII_DIG_CTRL1);
199
+		xpcs_write(bsp_priv, SR_MII_OFFSET(id) + VR_MII_DIG_CTRL1,
204200 			   val | MII_MAC_AUTO_SW);
205
-		xpcs_write(bsp_priv, SR_MII_OFFSET(0) + MII_BMCR,
201
+		xpcs_write(bsp_priv, SR_MII_OFFSET(id) + MII_BMCR,
206202 			   SR_MII_CTRL_AN_ENABLE);
207203 	}
208204 
....@@ -216,55 +212,8 @@
216212 #define GRF_CLR_BIT(nr)	(BIT(nr+16))
217213 
218214 #define DELAY_ENABLE(soc, tx, rx) \
219
-	((((tx) >= 0) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
220
-	 (((rx) >= 0) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
221
-
222
-#define DELAY_VALUE(soc, tx, rx) \
223
-	((((tx) >= 0) ? soc##_GMAC_CLK_TX_DL_CFG(tx) : 0) | \
224
-	 (((rx) >= 0) ? soc##_GMAC_CLK_RX_DL_CFG(rx) : 0))
225
-
226
-/* Integrated EPHY */
227
-
228
-#define RK_GRF_MACPHY_CON0		0xb00
229
-#define RK_GRF_MACPHY_CON1		0xb04
230
-#define RK_GRF_MACPHY_CON2		0xb08
231
-#define RK_GRF_MACPHY_CON3		0xb0c
232
-
233
-#define RK_MACPHY_ENABLE		GRF_BIT(0)
234
-#define RK_MACPHY_DISABLE		GRF_CLR_BIT(0)
235
-#define RK_MACPHY_CFG_CLK_50M		GRF_BIT(14)
236
-#define RK_GMAC2PHY_RMII_MODE		(GRF_BIT(6) | GRF_CLR_BIT(7))
237
-#define RK_GRF_CON2_MACPHY_ID		HIWORD_UPDATE(0x1234, 0xffff, 0)
238
-#define RK_GRF_CON3_MACPHY_ID		HIWORD_UPDATE(0x35, 0x3f, 0)
239
-
240
-static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)
241
-{
242
-	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
243
-	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
244
-
245
-	regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
246
-	regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
247
-
248
-	if (priv->phy_reset) {
249
-		/* PHY needs to be disabled before trying to reset it */
250
-		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
251
-		if (priv->phy_reset)
252
-			reset_control_assert(priv->phy_reset);
253
-		usleep_range(10, 20);
254
-		if (priv->phy_reset)
255
-			reset_control_deassert(priv->phy_reset);
256
-		usleep_range(10, 20);
257
-		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
258
-		msleep(30);
259
-	}
260
-}
261
-
262
-static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv)
263
-{
264
-	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
265
-	if (priv->phy_reset)
266
-		reset_control_assert(priv->phy_reset);
267
-}
215
+	(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
216
+	 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
268217 
269218 #define PX30_GRF_GMAC_CON1		0x0904
270219 
....@@ -357,10 +306,12 @@
357306 
358307 	regmap_write(bsp_priv->grf, RK1808_GRF_GMAC_CON1,
359308 		     RK1808_GMAC_PHY_INTF_SEL_RGMII |
360
-		     DELAY_ENABLE(RK1808, tx_delay, rx_delay));
309
+		     RK1808_GMAC_RXCLK_DLY_ENABLE |
310
+		     RK1808_GMAC_TXCLK_DLY_ENABLE);
361311 
362312 	regmap_write(bsp_priv->grf, RK1808_GRF_GMAC_CON0,
363
-		     DELAY_VALUE(RK1808, tx_delay, rx_delay));
313
+		     RK1808_GMAC_CLK_RX_DL_CFG(rx_delay) |
314
+		     RK1808_GMAC_CLK_TX_DL_CFG(tx_delay));
364315 }
365316 
366317 static void rk1808_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -488,7 +439,8 @@
488439 		     RK3128_GMAC_RMII_MODE_CLR);
489440 	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
490441 		     DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
491
-		     DELAY_VALUE(RK3128, tx_delay, rx_delay));
442
+		     RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
443
+		     RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
492444 }
493445 
494446 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -604,7 +556,8 @@
604556 		     DELAY_ENABLE(RK3228, tx_delay, rx_delay));
605557 
606558 	regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
607
-		     DELAY_VALUE(RK3128, tx_delay, rx_delay));
559
+		     RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
560
+		     RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
608561 }
609562 
610563 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -667,16 +620,10 @@
667620 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
668621 }
669622 
670
-static void rk3228_integrated_phy_power(struct rk_priv_data *priv, bool up)
623
+static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
671624 {
672
-	if (up) {
673
-		regmap_write(priv->grf, RK3228_GRF_CON_MUX,
674
-			     RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
675
-
676
-		rk_gmac_integrated_ephy_powerup(priv);
677
-	} else {
678
-		rk_gmac_integrated_ephy_powerdown(priv);
679
-	}
625
+	regmap_write(priv->grf, RK3228_GRF_CON_MUX,
626
+		     RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
680627 }
681628 
682629 static const struct rk_gmac_ops rk3228_ops = {
....@@ -684,7 +631,7 @@
684631 	.set_to_rmii = rk3228_set_to_rmii,
685632 	.set_rgmii_speed = rk3228_set_rgmii_speed,
686633 	.set_rmii_speed = rk3228_set_rmii_speed,
687
-	.integrated_phy_power = rk3228_integrated_phy_power,
634
+	.integrated_phy_powerup =  rk3228_integrated_phy_powerup,
688635 };
689636 
690637 #define RK3288_GRF_SOC_CON1	0x0248
....@@ -730,7 +677,8 @@
730677 		     RK3288_GMAC_RMII_MODE_CLR);
731678 	regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
732679 		     DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
733
-		     DELAY_VALUE(RK3288, tx_delay, rx_delay));
680
+		     RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
681
+		     RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
734682 }
735683 
736684 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -901,10 +849,12 @@
901849 	regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
902850 		     RK3328_GMAC_PHY_INTF_SEL_RGMII |
903851 		     RK3328_GMAC_RMII_MODE_CLR |
904
-		     DELAY_ENABLE(RK3328, tx_delay, rx_delay));
852
+		     RK3328_GMAC_RXCLK_DLY_ENABLE |
853
+		     RK3328_GMAC_TXCLK_DLY_ENABLE);
905854 
906855 	regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
907
-		     DELAY_VALUE(RK3328, tx_delay, rx_delay));
856
+		     RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
857
+		     RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
908858 }
909859 
910860 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -972,16 +922,10 @@
972922 		dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
973923 }
974924 
975
-static void rk3328_integrated_phy_power(struct rk_priv_data *priv, bool up)
925
+static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
976926 {
977
-	if (up) {
978
-		regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
979
-			     RK3328_MACPHY_RMII_MODE);
980
-
981
-		rk_gmac_integrated_ephy_powerup(priv);
982
-	} else {
983
-		rk_gmac_integrated_ephy_powerdown(priv);
984
-	}
927
+	regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
928
+		     RK3328_MACPHY_RMII_MODE);
985929 }
986930 
987931 static const struct rk_gmac_ops rk3328_ops = {
....@@ -989,7 +933,7 @@
989933 	.set_to_rmii = rk3328_set_to_rmii,
990934 	.set_rgmii_speed = rk3328_set_rgmii_speed,
991935 	.set_rmii_speed = rk3328_set_rmii_speed,
992
-	.integrated_phy_power = rk3328_integrated_phy_power,
936
+	.integrated_phy_powerup =  rk3328_integrated_phy_powerup,
993937 };
994938 
995939 #define RK3366_GRF_SOC_CON6	0x0418
....@@ -1035,7 +979,8 @@
1035979 		     RK3366_GMAC_RMII_MODE_CLR);
1036980 	regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
1037981 		     DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
1038
-		     DELAY_VALUE(RK3366, tx_delay, rx_delay));
982
+		     RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
983
+		     RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
1039984 }
1040985 
1041986 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -1145,7 +1090,8 @@
11451090 		     RK3368_GMAC_RMII_MODE_CLR);
11461091 	regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
11471092 		     DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
1148
-		     DELAY_VALUE(RK3368, tx_delay, rx_delay));
1093
+		     RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
1094
+		     RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
11491095 }
11501096 
11511097 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -1255,7 +1201,8 @@
12551201 		     RK3399_GMAC_RMII_MODE_CLR);
12561202 	regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
12571203 		     DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
1258
-		     DELAY_VALUE(RK3399, tx_delay, rx_delay));
1204
+		     RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
1205
+		     RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
12591206 }
12601207 
12611208 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -1402,10 +1349,12 @@
14021349 
14031350 	regmap_write(bsp_priv->grf, offset_con1,
14041351 		     RK3568_GMAC_PHY_INTF_SEL_RGMII |
1405
-		     DELAY_ENABLE(RK3568, tx_delay, rx_delay));
1352
+		     RK3568_GMAC_RXCLK_DLY_ENABLE |
1353
+		     RK3568_GMAC_TXCLK_DLY_ENABLE);
14061354 
14071355 	regmap_write(bsp_priv->grf, offset_con0,
1408
-		     DELAY_VALUE(RK3568, tx_delay, rx_delay));
1356
+		     RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
1357
+		     RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
14091358 }
14101359 
14111360 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -1451,34 +1400,6 @@
14511400 			__func__, rate, ret);
14521401 }
14531402 
1454
-static void rk3568_set_gmac_sgmii_speed(struct rk_priv_data *bsp_priv, int speed)
1455
-{
1456
-	struct device *dev = &bsp_priv->pdev->dev;
1457
-	unsigned int ctrl;
1458
-
1459
-	/* Only gmac1 set the speed for port1 */
1460
-	if (!bsp_priv->bus_id)
1461
-		return;
1462
-
1463
-	switch (speed) {
1464
-	case 10:
1465
-		ctrl = BMCR_SPEED10;
1466
-		break;
1467
-	case 100:
1468
-		ctrl = BMCR_SPEED100;
1469
-		break;
1470
-	case 1000:
1471
-		ctrl = BMCR_SPEED1000;
1472
-		break;
1473
-	default:
1474
-		dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1475
-		return;
1476
-	}
1477
-
1478
-	xpcs_write(bsp_priv, SR_MII_OFFSET(bsp_priv->bus_id) + MII_BMCR,
1479
-		   ctrl | BMCR_FULLDPLX);
1480
-}
1481
-
14821403 static const struct rk_gmac_ops rk3568_ops = {
14831404 	.set_to_rgmii = rk3568_set_to_rgmii,
14841405 	.set_to_rmii = rk3568_set_to_rmii,
....@@ -1486,7 +1407,6 @@
14861407 	.set_to_qsgmii = rk3568_set_to_qsgmii,
14871408 	.set_rgmii_speed = rk3568_set_gmac_speed,
14881409 	.set_rmii_speed = rk3568_set_gmac_speed,
1489
-	.set_sgmii_speed = rk3568_set_gmac_sgmii_speed,
14901410 };
14911411 
14921412 #define RV1108_GRF_GMAC_CON0		0X0900
....@@ -1552,18 +1472,21 @@
15521472 		(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
15531473 #define RV1126_GMAC_FLOW_CTRL			GRF_BIT(7)
15541474 #define RV1126_GMAC_FLOW_CTRL_CLR		GRF_CLR_BIT(7)
1555
-#define RV1126_M0_GMAC_RXCLK_DLY_ENABLE		GRF_BIT(1)
1556
-#define RV1126_M0_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(1)
1557
-#define RV1126_M0_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(0)
1558
-#define RV1126_M0_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
1559
-#define RV1126_M1_GMAC_RXCLK_DLY_ENABLE		GRF_BIT(3)
1560
-#define RV1126_M1_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(3)
1561
-#define RV1126_M1_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(2)
1562
-#define RV1126_M1_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(2)
1475
+#define RV1126_GMAC_M0_RXCLK_DLY_ENABLE		GRF_BIT(1)
1476
+#define RV1126_GMAC_M0_RXCLK_DLY_DISABLE	GRF_CLR_BIT(1)
1477
+#define RV1126_GMAC_M0_TXCLK_DLY_ENABLE		GRF_BIT(0)
1478
+#define RV1126_GMAC_M0_TXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
1479
+#define RV1126_GMAC_M1_RXCLK_DLY_ENABLE		GRF_BIT(3)
1480
+#define RV1126_GMAC_M1_RXCLK_DLY_DISABLE	GRF_CLR_BIT(3)
1481
+#define RV1126_GMAC_M1_TXCLK_DLY_ENABLE		GRF_BIT(2)
1482
+#define RV1126_GMAC_M1_TXCLK_DLY_DISABLE	GRF_CLR_BIT(2)
15631483 
1564
-/* RV1126_GRF_GMAC_CON1 && RV1126_GRF_GMAC_CON2 */
1565
-#define RV1126_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
1566
-#define RV1126_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
1484
+/* RV1126_GRF_GMAC_CON1 */
1485
+#define RV1126_GMAC_M0_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
1486
+#define RV1126_GMAC_M0_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
1487
+/* RV1126_GRF_GMAC_CON2 */
1488
+#define RV1126_GMAC_M1_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
1489
+#define RV1126_GMAC_M1_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
15671490 
15681491 static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
15691492 				int tx_delay, int rx_delay)
....@@ -1577,14 +1500,18 @@
15771500 
15781501 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
15791502 		     RV1126_GMAC_PHY_INTF_SEL_RGMII |
1580
-		     DELAY_ENABLE(RV1126_M0, tx_delay, rx_delay) |
1581
-		     DELAY_ENABLE(RV1126_M1, tx_delay, rx_delay));
1503
+		     RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
1504
+		     RV1126_GMAC_M0_TXCLK_DLY_ENABLE |
1505
+		     RV1126_GMAC_M1_RXCLK_DLY_ENABLE |
1506
+		     RV1126_GMAC_M1_TXCLK_DLY_ENABLE);
15821507 
15831508 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1,
1584
-		     DELAY_VALUE(RV1126, tx_delay, rx_delay));
1509
+		     RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) |
1510
+		     RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay));
15851511 
15861512 	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2,
1587
-		     DELAY_VALUE(RV1126, tx_delay, rx_delay));
1513
+		     RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) |
1514
+		     RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
15881515 }
15891516 
15901517 static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
....@@ -1657,6 +1584,50 @@
16571584 	.set_rgmii_speed = rv1126_set_rgmii_speed,
16581585 	.set_rmii_speed = rv1126_set_rmii_speed,
16591586 };
1587
+
1588
+#define RK_GRF_MACPHY_CON0		0xb00
1589
+#define RK_GRF_MACPHY_CON1		0xb04
1590
+#define RK_GRF_MACPHY_CON2		0xb08
1591
+#define RK_GRF_MACPHY_CON3		0xb0c
1592
+
1593
+#define RK_MACPHY_ENABLE		GRF_BIT(0)
1594
+#define RK_MACPHY_DISABLE		GRF_CLR_BIT(0)
1595
+#define RK_MACPHY_CFG_CLK_50M		GRF_BIT(14)
1596
+#define RK_GMAC2PHY_RMII_MODE		(GRF_BIT(6) | GRF_CLR_BIT(7))
1597
+#define RK_GRF_CON2_MACPHY_ID		HIWORD_UPDATE(0x1234, 0xffff, 0)
1598
+#define RK_GRF_CON3_MACPHY_ID		HIWORD_UPDATE(0x35, 0x3f, 0)
1599
+
1600
+static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
1601
+{
1602
+	if (priv->ops->integrated_phy_powerup)
1603
+		priv->ops->integrated_phy_powerup(priv);
1604
+
1605
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
1606
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
1607
+
1608
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
1609
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
1610
+
1611
+	if (priv->phy_reset) {
1612
+		/* PHY needs to be disabled before trying to reset it */
1613
+		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1614
+		if (priv->phy_reset)
1615
+			reset_control_assert(priv->phy_reset);
1616
+		usleep_range(10, 20);
1617
+		if (priv->phy_reset)
1618
+			reset_control_deassert(priv->phy_reset);
1619
+		usleep_range(10, 20);
1620
+		regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
1621
+		msleep(30);
1622
+	}
1623
+}
1624
+
1625
+static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
1626
+{
1627
+	regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1628
+	if (priv->phy_reset)
1629
+		reset_control_assert(priv->phy_reset);
1630
+}
16601631 
16611632 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
16621633 {
....@@ -1777,23 +1748,15 @@
17771748 			if (!IS_ERR(bsp_priv->pclk_xpcs))
17781749 				clk_prepare_enable(bsp_priv->pclk_xpcs);
17791750 
1780
-			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1781
-				bsp_priv->ops->set_clock_selection(bsp_priv, bsp_priv->clock_input,
1782
-								   true);
1783
-
17841751 			/**
17851752 			 * if (!IS_ERR(bsp_priv->clk_mac))
17861753 			 *	clk_prepare_enable(bsp_priv->clk_mac);
17871754 			 */
1788
-			usleep_range(100, 200);
1755
+			mdelay(5);
17891756 			bsp_priv->clk_enabled = true;
17901757 		}
17911758 	} else {
17921759 		if (bsp_priv->clk_enabled) {
1793
-			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1794
-				bsp_priv->ops->set_clock_selection(bsp_priv, bsp_priv->clock_input,
1795
-								   false);
1796
-
17971760 			if (phy_iface == PHY_INTERFACE_MODE_RMII) {
17981761 				clk_disable_unprepare(bsp_priv->mac_clk_rx);
17991762 
....@@ -1890,7 +1853,7 @@
18901853 
18911854 	ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
18921855 	if (ret) {
1893
-		bsp_priv->tx_delay = -1;
1856
+		bsp_priv->tx_delay = 0x30;
18941857 		dev_err(dev, "Can not read property: tx_delay.");
18951858 		dev_err(dev, "set tx_delay to 0x%x\n",
18961859 			bsp_priv->tx_delay);
....@@ -1901,7 +1864,7 @@
19011864 
19021865 	ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
19031866 	if (ret) {
1904
-		bsp_priv->rx_delay = -1;
1867
+		bsp_priv->rx_delay = 0x10;
19051868 		dev_err(dev, "Can not read property: rx_delay.");
19061869 		dev_err(dev, "set rx_delay to 0x%x\n",
19071870 			bsp_priv->rx_delay);
....@@ -1915,11 +1878,14 @@
19151878 	bsp_priv->xpcs = syscon_regmap_lookup_by_phandle(dev->of_node,
19161879 							 "rockchip,xpcs");
19171880 	if (!IS_ERR(bsp_priv->xpcs)) {
1918
-		bsp_priv->comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL);
1919
-		if (IS_ERR(bsp_priv->comphy)) {
1920
-			bsp_priv->comphy = NULL;
1881
+		struct phy *comphy;
1882
+
1883
+		comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL);
1884
+		if (IS_ERR(comphy))
19211885 			dev_err(dev, "devm_of_phy_get error\n");
1922
-		}
1886
+		ret = phy_init(comphy);
1887
+		if (ret)
1888
+			dev_err(dev, "phy_init error\n");
19231889 	}
19241890 
19251891 	if (plat->phy_node) {
....@@ -1961,17 +1927,17 @@
19611927 	case PHY_INTERFACE_MODE_RGMII_ID:
19621928 		dev_info(dev, "init for RGMII_ID\n");
19631929 		if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
1964
-			bsp_priv->ops->set_to_rgmii(bsp_priv, -1, -1);
1930
+			bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
19651931 		break;
19661932 	case PHY_INTERFACE_MODE_RGMII_RXID:
19671933 		dev_info(dev, "init for RGMII_RXID\n");
19681934 		if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
1969
-			bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, -1);
1935
+			bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
19701936 		break;
19711937 	case PHY_INTERFACE_MODE_RGMII_TXID:
19721938 		dev_info(dev, "init for RGMII_TXID\n");
19731939 		if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
1974
-			bsp_priv->ops->set_to_rgmii(bsp_priv, -1, bsp_priv->rx_delay);
1940
+			bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
19751941 		break;
19761942 	case PHY_INTERFACE_MODE_RMII:
19771943 		dev_info(dev, "init for RMII\n");
....@@ -1980,23 +1946,11 @@
19801946 		break;
19811947 	case PHY_INTERFACE_MODE_SGMII:
19821948 		dev_info(dev, "init for SGMII\n");
1983
-		ret = phy_init(bsp_priv->comphy);
1984
-		if (ret) {
1985
-			dev_err(dev, "phy_init error: %d\n", ret);
1986
-			return ret;
1987
-		}
1988
-
19891949 		if (bsp_priv->ops && bsp_priv->ops->set_to_sgmii)
19901950 			bsp_priv->ops->set_to_sgmii(bsp_priv);
19911951 		break;
19921952 	case PHY_INTERFACE_MODE_QSGMII:
19931953 		dev_info(dev, "init for QSGMII\n");
1994
-		ret = phy_init(bsp_priv->comphy);
1995
-		if (ret) {
1996
-			dev_err(dev, "phy_init error: %d\n", ret);
1997
-			return ret;
1998
-		}
1999
-
20001954 		if (bsp_priv->ops && bsp_priv->ops->set_to_qsgmii)
20011955 			bsp_priv->ops->set_to_qsgmii(bsp_priv);
20021956 		break;
....@@ -2013,6 +1967,9 @@
20131967 	pm_runtime_enable(dev);
20141968 	pm_runtime_get_sync(dev);
20151969 
1970
+	if (bsp_priv->integrated_phy)
1971
+		rk_gmac_integrated_phy_powerup(bsp_priv);
1972
+
20161973 	return 0;
20171974 }
20181975 
....@@ -2020,9 +1977,8 @@
20201977 {
20211978 	struct device *dev = &gmac->pdev->dev;
20221979 
2023
-	if (gmac->phy_iface == PHY_INTERFACE_MODE_SGMII ||
2024
-	    gmac->phy_iface == PHY_INTERFACE_MODE_QSGMII)
2025
-		phy_exit(gmac->comphy);
1980
+	if (gmac->integrated_phy)
1981
+		rk_gmac_integrated_phy_powerdown(gmac);
20261982 
20271983 	pm_runtime_put_sync(dev);
20281984 	pm_runtime_disable(dev);
....@@ -2049,26 +2005,11 @@
20492005 			bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
20502006 		break;
20512007 	case PHY_INTERFACE_MODE_SGMII:
2052
-		if (bsp_priv->ops && bsp_priv->ops->set_sgmii_speed)
2053
-			bsp_priv->ops->set_sgmii_speed(bsp_priv, speed);
20542008 	case PHY_INTERFACE_MODE_QSGMII:
20552009 		break;
20562010 	default:
20572011 		dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
20582012 	}
2059
-}
2060
-
2061
-static int rk_integrated_phy_power(void *priv, bool up)
2062
-{
2063
-	struct rk_priv_data *bsp_priv = priv;
2064
-
2065
-	if (!bsp_priv->integrated_phy || !bsp_priv->ops ||
2066
-	    !bsp_priv->ops->integrated_phy_power)
2067
-		return 0;
2068
-
2069
-	bsp_priv->ops->integrated_phy_power(bsp_priv, up);
2070
-
2071
-	return 0;
20722013 }
20732014 
20742015 void dwmac_rk_set_rgmii_delayline(struct stmmac_priv *priv,
....@@ -2109,17 +2050,24 @@
21092050 {
21102051 }
21112052 
2053
+static unsigned char macaddr[6];
2054
+extern ssize_t at24_mac_read(unsigned char* addr);
21122055 void rk_get_eth_addr(void *priv, unsigned char *addr)
21132056 {
21142057 	struct rk_priv_data *bsp_priv = priv;
21152058 	struct device *dev = &bsp_priv->pdev->dev;
2116
-	unsigned char ethaddr[ETH_ALEN * MAX_ETH] = {0};
2117
-	int ret, id = bsp_priv->bus_id;
2059
+	int i;
2060
+	//unsigned char ethaddr[ETH_ALEN * MAX_ETH] = {0};
2061
+	//int ret, id = bsp_priv->bus_id;
21182062 
2063
+	//ben
2064
+	printk("nk-debug:enter rk_get_eth_addr.. \n");
2065
+
2066
+	#if 0
21192067 	rk_devinfo_get_eth_mac(addr);
21202068 	if (is_valid_ether_addr(addr))
21212069 		goto out;
2122
-
2070
+		
21232071 	if (id < 0 || id >= MAX_ETH) {
21242072 		dev_err(dev, "%s: Invalid ethernet bus id %d\n", __func__, id);
21252073 		return;
....@@ -2146,7 +2094,35 @@
21462094 	} else {
21472095 		memcpy(addr, &ethaddr[id * ETH_ALEN], ETH_ALEN);
21482096 	}
2097
+	#endif
2098
+	
2099
+	#if 0
2100
+	macaddr[0] = 0xee;
2101
+	macaddr[1] = 0x31;
2102
+	macaddr[2] = 0x32;
2103
+	macaddr[3] = 0x33;
2104
+	macaddr[4] = 0x34;
2105
+	macaddr[5] = 0x35;
2106
+	
2107
+	memcpy(addr, macaddr, 6);
2108
+	#endif
2109
+	
2110
+	#if 1
2111
+	if (at24_mac_read(macaddr) > 0) {
2112
+		printk("ben %s: at24_mac_read Success!! \n", __func__);
2113
+		memcpy(addr, macaddr, 6);
21492114 
2115
+		printk("Read the Ethernet MAC address from :");
2116
+		for (i = 0; i < 5; i++)
2117
+			printk("%2.2x:", addr[i]);
2118
+ 
2119
+		printk("%2.2x\n", addr[i]);	
2120
+	} else {
2121
+		printk("ben %s: at24_mac_read Failed!! \n", __func__);
2122
+		goto out;
2123
+	}
2124
+	#endif
2125
+	
21502126 out:
21512127 	dev_err(dev, "%s: mac address: %pM\n", __func__, addr);
21522128 }
....@@ -2158,6 +2134,7 @@
21582134 	const struct rk_gmac_ops *data;
21592135 	int ret;
21602136 
2137
+	printk("nk-debug:enter rk_gmac_probe 1.. \n");
21612138 	data = of_device_get_match_data(&pdev->dev);
21622139 	if (!data) {
21632140 		dev_err(&pdev->dev, "no of match data provided\n");
....@@ -2177,7 +2154,6 @@
21772154 
21782155 	plat_dat->fix_mac_speed = rk_fix_speed;
21792156 	plat_dat->get_eth_addr = rk_get_eth_addr;
2180
-	plat_dat->integrated_phy_power = rk_integrated_phy_power;
21812157 
21822158 	plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
21832159 	if (IS_ERR(plat_dat->bsp_priv)) {
....@@ -2185,6 +2161,7 @@
21852161 		goto err_remove_config_dt;
21862162 	}
21872163 
2164
+	printk("nk-debug:enter rk_gmac_probe 2.. \n");
21882165 	ret = rk_gmac_clk_init(plat_dat);
21892166 	if (ret)
21902167 		goto err_remove_config_dt;
....@@ -2254,45 +2231,19 @@
22542231 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
22552232 
22562233 static const struct of_device_id rk_gmac_dwmac_match[] = {
2257
-#ifdef CONFIG_CPU_PX30
22582234 	{ .compatible = "rockchip,px30-gmac",	.data = &px30_ops   },
2259
-#endif
2260
-#ifdef CONFIG_CPU_RK1808
22612235 	{ .compatible = "rockchip,rk1808-gmac", .data = &rk1808_ops },
2262
-#endif
2263
-#ifdef CONFIG_CPU_RK312X
22642236 	{ .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
2265
-#endif
2266
-#ifdef CONFIG_CPU_RK322X
22672237 	{ .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
2268
-#endif
2269
-#ifdef CONFIG_CPU_RK3288
22702238 	{ .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
2271
-#endif
2272
-#ifdef CONFIG_CPU_RK3308
22732239 	{ .compatible = "rockchip,rk3308-mac",  .data = &rk3308_ops },
2274
-#endif
2275
-#ifdef CONFIG_CPU_RK3328
22762240 	{ .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
2277
-#endif
2278
-#ifdef CONFIG_CPU_RK3366
22792241 	{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
2280
-#endif
2281
-#ifdef CONFIG_CPU_RK3368
22822242 	{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
2283
-#endif
2284
-#ifdef CONFIG_CPU_RK3399
22852243 	{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
2286
-#endif
2287
-#ifdef CONFIG_CPU_RK3568
22882244 	{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
2289
-#endif
2290
-#ifdef CONFIG_CPU_RV110X
22912245 	{ .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
2292
-#endif
2293
-#ifdef CONFIG_CPU_RV1126
22942246 	{ .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
2295
-#endif
22962247 	{ }
22972248 };
22982249 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
....@@ -2306,7 +2257,8 @@
23062257 		.of_match_table = rk_gmac_dwmac_match,
23072258 	},
23082259 };
2309
-module_platform_driver(rk_gmac_dwmac_driver);
2260
+//module_platform_driver(rk_gmac_dwmac_driver);
2261
+ module_platform_driver1(rk_gmac_dwmac_driver);
23102262 
23112263 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
23122264 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");


 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
....@@ -86,10 +86,10 @@
8686 #define LPI_CTRL_STATUS_TLPIEN	0x00000001	/* Transmit LPI Entry */
8787 
8888 /* GMAC HW ADDR regs */
89
-#define GMAC_ADDR_HIGH(reg)	((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
90
-				 0x00000040 + (reg * 8))
91
-#define GMAC_ADDR_LOW(reg)	((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
92
-				 0x00000044 + (reg * 8))
89
+#define GMAC_ADDR_HIGH(reg)	(((reg > 15) ? 0x00000800 : 0x00000040) + \
90
+				(reg * 8))
91
+#define GMAC_ADDR_LOW(reg)	(((reg > 15) ? 0x00000804 : 0x00000044) + \
92
+				(reg * 8))
9393 #define GMAC_MAX_PERFECT_ADDRESSES	1
9494 
9595 #define GMAC_PCS_BASE		0x000000c0	/* PCS register base */


 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
....@@ -715,7 +715,6 @@
715715 		x->mac_gmii_rx_proto_engine++;
716716 }
717717 
718
-#ifdef CONFIG_STMMAC_FULL
719718 const struct stmmac_ops dwmac4_ops = {
720719 	.core_init = dwmac4_core_init,
721720 	.set_mac = stmmac_set_mac,
....@@ -746,7 +745,6 @@
746745 	.debug = dwmac4_debug,
747746 	.set_filter = dwmac4_set_filter,
748747 };
749
-#endif
750748 
751749 const struct stmmac_ops dwmac410_ops = {
752750 	.core_init = dwmac4_core_init,
....@@ -779,7 +777,6 @@
779777 	.set_filter = dwmac4_set_filter,
780778 };
781779 
782
-#ifdef CONFIG_STMMAC_FULL
783780 const struct stmmac_ops dwmac510_ops = {
784781 	.core_init = dwmac4_core_init,
785782 	.set_mac = stmmac_dwmac4_set_mac,
....@@ -815,7 +812,6 @@
815812 	.rxp_config = dwmac5_rxp_config,
816813 	.flex_pps_config = dwmac5_flex_pps_config,
817814 };
818
-#endif
819815 
820816 int dwmac4_setup(struct stmmac_priv *priv)
821817 {


 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
....@@ -119,23 +119,6 @@
119119 	       ioaddr + DMA_CHAN_INTR_ENA(chan));
120120 }
121121 
122
-static void dwmac410_dma_init_channel(void __iomem *ioaddr,
123
-				      struct stmmac_dma_cfg *dma_cfg, u32 chan)
124
-{
125
-	u32 value;
126
-
127
-	/* common channel control register config */
128
-	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
129
-	if (dma_cfg->pblx8)
130
-		value = value | DMA_BUS_MODE_PBL;
131
-
132
-	writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
133
-
134
-	/* Mask interrupts by writing to CSR7 */
135
-	writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,
136
-	       ioaddr + DMA_CHAN_INTR_ENA(chan));
137
-}
138
-
139122 static void dwmac4_dma_init(void __iomem *ioaddr,
140123 			    struct stmmac_dma_cfg *dma_cfg, int atds)
141124 {
....@@ -214,7 +197,7 @@
214197 				       u32 channel, int fifosz, u8 qmode)
215198 {
216199 	unsigned int rqs = fifosz / 256 - 1;
217
-	u32 mtl_rx_op;
200
+	u32 mtl_rx_op, mtl_rx_int;
218201 
219202 	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));
220203 
....@@ -285,6 +268,11 @@
285268 	}
286269 
287270 	writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));
271
+
272
+	/* Enable MTL RX overflow */
273
+	mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));
274
+	writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN,
275
+	       ioaddr + MTL_CHAN_INT_CTRL(channel));
288276 }
289277 
290278 static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode,
....@@ -473,7 +461,7 @@
473461 const struct stmmac_dma_ops dwmac410_dma_ops = {
474462 	.reset = dwmac4_dma_reset,
475463 	.init = dwmac4_dma_init,
476
-	.init_chan = dwmac410_dma_init_channel,
464
+	.init_chan = dwmac4_dma_init_channel,
477465 	.init_rx_chan = dwmac4_dma_init_rx_chan,
478466 	.init_tx_chan = dwmac4_dma_init_tx_chan,
479467 	.axi = dwmac4_dma_axi,


 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
....@@ -63,6 +63,10 @@
6363 
6464 	value &= ~DMA_CONTROL_ST;
6565 	writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan));
66
+
67
+	value = readl(ioaddr + GMAC_CONFIG);
68
+	value &= ~GMAC_CONFIG_TE;
69
+	writel(value, ioaddr + GMAC_CONFIG);
6670 }
6771 
6872 void dwmac4_dma_start_rx(void __iomem *ioaddr, u32 chan)


 kernel/drivers/net/ethernet/stmicro/stmmac/hwif.c
....@@ -23,7 +23,6 @@
2323 	return reg & GENMASK(7, 0);
2424 }
2525 
26
-#ifdef CONFIG_STMMAC_FULL
2726 static void stmmac_dwmac_mode_quirk(struct stmmac_priv *priv)
2827 {
2928 	struct mac_device_info *mac = priv->hw;
....@@ -69,7 +68,6 @@
6968 	stmmac_dwmac_mode_quirk(priv);
7069 	return 0;
7170 }
72
-#endif
7371 
7472 static const struct stmmac_hwif_entry {
7573 	bool gmac;
....@@ -80,16 +78,13 @@
8078 	const void *desc;
8179 	const void *dma;
8280 	const void *mac;
83
-#ifdef CONFIG_STMMAC_PTP
8481 	const void *hwtimestamp;
85
-#endif
8682 	const void *mode;
8783 	const void *tc;
8884 	int (*setup)(struct stmmac_priv *priv);
8985 	int (*quirks)(struct stmmac_priv *priv);
9086 } stmmac_hw[] = {
9187 	/* NOTE: New HW versions shall go to the end of this table */
92
-#ifdef CONFIG_STMMAC_FULL
9388 	{
9489 		.gmac = false,
9590 		.gmac4 = false,
....@@ -102,9 +97,7 @@
10297 		.desc = NULL,
10398 		.dma = &dwmac100_dma_ops,
10499 		.mac = &dwmac100_ops,
105
-#ifdef CONFIG_STMMAC_PTP
106100 		.hwtimestamp = &stmmac_ptp,
107
-#endif
108101 		.mode = NULL,
109102 		.tc = NULL,
110103 		.setup = dwmac100_setup,
....@@ -121,9 +114,7 @@
121114 		.desc = NULL,
122115 		.dma = &dwmac1000_dma_ops,
123116 		.mac = &dwmac1000_ops,
124
-#ifdef CONFIG_STMMAC_PTP
125117 		.hwtimestamp = &stmmac_ptp,
126
-#endif
127118 		.mode = NULL,
128119 		.tc = NULL,
129120 		.setup = dwmac1000_setup,
....@@ -140,9 +131,7 @@
140131 		.desc = &dwmac4_desc_ops,
141132 		.dma = &dwmac4_dma_ops,
142133 		.mac = &dwmac4_ops,
143
-#ifdef CONFIG_STMMAC_PTP
144134 		.hwtimestamp = &stmmac_ptp,
145
-#endif
146135 		.mode = NULL,
147136 		.tc = NULL,
148137 		.setup = dwmac4_setup,
....@@ -159,16 +148,12 @@
159148 		.desc = &dwmac4_desc_ops,
160149 		.dma = &dwmac4_dma_ops,
161150 		.mac = &dwmac410_ops,
162
-#ifdef CONFIG_STMMAC_PTP
163151 		.hwtimestamp = &stmmac_ptp,
164
-#endif
165152 		.mode = &dwmac4_ring_mode_ops,
166153 		.tc = NULL,
167154 		.setup = dwmac4_setup,
168155 		.quirks = NULL,
169
-	},
170
-#endif /* CONFIG_STMMAC_FULL */
171
-	{
156
+	}, {
172157 		.gmac = false,
173158 		.gmac4 = true,
174159 		.xgmac = false,
....@@ -180,16 +165,12 @@
180165 		.desc = &dwmac4_desc_ops,
181166 		.dma = &dwmac410_dma_ops,
182167 		.mac = &dwmac410_ops,
183
-#ifdef CONFIG_STMMAC_PTP
184168 		.hwtimestamp = &stmmac_ptp,
185
-#endif
186169 		.mode = &dwmac4_ring_mode_ops,
187170 		.tc = NULL,
188171 		.setup = dwmac4_setup,
189172 		.quirks = NULL,
190
-	},
191
-#ifdef CONFIG_STMMAC_FULL
192
-	{
173
+	}, {
193174 		.gmac = false,
194175 		.gmac4 = true,
195176 		.xgmac = false,
....@@ -201,9 +182,7 @@
201182 		.desc = &dwmac4_desc_ops,
202183 		.dma = &dwmac410_dma_ops,
203184 		.mac = &dwmac510_ops,
204
-#ifdef CONFIG_STMMAC_PTP
205185 		.hwtimestamp = &stmmac_ptp,
206
-#endif
207186 		.mode = &dwmac4_ring_mode_ops,
208187 		.tc = &dwmac510_tc_ops,
209188 		.setup = dwmac4_setup,
....@@ -220,15 +199,12 @@
220199 		.desc = &dwxgmac210_desc_ops,
221200 		.dma = &dwxgmac210_dma_ops,
222201 		.mac = &dwxgmac210_ops,
223
-#ifdef CONFIG_STMMAC_PTP
224202 		.hwtimestamp = &stmmac_ptp,
225
-#endif
226203 		.mode = NULL,
227204 		.tc = NULL,
228205 		.setup = dwxgmac2_setup,
229206 		.quirks = NULL,
230207 	},
231
-#endif
232208 };
233209 
234210 int stmmac_hwif_init(struct stmmac_priv *priv)
....@@ -288,9 +264,7 @@
288264 		mac->desc = mac->desc ? : entry->desc;
289265 		mac->dma = mac->dma ? : entry->dma;
290266 		mac->mac = mac->mac ? : entry->mac;
291
-#ifdef CONFIG_STMMAC_PTP
292267 		mac->ptp = mac->ptp ? : entry->hwtimestamp;
293
-#endif
294268 		mac->mode = mac->mode ? : entry->mode;
295269 		mac->tc = mac->tc ? : entry->tc;
296270 


 kernel/drivers/net/ethernet/stmicro/stmmac/stmmac.h
....@@ -217,27 +217,10 @@
217217 int stmmac_mdio_unregister(struct net_device *ndev);
218218 int stmmac_mdio_register(struct net_device *ndev);
219219 int stmmac_mdio_reset(struct mii_bus *mii);
220
-
221
-#ifdef CONFIG_STMMAC_ETHTOOL
222220 void stmmac_set_ethtool_ops(struct net_device *netdev);
223
-#else
224
-static inline void stmmac_set_ethtool_ops(struct net_device *netdev)
225
-{
226
-}
227
-#endif
228221 
229
-#ifdef CONFIG_STMMAC_PTP
230222 void stmmac_ptp_register(struct stmmac_priv *priv);
231223 void stmmac_ptp_unregister(struct stmmac_priv *priv);
232
-#else
233
-static inline void stmmac_ptp_register(struct stmmac_priv *priv)
234
-{
235
-}
236
-
237
-static inline void stmmac_ptp_unregister(struct stmmac_priv *priv)
238
-{
239
-}
240
-#endif
241224 int stmmac_resume(struct device *dev);
242225 int stmmac_suspend(struct device *dev);
243226 int stmmac_dvr_remove(struct device *dev);


 kernel/drivers/net/ethernet/stmicro/stmmac/stmmac_hwtstamp.c
....@@ -159,20 +159,15 @@
159159 
160160 static void get_systime(void __iomem *ioaddr, u64 *systime)
161161 {
162
-	u64 ns, sec0, sec1;
162
+	u64 ns;
163163 
164
-	/* Get the TSS value */
165
-	sec1 = readl_relaxed(ioaddr + PTP_STSR);
166
-	do {
167
-		sec0 = sec1;
168
-		/* Get the TSSS value */
169
-		ns = readl_relaxed(ioaddr + PTP_STNSR);
170
-		/* Get the TSS value */
171
-		sec1 = readl_relaxed(ioaddr + PTP_STSR);
172
-	} while (sec0 != sec1);
164
+	/* Get the TSSS value */
165
+	ns = readl(ioaddr + PTP_STNSR);
166
+	/* Get the TSS and convert sec time value to nanosecond */
167
+	ns += readl(ioaddr + PTP_STSR) * 1000000000ULL;
173168 
174169 	if (systime)
175
-		*systime = ns + (sec1 * 1000000000ULL);
170
+		*systime = ns;
176171 }
177172 
178173 const struct stmmac_hwtimestamp stmmac_ptp = {


 kernel/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
....@@ -228,7 +228,7 @@
228228 			priv->clk_csr = STMMAC_CSR_100_150M;
229229 		else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
230230 			priv->clk_csr = STMMAC_CSR_150_250M;
231
-		else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
231
+		else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
232232 			priv->clk_csr = STMMAC_CSR_250_300M;
233233 	}
234234 
....@@ -508,7 +508,6 @@
508508 	}
509509 }
510510 
511
-#ifdef CONFIG_STMMAC_PTP
512511 /**
513512  *  stmmac_hwtstamp_set - control hardware timestamping.
514513  *  @dev: device pointer.
....@@ -761,7 +760,6 @@
761760 	return copy_to_user(ifr->ifr_data, config,
762761 			    sizeof(*config)) ? -EFAULT : 0;
763762 }
764
-#endif /* CONFIG_STMMAC_PTP */
765763 
766764 /**
767765  * stmmac_init_ptp - init PTP
....@@ -802,7 +800,7 @@
802800 
803801 static void stmmac_release_ptp(struct stmmac_priv *priv)
804802 {
805
-	if (priv->plat->clk_ptp_ref && IS_ENABLED(CONFIG_STMMAC_PTP))
803
+	if (priv->plat->clk_ptp_ref)
806804 		clk_disable_unprepare(priv->plat->clk_ptp_ref);
807805 	stmmac_ptp_unregister(priv);
808806 }
....@@ -936,6 +934,23 @@
936934 	}
937935 }
938936 
937
+static void rtl8211F_led_control(struct phy_device *phydev)
938
+{
939
+	printk("ben debug:rtl8211F_led_control...1 \n");
940
+
941
+       	if(!phydev) return;
942
+       	if(phydev->phy_id!=0x001cc916) return; /* only for 8211E*/
943
+
944
+       	/*switch to extension page44*/
945
+	phy_write(phydev, 31, 0x0d04);
946
+//add hc 1000M --> orange   
947
+//	 100M  --> green
948
+	phy_write(phydev, 16, 0x6D02);  
949
+//add hc 1000M&100M  --> green
950
+//     	phy_write(phydev, 16, 0x6C0A); 
951
+	printk("ben debug:rtl8211F_led_control...2 \n");
952
+}
953
+
939954 /**
940955  * stmmac_init_phy - PHY initialization
941956  * @dev: net device structure
....@@ -956,9 +971,6 @@
956971 	priv->oldlink = false;
957972 	priv->speed = SPEED_UNKNOWN;
958973 	priv->oldduplex = DUPLEX_UNKNOWN;
959
-
960
-	if (priv->plat->integrated_phy_power)
961
-		priv->plat->integrated_phy_power(priv->plat->bsp_priv, true);
962974 
963975 	if (priv->plat->phy_node) {
964976 		phydev = of_phy_connect(dev, priv->plat->phy_node,
....@@ -1020,6 +1032,9 @@
10201032 		phydev->irq = PHY_POLL;
10211033 
10221034 	phy_attached_info(phydev);
1035
+
1036
+	//add ben
1037
+	rtl8211F_led_control(phydev);
10231038 	return 0;
10241039 }
10251040 
....@@ -2159,7 +2174,8 @@
21592174  */
21602175 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
21612176 {
2162
-	if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2177
+	//if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2178
+	if (1) {
21632179 		stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
21642180 		if (likely(priv->plat->get_eth_addr))
21652181 			priv->plat->get_eth_addr(priv->plat->bsp_priv,
....@@ -2552,7 +2568,7 @@
25522568 
25532569 	stmmac_mmc_setup(priv);
25542570 
2555
-	if (IS_ENABLED(CONFIG_STMMAC_PTP) && init_ptp) {
2571
+	if (init_ptp) {
25562572 		ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
25572573 		if (ret < 0)
25582574 			netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
....@@ -2594,8 +2610,7 @@
25942610 {
25952611 	struct stmmac_priv *priv = netdev_priv(dev);
25962612 
2597
-	if (IS_ENABLED(CONFIG_STMMAC_PTP))
2598
-		clk_disable_unprepare(priv->plat->clk_ptp_ref);
2613
+	clk_disable_unprepare(priv->plat->clk_ptp_ref);
25992614 }
26002615 
26012616 /**
....@@ -2733,9 +2748,6 @@
27332748 	if (dev->phydev) {
27342749 		phy_stop(dev->phydev);
27352750 		phy_disconnect(dev->phydev);
2736
-		if (priv->plat->integrated_phy_power)
2737
-			priv->plat->integrated_phy_power(priv->plat->bsp_priv,
2738
-							 false);
27392751 	}
27402752 
27412753 	stmmac_disable_all_queues(priv);
....@@ -2766,8 +2778,7 @@
27662778 
27672779 	netif_carrier_off(dev);
27682780 
2769
-	if (IS_ENABLED(CONFIG_STMMAC_PTP))
2770
-		stmmac_release_ptp(priv);
2781
+	stmmac_release_ptp(priv);
27712782 
27722783 	return 0;
27732784 }
....@@ -3746,6 +3757,7 @@
37463757 	/* To handle GMAC own interrupts */
37473758 	if ((priv->plat->has_gmac) || xmac) {
37483759 		int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3760
+		int mtl_status;
37493761 
37503762 		if (unlikely(status)) {
37513763 			/* For LPI we need to save the tx status */
....@@ -3756,8 +3768,17 @@
37563768 		}
37573769 
37583770 		for (queue = 0; queue < queues_count; queue++) {
3759
-			status = stmmac_host_mtl_irq_status(priv, priv->hw,
3760
-							    queue);
3771
+			struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3772
+
3773
+			mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3774
+								queue);
3775
+			if (mtl_status != -EINVAL)
3776
+				status |= mtl_status;
3777
+
3778
+			if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3779
+				stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3780
+						       rx_q->rx_tail_addr,
3781
+						       queue);
37613782 		}
37623783 
37633784 		/* PCS link status */
....@@ -3811,14 +3832,12 @@
38113832 			return -EINVAL;
38123833 		ret = phy_mii_ioctl(dev->phydev, rq, cmd);
38133834 		break;
3814
-#ifdef CONFIG_STMMAC_PTP
38153835 	case SIOCSHWTSTAMP:
38163836 		ret = stmmac_hwtstamp_set(dev, rq);
38173837 		break;
38183838 	case SIOCGHWTSTAMP:
38193839 		ret = stmmac_hwtstamp_get(dev, rq);
38203840 		break;
3821
-#endif
38223841 	default:
38233842 		break;
38243843 	}
....@@ -4565,13 +4584,10 @@
45654584 		stmmac_pmt(priv, priv->hw, priv->wolopts);
45664585 		priv->irq_wake = 1;
45674586 	} else {
4568
-		if (priv->plat->integrated_phy_power)
4569
-			priv->plat->integrated_phy_power(priv->plat->bsp_priv,
4570
-							 false);
45714587 		stmmac_mac_set(priv, priv->ioaddr, false);
45724588 		pinctrl_pm_select_sleep_state(priv->device);
45734589 		/* Disable clock in case of PWM is off */
4574
-		if (priv->plat->clk_ptp_ref && IS_ENABLED(CONFIG_STMMAC_PTP))
4590
+		if (priv->plat->clk_ptp_ref)
45754591 			clk_disable_unprepare(priv->plat->clk_ptp_ref);
45764592 		clk_disable_unprepare(priv->plat->pclk);
45774593 		clk_disable_unprepare(priv->plat->stmmac_clk);
....@@ -4608,8 +4624,6 @@
46084624 		tx_q->cur_tx = 0;
46094625 		tx_q->dirty_tx = 0;
46104626 		tx_q->mss = 0;
4611
-
4612
-		netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
46134627 	}
46144628 }
46154629 
....@@ -4627,6 +4641,7 @@
46274641 	if (!netif_running(ndev))
46284642 		return 0;
46294643 
4644
+	printk("troy test %s start .... \n",__func__);
46304645 	/* Power Down bit, into the PM register, is cleared
46314646 	 * automatically as soon as a magic packet or a Wake-up frame
46324647 	 * is received. Anyway, it's better to manually clear
....@@ -4643,14 +4658,11 @@
46434658 		/* enable the clk previously disabled */
46444659 		clk_prepare_enable(priv->plat->stmmac_clk);
46454660 		clk_prepare_enable(priv->plat->pclk);
4646
-		if (priv->plat->clk_ptp_ref && IS_ENABLED(CONFIG_STMMAC_PTP))
4661
+		if (priv->plat->clk_ptp_ref)
46474662 			clk_prepare_enable(priv->plat->clk_ptp_ref);
46484663 		/* reset the phy so that it's ready */
46494664 		if (priv->mii)
46504665 			stmmac_mdio_reset(priv->mii);
4651
-		if (priv->plat->integrated_phy_power)
4652
-			priv->plat->integrated_phy_power(priv->plat->bsp_priv,
4653
-							 true);
46544666 	}
46554667 
46564668 	mutex_lock(&priv->lock);
....@@ -4672,6 +4684,8 @@
46724684 
46734685 	if (ndev->phydev)
46744686 		phy_start(ndev->phydev);
4687
+	printk("troy test %s end .... \n",__func__);
4688
+	rtl8211F_led_control(ndev->phydev);
46754689 
46764690 	return 0;
46774691 }


 kernel/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
....@@ -469,14 +469,6 @@
469469 		plat->pmt = 1;
470470 	}
471471 
472
-	if (of_device_is_compatible(np, "snps,dwmac-3.40a")) {
473
-		plat->has_gmac = 1;
474
-		plat->enh_desc = 1;
475
-		plat->tx_coe = 1;
476
-		plat->bugged_jumbo = 1;
477
-		plat->pmt = 1;
478
-	}
479
-
480472 	if (of_device_is_compatible(np, "snps,dwmac-4.00") ||
481473 	    of_device_is_compatible(np, "snps,dwmac-4.10a") ||
482474 	    of_device_is_compatible(np, "snps,dwmac-4.20a")) {


 kernel/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c
....@@ -314,12 +314,7 @@
314314 
315315 		priv->plat->tx_queues_cfg[queue].mode_to_use = MTL_QUEUE_AVB;
316316 	} else if (!qopt->enable) {
317
-		ret = stmmac_dma_qmode(priv, priv->ioaddr, queue,
318
-				       MTL_QUEUE_DCB);
319
-		if (ret)
320
-			return ret;
321
-
322
-		priv->plat->tx_queues_cfg[queue].mode_to_use = MTL_QUEUE_DCB;
317
+		return stmmac_dma_qmode(priv, priv->ioaddr, queue, MTL_QUEUE_DCB);
323318 	}
324319 
325320 	/* Port Transmit Rate and Speed Divider */


 kernel/include/linux/device.h
....@@ -1711,6 +1711,17 @@
17111711 } \
17121712 module_exit(__driver##_exit);
17131713 
1714
+#define module_driver1(__driver, __register, __unregister, ...) \
1715
+static int __init __driver##_init(void) \
1716
+{ \
1717
+        return __register(&(__driver) , ##__VA_ARGS__); \
1718
+} \
1719
+arch_initcall(__driver##_init); \
1720
+static void __exit __driver##_exit(void) \
1721
+{ \
1722
+        __unregister(&(__driver) , ##__VA_ARGS__); \
1723
+} \
1724
+module_exit(__driver##_exit);
17141725 /**
17151726  * builtin_driver() - Helper macro for drivers that don't do anything
17161727  * special in init and have no exit. This eliminates some boilerplate.


 kernel/include/linux/platform_device.h
....@@ -234,6 +234,10 @@
234234 	module_driver(__platform_driver, platform_driver_register, \
235235 			platform_driver_unregister)
236236 
237
+#define module_platform_driver1(__platform_driver) \
238
+       module_driver1(__platform_driver, platform_driver_register, \
239
+                       platform_driver_unregister)
240
+
237241 /* builtin_platform_driver() - Helper macro for builtin drivers that
238242  * don't do anything special in driver init.  This eliminates some
239243  * boilerplate.  Each driver may only use this macro once, and


 rockdev/parameter.txt
....@@ -0,0 +1 @@
1
+../device/rockchip/rk356x/parameter-buildroot-fit.txt