hc
2023-11-06 9df731a176aab8e03b984b681b1bea01ccff6644
rk3568 rt uboot init
12 files deleted
1 files copied
107 files added
288 files modified
13 files renamed
106927 ■■■■ changed files
u-boot/Kconfig 15 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/Kconfig 4 ●●●● patch | view | raw | blame | history
u-boot/arch/arm/cpu/armv7/start.S 2 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/cpu/armv8/Kconfig 15 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/cpu/armv8/Makefile 2 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/cpu/armv8/sha1_ce_core.S 132 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/cpu/armv8/sha1_ce_glue.c 21 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/cpu/armv8/sha256_ce_core.S 134 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/cpu/armv8/sha256_ce_glue.c 21 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/cpu/armv8/start.S 74 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/Makefile 2 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/px30-u-boot.dtsi 7 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/px30.dtsi 7 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3036-sdk-u-boot.dtsi 28 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3036-sdk.dts 14 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3036.dtsi 29 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3128-u-boot.dtsi 5 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3128.dtsi 14 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3308-u-boot.dtsi 12 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3308.dtsi 7 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3528-evb.dts 31 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3528-pinctrl.dtsi 1241 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3528-u-boot.dtsi 206 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3528.dtsi 2184 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3562-evb.dts 31 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3562-pinctrl.dtsi 1872 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3562-u-boot.dtsi 203 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3562.dtsi 2325 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3568-u-boot.dtsi 33 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3568.dtsi 8 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3588-u-boot.dtsi 3 ●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3588.dtsi 4 ●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rk3588s.dtsi 21 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rv1106-evb2.dts 22 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rv1106-u-boot.dtsi 42 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rv1106.dtsi 2 ●●● patch | view | raw | blame | history
u-boot/arch/arm/dts/rv1126-u-boot.dtsi 9 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/boot_mode.h 2 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/clock.h 8 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3528.h 396 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3562.h 416 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/fit.h 2 ●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3528.h 89 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3562.h 76 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/ioc_rk3528.h 196 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/ioc_rk3562.h 211 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/pcie_ep_boot.h 11 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/resource_img.h 81 ●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/rk_meta.h 15 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/rockchip_smccc.h 23 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3528.h 12 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3562.h 12 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/uimage.h 3 ●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/arch-rockchip/vendor.h 3 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/include/asm/system.h 1 ●●●● patch | view | raw | blame | history
u-boot/arch/arm/lib/bootm-fdt.c 3 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/lib/bootm.c 9 ●●●● patch | view | raw | blame | history
u-boot/arch/arm/lib/crt0_64.S 36 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/Kconfig 95 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/Makefile 5 ●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/board.c 202 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/boot_mode.c 4 ●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/boot_rkimg.c 27 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/chip_info.c 4 ●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/fit.c 68 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/fit_args.sh 4 ●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/fit_misc.c 34 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/fit_nodes.sh 73 ●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/hotkey.c 4 ●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/kernel_dtb.c 517 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/make_fit_uboot.sh 16 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/pstore.c 2 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/resource_hwid.c 9 ●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/resource_img.c 705 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/resource_logo.c 95 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c 3 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rk3528/Kconfig 17 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rk3528/Makefile 11 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rk3528/clk_rk3528.c 41 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rk3528/rk3528.c 494 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c 24 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rk3562/Kconfig 17 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rk3562/Makefile 11 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rk3562/clk_rk3562.c 41 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rk3562/rk3562.c 661 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rk3562/syscon_rk3562.c 26 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rk3568/rk3568.c 17 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c 89 ●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rk_meta.c 25 ●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rockchip_smccc.c 17 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rv1106/rv1106.c 69 ●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/rv1126/rv1126.c 38 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/spl.c 12 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/spl_pcie_ep_boot.c 689 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/uimage.c 67 ●●●●● patch | view | raw | blame | history
u-boot/arch/arm/mach-rockchip/vendor.c 32 ●●●●● patch | view | raw | blame | history
u-boot/board/rockchip/evb_rk3528/Kconfig 15 ●●●●● patch | view | raw | blame | history
u-boot/board/rockchip/evb_rk3528/Makefile 7 ●●●●● patch | view | raw | blame | history
u-boot/board/rockchip/evb_rk3528/evb_rk3528.c 33 ●●●●● patch | view | raw | blame | history
u-boot/board/rockchip/evb_rk3562/Kconfig 15 ●●●●● patch | view | raw | blame | history
u-boot/board/rockchip/evb_rk3562/Makefile 7 ●●●●● patch | view | raw | blame | history
u-boot/board/rockchip/evb_rk3562/evb_rk3562.c 33 ●●●●● patch | view | raw | blame | history
u-boot/cmd/Kconfig 17 ●●●● patch | view | raw | blame | history
u-boot/cmd/Makefile 4 ●●●● patch | view | raw | blame | history
u-boot/cmd/boot_android.c 4 ●●●● patch | view | raw | blame | history
u-boot/cmd/bootfit.c 1 ●●●● patch | view | raw | blame | history
u-boot/cmd/cache.c 28 ●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/Kconfig 32 ●●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/Makefile 25 ●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/ddr_dq_eye/Makefile 7 ●●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/ddr_dq_eye/ddr_dq_eye.c patch | view | raw | blame | history
u-boot/cmd/ddr_tool/ddr_test/Makefile 20 ●●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/ddr_test/ddr_test_px30.S 4 ●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/ddr_test/ddr_test_rk1808.S 4 ●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/ddr_test/ddr_test_rk3328.S 4 ●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/ddr_test_rk3328.S 9940 ●●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/ddr_tool_common.c 9 ●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/ddr_tool_common.h 6 ●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/ddr_tool_mp.S 171 ●●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/io_map.c patch | view | raw | blame | history
u-boot/cmd/ddr_tool/io_map.h 6 ●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/memtester/Makefile 8 ●●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/memtester/memtester.c 4 ●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/memtester/memtester.h 6 ●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/memtester/sizes.h 6 ●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/memtester/tests.c 2 ●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/memtester/tests.h 5 ●●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/memtester/types.h patch | view | raw | blame | history
u-boot/cmd/ddr_tool/stressapptest/Makefile 7 ●●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/stressapptest/stressapptest.c 1207 ●●●●● patch | view | raw | blame | history
u-boot/cmd/ddr_tool/stressapptest/stressapptest.h 70 ●●●●● patch | view | raw | blame | history
u-boot/cmd/memtester/Makefile 4 ●●●● patch | view | raw | blame | history
u-boot/cmd/mmc.c 4 ●●● patch | view | raw | blame | history
u-boot/cmd/mtd.c 24 ●●●● patch | view | raw | blame | history
u-boot/cmd/pci.c 285 ●●●● patch | view | raw | blame | history
u-boot/cmd/script_update.c 38 ●●●● patch | view | raw | blame | history
u-boot/cmd/ufs.c 37 ●●●●● patch | view | raw | blame | history
u-boot/common/Kconfig 12 ●●●●● patch | view | raw | blame | history
u-boot/common/Makefile 10 ●●●●● patch | view | raw | blame | history
u-boot/common/android_ab.c 56 ●●●●● patch | view | raw | blame | history
u-boot/common/android_bootloader.c 415 ●●●● patch | view | raw | blame | history
u-boot/common/board_f.c 4 ●●●● patch | view | raw | blame | history
u-boot/common/board_info.c 1 ●●●● patch | view | raw | blame | history
u-boot/common/board_r.c 18 ●●●●● patch | view | raw | blame | history
u-boot/common/bootm.c 2 ●●● patch | view | raw | blame | history
u-boot/common/fb_mmc.c 18 ●●●●● patch | view | raw | blame | history
u-boot/common/image-android.c 306 ●●●● patch | view | raw | blame | history
u-boot/common/image-fdt.c 80 ●●●●● patch | view | raw | blame | history
u-boot/common/image-fit.c 1 ●●●● patch | view | raw | blame | history
u-boot/common/image-sparse.c 17 ●●●● patch | view | raw | blame | history
u-boot/common/mp_boot_rk3528.S 9682 ●●●●● patch | view | raw | blame | history
u-boot/common/spl/Kconfig 24 ●●●●● patch | view | raw | blame | history
u-boot/common/spl/Makefile 3 ●●●● patch | view | raw | blame | history
u-boot/common/spl/spl.c 14 ●●●● patch | view | raw | blame | history
u-boot/common/spl/spl_ab.c 35 ●●●●● patch | view | raw | blame | history
u-boot/common/spl/spl_boot_image.c 305 ●●●●● patch | view | raw | blame | history
u-boot/common/spl/spl_fit.c 20 ●●●● patch | view | raw | blame | history
u-boot/common/spl_mp_boot_rk3528.S 9214 ●●●●● patch | view | raw | blame | history
u-boot/configs/px30-tb_defconfig 2 ●●● patch | view | raw | blame | history
u-boot/configs/px30_defconfig 1 ●●●● patch | view | raw | blame | history
u-boot/configs/rk-amp.config 3 ●●●●● patch | view | raw | blame | history
u-boot/configs/rk3036_defconfig 2 ●●●●● patch | view | raw | blame | history
u-boot/configs/rk3126_defconfig 1 ●●●● patch | view | raw | blame | history
u-boot/configs/rk3128_defconfig 5 ●●●● patch | view | raw | blame | history
u-boot/configs/rk3128x_defconfig 2 ●●● patch | view | raw | blame | history
u-boot/configs/rk312x-rkflash.config 6 ●●●●● patch | view | raw | blame | history
u-boot/configs/rk322x_defconfig 2 ●●● patch | view | raw | blame | history
u-boot/configs/rk3308-amp.config 3 ●●●●● patch | view | raw | blame | history
u-boot/configs/rk3326_defconfig 4 ●●●● patch | view | raw | blame | history
u-boot/configs/rk3328_defconfig 2 ●●● patch | view | raw | blame | history
u-boot/configs/rk3399_defconfig 3 ●●●● patch | view | raw | blame | history
u-boot/configs/rk3528-aarch32.config 24 ●●●●● patch | view | raw | blame | history
u-boot/configs/rk3528_defconfig 201 ●●●●● patch | view | raw | blame | history
u-boot/configs/rk3562_defconfig 211 ●●●●● patch | view | raw | blame | history
u-boot/configs/rk3568-rt.config 2 ●●●●● patch | view | raw | blame | history
u-boot/configs/rk3568-spl-spi-nand_defconfig 11 ●●●●● patch | view | raw | blame | history
u-boot/configs/rk3568_defconfig 2 ●●●●● patch | view | raw | blame | history
u-boot/configs/rk3588-ab.config 3 ●●●●● patch | view | raw | blame | history
u-boot/configs/rk3588-qnx_defconfig 212 ●●●●● patch | view | raw | blame | history
u-boot/configs/rk3588_defconfig 9 ●●●●● patch | view | raw | blame | history
u-boot/configs/rv1106-display.config 2 ●●● patch | view | raw | blame | history
u-boot/configs/rv1106-emmc-tb_defconfig 11 ●●●● patch | view | raw | blame | history
u-boot/configs/rv1106-optee.config 5 ●●●●● patch | view | raw | blame | history
u-boot/configs/rv1106-spi-nor-tb_defconfig 11 ●●●● patch | view | raw | blame | history
u-boot/configs/rv1106-spi-nor_defconfig 10 ●●●●● patch | view | raw | blame | history
u-boot/configs/rv1106-usb.config 17 ●●●●● patch | view | raw | blame | history
u-boot/configs/rv1106_defconfig 3 ●●●● patch | view | raw | blame | history
u-boot/configs/rv1126-bat-spi-nor-tb.config 2 ●●● patch | view | raw | blame | history
u-boot/configs/rv1126-ipc.config 2 ●●●●● patch | view | raw | blame | history
u-boot/configs/rv1126-spi-nor-tiny_defconfig 1 ●●●● patch | view | raw | blame | history
u-boot/disk/Kconfig 8 ●●●● patch | view | raw | blame | history
u-boot/disk/part.c 25 ●●●● patch | view | raw | blame | history
u-boot/disk/part_efi.c 5 ●●●●● patch | view | raw | blame | history
u-boot/disk/part_env.c 9 ●●●● patch | view | raw | blame | history
u-boot/drivers/Kconfig 2 ●●●●● patch | view | raw | blame | history
u-boot/drivers/Makefile 3 ●●●● patch | view | raw | blame | history
u-boot/drivers/adc/rockchip-saradc-v2.c 33 ●●●●● patch | view | raw | blame | history
u-boot/drivers/clk/clk-uclass.c 3 ●●●● patch | view | raw | blame | history
u-boot/drivers/clk/rockchip/Makefile 2 ●●●●● patch | view | raw | blame | history
u-boot/drivers/clk/rockchip/clk_pll.c 23 ●●●● patch | view | raw | blame | history
u-boot/drivers/clk/rockchip/clk_rk3399.c 4 ●●●● patch | view | raw | blame | history
u-boot/drivers/clk/rockchip/clk_rk3528.c 2145 ●●●●● patch | view | raw | blame | history
u-boot/drivers/clk/rockchip/clk_rk3562.c 2046 ●●●●● patch | view | raw | blame | history
u-boot/drivers/clk/rockchip/clk_rk3568.c 14 ●●●● patch | view | raw | blame | history
u-boot/drivers/clk/rockchip/clk_rk3588.c 34 ●●●● patch | view | raw | blame | history
u-boot/drivers/core/device.c 2 ●●●●● patch | view | raw | blame | history
u-boot/drivers/core/fdtaddr.c 10 ●●●●● patch | view | raw | blame | history
u-boot/drivers/core/read.c 11 ●●●●● patch | view | raw | blame | history
u-boot/drivers/core/root.c 13 ●●●● patch | view | raw | blame | history
u-boot/drivers/cpu/amp.its 24 ●●●● patch | view | raw | blame | history
u-boot/drivers/cpu/rockchip_amp.c 52 ●●●● patch | view | raw | blame | history
u-boot/drivers/crypto/rockchip/crypto_v2.c 226 ●●●● patch | view | raw | blame | history
u-boot/drivers/gpio/Kconfig 15 ●●●●● patch | view | raw | blame | history
u-boot/drivers/gpio/Makefile 1 ●●●● patch | view | raw | blame | history
u-boot/drivers/gpio/gpio-max96752f.c 90 ●●●●● patch | view | raw | blame | history
u-boot/drivers/gpio/gpio-uclass.c 2 ●●●●● patch | view | raw | blame | history
u-boot/drivers/gpio/rk_gpio.c 11 ●●●●● patch | view | raw | blame | history
u-boot/drivers/i2c/muxes/Kconfig 7 ●●●●● patch | view | raw | blame | history
u-boot/drivers/i2c/muxes/Makefile 1 ●●●● patch | view | raw | blame | history
u-boot/drivers/i2c/muxes/max96745.c 44 ●●●● patch | view | raw | blame | history
u-boot/drivers/i2c/muxes/max96752f.c 100 ●●●●● patch | view | raw | blame | history
u-boot/drivers/input/adc_key.c 62 ●●●●● patch | view | raw | blame | history
u-boot/drivers/input/key-uclass.c 83 ●●●● patch | view | raw | blame | history
u-boot/drivers/input/rk_key.c 8 ●●●● patch | view | raw | blame | history
u-boot/drivers/input/spl_adc_key.c 141 ●●●● patch | view | raw | blame | history
u-boot/drivers/misc/Makefile 8 ●●●●● patch | view | raw | blame | history
u-boot/drivers/misc/rk3528-secure-otp.S 15901 ●●●●● patch | view | raw | blame | history
u-boot/drivers/misc/rk3562-secure-otp.S 15906 ●●●●● patch | view | raw | blame | history
u-boot/drivers/misc/rockchip-otp.c 10 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mmc/dw_mmc.c 78 ●●●● patch | view | raw | blame | history
u-boot/drivers/mmc/mmc-uclass.c 14 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mmc/mmc.c 77 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mmc/rockchip_dw_mmc.c 2 ●●● patch | view | raw | blame | history
u-boot/drivers/mmc/rockchip_sdhci.c 212 ●●●● patch | view | raw | blame | history
u-boot/drivers/mmc/sdhci.c 53 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/mtd_blk.c 16 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/nand/spi/Kconfig 12 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/nand/spi/Makefile 2 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/nand/spi/core.c 14 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/nand/spi/dosilicon.c 22 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/nand/spi/fmsh.c 40 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/nand/spi/foresee.c 20 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/nand/spi/gigadevice.c 202 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/nand/spi/gsto.c 92 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/nand/spi/hyf.c 22 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/nand/spi/jsc.c 9 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/nand/spi/skyhigh.c 51 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/nand/spi/unim.c 9 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/nand/spi/xincun.c 108 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/spi/sf_internal.h 1 ●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/spi/spi-nor-ids.c 186 ●●●●● patch | view | raw | blame | history
u-boot/drivers/mtd/ubi/debug.h 9 ●●●● patch | view | raw | blame | history
u-boot/drivers/net/gmac_rockchip.c 494 ●●●●● patch | view | raw | blame | history
u-boot/drivers/net/phy/rk630phy.c 3 ●●●●● patch | view | raw | blame | history
u-boot/drivers/nvme/nvme.c 27 ●●●● patch | view | raw | blame | history
u-boot/drivers/pci/pcie_dw_rockchip.c 63 ●●●● patch | view | raw | blame | history
u-boot/drivers/phy/Makefile 2 ●●●●● patch | view | raw | blame | history
u-boot/drivers/phy/phy-rockchip-inno-usb2.c 364 ●●●●● patch | view | raw | blame | history
u-boot/drivers/phy/phy-rockchip-naneng-combphy.c 231 ●●●●● patch | view | raw | blame | history
u-boot/drivers/phy/phy-rockchip-samsung-hdptx.c 23 ●●●● patch | view | raw | blame | history
u-boot/drivers/phy/phy-rockchip-usbdp.c 26 ●●●● patch | view | raw | blame | history
u-boot/drivers/pinctrl/Kconfig 8 ●●●●● patch | view | raw | blame | history
u-boot/drivers/pinctrl/Makefile 1 ●●●● patch | view | raw | blame | history
u-boot/drivers/pinctrl/pinctrl-max96752f.c 491 ●●●●● patch | view | raw | blame | history
u-boot/drivers/pinctrl/rockchip/Makefile 2 ●●●●● patch | view | raw | blame | history
u-boot/drivers/pinctrl/rockchip/pinctrl-rk3528.c 313 ●●●●● patch | view | raw | blame | history
u-boot/drivers/pinctrl/rockchip/pinctrl-rk3562.c 324 ●●●●● patch | view | raw | blame | history
u-boot/drivers/power/charge_animation.c 6 ●●●●● patch | view | raw | blame | history
u-boot/drivers/power/pmic/rk8xx.c 73 ●●●● patch | view | raw | blame | history
u-boot/drivers/power/regulator/fixed.c 10 ●●●●● patch | view | raw | blame | history
u-boot/drivers/power/regulator/regulator-uclass.c 92 ●●●●● patch | view | raw | blame | history
u-boot/drivers/ram/rockchip/Makefile 2 ●●●●● patch | view | raw | blame | history
u-boot/drivers/ram/rockchip/sdram_rk3528.c 21 ●●●●● patch | view | raw | blame | history
u-boot/drivers/ram/rockchip/sdram_rk3562.c 31 ●●●●● patch | view | raw | blame | history
u-boot/drivers/ram/rockchip/sdram_rv1126.c 38 ●●●● patch | view | raw | blame | history
u-boot/drivers/rkflash/sfc_nand.c 30 ●●●●● patch | view | raw | blame | history
u-boot/drivers/rkflash/sfc_nor.c 23 ●●●●● patch | view | raw | blame | history
u-boot/drivers/rng/rockchip_rng.c 143 ●●●● patch | view | raw | blame | history
u-boot/drivers/scsi/scsi.c 4 ●●●● patch | view | raw | blame | history
u-boot/drivers/spi/rockchip_sfc.c 2 ●●●●● patch | view | raw | blame | history
u-boot/drivers/spi/soft_spi.c 34 ●●●●● patch | view | raw | blame | history
u-boot/drivers/thermal/rockchip_thermal.c 283 ●●●●● patch | view | raw | blame | history
u-boot/drivers/ufs/Kconfig 24 ●●●●● patch | view | raw | blame | history
u-boot/drivers/ufs/Makefile 8 ●●●●● patch | view | raw | blame | history
u-boot/drivers/ufs/cdns-platform.c 125 ●●●●● patch | view | raw | blame | history
u-boot/drivers/ufs/ti-j721e-ufs.c 74 ●●●●● patch | view | raw | blame | history
u-boot/drivers/ufs/ufs-uclass.c 18 ●●●●● patch | view | raw | blame | history
u-boot/drivers/ufs/ufs.c 1970 ●●●●● patch | view | raw | blame | history
u-boot/drivers/ufs/ufs.h 917 ●●●●● patch | view | raw | blame | history
u-boot/drivers/ufs/ufshcd-dwc.c 149 ●●●●● patch | view | raw | blame | history
u-boot/drivers/ufs/ufshcd-dwc.h 23 ●●●●● patch | view | raw | blame | history
u-boot/drivers/ufs/ufshci-dwc.h 33 ●●●●● patch | view | raw | blame | history
u-boot/drivers/ufs/unipro.h 270 ●●●●● patch | view | raw | blame | history
u-boot/drivers/usb/dwc3/gadget.c 2 ●●● patch | view | raw | blame | history
u-boot/drivers/usb/dwc3/io.h 5 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/Kconfig 21 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/Makefile 6 ●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/Kconfig 28 ●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/Makefile 15 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/analogix_dp.c 52 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/drm_modes.c 52 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/dw-dp.c 54 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/dw_hdmi.c 186 ●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/dw_hdmi.h 4 ●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/dw_hdmi_qp.c 66 ●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/dw_mipi_dsi.c 19 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/dw_mipi_dsi2.c 248 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/max96745.c 105 ●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/max96752f.c 79 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/max96755f.c 47 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/panel-maxim-deserializer.c 300 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/panel-maxim-max96752f.c 303 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/panel-rohm-bu18rl82.c 349 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/phy-rockchip-samsung-hdptx-hdmi.c 81 ●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip-inno-hdmi-phy.c 426 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_connector.c 45 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_connector.h 124 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_crtc.c 40 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_crtc.h 6 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_display.c 661 ●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_display.h 50 ●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_display_helper.c 279 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_drm_tve.c 578 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_drm_tve.h 153 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_dw_hdmi.c 127 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_dw_hdmi_qp.c 25 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_lvds.c 26 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_panel.c 120 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_post_csc.c 1587 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_post_csc.h 35 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_rgb.c 362 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_spl_display.c 265 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_tve.c 848 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_tve.h 253 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_vop.c 31 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_vop.h 5 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_vop2.c 2254 ●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rockchip_vop_reg.c 22 ●●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rohm-bu18rl82.c 1 ●●●● patch | view | raw | blame | history
u-boot/drivers/video/drm/rohm-bu18tl82.c 17 ●●●●● patch | view | raw | blame | history
u-boot/drivers/watchdog/rockchip_wdt.c 11 ●●●●● patch | view | raw | blame | history
u-boot/env/envf.c 51 ●●●●● patch | view | raw | blame | history
u-boot/examples/standalone/Makefile 1 ●●●● patch | view | raw | blame | history
u-boot/examples/standalone/README_rkspi.md 126 ●●●●● patch | view | raw | blame | history
u-boot/examples/standalone/rkspi.c 454 ●●●●● patch | view | raw | blame | history
u-boot/examples/standalone/rkspi.h 138 ●●●●● patch | view | raw | blame | history
u-boot/fs/ubifs/debug.h 24 ●●●● patch | view | raw | blame | history
u-boot/fs/ubifs/io.c 8 ●●●● patch | view | raw | blame | history
u-boot/fs/ubifs/super.c 21 ●●●●● patch | view | raw | blame | history
u-boot/fs/ubifs/tnc.c 25 ●●●●● patch | view | raw | blame | history
u-boot/fs/ubifs/ubifs.c 18 ●●●● patch | view | raw | blame | history
u-boot/fs/ubifs/ubifs.h 8 ●●●● patch | view | raw | blame | history
u-boot/include/android_ab.h 2 ●●● patch | view | raw | blame | history
u-boot/include/android_avb/avb_ops_user.h 16 ●●●●● patch | view | raw | blame | history
u-boot/include/android_image.h 6 ●●●● patch | view | raw | blame | history
u-boot/include/asm-generic/atomic-long.h 2 ●●●●● patch | view | raw | blame | history
u-boot/include/asm-generic/u-boot.h 2 ●●●●● patch | view | raw | blame | history
u-boot/include/boot_rkimg.h 1 ●●●● patch | view | raw | blame | history
u-boot/include/charset.h 3 ●●●●● patch | view | raw | blame | history
u-boot/include/configs/evb_rk3528.h 26 ●●●●● patch | view | raw | blame | history
u-boot/include/configs/evb_rk3562.h 26 ●●●●● patch | view | raw | blame | history
u-boot/include/configs/rk3288_common.h 2 ●●● patch | view | raw | blame | history
u-boot/include/configs/rk3528_common.h 109 ●●●●● patch | view | raw | blame | history
u-boot/include/configs/rk3562_common.h 84 ●●●●● patch | view | raw | blame | history
u-boot/include/configs/rk3588_common.h 8 ●●●● patch | view | raw | blame | history
u-boot/include/configs/rockchip-common.h 2 ●●● patch | view | raw | blame | history
u-boot/include/configs/rv1106_common.h 1 ●●●● patch | view | raw | blame | history
u-boot/include/configs/rv1126_common.h 2 ●●● patch | view | raw | blame | history
u-boot/include/configs/woodburn_common.h 4 ●●●● patch | view | raw | blame | history
u-boot/include/dm/fdtaddr.h 12 ●●●●● patch | view | raw | blame | history
u-boot/include/dm/read.h 17 ●●●●● patch | view | raw | blame | history
u-boot/include/dm/uclass-id.h 1 ●●●● patch | view | raw | blame | history
u-boot/include/drm_modes.h 94 ●●●●● patch | view | raw | blame | history
u-boot/include/dt-bindings/clock/rk3528-cru.h 754 ●●●●● patch | view | raw | blame | history
u-boot/include/dt-bindings/clock/rk3562-cru.h 733 ●●●●● patch | view | raw | blame | history
u-boot/include/dt-bindings/display/rockchip-tve.h 15 ●●●●● patch | view | raw | blame | history
u-boot/include/dt-bindings/power/rk3528-power.h 18 ●●●●● patch | view | raw | blame | history
u-boot/include/dt-bindings/power/rk3562-power.h 33 ●●●●● patch | view | raw | blame | history
u-boot/include/dt-bindings/soc/rockchip,boot-mode.h 2 ●●●●● patch | view | raw | blame | history
u-boot/include/dt-bindings/suspend/rockchip-rk3528.h 54 ●●●●● patch | view | raw | blame | history
u-boot/include/edid.h 41 ●●●●● patch | view | raw | blame | history
u-boot/include/image.h 14 ●●●●● patch | view | raw | blame | history
u-boot/include/irq-platform.h 40 ●●●●● patch | view | raw | blame | history
u-boot/include/key.h 7 ●●●●● patch | view | raw | blame | history
u-boot/include/linux/dw_hdmi.h 3 ●●●● patch | view | raw | blame | history
u-boot/include/linux/mtd/mtd.h 24 ●●●●● patch | view | raw | blame | history
u-boot/include/linux/mtd/spinand.h 2 ●●●●● patch | view | raw | blame | history
u-boot/include/max96745.h 15 ●●●●● patch | view | raw | blame | history
u-boot/include/max96752f.h 66 ●●●●● patch | view | raw | blame | history
u-boot/include/max96755f.h 1 ●●●● patch | view | raw | blame | history
u-boot/include/mmc.h 10 ●●●●● patch | view | raw | blame | history
u-boot/include/mp_boot.h 25 ●●●●● patch | view | raw | blame | history
u-boot/include/power/rk8xx_pmic.h 2 ●●●●● patch | view | raw | blame | history
u-boot/include/rk_timer_irq.h 6 ●●●●● patch | view | raw | blame | history
u-boot/include/rockchip/crypto_v2.h 2 ●●● patch | view | raw | blame | history
u-boot/include/scsi.h 4 ●●●● patch | view | raw | blame | history
u-boot/include/sdhci.h 13 ●●●●● patch | view | raw | blame | history
u-boot/include/spl_ab.h 10 ●●●●● patch | view | raw | blame | history
u-boot/include/spl_display.h 28 ●●●●● patch | view | raw | blame | history
u-boot/include/u-boot/sha1.h 2 ●●● patch | view | raw | blame | history
u-boot/lib/avb/libavb/avb_sha512.c 59 ●●●● patch | view | raw | blame | history
u-boot/lib/avb/libavb/avb_slot_verify.c 15 ●●●● patch | view | raw | blame | history
u-boot/lib/avb/libavb_user/Kconfig 1 ●●●● patch | view | raw | blame | history
u-boot/lib/avb/libavb_user/avb_ops_user.c 147 ●●●● patch | view | raw | blame | history
u-boot/lib/avb/rk_avb_user/rk_avb_ops_user.c 12 ●●●●● patch | view | raw | blame | history
u-boot/lib/optee_clientApi/OpteeClientInterface.c 16 ●●●●● patch | view | raw | blame | history
u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v1.c 13 ●●●●● patch | view | raw | blame | history
u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v2.c 4 ●●● patch | view | raw | blame | history
u-boot/lib/rsa/rsa-sign.c 21 ●●●● patch | view | raw | blame | history
u-boot/lib/rsa/rsa-verify.c 16 ●●●●● patch | view | raw | blame | history
u-boot/lib/sha1.c 33 ●●●● patch | view | raw | blame | history
u-boot/lib/sha256.c 31 ●●●● patch | view | raw | blame | history
u-boot/make.sh 8 ●●●● patch | view | raw | blame | history
u-boot/scripts/README.rockchip 2 ●●● patch | view | raw | blame | history
u-boot/scripts/android2fit.sh 4 ●●●● patch | view | raw | blame | history
u-boot/scripts/check-rkconfig.sh 23 ●●●●● patch | view | raw | blame | history
u-boot/scripts/fit-core.sh 39 ●●●● patch | view | raw | blame | history
u-boot/scripts/setlocalversion 7 ●●●● patch | view | raw | blame | history
u-boot/tools/Makefile 6 ●●●●● patch | view | raw | blame | history
u-boot/tools/rkcommon.c 2 ●●●●● patch | view | raw | blame | history
u-boot/usb_update.txt 4 ●●●● patch | view | raw | blame | history
u-boot/Kconfig
....@@ -203,6 +203,18 @@
203203 SHA256 variant is supported: SHA512 and others are not currently
204204 supported in U-Boot.
205205
206
+config FIT_ENABLE_RSA4096_SUPPORT
207
+ bool "Support RSA4096 verification of FIT image contents"
208
+ select RSA_SOFTWARE_EXP if !DM_CRYPTO
209
+ default n
210
+ help
211
+ Enable this to support RSA4096 checksum of FIT image contents. A
212
+ RSA4096 is a 4096-bit (512-byte) key used to check that
213
+ check if the content comes from an encryption party. RSA4096 is one
214
+ of algorithms recommended for use in secure applications since (as at 2016)
215
+ there is no known feasible attack that could produce a 'collision' with differing
216
+ input data. Use this for the higher security than RSA2048 in default.
217
+
206218 config FIT_SIGNATURE
207219 bool "Enable signature verification of FIT uImages"
208220 depends on DM
....@@ -278,6 +290,9 @@
278290 Say y here if you want to enable fit image structure and data
279291 print.
280292
293
+config FIT_OMIT_UBOOT
294
+ bool "Omit u-boot-nodtb.bin and u-boot.dtb when output uboot.itb"
295
+
281296 if SPL
282297
283298 config SPL_FIT
u-boot/arch/arm/Kconfig
....@@ -343,6 +343,10 @@
343343 help
344344 This ARM64 system supports AArch32 execution state.
345345
346
+config ARM_SMP
347
+ bool "Enable ARM Symmetric Multiprocessing"
348
+ default n
349
+
346350 choice
347351 prompt "Target select"
348352 default TARGET_HIKEY
u-boot/arch/arm/cpu/armv7/start.S
....@@ -164,7 +164,9 @@
164164 mrc p15, 0, r0, c1, c0, 0
165165 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
166166 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
167
+#if 0 /* There is unalign access when decompress firmware. */
167168 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
169
+#endif
168170 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
169171 #ifdef CONFIG_SYS_ICACHE_OFF
170172 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
u-boot/arch/arm/cpu/armv8/Kconfig
....@@ -143,4 +143,19 @@
143143
144144 endif
145145
146
+menuconfig ARMV8_CRYPTO
147
+ bool "ARM64 Accelerated Cryptographic Algorithms"
148
+
149
+if ARMV8_CRYPTO
150
+
151
+config ARMV8_CE_SHA1
152
+ bool "SHA-1 digest algorithm (ARMv8 Crypto Extensions)"
153
+ default y if SHA1
154
+
155
+config ARMV8_CE_SHA256
156
+ bool "SHA-256 digest algorithm (ARMv8 Crypto Extensions)"
157
+ default y if SHA256
158
+
159
+endif
160
+
146161 endif
u-boot/arch/arm/cpu/armv8/Makefile
....@@ -36,3 +36,5 @@
3636 obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
3737 obj-$(CONFIG_ARMV8_PSCI) += psci.o
3838 obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
39
+obj-$(CONFIG_ARMV8_CE_SHA1) += sha1_ce_glue.o sha1_ce_core.o
40
+obj-$(CONFIG_ARMV8_CE_SHA256) += sha256_ce_glue.o sha256_ce_core.o
u-boot/arch/arm/cpu/armv8/sha1_ce_core.S
....@@ -0,0 +1,132 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
2
+/*
3
+ * sha1_ce_core.S - SHA-1 secure hash using ARMv8 Crypto Extensions
4
+ *
5
+ * Copyright (C) 2014 Linaro Ltd <ard.biesheuvel@linaro.org>
6
+ * Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org>
7
+ */
8
+
9
+#include <config.h>
10
+#include <linux/linkage.h>
11
+#include <asm/system.h>
12
+#include <asm/macro.h>
13
+
14
+ .text
15
+ .arch armv8-a+crypto
16
+
17
+ k0 .req v0
18
+ k1 .req v1
19
+ k2 .req v2
20
+ k3 .req v3
21
+
22
+ t0 .req v4
23
+ t1 .req v5
24
+
25
+ dga .req q6
26
+ dgav .req v6
27
+ dgb .req s7
28
+ dgbv .req v7
29
+
30
+ dg0q .req q12
31
+ dg0s .req s12
32
+ dg0v .req v12
33
+ dg1s .req s13
34
+ dg1v .req v13
35
+ dg2s .req s14
36
+
37
+ .macro add_only, op, ev, rc, s0, dg1
38
+ .ifc \ev, ev
39
+ add t1.4s, v\s0\().4s, \rc\().4s
40
+ sha1h dg2s, dg0s
41
+ .ifnb \dg1
42
+ sha1\op dg0q, \dg1, t0.4s
43
+ .else
44
+ sha1\op dg0q, dg1s, t0.4s
45
+ .endif
46
+ .else
47
+ .ifnb \s0
48
+ add t0.4s, v\s0\().4s, \rc\().4s
49
+ .endif
50
+ sha1h dg1s, dg0s
51
+ sha1\op dg0q, dg2s, t1.4s
52
+ .endif
53
+ .endm
54
+
55
+ .macro add_update, op, ev, rc, s0, s1, s2, s3, dg1
56
+ sha1su0 v\s0\().4s, v\s1\().4s, v\s2\().4s
57
+ add_only \op, \ev, \rc, \s1, \dg1
58
+ sha1su1 v\s0\().4s, v\s3\().4s
59
+ .endm
60
+
61
+ .macro loadrc, k, val, tmp
62
+ movz \tmp, :abs_g0_nc:\val
63
+ movk \tmp, :abs_g1:\val
64
+ dup \k, \tmp
65
+ .endm
66
+
67
+ /*
68
+ * void sha1_armv8_ce_process(uint32_t state[5], uint8_t const *src,
69
+ * uint32_t blocks)
70
+ */
71
+ENTRY(sha1_armv8_ce_process)
72
+ /* load round constants */
73
+ loadrc k0.4s, 0x5a827999, w6
74
+ loadrc k1.4s, 0x6ed9eba1, w6
75
+ loadrc k2.4s, 0x8f1bbcdc, w6
76
+ loadrc k3.4s, 0xca62c1d6, w6
77
+
78
+ /* load state (4+1 digest states) */
79
+ ld1 {dgav.4s}, [x0]
80
+ ldr dgb, [x0, #16]
81
+
82
+ /* load input (64 bytes into v8->v11 16B vectors) */
83
+0: ld1 {v8.4s-v11.4s}, [x1], #64
84
+ sub w2, w2, #1
85
+#if __BYTE_ORDER == __LITTLE_ENDIAN
86
+ rev32 v8.16b, v8.16b
87
+ rev32 v9.16b, v9.16b
88
+ rev32 v10.16b, v10.16b
89
+ rev32 v11.16b, v11.16b
90
+#endif
91
+
92
+1: add t0.4s, v8.4s, k0.4s
93
+ mov dg0v.16b, dgav.16b
94
+
95
+ add_update c, ev, k0, 8, 9, 10, 11, dgb
96
+ add_update c, od, k0, 9, 10, 11, 8
97
+ add_update c, ev, k0, 10, 11, 8, 9
98
+ add_update c, od, k0, 11, 8, 9, 10
99
+ add_update c, ev, k1, 8, 9, 10, 11
100
+
101
+ add_update p, od, k1, 9, 10, 11, 8
102
+ add_update p, ev, k1, 10, 11, 8, 9
103
+ add_update p, od, k1, 11, 8, 9, 10
104
+ add_update p, ev, k1, 8, 9, 10, 11
105
+ add_update p, od, k2, 9, 10, 11, 8
106
+
107
+ add_update m, ev, k2, 10, 11, 8, 9
108
+ add_update m, od, k2, 11, 8, 9, 10
109
+ add_update m, ev, k2, 8, 9, 10, 11
110
+ add_update m, od, k2, 9, 10, 11, 8
111
+ add_update m, ev, k3, 10, 11, 8, 9
112
+
113
+ add_update p, od, k3, 11, 8, 9, 10
114
+ add_only p, ev, k3, 9
115
+ add_only p, od, k3, 10
116
+ add_only p, ev, k3, 11
117
+ add_only p, od
118
+
119
+ /* update state */
120
+ add dgbv.2s, dgbv.2s, dg1v.2s
121
+ add dgav.4s, dgav.4s, dg0v.4s
122
+
123
+ /* loop on next block? */
124
+ cbz w2, 2f
125
+ b 0b
126
+
127
+ /* store new state */
128
+2: st1 {dgav.4s}, [x0]
129
+ str dgb, [x0, #16]
130
+ mov w0, w2
131
+ ret
132
+ENDPROC(sha1_armv8_ce_process)
u-boot/arch/arm/cpu/armv8/sha1_ce_glue.c
....@@ -0,0 +1,21 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
2
+/*
3
+ * sha1_ce_glue.c - SHA-1 secure hash using ARMv8 Crypto Extensions
4
+ *
5
+ * Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org>
6
+ */
7
+
8
+#include <common.h>
9
+#include <u-boot/sha1.h>
10
+
11
+extern void sha1_armv8_ce_process(uint32_t state[5], uint8_t const *src,
12
+ uint32_t blocks);
13
+
14
+void sha1_process(sha1_context *ctx, const unsigned char *data,
15
+ unsigned int blocks)
16
+{
17
+ if (!blocks)
18
+ return;
19
+
20
+ sha1_armv8_ce_process(ctx->state, data, blocks);
21
+}
u-boot/arch/arm/cpu/armv8/sha256_ce_core.S
....@@ -0,0 +1,134 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
2
+/*
3
+ * sha256-ce-core.S - core SHA-256 transform using v8 Crypto Extensions
4
+ *
5
+ * Copyright (C) 2014 Linaro Ltd <ard.biesheuvel@linaro.org>
6
+ * Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org>
7
+ */
8
+
9
+ #include <config.h>
10
+ #include <linux/linkage.h>
11
+ #include <asm/system.h>
12
+ #include <asm/macro.h>
13
+
14
+ .text
15
+ .arch armv8-a+crypto
16
+
17
+ dga .req q20
18
+ dgav .req v20
19
+ dgb .req q21
20
+ dgbv .req v21
21
+
22
+ t0 .req v22
23
+ t1 .req v23
24
+
25
+ dg0q .req q24
26
+ dg0v .req v24
27
+ dg1q .req q25
28
+ dg1v .req v25
29
+ dg2q .req q26
30
+ dg2v .req v26
31
+
32
+ .macro add_only, ev, rc, s0
33
+ mov dg2v.16b, dg0v.16b
34
+ .ifeq \ev
35
+ add t1.4s, v\s0\().4s, \rc\().4s
36
+ sha256h dg0q, dg1q, t0.4s
37
+ sha256h2 dg1q, dg2q, t0.4s
38
+ .else
39
+ .ifnb \s0
40
+ add t0.4s, v\s0\().4s, \rc\().4s
41
+ .endif
42
+ sha256h dg0q, dg1q, t1.4s
43
+ sha256h2 dg1q, dg2q, t1.4s
44
+ .endif
45
+ .endm
46
+
47
+ .macro add_update, ev, rc, s0, s1, s2, s3
48
+ sha256su0 v\s0\().4s, v\s1\().4s
49
+ add_only \ev, \rc, \s1
50
+ sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s
51
+ .endm
52
+
53
+ /*
54
+ * The SHA-256 round constants
55
+ */
56
+ .align 4
57
+.Lsha2_rcon:
58
+ .word 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5
59
+ .word 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5
60
+ .word 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3
61
+ .word 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174
62
+ .word 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc
63
+ .word 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da
64
+ .word 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7
65
+ .word 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967
66
+ .word 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13
67
+ .word 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85
68
+ .word 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3
69
+ .word 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070
70
+ .word 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5
71
+ .word 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3
72
+ .word 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208
73
+ .word 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
74
+
75
+ /*
76
+ * void sha256_armv8_ce_process(struct sha256_ce_state *sst,
77
+ * uint8_t const *src, uint32_t blocks)
78
+ */
79
+ENTRY(sha256_armv8_ce_process)
80
+ /* load round constants */
81
+ adr x8, .Lsha2_rcon
82
+ ld1 { v0.4s- v3.4s}, [x8], #64
83
+ ld1 { v4.4s- v7.4s}, [x8], #64
84
+ ld1 { v8.4s-v11.4s}, [x8], #64
85
+ ld1 {v12.4s-v15.4s}, [x8]
86
+
87
+ /* load state */
88
+ ldp dga, dgb, [x0]
89
+
90
+ /* load input */
91
+0: ld1 {v16.4s-v19.4s}, [x1], #64
92
+ sub w2, w2, #1
93
+#if __BYTE_ORDER == __LITTLE_ENDIAN
94
+ rev32 v16.16b, v16.16b
95
+ rev32 v17.16b, v17.16b
96
+ rev32 v18.16b, v18.16b
97
+ rev32 v19.16b, v19.16b
98
+#endif
99
+
100
+1: add t0.4s, v16.4s, v0.4s
101
+ mov dg0v.16b, dgav.16b
102
+ mov dg1v.16b, dgbv.16b
103
+
104
+ add_update 0, v1, 16, 17, 18, 19
105
+ add_update 1, v2, 17, 18, 19, 16
106
+ add_update 0, v3, 18, 19, 16, 17
107
+ add_update 1, v4, 19, 16, 17, 18
108
+
109
+ add_update 0, v5, 16, 17, 18, 19
110
+ add_update 1, v6, 17, 18, 19, 16
111
+ add_update 0, v7, 18, 19, 16, 17
112
+ add_update 1, v8, 19, 16, 17, 18
113
+
114
+ add_update 0, v9, 16, 17, 18, 19
115
+ add_update 1, v10, 17, 18, 19, 16
116
+ add_update 0, v11, 18, 19, 16, 17
117
+ add_update 1, v12, 19, 16, 17, 18
118
+
119
+ add_only 0, v13, 17
120
+ add_only 1, v14, 18
121
+ add_only 0, v15, 19
122
+ add_only 1
123
+
124
+ /* update state */
125
+ add dgav.4s, dgav.4s, dg0v.4s
126
+ add dgbv.4s, dgbv.4s, dg1v.4s
127
+
128
+ /* handled all input blocks? */
129
+ cbnz w2, 0b
130
+
131
+ /* store new state */
132
+3: stp dga, dgb, [x0]
133
+ ret
134
+ENDPROC(sha256_armv8_ce_process)
u-boot/arch/arm/cpu/armv8/sha256_ce_glue.c
....@@ -0,0 +1,21 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
2
+/*
3
+ * sha256_ce_glue.c - SHA-256 secure hash using ARMv8 Crypto Extensions
4
+ *
5
+ * Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org>
6
+ */
7
+
8
+#include <common.h>
9
+#include <u-boot/sha256.h>
10
+
11
+extern void sha256_armv8_ce_process(uint32_t state[8], uint8_t const *src,
12
+ uint32_t blocks);
13
+
14
+void sha256_process(sha256_context *ctx, const unsigned char *data,
15
+ unsigned int blocks)
16
+{
17
+ if (!blocks)
18
+ return;
19
+
20
+ sha256_armv8_ce_process(ctx->state, data, blocks);
21
+}
u-boot/arch/arm/cpu/armv8/start.S
....@@ -117,6 +117,43 @@
117117 0:
118118
119119 /*
120
+ * Enable instruction cache (if required), stack pointer,
121
+ * data access alignment checks and SError.
122
+ */
123
+#ifndef CONFIG_SYS_ICACHE_OFF
124
+ mov x1, #CR_I
125
+#else
126
+ mov x1, #0
127
+#endif
128
+ switch_el x2, 3f, 2f, 1f
129
+3: mrs x0, sctlr_el3
130
+ orr x0, x0, x1
131
+ msr sctlr_el3, x0
132
+#ifndef CONFIG_SUPPORT_USBPLUG
133
+ msr daifclr, #4 /* Enable SError. SCR_EL3.EA=1 was already set in start.S */
134
+#endif
135
+ b 0f
136
+2: mrs x0, sctlr_el2
137
+ orr x0, x0, x1
138
+ msr sctlr_el2, x0
139
+
140
+ mrs x0, hcr_el2
141
+ orr x0, x0, #HCR_EL2_TGE
142
+ orr x0, x0, #HCR_EL2_AMO
143
+#if CONFIG_IS_ENABLED(IRQ)
144
+ orr x0, x0, #HCR_EL2_IMO
145
+#endif
146
+ msr hcr_el2, x0
147
+ msr daifclr, #4
148
+ b 0f
149
+1: mrs x0, sctlr_el1
150
+ orr x0, x0, x1
151
+ msr sctlr_el1, x0
152
+ msr daifclr, #4
153
+0:
154
+ isb
155
+
156
+ /*
120157 * Enable SMPEN bit for coherency.
121158 * This register is not architectural but at the moment
122159 * this bit should be set for A53/A57/A72.
....@@ -160,6 +197,43 @@
160197 cbz x0, slave_cpu
161198 br x0 /* branch to the given address */
162199 #endif /* CONFIG_ARMV8_MULTIENTRY */
200
+
201
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARM_SMP)
202
+ mrs x0, mpidr_el1
203
+ and x0, x0, #0xfff
204
+ cmp x0, #0
205
+ beq master_cpu
206
+
207
+#ifdef SMP_CPU1
208
+ cmp x0, #(SMP_CPU1)
209
+ ldr x1, =(SMP_CPU1_STACK)
210
+ beq slave_cpu
211
+#endif
212
+
213
+#ifdef SMP_CPU2
214
+ cmp x0, #(SMP_CPU2)
215
+ ldr x1, =(SMP_CPU2_STACK)
216
+ beq slave_cpu
217
+#endif
218
+
219
+#ifdef SMP_CPU3
220
+ cmp x0, #(SMP_CPU3)
221
+ ldr x1, =(SMP_CPU3_STACK)
222
+ beq slave_cpu
223
+#endif
224
+ dsb sy
225
+ isb
226
+
227
+loop:
228
+ wfe
229
+ b loop
230
+
231
+slave_cpu:
232
+ bic sp, x1, #0xf
233
+ bl smp_entry
234
+ b loop
235
+#endif
236
+
163237 master_cpu:
164238 bl _main
165239
u-boot/arch/arm/dts/Makefile
....@@ -453,12 +453,14 @@
453453 dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
454454
455455 # Compile embeded kernel dts to dtb, and put it behind of u-boot.dtb
456
+ifeq ($(findstring arch/arm/dts/,$(EMBED_KERN_DTB_PATH)),arch/arm/dts/)
456457 EMBED_KERN_DTB_PATH := $(CONFIG_EMBED_KERNEL_DTB_PATH:"%"=%)
457458 EMBED_KERN_DTS_PATH := $(subst dtb,dts, $(EMBED_KERN_DTB_PATH))
458459 ifneq ($(wildcard $(EMBED_KERN_DTS_PATH)),)
459460 EMBED_KERN_DTB=$(shell echo $(EMBED_KERN_DTB_PATH) | awk -F '/' '{ print $$NF }')
460461 dtb-y += $(EMBED_KERN_DTB)
461462 endif
463
+endif
462464
463465 targets += $(dtb-y)
464466
u-boot/arch/arm/dts/px30-u-boot.dtsi
....@@ -14,6 +14,13 @@
1414 u-boot,spl-boot-order = &emmc, &sdmmc;
1515 stdout-path = &uart2;
1616 };
17
+
18
+ secure-otp@ff110000 {
19
+ compatible = "rockchip,px30-secure-otp";
20
+ reg = <0x0 0xff110000 0x0 0x4000>;
21
+ secure_conf = <0xff11C008>;
22
+ mask_addr = <0xff2d0000>;
23
+ };
1724 };
1825
1926 &psci {
u-boot/arch/arm/dts/px30.dtsi
....@@ -288,13 +288,6 @@
288288 status = "disabled";
289289 };
290290
291
- secure_otp: secure_otp@ff110000 {
292
- compatible = "rockchip,px30-secure-otp";
293
- reg = <0x0 0xff110000 0x0 0x4000>;
294
- secure_conf = <0xff11C008>;
295
- mask_addr = <0xff2d0000>;
296
- };
297
-
298291 gic: interrupt-controller@ff131000 {
299292 compatible = "arm,gic-400";
300293 #interrupt-cells = <3>;
u-boot/arch/arm/dts/rk3036-sdk-u-boot.dtsi
....@@ -37,3 +37,31 @@
3737 status = "okay";
3838 };
3939
40
+&pinctrl {
41
+ u-boot,dm-pre-reloc;
42
+ status = "okay";
43
+};
44
+
45
+&gpio0 {
46
+ u-boot,dm-pre-reloc;
47
+ status = "okay";
48
+};
49
+
50
+&gpio1 {
51
+ u-boot,dm-pre-reloc;
52
+ status = "okay";
53
+};
54
+
55
+&gpio2 {
56
+ u-boot,dm-pre-reloc;
57
+ status = "okay";
58
+};
59
+
60
+&usb2phy {
61
+ u-boot,dm-pre-reloc;
62
+ status = "okay";
63
+};
64
+
65
+&usb_otg {
66
+ u-boot,dm-pre-reloc;
67
+};
u-boot/arch/arm/dts/rk3036-sdk.dts
....@@ -7,6 +7,7 @@
77 /dts-v1/;
88
99 #include "rk3036.dtsi"
10
+#include <dt-bindings/input/input.h>
1011
1112 / {
1213 model = "SDK-RK3036";
....@@ -37,6 +38,19 @@
3738 regulator-max-microvolt = <5000000>;
3839 regulator-always-on;
3940 };
41
+
42
+ gpio-keys {
43
+ u-boot,dm-pre-reloc;
44
+ compatible = "gpio-keys";
45
+ status = "okay";
46
+
47
+ volume-up {
48
+ u-boot,dm-pre-reloc;
49
+ linux,code = <KEY_VOLUMEUP>;
50
+ label = "Volume Up";
51
+ gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
52
+ };
53
+ };
4054 };
4155
4256 &i2c1 {
u-boot/arch/arm/dts/rk3036.dtsi
....@@ -223,6 +223,35 @@
223223 grf: syscon@20008000 {
224224 compatible = "rockchip,rk3036-grf", "syscon";
225225 reg = <0x20008000 0x1000>;
226
+ #address-cells = <1>;
227
+ #size-cells = <1>;
228
+
229
+ usb2phy: usb2-phy@17c {
230
+ compatible = "rockchip,rk3036-usb2phy";
231
+ reg = <0x017c 0x0c>;
232
+ clocks = <&cru SCLK_OTGPHY0>;
233
+ clock-names = "phyclk";
234
+ #clock-cells = <0>;
235
+ clock-output-names = "usb480m_phy";
236
+ status = "disabled";
237
+
238
+ u2phy_otg: otg-port {
239
+ #phy-cells = <0>;
240
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
241
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
242
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
243
+ interrupt-names = "otg-bvalid", "otg-id",
244
+ "linestate";
245
+ status = "disabled";
246
+ };
247
+
248
+ u2phy_host: host-port {
249
+ #phy-cells = <0>;
250
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
251
+ interrupt-names = "linestate";
252
+ status = "disabled";
253
+ };
254
+ };
226255 };
227256
228257 usb_otg: usb@10180000 {
u-boot/arch/arm/dts/rk3128-u-boot.dtsi
....@@ -39,6 +39,11 @@
3939 };
4040 };
4141
42
+&sfc {
43
+ u-boot,dm-pre-reloc;
44
+ status = "okay";
45
+};
46
+
4247 &emmc {
4348 u-boot,dm-pre-reloc;
4449 status = "okay";
u-boot/arch/arm/dts/rk3128.dtsi
....@@ -222,6 +222,18 @@
222222 reg = <0x20000110 0x24>;
223223 #reset-cells = <1>;
224224 };
225
+
226
+ sfc: sfc@1020c000 {
227
+ compatible ="rockchip,rksfc","rockchip,sfc";
228
+ reg = <0x1020c000 0x8000>;
229
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
230
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
231
+ clock-names = "clk_sfc", "hclk_sfc";
232
+ assigned-clocks = <&cru SCLK_SFC>;
233
+ assigned-clock-rates = <60000000>;
234
+ status = "disabled";
235
+ };
236
+
225237 nandc: nandc@10500000 {
226238 compatible = "rockchip,rk-nandc";
227239 reg = <0x10500000 0x4000>;
....@@ -590,6 +602,8 @@
590602 grf: syscon@20008000 {
591603 compatible = "rockchip,rk3128-grf", "syscon";
592604 reg = <0x20008000 0x1000>;
605
+ #address-cells = <1>;
606
+ #size-cells = <1>;
593607
594608 lvds: lvds {
595609 compatible = "rockchip,rk3126-lvds";
u-boot/arch/arm/dts/rk3308-u-boot.dtsi
....@@ -14,6 +14,14 @@
1414 stdout-path = &uart2;
1515 u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc;
1616 };
17
+
18
+ secure-otp@ff2a8000 {
19
+ compatible = "rockchip,rk3308-secure-otp";
20
+ reg = <0x0 0xff2a8000 0x0 0x4000>;
21
+ secure_conf = <0xff2b0004>;
22
+ mask_addr = <0xff540000>;
23
+ u-boot,dm-pre-reloc;
24
+ };
1725 };
1826
1927 &psci {
....@@ -121,10 +129,6 @@
121129 &saradc {
122130 u-boot,dm-pre-reloc;
123131 status = "okay";
124
-};
125
-
126
-&secure_otp {
127
- u-boot,dm-pre-reloc;
128132 };
129133
130134 &uart0 {
u-boot/arch/arm/dts/rk3308.dtsi
....@@ -264,13 +264,6 @@
264264 status = "disabled";
265265 };
266266
267
- secure_otp: secure_otp@0xff2a8000 {
268
- compatible = "rockchip,rk3308-secure-otp";
269
- reg = <0x0 0xff2a8000 0x0 0x4000>;
270
- secure_conf = <0xff2b0004>;
271
- mask_addr = <0xff540000>;
272
- };
273
-
274267 vop: vop@ff2e0000 {
275268 compatible = "rockchip,rk3308-vop";
276269 reg = <0x0 0xff2e0000 0x0 0x1fc>, <0x0 0xff2e0a00 0x0 0x400>;
u-boot/arch/arm/dts/rk3528-evb.dts
....@@ -0,0 +1,31 @@
1
+/*
2
+ * SPDX-License-Identifier: GPL-2.0+
3
+ *
4
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
5
+ */
6
+
7
+/dts-v1/;
8
+#include "rk3528.dtsi"
9
+#include "rk3528-u-boot.dtsi"
10
+#include <dt-bindings/input/input.h>
11
+
12
+/ {
13
+ model = "Rockchip RK3528 Evaluation Board";
14
+ compatible = "rockchip,rk3528-evb", "rockchip,rk3528";
15
+
16
+ adc-keys {
17
+ compatible = "adc-keys";
18
+ io-channels = <&saradc 1>;
19
+ io-channel-names = "buttons";
20
+ keyup-threshold-microvolt = <1800000>;
21
+ u-boot,dm-pre-reloc;
22
+ status = "okay";
23
+
24
+ volumeup-key {
25
+ u-boot,dm-pre-reloc;
26
+ linux,code = <KEY_VOLUMEUP>;
27
+ label = "volume up";
28
+ press-threshold-microvolt = <9>;
29
+ };
30
+ };
31
+};
u-boot/arch/arm/dts/rk3528-pinctrl.dtsi
....@@ -0,0 +1,1241 @@
1
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+/*
3
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4
+ */
5
+
6
+#include <dt-bindings/pinctrl/rockchip.h>
7
+#include "rockchip-pinconf.dtsi"
8
+
9
+/*
10
+ * This file is auto generated by pin2dts tool, please keep these code
11
+ * by adding changes at end of this file.
12
+ */
13
+&pinctrl {
14
+ arm {
15
+ arm_pins: arm-pins {
16
+ rockchip,pins =
17
+ /* arm_avs */
18
+ <4 RK_PC4 3 &pcfg_pull_none>;
19
+ };
20
+ };
21
+
22
+ can0 {
23
+ can0m0_pins: can0m0-pins {
24
+ rockchip,pins =
25
+ /* can0_rx_m0 */
26
+ <4 RK_PA0 3 &pcfg_pull_none>,
27
+ /* can0_tx_m0 */
28
+ <4 RK_PA1 3 &pcfg_pull_none>;
29
+ };
30
+
31
+ can0m1_pins: can0m1-pins {
32
+ rockchip,pins =
33
+ /* can0_rx_m1 */
34
+ <4 RK_PC6 3 &pcfg_pull_none>,
35
+ /* can0_tx_m1 */
36
+ <4 RK_PC5 3 &pcfg_pull_none>;
37
+ };
38
+ };
39
+
40
+ can1 {
41
+ can1m0_pins: can1m0-pins {
42
+ rockchip,pins =
43
+ /* can1_rx_m0 */
44
+ <4 RK_PA2 4 &pcfg_pull_none>,
45
+ /* can1_tx_m0 */
46
+ <4 RK_PA3 4 &pcfg_pull_none>;
47
+ };
48
+
49
+ can1m1_pins: can1m1-pins {
50
+ rockchip,pins =
51
+ /* can1_rx_m1 */
52
+ <4 RK_PB0 4 &pcfg_pull_none>,
53
+ /* can1_tx_m1 */
54
+ <4 RK_PB1 4 &pcfg_pull_none>;
55
+ };
56
+ };
57
+
58
+ can2 {
59
+ can2m0_pins: can2m0-pins {
60
+ rockchip,pins =
61
+ /* can2_rx_m0 */
62
+ <1 RK_PB3 2 &pcfg_pull_none>,
63
+ /* can2_tx_m0 */
64
+ <1 RK_PB2 2 &pcfg_pull_none>;
65
+ };
66
+
67
+ can2m1_pins: can2m1-pins {
68
+ rockchip,pins =
69
+ /* can2_rx_m1 */
70
+ <3 RK_PA5 5 &pcfg_pull_none>,
71
+ /* can2_tx_m1 */
72
+ <3 RK_PA4 5 &pcfg_pull_none>;
73
+ };
74
+ };
75
+
76
+ can3 {
77
+ can3m0_pins: can3m0-pins {
78
+ rockchip,pins =
79
+ /* can3_rx_m0 */
80
+ <1 RK_PB5 2 &pcfg_pull_none>,
81
+ /* can3_tx_m0 */
82
+ <1 RK_PB4 2 &pcfg_pull_none>;
83
+ };
84
+
85
+ can3m1_pins: can3m1-pins {
86
+ rockchip,pins =
87
+ /* can3_rx_m1 */
88
+ <3 RK_PB3 2 &pcfg_pull_none>,
89
+ /* can3_tx_m1 */
90
+ <3 RK_PB2 2 &pcfg_pull_none>;
91
+ };
92
+ };
93
+
94
+ clk {
95
+ clkm0_32k_out: clkm0-32k-out {
96
+ rockchip,pins =
97
+ /* clkm0_32k_out */
98
+ <3 RK_PC3 3 &pcfg_pull_none>;
99
+ };
100
+
101
+ clkm1_32k_out: clkm1-32k-out {
102
+ rockchip,pins =
103
+ /* clkm1_32k_out */
104
+ <1 RK_PC3 1 &pcfg_pull_none>;
105
+ };
106
+ };
107
+
108
+ emmc {
109
+ emmc_rstnout: emmc-rstnout {
110
+ rockchip,pins =
111
+ /* emmc_rstn */
112
+ <1 RK_PD6 1 &pcfg_pull_none>;
113
+ };
114
+
115
+ emmc_bus8: emmc-bus8 {
116
+ rockchip,pins =
117
+ /* emmc_d0 */
118
+ <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>,
119
+ /* emmc_d1 */
120
+ <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>,
121
+ /* emmc_d2 */
122
+ <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>,
123
+ /* emmc_d3 */
124
+ <1 RK_PC7 1 &pcfg_pull_up_drv_level_2>,
125
+ /* emmc_d4 */
126
+ <1 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
127
+ /* emmc_d5 */
128
+ <1 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
129
+ /* emmc_d6 */
130
+ <1 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
131
+ /* emmc_d7 */
132
+ <1 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
133
+ };
134
+
135
+ emmc_clk: emmc-clk {
136
+ rockchip,pins =
137
+ /* emmc_clk */
138
+ <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
139
+ };
140
+
141
+ emmc_cmd: emmc-cmd {
142
+ rockchip,pins =
143
+ /* emmc_cmd */
144
+ <1 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
145
+ };
146
+
147
+ emmc_strb: emmc-strb {
148
+ rockchip,pins =
149
+ /* emmc_strb */
150
+ <1 RK_PD7 1 &pcfg_pull_none>;
151
+ };
152
+ };
153
+
154
+ eth {
155
+ eth_pins: eth-pins {
156
+ rockchip,pins =
157
+ /* eth_clk_25m_out */
158
+ <3 RK_PB5 2 &pcfg_pull_none>;
159
+ };
160
+ };
161
+
162
+ fephy {
163
+ fephym0_led_dpx: fephym0-led_dpx {
164
+ rockchip,pins =
165
+ /* fephy_led_dpx_m0 */
166
+ <4 RK_PB5 2 &pcfg_pull_none>;
167
+ };
168
+
169
+ fephym0_led_link: fephym0-led_link {
170
+ rockchip,pins =
171
+ /* fephy_led_link_m0 */
172
+ <4 RK_PC0 2 &pcfg_pull_none>;
173
+ };
174
+
175
+ fephym0_led_spd: fephym0-led_spd {
176
+ rockchip,pins =
177
+ /* fephy_led_spd_m0 */
178
+ <4 RK_PB7 2 &pcfg_pull_none>;
179
+ };
180
+
181
+ fephym1_led_dpx: fephym1-led_dpx {
182
+ rockchip,pins =
183
+ /* fephy_led_dpx_m1 */
184
+ <2 RK_PA4 5 &pcfg_pull_none>;
185
+ };
186
+
187
+ fephym1_led_link: fephym1-led_link {
188
+ rockchip,pins =
189
+ /* fephy_led_link_m1 */
190
+ <2 RK_PA6 5 &pcfg_pull_none>;
191
+ };
192
+
193
+ fephym1_led_spd: fephym1-led_spd {
194
+ rockchip,pins =
195
+ /* fephy_led_spd_m1 */
196
+ <2 RK_PA5 5 &pcfg_pull_none>;
197
+ };
198
+ };
199
+
200
+ fspi {
201
+ fspi_pins: fspi-pins {
202
+ rockchip,pins =
203
+ /* fspi_clk */
204
+ <1 RK_PD5 2 &pcfg_pull_none>,
205
+ /* fspi_d0 */
206
+ <1 RK_PC4 2 &pcfg_pull_none>,
207
+ /* fspi_d1 */
208
+ <1 RK_PC5 2 &pcfg_pull_none>,
209
+ /* fspi_d2 */
210
+ <1 RK_PC6 2 &pcfg_pull_none>,
211
+ /* fspi_d3 */
212
+ <1 RK_PC7 2 &pcfg_pull_none>;
213
+ };
214
+
215
+ fspi_csn0: fspi-csn0 {
216
+ rockchip,pins =
217
+ /* fspi_csn0 */
218
+ <1 RK_PD0 2 &pcfg_pull_none>;
219
+ };
220
+ fspi_csn1: fspi-csn1 {
221
+ rockchip,pins =
222
+ /* fspi_csn1 */
223
+ <1 RK_PD1 2 &pcfg_pull_none>;
224
+ };
225
+ };
226
+
227
+ gpu {
228
+ gpu_pins: gpu-pins {
229
+ rockchip,pins =
230
+ /* gpu_avs */
231
+ <4 RK_PC3 3 &pcfg_pull_none>;
232
+ };
233
+ };
234
+
235
+ hdmi {
236
+ hdmi_pins: hdmi-pins {
237
+ rockchip,pins =
238
+ /* hdmi_tx_cec */
239
+ <0 RK_PA3 1 &pcfg_pull_none>,
240
+ /* hdmi_tx_hpd */
241
+ <0 RK_PA2 1 &pcfg_pull_none>,
242
+ /* hdmi_tx_scl */
243
+ <0 RK_PA4 1 &pcfg_pull_none>,
244
+ /* hdmi_tx_sda */
245
+ <0 RK_PA5 1 &pcfg_pull_none>;
246
+ };
247
+ };
248
+
249
+ hsm {
250
+ hsmm0_pins: hsmm0-pins {
251
+ rockchip,pins =
252
+ /* hsm_clk_out_m0 */
253
+ <2 RK_PA2 4 &pcfg_pull_none>;
254
+ };
255
+
256
+ hsmm1_pins: hsmm1-pins {
257
+ rockchip,pins =
258
+ /* hsm_clk_out_m1 */
259
+ <1 RK_PA4 3 &pcfg_pull_none>;
260
+ };
261
+ };
262
+
263
+ i2c0 {
264
+ i2c0m0_xfer: i2c0m0-xfer {
265
+ rockchip,pins =
266
+ /* i2c0_scl_m0 */
267
+ <4 RK_PC4 2 &pcfg_pull_none_smt>,
268
+ /* i2c0_sda_m0 */
269
+ <4 RK_PC3 2 &pcfg_pull_none_smt>;
270
+ };
271
+
272
+ i2c0m1_xfer: i2c0m1-xfer {
273
+ rockchip,pins =
274
+ /* i2c0_scl_m1 */
275
+ <4 RK_PA1 2 &pcfg_pull_none_smt>,
276
+ /* i2c0_sda_m1 */
277
+ <4 RK_PA0 2 &pcfg_pull_none_smt>;
278
+ };
279
+ };
280
+
281
+ i2c1 {
282
+ i2c1m0_xfer: i2c1m0-xfer {
283
+ rockchip,pins =
284
+ /* i2c1_scl_m0 */
285
+ <4 RK_PA3 2 &pcfg_pull_none_smt>,
286
+ /* i2c1_sda_m0 */
287
+ <4 RK_PA2 2 &pcfg_pull_none_smt>;
288
+ };
289
+
290
+ i2c1m1_xfer: i2c1m1-xfer {
291
+ rockchip,pins =
292
+ /* i2c1_scl_m1 */
293
+ <4 RK_PC5 4 &pcfg_pull_none_smt>,
294
+ /* i2c1_sda_m1 */
295
+ <4 RK_PC6 4 &pcfg_pull_none_smt>;
296
+ };
297
+ };
298
+
299
+ i2c2 {
300
+ i2c2m0_xfer: i2c2m0-xfer {
301
+ rockchip,pins =
302
+ /* i2c2_scl_m0 */
303
+ <0 RK_PA4 2 &pcfg_pull_none_smt>,
304
+ /* i2c2_sda_m0 */
305
+ <0 RK_PA5 2 &pcfg_pull_none_smt>;
306
+ };
307
+
308
+ i2c2m1_xfer: i2c2m1-xfer {
309
+ rockchip,pins =
310
+ /* i2c2_scl_m1 */
311
+ <1 RK_PA5 3 &pcfg_pull_none_smt>,
312
+ /* i2c2_sda_m1 */
313
+ <1 RK_PA6 3 &pcfg_pull_none_smt>;
314
+ };
315
+ };
316
+
317
+ i2c3 {
318
+ i2c3m0_xfer: i2c3m0-xfer {
319
+ rockchip,pins =
320
+ /* i2c3_scl_m0 */
321
+ <1 RK_PA0 2 &pcfg_pull_none_smt>,
322
+ /* i2c3_sda_m0 */
323
+ <1 RK_PA1 2 &pcfg_pull_none_smt>;
324
+ };
325
+
326
+ i2c3m1_xfer: i2c3m1-xfer {
327
+ rockchip,pins =
328
+ /* i2c3_scl_m1 */
329
+ <3 RK_PC1 5 &pcfg_pull_none_smt>,
330
+ /* i2c3_sda_m1 */
331
+ <3 RK_PC3 5 &pcfg_pull_none_smt>;
332
+ };
333
+ };
334
+
335
+ i2c4 {
336
+ i2c4_xfer: i2c4-xfer {
337
+ rockchip,pins =
338
+ /* i2c4_scl */
339
+ <2 RK_PA0 4 &pcfg_pull_none_smt>,
340
+ /* i2c4_sda */
341
+ <2 RK_PA1 4 &pcfg_pull_none_smt>;
342
+ };
343
+ };
344
+
345
+ i2c5 {
346
+ i2c5m0_xfer: i2c5m0-xfer {
347
+ rockchip,pins =
348
+ /* i2c5_scl_m0 */
349
+ <1 RK_PB2 3 &pcfg_pull_none_smt>,
350
+ /* i2c5_sda_m0 */
351
+ <1 RK_PB3 3 &pcfg_pull_none_smt>;
352
+ };
353
+
354
+ i2c5m1_xfer: i2c5m1-xfer {
355
+ rockchip,pins =
356
+ /* i2c5_scl_m1 */
357
+ <1 RK_PD2 3 &pcfg_pull_none_smt>,
358
+ /* i2c5_sda_m1 */
359
+ <1 RK_PD3 3 &pcfg_pull_none_smt>;
360
+ };
361
+ };
362
+
363
+ i2c6 {
364
+ i2c6m0_xfer: i2c6m0-xfer {
365
+ rockchip,pins =
366
+ /* i2c6_scl_m0 */
367
+ <3 RK_PB2 5 &pcfg_pull_none_smt>,
368
+ /* i2c6_sda_m0 */
369
+ <3 RK_PB3 5 &pcfg_pull_none_smt>;
370
+ };
371
+
372
+ i2c6m1_xfer: i2c6m1-xfer {
373
+ rockchip,pins =
374
+ /* i2c6_scl_m1 */
375
+ <1 RK_PD4 3 &pcfg_pull_none_smt>,
376
+ /* i2c6_sda_m1 */
377
+ <1 RK_PD7 3 &pcfg_pull_none_smt>;
378
+ };
379
+ };
380
+
381
+ i2c7 {
382
+ i2c7_xfer: i2c7-xfer {
383
+ rockchip,pins =
384
+ /* i2c7_scl */
385
+ <2 RK_PA5 4 &pcfg_pull_none_smt>,
386
+ /* i2c7_sda */
387
+ <2 RK_PA6 4 &pcfg_pull_none_smt>;
388
+ };
389
+ };
390
+
391
+ i2s0 {
392
+ i2s0m0_pins: i2s0m0-pins {
393
+ rockchip,pins =
394
+ /* i2s0_lrck_m0 */
395
+ <3 RK_PB6 1 &pcfg_pull_none>,
396
+ /* i2s0_mclk_m0 */
397
+ <3 RK_PB4 1 &pcfg_pull_none>,
398
+ /* i2s0_sclk_m0 */
399
+ <3 RK_PB5 1 &pcfg_pull_none>,
400
+ /* i2s0_sdi_m0 */
401
+ <3 RK_PB7 1 &pcfg_pull_none>,
402
+ /* i2s0_sdo_m0 */
403
+ <3 RK_PC0 1 &pcfg_pull_none>;
404
+ };
405
+
406
+ i2s0m1_pins: i2s0m1-pins {
407
+ rockchip,pins =
408
+ /* i2s0_lrck_m1 */
409
+ <1 RK_PB6 1 &pcfg_pull_none>,
410
+ /* i2s0_mclk_m1 */
411
+ <1 RK_PB4 1 &pcfg_pull_none>,
412
+ /* i2s0_sclk_m1 */
413
+ <1 RK_PB5 1 &pcfg_pull_none>,
414
+ /* i2s0_sdi_m1 */
415
+ <1 RK_PB7 1 &pcfg_pull_none>,
416
+ /* i2s0_sdo_m1 */
417
+ <1 RK_PC0 1 &pcfg_pull_none>;
418
+ };
419
+ };
420
+
421
+ i2s1 {
422
+ i2s1_pins: i2s1-pins {
423
+ rockchip,pins =
424
+ /* i2s1_lrck */
425
+ <4 RK_PA6 1 &pcfg_pull_none>,
426
+ /* i2s1_mclk */
427
+ <4 RK_PA4 1 &pcfg_pull_none>,
428
+ /* i2s1_sclk */
429
+ <4 RK_PA5 1 &pcfg_pull_none>,
430
+ /* i2s1_sdi0 */
431
+ <4 RK_PB4 1 &pcfg_pull_none>,
432
+ /* i2s1_sdi1 */
433
+ <4 RK_PB3 1 &pcfg_pull_none>,
434
+ /* i2s1_sdi2 */
435
+ <4 RK_PA3 1 &pcfg_pull_none>,
436
+ /* i2s1_sdi3 */
437
+ <4 RK_PA2 1 &pcfg_pull_none>,
438
+ /* i2s1_sdo0 */
439
+ <4 RK_PA7 1 &pcfg_pull_none>,
440
+ /* i2s1_sdo1 */
441
+ <4 RK_PB0 1 &pcfg_pull_none>,
442
+ /* i2s1_sdo2 */
443
+ <4 RK_PB1 1 &pcfg_pull_none>,
444
+ /* i2s1_sdo3 */
445
+ <4 RK_PB2 1 &pcfg_pull_none>;
446
+ };
447
+ };
448
+
449
+ jtag {
450
+ jtagm0_pins: jtagm0-pins {
451
+ rockchip,pins =
452
+ /* jtag_cpu_tck_m0 */
453
+ <2 RK_PA2 2 &pcfg_pull_none>,
454
+ /* jtag_cpu_tms_m0 */
455
+ <2 RK_PA3 2 &pcfg_pull_none>,
456
+ /* jtag_mcu_tck_m0 */
457
+ <2 RK_PA4 2 &pcfg_pull_none>,
458
+ /* jtag_mcu_tms_m0 */
459
+ <2 RK_PA5 2 &pcfg_pull_none>;
460
+ };
461
+
462
+ jtagm1_pins: jtagm1-pins {
463
+ rockchip,pins =
464
+ /* jtag_cpu_tck_m1 */
465
+ <4 RK_PD0 2 &pcfg_pull_none>,
466
+ /* jtag_cpu_tms_m1 */
467
+ <4 RK_PC7 2 &pcfg_pull_none>,
468
+ /* jtag_mcu_tck_m1 */
469
+ <4 RK_PD0 3 &pcfg_pull_none>,
470
+ /* jtag_mcu_tms_m1 */
471
+ <4 RK_PC7 3 &pcfg_pull_none>;
472
+ };
473
+ };
474
+
475
+ pcie {
476
+ pciem0_pins: pciem0-pins {
477
+ rockchip,pins =
478
+ /* pcie_clkreqn_m0 */
479
+ <3 RK_PA6 5 &pcfg_pull_none>,
480
+ /* pcie_perstn_m0 */
481
+ <3 RK_PB0 5 &pcfg_pull_none>,
482
+ /* pcie_waken_m0 */
483
+ <3 RK_PA7 5 &pcfg_pull_none>;
484
+ };
485
+
486
+ pciem1_pins: pciem1-pins {
487
+ rockchip,pins =
488
+ /* pcie_clkreqn_m1 */
489
+ <1 RK_PA0 4 &pcfg_pull_none>,
490
+ /* pcie_perstn_m1 */
491
+ <1 RK_PA2 4 &pcfg_pull_none>,
492
+ /* pcie_waken_m1 */
493
+ <1 RK_PA1 4 &pcfg_pull_none>;
494
+ };
495
+ };
496
+
497
+ pdm {
498
+ pdm_clk0: pdm-clk0 {
499
+ rockchip,pins =
500
+ /* pdm_clk0 */
501
+ <4 RK_PB5 3 &pcfg_pull_none>;
502
+ };
503
+
504
+ pdm_clk1: pdm-clk1 {
505
+ rockchip,pins =
506
+ /* pdm_clk1 */
507
+ <4 RK_PA4 3 &pcfg_pull_none>;
508
+ };
509
+
510
+ pdm_sdi0: pdm-sdi0 {
511
+ rockchip,pins =
512
+ /* pdm_sdi0 */
513
+ <4 RK_PB2 3 &pcfg_pull_none>;
514
+ };
515
+
516
+ pdm_sdi1: pdm-sdi1 {
517
+ rockchip,pins =
518
+ /* pdm_sdi1 */
519
+ <4 RK_PB1 3 &pcfg_pull_none>;
520
+ };
521
+
522
+ pdm_sdi2: pdm-sdi2 {
523
+ rockchip,pins =
524
+ /* pdm_sdi2 */
525
+ <4 RK_PB3 3 &pcfg_pull_none>;
526
+ };
527
+
528
+ pdm_sdi3: pdm-sdi3 {
529
+ rockchip,pins =
530
+ /* pdm_sdi3 */
531
+ <4 RK_PC1 3 &pcfg_pull_none>;
532
+ };
533
+ };
534
+
535
+ pmu {
536
+ pmu_pins: pmu-pins {
537
+ rockchip,pins =
538
+ /* pmu_debug */
539
+ <4 RK_PA0 4 &pcfg_pull_none>;
540
+ };
541
+ };
542
+
543
+ pwm0 {
544
+ pwm0m0_pins: pwm0m0-pins {
545
+ rockchip,pins =
546
+ /* pwm0_m0 */
547
+ <4 RK_PC3 1 &pcfg_pull_none>;
548
+ };
549
+
550
+ pwm0m1_pins: pwm0m1-pins {
551
+ rockchip,pins =
552
+ /* pwm0_m1 */
553
+ <1 RK_PA2 5 &pcfg_pull_none>;
554
+ };
555
+ };
556
+
557
+ pwm1 {
558
+ pwm1m0_pins: pwm1m0-pins {
559
+ rockchip,pins =
560
+ /* pwm1_m0 */
561
+ <4 RK_PC4 1 &pcfg_pull_none>;
562
+ };
563
+
564
+ pwm1m1_pins: pwm1m1-pins {
565
+ rockchip,pins =
566
+ /* pwm1_m1 */
567
+ <1 RK_PA3 4 &pcfg_pull_none>;
568
+ };
569
+ };
570
+
571
+ pwm2 {
572
+ pwm2m0_pins: pwm2m0-pins {
573
+ rockchip,pins =
574
+ /* pwm2_m0 */
575
+ <4 RK_PC5 1 &pcfg_pull_none>;
576
+ };
577
+
578
+ pwm2m1_pins: pwm2m1-pins {
579
+ rockchip,pins =
580
+ /* pwm2_m1 */
581
+ <1 RK_PA7 2 &pcfg_pull_none>;
582
+ };
583
+ };
584
+
585
+ pwm3 {
586
+ pwm3m0_pins: pwm3m0-pins {
587
+ rockchip,pins =
588
+ /* pwm3_m0 */
589
+ <4 RK_PC6 1 &pcfg_pull_none>;
590
+ };
591
+
592
+ pwm3m1_pins: pwm3m1-pins {
593
+ rockchip,pins =
594
+ /* pwm3_m1 */
595
+ <2 RK_PA4 3 &pcfg_pull_none>;
596
+ };
597
+ };
598
+
599
+ pwm4 {
600
+ pwm4m0_pins: pwm4m0-pins {
601
+ rockchip,pins =
602
+ /* pwm4_m0 */
603
+ <4 RK_PB7 1 &pcfg_pull_none>;
604
+ };
605
+
606
+ pwm4m1_pins: pwm4m1-pins {
607
+ rockchip,pins =
608
+ /* pwm4_m1 */
609
+ <1 RK_PA4 2 &pcfg_pull_none>;
610
+ };
611
+ };
612
+
613
+ pwm5 {
614
+ pwm5m0_pins: pwm5m0-pins {
615
+ rockchip,pins =
616
+ /* pwm5_m0 */
617
+ <4 RK_PC0 1 &pcfg_pull_none>;
618
+ };
619
+
620
+ pwm5m1_pins: pwm5m1-pins {
621
+ rockchip,pins =
622
+ /* pwm5_m1 */
623
+ <3 RK_PC3 1 &pcfg_pull_none>;
624
+ };
625
+ };
626
+
627
+ pwm6 {
628
+ pwm6m0_pins: pwm6m0-pins {
629
+ rockchip,pins =
630
+ /* pwm6_m0 */
631
+ <4 RK_PC1 1 &pcfg_pull_none>;
632
+ };
633
+
634
+ pwm6m1_pins: pwm6m1-pins {
635
+ rockchip,pins =
636
+ /* pwm6_m1 */
637
+ <1 RK_PC3 3 &pcfg_pull_none>;
638
+ };
639
+
640
+ pwm6m2_pins: pwm6m2-pins {
641
+ rockchip,pins =
642
+ /* pwm6_m2 */
643
+ <3 RK_PC1 1 &pcfg_pull_none>;
644
+ };
645
+ };
646
+
647
+ pwm7 {
648
+ pwm7m0_pins: pwm7m0-pins {
649
+ rockchip,pins =
650
+ /* pwm7_m0 */
651
+ <4 RK_PC2 1 &pcfg_pull_none>;
652
+ };
653
+
654
+ pwm7m1_pins: pwm7m1-pins {
655
+ rockchip,pins =
656
+ /* pwm7_m1 */
657
+ <1 RK_PC2 2 &pcfg_pull_none>;
658
+ };
659
+ };
660
+
661
+ pwr {
662
+ pwr_pins: pwr-pins {
663
+ rockchip,pins =
664
+ /* pwr_ctrl0 */
665
+ <4 RK_PC2 2 &pcfg_pull_none>,
666
+ /* pwr_ctrl1 */
667
+ <4 RK_PB6 1 &pcfg_pull_none>;
668
+ };
669
+ };
670
+
671
+ ref {
672
+ refm0_pins: refm0-pins {
673
+ rockchip,pins =
674
+ /* ref_clk_out_m0 */
675
+ <0 RK_PA1 1 &pcfg_pull_none>;
676
+ };
677
+
678
+ refm1_pins: refm1-pins {
679
+ rockchip,pins =
680
+ /* ref_clk_out_m1 */
681
+ <3 RK_PC3 6 &pcfg_pull_none>;
682
+ };
683
+ };
684
+
685
+ rgmii {
686
+ rgmii_miim: rgmii-miim {
687
+ rockchip,pins =
688
+ /* rgmii_mdc */
689
+ <3 RK_PB6 2 &pcfg_pull_none>,
690
+ /* rgmii_mdio */
691
+ <3 RK_PB7 2 &pcfg_pull_none>;
692
+ };
693
+
694
+ rgmii_rx_bus2: rgmii-rx_bus2 {
695
+ rockchip,pins =
696
+ /* rgmii_rxd0 */
697
+ <3 RK_PA3 2 &pcfg_pull_none>,
698
+ /* rgmii_rxd1 */
699
+ <3 RK_PA2 2 &pcfg_pull_none>,
700
+ /* rgmii_rxdv_crs */
701
+ <3 RK_PC2 2 &pcfg_pull_none>;
702
+ };
703
+
704
+ rgmii_tx_bus2: rgmii-tx_bus2 {
705
+ rockchip,pins =
706
+ /* rgmii_txd0 */
707
+ <3 RK_PA1 2 &pcfg_pull_none>,
708
+ /* rgmii_txd1 */
709
+ <3 RK_PA0 2 &pcfg_pull_none>,
710
+ /* rgmii_txen */
711
+ <3 RK_PC0 2 &pcfg_pull_none>;
712
+ };
713
+
714
+ rgmii_rgmii_clk: rgmii-rgmii_clk {
715
+ rockchip,pins =
716
+ /* rgmii_rxclk */
717
+ <3 RK_PA5 2 &pcfg_pull_none>,
718
+ /* rgmii_txclk */
719
+ <3 RK_PA4 2 &pcfg_pull_none>;
720
+ };
721
+
722
+ rgmii_rgmii_bus: rgmii-rgmii_bus {
723
+ rockchip,pins =
724
+ /* rgmii_rxd2 */
725
+ <3 RK_PA7 2 &pcfg_pull_none>,
726
+ /* rgmii_rxd3 */
727
+ <3 RK_PA6 2 &pcfg_pull_none>,
728
+ /* rgmii_txd2 */
729
+ <3 RK_PB1 2 &pcfg_pull_none>,
730
+ /* rgmii_txd3 */
731
+ <3 RK_PB0 2 &pcfg_pull_none>;
732
+ };
733
+
734
+ rgmii_clk: rgmii-clk {
735
+ rockchip,pins =
736
+ /* rgmii_clk */
737
+ <3 RK_PB4 2 &pcfg_pull_none>;
738
+ };
739
+ rgmii_txer: rgmii-txer {
740
+ rockchip,pins =
741
+ /* rgmii_txer */
742
+ <3 RK_PC1 2 &pcfg_pull_none>;
743
+ };
744
+ };
745
+
746
+ scr {
747
+ scrm0_pins: scrm0-pins {
748
+ rockchip,pins =
749
+ /* scr_clk_m0 */
750
+ <1 RK_PA2 3 &pcfg_pull_none>,
751
+ /* scr_data_m0 */
752
+ <1 RK_PA1 3 &pcfg_pull_none>,
753
+ /* scr_detn_m0 */
754
+ <1 RK_PA0 3 &pcfg_pull_none>,
755
+ /* scr_rstn_m0 */
756
+ <1 RK_PA3 3 &pcfg_pull_none>;
757
+ };
758
+
759
+ scrm1_pins: scrm1-pins {
760
+ rockchip,pins =
761
+ /* scr_clk_m1 */
762
+ <2 RK_PA5 3 &pcfg_pull_none>,
763
+ /* scr_data_m1 */
764
+ <2 RK_PA3 4 &pcfg_pull_none>,
765
+ /* scr_detn_m1 */
766
+ <2 RK_PA6 3 &pcfg_pull_none>,
767
+ /* scr_rstn_m1 */
768
+ <2 RK_PA4 4 &pcfg_pull_none>;
769
+ };
770
+ };
771
+
772
+ sdio0 {
773
+ sdio0_bus4: sdio0-bus4 {
774
+ rockchip,pins =
775
+ /* sdio0_d0 */
776
+ <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
777
+ /* sdio0_d1 */
778
+ <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
779
+ /* sdio0_d2 */
780
+ <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
781
+ /* sdio0_d3 */
782
+ <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
783
+ };
784
+
785
+ sdio0_clk: sdio0-clk {
786
+ rockchip,pins =
787
+ /* sdio0_clk */
788
+ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
789
+ };
790
+
791
+ sdio0_cmd: sdio0-cmd {
792
+ rockchip,pins =
793
+ /* sdio0_cmd */
794
+ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
795
+ };
796
+
797
+ sdio0_det: sdio0-det {
798
+ rockchip,pins =
799
+ /* sdio0_det */
800
+ <1 RK_PA6 1 &pcfg_pull_up>;
801
+ };
802
+
803
+ sdio0_pwren: sdio0-pwren {
804
+ rockchip,pins =
805
+ /* sdio0_pwren */
806
+ <1 RK_PA7 1 &pcfg_pull_none>;
807
+ };
808
+ };
809
+
810
+ sdio1 {
811
+ sdio1_bus4: sdio1-bus4 {
812
+ rockchip,pins =
813
+ /* sdio1_d0 */
814
+ <3 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
815
+ /* sdio1_d1 */
816
+ <3 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
817
+ /* sdio1_d2 */
818
+ <3 RK_PB0 1 &pcfg_pull_up_drv_level_2>,
819
+ /* sdio1_d3 */
820
+ <3 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
821
+ };
822
+
823
+ sdio1_clk: sdio1-clk {
824
+ rockchip,pins =
825
+ /* sdio1_clk */
826
+ <3 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
827
+ };
828
+
829
+ sdio1_cmd: sdio1-cmd {
830
+ rockchip,pins =
831
+ /* sdio1_cmd */
832
+ <3 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
833
+ };
834
+
835
+ sdio1_det: sdio1-det {
836
+ rockchip,pins =
837
+ /* sdio1_det */
838
+ <3 RK_PB3 1 &pcfg_pull_up>;
839
+ };
840
+
841
+ sdio1_pwren: sdio1-pwren {
842
+ rockchip,pins =
843
+ /* sdio1_pwren */
844
+ <3 RK_PB2 1 &pcfg_pull_none>;
845
+ };
846
+ };
847
+
848
+ sdmmc_pins: sdmmc-pins {
849
+ sdmmc_bus4: sdmmc-bus4 {
850
+ rockchip,pins =
851
+ /* sdmmc_d0 */
852
+ <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
853
+ /* sdmmc_d1 */
854
+ <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
855
+ /* sdmmc_d2 */
856
+ <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
857
+ /* sdmmc_d3 */
858
+ <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
859
+ };
860
+
861
+ sdmmc_clk: sdmmc-clk {
862
+ rockchip,pins =
863
+ /* sdmmc_clk */
864
+ <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
865
+ };
866
+
867
+ sdmmc_cmd: sdmmc-cmd {
868
+ rockchip,pins =
869
+ /* sdmmc_cmd */
870
+ <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
871
+ };
872
+
873
+ sdmmc_det: sdmmc-det {
874
+ rockchip,pins =
875
+ /* sdmmc_detn */
876
+ <2 RK_PA6 1 &pcfg_pull_up>;
877
+ };
878
+
879
+ sdmmc_pwren: sdmmc-pwren {
880
+ rockchip,pins =
881
+ /* sdmmc_pwren */
882
+ <4 RK_PA1 1 &pcfg_pull_none>;
883
+ };
884
+ };
885
+
886
+ spdif {
887
+ spdifm0_pins: spdifm0-pins {
888
+ rockchip,pins =
889
+ /* spdif_tx_m0 */
890
+ <4 RK_PA0 1 &pcfg_pull_none>;
891
+ };
892
+
893
+ spdifm1_pins: spdifm1-pins {
894
+ rockchip,pins =
895
+ /* spdif_tx_m1 */
896
+ <1 RK_PC3 2 &pcfg_pull_none>;
897
+ };
898
+
899
+ spdifm2_pins: spdifm2-pins {
900
+ rockchip,pins =
901
+ /* spdif_tx_m2 */
902
+ <3 RK_PC3 2 &pcfg_pull_none>;
903
+ };
904
+ };
905
+
906
+ spi0 {
907
+ spi0_pins: spi0-pins {
908
+ rockchip,pins =
909
+ /* spi0_clk */
910
+ <4 RK_PB4 2 &pcfg_pull_none>,
911
+ /* spi0_miso */
912
+ <4 RK_PB3 2 &pcfg_pull_none>,
913
+ /* spi0_mosi */
914
+ <4 RK_PB2 2 &pcfg_pull_none>;
915
+ };
916
+
917
+ spi0_csn0: spi0-csn0 {
918
+ rockchip,pins =
919
+ /* spi0_csn0 */
920
+ <4 RK_PB6 2 &pcfg_pull_none>;
921
+ };
922
+ spi0_csn1: spi0-csn1 {
923
+ rockchip,pins =
924
+ /* spi0_csn1 */
925
+ <4 RK_PC1 2 &pcfg_pull_none>;
926
+ };
927
+ };
928
+
929
+ spi1 {
930
+ spi1_pins: spi1-pins {
931
+ rockchip,pins =
932
+ /* spi1_clk */
933
+ <1 RK_PB6 2 &pcfg_pull_none>,
934
+ /* spi1_miso */
935
+ <1 RK_PC0 2 &pcfg_pull_none>,
936
+ /* spi1_mosi */
937
+ <1 RK_PB7 2 &pcfg_pull_none>;
938
+ };
939
+
940
+ spi1_csn0: spi1-csn0 {
941
+ rockchip,pins =
942
+ /* spi1_csn0 */
943
+ <1 RK_PC1 1 &pcfg_pull_none>;
944
+ };
945
+ spi1_csn1: spi1-csn1 {
946
+ rockchip,pins =
947
+ /* spi1_csn1 */
948
+ <1 RK_PC2 1 &pcfg_pull_none>;
949
+ };
950
+ };
951
+
952
+ tsi0 {
953
+ tsi0_pins: tsi0-pins {
954
+ rockchip,pins =
955
+ /* tsi0_clkin */
956
+ <3 RK_PB2 3 &pcfg_pull_none>,
957
+ /* tsi0_d0 */
958
+ <3 RK_PB1 3 &pcfg_pull_none>,
959
+ /* tsi0_d1 */
960
+ <3 RK_PB5 3 &pcfg_pull_none>,
961
+ /* tsi0_d2 */
962
+ <3 RK_PB6 3 &pcfg_pull_none>,
963
+ /* tsi0_d3 */
964
+ <3 RK_PB7 3 &pcfg_pull_none>,
965
+ /* tsi0_d4 */
966
+ <3 RK_PA3 3 &pcfg_pull_none>,
967
+ /* tsi0_d5 */
968
+ <3 RK_PA2 3 &pcfg_pull_none>,
969
+ /* tsi0_d6 */
970
+ <3 RK_PA1 3 &pcfg_pull_none>,
971
+ /* tsi0_d7 */
972
+ <3 RK_PA0 3 &pcfg_pull_none>,
973
+ /* tsi0_fail */
974
+ <3 RK_PC0 3 &pcfg_pull_none>,
975
+ /* tsi0_sync */
976
+ <3 RK_PB4 3 &pcfg_pull_none>,
977
+ /* tsi0_valid */
978
+ <3 RK_PB3 3 &pcfg_pull_none>;
979
+ };
980
+ };
981
+
982
+ tsi1 {
983
+ tsi1_pins: tsi1-pins {
984
+ rockchip,pins =
985
+ /* tsi1_clkin */
986
+ <3 RK_PA5 3 &pcfg_pull_none>,
987
+ /* tsi1_d0 */
988
+ <3 RK_PA4 3 &pcfg_pull_none>,
989
+ /* tsi1_sync */
990
+ <3 RK_PA7 3 &pcfg_pull_none>,
991
+ /* tsi1_valid */
992
+ <3 RK_PA6 3 &pcfg_pull_none>;
993
+ };
994
+ };
995
+
996
+ uart0 {
997
+ uart0m0_xfer: uart0m0-xfer {
998
+ rockchip,pins =
999
+ /* uart0_rx_m0 */
1000
+ <4 RK_PC7 1 &pcfg_pull_up>,
1001
+ /* uart0_tx_m0 */
1002
+ <4 RK_PD0 1 &pcfg_pull_up>;
1003
+ };
1004
+
1005
+ uart0m1_xfer: uart0m1-xfer {
1006
+ rockchip,pins =
1007
+ /* uart0_rx_m1 */
1008
+ <2 RK_PA0 2 &pcfg_pull_up>,
1009
+ /* uart0_tx_m1 */
1010
+ <2 RK_PA1 2 &pcfg_pull_up>;
1011
+ };
1012
+ };
1013
+
1014
+ uart1 {
1015
+ uart1m0_xfer: uart1m0-xfer {
1016
+ rockchip,pins =
1017
+ /* uart1_rx_m0 */
1018
+ <4 RK_PA7 2 &pcfg_pull_up>,
1019
+ /* uart1_tx_m0 */
1020
+ <4 RK_PA6 2 &pcfg_pull_up>;
1021
+ };
1022
+
1023
+ uart1m1_xfer: uart1m1-xfer {
1024
+ rockchip,pins =
1025
+ /* uart1_rx_m1 */
1026
+ <4 RK_PC6 2 &pcfg_pull_up>,
1027
+ /* uart1_tx_m1 */
1028
+ <4 RK_PC5 2 &pcfg_pull_up>;
1029
+ };
1030
+
1031
+ uart1_ctsn: uart1-ctsn {
1032
+ rockchip,pins =
1033
+ /* uart1_ctsn */
1034
+ <4 RK_PA4 2 &pcfg_pull_none>;
1035
+ };
1036
+ uart1_rtsn: uart1-rtsn {
1037
+ rockchip,pins =
1038
+ /* uart1_rtsn */
1039
+ <4 RK_PA5 2 &pcfg_pull_none>;
1040
+ };
1041
+ };
1042
+
1043
+ uart2 {
1044
+ uart2m0_xfer: uart2m0-xfer {
1045
+ rockchip,pins =
1046
+ /* uart2_rx_m0 */
1047
+ <3 RK_PA0 1 &pcfg_pull_up>,
1048
+ /* uart2_tx_m0 */
1049
+ <3 RK_PA1 1 &pcfg_pull_up>;
1050
+ };
1051
+
1052
+ uart2m0_ctsn: uart2m0-ctsn {
1053
+ rockchip,pins =
1054
+ /* uart2m0_ctsn */
1055
+ <3 RK_PA3 1 &pcfg_pull_none>;
1056
+ };
1057
+ uart2m0_rtsn: uart2m0-rtsn {
1058
+ rockchip,pins =
1059
+ /* uart2m0_rtsn */
1060
+ <3 RK_PA2 1 &pcfg_pull_none>;
1061
+ };
1062
+
1063
+ uart2m1_xfer: uart2m1-xfer {
1064
+ rockchip,pins =
1065
+ /* uart2_rx_m1 */
1066
+ <1 RK_PB0 1 &pcfg_pull_up>,
1067
+ /* uart2_tx_m1 */
1068
+ <1 RK_PB1 1 &pcfg_pull_up>;
1069
+ };
1070
+
1071
+ uart2m1_ctsn: uart2m1-ctsn {
1072
+ rockchip,pins =
1073
+ /* uart2m1_ctsn */
1074
+ <1 RK_PB3 1 &pcfg_pull_none>;
1075
+ };
1076
+ uart2m1_rtsn: uart2m1-rtsn {
1077
+ rockchip,pins =
1078
+ /* uart2m1_rtsn */
1079
+ <1 RK_PB2 1 &pcfg_pull_none>;
1080
+ };
1081
+ };
1082
+
1083
+ uart3 {
1084
+ uart3m0_xfer: uart3m0-xfer {
1085
+ rockchip,pins =
1086
+ /* uart3_rx_m0 */
1087
+ <4 RK_PB0 2 &pcfg_pull_up>,
1088
+ /* uart3_tx_m0 */
1089
+ <4 RK_PB1 2 &pcfg_pull_up>;
1090
+ };
1091
+
1092
+ uart3m1_xfer: uart3m1-xfer {
1093
+ rockchip,pins =
1094
+ /* uart3_rx_m1 */
1095
+ <4 RK_PB7 3 &pcfg_pull_up>,
1096
+ /* uart3_tx_m1 */
1097
+ <4 RK_PC0 3 &pcfg_pull_up>;
1098
+ };
1099
+
1100
+ uart3_ctsn: uart3-ctsn {
1101
+ rockchip,pins =
1102
+ /* uart3_ctsn */
1103
+ <4 RK_PA3 3 &pcfg_pull_none>;
1104
+ };
1105
+ uart3_rtsn: uart3-rtsn {
1106
+ rockchip,pins =
1107
+ /* uart3_rtsn */
1108
+ <4 RK_PA2 3 &pcfg_pull_none>;
1109
+ };
1110
+ };
1111
+
1112
+ uart4 {
1113
+ uart4_xfer: uart4-xfer {
1114
+ rockchip,pins =
1115
+ /* uart4_rx */
1116
+ <2 RK_PA2 3 &pcfg_pull_up>,
1117
+ /* uart4_tx */
1118
+ <2 RK_PA3 3 &pcfg_pull_up>;
1119
+ };
1120
+
1121
+ uart4_ctsn: uart4-ctsn {
1122
+ rockchip,pins =
1123
+ /* uart4_ctsn */
1124
+ <2 RK_PA1 3 &pcfg_pull_none>;
1125
+ };
1126
+ uart4_rtsn: uart4-rtsn {
1127
+ rockchip,pins =
1128
+ /* uart4_rtsn */
1129
+ <2 RK_PA0 3 &pcfg_pull_none>;
1130
+ };
1131
+ };
1132
+
1133
+ uart5 {
1134
+ uart5m0_xfer: uart5m0-xfer {
1135
+ rockchip,pins =
1136
+ /* uart5_rx_m0 */
1137
+ <1 RK_PA2 2 &pcfg_pull_up>,
1138
+ /* uart5_tx_m0 */
1139
+ <1 RK_PA3 2 &pcfg_pull_up>;
1140
+ };
1141
+
1142
+ uart5m0_ctsn: uart5m0-ctsn {
1143
+ rockchip,pins =
1144
+ /* uart5m0_ctsn */
1145
+ <1 RK_PA6 2 &pcfg_pull_none>;
1146
+ };
1147
+ uart5m0_rtsn: uart5m0-rtsn {
1148
+ rockchip,pins =
1149
+ /* uart5m0_rtsn */
1150
+ <1 RK_PA5 2 &pcfg_pull_none>;
1151
+ };
1152
+
1153
+ uart5m1_xfer: uart5m1-xfer {
1154
+ rockchip,pins =
1155
+ /* uart5_rx_m1 */
1156
+ <1 RK_PD4 2 &pcfg_pull_up>,
1157
+ /* uart5_tx_m1 */
1158
+ <1 RK_PD7 2 &pcfg_pull_up>;
1159
+ };
1160
+
1161
+ uart5m1_ctsn: uart5m1-ctsn {
1162
+ rockchip,pins =
1163
+ /* uart5m1_ctsn */
1164
+ <1 RK_PD3 2 &pcfg_pull_none>;
1165
+ };
1166
+ uart5m1_rtsn: uart5m1-rtsn {
1167
+ rockchip,pins =
1168
+ /* uart5m1_rtsn */
1169
+ <1 RK_PD2 2 &pcfg_pull_none>;
1170
+ };
1171
+ };
1172
+
1173
+ uart6 {
1174
+ uart6m0_xfer: uart6m0-xfer {
1175
+ rockchip,pins =
1176
+ /* uart6_rx_m0 */
1177
+ <3 RK_PA7 4 &pcfg_pull_up>,
1178
+ /* uart6_tx_m0 */
1179
+ <3 RK_PA6 4 &pcfg_pull_up>;
1180
+ };
1181
+
1182
+ uart6m1_xfer: uart6m1-xfer {
1183
+ rockchip,pins =
1184
+ /* uart6_rx_m1 */
1185
+ <3 RK_PC3 4 &pcfg_pull_up>,
1186
+ /* uart6_tx_m1 */
1187
+ <3 RK_PC1 4 &pcfg_pull_up>;
1188
+ };
1189
+
1190
+ uart6_ctsn: uart6-ctsn {
1191
+ rockchip,pins =
1192
+ /* uart6_ctsn */
1193
+ <3 RK_PA4 4 &pcfg_pull_none>;
1194
+ };
1195
+ uart6_rtsn: uart6-rtsn {
1196
+ rockchip,pins =
1197
+ /* uart6_rtsn */
1198
+ <3 RK_PA5 4 &pcfg_pull_none>;
1199
+ };
1200
+ };
1201
+
1202
+ uart7 {
1203
+ uart7m0_xfer: uart7m0-xfer {
1204
+ rockchip,pins =
1205
+ /* uart7_rx_m0 */
1206
+ <3 RK_PB3 4 &pcfg_pull_up>,
1207
+ /* uart7_tx_m0 */
1208
+ <3 RK_PB2 4 &pcfg_pull_up>;
1209
+ };
1210
+
1211
+ uart7m0_ctsn: uart7m0-ctsn {
1212
+ rockchip,pins =
1213
+ /* uart7m0_ctsn */
1214
+ <3 RK_PB0 4 &pcfg_pull_none>;
1215
+ };
1216
+ uart7m0_rtsn: uart7m0-rtsn {
1217
+ rockchip,pins =
1218
+ /* uart7m0_rtsn */
1219
+ <3 RK_PB1 4 &pcfg_pull_none>;
1220
+ };
1221
+
1222
+ uart7m1_xfer: uart7m1-xfer {
1223
+ rockchip,pins =
1224
+ /* uart7_rx_m1 */
1225
+ <1 RK_PB3 4 &pcfg_pull_up>,
1226
+ /* uart7_tx_m1 */
1227
+ <1 RK_PB2 4 &pcfg_pull_up>;
1228
+ };
1229
+
1230
+ uart7m1_ctsn: uart7m1-ctsn {
1231
+ rockchip,pins =
1232
+ /* uart7m1_ctsn */
1233
+ <1 RK_PB0 4 &pcfg_pull_none>;
1234
+ };
1235
+ uart7m1_rtsn: uart7m1-rtsn {
1236
+ rockchip,pins =
1237
+ /* uart7m1_rtsn */
1238
+ <1 RK_PB1 4 &pcfg_pull_none>;
1239
+ };
1240
+ };
1241
+};
u-boot/arch/arm/dts/rk3528-u-boot.dtsi
....@@ -0,0 +1,206 @@
1
+/*
2
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+
7
+/ {
8
+ aliases {
9
+ mmc0 = &sdhci;
10
+ mmc1 = &sdmmc;
11
+ };
12
+
13
+ chosen {
14
+ stdout-path = &uart2;
15
+ u-boot,spl-boot-order = &sdmmc, &sdhci, &spi_nand, &spi_nor;
16
+ };
17
+
18
+ secure-otp@ffcd0000 {
19
+ compatible = "rockchip,rk3528-secure-otp";
20
+ reg = <0x0 0xffcd0000 0x0 0x4000>;
21
+ secure_conf = <0xff4500c0>;
22
+ mask_addr = <0x0>;
23
+ cru_rst_addr = <0xff4a8080>;
24
+ u-boot,dm-spl;
25
+ status = "okay";
26
+ };
27
+
28
+};
29
+
30
+&grf {
31
+ u-boot,dm-spl;
32
+ status = "okay";
33
+};
34
+
35
+&ioc_grf {
36
+ u-boot,dm-spl;
37
+ status = "okay";
38
+};
39
+
40
+&cru {
41
+ /delete-property/ assigned-clocks;
42
+ /delete-property/ assigned-clock-rates;
43
+ u-boot,dm-spl;
44
+ status = "okay";
45
+};
46
+
47
+&crypto {
48
+ u-boot,dm-spl;
49
+ status = "okay";
50
+};
51
+
52
+&rng {
53
+ u-boot,dm-pre-reloc;
54
+ status = "okay";
55
+};
56
+
57
+&psci {
58
+ u-boot,dm-pre-reloc;
59
+ status = "okay";
60
+};
61
+
62
+&uart2 {
63
+ clock-frequency = <24000000>;
64
+ u-boot,dm-spl;
65
+ status = "okay";
66
+};
67
+
68
+&sfc {
69
+ u-boot,dm-spl;
70
+ /delete-property/ pinctrl-names;
71
+ /delete-property/ pinctrl-0;
72
+ /delete-property/ assigned-clocks;
73
+ /delete-property/ assigned-clock-rates;
74
+ status = "okay";
75
+
76
+ #address-cells = <1>;
77
+ #size-cells = <0>;
78
+ spi_nand: flash@0 {
79
+ u-boot,dm-spl;
80
+ compatible = "spi-nand";
81
+ reg = <0>;
82
+ spi-tx-bus-width = <1>;
83
+ spi-rx-bus-width = <4>;
84
+ spi-max-frequency = <75000000>;
85
+ };
86
+
87
+ spi_nor: flash@1 {
88
+ u-boot,dm-spl;
89
+ compatible = "jedec,spi-nor";
90
+ label = "sfc_nor";
91
+ reg = <0>;
92
+ spi-tx-bus-width = <1>;
93
+ spi-rx-bus-width = <4>;
94
+ spi-max-frequency = <100000000>;
95
+ };
96
+};
97
+
98
+&sdhci {
99
+ bus-width = <8>;
100
+ u-boot,dm-spl;
101
+ /delete-property/ assigned-clocks;
102
+ /delete-property/ assigned-clock-rates;
103
+ /delete-property/ pinctrl-names;
104
+ /delete-property/ pinctrl-0;
105
+ mmc-hs400-1_8v;
106
+ mmc-hs400-enhanced-strobe;
107
+ fixed-emmc-driver-type = <1>;
108
+ status = "okay";
109
+};
110
+
111
+&sdmmc {
112
+ u-boot,dm-spl;
113
+ status = "okay";
114
+};
115
+
116
+&saradc {
117
+ u-boot,dm-pre-reloc;
118
+ status = "okay";
119
+};
120
+
121
+&u2phy_otg {
122
+ u-boot,dm-pre-reloc;
123
+ status = "okay";
124
+};
125
+
126
+&usb2phy {
127
+ u-boot,dm-pre-reloc;
128
+ status = "okay";
129
+};
130
+
131
+&firmware {
132
+ u-boot,dm-spl;
133
+};
134
+
135
+&scmi {
136
+ u-boot,dm-spl;
137
+};
138
+
139
+&scmi_clk {
140
+ u-boot,dm-spl;
141
+};
142
+
143
+&scmi_shmem {
144
+ u-boot,dm-spl;
145
+};
146
+
147
+&pinctrl {
148
+ u-boot,dm-spl;
149
+ status = "okay";
150
+};
151
+
152
+&gpio0 {
153
+ u-boot,dm-spl;
154
+};
155
+
156
+&gpio1 {
157
+ u-boot,dm-spl;
158
+};
159
+
160
+&gpio2 {
161
+ u-boot,dm-spl;
162
+};
163
+
164
+&pcfg_pull_none_drv_level_1 {
165
+ u-boot,dm-spl;
166
+};
167
+
168
+&pcfg_pull_none_drv_level_2 {
169
+ u-boot,dm-spl;
170
+};
171
+
172
+&pcfg_pull_up_drv_level_1 {
173
+ u-boot,dm-spl;
174
+};
175
+
176
+&pcfg_pull_up_drv_level_2 {
177
+ u-boot,dm-spl;
178
+};
179
+
180
+&pcfg_pull_up {
181
+ u-boot,dm-spl;
182
+};
183
+
184
+&pcfg_pull_none {
185
+ u-boot,dm-spl;
186
+};
187
+
188
+&sdmmc_pins {
189
+ u-boot,dm-spl;
190
+};
191
+
192
+&sdmmc_bus4 {
193
+ u-boot,dm-spl;
194
+};
195
+
196
+&sdmmc_clk {
197
+ u-boot,dm-spl;
198
+};
199
+
200
+&sdmmc_cmd {
201
+ u-boot,dm-spl;
202
+};
203
+
204
+&sdmmc_det {
205
+ u-boot,dm-spl;
206
+};
u-boot/arch/arm/dts/rk3528.dtsi
....@@ -0,0 +1,2184 @@
1
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+/*
3
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4
+ */
5
+
6
+#include <dt-bindings/clock/rk3528-cru.h>
7
+#include <dt-bindings/gpio/gpio.h>
8
+#include <dt-bindings/interrupt-controller/arm-gic.h>
9
+#include <dt-bindings/interrupt-controller/irq.h>
10
+#include <dt-bindings/phy/phy.h>
11
+#include <dt-bindings/pinctrl/rockchip.h>
12
+#include <dt-bindings/power/rk3528-power.h>
13
+#include <dt-bindings/soc/rockchip,boot-mode.h>
14
+#include <dt-bindings/soc/rockchip-system-status.h>
15
+#include <dt-bindings/suspend/rockchip-rk3528.h>
16
+#include <dt-bindings/thermal/thermal.h>
17
+#include <dt-bindings/display/rockchip-tve.h>
18
+
19
+/ {
20
+ compatible = "rockchip,rk3528";
21
+
22
+ interrupt-parent = <&gic>;
23
+ #address-cells = <2>;
24
+ #size-cells = <2>;
25
+
26
+ aliases {
27
+ ethernet0 = &gmac0;
28
+ ethernet1 = &gmac1;
29
+ gpio0 = &gpio0;
30
+ gpio1 = &gpio1;
31
+ gpio2 = &gpio2;
32
+ gpio3 = &gpio3;
33
+ gpio4 = &gpio4;
34
+ i2c0 = &i2c0;
35
+ i2c1 = &i2c1;
36
+ i2c2 = &i2c2;
37
+ i2c3 = &i2c3;
38
+ i2c4 = &i2c4;
39
+ i2c5 = &i2c5;
40
+ i2c6 = &i2c6;
41
+ i2c7 = &i2c7;
42
+ serial0 = &uart0;
43
+ serial1 = &uart1;
44
+ serial2 = &uart2;
45
+ serial3 = &uart3;
46
+ serial4 = &uart4;
47
+ serial5 = &uart5;
48
+ serial6 = &uart6;
49
+ serial7 = &uart7;
50
+ spi0 = &spi0;
51
+ spi1 = &spi1;
52
+ spi2 = &sfc;
53
+ };
54
+
55
+ cpus {
56
+ #address-cells = <2>;
57
+ #size-cells = <0>;
58
+
59
+ cpu-map {
60
+ cluster0 {
61
+ core0 {
62
+ cpu = <&cpu0>;
63
+ };
64
+ core1 {
65
+ cpu = <&cpu1>;
66
+ };
67
+ core2 {
68
+ cpu = <&cpu2>;
69
+ };
70
+ core3 {
71
+ cpu = <&cpu3>;
72
+ };
73
+ };
74
+ };
75
+
76
+ cpu0: cpu@0 {
77
+ device_type = "cpu";
78
+ compatible = "arm,cortex-a53";
79
+ reg = <0x0 0x0>;
80
+ enable-method = "psci";
81
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
82
+ operating-points-v2 = <&cpu0_opp_table>;
83
+ cpu-idle-states = <&CPU_SLEEP0>;
84
+ };
85
+
86
+ cpu1: cpu@1 {
87
+ device_type = "cpu";
88
+ compatible = "arm,cortex-a53";
89
+ reg = <0x0 0x1>;
90
+ enable-method = "psci";
91
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
92
+ operating-points-v2 = <&cpu0_opp_table>;
93
+ cpu-idle-states = <&CPU_SLEEP0>;
94
+ };
95
+
96
+ cpu2: cpu@2 {
97
+ device_type = "cpu";
98
+ compatible = "arm,cortex-a53";
99
+ reg = <0x0 0x2>;
100
+ enable-method = "psci";
101
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
102
+ operating-points-v2 = <&cpu0_opp_table>;
103
+ cpu-idle-states = <&CPU_SLEEP1>;
104
+ };
105
+
106
+ cpu3: cpu@3 {
107
+ device_type = "cpu";
108
+ compatible = "arm,cortex-a53";
109
+ reg = <0x0 0x3>;
110
+ enable-method = "psci";
111
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
112
+ operating-points-v2 = <&cpu0_opp_table>;
113
+ cpu-idle-states = <&CPU_SLEEP1>;
114
+ };
115
+
116
+ idle-states {
117
+ entry-method = "psci";
118
+
119
+ CPU_SLEEP0: cpu-sleep0 {
120
+ compatible = "arm,idle-state";
121
+ local-timer-stop;
122
+ arm,psci-suspend-param = <0x0010000>;
123
+ entry-latency-us = <120>;
124
+ exit-latency-us = <250>;
125
+ min-residency-us = <900>;
126
+ status = "disabled";
127
+ };
128
+
129
+ CPU_SLEEP1: cpu-sleep {
130
+ compatible = "arm,idle-state";
131
+ local-timer-stop;
132
+ arm,psci-suspend-param = <0x0010000>;
133
+ entry-latency-us = <120>;
134
+ exit-latency-us = <250>;
135
+ min-residency-us = <900>;
136
+ status = "okay";
137
+ };
138
+ };
139
+ };
140
+
141
+ cpu0_opp_table: cpu0-opp-table {
142
+ compatible = "operating-points-v2";
143
+ opp-shared;
144
+
145
+ nvmem-cells = <&cpu_leakage>;
146
+ nvmem-cell-names = "leakage";
147
+
148
+ rockchip,pvtm-voltage-sel = <
149
+ 0 1310 0
150
+ 1311 1340 1
151
+ 1341 1370 2
152
+ 1371 1400 3
153
+ 1401 1430 4
154
+ 1431 1460 5
155
+ 1461 9999 6
156
+ >;
157
+ rockchip,pvtm-pvtpll;
158
+ rockchip,pvtm-offset = <0x18>;
159
+ rockchip,pvtm-sample-time = <1100>;
160
+ rockchip,pvtm-freq = <1416000>;
161
+ rockchip,pvtm-volt = <900000>;
162
+ rockchip,pvtm-ref-temp = <40>;
163
+ rockchip,pvtm-temp-prop = <0 0>;
164
+ rockchip,pvtm-thermal-zone = "soc-thermal";
165
+ rockchip,grf = <&grf>;
166
+
167
+ opp-408000000 {
168
+ opp-hz = /bits/ 64 <408000000>;
169
+ opp-microvolt = <825000 825000 1100000>;
170
+ clock-latency-ns = <40000>;
171
+ opp-suspend;
172
+ };
173
+ opp-600000000 {
174
+ opp-hz = /bits/ 64 <600000000>;
175
+ opp-microvolt = <825000 825000 1100000>;
176
+ clock-latency-ns = <40000>;
177
+ };
178
+ opp-816000000 {
179
+ opp-hz = /bits/ 64 <816000000>;
180
+ opp-microvolt = <825000 825000 1100000>;
181
+ clock-latency-ns = <40000>;
182
+ };
183
+ opp-1008000000 {
184
+ opp-hz = /bits/ 64 <1008000000>;
185
+ opp-microvolt = <825000 825000 1100000>;
186
+ clock-latency-ns = <40000>;
187
+ };
188
+ opp-1200000000 {
189
+ opp-hz = /bits/ 64 <1200000000>;
190
+ opp-microvolt = <875000 875000 1100000>;
191
+ opp-microvolt-L1 = <862500 862500 1100000>;
192
+ opp-microvolt-L2 = <850000 850000 1100000>;
193
+ opp-microvolt-L3 = <837500 837500 1100000>;
194
+ opp-microvolt-L4 = <837500 837500 1100000>;
195
+ opp-microvolt-L5 = <837500 837500 1100000>;
196
+ opp-microvolt-L6 = <825000 825000 1100000>;
197
+ clock-latency-ns = <40000>;
198
+ };
199
+ opp-1416000000 {
200
+ opp-hz = /bits/ 64 <1416000000>;
201
+ opp-microvolt = <937500 937500 1100000>;
202
+ opp-microvolt-L1 = <925000 925000 1100000>;
203
+ opp-microvolt-L2 = <912500 912500 1100000>;
204
+ opp-microvolt-L3 = <900000 900000 1100000>;
205
+ opp-microvolt-L4 = <900000 900000 1100000>;
206
+ opp-microvolt-L5 = <900000 900000 1100000>;
207
+ opp-microvolt-L6 = <887500 887500 1100000>;
208
+ clock-latency-ns = <40000>;
209
+ };
210
+ opp-1608000000 {
211
+ opp-hz = /bits/ 64 <1608000000>;
212
+ opp-microvolt = <1012500 1012500 1100000>;
213
+ opp-microvolt-L1 = <1000000 1000000 1100000>;
214
+ opp-microvolt-L2 = <987500 987500 1100000>;
215
+ opp-microvolt-L3 = <975000 975000 1100000>;
216
+ opp-microvolt-L4 = <962500 962500 1100000>;
217
+ opp-microvolt-L5 = <950000 950000 1100000>;
218
+ opp-microvolt-L6 = <937500 937500 1100000>;
219
+ clock-latency-ns = <40000>;
220
+ };
221
+ opp-1800000000 {
222
+ opp-hz = /bits/ 64 <1800000000>;
223
+ opp-microvolt = <1062500 1062500 1100000>;
224
+ opp-microvolt-L1 = <1050000 1050000 1100000>;
225
+ opp-microvolt-L2 = <1037500 1037500 1100000>;
226
+ opp-microvolt-L3 = <1025000 1025000 1100000>;
227
+ opp-microvolt-L4 = <1012500 1012500 1100000>;
228
+ opp-microvolt-L5 = <1000000 1000000 1100000>;
229
+ opp-microvolt-L6 = <987500 987500 1100000>;
230
+ clock-latency-ns = <40000>;
231
+ };
232
+ opp-2016000000 {
233
+ opp-hz = /bits/ 64 <2016000000>;
234
+ opp-microvolt = <1100000 1100000 1100000>;
235
+ opp-microvolt-L1 = <1087500 1087500 1100000>;
236
+ opp-microvolt-L2 = <1075000 1075000 1100000>;
237
+ opp-microvolt-L3 = <1062500 1062500 1100000>;
238
+ opp-microvolt-L4 = <1050000 1050000 1100000>;
239
+ opp-microvolt-L5 = <1037500 1037500 1100000>;
240
+ opp-microvolt-L6 = <1025000 1025000 1100000>;
241
+ clock-latency-ns = <40000>;
242
+ };
243
+ };
244
+
245
+ arm-pmu {
246
+ compatible = "arm,cortex-a53-pmu";
247
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
248
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
249
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
250
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
251
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
252
+ };
253
+
254
+ cpuinfo {
255
+ compatible = "rockchip,cpuinfo";
256
+ nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
257
+ nvmem-cell-names = "id", "cpu-version", "cpu-code";
258
+ };
259
+
260
+ display_subsystem: display-subsystem {
261
+ compatible = "rockchip,display-subsystem";
262
+ ports = <&vop_out>;
263
+ status = "disabled";
264
+ };
265
+
266
+ firmware: firmware {
267
+ scmi: scmi {
268
+ compatible = "arm,scmi-smc";
269
+ shmem = <&scmi_shmem>;
270
+ arm,smc-id = <0x82000010>;
271
+ #address-cells = <1>;
272
+ #size-cells = <0>;
273
+
274
+ scmi_clk: protocol@14 {
275
+ reg = <0x14>;
276
+ #clock-cells = <1>;
277
+ };
278
+ };
279
+ };
280
+
281
+ mpp_srv: mpp-srv {
282
+ compatible = "rockchip,mpp-service";
283
+ rockchip,taskqueue-count = <5>;
284
+ rockchip,resetgroup-count = <5>;
285
+ status = "disabled";
286
+ };
287
+
288
+ psci: psci {
289
+ compatible = "arm,psci-1.0";
290
+ method = "smc";
291
+ };
292
+
293
+ rockchip_suspend: rockchip-suspend {
294
+ compatible = "rockchip,pm-rk3528";
295
+ status = "disabled";
296
+ rockchip,sleep-debug-en = <0>;
297
+ rockchip,sleep-mode-config = <
298
+ (0
299
+ | RKPM_SLP_ARMPD
300
+ )
301
+ >;
302
+ rockchip,wakeup-config = <
303
+ (0
304
+ | RKPM_CPU0_WKUP_EN
305
+ | RKPM_GPIO_WKUP_EN
306
+ )
307
+ >;
308
+ };
309
+
310
+ rockchip_system_monitor: rockchip-system-monitor {
311
+ compatible = "rockchip,system-monitor";
312
+
313
+ rockchip,thermal-zone = "soc-thermal";
314
+ };
315
+
316
+ thermal_zones: thermal-zones {
317
+ soc_thermal: soc-thermal {
318
+ polling-delay-passive = <20>; /* milliseconds */
319
+ polling-delay = <1000>; /* milliseconds */
320
+
321
+ thermal-sensors = <&tsadc 0>;
322
+ trips {
323
+ soc_crit: soc-crit {
324
+ /* millicelsius */
325
+ temperature = <115000>;
326
+ /* millicelsius */
327
+ hysteresis = <2000>;
328
+ type = "critical";
329
+ };
330
+ };
331
+ };
332
+ };
333
+
334
+ timer {
335
+ compatible = "arm,armv8-timer";
336
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
337
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
338
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
339
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
340
+ };
341
+
342
+ xin24m: xin24m {
343
+ compatible = "fixed-clock";
344
+ #clock-cells = <0>;
345
+ clock-frequency = <24000000>;
346
+ clock-output-names = "xin24m";
347
+ };
348
+
349
+ scmi_shmem: scmi-shmem@10f000 {
350
+ compatible = "arm,scmi-shmem";
351
+ reg = <0x0 0x0010f000 0x0 0x100>;
352
+ };
353
+
354
+ pcie2x1: pcie@fe4f0000 {
355
+ compatible = "rockchip,rk3528-pcie", "snps,dw-pcie";
356
+ #address-cells = <3>;
357
+ #size-cells = <2>;
358
+ bus-range = <0x0 0xff>;
359
+ clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
360
+ <&cru HCLK_PCIE_DBI>, <&cru PCLK_CRU_PCIE>,
361
+ <&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE>,
362
+ <&cru PCLK_PCIE_PHY>;
363
+ clock-names = "aclk", "hclk_slv",
364
+ "hclk_dbi", "pclk_cru",
365
+ "aux", "pclk",
366
+ "pipe";
367
+ device_type = "pci";
368
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
369
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
370
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
371
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
372
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
373
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
374
+ interrupt-names = "msi", "pmc", "sys", "legacy", "msg", "err";
375
+ #interrupt-cells = <1>;
376
+ interrupt-map-mask = <0 0 0 7>;
377
+ interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
378
+ <0 0 0 2 &pcie2x1_intc 1>,
379
+ <0 0 0 3 &pcie2x1_intc 2>,
380
+ <0 0 0 4 &pcie2x1_intc 3>;
381
+ linux,pci-domain = <0>;
382
+ num-ib-windows = <8>;
383
+ num-ob-windows = <8>;
384
+ num-viewport = <4>;
385
+ max-link-speed = <2>;
386
+ num-lanes = <1>;
387
+ phys = <&combphy_pu PHY_TYPE_PCIE>;
388
+ phy-names = "pcie-phy";
389
+ ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000
390
+ 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
391
+ 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
392
+ 0xc3000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>;
393
+ reg = <0x0 0xfe4f0000 0x0 0x10000>,
394
+ <0x1 0x40000000 0x0 0x400000>;
395
+ reg-names = "pcie-apb", "pcie-dbi";
396
+ resets = <&cru SRST_RESETN_PCIE_POWER_UP>, <&cru SRST_PRESETN_PCIE>,
397
+ <&cru SRST_PRESETN_CRU_PCIE>;
398
+ reset-names = "pcie", "periph", "preset_cru";
399
+ status = "disabled";
400
+
401
+ pcie2x1_intc: legacy-interrupt-controller {
402
+ interrupt-controller;
403
+ #address-cells = <0>;
404
+ #interrupt-cells = <1>;
405
+ interrupt-parent = <&gic>;
406
+ interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>;
407
+ };
408
+ };
409
+
410
+ usbdrd30: usbdrd {
411
+ compatible = "rockchip,rk3528-dwc3", "rockchip,rk3399-dwc3";
412
+ clocks = <&cru CLK_REF_USB3OTG>, <&cru CLK_SUSPEND_USB3OTG>,
413
+ <&cru ACLK_USB3OTG>;
414
+ clock-names = "ref_clk", "suspend_clk",
415
+ "bus_clk";
416
+ #address-cells = <2>;
417
+ #size-cells = <2>;
418
+ ranges;
419
+ status = "disabled";
420
+
421
+ usbdrd_dwc3: dwc3@fe500000 {
422
+ compatible = "snps,dwc3";
423
+ reg = <0x0 0xfe500000 0x0 0x400000>;
424
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
425
+ dr_mode = "otg";
426
+ phys = <&u2phy_otg>, <&combphy_pu PHY_TYPE_USB3>;
427
+ phy-names = "usb2-phy", "usb3-phy";
428
+ phy_type = "utmi_wide";
429
+ resets = <&cru SRST_ARESETN_USB3OTG>;
430
+ reset-names = "usb3-otg";
431
+ snps,dis_enblslpm_quirk;
432
+ snps,dis-u1u2-quirk;
433
+ snps,dis-u2-freeclk-exists-quirk;
434
+ snps,dis-del-phy-power-chg-quirk;
435
+ snps,dis-tx-ipgap-linecheck-quirk;
436
+ snps,xhci-trb-ent-quirk;
437
+ snps,dis_rxdet_inp3_quirk;
438
+ quirk-skip-phy-init;
439
+ status = "disabled";
440
+ };
441
+ };
442
+
443
+ gic: interrupt-controller@fed01000 {
444
+ compatible = "arm,gic-400";
445
+ #interrupt-cells = <3>;
446
+ #address-cells = <0>;
447
+ interrupt-controller;
448
+ reg = <0x0 0xfed01000 0 0x1000>,
449
+ <0x0 0xfed02000 0 0x2000>,
450
+ <0x0 0xfed04000 0 0x2000>,
451
+ <0x0 0xfed06000 0 0x2000>;
452
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
453
+ };
454
+
455
+ usb_host0_ehci: usb@ff100000 {
456
+ compatible = "generic-ehci";
457
+ reg = <0x0 0xff100000 0x0 0x40000>;
458
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
459
+ clocks = <&cru HCLK_USBHOST>,
460
+ <&cru HCLK_USBHOST_ARB>,
461
+ <&usb2phy>;
462
+ clock-names = "usbhost", "arbiter", "utmi";
463
+ phys = <&u2phy_host>;
464
+ phy-names = "usb2-phy";
465
+ status = "disabled";
466
+ };
467
+
468
+ usb_host0_ohci: usb@ff140000 {
469
+ compatible = "generic-ohci";
470
+ reg = <0x0 0xff140000 0x0 0x40000>;
471
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
472
+ clocks = <&cru HCLK_USBHOST>,
473
+ <&cru HCLK_USBHOST_ARB>,
474
+ <&usb2phy>;
475
+ clock-names = "usbhost", "arbiter", "utmi";
476
+ phys = <&u2phy_host>;
477
+ phy-names = "usb2-phy";
478
+ status = "disabled";
479
+ };
480
+
481
+ debug: debug@ff190000 {
482
+ compatible = "rockchip,debug";
483
+ reg = <0x0 0xff190000 0x0 0x1000>,
484
+ <0x0 0xff192000 0x0 0x1000>,
485
+ <0x0 0xff194000 0x0 0x1000>,
486
+ <0x0 0xff196000 0x0 0x1000>;
487
+ };
488
+
489
+ qos_crypto_a: qos@ff200000 {
490
+ compatible = "syscon";
491
+ reg = <0x0 0xff200000 0x0 0x20>;
492
+ };
493
+
494
+ qos_crypto_p: qos@ff200080 {
495
+ compatible = "syscon";
496
+ reg = <0x0 0xff200080 0x0 0x20>;
497
+ };
498
+
499
+ qos_dcf: qos@ff200100 {
500
+ compatible = "syscon";
501
+ reg = <0x0 0xff200100 0x0 0x20>;
502
+ };
503
+
504
+ qos_dft2apb: qos@ff200200 {
505
+ compatible = "syscon";
506
+ reg = <0x0 0xff200200 0x0 0x20>;
507
+ };
508
+
509
+ qos_dma2ddr: qos@ff200280 {
510
+ compatible = "syscon";
511
+ reg = <0x0 0xff200280 0x0 0x20>;
512
+ };
513
+
514
+ qos_dmac: qos@ff200300 {
515
+ compatible = "syscon";
516
+ reg = <0x0 0xff200300 0x0 0x20>;
517
+ };
518
+
519
+ qos_keyreader: qos@ff200380 {
520
+ compatible = "syscon";
521
+ reg = <0x0 0xff200380 0x0 0x20>;
522
+ };
523
+
524
+ qos_cpu: qos@ff210000 {
525
+ compatible = "syscon";
526
+ reg = <0x0 0xff210000 0x0 0x20>;
527
+ };
528
+
529
+ qos_debug: qos@ff210080 {
530
+ compatible = "syscon";
531
+ reg = <0x0 0xff210080 0x0 0x20>;
532
+ };
533
+
534
+ qos_gpu_m0: qos@ff220000 {
535
+ compatible = "syscon";
536
+ reg = <0x0 0xff220000 0x0 0x20>;
537
+ };
538
+
539
+ qos_gpu_m1: qos@ff220080 {
540
+ compatible = "syscon";
541
+ reg = <0x0 0xff220080 0x0 0x20>;
542
+ };
543
+
544
+ qos_pmu_mcu: qos@ff240000 {
545
+ compatible = "syscon";
546
+ reg = <0x0 0xff240000 0x0 0x20>;
547
+ };
548
+
549
+ qos_rkvdec: qos@ff250000 {
550
+ compatible = "syscon";
551
+ reg = <0x0 0xff250000 0x0 0x20>;
552
+ };
553
+
554
+ qos_rkvenc: qos@ff260000 {
555
+ compatible = "syscon";
556
+ reg = <0x0 0xff260000 0x0 0x20>;
557
+ };
558
+
559
+ qos_gmac0: qos@ff270000 {
560
+ compatible = "syscon";
561
+ reg = <0x0 0xff270000 0x0 0x20>;
562
+ };
563
+
564
+ qos_hdcp: qos@ff270080 {
565
+ compatible = "syscon";
566
+ reg = <0x0 0xff270080 0x0 0x20>;
567
+ };
568
+
569
+ qos_jpegdec: qos@ff270100 {
570
+ compatible = "syscon";
571
+ reg = <0x0 0xff270100 0x0 0x20>;
572
+ };
573
+
574
+ qos_rga2_m0ro: qos@ff270200 {
575
+ compatible = "syscon";
576
+ reg = <0x0 0xff270200 0x0 0x20>;
577
+ };
578
+
579
+ qos_rga2_m0wo: qos@ff270280 {
580
+ compatible = "syscon";
581
+ reg = <0x0 0xff270280 0x0 0x20>;
582
+ };
583
+
584
+ qos_sdmmc0: qos@ff270300 {
585
+ compatible = "syscon";
586
+ reg = <0x0 0xff270300 0x0 0x20>;
587
+ };
588
+
589
+ qos_usb2host: qos@ff270380 {
590
+ compatible = "syscon";
591
+ reg = <0x0 0xff270380 0x0 0x20>;
592
+ };
593
+
594
+ qos_vdpp: qos@ff270480 {
595
+ compatible = "syscon";
596
+ reg = <0x0 0xff270480 0x0 0x20>;
597
+ };
598
+
599
+ qos_vop: qos@ff270500 {
600
+ compatible = "syscon";
601
+ reg = <0x0 0xff270500 0x0 0x20>;
602
+ };
603
+
604
+ qos_emmc: qos@ff280000 {
605
+ compatible = "syscon";
606
+ reg = <0x0 0xff280000 0x0 0x20>;
607
+ };
608
+
609
+ qos_fspi: qos@ff280080 {
610
+ compatible = "syscon";
611
+ reg = <0x0 0xff280080 0x0 0x20>;
612
+ };
613
+
614
+ qos_gmac1: qos@ff280100 {
615
+ compatible = "syscon";
616
+ reg = <0x0 0xff280100 0x0 0x20>;
617
+ };
618
+
619
+ qos_pcie: qos@ff280180 {
620
+ compatible = "syscon";
621
+ reg = <0x0 0xff280180 0x0 0x20>;
622
+ };
623
+
624
+ qos_sdio0: qos@ff280200 {
625
+ compatible = "syscon";
626
+ reg = <0x0 0xff280200 0x0 0x20>;
627
+ };
628
+
629
+ qos_sdio1: qos@ff280280 {
630
+ compatible = "syscon";
631
+ reg = <0x0 0xff280280 0x0 0x20>;
632
+ };
633
+
634
+ qos_tsp: qos@ff280300 {
635
+ compatible = "syscon";
636
+ reg = <0x0 0xff280300 0x0 0x20>;
637
+ };
638
+
639
+ qos_usb3otg: qos@ff280380 {
640
+ compatible = "syscon";
641
+ reg = <0x0 0xff280380 0x0 0x20>;
642
+ };
643
+
644
+ qos_vpu: qos@ff280400 {
645
+ compatible = "syscon";
646
+ reg = <0x0 0xff280400 0x0 0x20>;
647
+ };
648
+
649
+ /*
650
+ * Merge all GRF, each independent GRF offset is shown as bellow:
651
+ * CORE_GRF: 0xff300000
652
+ * GPU_GRF: 0xff310000
653
+ * RKVENC_GRF: 0xff320000
654
+ * DDR_GRF: 0xff330000
655
+ * VPU_GRF: 0xff340000
656
+ * COMBO_PIPE_PHY_GRF: 0xff348000
657
+ * RKVDEC_GRF: 0xff350000
658
+ * VO_GRF: 0xff360000
659
+ * PMU_GRF: 0xff370000
660
+ * SYS_GRF: 0xff380000
661
+ */
662
+ grf: syscon@ff300000 {
663
+ compatible = "rockchip,rk3528-grf", "syscon", "simple-mfd";
664
+ reg = <0x0 0xff300000 0x0 0x90000>;
665
+
666
+ grf_cru: grf-clock-controller {
667
+ compatible = "rockchip,rk3528-grf-cru";
668
+ #clock-cells = <1>;
669
+ };
670
+
671
+ reboot_mode: reboot-mode {
672
+ compatible = "syscon-reboot-mode";
673
+ offset = <0x70200>;
674
+ mode-bootloader = <BOOT_BL_DOWNLOAD>;
675
+ mode-charge = <BOOT_CHARGING>;
676
+ mode-fastboot = <BOOT_FASTBOOT>;
677
+ mode-loader = <BOOT_BL_DOWNLOAD>;
678
+ mode-normal = <BOOT_NORMAL>;
679
+ mode-recovery = <BOOT_RECOVERY>;
680
+ mode-ums = <BOOT_UMS>;
681
+ mode-panic = <BOOT_PANIC>;
682
+ mode-watchdog = <BOOT_WATCHDOG>;
683
+ };
684
+ };
685
+
686
+ cru: clock-controller@ff4a0000 {
687
+ compatible = "rockchip,rk3528-cru";
688
+ reg = <0x0 0xff4a0000 0x0 0x30000>;
689
+ rockchip,grf = <&grf>;
690
+ #clock-cells = <1>;
691
+ #reset-cells = <1>;
692
+
693
+ assigned-clocks =
694
+ <&cru XIN_OSC0_DIV>,
695
+ <&cru PLL_GPLL>,
696
+ <&cru PLL_PPLL>,
697
+ <&cru PLL_CPLL>,
698
+ <&cru ARMCLK>,
699
+ <&cru CLK_MATRIX_250M_SRC>,
700
+ <&cru CLK_MATRIX_500M_SRC>,
701
+ <&cru CLK_MATRIX_50M_SRC>,
702
+ <&cru CLK_MATRIX_100M_SRC>,
703
+ <&cru CLK_MATRIX_150M_SRC>,
704
+ <&cru CLK_MATRIX_200M_SRC>,
705
+ <&cru CLK_MATRIX_300M_SRC>,
706
+ <&cru CLK_MATRIX_339M_SRC>,
707
+ <&cru CLK_MATRIX_400M_SRC>,
708
+ <&cru CLK_MATRIX_600M_SRC>,
709
+ <&cru CLK_PPLL_50M_MATRIX>,
710
+ <&cru CLK_PPLL_100M_MATRIX>,
711
+ <&cru CLK_PPLL_125M_MATRIX>,
712
+ <&cru ACLK_BUS_VOPGL_ROOT>;
713
+
714
+ assigned-clock-rates =
715
+ <32768>,
716
+ <1188000000>,
717
+ <1000000000>,
718
+ <996000000>,
719
+ <408000000>,
720
+ <250000000>,
721
+ <500000000>,
722
+ <50000000>,
723
+ <100000000>,
724
+ <150000000>,
725
+ <200000000>,
726
+ <300000000>,
727
+ <340000000>,
728
+ <400000000>,
729
+ <600000000>,
730
+ <50000000>,
731
+ <100000000>,
732
+ <125000000>,
733
+ <500000000>;
734
+ };
735
+
736
+ ioc_grf: syscon@ff540000 {
737
+ compatible = "rockchip,rk3528-ioc-grf", "syscon";
738
+ reg = <0x0 0xff540000 0x0 0x40000>;
739
+ };
740
+
741
+ pmu: power-management@ff600000 {
742
+ compatible = "rockchip,rk3528-pmu", "syscon", "simple-mfd";
743
+ reg = <0x0 0xff600000 0x0 0x2000>;
744
+
745
+ power: power-controller {
746
+ compatible = "rockchip,rk3528-power-controller";
747
+ #power-domain-cells = <1>;
748
+ #address-cells = <1>;
749
+ #size-cells = <0>;
750
+ status = "okay";
751
+
752
+ /* These power domains are grouped by VD_GPU */
753
+ pd_gpu@RK3528_PD_GPU {
754
+ reg = <RK3528_PD_GPU>;
755
+ clocks = <&cru ACLK_GPU_MALI>,
756
+ <&cru PCLK_GPU_ROOT>;
757
+ pm_qos = <&qos_gpu_m0>,
758
+ <&qos_gpu_m1>;
759
+ };
760
+ /* These power domains are grouped by VD_LOGIC */
761
+ pd_rkvdec@RK3528_PD_RKVDEC {
762
+ reg = <RK3528_PD_RKVDEC>;
763
+ };
764
+ pd_rkvenc@RK3528_PD_RKVENC {
765
+ reg = <RK3528_PD_RKVENC>;
766
+ };
767
+ pd_vo@RK3528_PD_VO {
768
+ reg = <RK3528_PD_VO>;
769
+ };
770
+ pd_vpu@RK3528_PD_VPU {
771
+ reg = <RK3528_PD_VPU>;
772
+ };
773
+ };
774
+ };
775
+
776
+ mailbox: mailbox@ff630000 {
777
+ compatible = "rockchip,rk3528-mailbox",
778
+ "rockchip,rk3368-mailbox";
779
+ reg = <0x0 0xff630000 0x0 0x200>;
780
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
781
+ clocks = <&cru PCLK_PMU_MAILBOX>;
782
+ clock-names = "pclk_mailbox";
783
+ #mbox-cells = <1>;
784
+ status = "disabled";
785
+ };
786
+
787
+ gpu: gpu@ff700000 {
788
+ compatible = "arm,mali-450";
789
+ reg = <0x0 0xff700000 0x0 0x40000>;
790
+
791
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
792
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
793
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
794
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
795
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
796
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
797
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
798
+ interrupt-names = "Mali_GP_IRQ",
799
+ "Mali_GP_MMU_IRQ",
800
+ "IRQPP",
801
+ "Mali_PP0_IRQ",
802
+ "Mali_PP0_MMU_IRQ",
803
+ "Mali_PP1_IRQ",
804
+ "Mali_PP1_MMU_IRQ";
805
+ clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru ACLK_GPU_MALI>,
806
+ <&cru PCLK_GPU_ROOT>;
807
+ clock-names = "clk_mali", "aclk_gpu_mali", "pclk_gpu";
808
+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
809
+ assigned-clock-rates = <300000000>;
810
+ power-domains = <&power RK3528_PD_GPU>;
811
+ operating-points-v2 = <&gpu_opp_table>;
812
+ status = "disabled";
813
+
814
+ gpu_power_model: power_model {
815
+ compatible = "arm,mali-simple-power-model";
816
+ voltage = <900>;
817
+ frequency = <500>;
818
+ static-power = <300>;
819
+ dynamic-power = <396>;
820
+ ts = <32000 4700 (-80) 2>;
821
+ thermal-zone = "soc-thermal";
822
+ };
823
+ };
824
+
825
+ gpu_opp_table: gpu-opp-table {
826
+ compatible = "operating-points-v2";
827
+
828
+ nvmem-cells = <&gpu_leakage>;
829
+ nvmem-cell-names = "leakage";
830
+
831
+ rockchip,pvtm-voltage-sel = <
832
+ 0 820 0
833
+ 821 840 1
834
+ 841 860 2
835
+ 861 880 3
836
+ 881 900 4
837
+ 901 9999 5
838
+ >;
839
+ rockchip,pvtm-pvtpll;
840
+ rockchip,pvtm-offset = <0x10018>;
841
+ rockchip,pvtm-sample-time = <1100>;
842
+ rockchip,pvtm-freq = <700000>;
843
+ rockchip,pvtm-volt = <900000>;
844
+ rockchip,pvtm-ref-temp = <40>;
845
+ rockchip,pvtm-temp-prop = <0 0>;
846
+ rockchip,pvtm-thermal-zone = "soc-thermal";
847
+ rockchip,grf = <&grf>;
848
+
849
+ opp-300000000 {
850
+ opp-hz = /bits/ 64 <300000000>;
851
+ opp-microvolt = <825000 825000 1000000>;
852
+ };
853
+ opp-500000000 {
854
+ opp-hz = /bits/ 64 <500000000>;
855
+ opp-microvolt = <825000 825000 1000000>;
856
+ };
857
+ opp-600000000 {
858
+ opp-hz = /bits/ 64 <600000000>;
859
+ opp-microvolt = <825000 825000 1000000>;
860
+ };
861
+ opp-700000000 {
862
+ opp-hz = /bits/ 64 <700000000>;
863
+ opp-microvolt = <825000 825000 1000000>;
864
+ opp-microvolt-L0 = <850000 850000 1000000>;
865
+ opp-microvolt-L1 = <837500 837500 1000000>;
866
+ clock-latency-ns = <40000>;
867
+ };
868
+ opp-800000000 {
869
+ opp-hz = /bits/ 64 <800000000>;
870
+ opp-microvolt = <900000 900000 1000000>;
871
+ opp-microvolt-L1 = <887500 887500 1000000>;
872
+ opp-microvolt-L2 = <875000 875000 1000000>;
873
+ opp-microvolt-L3 = <862500 862500 1000000>;
874
+ opp-microvolt-L4 = <850000 850000 1000000>;
875
+ opp-microvolt-L5 = <837500 837500 1000000>;
876
+ clock-latency-ns = <40000>;
877
+ };
878
+ };
879
+
880
+ rkvdec: rkvdec@ff740100 {
881
+ compatible = "rockchip,rkv-decoder-v2";
882
+ reg = <0x0 0xff740100 0x0 0x400>, <0x0 0xff740000 0x0 0x100>;
883
+ reg-names = "regs", "link";
884
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
885
+ interrupt-names = "irq_dec";
886
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>;
887
+ clock-names = "aclk_vcodec", "hclk_vcodec","clk_hevc_cabac";
888
+ rockchip,normal-rates = <340000000>, <0>, <600000000>;
889
+ assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>;
890
+ assigned-clock-rates = <340000000>, <600000000>;
891
+ resets = <&cru SRST_ARESETN_RKVDEC>, <&cru SRST_HRESETN_RKVDEC>,
892
+ <&cru SRST_RESETN_HEVC_CA_RKVDEC>;
893
+ reset-names = "video_a", "video_h", "video_hevc_cabac";
894
+ power-domains = <&power RK3528_PD_RKVDEC>;
895
+ iommus = <&rkvdec_mmu>;
896
+ rockchip,srv = <&mpp_srv>;
897
+ rockchip,taskqueue-node = <0>;
898
+ rockchip,resetgroup-node = <0>;
899
+ rockchip,task-capacity = <16>;
900
+ status = "disabled";
901
+ };
902
+
903
+ rkvdec_mmu: iommu@ff740800 {
904
+ compatible = "rockchip,iommu-v2";
905
+ reg = <0x0 0xff740800 0x0 0x40>, <0x0 0xff740900 0x0 0x40>;
906
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
907
+ interrupt-names = "rkvdec_mmu";
908
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>;
909
+ clock-names = "aclk", "iface", "clk_hevc_cabac";
910
+ power-domains = <&power RK3528_PD_RKVDEC>;
911
+ #iommu-cells = <0>;
912
+ status = "disabled";
913
+ };
914
+
915
+ rkvenc: rkvenc@ff780000 {
916
+ compatible = "rockchip,rkv-encoder-v2";
917
+ reg = <0x0 0xff780000 0x0 0x6000>;
918
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
919
+ interrupt-names = "irq_rkvenc";
920
+ clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_CORE_RKVENC>;
921
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
922
+ rockchip,normal-rates = <300000000>, <0>, <300000000>;
923
+ resets = <&cru SRST_ARESETN_RKVENC>, <&cru SRST_HRESETN_RKVENC>,
924
+ <&cru SRST_RESETN_CORE_RKVENC>;
925
+ reset-names = "video_a", "video_h", "video_core";
926
+ assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_CORE_RKVENC>;
927
+ assigned-clock-rates = <300000000>, <300000000>;
928
+ power-domains = <&power RK3528_PD_RKVENC>;
929
+ iommus = <&rkvenc_mmu>;
930
+ rockchip,srv = <&mpp_srv>;
931
+ rockchip,taskqueue-node = <1>;
932
+ rockchip,resetgroup-node = <1>;
933
+ status = "disabled";
934
+ };
935
+
936
+ rkvenc_mmu: iommu@ff78f000 {
937
+ compatible = "rockchip,iommu-v2";
938
+ reg = <0x0 0xff78f000 0x0 0x40>;
939
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
940
+ interrupt-names = "rkvenc_mmu";
941
+ clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>;
942
+ clock-names = "aclk", "iface";
943
+ power-domains = <&power RK3528_PD_RKVENC>;
944
+ #iommu-cells = <0>;
945
+ status = "disabled";
946
+ };
947
+
948
+ vdpu: vdpu@ff7c0400 {
949
+ compatible = "rockchip,vpu-decoder-v2";
950
+ reg = <0x0 0xff7c0400 0x0 0x400>;
951
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
952
+ interrupt-names = "irq_dec";
953
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
954
+ clock-names = "aclk_vcodec", "hclk_vcodec";
955
+ resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>;
956
+ reset-names = "shared_video_a", "shared_video_h";
957
+ power-domains = <&power RK3528_PD_VPU>;
958
+ iommus = <&vdpu_mmu>;
959
+ rockchip,srv = <&mpp_srv>;
960
+ rockchip,taskqueue-node = <2>;
961
+ rockchip,resetgroup-node = <2>;
962
+ status = "disabled";
963
+ };
964
+
965
+ vdpu_mmu: iommu@ff7c0800 {
966
+ compatible = "rockchip,iommu-v2";
967
+ reg = <0x0 0xff7c0800 0x0 0x40>;
968
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
969
+ interrupt-names = "vdpu_mmu";
970
+ clock-names = "aclk", "iface";
971
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
972
+ power-domains = <&power RK3528_PD_VPU>;
973
+ #iommu-cells = <0>;
974
+ status = "disabled";
975
+ };
976
+
977
+ avsd: avsd_plus@ff7c1000 {
978
+ compatible = "rockchip,avs-plus-decoder";
979
+ reg = <0x0 0xff7c1000 0x0 0x200>;
980
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
981
+ interrupt-names = "irq_dec";
982
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
983
+ clock-names = "aclk_vcodec", "hclk_vcodec";
984
+ resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>;
985
+ reset-names = "shared_video_a", "shared_video_h";
986
+ iommus = <&vdpu_mmu>;
987
+ power-domains = <&power RK3528_PD_VPU>;
988
+ rockchip,srv = <&mpp_srv>;
989
+ rockchip,taskqueue-node = <2>;
990
+ rockchip,resetgroup-node = <2>;
991
+ status = "disabled";
992
+ };
993
+
994
+ vop: vop@ff840000 {
995
+ compatible = "rockchip,rk3528-vop";
996
+ reg = <0x0 0xff840000 0x0 0x3000>,
997
+ <0x0 0xff845000 0x0 0x1000>,
998
+ <0x0 0xff846400 0x0 0x800>;
999
+ reg-names = "regs",
1000
+ "gamma_lut",
1001
+ "acm_regs";
1002
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1003
+ clocks = <&cru ACLK_VOP>,
1004
+ <&cru HCLK_VOP>,
1005
+ <&cru DCLK_VOP0>,
1006
+ <&cru DCLK_VOP1>;
1007
+ clock-names = "aclk_vop",
1008
+ "hclk_vop",
1009
+ "dclk_vp0",
1010
+ "dclk_vp1";
1011
+ assigned-clocks = <&cru DCLK_VOP0>;
1012
+ assigned-clock-parents = <&hdmiphy>;
1013
+ iommus = <&vop_mmu>;
1014
+ rockchip,grf = <&grf>;
1015
+ status = "disabled";
1016
+
1017
+ vop_out: ports {
1018
+ #address-cells = <1>;
1019
+ #size-cells = <0>;
1020
+
1021
+ port@0 {
1022
+ #address-cells = <1>;
1023
+ #size-cells = <0>;
1024
+ reg = <0>;
1025
+
1026
+ vp0_out_hdmi: endpoint@0 {
1027
+ reg = <0>;
1028
+ remote-endpoint = <&hdmi_in_vp0>;
1029
+ };
1030
+ };
1031
+
1032
+ port@1 {
1033
+ #address-cells = <1>;
1034
+ #size-cells = <0>;
1035
+ reg = <1>;
1036
+
1037
+ vp1_out_tve: endpoint@0 {
1038
+ reg = <0>;
1039
+ remote-endpoint = <&tve_in_vp1>;
1040
+ };
1041
+ };
1042
+ };
1043
+ };
1044
+
1045
+ vop_mmu: iommu@ff847e00 {
1046
+ compatible = "rockchip,iommu-v2";
1047
+ reg = <0x0 0xff847e00 0x0 0x100>;
1048
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1049
+ interrupt-names = "vop_mmu";
1050
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1051
+ clock-names = "aclk", "iface";
1052
+ #iommu-cells = <0>;
1053
+ rockchip,disable-device-link-resume;
1054
+ rockchip,shootdown-entire;
1055
+ status = "disabled";
1056
+ };
1057
+
1058
+ rga2: rga@ff850000 {
1059
+ compatible = "rockchip,rga2_core0";
1060
+ reg = <0x0 0xff850000 0x0 0x1000>;
1061
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1062
+ interrupt-names = "rga2_irq";
1063
+ clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>, <&cru CLK_CORE_RGA2E>;
1064
+ clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2";
1065
+ iommus = <&rga2_mmu>;
1066
+ status = "disabled";
1067
+ };
1068
+
1069
+ rga2_mmu: iommu@ff850f00 {
1070
+ compatible = "rockchip,iommu-v2";
1071
+ reg = <0x0 0xff850f00 0x0 0x100>;
1072
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1073
+ interrupt-names = "rga2_mmu";
1074
+ clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>;
1075
+ clock-names = "aclk", "iface";
1076
+ #iommu-cells = <0>;
1077
+ status = "disabled";
1078
+ };
1079
+
1080
+ iep: iep@ff860000 {
1081
+ compatible = "rockchip,iep-v2";
1082
+ reg = <0x0 0xff860000 0x0 0x500>;
1083
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1084
+ clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>;
1085
+ clock-names = "aclk", "hclk", "sclk";
1086
+ rockchip,normal-rates = <340000000>, <0>, <340000000>;
1087
+ assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>;
1088
+ assigned-clock-rates = <340000000>, <340000000>;
1089
+ resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>,
1090
+ <&cru SRST_RESETN_CORE_VDPP>;
1091
+ reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s";
1092
+ rockchip,srv = <&mpp_srv>;
1093
+ rockchip,taskqueue-node = <3>;
1094
+ rockchip,resetgroup-node = <3>;
1095
+ power-domains = <&power RK3528_PD_VO>;
1096
+ iommus = <&iep_mmu>;
1097
+ status = "disabled";
1098
+ };
1099
+
1100
+ iep_mmu: iommu@ff860800 {
1101
+ compatible = "rockchip,iommu-v2";
1102
+ reg = <0x0 0xff860800 0x0 0x100>;
1103
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1104
+ interrupt-names = "iep_mmu";
1105
+ clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>;
1106
+ clock-names = "aclk", "iface";
1107
+ #iommu-cells = <0>;
1108
+ power-domains = <&power RK3528_PD_VO>;
1109
+ status = "disabled";
1110
+ };
1111
+
1112
+ vdpp: vdpp@ff861000 {
1113
+ compatible = "rockchip,vdpp-v1";
1114
+ reg = <0x0 0xff861000 0x0 0x100>, <0x0 0xff862000 0x0 0x900>;
1115
+ reg-names = "vdpp_regs", "zme_regs";
1116
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1117
+ clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>;
1118
+ clock-names = "aclk", "hclk", "sclk";
1119
+ rockchip,normal-rates = <340000000>, <0>, <340000000>;
1120
+ assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>;
1121
+ assigned-clock-rates = <340000000>, <340000000>;
1122
+ resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>,
1123
+ <&cru SRST_RESETN_CORE_VDPP>;
1124
+ reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s";
1125
+ rockchip,srv = <&mpp_srv>;
1126
+ rockchip,taskqueue-node = <3>;
1127
+ rockchip,resetgroup-node = <3>;
1128
+ power-domains = <&power RK3528_PD_VO>;
1129
+ iommus = <&iep_mmu>;
1130
+ status = "disabled";
1131
+ };
1132
+
1133
+ jpegd: jpegd@ff870000 {
1134
+ compatible = "rockchip,rkv-jpeg-decoder-v1";
1135
+ reg = <0x0 0xff870000 0x0 0x400>;
1136
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1137
+ clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
1138
+ clock-names = "aclk_vcodec", "hclk_vcodec";
1139
+ rockchip,disable-auto-freq;
1140
+ resets = <&cru SRST_ARESETN_JPEG_DECODER>, <&cru SRST_HRESETN_JPEG_DECODER>;
1141
+ reset-names = "video_a", "video_h";
1142
+ power-domains = <&power RK3528_PD_VO>;
1143
+ iommus = <&jpegd_mmu>;
1144
+ rockchip,srv = <&mpp_srv>;
1145
+ rockchip,taskqueue-node = <4>;
1146
+ rockchip,resetgroup-node = <4>;
1147
+ status = "disabled";
1148
+ };
1149
+
1150
+ jpegd_mmu: iommu@ff870480 {
1151
+ compatible = "rockchip,iommu-v2";
1152
+ reg = <0x0 0xff870480 0x0 0x40>;
1153
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1154
+ interrupt-names = "jpegd_mmu";
1155
+ clock-names = "aclk", "iface";
1156
+ clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
1157
+ power-domains = <&power RK3528_PD_VO>;
1158
+ #iommu-cells = <0>;
1159
+ status = "disabled";
1160
+ };
1161
+
1162
+ tve: tve@ff880000 {
1163
+ compatible = "rockchip,rk3528-tve";
1164
+ reg = <0x0 0xff880000 0x0 0x4000>,
1165
+ <0x0 0xffde0000 0x0 0x300>;
1166
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1167
+ clocks = <&cru HCLK_CVBS>,
1168
+ <&cru PCLK_VCDCPHY>,
1169
+ <&cru DCLK_CVBS>,
1170
+ <&cru DCLK_4X_CVBS>;
1171
+ clock-names = "hclk",
1172
+ "pclk_vdac",
1173
+ "dclk",
1174
+ "dclk_4x";
1175
+ rockchip,lumafilter0 = <0x000a0ffa>;
1176
+ rockchip,lumafilter1 = <0x0ff4001a>;
1177
+ rockchip,lumafilter2 = <0x00110fd2>;
1178
+ rockchip,lumafilter3 = <0x0fe80051>;
1179
+ rockchip,lumafilter4 = <0x001a0f74>;
1180
+ rockchip,lumafilter5 = <0x0fe600ec>;
1181
+ rockchip,lumafilter6 = <0x0ffa0e43>;
1182
+ rockchip,lumafilter7 = <0x08200527>;
1183
+ rockchip,tve-upsample = <DCLK_UPSAMPLEx4>;
1184
+ rockchip,grf = <&grf>;
1185
+ status = "disabled";
1186
+
1187
+ ports {
1188
+ #address-cells = <1>;
1189
+ #size-cells = <0>;
1190
+
1191
+ port@0 {
1192
+ reg = <0>;
1193
+ #address-cells = <1>;
1194
+ #size-cells = <0>;
1195
+
1196
+ tve_in_vp1: endpoint@0 {
1197
+ reg = <0>;
1198
+ remote-endpoint = <&vp1_out_tve>;
1199
+ status = "disabled";
1200
+ };
1201
+ };
1202
+ };
1203
+ };
1204
+
1205
+ hdcp2: hdcp2@ff8c0000 {
1206
+ compatible = "rockchip,rk3528-hdmi-hdcp2";
1207
+ reg = <0x0 0xff8c0000 0x0 0x2000>;
1208
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1209
+ clocks = <&cru ACLK_HDCP>, <&cru PCLK_HDCP>,
1210
+ <&cru HCLK_HDCP>;
1211
+ clock-names ="aclk_hdcp2", "pclk_hdcp2", "hdcp2_clk_hdmi";
1212
+ status = "disabled";
1213
+ };
1214
+
1215
+ hdmi: hdmi@ff8d0000 {
1216
+ compatible = "rockchip,rk3528-dw-hdmi";
1217
+ reg = <0x0 0xff8d0000 0x0 0x20000>,
1218
+ <0x0 0xff610000 0x0 0x200>;
1219
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1220
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1221
+ clocks = <&cru PCLK_HDMI>,
1222
+ <&cru CLK_SFR_HDMI>,
1223
+ <&cru CLK_CEC_HDMI>;
1224
+ clock-names = "iahb", "isfr", "cec";
1225
+ reg-io-width = <4>;
1226
+ rockchip,grf = <&grf>;
1227
+ pinctrl-names = "default";
1228
+ pinctrl-0 = <&hdmi_pins>;
1229
+ phys = <&hdmiphy>;
1230
+ phy-names = "hdmi";
1231
+ #sound-dai-cells = <0>;
1232
+ hpd-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
1233
+ status = "disabled";
1234
+
1235
+ ports {
1236
+ #address-cells = <1>;
1237
+ #size-cells = <0>;
1238
+
1239
+ port@0 {
1240
+ reg = <0>;
1241
+ #address-cells = <1>;
1242
+ #size-cells = <0>;
1243
+
1244
+ hdmi_in_vp0: endpoint@0 {
1245
+ reg = <0>;
1246
+ remote-endpoint = <&vp0_out_hdmi>;
1247
+ status = "disabled";
1248
+ };
1249
+ };
1250
+ };
1251
+ };
1252
+
1253
+ can0: can@ff960000 {
1254
+ compatible = "rockchip,rk3528-can";
1255
+ reg = <0x0 0xff960000 0x0 0x100>;
1256
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1257
+ assigned-clocks = <&cru CLK_CAN0>;
1258
+ assigned-clock-rates = <198000000>;
1259
+ clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
1260
+ clock-names = "baudclk", "apb_pclk";
1261
+ resets = <&cru SRST_RESETN_CAN0>, <&cru SRST_PRESETN_CAN0>;
1262
+ reset-names = "can", "can-apb";
1263
+ status = "disabled";
1264
+ };
1265
+
1266
+ can1: can@ff970000 {
1267
+ compatible = "rockchip,rk3528-can";
1268
+ reg = <0x0 0xff970000 0x0 0x100>;
1269
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1270
+ assigned-clocks = <&cru CLK_CAN1>;
1271
+ assigned-clock-rates = <198000000>;
1272
+ clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
1273
+ clock-names = "baudclk", "apb_pclk";
1274
+ resets = <&cru SRST_RESETN_CAN1>, <&cru SRST_PRESETN_CAN1>;
1275
+ reset-names = "can", "can-apb";
1276
+ status = "disabled";
1277
+ };
1278
+
1279
+ can2: can@ff980000 {
1280
+ compatible = "rockchip,rk3528-can";
1281
+ reg = <0x0 0xff980000 0x0 0x100>;
1282
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1283
+ assigned-clocks = <&cru CLK_CAN2>;
1284
+ assigned-clock-rates = <198000000>;
1285
+ clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
1286
+ clock-names = "baudclk", "apb_pclk";
1287
+ resets = <&cru SRST_RESETN_CAN2>, <&cru SRST_PRESETN_CAN2>;
1288
+ reset-names = "can", "can-apb";
1289
+ status = "disabled";
1290
+ };
1291
+
1292
+ can3: can@ff990000 {
1293
+ compatible = "rockchip,rk3528-can";
1294
+ reg = <0x0 0xff990000 0x0 0x100>;
1295
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1296
+ assigned-clocks = <&cru CLK_CAN3>;
1297
+ assigned-clock-rates = <198000000>;
1298
+ clocks = <&cru CLK_CAN3>, <&cru PCLK_CAN3>;
1299
+ clock-names = "baudclk", "apb_pclk";
1300
+ resets = <&cru SRST_RESETN_CAN3>, <&cru SRST_PRESETN_CAN3>;
1301
+ reset-names = "can", "can-apb";
1302
+ status = "disabled";
1303
+ };
1304
+
1305
+ spi0: spi@ff9c0000 {
1306
+ compatible = "rockchip,rk3066-spi";
1307
+ reg = <0x0 0xff9c0000 0x0 0x1000>;
1308
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1309
+ #address-cells = <1>;
1310
+ #size-cells = <0>;
1311
+ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1312
+ clock-names = "spiclk", "apb_pclk";
1313
+ dmas = <&dmac 25>, <&dmac 24>;
1314
+ dma-names = "tx", "rx";
1315
+ pinctrl-names = "default";
1316
+ pinctrl-0 = <&spi0_csn0 &spi0_csn1 &spi0_pins>;
1317
+ status = "disabled";
1318
+ };
1319
+
1320
+ spi1: spi@ff9d0000 {
1321
+ compatible = "rockchip,rk3066-spi";
1322
+ reg = <0x0 0xff9d0000 0x0 0x1000>;
1323
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1324
+ #address-cells = <1>;
1325
+ #size-cells = <0>;
1326
+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1327
+ clock-names = "spiclk", "apb_pclk";
1328
+ dmas = <&dmac 31>, <&dmac 30>;
1329
+ dma-names = "tx", "rx";
1330
+ pinctrl-names = "default";
1331
+ pinctrl-0 = <&spi1_csn0 &spi1_csn1 &spi1_pins>;
1332
+ status = "disabled";
1333
+ };
1334
+
1335
+ uart0: serial@ff9f0000 {
1336
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
1337
+ reg = <0x0 0xff9f0000 0x0 0x100>;
1338
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1339
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
1340
+ clock-names = "baudclk", "apb_pclk";
1341
+ reg-shift = <2>;
1342
+ reg-io-width = <4>;
1343
+ dmas = <&dmac 9>, <&dmac 8>;
1344
+ status = "disabled";
1345
+ };
1346
+
1347
+ uart1: serial@ff9f8000 {
1348
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
1349
+ reg = <0x0 0xff9f8000 0x0 0x100>;
1350
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1351
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1352
+ clock-names = "baudclk", "apb_pclk";
1353
+ reg-shift = <2>;
1354
+ reg-io-width = <4>;
1355
+ dmas = <&dmac 11>, <&dmac 10>;
1356
+ status = "disabled";
1357
+ };
1358
+
1359
+ uart2: serial@ffa00000 {
1360
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
1361
+ reg = <0x0 0xffa00000 0x0 0x100>;
1362
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1363
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1364
+ clock-names = "baudclk", "apb_pclk";
1365
+ reg-shift = <2>;
1366
+ reg-io-width = <4>;
1367
+ dmas = <&dmac 13>, <&dmac 12>;
1368
+ status = "disabled";
1369
+ };
1370
+
1371
+ uart3: serial@ffa08000 {
1372
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
1373
+ reg = <0x0 0xffa08000 0x0 0x100>;
1374
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1375
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1376
+ clock-names = "baudclk", "apb_pclk";
1377
+ reg-shift = <2>;
1378
+ reg-io-width = <4>;
1379
+ dmas = <&dmac 15>, <&dmac 14>;
1380
+ status = "disabled";
1381
+ };
1382
+
1383
+ uart4: serial@ffa10000 {
1384
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
1385
+ reg = <0x0 0xffa10000 0x0 0x100>;
1386
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1387
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1388
+ clock-names = "baudclk", "apb_pclk";
1389
+ reg-shift = <2>;
1390
+ reg-io-width = <4>;
1391
+ dmas = <&dmac 17>, <&dmac 16>;
1392
+ status = "disabled";
1393
+ };
1394
+
1395
+ uart5: serial@ffa18000 {
1396
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
1397
+ reg = <0x0 0xffa18000 0x0 0x100>;
1398
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1399
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1400
+ clock-names = "baudclk", "apb_pclk";
1401
+ reg-shift = <2>;
1402
+ reg-io-width = <4>;
1403
+ dmas = <&dmac 19>, <&dmac 18>;
1404
+ status = "disabled";
1405
+ };
1406
+
1407
+ uart6: serial@ffa20000 {
1408
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
1409
+ reg = <0x0 0xffa20000 0x0 0x100>;
1410
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1411
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1412
+ clock-names = "baudclk", "apb_pclk";
1413
+ reg-shift = <2>;
1414
+ reg-io-width = <4>;
1415
+ dmas = <&dmac 21>, <&dmac 20>;
1416
+ status = "disabled";
1417
+ };
1418
+
1419
+ uart7: serial@ffa28000 {
1420
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
1421
+ reg = <0x0 0xffa28000 0x0 0x100>;
1422
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1423
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1424
+ clock-names = "baudclk", "apb_pclk";
1425
+ reg-shift = <2>;
1426
+ reg-io-width = <4>;
1427
+ dmas = <&dmac 23>, <&dmac 22>;
1428
+ status = "disabled";
1429
+ };
1430
+
1431
+ i2c0: i2c@ffa50000 {
1432
+ compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
1433
+ reg = <0x0 0xffa50000 0x0 0x1000>;
1434
+ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
1435
+ clock-names = "i2c", "pclk";
1436
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1437
+ pinctrl-names = "default";
1438
+ pinctrl-0 = <&i2c0m0_xfer>;
1439
+ #address-cells = <1>;
1440
+ #size-cells = <0>;
1441
+ status = "disabled";
1442
+ };
1443
+
1444
+ i2c1: i2c@ffa58000 {
1445
+ compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
1446
+ reg = <0x0 0xffa58000 0x0 0x1000>;
1447
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1448
+ clock-names = "i2c", "pclk";
1449
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1450
+ pinctrl-names = "default";
1451
+ pinctrl-0 = <&i2c1m0_xfer>;
1452
+ #address-cells = <1>;
1453
+ #size-cells = <0>;
1454
+ status = "disabled";
1455
+ };
1456
+
1457
+ i2c2: i2c@ffa60000 {
1458
+ compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
1459
+ reg = <0x0 0xffa60000 0x0 0x1000>;
1460
+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1461
+ clock-names = "i2c", "pclk";
1462
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1463
+ pinctrl-names = "default";
1464
+ pinctrl-0 = <&i2c2m0_xfer>;
1465
+ #address-cells = <1>;
1466
+ #size-cells = <0>;
1467
+ status = "disabled";
1468
+ };
1469
+
1470
+ i2c3: i2c@ffa68000 {
1471
+ compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
1472
+ reg = <0x0 0xffa68000 0x0 0x1000>;
1473
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1474
+ clock-names = "i2c", "pclk";
1475
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1476
+ pinctrl-names = "default";
1477
+ pinctrl-0 = <&i2c3m0_xfer>;
1478
+ #address-cells = <1>;
1479
+ #size-cells = <0>;
1480
+ status = "disabled";
1481
+ };
1482
+
1483
+ i2c4: i2c@ffa70000 {
1484
+ compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
1485
+ reg = <0x0 0xffa70000 0x0 0x1000>;
1486
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1487
+ clock-names = "i2c", "pclk";
1488
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1489
+ pinctrl-names = "default";
1490
+ pinctrl-0 = <&i2c4_xfer>;
1491
+ #address-cells = <1>;
1492
+ #size-cells = <0>;
1493
+ status = "disabled";
1494
+ };
1495
+
1496
+ i2c5: i2c@ffa78000 {
1497
+ compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
1498
+ reg = <0x0 0xffa78000 0x0 0x1000>;
1499
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1500
+ clock-names = "i2c", "pclk";
1501
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1502
+ pinctrl-names = "default";
1503
+ pinctrl-0 = <&i2c5m0_xfer>;
1504
+ #address-cells = <1>;
1505
+ #size-cells = <0>;
1506
+ status = "disabled";
1507
+ };
1508
+
1509
+ i2c6: i2c@ffa80000 {
1510
+ compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
1511
+ reg = <0x0 0xffa80000 0x0 0x1000>;
1512
+ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
1513
+ clock-names = "i2c", "pclk";
1514
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1515
+ pinctrl-names = "default";
1516
+ pinctrl-0 = <&i2c6m0_xfer>;
1517
+ #address-cells = <1>;
1518
+ #size-cells = <0>;
1519
+ status = "disabled";
1520
+ };
1521
+
1522
+ i2c7: i2c@ffa88000 {
1523
+ compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
1524
+ reg = <0x0 0xffa88000 0x0 0x1000>;
1525
+ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
1526
+ clock-names = "i2c", "pclk";
1527
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1528
+ pinctrl-names = "default";
1529
+ pinctrl-0 = <&i2c7_xfer>;
1530
+ #address-cells = <1>;
1531
+ #size-cells = <0>;
1532
+ status = "disabled";
1533
+ };
1534
+
1535
+ pwm0: pwm@ffa90000 {
1536
+ compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
1537
+ reg = <0x0 0xffa90000 0x0 0x10>;
1538
+ #pwm-cells = <3>;
1539
+ pinctrl-names = "active";
1540
+ pinctrl-0 = <&pwm0m0_pins>;
1541
+ clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
1542
+ clock-names = "pwm", "pclk";
1543
+ status = "disabled";
1544
+ };
1545
+
1546
+ pwm1: pwm@ffa90010 {
1547
+ compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
1548
+ reg = <0x0 0xffa90010 0x0 0x10>;
1549
+ #pwm-cells = <3>;
1550
+ pinctrl-names = "active";
1551
+ pinctrl-0 = <&pwm1m0_pins>;
1552
+ clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
1553
+ clock-names = "pwm", "pclk";
1554
+ status = "disabled";
1555
+ };
1556
+
1557
+ pwm2: pwm@ffa90020 {
1558
+ compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
1559
+ reg = <0x0 0xffa90020 0x0 0x10>;
1560
+ #pwm-cells = <3>;
1561
+ pinctrl-names = "active";
1562
+ pinctrl-0 = <&pwm2m0_pins>;
1563
+ clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
1564
+ clock-names = "pwm", "pclk";
1565
+ status = "disabled";
1566
+ };
1567
+
1568
+ pwm3: pwm@ffa90030 {
1569
+ compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
1570
+ reg = <0x0 0xffa90030 0x0 0x10>;
1571
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
1572
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1573
+ #pwm-cells = <3>;
1574
+ pinctrl-names = "active";
1575
+ pinctrl-0 = <&pwm3m0_pins>;
1576
+ clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
1577
+ clock-names = "pwm", "pclk";
1578
+ status = "disabled";
1579
+ };
1580
+
1581
+ pwm4: pwm@ffa98000 {
1582
+ compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
1583
+ reg = <0x0 0xffa98000 0x0 0x10>;
1584
+ #pwm-cells = <3>;
1585
+ pinctrl-names = "active";
1586
+ pinctrl-0 = <&pwm4m0_pins>;
1587
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1588
+ clock-names = "pwm", "pclk";
1589
+ status = "disabled";
1590
+ };
1591
+
1592
+ pwm5: pwm@ffa98010 {
1593
+ compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
1594
+ reg = <0x0 0xffa98010 0x0 0x10>;
1595
+ #pwm-cells = <3>;
1596
+ pinctrl-names = "active";
1597
+ pinctrl-0 = <&pwm5m0_pins>;
1598
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1599
+ clock-names = "pwm", "pclk";
1600
+ status = "disabled";
1601
+ };
1602
+
1603
+ pwm6: pwm@ffa98020 {
1604
+ compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
1605
+ reg = <0x0 0xffa98020 0x0 0x10>;
1606
+ #pwm-cells = <3>;
1607
+ pinctrl-names = "active";
1608
+ pinctrl-0 = <&pwm6m0_pins>;
1609
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1610
+ clock-names = "pwm", "pclk";
1611
+ status = "disabled";
1612
+ };
1613
+
1614
+ pwm7: pwm@ffa98030 {
1615
+ compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
1616
+ reg = <0x0 0xffa98030 0x0 0x10>;
1617
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
1618
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1619
+ #pwm-cells = <3>;
1620
+ pinctrl-names = "active";
1621
+ pinctrl-0 = <&pwm7m0_pins>;
1622
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1623
+ clock-names = "pwm", "pclk";
1624
+ status = "disabled";
1625
+ };
1626
+
1627
+ rktimer: timer@ffab0000 {
1628
+ compatible = "rockchip,rk3528-timer", "rockchip,rk3288-timer";
1629
+ reg = <0x0 0xffab0000 0x0 0x20>;
1630
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1631
+ clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
1632
+ clock-names = "pclk", "timer";
1633
+ };
1634
+
1635
+ wdt: watchdog@ffac0000 {
1636
+ compatible = "snps,dw-wdt";
1637
+ reg = <0x0 0xffac0000 0x0 0x100>;
1638
+ clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
1639
+ clock-names = "tclk", "pclk";
1640
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1641
+ status = "disabled";
1642
+ };
1643
+
1644
+ tsadc: tsadc@ffad0000 {
1645
+ compatible = "rockchip,rk3528-tsadc";
1646
+ reg = <0x0 0xffad0000 0x0 0x400>;
1647
+ rockchip,grf = <&grf>;
1648
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1649
+ clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>, <&cru PCLK_TSADC>;
1650
+ clock-names = "tsadc", "tsadc_tsen", "apb_pclk";
1651
+ assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
1652
+ assigned-clock-rates = <1200000>, <12000000>;
1653
+ resets = <&cru SRST_RESETN_TSADC>, <&cru SRST_PRESETN_TSADC>;
1654
+ reset-names = "tsadc", "tsadc-apb";
1655
+ #thermal-sensor-cells = <1>;
1656
+ rockchip,hw-tshut-temp = <120000>;
1657
+ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
1658
+ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
1659
+ status = "disabled";
1660
+ };
1661
+
1662
+ saradc: saradc@ffae0000 {
1663
+ compatible = "rockchip,rk3528-saradc";
1664
+ reg = <0x0 0xffae0000 0x0 0x10000>;
1665
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1666
+ #io-channel-cells = <1>;
1667
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1668
+ clock-names = "saradc", "apb_pclk";
1669
+ resets = <&cru SRST_PRESETN_SARADC>;
1670
+ reset-names = "saradc-apb";
1671
+ status = "disabled";
1672
+ };
1673
+
1674
+ sai3: sai@ffb70000 {
1675
+ compatible = "rockchip,rk3528-sai", "rockchip,sai-v1";
1676
+ reg = <0x0 0xffb70000 0x0 0x1000>;
1677
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
1678
+ clocks = <&cru MCLK_SAI_I2S3>, <&cru HCLK_SAI_I2S3>;
1679
+ clock-names = "mclk", "hclk";
1680
+ dmas = <&dmac 5>;
1681
+ dma-names = "tx";
1682
+ resets = <&cru SRST_MRESETN_SAI_I2S3>, <&cru SRST_HRESETN_SAI_I2S3>;
1683
+ reset-names = "m", "h";
1684
+ #sound-dai-cells = <0>;
1685
+ status = "disabled";
1686
+ };
1687
+
1688
+ sai0: sai@ffb80000 {
1689
+ compatible = "rockchip,rk3528-sai", "rockchip,sai-v1";
1690
+ reg = <0x0 0xffb80000 0x0 0x1000>;
1691
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1692
+ clocks = <&cru MCLK_SAI_I2S0>, <&cru HCLK_SAI_I2S0>;
1693
+ clock-names = "mclk", "hclk";
1694
+ dmas = <&dmac 1>, <&dmac 0>;
1695
+ dma-names = "tx", "rx";
1696
+ resets = <&cru SRST_MRESETN_SAI_I2S0>, <&cru SRST_HRESETN_SAI_I2S0>;
1697
+ reset-names = "m", "h";
1698
+ pinctrl-names = "default";
1699
+ pinctrl-0 = <&i2s0m0_pins>;
1700
+ #sound-dai-cells = <0>;
1701
+ status = "disabled";
1702
+ };
1703
+
1704
+ sai2: sai@ffb90000 {
1705
+ compatible = "rockchip,rk3528-sai", "rockchip,sai-v1";
1706
+ reg = <0x0 0xffb90000 0x0 0x1000>;
1707
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1708
+ clocks = <&cru MCLK_SAI_I2S2>, <&cru HCLK_SAI_I2S2>;
1709
+ clock-names = "mclk", "hclk";
1710
+ dmas = <&dmac 4>;
1711
+ dma-names = "tx";
1712
+ resets = <&cru SRST_MRESETN_SAI_I2S2>, <&cru SRST_HRESETN_SAI_I2S2>;
1713
+ reset-names = "m", "h";
1714
+ #sound-dai-cells = <0>;
1715
+ status = "disabled";
1716
+ };
1717
+
1718
+ sai1: sai@ffba0000 {
1719
+ compatible = "rockchip,rk3528-sai", "rockchip,sai-v1";
1720
+ reg = <0x0 0xffba0000 0x0 0x1000>;
1721
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1722
+ clocks = <&cru MCLK_SAI_I2S1>, <&cru HCLK_SAI_I2S1>;
1723
+ clock-names = "mclk", "hclk";
1724
+ dmas = <&dmac 3>, <&dmac 2>;
1725
+ dma-names = "tx", "rx";
1726
+ resets = <&cru SRST_MRESETN_SAI_I2S1>, <&cru SRST_HRESETN_SAI_I2S1>;
1727
+ reset-names = "m", "h";
1728
+ pinctrl-names = "default";
1729
+ pinctrl-0 = <&i2s1_pins>;
1730
+ #sound-dai-cells = <0>;
1731
+ status = "disabled";
1732
+ };
1733
+
1734
+ pdm: pdm@ffbb0000 {
1735
+ compatible = "rockchip,rk3528-pdm", "rockchip,rk3568-pdm";
1736
+ reg = <0x0 0xffbb0000 0x0 0x1000>;
1737
+ clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
1738
+ clock-names = "pdm_clk", "pdm_hclk";
1739
+ dmas = <&dmac 6>;
1740
+ dma-names = "rx";
1741
+ pinctrl-names = "default";
1742
+ pinctrl-0 = <&pdm_clk0
1743
+ &pdm_clk1
1744
+ &pdm_sdi0
1745
+ &pdm_sdi1
1746
+ &pdm_sdi2
1747
+ &pdm_sdi3>;
1748
+ #sound-dai-cells = <0>;
1749
+ status = "disabled";
1750
+ };
1751
+
1752
+ spdif_8ch: spdif@ffbc0000 {
1753
+ compatible = "rockchip,rk3528-spdif", "rockchip,rk3568-spdif";
1754
+ reg = <0x0 0xffbc0000 0x0 0x1000>;
1755
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
1756
+ dmas = <&dmac 7>;
1757
+ dma-names = "tx";
1758
+ clock-names = "mclk", "hclk";
1759
+ clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>;
1760
+ #sound-dai-cells = <0>;
1761
+ pinctrl-names = "default";
1762
+ pinctrl-0 = <&spdifm0_pins>;
1763
+ status = "disabled";
1764
+ };
1765
+
1766
+ gmac0: ethernet@ffbd0000 {
1767
+ compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
1768
+ reg = <0x0 0xffbd0000 0x0 0x10000>;
1769
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1770
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1771
+ interrupt-names = "macirq", "eth_wake_irq";
1772
+ rockchip,grf = <&grf>;
1773
+ clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>,
1774
+ <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>,
1775
+ <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>;
1776
+ clock-names = "stmmaceth", "clk_mac_ref",
1777
+ "mac_clk_rx", "mac_clk_tx",
1778
+ "pclk_mac", "aclk_mac";
1779
+ resets = <&cru SRST_ARESETN_MAC_VO>;
1780
+ reset-names = "stmmaceth";
1781
+
1782
+ snps,mixed-burst;
1783
+ snps,tso;
1784
+
1785
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
1786
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
1787
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
1788
+
1789
+ phy-mode = "rmii";
1790
+ clock_in_out = "input";
1791
+ phy-handle = <&rmii0_phy>;
1792
+
1793
+ nvmem-cells = <&macphy_bgs>;
1794
+ nvmem-cell-names = "bgs";
1795
+ status = "disabled";
1796
+
1797
+ mdio0: mdio {
1798
+ compatible = "snps,dwmac-mdio";
1799
+ #address-cells = <0x1>;
1800
+ #size-cells = <0x0>;
1801
+ rmii0_phy: ethernet-phy@2 {
1802
+ compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22";
1803
+ reg = <2>;
1804
+ clocks = <&cru CLK_MACPHY>;
1805
+ resets = <&cru SRST_RESETN_MACPHY>;
1806
+ phy-is-integrated;
1807
+ pinctrl-names = "default";
1808
+ pinctrl-0 = <&fephym0_led_link &fephym0_led_spd>;
1809
+ nvmem-cells = <&macphy_txlevel>;
1810
+ nvmem-cell-names = "txlevel";
1811
+ };
1812
+ };
1813
+
1814
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
1815
+ snps,wr_osr_lmt = <4>;
1816
+ snps,rd_osr_lmt = <8>;
1817
+ snps,blen = <0 0 0 0 16 8 4>;
1818
+ };
1819
+
1820
+ gmac0_mtl_rx_setup: rx-queues-config {
1821
+ snps,rx-queues-to-use = <1>;
1822
+ queue0 {};
1823
+ };
1824
+
1825
+ gmac0_mtl_tx_setup: tx-queues-config {
1826
+ snps,tx-queues-to-use = <1>;
1827
+ queue0 {};
1828
+ };
1829
+ };
1830
+
1831
+ gmac1: ethernet@ffbe0000 {
1832
+ compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
1833
+ reg = <0x0 0xffbe0000 0x0 0x10000>;
1834
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1835
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1836
+ interrupt-names = "macirq", "eth_wake_irq";
1837
+ rockchip,grf = <&grf>;
1838
+ clocks = <&cru CLK_GMAC1_SRC_VPU>, <&cru CLK_GMAC1_RMII_VPU>,
1839
+ <&cru PCLK_MAC_VPU>, <&cru ACLK_MAC_VPU>;
1840
+ clock-names = "stmmaceth", "clk_mac_ref",
1841
+ "pclk_mac", "aclk_mac";
1842
+ resets = <&cru SRST_ARESETN_MAC>;
1843
+ reset-names = "stmmaceth";
1844
+
1845
+ snps,mixed-burst;
1846
+ snps,tso;
1847
+
1848
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
1849
+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1850
+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1851
+
1852
+ status = "disabled";
1853
+
1854
+ mdio1: mdio {
1855
+ compatible = "snps,dwmac-mdio";
1856
+ #address-cells = <0x1>;
1857
+ #size-cells = <0x0>;
1858
+ };
1859
+
1860
+ gmac1_stmmac_axi_setup: stmmac-axi-config {
1861
+ snps,wr_osr_lmt = <4>;
1862
+ snps,rd_osr_lmt = <8>;
1863
+ snps,blen = <0 0 0 0 16 8 4>;
1864
+ };
1865
+
1866
+ gmac1_mtl_rx_setup: rx-queues-config {
1867
+ snps,rx-queues-to-use = <1>;
1868
+ queue0 {};
1869
+ };
1870
+
1871
+ gmac1_mtl_tx_setup: tx-queues-config {
1872
+ snps,tx-queues-to-use = <1>;
1873
+ queue0 {};
1874
+ };
1875
+ };
1876
+
1877
+ sdhci: mmc@ffbf0000 {
1878
+ compatible = "rockchip,rk3528-dwcmshc";
1879
+ reg = <0x0 0xffbf0000 0x0 0x10000>;
1880
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1881
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>;
1882
+ assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1883
+ clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
1884
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1885
+ <&cru TCLK_EMMC>;
1886
+ clock-names = "core", "bus", "axi", "block", "timer";
1887
+ resets = <&cru SRST_CRESETN_EMMC>, <&cru SRST_HRESETN_EMMC>,
1888
+ <&cru SRST_ARESETN_EMMC>, <&cru SRST_BRESETN_EMMC>,
1889
+ <&cru SRST_TRESETN_EMMC>;
1890
+ reset-names = "core", "bus", "axi", "block", "timer";
1891
+ max-frequency = <200000000>;
1892
+ status = "disabled";
1893
+ };
1894
+
1895
+ sfc: spi@ffc00000 {
1896
+ compatible = "rockchip,sfc";
1897
+ reg = <0x0 0xffc00000 0x0 0x4000>;
1898
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1899
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1900
+ clock-names = "clk_sfc", "hclk_sfc";
1901
+ assigned-clocks = <&cru SCLK_SFC>;
1902
+ assigned-clock-rates = <100000000>;
1903
+ #address-cells = <1>;
1904
+ #size-cells = <0>;
1905
+ status = "disabled";
1906
+ };
1907
+
1908
+ sdio0: mmc@ffc10000 {
1909
+ compatible = "rockchip,rk3528-dw-mshc",
1910
+ "rockchip,rk3288-dw-mshc";
1911
+ reg = <0x0 0xffc10000 0x0 0x4000>;
1912
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1913
+ max-frequency = <150000000>;
1914
+ clocks = <&cru HCLK_SDIO0>, <&cru CCLK_SRC_SDIO0>,
1915
+ <&grf_cru SCLK_SDIO0_DRV>, <&grf_cru SCLK_SDIO0_SAMPLE>;
1916
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1917
+ fifo-depth = <0x100>;
1918
+ resets = <&cru SRST_HRESETN_SDIO0>;
1919
+ reset-names = "reset";
1920
+ rockchip,use-v2-tuning;
1921
+ status = "disabled";
1922
+ };
1923
+
1924
+ sdio1: mmc@ffc20000 {
1925
+ compatible = "rockchip,rk3528-dw-mshc",
1926
+ "rockchip,rk3288-dw-mshc";
1927
+ reg = <0x0 0xffc20000 0x0 0x4000>;
1928
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1929
+ max-frequency = <150000000>;
1930
+ clocks = <&cru HCLK_SDIO1>, <&cru CCLK_SRC_SDIO1>,
1931
+ <&grf_cru SCLK_SDIO1_DRV>, <&grf_cru SCLK_SDIO1_SAMPLE>;
1932
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1933
+ fifo-depth = <0x100>;
1934
+ resets = <&cru SRST_HRESETN_SDIO1>;
1935
+ reset-names = "reset";
1936
+ rockchip,use-v2-tuning;
1937
+ status = "disabled";
1938
+ };
1939
+
1940
+ sdmmc: mmc@ffc30000 {
1941
+ compatible = "rockchip,rk3528-dw-mshc",
1942
+ "rockchip,rk3288-dw-mshc";
1943
+ reg = <0x0 0xffc30000 0x0 0x4000>;
1944
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1945
+ max-frequency = <150000000>;
1946
+ clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>,
1947
+ <&grf_cru SCLK_SDMMC_DRV>, <&grf_cru SCLK_SDMMC_SAMPLE>;
1948
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1949
+ fifo-depth = <0x100>;
1950
+ resets = <&cru SRST_HRESETN_SDMMC0>;
1951
+ reset-names = "reset";
1952
+ rockchip,use-v2-tuning;
1953
+ pinctrl-names = "default";
1954
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1955
+ status = "disabled";
1956
+ };
1957
+
1958
+ crypto: crypto@ffc40000 {
1959
+ compatible = "rockchip,crypto-v4";
1960
+ reg = <0x0 0xffc40000 0x0 0x2000>;
1961
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1962
+ clocks = <&scmi_clk SCMI_ACLK_CRYPTO>, <&scmi_clk SCMI_HCLK_CRYPTO>,
1963
+ <&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>;
1964
+ clock-names = "aclk", "hclk", "sclk", "pka";
1965
+ assigned-clocks = <&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>;
1966
+ assigned-clock-rates = <300000000>, <300000000>;
1967
+ resets = <&cru SRST_RESETN_CORE_CRYPTO>;
1968
+ reset-names = "crypto-rst";
1969
+ status = "disabled";
1970
+ };
1971
+
1972
+ rng: rng@ffc50000 {
1973
+ compatible = "rockchip,rkrng";
1974
+ reg = <0x0 0xffc50000 0x0 0x200>;
1975
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1976
+ clocks = <&scmi_clk SCMI_HCLK_TRNG>;
1977
+ clock-names = "hclk_trng";
1978
+ resets = <&cru SRST_HRESETN_TRNG_NS>;
1979
+ reset-names = "reset";
1980
+ status = "disabled";
1981
+ };
1982
+
1983
+ otp: otp@ffce0000 {
1984
+ compatible = "rockchip,rk3528-otp";
1985
+ reg = <0x0 0xffce0000 0x0 0x4000>;
1986
+ #address-cells = <1>;
1987
+ #size-cells = <1>;
1988
+ clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
1989
+ <&cru PCLK_OTPC_NS>;
1990
+ clock-names = "usr", "sbpi", "apb";
1991
+ resets = <&cru SRST_RESETN_USER_OTPC_NS>,
1992
+ <&cru SRST_RESETN_SBPI_OTPC_NS>,
1993
+ <&cru SRST_PRESETN_OTPC_NS>;
1994
+ reset-names = "usr", "sbpi", "apb";
1995
+
1996
+ /* Data cells */
1997
+ cpu_code: cpu-code@2 {
1998
+ reg = <0x02 0x2>;
1999
+ };
2000
+ otp_cpu_version: cpu-version@8 {
2001
+ reg = <0x08 0x1>;
2002
+ bits = <3 3>;
2003
+ };
2004
+ otp_id: id@a {
2005
+ reg = <0x0a 0x10>;
2006
+ };
2007
+ cpu_leakage: cpu-leakage@1a {
2008
+ reg = <0x1a 0x1>;
2009
+ };
2010
+ log_leakage: log-leakage@1b {
2011
+ reg = <0x1b 0x1>;
2012
+ };
2013
+ gpu_leakage: gpu-leakage@1c {
2014
+ reg = <0x1c 0x1>;
2015
+ };
2016
+ macphy_bgs: macphy-bgs@2d {
2017
+ reg = <0x2d 0x1>;
2018
+ };
2019
+ macphy_txlevel: macphy-txlevel@2e {
2020
+ reg = <0x2e 0x2>;
2021
+ };
2022
+ };
2023
+
2024
+ dmac: dma-controller@ffd60000 {
2025
+ compatible = "arm,pl330", "arm,primecell";
2026
+ reg = <0x0 0xffd60000 0x0 0x4000>;
2027
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
2028
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
2029
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
2030
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
2031
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
2032
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
2033
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
2034
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
2035
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2036
+ clocks = <&cru ACLK_DMAC>;
2037
+ clock-names = "apb_pclk";
2038
+ #dma-cells = <1>;
2039
+ arm,pl330-periph-burst;
2040
+ };
2041
+
2042
+ hwlock: hwspinlock@ffd70000 {
2043
+ compatible = "rockchip,hwspinlock";
2044
+ reg = <0x0 0xffd70000 0x0 0x100>;
2045
+ #hwlock-cells = <1>;
2046
+ status = "disabled";
2047
+ };
2048
+
2049
+ combphy_pu: phy@ffdc0000 {
2050
+ compatible = "rockchip,rk3528-naneng-combphy";
2051
+ reg = <0x0 0xffdc0000 0x0 0x10000>;
2052
+ #phy-cells = <1>;
2053
+ clocks = <&cru CLK_REF_PCIE_INNER_PHY>, <&cru PCLK_PCIE_PHY>, <&cru PCLK_PIPE_GRF>;
2054
+ clock-names = "refclk", "apbclk", "pipe_clk";
2055
+ assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>;
2056
+ assigned-clock-rates = <100000000>;
2057
+ resets = <&cru SRST_PRESETN_PCIE_PHY>, <&cru SRST_RESETN_PCIE_PIPE_PHY>;
2058
+ reset-names = "combphy-apb", "combphy";
2059
+ rockchip,pipe-grf = <&grf>;
2060
+ rockchip,pipe-phy-grf = <&grf>;
2061
+ status = "disabled";
2062
+ };
2063
+
2064
+ usb2phy: usb2-phy@ffdf0000 {
2065
+ compatible = "rockchip,rk3528-usb2phy";
2066
+ reg = <0x0 0xffdf0000 0x0 0x10000>;
2067
+ clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>;
2068
+ clock-names = "phyclk", "apb_pclk";
2069
+ #clock-cells = <0>;
2070
+ rockchip,usbgrf = <&grf>;
2071
+ status = "disabled";
2072
+
2073
+ u2phy_otg: otg-port {
2074
+ #phy-cells = <0>;
2075
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2076
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2077
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2078
+ interrupt-names = "otg-bvalid",
2079
+ "otg-id",
2080
+ "linestate";
2081
+ status = "disabled";
2082
+ };
2083
+
2084
+ u2phy_host: host-port {
2085
+ #phy-cells = <0>;
2086
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2087
+ interrupt-names = "linestate";
2088
+ status = "disabled";
2089
+ };
2090
+ };
2091
+
2092
+ hdmiphy: hdmiphy@ffe00000 {
2093
+ compatible = "rockchip,rk3528-hdmi-phy";
2094
+ reg = <0x0 0xffe00000 0x0 0x10000>;
2095
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2096
+ #phy-cells = <0>;
2097
+ clocks = <&cru PCLK_HDMIPHY>, <&xin24m>;
2098
+ clock-names = "sysclk", "refclk";
2099
+ #clock-cells = <0>;
2100
+ clock-output-names = "clk_hdmiphy_pixel_io";
2101
+ status = "disabled";
2102
+ };
2103
+
2104
+ acodec: acodec@ffe10000 {
2105
+ compatible = "rockchip,rk3528-codec";
2106
+ reg = <0x0 0xffe10000 0x0 0x1000>;
2107
+ #sound-dai-cells = <0>;
2108
+ clocks = <&cru PCLK_ACODEC>, <&cru MCLK_ACODEC_TX>;
2109
+ clock-names = "pclk", "mclk";
2110
+ resets = <&cru SRST_PRESETN_ACODEC>;
2111
+ reset-names = "acodec";
2112
+ status = "disabled";
2113
+ };
2114
+
2115
+ pinctrl: pinctrl {
2116
+ compatible = "rockchip,rk3528-pinctrl";
2117
+ rockchip,grf = <&ioc_grf>;
2118
+ #address-cells = <2>;
2119
+ #size-cells = <2>;
2120
+ ranges;
2121
+
2122
+ gpio0: gpio@ff610000 {
2123
+ compatible = "rockchip,gpio-bank";
2124
+ reg = <0x0 0xff610000 0x0 0x200>;
2125
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
2126
+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
2127
+ gpio-controller;
2128
+ #gpio-cells = <2>;
2129
+ gpio-ranges = <&pinctrl 0 0 32>;
2130
+ interrupt-controller;
2131
+ #interrupt-cells = <2>;
2132
+ };
2133
+
2134
+ gpio1: gpio@ffaf0000 {
2135
+ compatible = "rockchip,gpio-bank";
2136
+ reg = <0x0 0xffaf0000 0x0 0x200>;
2137
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
2138
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
2139
+ gpio-controller;
2140
+ #gpio-cells = <2>;
2141
+ gpio-ranges = <&pinctrl 0 32 32>;
2142
+ interrupt-controller;
2143
+ #interrupt-cells = <2>;
2144
+ };
2145
+
2146
+ gpio2: gpio@ffb00000 {
2147
+ compatible = "rockchip,gpio-bank";
2148
+ reg = <0x0 0xffb00000 0x0 0x200>;
2149
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
2150
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
2151
+ gpio-controller;
2152
+ #gpio-cells = <2>;
2153
+ gpio-ranges = <&pinctrl 0 64 32>;
2154
+ interrupt-controller;
2155
+ #interrupt-cells = <2>;
2156
+ };
2157
+
2158
+ gpio3: gpio@ffb10000 {
2159
+ compatible = "rockchip,gpio-bank";
2160
+ reg = <0x0 0xffb10000 0x0 0x200>;
2161
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
2162
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
2163
+ gpio-controller;
2164
+ #gpio-cells = <2>;
2165
+ gpio-ranges = <&pinctrl 0 96 32>;
2166
+ interrupt-controller;
2167
+ #interrupt-cells = <2>;
2168
+ };
2169
+
2170
+ gpio4: gpio@ffb20000 {
2171
+ compatible = "rockchip,gpio-bank";
2172
+ reg = <0x0 0xffb20000 0x0 0x200>;
2173
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
2174
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
2175
+ gpio-controller;
2176
+ #gpio-cells = <2>;
2177
+ gpio-ranges = <&pinctrl 0 128 32>;
2178
+ interrupt-controller;
2179
+ #interrupt-cells = <2>;
2180
+ };
2181
+ };
2182
+};
2183
+
2184
+#include "rk3528-pinctrl.dtsi"
u-boot/arch/arm/dts/rk3562-evb.dts
....@@ -0,0 +1,31 @@
1
+/*
2
+ * SPDX-License-Identifier: GPL-2.0+
3
+ *
4
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
5
+ */
6
+
7
+/dts-v1/;
8
+#include "rk3562.dtsi"
9
+#include "rk3562-u-boot.dtsi"
10
+#include <dt-bindings/input/input.h>
11
+
12
+/ {
13
+ model = "Rockchip RK3562 Evaluation Board";
14
+ compatible = "rockchip,rk3562-evb", "rockchip,rk3562";
15
+
16
+ adc-keys {
17
+ compatible = "adc-keys";
18
+ io-channels = <&saradc0 1>;
19
+ io-channel-names = "buttons";
20
+ keyup-threshold-microvolt = <1800000>;
21
+ u-boot,dm-pre-reloc;
22
+ status = "okay";
23
+
24
+ volumeup-key {
25
+ u-boot,dm-pre-reloc;
26
+ linux,code = <KEY_VOLUMEUP>;
27
+ label = "volume up";
28
+ press-threshold-microvolt = <9>;
29
+ };
30
+ };
31
+};
u-boot/arch/arm/dts/rk3562-pinctrl.dtsi
....@@ -0,0 +1,1872 @@
1
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+/*
3
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4
+ */
5
+
6
+#include <dt-bindings/pinctrl/rockchip.h>
7
+#include "rockchip-pinconf.dtsi"
8
+
9
+/*
10
+ * This file is auto generated by pin2dts tool, please keep these code
11
+ * by adding changes at end of this file.
12
+ */
13
+&pinctrl {
14
+ cam {
15
+ camm0_pins: camm0-pins {
16
+ rockchip,pins =
17
+ /* cam_clk0_out_m0 */
18
+ <3 RK_PB2 2 &pcfg_pull_none>,
19
+ /* cam_clk1_out_m0 */
20
+ <3 RK_PB3 2 &pcfg_pull_none>;
21
+ };
22
+
23
+ camm1_pins: camm1-pins {
24
+ rockchip,pins =
25
+ /* cam_clk0_out_m1 */
26
+ <4 RK_PB1 3 &pcfg_pull_none>,
27
+ /* cam_clk1_out_m1 */
28
+ <4 RK_PB7 3 &pcfg_pull_none>;
29
+ };
30
+
31
+ cam_clk2_out: cam-clk2-out {
32
+ rockchip,pins =
33
+ /* cam_clk2_out */
34
+ <3 RK_PB4 2 &pcfg_pull_none>;
35
+ };
36
+ cam_clk3_out: cam-clk3-out {
37
+ rockchip,pins =
38
+ /* cam_clk3_out */
39
+ <3 RK_PB5 2 &pcfg_pull_none>;
40
+ };
41
+ };
42
+
43
+ can0 {
44
+ can0m0_pins: can0m0-pins {
45
+ rockchip,pins =
46
+ /* can0_rx_m0 */
47
+ <3 RK_PA1 4 &pcfg_pull_none>,
48
+ /* can0_tx_m0 */
49
+ <3 RK_PA0 4 &pcfg_pull_none>;
50
+ };
51
+
52
+ can0m1_pins: can0m1-pins {
53
+ rockchip,pins =
54
+ /* can0_rx_m1 */
55
+ <3 RK_PB7 6 &pcfg_pull_none>,
56
+ /* can0_tx_m1 */
57
+ <3 RK_PB6 6 &pcfg_pull_none>;
58
+ };
59
+
60
+ can0m2_pins: can0m2-pins {
61
+ rockchip,pins =
62
+ /* can0_rx_m2 */
63
+ <0 RK_PC7 2 &pcfg_pull_none>,
64
+ /* can0_tx_m2 */
65
+ <0 RK_PC6 2 &pcfg_pull_none>;
66
+ };
67
+ };
68
+
69
+ can1 {
70
+ can1m0_pins: can1m0-pins {
71
+ rockchip,pins =
72
+ /* can1_rx_m0 */
73
+ <1 RK_PB7 4 &pcfg_pull_none>,
74
+ /* can1_tx_m0 */
75
+ <1 RK_PC0 5 &pcfg_pull_none>;
76
+ };
77
+
78
+ can1m1_pins: can1m1-pins {
79
+ rockchip,pins =
80
+ /* can1_rx_m1 */
81
+ <0 RK_PC1 4 &pcfg_pull_none>,
82
+ /* can1_tx_m1 */
83
+ <0 RK_PC0 4 &pcfg_pull_none>;
84
+ };
85
+ };
86
+
87
+ clk {
88
+ clk_32k_in: clk-32k-in {
89
+ rockchip,pins =
90
+ /* clk_32k_in */
91
+ <0 RK_PB0 1 &pcfg_pull_none>;
92
+ };
93
+ };
94
+
95
+ clk0 {
96
+ clk0_32k_out: clk0-32k-out {
97
+ rockchip,pins =
98
+ /* clk0_32k_out */
99
+ <0 RK_PB0 2 &pcfg_pull_none>;
100
+ };
101
+ };
102
+
103
+ clk1 {
104
+ clk1_32k_out: clk1-32k-out {
105
+ rockchip,pins =
106
+ /* clk1_32k_out */
107
+ <2 RK_PA1 3 &pcfg_pull_none>;
108
+ };
109
+ };
110
+
111
+ cpu {
112
+ cpu_pins: cpu-pins {
113
+ rockchip,pins =
114
+ /* cpu_avs */
115
+ <0 RK_PB7 3 &pcfg_pull_none>;
116
+ };
117
+ };
118
+
119
+ dsm {
120
+ dsm_pins: dsm-pins {
121
+ rockchip,pins =
122
+ /* dsm_aud_ln */
123
+ <1 RK_PB4 5 &pcfg_pull_none>,
124
+ /* dsm_aud_lp */
125
+ <1 RK_PB3 5 &pcfg_pull_none>,
126
+ /* dsm_aud_rn */
127
+ <1 RK_PB6 6 &pcfg_pull_none>,
128
+ /* dsm_aud_rp */
129
+ <1 RK_PB5 6 &pcfg_pull_none>;
130
+ };
131
+ };
132
+
133
+ emmc {
134
+ emmc_bus8: emmc-bus8 {
135
+ rockchip,pins =
136
+ /* emmc_d0 */
137
+ <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
138
+ /* emmc_d1 */
139
+ <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
140
+ /* emmc_d2 */
141
+ <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
142
+ /* emmc_d3 */
143
+ <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
144
+ /* emmc_d4 */
145
+ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
146
+ /* emmc_d5 */
147
+ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
148
+ /* emmc_d6 */
149
+ <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
150
+ /* emmc_d7 */
151
+ <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
152
+ };
153
+
154
+ emmc_clk: emmc-clk {
155
+ rockchip,pins =
156
+ /* emmc_clk */
157
+ <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
158
+ };
159
+
160
+ emmc_cmd: emmc-cmd {
161
+ rockchip,pins =
162
+ /* emmc_cmd */
163
+ <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
164
+ };
165
+
166
+ emmc_strb: emmc-strb {
167
+ rockchip,pins =
168
+ /* emmc_strb */
169
+ <1 RK_PB2 1 &pcfg_pull_none>;
170
+ };
171
+ };
172
+
173
+ eth {
174
+ ethm0_pins: ethm0-pins {
175
+ rockchip,pins =
176
+ /* eth_clk_25m_out_m0 */
177
+ <4 RK_PB1 2 &pcfg_pull_none>;
178
+ };
179
+
180
+ ethm1_pins: ethm1-pins {
181
+ rockchip,pins =
182
+ /* eth_clk_25m_out_m1 */
183
+ <2 RK_PA1 2 &pcfg_pull_none>;
184
+ };
185
+ };
186
+
187
+ fspi {
188
+ fspi_pins: fspi-pins {
189
+ rockchip,pins =
190
+ /* fspi_clk */
191
+ <1 RK_PB1 2 &pcfg_pull_none>,
192
+ /* fspi_d0 */
193
+ <1 RK_PA0 2 &pcfg_pull_none>,
194
+ /* fspi_d1 */
195
+ <1 RK_PA1 2 &pcfg_pull_none>,
196
+ /* fspi_d2 */
197
+ <1 RK_PA2 2 &pcfg_pull_none>,
198
+ /* fspi_d3 */
199
+ <1 RK_PA3 2 &pcfg_pull_none>;
200
+ };
201
+
202
+ fspi_csn0: fspi-csn0 {
203
+ rockchip,pins =
204
+ /* fspi_csn0 */
205
+ <1 RK_PB0 2 &pcfg_pull_none>;
206
+ };
207
+ fspi_csn1: fspi-csn1 {
208
+ rockchip,pins =
209
+ /* fspi_csn1 */
210
+ <1 RK_PB2 2 &pcfg_pull_none>;
211
+ };
212
+ };
213
+
214
+ gpu {
215
+ gpu_pins: gpu-pins {
216
+ rockchip,pins =
217
+ /* gpu_avs */
218
+ <0 RK_PC0 3 &pcfg_pull_none>;
219
+ };
220
+ };
221
+
222
+ i2c0 {
223
+ i2c0_xfer: i2c0-xfer {
224
+ rockchip,pins =
225
+ /* i2c0_scl */
226
+ <0 RK_PB1 1 &pcfg_pull_none_smt>,
227
+ /* i2c0_sda */
228
+ <0 RK_PB2 1 &pcfg_pull_none_smt>;
229
+ };
230
+ };
231
+
232
+ i2c1 {
233
+ i2c1m0_xfer: i2c1m0-xfer {
234
+ rockchip,pins =
235
+ /* i2c1_scl_m0 */
236
+ <0 RK_PB3 1 &pcfg_pull_none_smt>,
237
+ /* i2c1_sda_m0 */
238
+ <0 RK_PB4 1 &pcfg_pull_none_smt>;
239
+ };
240
+
241
+ i2c1m1_xfer: i2c1m1-xfer {
242
+ rockchip,pins =
243
+ /* i2c1_scl_m1 */
244
+ <4 RK_PB4 5 &pcfg_pull_none_smt>,
245
+ /* i2c1_sda_m1 */
246
+ <4 RK_PB5 5 &pcfg_pull_none_smt>;
247
+ };
248
+ };
249
+
250
+ i2c2 {
251
+ i2c2m0_xfer: i2c2m0-xfer {
252
+ rockchip,pins =
253
+ /* i2c2_scl_m0 */
254
+ <0 RK_PB5 1 &pcfg_pull_none_smt>,
255
+ /* i2c2_sda_m0 */
256
+ <0 RK_PB6 1 &pcfg_pull_none_smt>;
257
+ };
258
+
259
+ i2c2m1_xfer: i2c2m1-xfer {
260
+ rockchip,pins =
261
+ /* i2c2_scl_m1 */
262
+ <3 RK_PD2 5 &pcfg_pull_none_smt>,
263
+ /* i2c2_sda_m1 */
264
+ <3 RK_PD3 5 &pcfg_pull_none_smt>;
265
+ };
266
+ };
267
+
268
+ i2c3 {
269
+ i2c3m0_xfer: i2c3m0-xfer {
270
+ rockchip,pins =
271
+ /* i2c3_scl_m0 */
272
+ <3 RK_PA0 1 &pcfg_pull_none_smt>,
273
+ /* i2c3_sda_m0 */
274
+ <3 RK_PA1 1 &pcfg_pull_none_smt>;
275
+ };
276
+
277
+ i2c3m1_xfer: i2c3m1-xfer {
278
+ rockchip,pins =
279
+ /* i2c3_scl_m1 */
280
+ <4 RK_PA5 5 &pcfg_pull_none_smt>,
281
+ /* i2c3_sda_m1 */
282
+ <4 RK_PA6 5 &pcfg_pull_none_smt>;
283
+ };
284
+ };
285
+
286
+ i2c4 {
287
+ i2c4m0_xfer: i2c4m0-xfer {
288
+ rockchip,pins =
289
+ /* i2c4_scl_m0 */
290
+ <3 RK_PB6 5 &pcfg_pull_none_smt>,
291
+ /* i2c4_sda_m0 */
292
+ <3 RK_PB7 5 &pcfg_pull_none_smt>;
293
+ };
294
+
295
+ i2c4m1_xfer: i2c4m1-xfer {
296
+ rockchip,pins =
297
+ /* i2c4_scl_m1 */
298
+ <0 RK_PA5 2 &pcfg_pull_none_smt>,
299
+ /* i2c4_sda_m1 */
300
+ <0 RK_PA4 2 &pcfg_pull_none_smt>;
301
+ };
302
+ };
303
+
304
+ i2c5 {
305
+ i2c5m0_xfer: i2c5m0-xfer {
306
+ rockchip,pins =
307
+ /* i2c5_scl_m0 */
308
+ <3 RK_PC2 1 &pcfg_pull_none_smt>,
309
+ /* i2c5_sda_m0 */
310
+ <3 RK_PC3 1 &pcfg_pull_none_smt>;
311
+ };
312
+
313
+ i2c5m1_xfer: i2c5m1-xfer {
314
+ rockchip,pins =
315
+ /* i2c5_scl_m1 */
316
+ <1 RK_PC7 4 &pcfg_pull_none_smt>,
317
+ /* i2c5_sda_m1 */
318
+ <1 RK_PD0 4 &pcfg_pull_none_smt>;
319
+ };
320
+ };
321
+
322
+ i2s0 {
323
+ i2s0m0_lrck: i2s0m0-lrck {
324
+ rockchip,pins =
325
+ /* i2s0_lrck_m0 */
326
+ <3 RK_PA4 1 &pcfg_pull_none>;
327
+ };
328
+
329
+ i2s0m0_mclk: i2s0m0-mclk {
330
+ rockchip,pins =
331
+ /* i2s0_mclk_m0 */
332
+ <3 RK_PA2 1 &pcfg_pull_none>;
333
+ };
334
+
335
+ i2s0m0_sclk: i2s0m0-sclk {
336
+ rockchip,pins =
337
+ /* i2s0_sclk_m0 */
338
+ <3 RK_PA3 1 &pcfg_pull_none>;
339
+ };
340
+
341
+ i2s0m0_sdi0: i2s0m0-sdi0 {
342
+ rockchip,pins =
343
+ /* i2s0_sdi0_m0 */
344
+ <3 RK_PB1 1 &pcfg_pull_none>;
345
+ };
346
+
347
+ i2s0m0_sdi1: i2s0m0-sdi1 {
348
+ rockchip,pins =
349
+ /* i2s0_sdi1_m0 */
350
+ <3 RK_PB0 2 &pcfg_pull_none>;
351
+ };
352
+
353
+ i2s0m0_sdi2: i2s0m0-sdi2 {
354
+ rockchip,pins =
355
+ /* i2s0_sdi2_m0 */
356
+ <3 RK_PA7 2 &pcfg_pull_none>;
357
+ };
358
+
359
+ i2s0m0_sdi3: i2s0m0-sdi3 {
360
+ rockchip,pins =
361
+ /* i2s0_sdi3_m0 */
362
+ <3 RK_PA6 2 &pcfg_pull_none>;
363
+ };
364
+
365
+ i2s0m0_sdo0: i2s0m0-sdo0 {
366
+ rockchip,pins =
367
+ /* i2s0_sdo0_m0 */
368
+ <3 RK_PA5 1 &pcfg_pull_none>;
369
+ };
370
+
371
+ i2s0m0_sdo1: i2s0m0-sdo1 {
372
+ rockchip,pins =
373
+ /* i2s0_sdo1_m0 */
374
+ <3 RK_PA6 1 &pcfg_pull_none>;
375
+ };
376
+
377
+ i2s0m0_sdo2: i2s0m0-sdo2 {
378
+ rockchip,pins =
379
+ /* i2s0_sdo2_m0 */
380
+ <3 RK_PA7 1 &pcfg_pull_none>;
381
+ };
382
+
383
+ i2s0m0_sdo3: i2s0m0-sdo3 {
384
+ rockchip,pins =
385
+ /* i2s0_sdo3_m0 */
386
+ <3 RK_PB0 1 &pcfg_pull_none>;
387
+ };
388
+
389
+ i2s0m1_lrck: i2s0m1-lrck {
390
+ rockchip,pins =
391
+ /* i2s0_lrck_m1 */
392
+ <1 RK_PC4 3 &pcfg_pull_none>;
393
+ };
394
+
395
+ i2s0m1_mclk: i2s0m1-mclk {
396
+ rockchip,pins =
397
+ /* i2s0_mclk_m1 */
398
+ <1 RK_PC6 3 &pcfg_pull_none>;
399
+ };
400
+
401
+ i2s0m1_sclk: i2s0m1-sclk {
402
+ rockchip,pins =
403
+ /* i2s0_sclk_m1 */
404
+ <1 RK_PC5 3 &pcfg_pull_none>;
405
+ };
406
+
407
+ i2s0m1_sdi0: i2s0m1-sdi0 {
408
+ rockchip,pins =
409
+ /* i2s0_sdi0_m1 */
410
+ <1 RK_PC1 3 &pcfg_pull_none>;
411
+ };
412
+
413
+ i2s0m1_sdi1: i2s0m1-sdi1 {
414
+ rockchip,pins =
415
+ /* i2s0_sdi1_m1 */
416
+ <1 RK_PC2 3 &pcfg_pull_none>;
417
+ };
418
+
419
+ i2s0m1_sdi2: i2s0m1-sdi2 {
420
+ rockchip,pins =
421
+ /* i2s0_sdi2_m1 */
422
+ <1 RK_PD3 3 &pcfg_pull_none>;
423
+ };
424
+
425
+ i2s0m1_sdi3: i2s0m1-sdi3 {
426
+ rockchip,pins =
427
+ /* i2s0_sdi3_m1 */
428
+ <1 RK_PD4 3 &pcfg_pull_none>;
429
+ };
430
+
431
+ i2s0m1_sdo0: i2s0m1-sdo0 {
432
+ rockchip,pins =
433
+ /* i2s0_sdo0_m1 */
434
+ <1 RK_PC3 3 &pcfg_pull_none>;
435
+ };
436
+
437
+ i2s0m1_sdo1: i2s0m1-sdo1 {
438
+ rockchip,pins =
439
+ /* i2s0_sdo1_m1 */
440
+ <1 RK_PD1 3 &pcfg_pull_none>;
441
+ };
442
+
443
+ i2s0m1_sdo2: i2s0m1-sdo2 {
444
+ rockchip,pins =
445
+ /* i2s0_sdo2_m1 */
446
+ <1 RK_PD2 3 &pcfg_pull_none>;
447
+ };
448
+
449
+ i2s0m1_sdo3: i2s0m1-sdo3 {
450
+ rockchip,pins =
451
+ /* i2s0_sdo3_m1 */
452
+ <2 RK_PA1 5 &pcfg_pull_none>;
453
+ };
454
+ };
455
+
456
+ i2s1 {
457
+ i2s1m0_lrck: i2s1m0-lrck {
458
+ rockchip,pins =
459
+ /* i2s1_lrck_m0 */
460
+ <3 RK_PC6 2 &pcfg_pull_none>;
461
+ };
462
+
463
+ i2s1m0_mclk: i2s1m0-mclk {
464
+ rockchip,pins =
465
+ /* i2s1_mclk_m0 */
466
+ <3 RK_PC4 2 &pcfg_pull_none>;
467
+ };
468
+
469
+ i2s1m0_sclk: i2s1m0-sclk {
470
+ rockchip,pins =
471
+ /* i2s1_sclk_m0 */
472
+ <3 RK_PC5 2 &pcfg_pull_none>;
473
+ };
474
+
475
+ i2s1m0_sdi0: i2s1m0-sdi0 {
476
+ rockchip,pins =
477
+ /* i2s1_sdi0_m0 */
478
+ <3 RK_PD0 2 &pcfg_pull_none>;
479
+ };
480
+
481
+ i2s1m0_sdi1: i2s1m0-sdi1 {
482
+ rockchip,pins =
483
+ /* i2s1_sdi1_m0 */
484
+ <3 RK_PD1 2 &pcfg_pull_none>;
485
+ };
486
+
487
+ i2s1m0_sdi2: i2s1m0-sdi2 {
488
+ rockchip,pins =
489
+ /* i2s1_sdi2_m0 */
490
+ <3 RK_PD2 2 &pcfg_pull_none>;
491
+ };
492
+
493
+ i2s1m0_sdi3: i2s1m0-sdi3 {
494
+ rockchip,pins =
495
+ /* i2s1_sdi3_m0 */
496
+ <3 RK_PD3 2 &pcfg_pull_none>;
497
+ };
498
+
499
+ i2s1m0_sdo0: i2s1m0-sdo0 {
500
+ rockchip,pins =
501
+ /* i2s1_sdo0_m0 */
502
+ <3 RK_PC7 2 &pcfg_pull_none>;
503
+ };
504
+
505
+ i2s1m0_sdo1: i2s1m0-sdo1 {
506
+ rockchip,pins =
507
+ /* i2s1_sdo1_m0 */
508
+ <4 RK_PB4 2 &pcfg_pull_none>;
509
+ };
510
+
511
+ i2s1m0_sdo2: i2s1m0-sdo2 {
512
+ rockchip,pins =
513
+ /* i2s1_sdo2_m0 */
514
+ <4 RK_PB5 2 &pcfg_pull_none>;
515
+ };
516
+
517
+ i2s1m0_sdo3: i2s1m0-sdo3 {
518
+ rockchip,pins =
519
+ /* i2s1_sdo3_m0 */
520
+ <4 RK_PB6 2 &pcfg_pull_none>;
521
+ };
522
+
523
+ i2s1m1_lrck: i2s1m1-lrck {
524
+ rockchip,pins =
525
+ /* i2s1_lrck_m1 */
526
+ <3 RK_PB4 1 &pcfg_pull_none>;
527
+ };
528
+
529
+ i2s1m1_mclk: i2s1m1-mclk {
530
+ rockchip,pins =
531
+ /* i2s1_mclk_m1 */
532
+ <3 RK_PB2 1 &pcfg_pull_none>;
533
+ };
534
+
535
+ i2s1m1_sclk: i2s1m1-sclk {
536
+ rockchip,pins =
537
+ /* i2s1_sclk_m1 */
538
+ <3 RK_PB3 1 &pcfg_pull_none>;
539
+ };
540
+
541
+ i2s1m1_sdi0: i2s1m1-sdi0 {
542
+ rockchip,pins =
543
+ /* i2s1_sdi0_m1 */
544
+ <3 RK_PC1 1 &pcfg_pull_none>;
545
+ };
546
+
547
+ i2s1m1_sdi1: i2s1m1-sdi1 {
548
+ rockchip,pins =
549
+ /* i2s1_sdi1_m1 */
550
+ <3 RK_PC0 2 &pcfg_pull_none>;
551
+ };
552
+
553
+ i2s1m1_sdi2: i2s1m1-sdi2 {
554
+ rockchip,pins =
555
+ /* i2s1_sdi2_m1 */
556
+ <3 RK_PB7 2 &pcfg_pull_none>;
557
+ };
558
+
559
+ i2s1m1_sdi3: i2s1m1-sdi3 {
560
+ rockchip,pins =
561
+ /* i2s1_sdi3_m1 */
562
+ <3 RK_PB6 2 &pcfg_pull_none>;
563
+ };
564
+
565
+ i2s1m1_sdo0: i2s1m1-sdo0 {
566
+ rockchip,pins =
567
+ /* i2s1_sdo0_m1 */
568
+ <3 RK_PB5 1 &pcfg_pull_none>;
569
+ };
570
+
571
+ i2s1m1_sdo1: i2s1m1-sdo1 {
572
+ rockchip,pins =
573
+ /* i2s1_sdo1_m1 */
574
+ <3 RK_PB6 1 &pcfg_pull_none>;
575
+ };
576
+
577
+ i2s1m1_sdo2: i2s1m1-sdo2 {
578
+ rockchip,pins =
579
+ /* i2s1_sdo2_m1 */
580
+ <3 RK_PB7 1 &pcfg_pull_none>;
581
+ };
582
+
583
+ i2s1m1_sdo3: i2s1m1-sdo3 {
584
+ rockchip,pins =
585
+ /* i2s1_sdo3_m1 */
586
+ <3 RK_PC0 1 &pcfg_pull_none>;
587
+ };
588
+ };
589
+
590
+ i2s2 {
591
+ i2s2m0_lrck: i2s2m0-lrck {
592
+ rockchip,pins =
593
+ /* i2s2_lrck_m0 */
594
+ <1 RK_PD6 1 &pcfg_pull_none>;
595
+ };
596
+
597
+ i2s2m0_mclk: i2s2m0-mclk {
598
+ rockchip,pins =
599
+ /* i2s2_mclk_m0 */
600
+ <2 RK_PA1 1 &pcfg_pull_none>;
601
+ };
602
+
603
+ i2s2m0_sclk: i2s2m0-sclk {
604
+ rockchip,pins =
605
+ /* i2s2_sclk_m0 */
606
+ <1 RK_PD5 1 &pcfg_pull_none>;
607
+ };
608
+
609
+ i2s2m0_sdi: i2s2m0-sdi {
610
+ rockchip,pins =
611
+ /* i2s2_sdi_m0 */
612
+ <2 RK_PA0 1 &pcfg_pull_none>;
613
+ };
614
+
615
+ i2s2m0_sdo: i2s2m0-sdo {
616
+ rockchip,pins =
617
+ /* i2s2_sdo_m0 */
618
+ <1 RK_PD7 1 &pcfg_pull_none>;
619
+ };
620
+
621
+ i2s2m1_lrck: i2s2m1-lrck {
622
+ rockchip,pins =
623
+ /* i2s2_lrck_m1 */
624
+ <4 RK_PA1 3 &pcfg_pull_none>;
625
+ };
626
+
627
+ i2s2m1_mclk: i2s2m1-mclk {
628
+ rockchip,pins =
629
+ /* i2s2_mclk_m1 */
630
+ <3 RK_PD6 3 &pcfg_pull_none>;
631
+ };
632
+
633
+ i2s2m1_sclk: i2s2m1-sclk {
634
+ rockchip,pins =
635
+ /* i2s2_sclk_m1 */
636
+ <4 RK_PB1 4 &pcfg_pull_none>;
637
+ };
638
+
639
+ i2s2m1_sdi: i2s2m1-sdi {
640
+ rockchip,pins =
641
+ /* i2s2_sdi_m1 */
642
+ <3 RK_PD4 4 &pcfg_pull_none>;
643
+ };
644
+
645
+ i2s2m1_sdo: i2s2m1-sdo {
646
+ rockchip,pins =
647
+ /* i2s2_sdo_m1 */
648
+ <3 RK_PD5 4 &pcfg_pull_none>;
649
+ };
650
+ };
651
+
652
+ isp {
653
+ isp_pins: isp-pins {
654
+ rockchip,pins =
655
+ /* isp_flash_trigin */
656
+ <3 RK_PC1 2 &pcfg_pull_none>,
657
+ /* isp_flash_trigout */
658
+ <3 RK_PC3 2 &pcfg_pull_none>,
659
+ /* isp_prelight_trigout */
660
+ <3 RK_PC2 2 &pcfg_pull_none>;
661
+ };
662
+ };
663
+
664
+ jtag {
665
+ jtagm0_pins: jtagm0-pins {
666
+ rockchip,pins =
667
+ /* jtag_cpu_mcu_tck_m0 */
668
+ <0 RK_PD1 2 &pcfg_pull_none>,
669
+ /* jtag_cpu_mcu_tms_m0 */
670
+ <0 RK_PD0 2 &pcfg_pull_none>;
671
+ };
672
+
673
+ jtagm1_pins: jtagm1-pins {
674
+ rockchip,pins =
675
+ /* jtag_cpu_mcu_tck_m1 */
676
+ <1 RK_PB5 2 &pcfg_pull_none>,
677
+ /* jtag_cpu_mcu_tms_m1 */
678
+ <1 RK_PB6 2 &pcfg_pull_none>;
679
+ };
680
+ };
681
+
682
+ npu {
683
+ npu_pins: npu-pins {
684
+ rockchip,pins =
685
+ /* npu_avs */
686
+ <0 RK_PC1 3 &pcfg_pull_none>;
687
+ };
688
+ };
689
+
690
+ pcie20 {
691
+ pcie20m0_pins: pcie20m0-pins {
692
+ rockchip,pins =
693
+ /* pcie20_clkreqn_m0 */
694
+ <0 RK_PA6 1 &pcfg_pull_none>,
695
+ /* pcie20_perstn_m0 */
696
+ <0 RK_PB5 2 &pcfg_pull_none>,
697
+ /* pcie20_waken_m0 */
698
+ <0 RK_PB6 2 &pcfg_pull_none>;
699
+ };
700
+
701
+ pcie20m1_pins: pcie20m1-pins {
702
+ rockchip,pins =
703
+ /* pcie20_clkreqn_m1 */
704
+ <3 RK_PA6 4 &pcfg_pull_none>,
705
+ /* pcie20_perstn_m1 */
706
+ <3 RK_PB0 4 &pcfg_pull_none>,
707
+ /* pcie20_waken_m1 */
708
+ <3 RK_PA7 4 &pcfg_pull_none>;
709
+ };
710
+
711
+ pcie20_buttonrstn: pcie20-buttonrstn {
712
+ rockchip,pins =
713
+ /* pcie20_buttonrstn */
714
+ <0 RK_PB0 3 &pcfg_pull_none>;
715
+ };
716
+ };
717
+
718
+ pdm {
719
+ pdmm0_clk0: pdmm0-clk0 {
720
+ rockchip,pins =
721
+ /* pdm_clk0_m0 */
722
+ <3 RK_PA6 3 &pcfg_pull_none>;
723
+ };
724
+
725
+ pdmm0_clk1: pdmm0-clk1 {
726
+ rockchip,pins =
727
+ /* pdm_clk1_m0 */
728
+ <3 RK_PA2 3 &pcfg_pull_none>;
729
+ };
730
+
731
+ pdmm0_sdi0: pdmm0-sdi0 {
732
+ rockchip,pins =
733
+ /* pdm_sdi0_m0 */
734
+ <3 RK_PB1 2 &pcfg_pull_none>;
735
+ };
736
+
737
+ pdmm0_sdi1: pdmm0-sdi1 {
738
+ rockchip,pins =
739
+ /* pdm_sdi1_m0 */
740
+ <3 RK_PB0 3 &pcfg_pull_none>;
741
+ };
742
+
743
+ pdmm0_sdi2: pdmm0-sdi2 {
744
+ rockchip,pins =
745
+ /* pdm_sdi2_m0 */
746
+ <3 RK_PA7 3 &pcfg_pull_none>;
747
+ };
748
+
749
+ pdmm0_sdi3: pdmm0-sdi3 {
750
+ rockchip,pins =
751
+ /* pdm_sdi3_m0 */
752
+ <3 RK_PA0 3 &pcfg_pull_none>;
753
+ };
754
+
755
+ pdmm1_clk0: pdmm1-clk0 {
756
+ rockchip,pins =
757
+ /* pdm_clk0_m1 */
758
+ <4 RK_PB7 4 &pcfg_pull_none>;
759
+ };
760
+
761
+ pdmm1_clk1: pdmm1-clk1 {
762
+ rockchip,pins =
763
+ /* pdm_clk1_m1 */
764
+ <4 RK_PB1 5 &pcfg_pull_none>;
765
+ };
766
+
767
+ pdmm1_sdi0: pdmm1-sdi0 {
768
+ rockchip,pins =
769
+ /* pdm_sdi0_m1 */
770
+ <4 RK_PA7 4 &pcfg_pull_none>;
771
+ };
772
+
773
+ pdmm1_sdi1: pdmm1-sdi1 {
774
+ rockchip,pins =
775
+ /* pdm_sdi1_m1 */
776
+ <4 RK_PB0 4 &pcfg_pull_none>;
777
+ };
778
+
779
+ pdmm1_sdi2: pdmm1-sdi2 {
780
+ rockchip,pins =
781
+ /* pdm_sdi2_m1 */
782
+ <4 RK_PA5 4 &pcfg_pull_none>;
783
+ };
784
+
785
+ pdmm1_sdi3: pdmm1-sdi3 {
786
+ rockchip,pins =
787
+ /* pdm_sdi3_m1 */
788
+ <4 RK_PA6 4 &pcfg_pull_none>;
789
+ };
790
+ };
791
+
792
+ pmic {
793
+ pmic_int: pmic-int {
794
+ rockchip,pins =
795
+ <0 RK_PA3 0 &pcfg_pull_up>;
796
+ };
797
+
798
+ soc_slppin_gpio: soc-slppin-gpio {
799
+ rockchip,pins =
800
+ <0 RK_PA2 0 &pcfg_output_low>;
801
+ };
802
+
803
+ soc_slppin_slp: soc-slppin-slp {
804
+ rockchip,pins =
805
+ <0 RK_PA2 1 &pcfg_pull_none>;
806
+ };
807
+ };
808
+
809
+ pmu {
810
+ pmu_pins: pmu-pins {
811
+ rockchip,pins =
812
+ /* pmu_debug */
813
+ <0 RK_PA5 3 &pcfg_pull_none>;
814
+ };
815
+ };
816
+
817
+ pwm0 {
818
+ pwm0m0_pins: pwm0m0-pins {
819
+ rockchip,pins =
820
+ /* pwm0_m0 */
821
+ <0 RK_PC3 2 &pcfg_pull_none>;
822
+ };
823
+
824
+ pwm0m1_pins: pwm0m1-pins {
825
+ rockchip,pins =
826
+ /* pwm0_m1 */
827
+ <1 RK_PC5 4 &pcfg_pull_none>;
828
+ };
829
+ };
830
+
831
+ pwm1 {
832
+ pwm1m0_pins: pwm1m0-pins {
833
+ rockchip,pins =
834
+ /* pwm1_m0 */
835
+ <0 RK_PC4 2 &pcfg_pull_none>;
836
+ };
837
+
838
+ pwm1m1_pins: pwm1m1-pins {
839
+ rockchip,pins =
840
+ /* pwm1_m1 */
841
+ <1 RK_PC6 4 &pcfg_pull_none>;
842
+ };
843
+ };
844
+
845
+ pwm2 {
846
+ pwm2m0_pins: pwm2m0-pins {
847
+ rockchip,pins =
848
+ /* pwm2_m0 */
849
+ <0 RK_PC5 2 &pcfg_pull_none>;
850
+ };
851
+
852
+ pwm2m1_pins: pwm2m1-pins {
853
+ rockchip,pins =
854
+ /* pwm2_m1 */
855
+ <1 RK_PC7 3 &pcfg_pull_none>;
856
+ };
857
+ };
858
+
859
+ pwm3 {
860
+ pwm3m0_pins: pwm3m0-pins {
861
+ rockchip,pins =
862
+ /* pwm3_m0 */
863
+ <0 RK_PA7 1 &pcfg_pull_none>;
864
+ };
865
+
866
+ pwm3m1_pins: pwm3m1-pins {
867
+ rockchip,pins =
868
+ /* pwm3_m1 */
869
+ <1 RK_PD0 3 &pcfg_pull_none>;
870
+ };
871
+ };
872
+
873
+ pwm4 {
874
+ pwm4m0_pins: pwm4m0-pins {
875
+ rockchip,pins =
876
+ /* pwm4_m0 */
877
+ <0 RK_PB7 2 &pcfg_pull_none>;
878
+ };
879
+
880
+ pwm4m1_pins: pwm4m1-pins {
881
+ rockchip,pins =
882
+ /* pwm4_m1 */
883
+ <1 RK_PD1 4 &pcfg_pull_none>;
884
+ };
885
+ };
886
+
887
+ pwm5 {
888
+ pwm5m0_pins: pwm5m0-pins {
889
+ rockchip,pins =
890
+ /* pwm5_m0 */
891
+ <0 RK_PC2 2 &pcfg_pull_none>;
892
+ };
893
+
894
+ pwm5m1_pins: pwm5m1-pins {
895
+ rockchip,pins =
896
+ /* pwm5_m1 */
897
+ <1 RK_PD2 4 &pcfg_pull_none>;
898
+ };
899
+ };
900
+
901
+ pwm6 {
902
+ pwm6m0_pins: pwm6m0-pins {
903
+ rockchip,pins =
904
+ /* pwm6_m0 */
905
+ <0 RK_PC1 2 &pcfg_pull_none>;
906
+ };
907
+
908
+ pwm6m1_pins: pwm6m1-pins {
909
+ rockchip,pins =
910
+ /* pwm6_m1 */
911
+ <1 RK_PD3 4 &pcfg_pull_none>;
912
+ };
913
+ };
914
+
915
+ pwm7 {
916
+ pwm7m0_pins: pwm7m0-pins {
917
+ rockchip,pins =
918
+ /* pwm7_m0 */
919
+ <0 RK_PC0 2 &pcfg_pull_none>;
920
+ };
921
+
922
+ pwm7m1_pins: pwm7m1-pins {
923
+ rockchip,pins =
924
+ /* pwm7_m1 */
925
+ <1 RK_PD4 4 &pcfg_pull_none>;
926
+ };
927
+ };
928
+
929
+ pwm8 {
930
+ pwm8m0_pins: pwm8m0-pins {
931
+ rockchip,pins =
932
+ /* pwm8_m0 */
933
+ <3 RK_PA4 2 &pcfg_pull_none>;
934
+ };
935
+
936
+ pwm8m1_pins: pwm8m1-pins {
937
+ rockchip,pins =
938
+ /* pwm8_m1 */
939
+ <1 RK_PC1 4 &pcfg_pull_none>;
940
+ };
941
+ };
942
+
943
+ pwm9 {
944
+ pwm9m0_pins: pwm9m0-pins {
945
+ rockchip,pins =
946
+ /* pwm9_m0 */
947
+ <3 RK_PA5 2 &pcfg_pull_none>;
948
+ };
949
+
950
+ pwm9m1_pins: pwm9m1-pins {
951
+ rockchip,pins =
952
+ /* pwm9_m1 */
953
+ <1 RK_PC2 4 &pcfg_pull_none>;
954
+ };
955
+ };
956
+
957
+ pwm10 {
958
+ pwm10m0_pins: pwm10m0-pins {
959
+ rockchip,pins =
960
+ /* pwm10_m0 */
961
+ <1 RK_PB5 5 &pcfg_pull_none>;
962
+ };
963
+
964
+ pwm10m1_pins: pwm10m1-pins {
965
+ rockchip,pins =
966
+ /* pwm10_m1 */
967
+ <1 RK_PC3 4 &pcfg_pull_none>;
968
+ };
969
+ };
970
+
971
+ pwm11 {
972
+ pwm11m0_pins: pwm11m0-pins {
973
+ rockchip,pins =
974
+ /* pwm11_m0 */
975
+ <1 RK_PB6 5 &pcfg_pull_none>;
976
+ };
977
+
978
+ pwm11m1_pins: pwm11m1-pins {
979
+ rockchip,pins =
980
+ /* pwm11_m1 */
981
+ <1 RK_PC4 4 &pcfg_pull_none>;
982
+ };
983
+ };
984
+
985
+ pwm12 {
986
+ pwm12m0_pins: pwm12m0-pins {
987
+ rockchip,pins =
988
+ /* pwm12_m0 */
989
+ <4 RK_PA1 4 &pcfg_pull_none>;
990
+ };
991
+
992
+ pwm12m1_pins: pwm12m1-pins {
993
+ rockchip,pins =
994
+ /* pwm12_m1 */
995
+ <3 RK_PB4 5 &pcfg_pull_none>;
996
+ };
997
+ };
998
+
999
+ pwm13 {
1000
+ pwm13m0_pins: pwm13m0-pins {
1001
+ rockchip,pins =
1002
+ /* pwm13_m0 */
1003
+ <4 RK_PA4 3 &pcfg_pull_none>;
1004
+ };
1005
+
1006
+ pwm13m1_pins: pwm13m1-pins {
1007
+ rockchip,pins =
1008
+ /* pwm13_m1 */
1009
+ <3 RK_PB5 5 &pcfg_pull_none>;
1010
+ };
1011
+ };
1012
+
1013
+ pwm14 {
1014
+ pwm14m0_pins: pwm14m0-pins {
1015
+ rockchip,pins =
1016
+ /* pwm14_m0 */
1017
+ <3 RK_PC5 4 &pcfg_pull_none>;
1018
+ };
1019
+
1020
+ pwm14m1_pins: pwm14m1-pins {
1021
+ rockchip,pins =
1022
+ /* pwm14_m1 */
1023
+ <1 RK_PD7 5 &pcfg_pull_none>;
1024
+ };
1025
+ };
1026
+
1027
+ pwm15 {
1028
+ pwm15m0_pins: pwm15m0-pins {
1029
+ rockchip,pins =
1030
+ /* pwm15_m0 */
1031
+ <3 RK_PC6 4 &pcfg_pull_none>;
1032
+ };
1033
+
1034
+ pwm15m1_pins: pwm15m1-pins {
1035
+ rockchip,pins =
1036
+ /* pwm15_m1 */
1037
+ <2 RK_PA0 5 &pcfg_pull_none>;
1038
+ };
1039
+ };
1040
+
1041
+ pwr {
1042
+ pwr_pins: pwr-pins {
1043
+ rockchip,pins =
1044
+ /* pwr_ctrl0 */
1045
+ <0 RK_PA2 1 &pcfg_pull_none>,
1046
+ /* pwr_ctrl1 */
1047
+ <0 RK_PA3 1 &pcfg_pull_none>;
1048
+ };
1049
+ };
1050
+
1051
+ ref {
1052
+ ref_pins: ref-pins {
1053
+ rockchip,pins =
1054
+ /* ref_clk_out */
1055
+ <0 RK_PA0 1 &pcfg_pull_none>;
1056
+ };
1057
+ };
1058
+
1059
+ rgmii {
1060
+ rgmiim0_miim: rgmiim0-miim {
1061
+ rockchip,pins =
1062
+ /* rgmii_mdc_m0 */
1063
+ <4 RK_PB2 2 &pcfg_pull_none>,
1064
+ /* rgmii_mdio_m0 */
1065
+ <4 RK_PB3 2 &pcfg_pull_none>;
1066
+ };
1067
+
1068
+ rgmiim0_rx_er: rgmiim0-rx_er {
1069
+ rockchip,pins =
1070
+ /* rgmii_rxer_m0 */
1071
+ <4 RK_PB0 2 &pcfg_pull_none>;
1072
+ };
1073
+
1074
+ rgmiim0_rx_bus2: rgmiim0-rx_bus2 {
1075
+ rockchip,pins =
1076
+ /* rgmii_rxd0_m0 */
1077
+ <4 RK_PA5 2 &pcfg_pull_none>,
1078
+ /* rgmii_rxd1_m0 */
1079
+ <4 RK_PA6 2 &pcfg_pull_none>,
1080
+ /* rgmii_rxdv_m0 */
1081
+ <4 RK_PA7 2 &pcfg_pull_none>;
1082
+ };
1083
+
1084
+ rgmiim0_tx_bus2: rgmiim0-tx_bus2 {
1085
+ rockchip,pins =
1086
+ /* rgmii_txd0_m0 */
1087
+ <4 RK_PA2 2 &pcfg_pull_none>,
1088
+ /* rgmii_txd1_m0 */
1089
+ <4 RK_PA3 2 &pcfg_pull_none>,
1090
+ /* rgmii_txen_m0 */
1091
+ <4 RK_PA4 2 &pcfg_pull_none>;
1092
+ };
1093
+
1094
+ rgmiim0_rgmii_clk: rgmiim0-rgmii_clk {
1095
+ rockchip,pins =
1096
+ /* rgmii_rxclk_m0 */
1097
+ <4 RK_PA1 2 &pcfg_pull_none>,
1098
+ /* rgmii_txclk_m0 */
1099
+ <3 RK_PD6 2 &pcfg_pull_none>;
1100
+ };
1101
+
1102
+ rgmiim0_rgmii_bus: rgmiim0-rgmii_bus {
1103
+ rockchip,pins =
1104
+ /* rgmii_rxd2_m0 */
1105
+ <3 RK_PD7 2 &pcfg_pull_none>,
1106
+ /* rgmii_rxd3_m0 */
1107
+ <4 RK_PA0 2 &pcfg_pull_none>,
1108
+ /* rgmii_txd2_m0 */
1109
+ <3 RK_PD4 2 &pcfg_pull_none>,
1110
+ /* rgmii_txd3_m0 */
1111
+ <3 RK_PD5 2 &pcfg_pull_none>;
1112
+ };
1113
+
1114
+ rgmiim0_clk: rgmiim0-clk {
1115
+ rockchip,pins =
1116
+ /* rgmiim0_clk */
1117
+ <4 RK_PB7 2 &pcfg_pull_none>;
1118
+ };
1119
+
1120
+ rgmiim1_miim: rgmiim1-miim {
1121
+ rockchip,pins =
1122
+ /* rgmii_mdc_m1 */
1123
+ <1 RK_PC7 2 &pcfg_pull_none>,
1124
+ /* rgmii_mdio_m1 */
1125
+ <1 RK_PD0 2 &pcfg_pull_none>;
1126
+ };
1127
+
1128
+ rgmiim1_rx_er: rgmiim1-rx_er {
1129
+ rockchip,pins =
1130
+ /* rgmii_rxer_m1 */
1131
+ <2 RK_PA0 2 &pcfg_pull_none>;
1132
+ };
1133
+
1134
+ rgmiim1_rx_bus2: rgmiim1-rx_bus2 {
1135
+ rockchip,pins =
1136
+ /* rgmii_rxd0_m1 */
1137
+ <1 RK_PD4 2 &pcfg_pull_none>,
1138
+ /* rgmii_rxd1_m1 */
1139
+ <1 RK_PD7 2 &pcfg_pull_none>,
1140
+ /* rgmii_rxdv_m1 */
1141
+ <1 RK_PD6 2 &pcfg_pull_none>;
1142
+ };
1143
+
1144
+ rgmiim1_tx_bus2: rgmiim1-tx_bus2 {
1145
+ rockchip,pins =
1146
+ /* rgmii_txd0_m1 */
1147
+ <1 RK_PD1 2 &pcfg_pull_none>,
1148
+ /* rgmii_txd1_m1 */
1149
+ <1 RK_PD2 2 &pcfg_pull_none>,
1150
+ /* rgmii_txen_m1 */
1151
+ <1 RK_PD3 2 &pcfg_pull_none>;
1152
+ };
1153
+
1154
+ rgmiim1_rgmii_clk: rgmiim1-rgmii_clk {
1155
+ rockchip,pins =
1156
+ /* rgmii_rxclk_m1 */
1157
+ <1 RK_PC6 2 &pcfg_pull_none>,
1158
+ /* rgmii_txclk_m1 */
1159
+ <1 RK_PC3 2 &pcfg_pull_none>;
1160
+ };
1161
+
1162
+ rgmiim1_rgmii_bus: rgmiim1-rgmii_bus {
1163
+ rockchip,pins =
1164
+ /* rgmii_rxd2_m1 */
1165
+ <1 RK_PC4 2 &pcfg_pull_none>,
1166
+ /* rgmii_rxd3_m1 */
1167
+ <1 RK_PC5 2 &pcfg_pull_none>,
1168
+ /* rgmii_txd2_m1 */
1169
+ <1 RK_PC1 2 &pcfg_pull_none>,
1170
+ /* rgmii_txd3_m1 */
1171
+ <1 RK_PC2 2 &pcfg_pull_none>;
1172
+ };
1173
+
1174
+ rgmiim1_clk: rgmiim1-clk {
1175
+ rockchip,pins =
1176
+ /* rgmiim1_clk */
1177
+ <1 RK_PD5 2 &pcfg_pull_none>;
1178
+ };
1179
+ };
1180
+
1181
+ rmii {
1182
+ rmii_pins: rmii-pins {
1183
+ rockchip,pins =
1184
+ /* rmii_clk */
1185
+ <1 RK_PD5 5 &pcfg_pull_none>,
1186
+ /* rmii_mdc */
1187
+ <1 RK_PC7 5 &pcfg_pull_none>,
1188
+ /* rmii_mdio */
1189
+ <1 RK_PD0 5 &pcfg_pull_none>,
1190
+ /* rmii_rxd0 */
1191
+ <1 RK_PD4 5 &pcfg_pull_none>,
1192
+ /* rmii_rxd1 */
1193
+ <1 RK_PD7 6 &pcfg_pull_none>,
1194
+ /* rmii_rxdv_crs */
1195
+ <1 RK_PD6 5 &pcfg_pull_none>,
1196
+ /* rmii_rxer */
1197
+ <2 RK_PA0 6 &pcfg_pull_none>,
1198
+ /* rmii_txd0 */
1199
+ <1 RK_PD1 5 &pcfg_pull_none>,
1200
+ /* rmii_txd1 */
1201
+ <1 RK_PD2 5 &pcfg_pull_none>,
1202
+ /* rmii_txen */
1203
+ <1 RK_PD3 5 &pcfg_pull_none>;
1204
+ };
1205
+ };
1206
+
1207
+ sdmmc0_pins: sdmmc0-pins {
1208
+ sdmmc0_bus4: sdmmc0-bus4 {
1209
+ rockchip,pins =
1210
+ /* sdmmc0_d0 */
1211
+ <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>,
1212
+ /* sdmmc0_d1 */
1213
+ <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
1214
+ /* sdmmc0_d2 */
1215
+ <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
1216
+ /* sdmmc0_d3 */
1217
+ <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>;
1218
+ };
1219
+
1220
+ sdmmc0_clk: sdmmc0-clk {
1221
+ rockchip,pins =
1222
+ /* sdmmc0_clk */
1223
+ <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>;
1224
+ };
1225
+
1226
+ sdmmc0_cmd: sdmmc0-cmd {
1227
+ rockchip,pins =
1228
+ /* sdmmc0_cmd */
1229
+ <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
1230
+ };
1231
+
1232
+ sdmmc0_det: sdmmc0-det {
1233
+ rockchip,pins =
1234
+ /* sdmmc0_detn */
1235
+ <0 RK_PA4 1 &pcfg_pull_up>;
1236
+ };
1237
+
1238
+ sdmmc0_pwren: sdmmc0-pwren {
1239
+ rockchip,pins =
1240
+ /* sdmmc0_pwren */
1241
+ <0 RK_PA5 1 &pcfg_pull_none>;
1242
+ };
1243
+ };
1244
+
1245
+ sdmmc1 {
1246
+ sdmmc1_bus4: sdmmc1-bus4 {
1247
+ rockchip,pins =
1248
+ /* sdmmc1_d0 */
1249
+ <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>,
1250
+ /* sdmmc1_d1 */
1251
+ <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>,
1252
+ /* sdmmc1_d2 */
1253
+ <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>,
1254
+ /* sdmmc1_d3 */
1255
+ <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>;
1256
+ };
1257
+
1258
+ sdmmc1_clk: sdmmc1-clk {
1259
+ rockchip,pins =
1260
+ /* sdmmc1_clk */
1261
+ <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>;
1262
+ };
1263
+
1264
+ sdmmc1_cmd: sdmmc1-cmd {
1265
+ rockchip,pins =
1266
+ /* sdmmc1_cmd */
1267
+ <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>;
1268
+ };
1269
+
1270
+ sdmmc1_det: sdmmc1-det {
1271
+ rockchip,pins =
1272
+ /* sdmmc1_detn */
1273
+ <1 RK_PD0 1 &pcfg_pull_up>;
1274
+ };
1275
+
1276
+ sdmmc1_pwren: sdmmc1-pwren {
1277
+ rockchip,pins =
1278
+ /* sdmmc1_pwren */
1279
+ <1 RK_PC7 1 &pcfg_pull_none>;
1280
+ };
1281
+ };
1282
+
1283
+ spdif {
1284
+ spdifm0_pins: spdifm0-pins {
1285
+ rockchip,pins =
1286
+ /* spdif_tx_m0 */
1287
+ <3 RK_PA1 3 &pcfg_pull_none>;
1288
+ };
1289
+
1290
+ spdifm1_pins: spdifm1-pins {
1291
+ rockchip,pins =
1292
+ /* spdif_tx_m1 */
1293
+ <0 RK_PB7 4 &pcfg_pull_none>;
1294
+ };
1295
+
1296
+ spdifm2_pins: spdifm2-pins {
1297
+ rockchip,pins =
1298
+ /* spdif_tx_m2 */
1299
+ <1 RK_PB7 2 &pcfg_pull_none>;
1300
+ };
1301
+ };
1302
+
1303
+ spi0 {
1304
+ spi0m0_pins: spi0m0-pins {
1305
+ rockchip,pins =
1306
+ /* spi0_clk_m0 */
1307
+ <0 RK_PC3 3 &pcfg_pull_none>,
1308
+ /* spi0_miso_m0 */
1309
+ <0 RK_PC5 3 &pcfg_pull_none>,
1310
+ /* spi0_mosi_m0 */
1311
+ <0 RK_PC4 3 &pcfg_pull_none>;
1312
+ };
1313
+
1314
+ spi0m0_csn0: spi0m0-csn0 {
1315
+ rockchip,pins =
1316
+ /* spi0m0_csn0 */
1317
+ <0 RK_PC2 3 &pcfg_pull_none>;
1318
+ };
1319
+ spi0m0_csn1: spi0m0-csn1 {
1320
+ rockchip,pins =
1321
+ /* spi0m0_csn1 */
1322
+ <0 RK_PB7 1 &pcfg_pull_none>;
1323
+ };
1324
+
1325
+ spi0m1_pins: spi0m1-pins {
1326
+ rockchip,pins =
1327
+ /* spi0_clk_m1 */
1328
+ <3 RK_PB5 4 &pcfg_pull_none>,
1329
+ /* spi0_miso_m1 */
1330
+ <3 RK_PC0 4 &pcfg_pull_none>,
1331
+ /* spi0_mosi_m1 */
1332
+ <3 RK_PB4 4 &pcfg_pull_none>;
1333
+ };
1334
+
1335
+ spi0m1_csn0: spi0m1-csn0 {
1336
+ rockchip,pins =
1337
+ /* spi0m1_csn0 */
1338
+ <3 RK_PB7 4 &pcfg_pull_none>;
1339
+ };
1340
+ spi0m1_csn1: spi0m1-csn1 {
1341
+ rockchip,pins =
1342
+ /* spi0m1_csn1 */
1343
+ <3 RK_PB6 4 &pcfg_pull_none>;
1344
+ };
1345
+ };
1346
+
1347
+ spi1 {
1348
+ spi1m0_pins: spi1m0-pins {
1349
+ rockchip,pins =
1350
+ /* spi1_clk_m0 */
1351
+ <3 RK_PD6 4 &pcfg_pull_none>,
1352
+ /* spi1_miso_m0 */
1353
+ <4 RK_PA3 4 &pcfg_pull_none>,
1354
+ /* spi1_mosi_m0 */
1355
+ <4 RK_PA2 4 &pcfg_pull_none>;
1356
+ };
1357
+
1358
+ spi1m0_csn0: spi1m0-csn0 {
1359
+ rockchip,pins =
1360
+ /* spi1m0_csn0 */
1361
+ <3 RK_PD7 4 &pcfg_pull_none>;
1362
+ };
1363
+ spi1m0_csn1: spi1m0-csn1 {
1364
+ rockchip,pins =
1365
+ /* spi1m0_csn1 */
1366
+ <4 RK_PA0 4 &pcfg_pull_none>;
1367
+ };
1368
+
1369
+ spi1m1_pins: spi1m1-pins {
1370
+ rockchip,pins =
1371
+ /* spi1_clk_m1 */
1372
+ <1 RK_PC0 4 &pcfg_pull_none>,
1373
+ /* spi1_miso_m1 */
1374
+ <1 RK_PB4 4 &pcfg_pull_none>,
1375
+ /* spi1_mosi_m1 */
1376
+ <1 RK_PB3 4 &pcfg_pull_none>;
1377
+ };
1378
+
1379
+ spi1m1_csn0: spi1m1-csn0 {
1380
+ rockchip,pins =
1381
+ /* spi1m1_csn0 */
1382
+ <1 RK_PB6 4 &pcfg_pull_none>;
1383
+ };
1384
+ spi1m1_csn1: spi1m1-csn1 {
1385
+ rockchip,pins =
1386
+ /* spi1m1_csn1 */
1387
+ <1 RK_PB5 4 &pcfg_pull_none>;
1388
+ };
1389
+ };
1390
+
1391
+ spi2 {
1392
+ spi2m0_pins: spi2m0-pins {
1393
+ rockchip,pins =
1394
+ /* spi2_clk_m0 */
1395
+ <4 RK_PB6 4 &pcfg_pull_none>,
1396
+ /* spi2_miso_m0 */
1397
+ <3 RK_PD2 4 &pcfg_pull_none>,
1398
+ /* spi2_mosi_m0 */
1399
+ <3 RK_PD3 4 &pcfg_pull_none>;
1400
+ };
1401
+
1402
+ spi2m0_csn0: spi2m0-csn0 {
1403
+ rockchip,pins =
1404
+ /* spi2m0_csn0 */
1405
+ <4 RK_PB5 4 &pcfg_pull_none>;
1406
+ };
1407
+ spi2m0_csn1: spi2m0-csn1 {
1408
+ rockchip,pins =
1409
+ /* spi2m0_csn1 */
1410
+ <4 RK_PB4 4 &pcfg_pull_none>;
1411
+ };
1412
+
1413
+ spi2m1_pins: spi2m1-pins {
1414
+ rockchip,pins =
1415
+ /* spi2_clk_m1 */
1416
+ <2 RK_PA1 4 &pcfg_pull_none>,
1417
+ /* spi2_miso_m1 */
1418
+ <2 RK_PA0 4 &pcfg_pull_none>,
1419
+ /* spi2_mosi_m1 */
1420
+ <1 RK_PD7 4 &pcfg_pull_none>;
1421
+ };
1422
+
1423
+ spi2m1_csn0: spi2m1-csn0 {
1424
+ rockchip,pins =
1425
+ /* spi2m1_csn0 */
1426
+ <1 RK_PD6 4 &pcfg_pull_none>;
1427
+ };
1428
+ spi2m1_csn1: spi2m1-csn1 {
1429
+ rockchip,pins =
1430
+ /* spi2m1_csn1 */
1431
+ <1 RK_PD5 4 &pcfg_pull_none>;
1432
+ };
1433
+ };
1434
+
1435
+ tsadc {
1436
+ tsadcm0_pins: tsadcm0-pins {
1437
+ rockchip,pins =
1438
+ /* tsadc_shut_m0 */
1439
+ <0 RK_PA1 1 &pcfg_pull_none>;
1440
+ };
1441
+
1442
+ tsadcm1_pins: tsadcm1-pins {
1443
+ rockchip,pins =
1444
+ /* tsadc_shut_m1 */
1445
+ <0 RK_PA2 2 &pcfg_pull_none>;
1446
+ };
1447
+
1448
+ tsadc_shut_org: tsadc-shut-org {
1449
+ rockchip,pins =
1450
+ /* tsadc_shut_org */
1451
+ <0 RK_PA1 2 &pcfg_pull_none>;
1452
+ };
1453
+ };
1454
+
1455
+ uart0 {
1456
+ uart0m0_xfer: uart0m0-xfer {
1457
+ rockchip,pins =
1458
+ /* uart0_rx_m0 */
1459
+ <0 RK_PD0 1 &pcfg_pull_up>,
1460
+ /* uart0_tx_m0 */
1461
+ <0 RK_PD1 1 &pcfg_pull_up>;
1462
+ };
1463
+
1464
+ uart0m1_xfer: uart0m1-xfer {
1465
+ rockchip,pins =
1466
+ /* uart0_rx_m1 */
1467
+ <1 RK_PB3 2 &pcfg_pull_up>,
1468
+ /* uart0_tx_m1 */
1469
+ <1 RK_PB4 2 &pcfg_pull_up>;
1470
+ };
1471
+ };
1472
+
1473
+ uart1 {
1474
+ uart1m0_xfer: uart1m0-xfer {
1475
+ rockchip,pins =
1476
+ /* uart1_rx_m0 */
1477
+ <1 RK_PD1 1 &pcfg_pull_up>,
1478
+ /* uart1_tx_m0 */
1479
+ <1 RK_PD2 1 &pcfg_pull_up>;
1480
+ };
1481
+
1482
+ uart1m0_ctsn: uart1m0-ctsn {
1483
+ rockchip,pins =
1484
+ /* uart1m0_ctsn */
1485
+ <1 RK_PD4 1 &pcfg_pull_none>;
1486
+ };
1487
+ uart1m0_rtsn: uart1m0-rtsn {
1488
+ rockchip,pins =
1489
+ /* uart1m0_rtsn */
1490
+ <1 RK_PD3 1 &pcfg_pull_none>;
1491
+ };
1492
+
1493
+ uart1m1_xfer: uart1m1-xfer {
1494
+ rockchip,pins =
1495
+ /* uart1_rx_m1 */
1496
+ <4 RK_PA6 3 &pcfg_pull_up>,
1497
+ /* uart1_tx_m1 */
1498
+ <4 RK_PA5 3 &pcfg_pull_up>;
1499
+ };
1500
+
1501
+ uart1m1_ctsn: uart1m1-ctsn {
1502
+ rockchip,pins =
1503
+ /* uart1m1_ctsn */
1504
+ <4 RK_PB0 3 &pcfg_pull_none>;
1505
+ };
1506
+ uart1m1_rtsn: uart1m1-rtsn {
1507
+ rockchip,pins =
1508
+ /* uart1m1_rtsn */
1509
+ <4 RK_PA7 3 &pcfg_pull_none>;
1510
+ };
1511
+ };
1512
+
1513
+ uart2 {
1514
+ uart2m0_xfer: uart2m0-xfer {
1515
+ rockchip,pins =
1516
+ /* uart2_rx_m0 */
1517
+ <0 RK_PC1 1 &pcfg_pull_up>,
1518
+ /* uart2_tx_m0 */
1519
+ <0 RK_PC0 1 &pcfg_pull_up>;
1520
+ };
1521
+
1522
+ uart2m0_ctsn: uart2m0-ctsn {
1523
+ rockchip,pins =
1524
+ /* uart2m0_ctsn */
1525
+ <0 RK_PC2 1 &pcfg_pull_none>;
1526
+ };
1527
+ uart2m0_rtsn: uart2m0-rtsn {
1528
+ rockchip,pins =
1529
+ /* uart2m0_rtsn */
1530
+ <0 RK_PC3 1 &pcfg_pull_none>;
1531
+ };
1532
+
1533
+ uart2m1_xfer: uart2m1-xfer {
1534
+ rockchip,pins =
1535
+ /* uart2_rx_m1 */
1536
+ <3 RK_PA1 2 &pcfg_pull_up>,
1537
+ /* uart2_tx_m1 */
1538
+ <3 RK_PA0 2 &pcfg_pull_up>;
1539
+ };
1540
+
1541
+ uart2m1_ctsn: uart2m1-ctsn {
1542
+ rockchip,pins =
1543
+ /* uart2m1_ctsn */
1544
+ <3 RK_PA2 2 &pcfg_pull_none>;
1545
+ };
1546
+ uart2m1_rtsn: uart2m1-rtsn {
1547
+ rockchip,pins =
1548
+ /* uart2m1_rtsn */
1549
+ <3 RK_PA3 2 &pcfg_pull_none>;
1550
+ };
1551
+ };
1552
+
1553
+ uart3 {
1554
+ uart3m0_xfer: uart3m0-xfer {
1555
+ rockchip,pins =
1556
+ /* uart3_rx_m0 */
1557
+ <4 RK_PB5 6 &pcfg_pull_up>,
1558
+ /* uart3_tx_m0 */
1559
+ <4 RK_PB4 6 &pcfg_pull_up>;
1560
+ };
1561
+
1562
+ uart3m0_ctsn: uart3m0-ctsn {
1563
+ rockchip,pins =
1564
+ /* uart3m0_ctsn */
1565
+ <4 RK_PB6 3 &pcfg_pull_none>;
1566
+ };
1567
+ uart3m0_rtsn: uart3m0-rtsn {
1568
+ rockchip,pins =
1569
+ /* uart3m0_rtsn */
1570
+ <3 RK_PD1 4 &pcfg_pull_none>;
1571
+ };
1572
+
1573
+ uart3m1_xfer: uart3m1-xfer {
1574
+ rockchip,pins =
1575
+ /* uart3_rx_m1 */
1576
+ <3 RK_PC0 3 &pcfg_pull_up>,
1577
+ /* uart3_tx_m1 */
1578
+ <3 RK_PB7 3 &pcfg_pull_up>;
1579
+ };
1580
+
1581
+ uart3m1_ctsn: uart3m1-ctsn {
1582
+ rockchip,pins =
1583
+ /* uart3m1_ctsn */
1584
+ <3 RK_PB6 3 &pcfg_pull_none>;
1585
+ };
1586
+ uart3m1_rtsn: uart3m1-rtsn {
1587
+ rockchip,pins =
1588
+ /* uart3m1_rtsn */
1589
+ <3 RK_PC1 3 &pcfg_pull_none>;
1590
+ };
1591
+ };
1592
+
1593
+ uart4 {
1594
+ uart4m0_xfer: uart4m0-xfer {
1595
+ rockchip,pins =
1596
+ /* uart4_rx_m0 */
1597
+ <3 RK_PD1 3 &pcfg_pull_up>,
1598
+ /* uart4_tx_m0 */
1599
+ <3 RK_PD0 3 &pcfg_pull_up>;
1600
+ };
1601
+
1602
+ uart4m0_ctsn: uart4m0-ctsn {
1603
+ rockchip,pins =
1604
+ /* uart4m0_ctsn */
1605
+ <3 RK_PC5 3 &pcfg_pull_none>;
1606
+ };
1607
+ uart4m0_rtsn: uart4m0-rtsn {
1608
+ rockchip,pins =
1609
+ /* uart4m0_rtsn */
1610
+ <3 RK_PC6 3 &pcfg_pull_none>;
1611
+ };
1612
+
1613
+ uart4m1_xfer: uart4m1-xfer {
1614
+ rockchip,pins =
1615
+ /* uart4_rx_m1 */
1616
+ <1 RK_PD5 3 &pcfg_pull_up>,
1617
+ /* uart4_tx_m1 */
1618
+ <1 RK_PD6 3 &pcfg_pull_up>;
1619
+ };
1620
+
1621
+ uart4m1_ctsn: uart4m1-ctsn {
1622
+ rockchip,pins =
1623
+ /* uart4m1_ctsn */
1624
+ <2 RK_PA0 3 &pcfg_pull_none>;
1625
+ };
1626
+ uart4m1_rtsn: uart4m1-rtsn {
1627
+ rockchip,pins =
1628
+ /* uart4m1_rtsn */
1629
+ <1 RK_PD7 3 &pcfg_pull_none>;
1630
+ };
1631
+ };
1632
+
1633
+ uart5 {
1634
+ uart5m0_xfer: uart5m0-xfer {
1635
+ rockchip,pins =
1636
+ /* uart5_rx_m0 */
1637
+ <1 RK_PB7 3 &pcfg_pull_up>,
1638
+ /* uart5_tx_m0 */
1639
+ <1 RK_PC0 3 &pcfg_pull_up>;
1640
+ };
1641
+
1642
+ uart5m0_ctsn: uart5m0-ctsn {
1643
+ rockchip,pins =
1644
+ /* uart5m0_ctsn */
1645
+ <1 RK_PB5 3 &pcfg_pull_none>;
1646
+ };
1647
+ uart5m0_rtsn: uart5m0-rtsn {
1648
+ rockchip,pins =
1649
+ /* uart5m0_rtsn */
1650
+ <1 RK_PB6 3 &pcfg_pull_none>;
1651
+ };
1652
+
1653
+ uart5m1_xfer: uart5m1-xfer {
1654
+ rockchip,pins =
1655
+ /* uart5_rx_m1 */
1656
+ <3 RK_PA7 5 &pcfg_pull_up>,
1657
+ /* uart5_tx_m1 */
1658
+ <3 RK_PA6 5 &pcfg_pull_up>;
1659
+ };
1660
+
1661
+ uart5m1_ctsn: uart5m1-ctsn {
1662
+ rockchip,pins =
1663
+ /* uart5m1_ctsn */
1664
+ <3 RK_PA0 5 &pcfg_pull_none>;
1665
+ };
1666
+ uart5m1_rtsn: uart5m1-rtsn {
1667
+ rockchip,pins =
1668
+ /* uart5m1_rtsn */
1669
+ <3 RK_PA1 5 &pcfg_pull_none>;
1670
+ };
1671
+ };
1672
+
1673
+ uart6 {
1674
+ uart6m0_xfer: uart6m0-xfer {
1675
+ rockchip,pins =
1676
+ /* uart6_rx_m0 */
1677
+ <0 RK_PC7 1 &pcfg_pull_up>,
1678
+ /* uart6_tx_m0 */
1679
+ <0 RK_PC6 1 &pcfg_pull_up>;
1680
+ };
1681
+
1682
+ uart6m0_ctsn: uart6m0-ctsn {
1683
+ rockchip,pins =
1684
+ /* uart6m0_ctsn */
1685
+ <0 RK_PC4 1 &pcfg_pull_none>;
1686
+ };
1687
+ uart6m0_rtsn: uart6m0-rtsn {
1688
+ rockchip,pins =
1689
+ /* uart6m0_rtsn */
1690
+ <0 RK_PC5 1 &pcfg_pull_none>;
1691
+ };
1692
+
1693
+ uart6m1_xfer: uart6m1-xfer {
1694
+ rockchip,pins =
1695
+ /* uart6_rx_m1 */
1696
+ <4 RK_PB0 5 &pcfg_pull_up>,
1697
+ /* uart6_tx_m1 */
1698
+ <4 RK_PA7 5 &pcfg_pull_up>;
1699
+ };
1700
+
1701
+ uart6m1_ctsn: uart6m1-ctsn {
1702
+ rockchip,pins =
1703
+ /* uart6m1_ctsn */
1704
+ <4 RK_PA2 3 &pcfg_pull_none>;
1705
+ };
1706
+ uart6m1_rtsn: uart6m1-rtsn {
1707
+ rockchip,pins =
1708
+ /* uart6m1_rtsn */
1709
+ <4 RK_PA3 3 &pcfg_pull_none>;
1710
+ };
1711
+ };
1712
+
1713
+ uart7 {
1714
+ uart7m0_xfer: uart7m0-xfer {
1715
+ rockchip,pins =
1716
+ /* uart7_rx_m0 */
1717
+ <3 RK_PC7 3 &pcfg_pull_up>,
1718
+ /* uart7_tx_m0 */
1719
+ <3 RK_PC4 3 &pcfg_pull_up>;
1720
+ };
1721
+
1722
+ uart7m0_ctsn: uart7m0-ctsn {
1723
+ rockchip,pins =
1724
+ /* uart7m0_ctsn */
1725
+ <3 RK_PD2 3 &pcfg_pull_none>;
1726
+ };
1727
+ uart7m0_rtsn: uart7m0-rtsn {
1728
+ rockchip,pins =
1729
+ /* uart7m0_rtsn */
1730
+ <3 RK_PD3 3 &pcfg_pull_none>;
1731
+ };
1732
+
1733
+ uart7m1_xfer: uart7m1-xfer {
1734
+ rockchip,pins =
1735
+ /* uart7_rx_m1 */
1736
+ <1 RK_PB3 3 &pcfg_pull_up>,
1737
+ /* uart7_tx_m1 */
1738
+ <1 RK_PB4 3 &pcfg_pull_up>;
1739
+ };
1740
+ };
1741
+
1742
+ uart8 {
1743
+ uart8m0_xfer: uart8m0-xfer {
1744
+ rockchip,pins =
1745
+ /* uart8_rx_m0 */
1746
+ <3 RK_PB3 3 &pcfg_pull_up>,
1747
+ /* uart8_tx_m0 */
1748
+ <3 RK_PB2 3 &pcfg_pull_up>;
1749
+ };
1750
+
1751
+ uart8m0_ctsn: uart8m0-ctsn {
1752
+ rockchip,pins =
1753
+ /* uart8m0_ctsn */
1754
+ <3 RK_PB4 3 &pcfg_pull_none>;
1755
+ };
1756
+ uart8m0_rtsn: uart8m0-rtsn {
1757
+ rockchip,pins =
1758
+ /* uart8m0_rtsn */
1759
+ <3 RK_PB5 3 &pcfg_pull_none>;
1760
+ };
1761
+
1762
+ uart8m1_xfer: uart8m1-xfer {
1763
+ rockchip,pins =
1764
+ /* uart8_rx_m1 */
1765
+ <3 RK_PD5 3 &pcfg_pull_up>,
1766
+ /* uart8_tx_m1 */
1767
+ <3 RK_PD4 3 &pcfg_pull_up>;
1768
+ };
1769
+
1770
+ uart8m1_ctsn: uart8m1-ctsn {
1771
+ rockchip,pins =
1772
+ /* uart8m1_ctsn */
1773
+ <3 RK_PD7 3 &pcfg_pull_none>;
1774
+ };
1775
+ uart8m1_rtsn: uart8m1-rtsn {
1776
+ rockchip,pins =
1777
+ /* uart8m1_rtsn */
1778
+ <4 RK_PA0 3 &pcfg_pull_none>;
1779
+ };
1780
+ };
1781
+
1782
+ uart9 {
1783
+ uart9m0_xfer: uart9m0-xfer {
1784
+ rockchip,pins =
1785
+ /* uart9_rx_m0 */
1786
+ <4 RK_PB3 3 &pcfg_pull_up>,
1787
+ /* uart9_tx_m0 */
1788
+ <4 RK_PB2 3 &pcfg_pull_up>;
1789
+ };
1790
+
1791
+ uart9m0_ctsn: uart9m0-ctsn {
1792
+ rockchip,pins =
1793
+ /* uart9m0_ctsn */
1794
+ <4 RK_PB4 3 &pcfg_pull_none>;
1795
+ };
1796
+ uart9m0_rtsn: uart9m0-rtsn {
1797
+ rockchip,pins =
1798
+ /* uart9m0_rtsn */
1799
+ <4 RK_PB5 3 &pcfg_pull_none>;
1800
+ };
1801
+
1802
+ uart9m1_xfer: uart9m1-xfer {
1803
+ rockchip,pins =
1804
+ /* uart9_rx_m1 */
1805
+ <3 RK_PC3 3 &pcfg_pull_up>,
1806
+ /* uart9_tx_m1 */
1807
+ <3 RK_PC2 3 &pcfg_pull_up>;
1808
+ };
1809
+ };
1810
+
1811
+ vo {
1812
+ vo_pins: vo-pins {
1813
+ rockchip,pins =
1814
+ /* vo_lcdc_clk */
1815
+ <4 RK_PB7 1 &pcfg_pull_none>,
1816
+ /* vo_lcdc_d0 */
1817
+ <4 RK_PA4 1 &pcfg_pull_none>,
1818
+ /* vo_lcdc_d1 */
1819
+ <4 RK_PA5 1 &pcfg_pull_none>,
1820
+ /* vo_lcdc_d2 */
1821
+ <4 RK_PB2 1 &pcfg_pull_none>,
1822
+ /* vo_lcdc_d3 */
1823
+ <3 RK_PC4 1 &pcfg_pull_none>,
1824
+ /* vo_lcdc_d4 */
1825
+ <3 RK_PC5 1 &pcfg_pull_none>,
1826
+ /* vo_lcdc_d5 */
1827
+ <3 RK_PC6 1 &pcfg_pull_none>,
1828
+ /* vo_lcdc_d6 */
1829
+ <3 RK_PC7 1 &pcfg_pull_none>,
1830
+ /* vo_lcdc_d7 */
1831
+ <3 RK_PD0 1 &pcfg_pull_none>,
1832
+ /* vo_lcdc_d8 */
1833
+ <4 RK_PA6 1 &pcfg_pull_none>,
1834
+ /* vo_lcdc_d9 */
1835
+ <4 RK_PA7 1 &pcfg_pull_none>,
1836
+ /* vo_lcdc_d10 */
1837
+ <3 RK_PD1 1 &pcfg_pull_none>,
1838
+ /* vo_lcdc_d11 */
1839
+ <3 RK_PD2 1 &pcfg_pull_none>,
1840
+ /* vo_lcdc_d12 */
1841
+ <3 RK_PD3 1 &pcfg_pull_none>,
1842
+ /* vo_lcdc_d13 */
1843
+ <3 RK_PD4 1 &pcfg_pull_none>,
1844
+ /* vo_lcdc_d14 */
1845
+ <3 RK_PD5 1 &pcfg_pull_none>,
1846
+ /* vo_lcdc_d15 */
1847
+ <3 RK_PD6 1 &pcfg_pull_none>,
1848
+ /* vo_lcdc_d16 */
1849
+ <4 RK_PB0 1 &pcfg_pull_none>,
1850
+ /* vo_lcdc_d17 */
1851
+ <4 RK_PB1 1 &pcfg_pull_none>,
1852
+ /* vo_lcdc_d18 */
1853
+ <4 RK_PB3 1 &pcfg_pull_none>,
1854
+ /* vo_lcdc_d19 */
1855
+ <3 RK_PD7 1 &pcfg_pull_none>,
1856
+ /* vo_lcdc_d20 */
1857
+ <4 RK_PA0 1 &pcfg_pull_none>,
1858
+ /* vo_lcdc_d21 */
1859
+ <4 RK_PA1 1 &pcfg_pull_none>,
1860
+ /* vo_lcdc_d22 */
1861
+ <4 RK_PA2 1 &pcfg_pull_none>,
1862
+ /* vo_lcdc_d23 */
1863
+ <4 RK_PA3 1 &pcfg_pull_none>,
1864
+ /* vo_lcdc_den */
1865
+ <4 RK_PB6 1 &pcfg_pull_none>,
1866
+ /* vo_lcdc_hsync */
1867
+ <4 RK_PB4 1 &pcfg_pull_none>,
1868
+ /* vo_lcdc_vsync */
1869
+ <4 RK_PB5 1 &pcfg_pull_none>;
1870
+ };
1871
+ };
1872
+};
u-boot/arch/arm/dts/rk3562-u-boot.dtsi
....@@ -0,0 +1,203 @@
1
+/*
2
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+
7
+/ {
8
+ aliases {
9
+ mmc0 = &sdhci;
10
+ mmc1 = &sdmmc0;
11
+ };
12
+
13
+ chosen {
14
+ stdout-path = &uart2;
15
+ u-boot,spl-boot-order = &sdmmc0, &sdhci, &spi_nand, &spi_nor;
16
+ };
17
+
18
+ secure-otp@ff920000 {
19
+ compatible = "rockchip,rk3562-secure-otp";
20
+ reg = <0x0 0xff920000 0x0 0x4000>;
21
+ secure_conf = <0xff020034>;
22
+ mask_addr = <0x0>;
23
+ cru_rst_addr = <0xff130438>;
24
+ u-boot,dm-spl;
25
+ status = "okay";
26
+ };
27
+};
28
+
29
+&sys_grf {
30
+ u-boot,dm-spl;
31
+ status = "okay";
32
+};
33
+
34
+&ioc_grf {
35
+ u-boot,dm-spl;
36
+ status = "okay";
37
+};
38
+
39
+&pmu_grf {
40
+ u-boot,dm-spl;
41
+ status = "okay";
42
+};
43
+
44
+&usbphy_grf {
45
+ u-boot,dm-pre-reloc;
46
+ status = "okay";
47
+};
48
+
49
+&firmware {
50
+ u-boot,dm-spl;
51
+};
52
+
53
+&scmi {
54
+ u-boot,dm-spl;
55
+};
56
+
57
+&scmi_clk {
58
+ u-boot,dm-spl;
59
+};
60
+
61
+&scmi_shmem {
62
+ u-boot,dm-spl;
63
+};
64
+
65
+&cru {
66
+ u-boot,dm-spl;
67
+ status = "okay";
68
+};
69
+
70
+&crypto {
71
+ u-boot,dm-spl;
72
+ status = "okay";
73
+};
74
+
75
+&rng {
76
+ u-boot,dm-pre-reloc;
77
+ status = "okay";
78
+};
79
+
80
+&uart2 {
81
+ clock-frequency = <24000000>;
82
+ u-boot,dm-spl;
83
+ status = "okay";
84
+};
85
+
86
+&saradc0 {
87
+ u-boot,dm-pre-reloc;
88
+ status = "okay";
89
+};
90
+
91
+&psci {
92
+ u-boot,dm-pre-reloc;
93
+ status = "okay";
94
+};
95
+
96
+&sdhci {
97
+ bus-width = <8>;
98
+ u-boot,dm-spl;
99
+ /delete-property/ pinctrl-names;
100
+ /delete-property/ pinctrl-0;
101
+ mmc-hs400-1_8v;
102
+ mmc-hs400-enhanced-strobe;
103
+ fixed-emmc-driver-type = <1>;
104
+ status = "okay";
105
+};
106
+
107
+&sdmmc0 {
108
+ u-boot,dm-spl;
109
+ pinctrl-names = "default";
110
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
111
+ status = "okay";
112
+};
113
+
114
+&sdmmc0_pins {
115
+ u-boot,dm-spl;
116
+};
117
+
118
+&sdmmc0_bus4 {
119
+ u-boot,dm-spl;
120
+};
121
+
122
+&sdmmc0_clk {
123
+ u-boot,dm-spl;
124
+};
125
+
126
+&sdmmc0_cmd {
127
+ u-boot,dm-spl;
128
+};
129
+
130
+&sdmmc0_det {
131
+ u-boot,dm-spl;
132
+};
133
+
134
+&sfc {
135
+ u-boot,dm-spl;
136
+ status = "okay";
137
+
138
+ #address-cells = <1>;
139
+ #size-cells = <0>;
140
+ spi_nand: flash@0 {
141
+ u-boot,dm-spl;
142
+ compatible = "spi-nand";
143
+ reg = <0>;
144
+ spi-tx-bus-width = <1>;
145
+ spi-rx-bus-width = <4>;
146
+ spi-max-frequency = <80000000>;
147
+ };
148
+
149
+ spi_nor: flash@1 {
150
+ u-boot,dm-spl;
151
+ compatible = "jedec,spi-nor";
152
+ label = "sfc_nor";
153
+ reg = <0>;
154
+ spi-tx-bus-width = <1>;
155
+ spi-rx-bus-width = <4>;
156
+ spi-max-frequency = <80000000>;
157
+ };
158
+};
159
+
160
+&pinctrl {
161
+ u-boot,dm-spl;
162
+ status = "okay";
163
+};
164
+
165
+&gpio0 {
166
+ u-boot,dm-pre-reloc;
167
+};
168
+
169
+&gpio1 {
170
+ u-boot,dm-pre-reloc;
171
+};
172
+
173
+&gpio2 {
174
+ u-boot,dm-pre-reloc;
175
+};
176
+
177
+&gpio3 {
178
+ u-boot,dm-pre-reloc;
179
+};
180
+
181
+&gpio4 {
182
+ u-boot,dm-pre-reloc;
183
+};
184
+
185
+&pcfg_pull_up_drv_level_2 {
186
+ u-boot,dm-spl;
187
+ status = "okay";
188
+};
189
+
190
+&pcfg_pull_up {
191
+ u-boot,dm-spl;
192
+ status = "okay";
193
+};
194
+
195
+&u2phy {
196
+ u-boot,dm-pre-reloc;
197
+ status = "okay";
198
+};
199
+
200
+&u2phy_otg {
201
+ u-boot,dm-pre-reloc;
202
+ status = "okay";
203
+};
u-boot/arch/arm/dts/rk3562.dtsi
....@@ -0,0 +1,2325 @@
1
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+/*
3
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4
+ */
5
+
6
+#include <dt-bindings/clock/rk3562-cru.h>
7
+#include <dt-bindings/interrupt-controller/arm-gic.h>
8
+#include <dt-bindings/interrupt-controller/irq.h>
9
+#include <dt-bindings/phy/phy.h>
10
+#include <dt-bindings/power/rk3562-power.h>
11
+#include <dt-bindings/pinctrl/rockchip.h>
12
+#include <dt-bindings/soc/rockchip,boot-mode.h>
13
+#include <dt-bindings/soc/rockchip-system-status.h>
14
+#include <dt-bindings/thermal/thermal.h>
15
+
16
+/ {
17
+ compatible = "rockchip,rk3562";
18
+
19
+ interrupt-parent = <&gic>;
20
+ #address-cells = <2>;
21
+ #size-cells = <2>;
22
+
23
+ aliases {
24
+ csi2dphy0 = &csi2_dphy0;
25
+ csi2dphy1 = &csi2_dphy1;
26
+ csi2dphy2 = &csi2_dphy2;
27
+ csi2dphy3 = &csi2_dphy3;
28
+ csi2dphy4 = &csi2_dphy4;
29
+ csi2dphy5 = &csi2_dphy5;
30
+ ethernet0 = &gmac0;
31
+ ethernet1 = &gmac1;
32
+ gpio0 = &gpio0;
33
+ gpio1 = &gpio1;
34
+ gpio2 = &gpio2;
35
+ gpio3 = &gpio3;
36
+ gpio4 = &gpio4;
37
+ i2c0 = &i2c0;
38
+ i2c1 = &i2c1;
39
+ i2c2 = &i2c2;
40
+ i2c3 = &i2c3;
41
+ i2c4 = &i2c4;
42
+ i2c5 = &i2c5;
43
+ rkcif_mipi_lvds0= &rkcif_mipi_lvds;
44
+ rkcif_mipi_lvds1= &rkcif_mipi_lvds1;
45
+ rkcif_mipi_lvds2= &rkcif_mipi_lvds2;
46
+ rkcif_mipi_lvds3= &rkcif_mipi_lvds3;
47
+ serial0 = &uart0;
48
+ serial1 = &uart1;
49
+ serial2 = &uart2;
50
+ serial3 = &uart3;
51
+ serial4 = &uart4;
52
+ serial5 = &uart5;
53
+ serial6 = &uart6;
54
+ serial7 = &uart7;
55
+ serial8 = &uart8;
56
+ serial9 = &uart9;
57
+ spi0 = &spi0;
58
+ spi1 = &spi1;
59
+ spi2 = &spi2;
60
+ spi3 = &sfc;
61
+ };
62
+
63
+ clocks {
64
+ compatible = "simple-bus";
65
+ #address-cells = <2>;
66
+ #size-cells = <2>;
67
+ ranges;
68
+
69
+ xin32k: xin32k {
70
+ compatible = "fixed-clock";
71
+ #clock-cells = <0>;
72
+ clock-frequency = <32768>;
73
+ clock-output-names = "xin32k";
74
+ };
75
+
76
+ xin24m: xin24m {
77
+ compatible = "fixed-clock";
78
+ #clock-cells = <0>;
79
+ clock-frequency = <24000000>;
80
+ clock-output-names = "xin24m";
81
+ };
82
+
83
+ aclk_vepu: aclk_vepu@ff100324 {
84
+ compatible = "rockchip,rk3562-clock-gate-link";
85
+ reg = <0 0xff100324 0 0x10>;
86
+ clock-names = "link";
87
+ clocks = <&cru ACLK_ISP>;
88
+ #power-domain-cells = <1>;
89
+ #clock-cells = <0>;
90
+ };
91
+
92
+ aclk_vdpu: aclk_vdpu@ff100328 {
93
+ compatible = "rockchip,rk3562-clock-gate-link";
94
+ reg = <0 0xff100328 0 0x10>;
95
+ clock-names = "link";
96
+ clocks = <&cru ACLK_TOP_VIO>;
97
+ #power-domain-cells = <1>;
98
+ #clock-cells = <0>;
99
+ };
100
+
101
+ aclk_vi_isp: aclk_vi_isp@ff10032c {
102
+ compatible = "rockchip,rk3562-clock-gate-link";
103
+ reg = <0 0xff10032c 0 0x10>;
104
+ clock-names = "link";
105
+ clocks = <&cru ACLK_TOP_VIO>;
106
+ #power-domain-cells = <1>;
107
+ #clock-cells = <0>;
108
+ };
109
+
110
+ aclk_vo: aclk_vo@ff100334 {
111
+ compatible = "rockchip,rk3562-clock-gate-link";
112
+ reg = <0 0xff100334 0 0x10>;
113
+ clock-names = "link";
114
+ clocks = <&cru ACLK_TOP_VIO>;
115
+ #power-domain-cells = <1>;
116
+ #clock-cells = <0>;
117
+ };
118
+
119
+ aclk_rga_jdec: aclk_rga_jdec@ff100338 {
120
+ compatible = "rockchip,rk3562-clock-gate-link";
121
+ reg = <0 0xff100338 0 0x10>;
122
+ clock-names = "link";
123
+ clocks = <&cru ACLK_VOP>;
124
+ #power-domain-cells = <1>;
125
+ #clock-cells = <0>;
126
+ };
127
+ };
128
+
129
+ cpus {
130
+ #address-cells = <2>;
131
+ #size-cells = <0>;
132
+
133
+ cpu0: cpu@0 {
134
+ device_type = "cpu";
135
+ compatible = "arm,cortex-a53";
136
+ reg = <0x0 0x0>;
137
+ enable-method = "psci";
138
+ clocks = <&cru ARMCLK>;
139
+ operating-points-v2 = <&cpu0_opp_table>;
140
+ };
141
+ cpu1: cpu@1 {
142
+ device_type = "cpu";
143
+ compatible = "arm,cortex-a53";
144
+ reg = <0x0 0x1>;
145
+ enable-method = "psci";
146
+ clocks = <&cru ARMCLK>;
147
+ operating-points-v2 = <&cpu0_opp_table>;
148
+ };
149
+ cpu2: cpu@2 {
150
+ device_type = "cpu";
151
+ compatible = "arm,cortex-a53";
152
+ reg = <0x0 0x2>;
153
+ enable-method = "psci";
154
+ clocks = <&cru ARMCLK>;
155
+ operating-points-v2 = <&cpu0_opp_table>;
156
+ };
157
+ cpu3: cpu@3 {
158
+ device_type = "cpu";
159
+ compatible = "arm,cortex-a53";
160
+ reg = <0x0 0x3>;
161
+ enable-method = "psci";
162
+ clocks = <&cru ARMCLK>;
163
+ operating-points-v2 = <&cpu0_opp_table>;
164
+ };
165
+ };
166
+
167
+ cpu0_opp_table: cpu0-opp-table {
168
+ compatible = "operating-points-v2";
169
+ opp-shared;
170
+
171
+ nvmem-cells = <&cpu_leakage>;
172
+ nvmem-cell-names = "leakage";
173
+
174
+ opp-408000000 {
175
+ opp-hz = /bits/ 64 <408000000>;
176
+ opp-microvolt = <900000 900000 1100000>;
177
+ clock-latency-ns = <40000>;
178
+ opp-suspend;
179
+ };
180
+ opp-600000000 {
181
+ opp-hz = /bits/ 64 <600000000>;
182
+ opp-microvolt = <900000 900000 1100000>;
183
+ clock-latency-ns = <40000>;
184
+ };
185
+ opp-816000000 {
186
+ opp-hz = /bits/ 64 <816000000>;
187
+ opp-microvolt = <900000 900000 1100000>;
188
+ clock-latency-ns = <40000>;
189
+ };
190
+ opp-1008000000 {
191
+ opp-hz = /bits/ 64 <1008000000>;
192
+ opp-microvolt = <900000 900000 1100000>;
193
+ clock-latency-ns = <40000>;
194
+ };
195
+ opp-1200000000 {
196
+ opp-hz = /bits/ 64 <1200000000>;
197
+ opp-microvolt = <900000 900000 1100000>;
198
+ clock-latency-ns = <40000>;
199
+ };
200
+ };
201
+
202
+ arm-pmu {
203
+ compatible = "arm,cortex-a53-pmu";
204
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
205
+ <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
206
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
207
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
208
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
209
+ };
210
+
211
+ cpuinfo {
212
+ compatible = "rockchip,cpuinfo";
213
+ nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
214
+ nvmem-cell-names = "id", "cpu-version", "cpu-code";
215
+ };
216
+
217
+ /* dphy0 full mode */
218
+ csi2_dphy0: csi2-dphy0 {
219
+ compatible = "rockchip,rk3562-csi2-dphy";
220
+ rockchip,hw = <&csi2_dphy0_hw>;
221
+ status = "disabled";
222
+ };
223
+
224
+ /* dphy0 split mode 01 */
225
+ csi2_dphy1: csi2-dphy1 {
226
+ compatible = "rockchip,rk3562-csi2-dphy";
227
+ rockchip,hw = <&csi2_dphy0_hw>;
228
+ status = "disabled";
229
+ };
230
+
231
+ /* dphy0 split mode 23 */
232
+ csi2_dphy2: csi2-dphy2 {
233
+ compatible = "rockchip,rk3562-csi2-dphy";
234
+ rockchip,hw = <&csi2_dphy0_hw>;
235
+ status = "disabled";
236
+ };
237
+
238
+ /* dphy1 full mode */
239
+ csi2_dphy3: csi2-dphy3 {
240
+ compatible = "rockchip,rk3562-csi2-dphy";
241
+ rockchip,hw = <&csi2_dphy1_hw>;
242
+ status = "disabled";
243
+ };
244
+
245
+ /* dphy1 split mode 01 */
246
+ csi2_dphy4: csi2-dphy4 {
247
+ compatible = "rockchip,rk3562-csi2-dphy";
248
+ rockchip,hw = <&csi2_dphy1_hw>;
249
+ status = "disabled";
250
+ };
251
+
252
+ /* dphy1 split mode 23 */
253
+ csi2_dphy5: csi2-dphy5 {
254
+ compatible = "rockchip,rk3562-csi2-dphy";
255
+ rockchip,hw = <&csi2_dphy1_hw>;
256
+ status = "disabled";
257
+ };
258
+
259
+ display_subsystem: display-subsystem {
260
+ compatible = "rockchip,display-subsystem";
261
+ ports = <&vop_out>;
262
+ status = "disabled";
263
+ };
264
+
265
+ firmware: firmware {
266
+ scmi: scmi {
267
+ compatible = "arm,scmi-smc";
268
+ shmem = <&scmi_shmem>;
269
+ arm,smc-id = <0x82000010>;
270
+ #address-cells = <1>;
271
+ #size-cells = <0>;
272
+
273
+ scmi_clk: protocol@14 {
274
+ reg = <0x14>;
275
+ #clock-cells = <1>;
276
+ };
277
+ };
278
+ };
279
+
280
+ mpp_srv: mpp-srv {
281
+ compatible = "rockchip,mpp-service";
282
+ rockchip,taskqueue-count = <3>;
283
+ rockchip,resetgroup-count = <3>;
284
+ status = "disabled";
285
+ };
286
+
287
+ psci: psci {
288
+ compatible = "arm,psci-1.0";
289
+ method = "smc";
290
+ };
291
+
292
+ rkcif_mipi_lvds: rkcif-mipi-lvds {
293
+ compatible = "rockchip,rkcif-mipi-lvds";
294
+ rockchip,hw = <&rkcif>;
295
+ iommus = <&rkcif_mmu>;
296
+ status = "disabled";
297
+ };
298
+
299
+ rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf {
300
+ compatible = "rockchip,rkcif-sditf";
301
+ rockchip,cif = <&rkcif_mipi_lvds>;
302
+ status = "disabled";
303
+ };
304
+
305
+ rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 {
306
+ compatible = "rockchip,rkcif-sditf";
307
+ rockchip,cif = <&rkcif_mipi_lvds>;
308
+ status = "disabled";
309
+ };
310
+
311
+ rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 {
312
+ compatible = "rockchip,rkcif-sditf";
313
+ rockchip,cif = <&rkcif_mipi_lvds>;
314
+ status = "disabled";
315
+ };
316
+
317
+ rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 {
318
+ compatible = "rockchip,rkcif-sditf";
319
+ rockchip,cif = <&rkcif_mipi_lvds>;
320
+ status = "disabled";
321
+ };
322
+
323
+ rkcif_mipi_lvds1: rkcif-mipi-lvds1 {
324
+ compatible = "rockchip,rkcif-mipi-lvds";
325
+ rockchip,hw = <&rkcif>;
326
+ iommus = <&rkcif_mmu>;
327
+ status = "disabled";
328
+ };
329
+
330
+ rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf {
331
+ compatible = "rockchip,rkcif-sditf";
332
+ rockchip,cif = <&rkcif_mipi_lvds1>;
333
+ status = "disabled";
334
+ };
335
+
336
+ rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 {
337
+ compatible = "rockchip,rkcif-sditf";
338
+ rockchip,cif = <&rkcif_mipi_lvds1>;
339
+ status = "disabled";
340
+ };
341
+
342
+ rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 {
343
+ compatible = "rockchip,rkcif-sditf";
344
+ rockchip,cif = <&rkcif_mipi_lvds1>;
345
+ status = "disabled";
346
+ };
347
+
348
+ rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 {
349
+ compatible = "rockchip,rkcif-sditf";
350
+ rockchip,cif = <&rkcif_mipi_lvds1>;
351
+ status = "disabled";
352
+ };
353
+
354
+ rkcif_mipi_lvds2: rkcif-mipi-lvds2 {
355
+ compatible = "rockchip,rkcif-mipi-lvds";
356
+ rockchip,hw = <&rkcif>;
357
+ iommus = <&rkcif_mmu>;
358
+ status = "disabled";
359
+ };
360
+
361
+ rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf {
362
+ compatible = "rockchip,rkcif-sditf";
363
+ rockchip,cif = <&rkcif_mipi_lvds2>;
364
+ status = "disabled";
365
+ };
366
+
367
+ rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 {
368
+ compatible = "rockchip,rkcif-sditf";
369
+ rockchip,cif = <&rkcif_mipi_lvds2>;
370
+ status = "disabled";
371
+ };
372
+
373
+ rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 {
374
+ compatible = "rockchip,rkcif-sditf";
375
+ rockchip,cif = <&rkcif_mipi_lvds2>;
376
+ status = "disabled";
377
+ };
378
+
379
+ rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 {
380
+ compatible = "rockchip,rkcif-sditf";
381
+ rockchip,cif = <&rkcif_mipi_lvds2>;
382
+ status = "disabled";
383
+ };
384
+
385
+ rkcif_mipi_lvds3: rkcif-mipi-lvds3 {
386
+ compatible = "rockchip,rkcif-mipi-lvds";
387
+ rockchip,hw = <&rkcif>;
388
+ iommus = <&rkcif_mmu>;
389
+ status = "disabled";
390
+ };
391
+
392
+ rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf {
393
+ compatible = "rockchip,rkcif-sditf";
394
+ rockchip,cif = <&rkcif_mipi_lvds3>;
395
+ status = "disabled";
396
+ };
397
+
398
+ rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 {
399
+ compatible = "rockchip,rkcif-sditf";
400
+ rockchip,cif = <&rkcif_mipi_lvds3>;
401
+ status = "disabled";
402
+ };
403
+
404
+ rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 {
405
+ compatible = "rockchip,rkcif-sditf";
406
+ rockchip,cif = <&rkcif_mipi_lvds3>;
407
+ status = "disabled";
408
+ };
409
+
410
+ rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 {
411
+ compatible = "rockchip,rkcif-sditf";
412
+ rockchip,cif = <&rkcif_mipi_lvds3>;
413
+ status = "disabled";
414
+ };
415
+
416
+ rkisp_vir0: rkisp-vir0 {
417
+ compatible = "rockchip,rkisp-vir";
418
+ rockchip,hw = <&rkisp>;
419
+ status = "disabled";
420
+ };
421
+
422
+ rkisp_vir1: rkisp-vir1 {
423
+ compatible = "rockchip,rkisp-vir";
424
+ rockchip,hw = <&rkisp>;
425
+ status = "disabled";
426
+ };
427
+
428
+ rkisp_vir2: rkisp-vir2 {
429
+ compatible = "rockchip,rkisp-vir";
430
+ rockchip,hw = <&rkisp>;
431
+ status = "disabled";
432
+ };
433
+
434
+ rkisp_vir3: rkisp-vir3 {
435
+ compatible = "rockchip,rkisp-vir";
436
+ rockchip,hw = <&rkisp>;
437
+ status = "disabled";
438
+ };
439
+
440
+ thermal_zones: thermal-zones {
441
+ soc_thermal: soc-thermal {
442
+ polling-delay-passive = <20>; /* milliseconds */
443
+ polling-delay = <1000>; /* milliseconds */
444
+
445
+ thermal-sensors = <&tsadc 0>;
446
+ trips {
447
+ soc_crit: soc-crit {
448
+ /* millicelsius */
449
+ temperature = <115000>;
450
+ /* millicelsius */
451
+ hysteresis = <2000>;
452
+ type = "critical";
453
+ };
454
+ };
455
+ };
456
+ };
457
+
458
+ timer {
459
+ compatible = "arm,armv8-timer";
460
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
461
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
462
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
463
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
464
+ };
465
+
466
+ scmi_shmem: scmi-shmem@10f000 {
467
+ compatible = "arm,scmi-shmem";
468
+ reg = <0x0 0x0010f000 0x0 0x100>;
469
+ };
470
+
471
+ usbdrd30: usbdrd {
472
+ compatible = "rockchip,rk3562-dwc3", "rockchip,rk3399-dwc3";
473
+ clocks = <&cru CLK_USB3OTG_REF>, <&cru CLK_USB3OTG_SUSPEND>,
474
+ <&cru ACLK_USB3OTG>, <&cru PCLK_PHP>;
475
+ clock-names = "ref", "suspend", "bus", "pipe_clk";
476
+ #address-cells = <2>;
477
+ #size-cells = <2>;
478
+ ranges;
479
+ status = "disabled";
480
+
481
+ usbdrd_dwc3: usb@fe500000 {
482
+ compatible = "snps,dwc3";
483
+ reg = <0x0 0xfe500000 0x0 0x400000>;
484
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
485
+ dr_mode = "otg";
486
+ phys = <&u2phy_otg>, <&combphy_pu PHY_TYPE_USB3>;
487
+ phy-names = "usb2-phy", "usb3-phy";
488
+ phy_type = "utmi_wide";
489
+ power-domains = <&power RK3562_PD_PHP>;
490
+ resets = <&cru SRST_USB3OTG>;
491
+ reset-names = "usb3-otg";
492
+ snps,dis_enblslpm_quirk;
493
+ snps,dis-u1-entry-quirk;
494
+ snps,dis-u2-entry-quirk;
495
+ snps,dis-u2-freeclk-exists-quirk;
496
+ snps,dis-del-phy-power-chg-quirk;
497
+ snps,dis-tx-ipgap-linecheck-quirk;
498
+ snps,dis_rxdet_inp3_quirk;
499
+ quirk-skip-phy-init;
500
+ status = "disabled";
501
+ };
502
+ };
503
+
504
+ gic: interrupt-controller@fe901000 {
505
+ compatible = "arm,gic-400";
506
+ #interrupt-cells = <3>;
507
+ #address-cells = <0>;
508
+ interrupt-controller;
509
+ reg = <0x0 0xfe901000 0 0x1000>,
510
+ <0x0 0xfe902000 0 0x2000>,
511
+ <0x0 0xfe904000 0 0x2000>,
512
+ <0x0 0xfe906000 0 0x2000>;
513
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
514
+ };
515
+
516
+ usb_host0_ehci: usb@fed00000 {
517
+ compatible = "generic-ehci";
518
+ reg = <0x0 0xfed00000 0x0 0x40000>;
519
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
520
+ clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>,
521
+ <&u2phy>;
522
+ clock-names = "usbhost", "arbiter", "utmi";
523
+ phys = <&u2phy_host>;
524
+ phy-names = "usb2-phy";
525
+ status = "disabled";
526
+ };
527
+
528
+ usb_host0_ohci: usb@fed40000 {
529
+ compatible = "generic-ohci";
530
+ reg = <0x0 0xfed40000 0x0 0x40000>;
531
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
532
+ clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>,
533
+ <&u2phy>;
534
+ clock-names = "usbhost", "arbiter", "utmi";
535
+ phys = <&u2phy_host>;
536
+ phy-names = "usb2-phy";
537
+ status = "disabled";
538
+ };
539
+
540
+ qos_dma2ddr: qos@fee03800 {
541
+ compatible = "syscon";
542
+ reg = <0x0 0xfee03800 0x0 0x20>;
543
+ };
544
+
545
+ qos_mcu: qos@fee10000 {
546
+ compatible = "syscon";
547
+ reg = <0x0 0xfee10000 0x0 0x20>;
548
+ };
549
+
550
+ qos_dft_apb: qos@fee10100 {
551
+ compatible = "syscon";
552
+ reg = <0x0 0xfee10100 0x0 0x20>;
553
+ };
554
+
555
+ qos_gmac: qos@fee10200 {
556
+ compatible = "syscon";
557
+ reg = <0x0 0xfee10200 0x0 0x20>;
558
+ };
559
+
560
+ qos_mac100: qos@fee10300 {
561
+ compatible = "syscon";
562
+ reg = <0x0 0xfee10300 0x0 0x20>;
563
+ };
564
+
565
+ qos_dcf: qos@fee10400 {
566
+ compatible = "syscon";
567
+ reg = <0x0 0xfee10400 0x0 0x20>;
568
+ };
569
+
570
+ qos_cpu: qos@fee20000 {
571
+ compatible = "syscon";
572
+ reg = <0x0 0xfee20000 0x0 0x20>;
573
+ };
574
+
575
+ qos_daplite_apb: qos@fee20100 {
576
+ compatible = "syscon";
577
+ reg = <0x0 0xfee20100 0x0 0x20>;
578
+ };
579
+
580
+ qos_gpu: qos@fee30000 {
581
+ compatible = "syscon";
582
+ reg = <0x0 0xfee30000 0x0 0x20>;
583
+ };
584
+
585
+ qos_npu: qos@fee40000 {
586
+ compatible = "syscon";
587
+ reg = <0x0 0xfee40000 0x0 0x20>;
588
+ };
589
+
590
+ qos_rkvdec: qos@fee50000 {
591
+ compatible = "syscon";
592
+ reg = <0x0 0xfee50000 0x0 0x20>;
593
+ };
594
+
595
+ qos_vepu: qos@fee60000 {
596
+ compatible = "syscon";
597
+ reg = <0x0 0xfee60000 0x0 0x20>;
598
+ };
599
+
600
+ qos_isp: qos@fee70000 {
601
+ compatible = "syscon";
602
+ reg = <0x0 0xfee70000 0x0 0x20>;
603
+ };
604
+
605
+ qos_vicap: qos@fee70100 {
606
+ compatible = "syscon";
607
+ reg = <0x0 0xfee70100 0x0 0x20>;
608
+ };
609
+
610
+ qos_vop: qos@fee80000 {
611
+ compatible = "syscon";
612
+ reg = <0x0 0xfee80000 0x0 0x20>;
613
+ };
614
+
615
+ qos_jpeg: qos@fee90000 {
616
+ compatible = "syscon";
617
+ reg = <0x0 0xfee90000 0x0 0x20>;
618
+ };
619
+
620
+ qos_rga_rd: qos@fee90100 {
621
+ compatible = "syscon";
622
+ reg = <0x0 0xfee90100 0x0 0x20>;
623
+ };
624
+
625
+ qos_rga_wr: qos@fee90200 {
626
+ compatible = "syscon";
627
+ reg = <0x0 0xfee90200 0x0 0x20>;
628
+ };
629
+
630
+ qos_pcie: qos@feea0000 {
631
+ compatible = "syscon";
632
+ reg = <0x0 0xfeea0000 0x0 0x20>;
633
+ };
634
+
635
+ qos_usb3: qos@feea0100 {
636
+ compatible = "syscon";
637
+ reg = <0x0 0xfeea0100 0x0 0x20>;
638
+ };
639
+
640
+ qos_crypto_apb: qos@feeb0000 {
641
+ compatible = "syscon";
642
+ reg = <0x0 0xfeeb0000 0x0 0x20>;
643
+ };
644
+
645
+ qos_crypto: qos@feeb0100 {
646
+ compatible = "syscon";
647
+ reg = <0x0 0xfeeb0100 0x0 0x20>;
648
+ };
649
+
650
+ qos_dmac: qos@feeb0200 {
651
+ compatible = "syscon";
652
+ reg = <0x0 0xfeeb0200 0x0 0x20>;
653
+ };
654
+
655
+ qos_emmc: qos@feeb0300 {
656
+ compatible = "syscon";
657
+ reg = <0x0 0xfeeb0300 0x0 0x20>;
658
+ };
659
+
660
+ qos_fspi: qos@feeb0400 {
661
+ compatible = "syscon";
662
+ reg = <0x0 0xfeeb0400 0x0 0x20>;
663
+ };
664
+
665
+ qos_rkdma: qos@feeb0500 {
666
+ compatible = "syscon";
667
+ reg = <0x0 0xfeeb0500 0x0 0x20>;
668
+ };
669
+
670
+ qos_sdmmc0: qos@feeb0600 {
671
+ compatible = "syscon";
672
+ reg = <0x0 0xfeeb0600 0x0 0x20>;
673
+ };
674
+
675
+ qos_sdmmc1: qos@feeb0700 {
676
+ compatible = "syscon";
677
+ reg = <0x0 0xfeeb0700 0x0 0x20>;
678
+ };
679
+
680
+ qos_usb2: qos@feeb0800 {
681
+ compatible = "syscon";
682
+ reg = <0x0 0xfeeb0800 0x0 0x20>;
683
+ };
684
+
685
+ pmu_grf: syscon@ff010000 {
686
+ compatible = "rockchip,rk3562-pmu-grf", "syscon", "simple-mfd";
687
+ reg = <0x0 0xff010000 0x0 0x10000>;
688
+
689
+ reboot_mode: reboot-mode {
690
+ compatible = "syscon-reboot-mode";
691
+ offset = <0x200>;
692
+ mode-bootloader = <BOOT_BL_DOWNLOAD>;
693
+ mode-charge = <BOOT_CHARGING>;
694
+ mode-fastboot = <BOOT_FASTBOOT>;
695
+ mode-loader = <BOOT_BL_DOWNLOAD>;
696
+ mode-normal = <BOOT_NORMAL>;
697
+ mode-recovery = <BOOT_RECOVERY>;
698
+ mode-ums = <BOOT_UMS>;
699
+ mode-panic = <BOOT_PANIC>;
700
+ mode-watchdog = <BOOT_WATCHDOG>;
701
+ };
702
+ };
703
+
704
+ sys_grf: syscon@ff030000 {
705
+ compatible = "rockchip,rk3562-sys-grf", "syscon", "simple-mfd";
706
+ reg = <0x0 0xff030000 0x0 0x10000>;
707
+
708
+ lvds: lvds {
709
+ compatible = "rockchip,rk3562-lvds";
710
+ phys = <&video_phy>;
711
+ phy-names = "phy";
712
+ status = "disabled";
713
+
714
+ ports {
715
+ #address-cells = <1>;
716
+ #size-cells = <0>;
717
+
718
+ port@0 {
719
+ reg = <0>;
720
+ #address-cells = <1>;
721
+ #size-cells = <0>;
722
+
723
+ lvds_in_vp0: endpoint@0 {
724
+ reg = <0>;
725
+ remote-endpoint = <&vp0_out_lvds>;
726
+ status = "disabled";
727
+ };
728
+
729
+ lvds_in_vp1: endpoint@1 {
730
+ reg = <1>;
731
+ remote-endpoint = <&vp1_out_lvds>;
732
+ status = "disabled";
733
+ };
734
+ };
735
+ };
736
+ };
737
+
738
+ rgb: rgb {
739
+ compatible = "rockchip,rk3562-rgb";
740
+ pinctrl-names = "default";
741
+ pinctrl-0 = <&vo_pins>;
742
+ status = "disabled";
743
+
744
+ ports {
745
+ #address-cells = <1>;
746
+ #size-cells = <0>;
747
+
748
+ port@0 {
749
+ reg = <0>;
750
+ #address-cells = <1>;
751
+ #size-cells = <0>;
752
+
753
+ rgb_in_vp0: endpoint@0 {
754
+ reg = <0>;
755
+ remote-endpoint = <&vp0_out_rgb>;
756
+ status = "disabled";
757
+ };
758
+
759
+ rgb_in_vp1: endpoint@1 {
760
+ reg = <1>;
761
+ remote-endpoint = <&vp1_out_rgb>;
762
+ status = "disabled";
763
+ };
764
+ };
765
+ };
766
+ };
767
+ };
768
+
769
+ peri_grf: syscon@ff040000 {
770
+ compatible = "rockchip,rk3562-peri-grf", "syscon";
771
+ reg = <0x0 0xff040000 0x0 0x10000>;
772
+ };
773
+
774
+ ioc_grf: syscon@ff060000 {
775
+ compatible = "rockchip,rk3562-ioc-grf", "syscon";
776
+ reg = <0x0 0xff060000 0x0 0x30000>;
777
+ };
778
+
779
+ usbphy_grf: syscon@ff090000 {
780
+ compatible = "rockchip,rk3562-usbphy-grf", "syscon";
781
+ reg = <0x0 0xff090000 0x0 0x8000>;
782
+ };
783
+
784
+ pipephy_grf: syscon@ff098000 {
785
+ compatible = "rockchip,rk3562-pipephy-grf", "syscon";
786
+ reg = <0x0 0xff098000 0x0 0x8000>;
787
+ };
788
+
789
+ cru: clock-controller@ff100000 {
790
+ compatible = "rockchip,rk3562-cru";
791
+ reg = <0x0 0xff100000 0x0 0x40000>;
792
+ rockchip,grf = <&sys_grf>;
793
+ #clock-cells = <1>;
794
+ #reset-cells = <1>;
795
+
796
+ assigned-clocks =
797
+ <&cru PLL_GPLL>, <&cru PLL_CPLL>,
798
+ <&cru ARMCLK>;
799
+ assigned-clock-rates =
800
+ <1188000000>, <1000000000>,
801
+ <600000000>;
802
+ };
803
+
804
+ i2c0: i2c@ff200000 {
805
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
806
+ reg = <0x0 0xff200000 0x0 0x1000>;
807
+ clocks = <&cru CLK_PMU0_I2C0>, <&cru PCLK_PMU0_I2C0>;
808
+ clock-names = "i2c", "pclk";
809
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
810
+ pinctrl-names = "default";
811
+ pinctrl-0 = <&i2c0_xfer>;
812
+ #address-cells = <1>;
813
+ #size-cells = <0>;
814
+ status = "disabled";
815
+ };
816
+
817
+ uart0: serial@ff210000 {
818
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
819
+ reg = <0x0 0xff210000 0x0 0x100>;
820
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
821
+ clocks = <&cru SCLK_PMU1_UART0>, <&cru PCLK_PMU1_UART0>;
822
+ clock-names = "baudclk", "apb_pclk";
823
+ reg-shift = <2>;
824
+ reg-io-width = <4>;
825
+ dmas = <&dmac 0>;
826
+ status = "disabled";
827
+ };
828
+
829
+ spi0: spi@ff220000 {
830
+ compatible = "rockchip,rk3066-spi";
831
+ reg = <0x0 0xff220000 0x0 0x1000>;
832
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
833
+ #address-cells = <1>;
834
+ #size-cells = <0>;
835
+ clocks = <&cru CLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>;
836
+ clock-names = "spiclk", "apb_pclk", "sclk_in";
837
+ dmas = <&dmac 13>, <&dmac 12>;
838
+ dma-names = "tx", "rx";
839
+ pinctrl-names = "default";
840
+ pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
841
+ num-cs = <2>;
842
+ status = "disabled";
843
+ };
844
+
845
+ pwm0: pwm@ff230000 {
846
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
847
+ reg = <0x0 0xff230000 0x0 0x10>;
848
+ #pwm-cells = <3>;
849
+ pinctrl-names = "active";
850
+ pinctrl-0 = <&pwm0m0_pins>;
851
+ clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
852
+ clock-names = "pwm", "pclk";
853
+ status = "disabled";
854
+ };
855
+
856
+ pwm1: pwm@ff230010 {
857
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
858
+ reg = <0x0 0xff230010 0x0 0x10>;
859
+ #pwm-cells = <3>;
860
+ pinctrl-names = "active";
861
+ pinctrl-0 = <&pwm1m0_pins>;
862
+ clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
863
+ clock-names = "pwm", "pclk";
864
+ status = "disabled";
865
+ };
866
+
867
+ pwm2: pwm@ff230020 {
868
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
869
+ reg = <0x0 0xff230020 0x0 0x10>;
870
+ #pwm-cells = <3>;
871
+ pinctrl-names = "active";
872
+ pinctrl-0 = <&pwm2m0_pins>;
873
+ clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
874
+ clock-names = "pwm", "pclk";
875
+ status = "disabled";
876
+ };
877
+
878
+ pwm3: pwm@ff230030 {
879
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
880
+ reg = <0x0 0xff230030 0x0 0x10>;
881
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
882
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
883
+ #pwm-cells = <3>;
884
+ pinctrl-names = "active";
885
+ pinctrl-0 = <&pwm3m0_pins>;
886
+ clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
887
+ clock-names = "pwm", "pclk";
888
+ status = "disabled";
889
+ };
890
+
891
+ pmu: power-management@ff258000 {
892
+ compatible = "rockchip,rk3562-pmu", "syscon", "simple-mfd";
893
+ reg = <0x0 0xff258000 0x0 0x1000>;
894
+
895
+ power: power-controller {
896
+ compatible = "rockchip,rk3562-power-controller";
897
+ #power-domain-cells = <1>;
898
+ #address-cells = <1>;
899
+ #size-cells = <0>;
900
+ status = "okay";
901
+
902
+ /* These power domains are grouped by VD_GPU */
903
+ pd_gpu@RK3562_PD_GPU {
904
+ reg = <RK3562_PD_GPU>;
905
+ pm_qos = <&qos_gpu>;
906
+ };
907
+ /* These power domains are grouped by VD_NPU */
908
+ pd_npu@RK3562_PD_NPU {
909
+ reg = <RK3562_PD_NPU>;
910
+ pm_qos = <&qos_npu>;
911
+ };
912
+ /* These power domains are grouped by VD_LOGIC */
913
+ pd_vdpu@RK3562_PD_VDPU {
914
+ reg = <RK3562_PD_VDPU>;
915
+ pm_qos = <&qos_rkvdec>;
916
+ };
917
+ pd_vi@RK3562_PD_VI {
918
+ reg = <RK3562_PD_VI>;
919
+ #address-cells = <1>;
920
+ #size-cells = <0>;
921
+ pm_qos = <&qos_isp>,
922
+ <&qos_vicap>;
923
+
924
+ pd_vepu@RK3562_PD_VEPU {
925
+ reg = <RK3562_PD_VEPU>;
926
+ pm_qos = <&qos_vepu>;
927
+ };
928
+ };
929
+ pd_vo@RK3562_PD_VO {
930
+ reg = <RK3562_PD_VO>;
931
+ #address-cells = <1>;
932
+ #size-cells = <0>;
933
+ pm_qos = <&qos_vop>;
934
+
935
+ pd_rga@RK3562_PD_RGA {
936
+ reg = <RK3562_PD_RGA>;
937
+ pm_qos = <&qos_rga_rd>,
938
+ <&qos_rga_wr>,
939
+ <&qos_jpeg>;
940
+ };
941
+ };
942
+ pd_php@RK3562_PD_PHP {
943
+ reg = <RK3562_PD_PHP>;
944
+ pm_qos = <&qos_pcie>,
945
+ <&qos_usb3>;
946
+ };
947
+ };
948
+ };
949
+
950
+ pmu_mailbox: mailbox@ff290000 {
951
+ compatible = "rockchip,rk3562-mailbox",
952
+ "rockchip,rk3368-mailbox";
953
+ reg = <0x0 0xff290000 0x0 0x200>;
954
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
955
+ clocks = <&cru PCLK_PMU1_MAILBOX>;
956
+ clock-names = "pclk_mailbox";
957
+ #mbox-cells = <1>;
958
+ status = "disabled";
959
+ };
960
+
961
+ rknpu: npu@ff300000 {
962
+ compatible = "rockchip,rk3562-rknpu";
963
+ reg = <0x0 0xff300000 0x0 0x10000>;
964
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
965
+ clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>;
966
+ clock-names = "aclk", "hclk";
967
+ assigned-clocks = <&cru ACLK_RKNN>;
968
+ assigned-clock-rates = <600000000>;
969
+ resets = <&cru SRST_A_RKNN>, <&cru SRST_H_RKNN>;
970
+ reset-names = "srst_a", "srst_h";
971
+ power-domains = <&power RK3562_PD_NPU>;
972
+ iommus = <&rknpu_mmu>;
973
+ status = "disabled";
974
+ };
975
+
976
+ rknpu_mmu: iommu@ff30b000 {
977
+ compatible = "rockchip,iommu-v2";
978
+ reg = <0x0 0xff30b000 0x0 0x40>;
979
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
980
+ interrupt-names = "rknpu_mmu";
981
+ clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>;
982
+ clock-names = "aclk", "iface";
983
+ power-domains = <&power RK3562_PD_NPU>;
984
+ #iommu-cells = <0>;
985
+ status = "disabled";
986
+ };
987
+
988
+ gpu: gpu@ff320000 {
989
+ compatible = "arm,mali-bifrost";
990
+ reg = <0x0 0xff320000 0x0 0x4000>;
991
+
992
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
993
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
994
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
995
+ interrupt-names = "GPU", "MMU", "JOB";
996
+
997
+ upthreshold = <40>;
998
+ downdifferential = <10>;
999
+
1000
+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_BRG>;
1001
+ clock-names = "clk_gpu", "clk_gpu_brg";
1002
+ power-domains = <&power RK3562_PD_GPU>;
1003
+ operating-points-v2 = <&gpu_opp_table>;
1004
+ #cooling-cells = <2>;
1005
+
1006
+ status = "disabled";
1007
+ };
1008
+
1009
+ gpu_opp_table: gpu-opp-table {
1010
+ compatible = "operating-points-v2";
1011
+
1012
+ nvmem-cells = <&gpu_leakage>;
1013
+ nvmem-cell-names = "leakage";
1014
+
1015
+ opp-300000000 {
1016
+ opp-hz = /bits/ 64 <300000000>;
1017
+ opp-microvolt = <900000 900000 1000000>;
1018
+ };
1019
+ opp-400000000 {
1020
+ opp-hz = /bits/ 64 <400000000>;
1021
+ opp-microvolt = <900000 900000 1000000>;
1022
+ };
1023
+ };
1024
+
1025
+ rkvdec: rkvdec@ff340100 {
1026
+ compatible = "rockchip,rkv-decoder-vdpu382", "rockchip,rkv-decoder-v2";
1027
+ reg = <0x0 0xff340100 0x0 0x400>, <0x0 0xff340000 0x0 0x100>;
1028
+ reg-names = "regs", "link";
1029
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1030
+ interrupt-names = "irq_dec";
1031
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>;
1032
+ clock-names = "aclk_vcodec", "hclk_vcodec","clk_hevc_cabac";
1033
+ rockchip,normal-rates = <198000000>, <0>, <396000000>;
1034
+ assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>;
1035
+ assigned-clock-rates = <198000000>, <396000000>;
1036
+ resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>,
1037
+ <&cru SRST_RKVDEC_HEVC_CA>;
1038
+ reset-names = "video_a", "video_h", "video_hevc_cabac";
1039
+ power-domains = <&power RK3562_PD_VDPU>;
1040
+ iommus = <&rkvdec_mmu>;
1041
+ rockchip,srv = <&mpp_srv>;
1042
+ rockchip,taskqueue-node = <0>;
1043
+ rockchip,resetgroup-node = <0>;
1044
+ rockchip,task-capacity = <16>;
1045
+ status = "disabled";
1046
+ };
1047
+
1048
+ rkvdec_mmu: iommu@ff340800 {
1049
+ compatible = "rockchip,iommu-v2";
1050
+ reg = <0x0 0xff340800 0x0 0x40>, <0x0 0xff340900 0x0 0x40>;
1051
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1052
+ interrupt-names = "rkvdec_mmu";
1053
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
1054
+ clock-names = "aclk", "iface";
1055
+ power-domains = <&power RK3562_PD_VDPU>;
1056
+ #iommu-cells = <0>;
1057
+ status = "disabled";
1058
+ };
1059
+
1060
+ rkvenc: rkvenc@ff360000 {
1061
+ compatible = "rockchip,rkv-encoder-vepu540c", "rockchip,rkv-encoder-v2";
1062
+ reg = <0x0 0xff360000 0x0 0x6000>;
1063
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1064
+ interrupt-names = "irq_rkvenc";
1065
+ clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_RKVENC_CORE>;
1066
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
1067
+ rockchip,normal-rates = <297000000>, <0>, <297000000>;
1068
+ resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>,
1069
+ <&cru SRST_RKVENC_CORE>;
1070
+ reset-names = "video_a", "video_h", "video_core";
1071
+ assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>;
1072
+ assigned-clock-rates = <297000000>, <297000000>;
1073
+ power-domains = <&power RK3562_PD_VEPU>;
1074
+ iommus = <&rkvenc_mmu>;
1075
+ rockchip,srv = <&mpp_srv>;
1076
+ rockchip,taskqueue-node = <1>;
1077
+ rockchip,resetgroup-node = <1>;
1078
+ status = "disabled";
1079
+ };
1080
+
1081
+ rkvenc_mmu: iommu@ff36f000 {
1082
+ compatible = "rockchip,iommu-v2";
1083
+ reg = <0x0 0xff36f000 0x0 0x40>;
1084
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1085
+ interrupt-names = "rkvenc_mmu";
1086
+ clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>;
1087
+ clock-names = "aclk", "iface";
1088
+ power-domains = <&power RK3562_PD_VEPU>;
1089
+ #iommu-cells = <0>;
1090
+ status = "disabled";
1091
+ };
1092
+
1093
+ mipi0_csi2: mipi0-csi2@ff380000 {
1094
+ compatible = "rockchip,rk3562-mipi-csi2";
1095
+ reg = <0x0 0xff380000 0x0 0x10000>;
1096
+ reg-names = "csihost_regs";
1097
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1098
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1099
+ interrupt-names = "csi-intr1", "csi-intr2";
1100
+ clocks = <&cru PCLK_CSIHOST0>;
1101
+ clock-names = "pclk_csi2host";
1102
+ resets = <&cru SRST_P_CSIHOST0>;
1103
+ reset-names = "srst_csihost_p";
1104
+ status = "disabled";
1105
+ };
1106
+
1107
+ mipi1_csi2: mipi1-csi2@ff390000 {
1108
+ compatible = "rockchip,rk3562-mipi-csi2";
1109
+ reg = <0x0 0xff390000 0x0 0x10000>;
1110
+ reg-names = "csihost_regs";
1111
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1112
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1113
+ interrupt-names = "csi-intr1", "csi-intr2";
1114
+ clocks = <&cru PCLK_CSIHOST1>;
1115
+ clock-names = "pclk_csi2host";
1116
+ resets = <&cru SRST_P_CSIHOST1>;
1117
+ reset-names = "srst_csihost_p";
1118
+ status = "disabled";
1119
+ };
1120
+
1121
+ mipi2_csi2: mipi2-csi2@ff3a0000 {
1122
+ compatible = "rockchip,rk3562-mipi-csi2";
1123
+ reg = <0x0 0xff3a0000 0x0 0x10000>;
1124
+ reg-names = "csihost_regs";
1125
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
1126
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1127
+ interrupt-names = "csi-intr1", "csi-intr2";
1128
+ clocks = <&cru PCLK_CSIHOST2>;
1129
+ clock-names = "pclk_csi2host";
1130
+ resets = <&cru SRST_P_CSIHOST2>;
1131
+ reset-names = "srst_csihost_p";
1132
+ status = "disabled";
1133
+ };
1134
+
1135
+ mipi3_csi2: mipi3-csi2@ff3b0000 {
1136
+ compatible = "rockchip,rk3562-mipi-csi2";
1137
+ reg = <0x0 0xff3b0000 0x0 0x10000>;
1138
+ reg-names = "csihost_regs";
1139
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1140
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1141
+ interrupt-names = "csi-intr1", "csi-intr2";
1142
+ clocks = <&cru PCLK_CSIHOST3>;
1143
+ clock-names = "pclk_csi2host";
1144
+ resets = <&cru SRST_P_CSIHOST3>;
1145
+ reset-names = "srst_csihost_p";
1146
+ status = "disabled";
1147
+ };
1148
+
1149
+ csi2_dphy0_hw: csi2-dphy0-hw@ff3c0000 {
1150
+ compatible = "rockchip,rk3562-csi2-dphy-hw";
1151
+ reg = <0x0 0xff3c0000 0x0 0x10000>;
1152
+ clocks = <&cru PCLK_CSIPHY0>;
1153
+ clock-names = "pclk";
1154
+ resets = <&cru SRST_P_CSIPHY0>;
1155
+ reset-names = "srst_p_csiphy0";
1156
+ rockchip,grf = <&sys_grf>;
1157
+ status = "disabled";
1158
+ };
1159
+
1160
+ csi2_dphy1_hw: csi2-dphy1-hw@ff3d0000 {
1161
+ compatible = "rockchip,rk3562-csi2-dphy-hw";
1162
+ reg = <0x0 0xff3d0000 0x0 0x10000>;
1163
+ clocks = <&cru PCLK_CSIPHY1>;
1164
+ clock-names = "pclk";
1165
+ resets = <&cru SRST_P_CSIPHY1>;
1166
+ reset-names = "srst_p_csiphy1";
1167
+ rockchip,grf = <&sys_grf>;
1168
+ status = "disabled";
1169
+ };
1170
+
1171
+ rkcif: rkcif@ff3e0000 {
1172
+ compatible = "rockchip,rk3562-cif";
1173
+ reg = <0x0 0xff3e0000 0x0 0x800>;
1174
+ reg-names = "cif_regs";
1175
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1176
+ interrupt-names = "cif-intr";
1177
+ clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>;
1178
+ clock-names = "aclk_cif", "hclk_cif", "dclk_cif";
1179
+ resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>,
1180
+ <&cru SRST_I0_VICAP>, <&cru SRST_I1_VICAP>, <&cru SRST_I2_VICAP>,
1181
+ <&cru SRST_I3_VICAP>;
1182
+ reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d",
1183
+ "rst_cif_i0", "rst_cif_i1", "rst_cif_i2",
1184
+ "rst_cif_i3";
1185
+ power-domains = <&power RK3562_PD_VI>;
1186
+ rockchip,grf = <&sys_grf>;
1187
+ iommus = <&rkcif_mmu>;
1188
+ status = "disabled";
1189
+ };
1190
+
1191
+ rkcif_mmu: iommu@ff3e0800 {
1192
+ compatible = "rockchip,iommu-v2";
1193
+ reg = <0x0 0xff3e0800 0x0 0x100>;
1194
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1195
+ interrupt-names = "cif_mmu";
1196
+ clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
1197
+ clock-names = "aclk", "iface";
1198
+ power-domains = <&power RK3562_PD_VI>;
1199
+ rockchip,disable-mmu-reset;
1200
+ #iommu-cells = <0>;
1201
+ status = "disabled";
1202
+ };
1203
+
1204
+ rkisp: isp@ff3f0000 {
1205
+ compatible = "rockchip,rk3562-rkisp";
1206
+ reg = <0x0 0xff3f0000 0x0 0x7f00>;
1207
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1208
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
1209
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1210
+ interrupt-names = "mipi_irq", "mi_irq", "isp_irq";
1211
+ clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>;
1212
+ clock-names = "aclk_isp", "hclk_isp", "clk_isp_core";
1213
+ power-domains = <&power RK3562_PD_VI>;
1214
+ iommus = <&rkisp_mmu>;
1215
+ status = "disabled";
1216
+ };
1217
+
1218
+ rkisp_mmu: iommu@ff3f7f00 {
1219
+ compatible = "rockchip,iommu-v2";
1220
+ reg = <0x0 0xff3f7f00 0x0 0x100>;
1221
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1222
+ interrupt-names = "isp_mmu";
1223
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>;
1224
+ clock-names = "aclk", "iface";
1225
+ rockchip,disable-mmu-reset;
1226
+ #iommu-cells = <0>;
1227
+ power-domains = <&power RK3562_PD_VI>;
1228
+ status = "disabled";
1229
+ };
1230
+
1231
+ vop: vop@ff400000 {
1232
+ compatible = "rockchip,rk3562-vop";
1233
+ reg = <0x0 0xff400000 0x0 0x2000>, <0x0 0xff405000 0x0 0x1000>;
1234
+ reg-names = "regs", "gamma_lut";
1235
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1236
+ clocks = <&cru ACLK_VOP>,
1237
+ <&cru HCLK_VOP>,
1238
+ <&cru DCLK_VOP>,
1239
+ <&cru DCLK_VOP1>;
1240
+ clock-names = "aclk_vop",
1241
+ "hclk_vop",
1242
+ "dclk_vp0",
1243
+ "dclk_vp1";
1244
+ resets = <&cru SRST_A_VOP>,
1245
+ <&cru SRST_H_VOP>,
1246
+ <&cru SRST_D_VOP>,
1247
+ <&cru SRST_D_VOP1>;
1248
+ reset-names = "axi",
1249
+ "ahb",
1250
+ "dclk_vp0",
1251
+ "dclk_vp1";
1252
+ iommus = <&vop_mmu>;
1253
+ power-domains = <&power RK3562_PD_VO>;
1254
+ rockchip,grf = <&sys_grf>;
1255
+ status = "disabled";
1256
+
1257
+ vop_out: ports {
1258
+ #address-cells = <1>;
1259
+ #size-cells = <0>;
1260
+
1261
+ port@0 {
1262
+ #address-cells = <1>;
1263
+ #size-cells = <0>;
1264
+ reg = <0>;
1265
+
1266
+ vp0_out_rgb: endpoint@0 {
1267
+ reg = <0>;
1268
+ remote-endpoint = <&rgb_in_vp0>;
1269
+ };
1270
+
1271
+ vp0_out_dsi: endpoint@1 {
1272
+ reg = <1>;
1273
+ remote-endpoint = <&dsi_in_vp0>;
1274
+ };
1275
+
1276
+ vp0_out_lvds: endpoint@2 {
1277
+ reg = <2>;
1278
+ remote-endpoint = <&lvds_in_vp0>;
1279
+ };
1280
+ };
1281
+
1282
+ port@1 {
1283
+ #address-cells = <1>;
1284
+ #size-cells = <0>;
1285
+ reg = <1>;
1286
+
1287
+ vp1_out_rgb: endpoint@0 {
1288
+ reg = <0>;
1289
+ remote-endpoint = <&rgb_in_vp1>;
1290
+ };
1291
+
1292
+ vp1_out_dsi: endpoint@1 {
1293
+ reg = <1>;
1294
+ remote-endpoint = <&dsi_in_vp1>;
1295
+ };
1296
+
1297
+ vp1_out_lvds: endpoint@2 {
1298
+ reg = <2>;
1299
+ remote-endpoint = <&lvds_in_vp1>;
1300
+ };
1301
+ };
1302
+ };
1303
+ };
1304
+
1305
+ vop_mmu: iommu@ff407e00 {
1306
+ compatible = "rockchip,iommu-v2";
1307
+ reg = <0x0 0xff407e00 0x0 0x100>;
1308
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1309
+ interrupt-names = "vop_mmu";
1310
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1311
+ clock-names = "aclk", "iface";
1312
+ #iommu-cells = <0>;
1313
+ rockchip,disable-device-link-resume;
1314
+ rockchip,shootdown-entire;
1315
+ status = "disabled";
1316
+ };
1317
+
1318
+ rga2: rga@ff440000 {
1319
+ compatible = "rockchip,rga2_core0";
1320
+ reg = <0x0 0xff440000 0x0 0x1000>;
1321
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1322
+ interrupt-names = "rga2_irq";
1323
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
1324
+ clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2";
1325
+ iommus = <&rga2_mmu>;
1326
+ power-domains = <&power RK3562_PD_RGA>;
1327
+ status = "disabled";
1328
+ };
1329
+
1330
+ rga2_mmu: iommu@ff440f00 {
1331
+ compatible = "rockchip,iommu-v2";
1332
+ reg = <0x0 0xff440f00 0x0 0x100>;
1333
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1334
+ interrupt-names = "rga2_mmu";
1335
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>;
1336
+ clock-names = "aclk", "iface";
1337
+ #iommu-cells = <0>;
1338
+ power-domains = <&power RK3562_PD_RGA>;
1339
+ status = "disabled";
1340
+ };
1341
+
1342
+ jpegd: jpegd@ff450000 {
1343
+ compatible = "rockchip,rkv-jpeg-decoder-v1";
1344
+ reg = <0x0 0xff450000 0x0 0x400>;
1345
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1346
+ clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
1347
+ clock-names = "aclk_vcodec", "hclk_vcodec";
1348
+ rockchip,disable-auto-freq;
1349
+ resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>;
1350
+ reset-names = "video_a", "video_h";
1351
+ power-domains = <&power RK3562_PD_RGA>;
1352
+ iommus = <&jpegd_mmu>;
1353
+ rockchip,srv = <&mpp_srv>;
1354
+ rockchip,taskqueue-node = <2>;
1355
+ rockchip,resetgroup-node = <2>;
1356
+ status = "disabled";
1357
+ };
1358
+
1359
+ jpegd_mmu: iommu@ff450480 {
1360
+ compatible = "rockchip,iommu-v2";
1361
+ reg = <0x0 0xff450480 0x0 0x40>;
1362
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1363
+ interrupt-names = "jpegd_mmu";
1364
+ clock-names = "aclk", "iface";
1365
+ clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
1366
+ power-domains = <&power RK3562_PD_RGA>;
1367
+ #iommu-cells = <0>;
1368
+ status = "disabled";
1369
+ };
1370
+
1371
+ pcie2x1: pcie@ff500000 {
1372
+ compatible = "rockchip,rk3562-pcie", "snps,dw-pcie";
1373
+ #address-cells = <3>;
1374
+ #size-cells = <2>;
1375
+ bus-range = <0x0 0xff>;
1376
+ clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
1377
+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
1378
+ <&cru CLK_PCIE20_AUX>;
1379
+ clock-names = "aclk_mst", "aclk_slv",
1380
+ "aclk_dbi", "pclk", "aux";
1381
+ device_type = "pci";
1382
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1383
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1384
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1385
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1386
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1387
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1388
+ interrupt-names = "msi", "pmc", "sys", "legacy", "msg", "err";
1389
+ #interrupt-cells = <1>;
1390
+ interrupt-map-mask = <0 0 0 7>;
1391
+ interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
1392
+ <0 0 0 2 &pcie2x1_intc 1>,
1393
+ <0 0 0 3 &pcie2x1_intc 2>,
1394
+ <0 0 0 4 &pcie2x1_intc 3>;
1395
+ linux,pci-domain = <0>;
1396
+ num-ib-windows = <8>;
1397
+ num-viewport = <8>;
1398
+ num-ob-windows = <2>;
1399
+ max-link-speed = <2>;
1400
+ num-lanes = <1>;
1401
+ phys = <&combphy_pu PHY_TYPE_PCIE>;
1402
+ phy-names = "pcie-phy";
1403
+ ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000
1404
+ 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
1405
+ 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
1406
+ 0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
1407
+ reg = <0x0 0xfe000000 0x0 0x400000>,
1408
+ <0x0 0xff500000 0x0 0x10000>;
1409
+ reg-names = "pcie-dbi", "pcie-apb";
1410
+ resets = <&cru SRST_PCIE20_POWERUP>;
1411
+ reset-names = "pipe";
1412
+ status = "disabled";
1413
+
1414
+ pcie2x1_intc: legacy-interrupt-controller {
1415
+ interrupt-controller;
1416
+ #address-cells = <0>;
1417
+ #interrupt-cells = <1>;
1418
+ interrupt-parent = <&gic>;
1419
+ };
1420
+ };
1421
+
1422
+ spi1: spi@ff640000 {
1423
+ compatible = "rockchip,rk3066-spi";
1424
+ reg = <0x0 0xff640000 0x0 0x1000>;
1425
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1426
+ #address-cells = <1>;
1427
+ #size-cells = <0>;
1428
+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1429
+ clock-names = "spiclk", "apb_pclk";
1430
+ dmas = <&dmac 15>, <&dmac 14>;
1431
+ dma-names = "tx", "rx";
1432
+ pinctrl-names = "default";
1433
+ pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
1434
+ num-cs = <2>;
1435
+ status = "disabled";
1436
+ };
1437
+
1438
+ spi2: spi@ff650000 {
1439
+ compatible = "rockchip,rk3066-spi";
1440
+ reg = <0x0 0xff650000 0x0 0x1000>;
1441
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1442
+ #address-cells = <1>;
1443
+ #size-cells = <0>;
1444
+ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1445
+ clock-names = "spiclk", "apb_pclk";
1446
+ dmas = <&dmac 17>, <&dmac 16>;
1447
+ dma-names = "tx", "rx";
1448
+ pinctrl-names = "default";
1449
+ pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
1450
+ num-cs = <2>;
1451
+ status = "disabled";
1452
+ };
1453
+
1454
+ uart1: serial@ff670000 {
1455
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1456
+ reg = <0x0 0xff670000 0x0 0x100>;
1457
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1458
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1459
+ clock-names = "baudclk", "apb_pclk";
1460
+ reg-shift = <2>;
1461
+ reg-io-width = <4>;
1462
+ dmas = <&dmac 1>, <&dmac 10>;
1463
+ status = "disabled";
1464
+ };
1465
+
1466
+ uart2: serial@ff680000 {
1467
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1468
+ reg = <0x0 0xff680000 0x0 0x100>;
1469
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1470
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1471
+ clock-names = "baudclk", "apb_pclk";
1472
+ reg-shift = <2>;
1473
+ reg-io-width = <4>;
1474
+ dmas = <&dmac 2>;
1475
+ status = "disabled";
1476
+ };
1477
+
1478
+ uart3: serial@ff690000 {
1479
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1480
+ reg = <0x0 0xff690000 0x0 0x100>;
1481
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1482
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1483
+ clock-names = "baudclk", "apb_pclk";
1484
+ reg-shift = <2>;
1485
+ reg-io-width = <4>;
1486
+ dmas = <&dmac 3>;
1487
+ status = "disabled";
1488
+ };
1489
+
1490
+ uart4: serial@ff6a0000 {
1491
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1492
+ reg = <0x0 0xff6a0000 0x0 0x100>;
1493
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1494
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1495
+ clock-names = "baudclk", "apb_pclk";
1496
+ reg-shift = <2>;
1497
+ reg-io-width = <4>;
1498
+ dmas = <&dmac 4>;
1499
+ status = "disabled";
1500
+ };
1501
+
1502
+ uart5: serial@ff6b0000 {
1503
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1504
+ reg = <0x0 0xff6b0000 0x0 0x100>;
1505
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1506
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1507
+ clock-names = "baudclk", "apb_pclk";
1508
+ reg-shift = <2>;
1509
+ reg-io-width = <4>;
1510
+ dmas = <&dmac 5>, <&dmac 11>;
1511
+ status = "disabled";
1512
+ };
1513
+
1514
+ uart6: serial@ff6c0000 {
1515
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1516
+ reg = <0x0 0xff6c0000 0x0 0x100>;
1517
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1518
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1519
+ clock-names = "baudclk", "apb_pclk";
1520
+ reg-shift = <2>;
1521
+ reg-io-width = <4>;
1522
+ dmas = <&dmac 6>;
1523
+ status = "disabled";
1524
+ };
1525
+
1526
+ uart7: serial@ff6d0000 {
1527
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1528
+ reg = <0x0 0xff6d0000 0x0 0x100>;
1529
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1530
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1531
+ clock-names = "baudclk", "apb_pclk";
1532
+ reg-shift = <2>;
1533
+ reg-io-width = <4>;
1534
+ dmas = <&dmac 7>;
1535
+ status = "disabled";
1536
+ };
1537
+
1538
+ uart8: serial@ff6e0000 {
1539
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1540
+ reg = <0x0 0xff6e0000 0x0 0x100>;
1541
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1542
+ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1543
+ clock-names = "baudclk", "apb_pclk";
1544
+ reg-shift = <2>;
1545
+ reg-io-width = <4>;
1546
+ dmas = <&dmac 8>;
1547
+ status = "disabled";
1548
+ };
1549
+
1550
+ uart9: serial@ff6f0000 {
1551
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
1552
+ reg = <0x0 0xff6f0000 0x0 0x100>;
1553
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1554
+ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1555
+ clock-names = "baudclk", "apb_pclk";
1556
+ reg-shift = <2>;
1557
+ reg-io-width = <4>;
1558
+ dmas = <&dmac 9>;
1559
+ status = "disabled";
1560
+ };
1561
+
1562
+ pwm4: pwm@ff700000 {
1563
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1564
+ reg = <0x0 0xff700000 0x0 0x10>;
1565
+ #pwm-cells = <3>;
1566
+ pinctrl-names = "active";
1567
+ pinctrl-0 = <&pwm4m0_pins>;
1568
+ clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
1569
+ clock-names = "pwm", "pclk";
1570
+ status = "disabled";
1571
+ };
1572
+
1573
+ pwm5: pwm@ff700010 {
1574
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1575
+ reg = <0x0 0xff700010 0x0 0x10>;
1576
+ #pwm-cells = <3>;
1577
+ pinctrl-names = "active";
1578
+ pinctrl-0 = <&pwm5m0_pins>;
1579
+ clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
1580
+ clock-names = "pwm", "pclk";
1581
+ status = "disabled";
1582
+ };
1583
+
1584
+ pwm6: pwm@ff700020 {
1585
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1586
+ reg = <0x0 0xff700020 0x0 0x10>;
1587
+ #pwm-cells = <3>;
1588
+ pinctrl-names = "active";
1589
+ pinctrl-0 = <&pwm6m0_pins>;
1590
+ clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
1591
+ clock-names = "pwm", "pclk";
1592
+ status = "disabled";
1593
+ };
1594
+
1595
+ pwm7: pwm@ff700030 {
1596
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1597
+ reg = <0x0 0xff700030 0x0 0x10>;
1598
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1599
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1600
+ #pwm-cells = <3>;
1601
+ pinctrl-names = "active";
1602
+ pinctrl-0 = <&pwm7m0_pins>;
1603
+ clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
1604
+ clock-names = "pwm", "pclk";
1605
+ status = "disabled";
1606
+ };
1607
+
1608
+ pwm8: pwm@ff710000 {
1609
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1610
+ reg = <0x0 0xff710000 0x0 0x10>;
1611
+ #pwm-cells = <3>;
1612
+ pinctrl-names = "active";
1613
+ pinctrl-0 = <&pwm8m0_pins>;
1614
+ clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
1615
+ clock-names = "pwm", "pclk";
1616
+ status = "disabled";
1617
+ };
1618
+
1619
+ pwm9: pwm@ff710010 {
1620
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1621
+ reg = <0x0 0xff710010 0x0 0x10>;
1622
+ #pwm-cells = <3>;
1623
+ pinctrl-names = "active";
1624
+ pinctrl-0 = <&pwm9m0_pins>;
1625
+ clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
1626
+ clock-names = "pwm", "pclk";
1627
+ status = "disabled";
1628
+ };
1629
+
1630
+ pwm10: pwm@ff710020 {
1631
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1632
+ reg = <0x0 0xff710020 0x0 0x10>;
1633
+ #pwm-cells = <3>;
1634
+ pinctrl-names = "active";
1635
+ pinctrl-0 = <&pwm10m0_pins>;
1636
+ clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
1637
+ clock-names = "pwm", "pclk";
1638
+ status = "disabled";
1639
+ };
1640
+
1641
+ pwm11: pwm@ff710030 {
1642
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1643
+ reg = <0x0 0xff710030 0x0 0x10>;
1644
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1645
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1646
+ #pwm-cells = <3>;
1647
+ pinctrl-names = "active";
1648
+ pinctrl-0 = <&pwm11m0_pins>;
1649
+ clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
1650
+ clock-names = "pwm", "pclk";
1651
+ status = "disabled";
1652
+ };
1653
+
1654
+ pwm12: pwm@ff720000 {
1655
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1656
+ reg = <0x0 0xff720000 0x0 0x10>;
1657
+ #pwm-cells = <3>;
1658
+ pinctrl-names = "active";
1659
+ pinctrl-0 = <&pwm12m0_pins>;
1660
+ clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
1661
+ clock-names = "pwm", "pclk";
1662
+ status = "disabled";
1663
+ };
1664
+
1665
+ pwm13: pwm@ff720010 {
1666
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1667
+ reg = <0x0 0xff720010 0x0 0x10>;
1668
+ #pwm-cells = <3>;
1669
+ pinctrl-names = "active";
1670
+ pinctrl-0 = <&pwm13m0_pins>;
1671
+ clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
1672
+ clock-names = "pwm", "pclk";
1673
+ status = "disabled";
1674
+ };
1675
+
1676
+ pwm14: pwm@ff720020 {
1677
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1678
+ reg = <0x0 0xff720020 0x0 0x10>;
1679
+ #pwm-cells = <3>;
1680
+ pinctrl-names = "active";
1681
+ pinctrl-0 = <&pwm14m0_pins>;
1682
+ clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
1683
+ clock-names = "pwm", "pclk";
1684
+ status = "disabled";
1685
+ };
1686
+
1687
+ pwm15: pwm@ff720030 {
1688
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
1689
+ reg = <0x0 0xff720030 0x0 0x10>;
1690
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1691
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1692
+ #pwm-cells = <3>;
1693
+ pinctrl-names = "active";
1694
+ pinctrl-0 = <&pwm15m0_pins>;
1695
+ clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
1696
+ clock-names = "pwm", "pclk";
1697
+ status = "disabled";
1698
+ };
1699
+
1700
+ saradc0: saradc@ff730000 {
1701
+ compatible = "rockchip,rk3562-saradc";
1702
+ reg = <0x0 0xff730000 0x0 0x100>;
1703
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1704
+ #io-channel-cells = <1>;
1705
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1706
+ clock-names = "saradc", "apb_pclk";
1707
+ resets = <&cru SRST_P_SARADC>;
1708
+ reset-names = "saradc-apb";
1709
+ status = "disabled";
1710
+ };
1711
+
1712
+ u2phy: usb2-phy@ff740000 {
1713
+ compatible = "rockchip,rk3562-usb2phy";
1714
+ reg = <0x0 0xff740000 0x0 0x10000>;
1715
+ clocks = <&cru CLK_USB2PHY_REF>, <&cru PCLK_USB2PHY>;
1716
+ clock-names = "phyclk", "pclk";
1717
+ #clock-cells = <0>;
1718
+ clock-output-names = "usb480m_phy";
1719
+ rockchip,usbgrf = <&usbphy_grf>;
1720
+ status = "disabled";
1721
+
1722
+ u2phy_otg: otg-port {
1723
+ #phy-cells = <0>;
1724
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1725
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1726
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1727
+ interrupt-names = "otg-bvalid", "otg-id", "linestate";
1728
+ status = "disabled";
1729
+ };
1730
+
1731
+ u2phy_host: host-port {
1732
+ #phy-cells = <0>;
1733
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1734
+ interrupt-names = "linestate";
1735
+ status = "disabled";
1736
+ };
1737
+ };
1738
+
1739
+ combphy_pu: phy@ff750000 {
1740
+ compatible = "rockchip,rk3562-naneng-combphy";
1741
+ reg = <0x0 0xff750000 0x0 0x100>;
1742
+ #phy-cells = <1>;
1743
+ clocks = <&cru CLK_PIPEPHY_REF>, <&cru PCLK_PIPEPHY>,
1744
+ <&cru PCLK_PHP>;
1745
+ clock-names = "refclk", "apbclk", "pipe_clk";
1746
+ assigned-clocks = <&cru CLK_PIPEPHY_REF>;
1747
+ assigned-clock-rates = <100000000>;
1748
+ resets = <&cru SRST_P_PIPEPHY>, <&cru SRST_PIPEPHY>;
1749
+ reset-names = "combphy-apb", "combphy";
1750
+ rockchip,pipe-grf = <&peri_grf>;
1751
+ rockchip,pipe-phy-grf = <&pipephy_grf>;
1752
+ status = "disabled";
1753
+ };
1754
+
1755
+ sai0: sai@ff800000 {
1756
+ compatible = "rockchip,rk3562-sai", "rockchip,sai-v1";
1757
+ reg = <0x0 0xff800000 0x0 0x1000>;
1758
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1759
+ clocks = <&cru MCLK_SAI0>, <&cru HCLK_SAI0>;
1760
+ clock-names = "mclk", "hclk";
1761
+ dmas = <&dmac 19>, <&dmac 18>;
1762
+ dma-names = "tx", "rx";
1763
+ resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>;
1764
+ reset-names = "m", "h";
1765
+ pinctrl-names = "default";
1766
+ pinctrl-0 = <&i2s0m0_lrck
1767
+ &i2s0m0_sclk
1768
+ &i2s0m0_sdi0
1769
+ &i2s0m0_sdo0
1770
+ &i2s0m0_sdo1
1771
+ &i2s0m0_sdo2
1772
+ &i2s0m0_sdo3>;
1773
+ #sound-dai-cells = <0>;
1774
+ status = "disabled";
1775
+ };
1776
+
1777
+ sai1: sai@ff810000 {
1778
+ compatible = "rockchip,rk3562-sai", "rockchip,sai-v1";
1779
+ reg = <0x0 0xff810000 0x0 0x1000>;
1780
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1781
+ clocks = <&cru MCLK_SAI1>, <&cru HCLK_SAI1>;
1782
+ clock-names = "mclk", "hclk";
1783
+ dmas = <&dmac 21>, <&dmac 20>;
1784
+ dma-names = "tx", "rx";
1785
+ resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>;
1786
+ reset-names = "m", "h";
1787
+ pinctrl-names = "default";
1788
+ pinctrl-0 = <&i2s1m0_lrck
1789
+ &i2s1m0_sclk
1790
+ &i2s1m0_sdi0
1791
+ &i2s1m0_sdi1
1792
+ &i2s1m0_sdi2
1793
+ &i2s1m0_sdi3
1794
+ &i2s1m0_sdo0
1795
+ &i2s1m0_sdo1
1796
+ &i2s1m0_sdo2
1797
+ &i2s1m0_sdo3>;
1798
+ #sound-dai-cells = <0>;
1799
+ status = "disabled";
1800
+ };
1801
+
1802
+ sai2: sai@ff820000 {
1803
+ compatible = "rockchip,rk3562-sai", "rockchip,sai-v1";
1804
+ reg = <0x0 0xff820000 0x0 0x1000>;
1805
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1806
+ clocks = <&cru MCLK_SAI2>, <&cru HCLK_SAI2>;
1807
+ clock-names = "mclk", "hclk";
1808
+ dmas = <&dmac 23>, <&dmac 22>;
1809
+ dma-names = "tx", "rx";
1810
+ resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>;
1811
+ reset-names = "m", "h";
1812
+ pinctrl-names = "default";
1813
+ pinctrl-0 = <&i2s2m0_lrck
1814
+ &i2s2m0_sclk
1815
+ &i2s2m0_sdi
1816
+ &i2s2m0_sdo>;
1817
+ #sound-dai-cells = <0>;
1818
+ status = "disabled";
1819
+ };
1820
+
1821
+ pdm: pdm@ff830000 {
1822
+ compatible = "rockchip,rk3562-pdm", "rockchip,pdm";
1823
+ reg = <0x0 0xff830000 0x0 0x1000>;
1824
+ clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
1825
+ clock-names = "pdm_clk", "pdm_hclk";
1826
+ dmas = <&dmac 31>;
1827
+ dma-names = "rx";
1828
+ pinctrl-names = "default";
1829
+ pinctrl-0 = <&pdmm0_clk0
1830
+ &pdmm0_clk1
1831
+ &pdmm0_sdi0
1832
+ &pdmm0_sdi1
1833
+ &pdmm0_sdi2
1834
+ &pdmm0_sdi3>;
1835
+ #sound-dai-cells = <0>;
1836
+ status = "disabled";
1837
+ };
1838
+
1839
+ spdif_8ch: spdif@ff840000 {
1840
+ compatible = "rockchip,rk3562-spdif", "rockchip,rk3568-spdif";
1841
+ reg = <0x0 0xff840000 0x0 0x1000>;
1842
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1843
+ dmas = <&dmac 30>;
1844
+ dma-names = "tx";
1845
+ clock-names = "mclk", "hclk";
1846
+ clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>;
1847
+ #sound-dai-cells = <0>;
1848
+ pinctrl-names = "default";
1849
+ pinctrl-0 = <&spdifm0_pins>;
1850
+ status = "disabled";
1851
+ };
1852
+
1853
+ acdcdig_dsm: codec-digital@ff850000 {
1854
+ compatible = "rockchip,rk3562-codec-digital", "rockchip,codec-digital-v1";
1855
+ reg = <0x0 0xff850000 0x0 0x1000>;
1856
+ clocks = <&cru CLK_DSM>, <&cru HCLK_DSM>;
1857
+ clock-names = "dac", "pclk";
1858
+ resets = <&cru SRST_DSM>;
1859
+ reset-names = "reset" ;
1860
+ rockchip,grf = <&sys_grf>;
1861
+ rockchip,pwm-output-mode;
1862
+ pinctrl-names = "default";
1863
+ pinctrl-0 = <&dsm_pins>;
1864
+ #sound-dai-cells = <0>;
1865
+ status = "disabled";
1866
+ };
1867
+
1868
+ sfc: spi@ff860000 {
1869
+ compatible = "rockchip,sfc";
1870
+ reg = <0x0 0xff860000 0x0 0x10000>;
1871
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
1872
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1873
+ clock-names = "clk_sfc", "hclk_sfc";
1874
+ assigned-clocks = <&cru SCLK_SFC>;
1875
+ assigned-clock-rates = <100000000>;
1876
+ #address-cells = <1>;
1877
+ #size-cells = <0>;
1878
+ status = "disabled";
1879
+ };
1880
+
1881
+ sdhci: mmc@ff870000 {
1882
+ compatible = "rockchip,rk3562-dwcmshc", "rockchip,rk3528-dwcmshc";
1883
+ reg = <0x0 0xff870000 0x0 0x10000>;
1884
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1885
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru CCLK_EMMC>;
1886
+ assigned-clock-rates = <200000000>, <200000000>;
1887
+ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1888
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1889
+ <&cru TMCLK_EMMC>;
1890
+ clock-names = "core", "bus", "axi", "block", "timer";
1891
+ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
1892
+ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
1893
+ <&cru SRST_T_EMMC>;
1894
+ reset-names = "core", "bus", "axi", "block", "timer";
1895
+ max-frequency = <200000000>;
1896
+ status = "disabled";
1897
+ };
1898
+
1899
+ sdmmc0: mmc@ff880000 {
1900
+ compatible = "rockchip,rk3562-dw-mshc",
1901
+ "rockchip,rk3288-dw-mshc";
1902
+ reg = <0x0 0xff880000 0x0 0x10000>;
1903
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1904
+ max-frequency = <150000000>;
1905
+ clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>,
1906
+ <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
1907
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1908
+ resets = <&cru SRST_H_SDMMC0>;
1909
+ reset-names = "reset";
1910
+ fifo-depth = <0x100>;
1911
+ status = "disabled";
1912
+ };
1913
+
1914
+ sdmmc1: mmc@ff890000 {
1915
+ compatible = "rockchip,rk3562-dw-mshc",
1916
+ "rockchip,rk3288-dw-mshc";
1917
+ reg = <0x0 0xff890000 0x0 0x10000>;
1918
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1919
+ max-frequency = <150000000>;
1920
+ clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>,
1921
+ <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
1922
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1923
+ resets = <&cru SRST_H_SDMMC1>;
1924
+ reset-names = "reset";
1925
+ fifo-depth = <0x100>;
1926
+ status = "disabled";
1927
+ };
1928
+
1929
+ crypto: crypto@ff8a0000 {
1930
+ compatible = "rockchip,crypto-v4";
1931
+ reg = <0x0 0xff8a0000 0x0 0x2000>;
1932
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1933
+ clocks = <&scmi_clk CLK_CORE_CRYPTO>, <&scmi_clk CLK_PKA_CRYPTO>,
1934
+ <&scmi_clk ACLK_CRYPTO>, <&scmi_clk HCLK_CRYPTO>,
1935
+ <&scmi_clk PCLK_CRYPTO>;
1936
+ clock-names = "sclk", "pka", "aclk", "pclk", "pclk";
1937
+ assigned-clocks = <&scmi_clk CLK_CORE_CRYPTO>, <&scmi_clk CLK_PKA_CRYPTO>;
1938
+ assigned-clock-rates = <200000000>, <300000000>;
1939
+ resets = <&cru SRST_CORE_CRYPTO>;
1940
+ reset-names = "crypto-rst";
1941
+ status = "disabled";
1942
+ };
1943
+
1944
+ rng: rng@ff8e0000 {
1945
+ compatible = "rockchip,rkrng";
1946
+ reg = <0x0 0xff8e0000 0x0 0x200>;
1947
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1948
+ clocks = <&scmi_clk HCLK_RK_RNG_NS>;
1949
+ clock-names = "hclk_trng";
1950
+ resets = <&cru SRST_H_RK_RNG_NS>;
1951
+ reset-names = "reset";
1952
+ status = "disabled";
1953
+ };
1954
+
1955
+ otp: otp@ff930000 {
1956
+ compatible = "rockchip,rk3562-otp";
1957
+ reg = <0x0 0xff930000 0x0 0x4000>;
1958
+ #address-cells = <1>;
1959
+ #size-cells = <1>;
1960
+ clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
1961
+ <&cru PCLK_OTPC_NS>, <&cru CLK_OTPC_ARB>,
1962
+ <&cru PCLK_OTPPHY>;
1963
+ clock-names = "usr", "sbpi", "apb", "arb", "phy";
1964
+ resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>,
1965
+ <&cru SRST_P_OTPC_NS>, <&cru SRST_OTPC_ARB>,
1966
+ <&cru SRST_P_OTPPHY>;
1967
+ reset-names = "usr", "sbpi", "apb", "arb", "phy";
1968
+
1969
+ /* Data cells */
1970
+ cpu_code: cpu-code@2 {
1971
+ reg = <0x02 0x2>;
1972
+ };
1973
+ otp_cpu_version: cpu-version@8 {
1974
+ reg = <0x08 0x1>;
1975
+ bits = <3 3>;
1976
+ };
1977
+ otp_id: id@a {
1978
+ reg = <0x0a 0x10>;
1979
+ };
1980
+ cpu_leakage: cpu-leakage@1a {
1981
+ reg = <0x1a 0x1>;
1982
+ };
1983
+ log_leakage: log-leakage@1b {
1984
+ reg = <0x1b 0x1>;
1985
+ };
1986
+ npu_leakage: npu-leakage@1c {
1987
+ reg = <0x1c 0x1>;
1988
+ };
1989
+ gpu_leakage: gpu-leakage@1d {
1990
+ reg = <0x1d 0x1>;
1991
+ };
1992
+ };
1993
+
1994
+ dmac: dma-controller@ff990000 {
1995
+ compatible = "arm,pl330", "arm,primecell";
1996
+ reg = <0x0 0xff990000 0x0 0x4000>;
1997
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1998
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1999
+ clocks = <&cru ACLK_DMAC>;
2000
+ clock-names = "apb_pclk";
2001
+ #dma-cells = <1>;
2002
+ arm,pl330-periph-burst;
2003
+ };
2004
+
2005
+ hwlock: hwspinlock@ff9e0000 {
2006
+ compatible = "rockchip,hwspinlock";
2007
+ reg = <0x0 0xff9e0000 0x0 0x100>;
2008
+ #hwlock-cells = <1>;
2009
+ status = "disabled";
2010
+ };
2011
+
2012
+ i2c1: i2c@ffa00000 {
2013
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
2014
+ reg = <0x0 0xffa00000 0x0 0x1000>;
2015
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
2016
+ clock-names = "i2c", "pclk";
2017
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2018
+ pinctrl-names = "default";
2019
+ pinctrl-0 = <&i2c1m0_xfer>;
2020
+ #address-cells = <1>;
2021
+ #size-cells = <0>;
2022
+ status = "disabled";
2023
+ };
2024
+
2025
+ i2c2: i2c@ffa10000 {
2026
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
2027
+ reg = <0x0 0xffa10000 0x0 0x1000>;
2028
+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
2029
+ clock-names = "i2c", "pclk";
2030
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
2031
+ pinctrl-names = "default";
2032
+ pinctrl-0 = <&i2c2m0_xfer>;
2033
+ #address-cells = <1>;
2034
+ #size-cells = <0>;
2035
+ status = "disabled";
2036
+ };
2037
+
2038
+ i2c3: i2c@ffa20000 {
2039
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
2040
+ reg = <0x0 0xffa20000 0x0 0x1000>;
2041
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
2042
+ clock-names = "i2c", "pclk";
2043
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2044
+ pinctrl-names = "default";
2045
+ pinctrl-0 = <&i2c3m0_xfer>;
2046
+ #address-cells = <1>;
2047
+ #size-cells = <0>;
2048
+ status = "disabled";
2049
+ };
2050
+
2051
+ i2c4: i2c@ffa30000 {
2052
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
2053
+ reg = <0x0 0xffa30000 0x0 0x1000>;
2054
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
2055
+ clock-names = "i2c", "pclk";
2056
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
2057
+ pinctrl-names = "default";
2058
+ pinctrl-0 = <&i2c4m0_xfer>;
2059
+ #address-cells = <1>;
2060
+ #size-cells = <0>;
2061
+ status = "disabled";
2062
+ };
2063
+
2064
+ i2c5: i2c@ffa40000 {
2065
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
2066
+ reg = <0x0 0xffa40000 0x0 0x1000>;
2067
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
2068
+ clock-names = "i2c", "pclk";
2069
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
2070
+ pinctrl-names = "default";
2071
+ pinctrl-0 = <&i2c5m0_xfer>;
2072
+ #address-cells = <1>;
2073
+ #size-cells = <0>;
2074
+ status = "disabled";
2075
+ };
2076
+
2077
+ wdt: watchdog@ffa60000 {
2078
+ compatible = "snps,dw-wdt";
2079
+ reg = <0x0 0xffa60000 0x0 0x100>;
2080
+ clocks = <&cru CLK_WDTNS>, <&cru PCLK_WDTNS>;
2081
+ clock-names = "tclk", "pclk";
2082
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2083
+ status = "disabled";
2084
+ };
2085
+
2086
+ tsadc: tsadc@ffa70000 {
2087
+ compatible = "rockchip,rk3562-tsadc";
2088
+ reg = <0x0 0xffa70000 0x0 0x400>;
2089
+ rockchip,grf = <&sys_grf>;
2090
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2091
+ clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>, <&cru PCLK_TSADC>;
2092
+ clock-names = "tsadc", "tsadc_tsen", "apb_pclk";
2093
+ assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
2094
+ assigned-clock-rates = <1200000>, <12000000>;
2095
+ resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, <&cru SRST_TSADCPHY>;
2096
+ reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
2097
+ #thermal-sensor-cells = <1>;
2098
+ rockchip,hw-tshut-temp = <120000>;
2099
+ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
2100
+ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2101
+ status = "disabled";
2102
+ };
2103
+
2104
+ gmac0: ethernet@ffa80000 {
2105
+ compatible = "rockchip,rk3562-gmac", "snps,dwmac-4.20a";
2106
+ reg = <0x0 0xffa80000 0x0 0x10000>;
2107
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
2108
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
2109
+ interrupt-names = "macirq", "eth_wake_irq";
2110
+ rockchip,grf = <&sys_grf>;
2111
+ rockchip,php_grf = <&ioc_grf>;
2112
+ clocks = <&cru CLK_GMAC_125M_CRU_I>, <&cru CLK_GMAC_50M_CRU_I>,
2113
+ <&cru PCLK_GMAC>, <&cru ACLK_GMAC>;
2114
+ clock-names = "stmmaceth", "clk_mac_ref",
2115
+ "pclk_mac", "aclk_mac";
2116
+ resets = <&cru SRST_A_GMAC>;
2117
+ reset-names = "stmmaceth";
2118
+
2119
+ snps,mixed-burst;
2120
+ snps,tso;
2121
+
2122
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
2123
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
2124
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
2125
+ status = "disabled";
2126
+
2127
+ mdio0: mdio {
2128
+ compatible = "snps,dwmac-mdio";
2129
+ #address-cells = <0x1>;
2130
+ #size-cells = <0x0>;
2131
+ };
2132
+
2133
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
2134
+ snps,wr_osr_lmt = <4>;
2135
+ snps,rd_osr_lmt = <8>;
2136
+ snps,blen = <0 0 0 0 16 8 4>;
2137
+ };
2138
+
2139
+ gmac0_mtl_rx_setup: rx-queues-config {
2140
+ snps,rx-queues-to-use = <1>;
2141
+ queue0 {};
2142
+ };
2143
+
2144
+ gmac0_mtl_tx_setup: tx-queues-config {
2145
+ snps,tx-queues-to-use = <1>;
2146
+ queue0 {};
2147
+ };
2148
+ };
2149
+
2150
+ saradc1: saradc@ffaa0000 {
2151
+ compatible = "rockchip,rk3562-saradc";
2152
+ reg = <0x0 0xffaa0000 0x0 0x100>;
2153
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
2154
+ #io-channel-cells = <1>;
2155
+ clocks = <&cru CLK_SARADC_VCCIO156>, <&cru PCLK_SARADC_VCCIO156>;
2156
+ clock-names = "saradc", "apb_pclk";
2157
+ resets = <&cru SRST_P_SARADC_VCCIO156>;
2158
+ reset-names = "saradc-apb";
2159
+ status = "disabled";
2160
+ };
2161
+
2162
+ mailbox: mailbox@ffae0000 {
2163
+ compatible = "rockchip,rk3562-mailbox",
2164
+ "rockchip,rk3368-mailbox";
2165
+ reg = <0x0 0xffae0000 0x0 0x200>;
2166
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2167
+ clocks = <&cru PCLK_MAILBOX>;
2168
+ clock-names = "pclk_mailbox";
2169
+ #mbox-cells = <1>;
2170
+ status = "disabled";
2171
+ };
2172
+
2173
+ dsi: dsi@ffb10000 {
2174
+ compatible = "rockchip,rk3562-mipi-dsi";
2175
+ reg = <0x0 0xffb10000 0x0 0x10000>;
2176
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
2177
+ clocks = <&cru PCLK_DSITX>;
2178
+ clock-names = "pclk";
2179
+ resets = <&cru SRST_P_DSITX>;
2180
+ reset-names = "apb";
2181
+ phys = <&video_phy>;
2182
+ phy-names = "dphy";
2183
+ rockchip,grf = <&sys_grf>;
2184
+ #address-cells = <1>;
2185
+ #size-cells = <0>;
2186
+ status = "disabled";
2187
+
2188
+ ports {
2189
+ #address-cells = <1>;
2190
+ #size-cells = <0>;
2191
+
2192
+ dsi_in: port@0 {
2193
+ reg = <0>;
2194
+ #address-cells = <1>;
2195
+ #size-cells = <0>;
2196
+
2197
+ dsi_in_vp0: endpoint@0 {
2198
+ reg = <0>;
2199
+ remote-endpoint = <&vp0_out_dsi>;
2200
+ status = "disabled";
2201
+ };
2202
+
2203
+ dsi_in_vp1: endpoint@1 {
2204
+ reg = <1>;
2205
+ remote-endpoint = <&vp1_out_dsi>;
2206
+ status = "disabled";
2207
+ };
2208
+ };
2209
+ };
2210
+ };
2211
+
2212
+ video_phy: phy@ffb20000 {
2213
+ compatible = "rockchip,rk3562-dsi-dphy", "rockchip,rk3562-video-phy",
2214
+ "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy";
2215
+ reg = <0x0 0xffb20000 0x0 0x10000>,
2216
+ <0x0 0xffb10000 0x0 0x10000>;
2217
+ reg-names = "phy", "host";
2218
+ clocks = <&cru CLK_MIPIDSIPHY_REF>,
2219
+ <&cru PCLK_DSIPHY>, <&cru PCLK_DSITX>;
2220
+ clock-names = "ref", "pclk", "pclk_host";
2221
+ #clock-cells = <0>;
2222
+ resets = <&cru SRST_P_DSIPHY>;
2223
+ reset-names = "apb";
2224
+ #phy-cells = <0>;
2225
+ status = "disabled";
2226
+ };
2227
+
2228
+ gmac1: ethernet@ffb30000 {
2229
+ compatible = "rockchip,rk3562-gmac";
2230
+ reg = <0x0 0xffb30000 0x0 0x10000>;
2231
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
2232
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
2233
+ interrupt-names = "macirq", "eth_wake_irq";
2234
+ rockchip,grf = <&sys_grf>;
2235
+ rockchip,php_grf = <&ioc_grf>;
2236
+ clocks = <&cru CLK_GMAC_50M_CRU_I>, <&cru CLK_GMAC_50M_CRU_I>,
2237
+ <&cru PCLK_GMAC>, <&cru ACLK_GMAC>;
2238
+ clock-names = "stmmaceth", "clk_mac_ref",
2239
+ "pclk_mac", "aclk_mac";
2240
+ resets = <&cru SRST_A_MAC100>;
2241
+ reset-names = "stmmaceth";
2242
+ status = "disabled";
2243
+
2244
+ mdio1: mdio {
2245
+ compatible = "snps,dwmac-mdio";
2246
+ #address-cells = <0x1>;
2247
+ #size-cells = <0x0>;
2248
+ };
2249
+ };
2250
+
2251
+ pinctrl: pinctrl {
2252
+ compatible = "rockchip,rk3562-pinctrl";
2253
+ rockchip,grf = <&ioc_grf>;
2254
+ #address-cells = <2>;
2255
+ #size-cells = <2>;
2256
+ ranges;
2257
+
2258
+ gpio0: gpio@ff260000 {
2259
+ compatible = "rockchip,gpio-bank";
2260
+ reg = <0x0 0xff260000 0x0 0x100>;
2261
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
2262
+ clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>;
2263
+
2264
+ gpio-controller;
2265
+ #gpio-cells = <2>;
2266
+ gpio-ranges = <&pinctrl 0 0 32>;
2267
+ interrupt-controller;
2268
+ #interrupt-cells = <2>;
2269
+ };
2270
+
2271
+ gpio1: gpio@ff620000 {
2272
+ compatible = "rockchip,gpio-bank";
2273
+ reg = <0x0 0xff620000 0x0 0x100>;
2274
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
2275
+ clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>;
2276
+
2277
+ gpio-controller;
2278
+ #gpio-cells = <2>;
2279
+ gpio-ranges = <&pinctrl 0 32 32>;
2280
+ interrupt-controller;
2281
+ #interrupt-cells = <2>;
2282
+ };
2283
+
2284
+ gpio2: gpio@ff630000 {
2285
+ compatible = "rockchip,gpio-bank";
2286
+ reg = <0x0 0xff630000 0x0 0x100>;
2287
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
2288
+ clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>;
2289
+
2290
+ gpio-controller;
2291
+ #gpio-cells = <2>;
2292
+ gpio-ranges = <&pinctrl 0 64 32>;
2293
+ interrupt-controller;
2294
+ #interrupt-cells = <2>;
2295
+ };
2296
+
2297
+ gpio3: gpio@ffac0000 {
2298
+ compatible = "rockchip,gpio-bank";
2299
+ reg = <0x0 0xffac0000 0x0 0x100>;
2300
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
2301
+ clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>;
2302
+
2303
+ gpio-controller;
2304
+ #gpio-cells = <2>;
2305
+ gpio-ranges = <&pinctrl 0 96 32>;
2306
+ interrupt-controller;
2307
+ #interrupt-cells = <2>;
2308
+ };
2309
+
2310
+ gpio4: gpio@ffad0000 {
2311
+ compatible = "rockchip,gpio-bank";
2312
+ reg = <0x0 0xffad0000 0x0 0x100>;
2313
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
2314
+ clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>;
2315
+
2316
+ gpio-controller;
2317
+ #gpio-cells = <2>;
2318
+ gpio-ranges = <&pinctrl 0 128 32>;
2319
+ interrupt-controller;
2320
+ #interrupt-cells = <2>;
2321
+ };
2322
+ };
2323
+};
2324
+
2325
+#include "rk3562-pinctrl.dtsi"
u-boot/arch/arm/dts/rk3568-u-boot.dtsi
....@@ -17,6 +17,15 @@
1717 stdout-path = &uart2;
1818 u-boot,spl-boot-order = &sdmmc0, &sdhci, &nandc0, &spi_nand, &spi_nor;
1919 };
20
+
21
+ secure-otp@fe3a0000 {
22
+ compatible = "rockchip,rk3568-secure-otp";
23
+ reg = <0x0 0xfe3a0000 0x0 0x4000>;
24
+ secure_conf = <0xfdd18008>;
25
+ mask_addr = <0xfe880000>;
26
+ cru_rst_addr = <0xfdd20470>;
27
+ u-boot,dm-spl;
28
+ };
2029 };
2130
2231 &psci {
....@@ -25,7 +34,7 @@
2534 };
2635
2736 &crypto {
28
- u-boot,dm-pre-reloc;
37
+ u-boot,dm-spl;
2938 };
3039
3140 &uart2 {
....@@ -37,12 +46,12 @@
3746 };
3847
3948 &grf {
40
- u-boot,dm-pre-reloc;
49
+ u-boot,dm-spl;
4150 status = "okay";
4251 };
4352
4453 &pmugrf {
45
- u-boot,dm-pre-reloc;
54
+ u-boot,dm-spl;
4655 status = "okay";
4756 };
4857
....@@ -87,12 +96,12 @@
8796 };
8897
8998 &cru {
90
- u-boot,dm-pre-reloc;
99
+ u-boot,dm-spl;
91100 status = "okay";
92101 };
93102
94103 &pmucru {
95
- u-boot,dm-pre-reloc;
104
+ u-boot,dm-spl;
96105 status = "okay";
97106 };
98107
....@@ -132,7 +141,7 @@
132141 };
133142
134143 &saradc {
135
- u-boot,dm-spl;
144
+ u-boot,dm-pre-reloc;
136145 status = "okay";
137146 };
138147
....@@ -194,7 +203,7 @@
194203 };
195204 };
196205
197
-&gmac0_clkin{
206
+&gmac0_clkin {
198207 u-boot,dm-pre-reloc;
199208 };
200209
....@@ -391,15 +400,15 @@
391400 };
392401
393402 &gpio2 {
394
- u-boot,dm-pre-reloc;
403
+ u-boot,dm-spl;
395404 };
396405
397406 &pcfg_pull_none_drv_level_1 {
398
- u-boot,dm-pre-reloc;
407
+ u-boot,dm-spl;
399408 };
400409
401410 &pcfg_pull_none_drv_level_2 {
402
- u-boot,dm-pre-reloc;
411
+ u-boot,dm-spl;
403412 };
404413
405414
....@@ -416,10 +425,6 @@
416425 };
417426
418427 &pcfg_pull_none {
419
- u-boot,dm-pre-reloc;
420
-};
421
-
422
-&secure_otp {
423428 u-boot,dm-spl;
424429 };
425430
u-boot/arch/arm/dts/rk3568.dtsi
....@@ -1892,14 +1892,6 @@
18921892 status = "disabled";
18931893 };
18941894
1895
- secure_otp: secure_otp@fe3a0000 {
1896
- compatible = "rockchip,rk3568-secure-otp";
1897
- reg = <0x0 0xfe3a0000 0x0 0x4000>;
1898
- secure_conf = <0xfdd18008>;
1899
- mask_addr = <0xfe880000>;
1900
- cru_rst_addr = <0xfdd20470>;
1901
- };
1902
-
19031895 i2s0_8ch: i2s@fe400000 {
19041896 compatible = "rockchip,rk3568-i2s-tdm";
19051897 reg = <0x0 0xfe400000 0x0 0x1000>;
u-boot/arch/arm/dts/rk3588-u-boot.dtsi
....@@ -173,7 +173,8 @@
173173 &sdhci {
174174 bus-width = <8>;
175175 u-boot,dm-spl;
176
- mmc-hs200-1_8v;
176
+ mmc-hs400-1_8v;
177
+ mmc-hs400-enhanced-strobe;
177178 non-removable;
178179 status = "okay";
179180 };
u-boot/arch/arm/dts/rk3588.dtsi
....@@ -34,6 +34,8 @@
3434 resets = <&cru SRST_A_USB3OTG1>;
3535 reset-names = "usb3-otg";
3636 dr_mode = "host";
37
+ phys = <&u2phy1_otg>;
38
+ phy-names = "usb2-phy";
3739 phy_type = "utmi_wide";
3840 snps,dis_enblslpm_quirk;
3941 snps,dis-u2-freeclk-exists-quirk;
....@@ -69,6 +71,8 @@
6971 compatible = "rockchip,rk3588-usb2phy";
7072 reg = <0x4000 0x10>;
7173 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
74
+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
75
+ reset-names = "phy", "apb";
7276 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
7377 clock-names = "phyclk";
7478 #clock-cells = <0>;
u-boot/arch/arm/dts/rk3588s.dtsi
....@@ -44,6 +44,11 @@
4444 spi3 = &spi3;
4545 spi4 = &spi4;
4646 spi5 = &sfc;
47
+ gpio0 = &gpio0;
48
+ gpio1 = &gpio1;
49
+ gpio2 = &gpio2;
50
+ gpio3 = &gpio3;
51
+ gpio4 = &gpio4;
4752 };
4853
4954 cpus {
....@@ -253,6 +258,8 @@
253258 resets = <&cru SRST_A_USB3OTG0>;
254259 reset-names = "usb3-otg";
255260 dr_mode = "otg";
261
+ phys = <&u2phy0_otg>;
262
+ phy-names = "usb2-phy";
256263 phy_type = "utmi_wide";
257264 snps,dis_enblslpm_quirk;
258265 snps,dis-u1-entry-quirk;
....@@ -270,6 +277,8 @@
270277 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
271278 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
272279 clock-names = "usbhost", "arbiter";
280
+ phys = <&u2phy2_host>;
281
+ phy-names = "usb2-phy";
273282 power-domains = <&power RK3588_PD_USB>;
274283 status = "disabled";
275284 };
....@@ -280,6 +289,8 @@
280289 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
281290 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
282291 clock-names = "usbhost", "arbiter";
292
+ phys = <&u2phy2_host>;
293
+ phy-names = "usb2-phy";
283294 power-domains = <&power RK3588_PD_USB>;
284295 status = "disabled";
285296 };
....@@ -290,6 +301,8 @@
290301 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
291302 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
292303 clock-names = "usbhost", "arbiter";
304
+ phys = <&u2phy3_host>;
305
+ phy-names = "usb2-phy";
293306 power-domains = <&power RK3588_PD_USB>;
294307 status = "disabled";
295308 };
....@@ -300,6 +313,8 @@
300313 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
301314 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
302315 clock-names = "usbhost", "arbiter";
316
+ phys = <&u2phy3_host>;
317
+ phy-names = "usb2-phy";
303318 power-domains = <&power RK3588_PD_USB>;
304319 status = "disabled";
305320 };
....@@ -406,6 +421,8 @@
406421 compatible = "rockchip,rk3588-usb2phy";
407422 reg = <0x0 0x10>;
408423 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
424
+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
425
+ reset-names = "phy", "apb";
409426 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
410427 clock-names = "phyclk";
411428 #clock-cells = <0>;
....@@ -429,6 +446,8 @@
429446 compatible = "rockchip,rk3588-usb2phy";
430447 reg = <0x8000 0x10>;
431448 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
449
+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
450
+ reset-names = "phy", "apb";
432451 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
433452 clock-names = "phyclk";
434453 #clock-cells = <0>;
....@@ -452,6 +471,8 @@
452471 compatible = "rockchip,rk3588-usb2phy";
453472 reg = <0xc000 0x10>;
454473 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
474
+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
475
+ reset-names = "phy", "apb";
455476 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
456477 clock-names = "phyclk";
457478 #clock-cells = <0>;
u-boot/arch/arm/dts/rv1106-evb2.dts
....@@ -7,6 +7,7 @@
77
88 #include "rv1106.dtsi"
99 #include "rv1106-u-boot.dtsi"
10
+#include <dt-bindings/input/input.h>
1011
1112 / {
1213 model = "Rockchip RV1106 EVB2 Board";
....@@ -15,6 +16,22 @@
1516 chosen {
1617 stdout-path = &uart2;
1718 u-boot,spl-boot-order = &spi_nor, &emmc;
19
+ };
20
+
21
+ adc-keys {
22
+ compatible = "adc-keys";
23
+ io-channels = <&saradc 0>;
24
+ io-channel-names = "buttons";
25
+ keyup-threshold-microvolt = <1800000>;
26
+ u-boot,dm-spl;
27
+ status = "okay";
28
+
29
+ volumeup-key {
30
+ u-boot,dm-spl;
31
+ linux,code = <KEY_VOLUMEUP>;
32
+ label = "volume up";
33
+ press-threshold-microvolt = <17578>;
34
+ };
1835 };
1936 };
2037
....@@ -63,6 +80,11 @@
6380 status = "disabled";
6481 };
6582
83
+&saradc {
84
+ u-boot,dm-spl;
85
+ status = "okay";
86
+};
87
+
6688 &sdmmc {
6789 /delete-property/ u-boot,dm-spl;
6890 status = "disabled";
u-boot/arch/arm/dts/rv1106-u-boot.dtsi
....@@ -15,7 +15,7 @@
1515 u-boot,spl-boot-order = &sdmmc, &spi_nor, &spi_nand, &emmc;
1616 };
1717
18
- secure_otp: secure_otp@ff3fd8000 {
18
+ secure-otp@ff3fd8000 {
1919 compatible = "rockchip,rv1106-secure-otp";
2020 reg = <0xff3d8000 0x4000>;
2121 secure_conf = <0xff07a018>;
....@@ -112,8 +112,28 @@
112112 u-boot,dm-spl;
113113 };
114114
115
+&gpio0 {
116
+ u-boot,dm-pre-reloc;
117
+ status = "okay";
118
+};
119
+
120
+&gpio1 {
121
+ u-boot,dm-pre-reloc;
122
+ status = "okay";
123
+};
124
+
125
+&gpio2 {
126
+ u-boot,dm-pre-reloc;
127
+ status = "okay";
128
+};
129
+
115130 &gpio3 {
116131 u-boot,dm-spl;
132
+ status = "okay";
133
+};
134
+
135
+&gpio4 {
136
+ u-boot,dm-pre-reloc;
117137 status = "okay";
118138 };
119139
....@@ -159,3 +179,23 @@
159179 spi-max-frequency = <100000000>;
160180 };
161181 };
182
+
183
+&u2phy {
184
+ u-boot,dm-pre-reloc;
185
+ status = "okay";
186
+};
187
+
188
+&u2phy_otg {
189
+ u-boot,dm-pre-reloc;
190
+ status = "okay";
191
+};
192
+
193
+&usbdrd {
194
+ u-boot,dm-pre-reloc;
195
+ status = "okay";
196
+};
197
+
198
+&usbdrd_dwc3 {
199
+ u-boot,dm-pre-reloc;
200
+ status = "okay";
201
+};
u-boot/arch/arm/dts/rv1106.dtsi
....@@ -492,7 +492,7 @@
492492 };
493493
494494 saradc: saradc@ff3c0000 {
495
- compatible = "rockchip,rk3588-saradc";
495
+ compatible = "rockchip,rv1106-saradc";
496496 reg = <0xff3c0000 0x100>;
497497 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
498498 #io-channel-cells = <1>;
u-boot/arch/arm/dts/rv1126-u-boot.dtsi
....@@ -15,10 +15,12 @@
1515 u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc;
1616 };
1717
18
- secure_otp: secure_otp@0xff5d0000 {
18
+ secure-otp@ff5d0000 {
1919 compatible = "rockchip,rv1126-secure-otp";
2020 reg = <0xff5d0000 0x4000>;
2121 secure_conf = <0xfe0a0008>;
22
+ u-boot,dm-spl;
23
+ status = "okay";
2224 };
2325 };
2426
....@@ -147,11 +149,6 @@
147149 };
148150
149151 &hw_decompress {
150
- u-boot,dm-spl;
151
- status = "okay";
152
-};
153
-
154
-&secure_otp {
155152 u-boot,dm-spl;
156153 status = "okay";
157154 };
u-boot/arch/arm/include/asm/arch-rockchip/boot_mode.h
....@@ -23,6 +23,8 @@
2323 #define BOOT_UMS (REBOOT_FLAG + 12)
2424 /* enter dfu download mode */
2525 #define BOOT_DFU (REBOOT_FLAG + 13)
26
+/* reboot system quiescent */
27
+#define BOOT_QUIESCENT (REBOOT_FLAG + 14)
2628 /* enter bootrom download mode */
2729 #define BOOT_BROM_DOWNLOAD 0xEF08A53C
2830
u-boot/arch/arm/include/asm/arch-rockchip/clock.h
....@@ -12,6 +12,13 @@
1212 #define RKCLK_PLL_MODE_NORMAL 1
1313 #define RKCLK_PLL_MODE_DEEP 2
1414
15
+/*
16
+ * PLL flags
17
+ */
18
+#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
19
+/* normal mode only. now only for pll_rk3036, pll_rk3328 type */
20
+#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
21
+
1522 enum {
1623 ROCKCHIP_SYSCON_NOC,
1724 ROCKCHIP_SYSCON_GRF,
....@@ -29,6 +36,7 @@
2936 ROCKCHIP_SYSCON_PIPE_PHY2_GRF,
3037 ROCKCHIP_SYSCON_VOP_GRF,
3138 ROCKCHIP_SYSCON_VO_GRF,
39
+ ROCKCHIP_SYSCON_IOC,
3240 };
3341
3442 /* Standard Rockchip clock numbers */
u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3528.h
....@@ -0,0 +1,396 @@
1
+/* SPDX-License-Identifier: GPL-2.0 */
2
+/*
3
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
4
+ * Author: Joseph Chen <chenjh@rock-chips.com>
5
+ */
6
+
7
+#ifndef _ASM_ARCH_CRU_RK3528_H
8
+#define _ASM_ARCH_CRU_RK3528_H
9
+
10
+#define MHz 1000000
11
+#define KHz 1000
12
+#define OSC_HZ (24 * MHz)
13
+
14
+#define CPU_PVTPLL_HZ (1200 * MHz)
15
+#define APLL_HZ (600 * MHz)
16
+#define GPLL_HZ (1188 * MHz)
17
+#define CPLL_HZ (996 * MHz)
18
+#define PPLL_HZ (1000 * MHz)
19
+
20
+/* RK3528 pll id */
21
+enum rk3528_pll_id {
22
+ APLL,
23
+ CPLL,
24
+ GPLL,
25
+ PPLL,
26
+ DPLL,
27
+ PLL_COUNT,
28
+};
29
+
30
+struct rk3528_clk_info {
31
+ unsigned long id;
32
+ char *name;
33
+};
34
+
35
+struct rk3528_clk_priv {
36
+ struct rk3528_cru *cru;
37
+ struct rk3528_sysgrf *grf;
38
+ ulong ppll_hz;
39
+ ulong gpll_hz;
40
+ ulong cpll_hz;
41
+ ulong armclk_hz;
42
+ ulong armclk_enter_hz;
43
+ ulong armclk_init_hz;
44
+ bool sync_kernel;
45
+ bool set_armclk_rate;
46
+};
47
+
48
+struct rk3528_pll {
49
+ unsigned int con0;
50
+ unsigned int con1;
51
+ unsigned int con2;
52
+ unsigned int con3;
53
+ unsigned int con4;
54
+ unsigned int reserved0[3];
55
+};
56
+
57
+struct rk3528_cru {
58
+ uint32_t apll_con[5];
59
+ uint32_t reserved0014[3];
60
+ uint32_t cpll_con[5];
61
+ uint32_t reserved0034[11];
62
+ uint32_t gpll_con[5];
63
+ uint32_t reserved0074[51+32];
64
+ uint32_t reserved01c0[48];
65
+ uint32_t mode_con[1];
66
+ uint32_t reserved0284[31];
67
+ uint32_t clksel_con[91];
68
+ uint32_t reserved046c[229];
69
+ uint32_t gate_con[46];
70
+ uint32_t reserved08b8[82];
71
+ uint32_t softrst_con[47];
72
+ uint32_t reserved0abc[81];
73
+ uint32_t glb_cnt_th;
74
+ uint32_t glb_rst_st;
75
+ uint32_t glb_srst_fst;
76
+ uint32_t glb_srst_snd;
77
+ uint32_t glb_rst_con;
78
+ uint32_t reserved0c14[6];
79
+ uint32_t corewfi_con;
80
+ uint32_t reserved0c30[15604];
81
+
82
+ /* pmucru */
83
+ uint32_t reserved10000[192];
84
+ uint32_t pmuclksel_con[3];
85
+ uint32_t reserved1030c[317];
86
+ uint32_t pmugate_con[3];
87
+ uint32_t reserved1080c[125];
88
+ uint32_t pmusoftrst_con[3];
89
+ uint32_t reserved10a08[7550+8191];
90
+
91
+ /* pciecru */
92
+ uint32_t reserved20000[32];
93
+ uint32_t ppll_con[5];
94
+ uint32_t reserved20094[155];
95
+ uint32_t pcieclksel_con[2];
96
+ uint32_t reserved20308[318];
97
+ uint32_t pciegate_con;
98
+};
99
+check_member(rk3528_cru, pciegate_con, 0x20800);
100
+
101
+struct rk3528_grf_clk_priv {
102
+ struct rk3528_grf *grf;
103
+};
104
+
105
+struct pll_rate_table {
106
+ unsigned long rate;
107
+ unsigned int fbdiv;
108
+ unsigned int postdiv1;
109
+ unsigned int refdiv;
110
+ unsigned int postdiv2;
111
+ unsigned int dsmpd;
112
+ unsigned int frac;
113
+};
114
+
115
+#define RK3528_PMU_CRU_BASE 0x10000
116
+#define RK3528_PCIE_CRU_BASE 0x20000
117
+#define RK3528_DDRPHY_CRU_BASE 0x28000
118
+#define RK3528_PLL_CON(x) ((x) * 0x4)
119
+#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
120
+#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
121
+#define RK3528_MODE_CON 0x280
122
+#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
123
+#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
124
+#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
125
+#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
126
+
127
+#define RK3528_DIV_ACLK_M_CORE_MASK 0x1f
128
+#define RK3528_DIV_ACLK_M_CORE_SHIFT 11
129
+#define RK3528_DIV_PCLK_DBG_MASK 0x1f
130
+#define RK3528_DIV_PCLK_DBG_SHIFT 1
131
+
132
+enum {
133
+ /* CRU_CLKSEL_CON00 */
134
+ CLK_MATRIX_50M_SRC_DIV_SHIFT = 2,
135
+ CLK_MATRIX_50M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_50M_SRC_DIV_SHIFT,
136
+ CLK_MATRIX_100M_SRC_DIV_SHIFT = 7,
137
+ CLK_MATRIX_100M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_100M_SRC_DIV_SHIFT,
138
+
139
+ /* CRU_CLKSEL_CON01 */
140
+ CLK_MATRIX_150M_SRC_DIV_SHIFT = 0,
141
+ CLK_MATRIX_150M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_150M_SRC_DIV_SHIFT,
142
+ CLK_MATRIX_200M_SRC_DIV_SHIFT = 5,
143
+ CLK_MATRIX_200M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_200M_SRC_DIV_SHIFT,
144
+ CLK_MATRIX_250M_SRC_DIV_SHIFT = 10,
145
+ CLK_MATRIX_250M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_250M_SRC_DIV_SHIFT,
146
+ CLK_MATRIX_250M_SRC_SEL_SHIFT = 15,
147
+ CLK_MATRIX_250M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_250M_SRC_SEL_SHIFT,
148
+
149
+ /* CRU_CLKSEL_CON02 */
150
+ CLK_MATRIX_300M_SRC_DIV_SHIFT = 0,
151
+ CLK_MATRIX_300M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_300M_SRC_DIV_SHIFT,
152
+ CLK_MATRIX_339M_SRC_DIV_SHIFT = 5,
153
+ CLK_MATRIX_339M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_339M_SRC_DIV_SHIFT,
154
+ CLK_MATRIX_400M_SRC_DIV_SHIFT = 10,
155
+ CLK_MATRIX_400M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_400M_SRC_DIV_SHIFT,
156
+
157
+ /* CRU_CLKSEL_CON03 */
158
+ CLK_MATRIX_500M_SRC_DIV_SHIFT = 6,
159
+ CLK_MATRIX_500M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_500M_SRC_DIV_SHIFT,
160
+ CLK_MATRIX_500M_SRC_SEL_SHIFT = 11,
161
+ CLK_MATRIX_500M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_500M_SRC_SEL_SHIFT,
162
+
163
+ /* CRU_CLKSEL_CON04 */
164
+ CLK_MATRIX_600M_SRC_DIV_SHIFT = 0,
165
+ CLK_MATRIX_600M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_600M_SRC_DIV_SHIFT,
166
+ CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX = 0U,
167
+ CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX = 1U,
168
+ CLK_MATRIX_500M_SRC_SEL_CLK_GPLL_MUX = 0U,
169
+ CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX = 1U,
170
+
171
+ /* PMUCRU_CLKSEL_CON00 */
172
+ CLK_I2C2_SEL_SHIFT = 0,
173
+ CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT,
174
+
175
+ /* PCIE_CRU_CLKSEL_CON01 */
176
+ PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT = 7,
177
+ PCIE_CLK_MATRIX_50M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT,
178
+ PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT = 11,
179
+ PCIE_CLK_MATRIX_100M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT,
180
+
181
+ /* CRU_CLKSEL_CON32 */
182
+ DCLK_VOP_SRC0_SEL_SHIFT = 10,
183
+ DCLK_VOP_SRC0_SEL_MASK = 0x1 << DCLK_VOP_SRC0_SEL_SHIFT,
184
+ DCLK_VOP_SRC0_DIV_SHIFT = 2,
185
+ DCLK_VOP_SRC0_DIV_MASK = 0xFF << DCLK_VOP_SRC0_DIV_SHIFT,
186
+
187
+ /* CRU_CLKSEL_CON33 */
188
+ DCLK_VOP_SRC1_SEL_SHIFT = 8,
189
+ DCLK_VOP_SRC1_SEL_MASK = 0x1 << DCLK_VOP_SRC1_SEL_SHIFT,
190
+ DCLK_VOP_SRC1_DIV_SHIFT = 0,
191
+ DCLK_VOP_SRC1_DIV_MASK = 0xFF << DCLK_VOP_SRC1_DIV_SHIFT,
192
+
193
+ /* CRU_CLKSEL_CON43 */
194
+ CLK_CORE_CRYPTO_SEL_SHIFT = 14,
195
+ CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT,
196
+ ACLK_BUS_VOPGL_ROOT_DIV_SHIFT = 0U,
197
+ ACLK_BUS_VOPGL_ROOT_DIV_MASK = 0x7U << ACLK_BUS_VOPGL_ROOT_DIV_SHIFT,
198
+
199
+ /* CRU_CLKSEL_CON44 */
200
+ CLK_PWM0_SEL_SHIFT = 6,
201
+ CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT,
202
+ CLK_PWM1_SEL_SHIFT = 8,
203
+ CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
204
+ CLK_PWM0_SEL_CLK_MATRIX_100M_SRC = 0U,
205
+ CLK_PWM0_SEL_CLK_MATRIX_50M_SRC = 1U,
206
+ CLK_PWM0_SEL_XIN_OSC0_FUNC = 2U,
207
+ CLK_PWM1_SEL_CLK_MATRIX_100M_SRC = 0U,
208
+ CLK_PWM1_SEL_CLK_MATRIX_50M_SRC = 1U,
209
+ CLK_PWM1_SEL_XIN_OSC0_FUNC = 2U,
210
+ CLK_PKA_CRYPTO_SEL_SHIFT = 0,
211
+ CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT,
212
+ CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U,
213
+ CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U,
214
+ CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U,
215
+ CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC = 3U,
216
+ CLK_PKA_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U,
217
+ CLK_PKA_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U,
218
+ CLK_PKA_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U,
219
+ CLK_PKA_CRYPTO_SEL_XIN_OSC0_FUNC = 3U,
220
+
221
+ /* CRU_CLKSEL_CON60 */
222
+ CLK_MATRIX_25M_SRC_DIV_SHIFT = 2,
223
+ CLK_MATRIX_25M_SRC_DIV_MASK = 0xff << CLK_MATRIX_25M_SRC_DIV_SHIFT,
224
+ CLK_MATRIX_125M_SRC_DIV_SHIFT = 10,
225
+ CLK_MATRIX_125M_SRC_DIV_MASK = 0x1f << CLK_MATRIX_125M_SRC_DIV_SHIFT,
226
+
227
+ /* CRU_CLKSEL_CON61 */
228
+ SCLK_SFC_DIV_SHIFT = 6,
229
+ SCLK_SFC_DIV_MASK = 0x3F << SCLK_SFC_DIV_SHIFT,
230
+ SCLK_SFC_SEL_SHIFT = 12,
231
+ SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT,
232
+ SCLK_SFC_SEL_CLK_GPLL_MUX = 0U,
233
+ SCLK_SFC_SEL_CLK_CPLL_MUX = 1U,
234
+ SCLK_SFC_SEL_XIN_OSC0_FUNC = 2U,
235
+
236
+ /* CRU_CLKSEL_CON62 */
237
+ CCLK_SRC_EMMC_DIV_SHIFT = 0,
238
+ CCLK_SRC_EMMC_DIV_MASK = 0x3F << CCLK_SRC_EMMC_DIV_SHIFT,
239
+ CCLK_SRC_EMMC_SEL_SHIFT = 6,
240
+ CCLK_SRC_EMMC_SEL_MASK = 0x3 << CCLK_SRC_EMMC_SEL_SHIFT,
241
+ BCLK_EMMC_SEL_SHIFT = 8,
242
+ BCLK_EMMC_SEL_MASK = 0x3 << BCLK_EMMC_SEL_SHIFT,
243
+
244
+ /* CRU_CLKSEL_CON63 */
245
+ CLK_I2C3_SEL_SHIFT = 12,
246
+ CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT,
247
+ CLK_I2C5_SEL_SHIFT = 14,
248
+ CLK_I2C5_SEL_MASK = 0x3 << CLK_I2C5_SEL_SHIFT,
249
+ CLK_SPI1_SEL_SHIFT = 10,
250
+ CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT,
251
+
252
+ /* CRU_CLKSEL_CON64 */
253
+ CLK_I2C6_SEL_SHIFT = 0,
254
+ CLK_I2C6_SEL_MASK = 0x3 << CLK_I2C6_SEL_SHIFT,
255
+
256
+ /* CRU_CLKSEL_CON74 */
257
+ CLK_SARADC_DIV_SHIFT = 0,
258
+ CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT,
259
+ CLK_TSADC_DIV_SHIFT = 3,
260
+ CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT,
261
+ CLK_TSADC_TSEN_DIV_SHIFT = 8,
262
+ CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT,
263
+
264
+ /* CRU_CLKSEL_CON79 */
265
+ CLK_I2C1_SEL_SHIFT = 9,
266
+ CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT,
267
+ CLK_I2C0_SEL_SHIFT = 11,
268
+ CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT,
269
+ CLK_SPI0_SEL_SHIFT = 13,
270
+ CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT,
271
+
272
+ /* CRU_CLKSEL_CON83 */
273
+ ACLK_VOP_ROOT_DIV_SHIFT = 12,
274
+ ACLK_VOP_ROOT_DIV_MASK = 0x7 << ACLK_VOP_ROOT_DIV_SHIFT,
275
+ ACLK_VOP_ROOT_SEL_SHIFT = 15,
276
+ ACLK_VOP_ROOT_SEL_MASK = 0x1 << ACLK_VOP_ROOT_SEL_SHIFT,
277
+
278
+ /* CRU_CLKSEL_CON84 */
279
+ DCLK_VOP0_SEL_SHIFT = 0,
280
+ DCLK_VOP0_SEL_MASK = 0x1 << DCLK_VOP0_SEL_SHIFT,
281
+ DCLK_VOP_SRC_SEL_CLK_GPLL_MUX = 0U,
282
+ DCLK_VOP_SRC_SEL_CLK_CPLL_MUX = 1U,
283
+ ACLK_VOP_ROOT_SEL_CLK_GPLL_MUX = 0U,
284
+ ACLK_VOP_ROOT_SEL_CLK_CPLL_MUX = 1U,
285
+ DCLK_VOP0_SEL_DCLK_VOP_SRC0 = 0U,
286
+ DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL_IO = 1U,
287
+
288
+ /* CRU_CLKSEL_CON85 */
289
+ CLK_I2C4_SEL_SHIFT = 13,
290
+ CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT,
291
+ CLK_I2C7_SEL_SHIFT = 0,
292
+ CLK_I2C7_SEL_MASK = 0x3 << CLK_I2C7_SEL_SHIFT,
293
+ CLK_I2C3_SEL_CLK_MATRIX_200M_SRC = 0U,
294
+ CLK_I2C3_SEL_CLK_MATRIX_100M_SRC = 1U,
295
+ CLK_I2C3_SEL_CLK_MATRIX_50M_SRC = 2U,
296
+ CLK_I2C3_SEL_XIN_OSC0_FUNC = 3U,
297
+ CLK_SPI1_SEL_CLK_MATRIX_200M_SRC = 0U,
298
+ CLK_SPI1_SEL_CLK_MATRIX_100M_SRC = 1U,
299
+ CLK_SPI1_SEL_CLK_MATRIX_50M_SRC = 2U,
300
+ CLK_SPI1_SEL_XIN_OSC0_FUNC = 3U,
301
+ CCLK_SRC_SDMMC0_DIV_SHIFT = 0,
302
+ CCLK_SRC_SDMMC0_DIV_MASK = 0x3F << CCLK_SRC_SDMMC0_DIV_SHIFT,
303
+ CCLK_SRC_SDMMC0_SEL_SHIFT = 6,
304
+ CCLK_SRC_SDMMC0_SEL_MASK = 0x3 << CCLK_SRC_SDMMC0_SEL_SHIFT,
305
+ CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX = 0U,
306
+ CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX = 1U,
307
+ CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC = 2U,
308
+ BCLK_EMMC_SEL_CLK_MATRIX_200M_SRC = 0U,
309
+ BCLK_EMMC_SEL_CLK_MATRIX_100M_SRC = 1U,
310
+ BCLK_EMMC_SEL_CLK_MATRIX_50M_SRC = 2U,
311
+ BCLK_EMMC_SEL_XIN_OSC0_FUNC = 3U,
312
+ CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX = 0U,
313
+ CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX = 1U,
314
+ CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC = 2U,
315
+
316
+ /* CRU_CLKSEL_CON04 */
317
+ CLK_UART0_SRC_DIV_SHIFT = 5,
318
+ CLK_UART0_SRC_DIV_MASK = 0x1F << CLK_UART0_SRC_DIV_SHIFT,
319
+ /* CRU_CLKSEL_CON05 */
320
+ CLK_UART0_FRAC_DIV_SHIFT = 0,
321
+ CLK_UART0_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART0_FRAC_DIV_SHIFT,
322
+ /* CRU_CLKSEL_CON06 */
323
+ SCLK_UART0_SRC_SEL_SHIFT = 0,
324
+ SCLK_UART0_SRC_SEL_MASK = 0x3 << SCLK_UART0_SRC_SEL_SHIFT,
325
+ CLK_UART1_SRC_DIV_SHIFT = 2,
326
+ CLK_UART1_SRC_DIV_MASK = 0x1F << CLK_UART1_SRC_DIV_SHIFT,
327
+ /* CRU_CLKSEL_CON07 */
328
+ CLK_UART1_FRAC_DIV_SHIFT = 0,
329
+ CLK_UART1_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART1_FRAC_DIV_SHIFT,
330
+ /* CRU_CLKSEL_CON08 */
331
+ SCLK_UART1_SRC_SEL_SHIFT = 0,
332
+ SCLK_UART1_SRC_SEL_MASK = 0x3 << SCLK_UART1_SRC_SEL_SHIFT,
333
+ CLK_UART2_SRC_DIV_SHIFT = 2,
334
+ CLK_UART2_SRC_DIV_MASK = 0x1F << CLK_UART2_SRC_DIV_SHIFT,
335
+ /* CRU_CLKSEL_CON09 */
336
+ CLK_UART2_FRAC_DIV_SHIFT = 0,
337
+ CLK_UART2_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART2_FRAC_DIV_SHIFT,
338
+ /* CRU_CLKSEL_CON10 */
339
+ SCLK_UART2_SRC_SEL_SHIFT = 0,
340
+ SCLK_UART2_SRC_SEL_MASK = 0x3 << SCLK_UART2_SRC_SEL_SHIFT,
341
+ CLK_UART3_SRC_DIV_SHIFT = 2,
342
+ CLK_UART3_SRC_DIV_MASK = 0x1F << CLK_UART3_SRC_DIV_SHIFT,
343
+ /* CRU_CLKSEL_CON11 */
344
+ CLK_UART3_FRAC_DIV_SHIFT = 0,
345
+ CLK_UART3_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART3_FRAC_DIV_SHIFT,
346
+ /* CRU_CLKSEL_CON12 */
347
+ SCLK_UART3_SRC_SEL_SHIFT = 0,
348
+ SCLK_UART3_SRC_SEL_MASK = 0x3 << SCLK_UART3_SRC_SEL_SHIFT,
349
+ CLK_UART4_SRC_DIV_SHIFT = 2,
350
+ CLK_UART4_SRC_DIV_MASK = 0x1F << CLK_UART4_SRC_DIV_SHIFT,
351
+ /* CRU_CLKSEL_CON13 */
352
+ CLK_UART4_FRAC_DIV_SHIFT = 0,
353
+ CLK_UART4_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART4_FRAC_DIV_SHIFT,
354
+ /* CRU_CLKSEL_CON14 */
355
+ SCLK_UART4_SRC_SEL_SHIFT = 0,
356
+ SCLK_UART4_SRC_SEL_MASK = 0x3 << SCLK_UART4_SRC_SEL_SHIFT,
357
+ CLK_UART5_SRC_DIV_SHIFT = 2,
358
+ CLK_UART5_SRC_DIV_MASK = 0x1F << CLK_UART5_SRC_DIV_SHIFT,
359
+ /* CRU_CLKSEL_CON15 */
360
+ CLK_UART5_FRAC_DIV_SHIFT = 0,
361
+ CLK_UART5_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART5_FRAC_DIV_SHIFT,
362
+ /* CRU_CLKSEL_CON16 */
363
+ SCLK_UART5_SRC_SEL_SHIFT = 0,
364
+ SCLK_UART5_SRC_SEL_MASK = 0x3 << SCLK_UART5_SRC_SEL_SHIFT,
365
+ CLK_UART6_SRC_DIV_SHIFT = 2,
366
+ CLK_UART6_SRC_DIV_MASK = 0x1F << CLK_UART6_SRC_DIV_SHIFT,
367
+ /* CRU_CLKSEL_CON17 */
368
+ CLK_UART6_FRAC_DIV_SHIFT = 0,
369
+ CLK_UART6_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART6_FRAC_DIV_SHIFT,
370
+ /* CRU_CLKSEL_CON18 */
371
+ SCLK_UART6_SRC_SEL_SHIFT = 0,
372
+ SCLK_UART6_SRC_SEL_MASK = 0x3 << SCLK_UART6_SRC_SEL_SHIFT,
373
+ CLK_UART7_SRC_DIV_SHIFT = 2,
374
+ CLK_UART7_SRC_DIV_MASK = 0x1F << CLK_UART7_SRC_DIV_SHIFT,
375
+ /* CRU_CLKSEL_CON19 */
376
+ CLK_UART7_FRAC_DIV_SHIFT = 0,
377
+ CLK_UART7_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART7_FRAC_DIV_SHIFT,
378
+ /* CRU_CLKSEL_CON20 */
379
+ SCLK_UART7_SRC_SEL_SHIFT = 0,
380
+ SCLK_UART7_SRC_SEL_MASK = 0x3 << SCLK_UART7_SRC_SEL_SHIFT,
381
+ SCLK_UART0_SRC_SEL_CLK_UART0_SRC = 0U,
382
+ SCLK_UART0_SRC_SEL_CLK_UART0_FRAC = 1U,
383
+ SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC = 2U,
384
+
385
+ /* CRU_CLKSEL_CON60 */
386
+ CLK_GMAC1_VPU_25M_DIV_SHIFT = 2,
387
+ CLK_GMAC1_VPU_25M_DIV_MASK = 0xFF << CLK_GMAC1_VPU_25M_DIV_SHIFT,
388
+ /* CRU_CLKSEL_CON66 */
389
+ CLK_GMAC1_SRC_VPU_DIV_SHIFT = 0,
390
+ CLK_GMAC1_SRC_VPU_DIV_MASK = 0x3F << CLK_GMAC1_SRC_VPU_DIV_SHIFT,
391
+ /* CRU_CLKSEL_CON84 */
392
+ CLK_GMAC0_SRC_DIV_SHIFT = 3,
393
+ CLK_GMAC0_SRC_DIV_MASK = 0x3F << CLK_GMAC0_SRC_DIV_SHIFT,
394
+};
395
+
396
+#endif
u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3562.h
....@@ -0,0 +1,416 @@
1
+/* SPDX-License-Identifier: GPL-2.0 */
2
+/*
3
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
4
+ * Author:
5
+ * Elaine Zhang <zhangqing@rock-chips.com>
6
+ * Finley Xiao <finley.xiao@rock-chips.com>
7
+ */
8
+
9
+#ifndef _ASM_ARCH_CRU_RK3562_H
10
+#define _ASM_ARCH_CRU_RK3562_H
11
+
12
+#define MHz 1000000
13
+#define KHz 1000
14
+#define OSC_HZ (24 * MHz)
15
+
16
+#define CPU_PVTPLL_HZ (1008 * MHz)
17
+#define APLL_HZ (600 * MHz)
18
+#define GPLL_HZ (1188 * MHz)
19
+#define CPLL_HZ (1000 * MHz)
20
+#define HPLL_HZ (1000 * MHz)
21
+
22
+/* RK3562 pll id */
23
+enum rk3562_pll_id {
24
+ APLL,
25
+ GPLL,
26
+ VPLL,
27
+ HPLL,
28
+ CPLL,
29
+ DPLL,
30
+ PLL_COUNT,
31
+};
32
+
33
+struct rk3562_clk_info {
34
+ unsigned long id;
35
+ char *name;
36
+};
37
+
38
+struct rk3562_clk_priv {
39
+ struct rk3562_cru *cru;
40
+ ulong gpll_hz;
41
+ ulong vpll_hz;
42
+ ulong hpll_hz;
43
+ ulong cpll_hz;
44
+ ulong armclk_hz;
45
+ ulong armclk_enter_hz;
46
+ ulong armclk_init_hz;
47
+ bool sync_kernel;
48
+ bool set_armclk_rate;
49
+};
50
+
51
+struct rk3562_cru {
52
+ /* top cru */
53
+ uint32_t apll_con[5];
54
+ uint32_t reserved0014[19];
55
+ uint32_t gpll_con[5];
56
+ uint32_t reserved0074[3];
57
+ uint32_t vpll_con[5];
58
+ uint32_t reserved0094[3];
59
+ uint32_t hpll_con[5];
60
+ uint32_t reserved00b4[19];
61
+ uint32_t clksel_con[48];
62
+ uint32_t reserved01c0[80];
63
+ uint32_t gate_con[28];
64
+ uint32_t reserved370[36];
65
+ uint32_t softrst_con[28];
66
+ uint32_t reserved0470[100];
67
+ uint32_t mode_con[1];
68
+ uint32_t reserved0604[3];
69
+ uint32_t glb_cnt_th;
70
+ uint32_t glb_srst_fst;
71
+ uint32_t glb_srst_snd;
72
+ uint32_t glb_rst_con;
73
+ uint32_t glb_rst_st;
74
+ unsigned int sdmmc0_con[2];
75
+ unsigned int sdmmc1_con[2];
76
+ uint32_t reserved0634[2];
77
+ unsigned int emmc_con[1];
78
+ uint32_t reserved0640[15984];
79
+
80
+ /* pmu0 cru */
81
+ uint32_t reserved10000[64];
82
+ uint32_t pmu0clksel_con[4];
83
+ uint32_t reserved10110[28];
84
+ uint32_t pmu0gate_con[3];
85
+ uint32_t reserved1018c[29];
86
+ uint32_t pmu0softrst_con[3];
87
+ uint32_t reserved1020c[8061];
88
+
89
+ /* pmu1 cru */
90
+ uint32_t reserved18000[16];
91
+ uint32_t cpll_con[5];
92
+ uint32_t reserved18054[43];
93
+ uint32_t pmu1clksel_con[7];
94
+ uint32_t reserved1811c[25];
95
+ uint32_t pmu1gate_con[4];
96
+ uint32_t reserved18190[28];
97
+ uint32_t pmu1softrst_con[3];
98
+ uint32_t reserved1820c[93];
99
+ uint32_t pmu1mode_con[1];
100
+ uint32_t reserved18384[7967];
101
+
102
+ /* ddr cru */
103
+ uint32_t reserved20000[64];
104
+ uint32_t ddrclksel_con[2];
105
+ uint32_t reserved20108[30];
106
+ uint32_t ddrgate_con[2];
107
+ uint32_t reserved20188[30];
108
+ uint32_t ddrsoftrst_con[2];
109
+ uint32_t reserved20208[8062];
110
+
111
+ /* subddr cru */
112
+ uint32_t reserved28000[8];
113
+ uint32_t dpll_con[5];
114
+ uint32_t reserved28034[51];
115
+ uint32_t sudbddrclksel_con[1];
116
+ uint32_t reserved28104[31];
117
+ uint32_t subddrgate_con[1];
118
+ uint32_t reserved28184[31];
119
+ uint32_t sudbddrsoftrst_con[1];
120
+ uint32_t reserved28204[95];
121
+ uint32_t subddrmode_con[1];
122
+ uint32_t reserved28384[7967];
123
+
124
+ /* peri cru */
125
+ uint32_t reserved30000[64];
126
+ uint32_t periclksel_con[48];
127
+ uint32_t reserved301c0[80];
128
+ uint32_t perigate_con[18];
129
+ uint32_t reserved30348[46];
130
+ uint32_t perisoftrst_con[18];
131
+ uint32_t reserved30448[143];
132
+};
133
+check_member(rk3562_cru, reserved0640[0], 0x00640);
134
+check_member(rk3562_cru, reserved1020c[0], 0x1020c);
135
+check_member(rk3562_cru, reserved18384[0], 0x18384);
136
+check_member(rk3562_cru, reserved20208[0], 0x20208);
137
+check_member(rk3562_cru, reserved28384[0], 0x28384);
138
+check_member(rk3562_cru, reserved30448[0], 0x30448);
139
+
140
+struct pll_rate_table {
141
+ unsigned long rate;
142
+ unsigned int fbdiv;
143
+ unsigned int postdiv1;
144
+ unsigned int refdiv;
145
+ unsigned int postdiv2;
146
+ unsigned int dsmpd;
147
+ unsigned int frac;
148
+};
149
+
150
+#define RK3562_PMU0_CRU_BASE 0x10000
151
+#define RK3562_PMU1_CRU_BASE 0x18000
152
+#define RK3562_DDR_CRU_BASE 0x20000
153
+#define RK3562_SUBDDR_CRU_BASE 0x28000
154
+#define RK3562_PERI_CRU_BASE 0x30000
155
+
156
+#define RK3562_PLL_CON(x) ((x) * 0x4)
157
+#define RK3562_PMU1_PLL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40)
158
+#define RK3562_SUBDDR_PLL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20)
159
+#define RK3562_MODE_CON 0x600
160
+#define RK3562_PMU1_MODE_CON (RK3562_PMU1_CRU_BASE + 0x380)
161
+#define RK3562_SUBDDR_MODE_CON (RK3562_SUBDDR_CRU_BASE + 0x380)
162
+#define RK3562_GLB_SRST_FST 0x614
163
+#define RK3562_GLB_SRST_SND 0x618
164
+#define RK3562_GLB_RST_CON 0x61c
165
+#define RK3562_GLB_RST_ST 0x620
166
+
167
+enum {
168
+ /* CRU_CLKSEL_CON10 */
169
+ CLK_CORE_PRE_DIV_SHIFT = 0,
170
+ CLK_CORE_PRE_DIV_MASK = 0x1f << CLK_CORE_PRE_DIV_SHIFT,
171
+
172
+ /* CRU_CLKSEL_CON11 */
173
+ ACLK_CORE_PRE_DIV_SHIFT = 0,
174
+ ACLK_CORE_PRE_DIV_MASK = 0x7 << ACLK_CORE_PRE_DIV_SHIFT,
175
+ CLK_SCANHS_ACLKM_CORE_DIV_SHIFT = 8,
176
+ CLK_SCANHS_ACLKM_CORE_DIV_MASK = 0x7 << CLK_SCANHS_ACLKM_CORE_DIV_SHIFT,
177
+
178
+ /* CRU_CLKSEL_CON12 */
179
+ PCLK_DBG_PRE_DIV_SHIFT = 0,
180
+ PCLK_DBG_PRE_DIV_MASK = 0xf << PCLK_DBG_PRE_DIV_SHIFT,
181
+ CLK_SCANHS_PCLK_DBG_DIV_SHIFT = 8,
182
+ CLK_SCANHS_PCLK_DBG_DIV_MASK = 0xf << CLK_SCANHS_PCLK_DBG_DIV_SHIFT,
183
+
184
+ /* CRU_CLKSEL_CON28 */
185
+ ACLK_VOP_DIV_SHIFT = 0,
186
+ ACLK_VOP_DIV_MASK = 0x1f << ACLK_VOP_DIV_SHIFT,
187
+ ACLK_VOP_SEL_SHIFT = 6,
188
+ ACLK_VOP_SEL_MASK = 0x3 << ACLK_VOP_SEL_SHIFT,
189
+ ACLK_VOP_SEL_GPLL = 0,
190
+ ACLK_VOP_SEL_CPLL,
191
+ ACLK_VOP_SEL_VPLL,
192
+ ACLK_VOP_SEL_HPLL,
193
+
194
+ /* CRU_CLKSEL_CON30 */
195
+ DCLK_VOP_DIV_SHIFT = 0,
196
+ DCLK_VOP_DIV_MASK = 0xff << DCLK_VOP_DIV_SHIFT,
197
+ DCLK_VOP_SEL_SHIFT = 14,
198
+ DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT,
199
+ DCLK_VOP_SEL_GPLL = 0,
200
+ DCLK_VOP_SEL_HPLL,
201
+ DCLK_VOP_SEL_VPLL,
202
+ DCLK_VOP_SEL_APLL,
203
+
204
+ /* CRU_CLKSEL_CON31 */
205
+ DCLK_VOP1_DIV_SHIFT = 0,
206
+ DCLK_VOP1_DIV_MASK = 0xff << DCLK_VOP1_DIV_SHIFT,
207
+ DCLK_VOP1_SEL_SHIFT = 14,
208
+ DCLK_VOP1_SEL_MASK = 0x3 << DCLK_VOP1_SEL_SHIFT,
209
+
210
+ /* CRU_CLKSEL_CON40 */
211
+ ACLK_BUS_DIV_SHIFT = 0,
212
+ ACLK_BUS_DIV_MASK = 0x1f << ACLK_BUS_DIV_SHIFT,
213
+ ACLK_BUS_SEL_SHIFT = 7,
214
+ ACLK_BUS_SEL_MASK = 0x1 << ACLK_BUS_SEL_SHIFT,
215
+ ACLK_BUS_SEL_GPLL = 0,
216
+ ACLK_BUS_SEL_CPLL,
217
+ HCLK_BUS_DIV_SHIFT = 8,
218
+ HCLK_BUS_DIV_MASK = 0x3f << HCLK_BUS_DIV_SHIFT,
219
+ HCLK_BUS_SEL_SHIFT = 15,
220
+ HCLK_BUS_SEL_MASK = 0x1 << HCLK_BUS_SEL_SHIFT,
221
+
222
+ /* CRU_CLKSEL_CON41 */
223
+ PCLK_BUS_DIV_SHIFT = 0,
224
+ PCLK_BUS_DIV_MASK = 0x1f << PCLK_BUS_DIV_SHIFT,
225
+ PCLK_BUS_SEL_SHIFT = 7,
226
+ PCLK_BUS_SEL_MASK = 0x1 << PCLK_BUS_SEL_SHIFT,
227
+ CLK_I2C_SEL_SHIFT = 8,
228
+ CLK_I2C_SEL_MASK = 0x3 << CLK_I2C_SEL_SHIFT,
229
+ CLK_I2C_SEL_200M = 0,
230
+ CLK_I2C_SEL_100M,
231
+ CLK_I2C_SEL_50M,
232
+ CLK_I2C_SEL_24M,
233
+ DCLK_BUS_GPIO_SEL_SHIFT = 15,
234
+ DCLK_BUS_GPIO_SEL_MASK = 0x1 << DCLK_BUS_GPIO_SEL_SHIFT,
235
+
236
+ /* CRU_CLKSEL_CON43 */
237
+ CLK_TSADC_DIV_SHIFT = 0,
238
+ CLK_TSADC_DIV_MASK = 0x7ff << CLK_TSADC_DIV_SHIFT,
239
+ CLK_TSADC_TSEN_DIV_SHIFT = 11,
240
+ CLK_TSADC_TSEN_DIV_MASK = 0x1f << CLK_TSADC_TSEN_DIV_SHIFT,
241
+
242
+ /* CRU_CLKSEL_CON44 */
243
+ CLK_SARADC_VCCIO156_DIV_SHIFT = 0,
244
+ CLK_SARADC_VCCIO156_DIV_MASK = 0xfff << CLK_SARADC_VCCIO156_DIV_SHIFT,
245
+
246
+ /* CRU_CLKSEL_CON45 */
247
+ CLK_GMAC_125M_SEL_SHIFT = 8,
248
+ CLK_GMAC_125M_SEL_MASK = 0x1 << CLK_GMAC_125M_SEL_SHIFT,
249
+ CLK_GMAC_125M = 0,
250
+ CLK_GMAC_24M,
251
+ CLK_GMAC_50M_SEL_SHIFT = 7,
252
+ CLK_GMAC_50M_SEL_MASK = 0x1 << CLK_GMAC_50M_SEL_SHIFT,
253
+ CLK_GMAC_50M = 0,
254
+
255
+ /* CRU_CLKSEL_CON46 */
256
+ CLK_GMAC_ETH_OUT2IO_SEL_SHIFT = 7,
257
+ CLK_GMAC_ETH_OUT2IO_SEL_MASK = 0x1 << CLK_GMAC_ETH_OUT2IO_SEL_SHIFT,
258
+ CLK_GMAC_ETH_OUT2IO_GPLL = 0,
259
+ CLK_GMAC_ETH_OUT2IO_CPLL,
260
+ CLK_GMAC_ETH_OUT2IO_DIV_SHIFT = 0,
261
+ CLK_GMAC_ETH_OUT2IO_DIV_MASK = 0x7f,
262
+
263
+ /* PMU0CRU_CLKSEL_CON03 */
264
+ CLK_PMU0_I2C0_DIV_SHIFT = 8,
265
+ CLK_PMU0_I2C0_DIV_MASK = 0x1f << CLK_PMU0_I2C0_DIV_SHIFT,
266
+ CLK_PMU0_I2C0_SEL_SHIFT = 14,
267
+ CLK_PMU0_I2C0_SEL_MASK = 0x3 << CLK_PMU0_I2C0_SEL_SHIFT,
268
+ CLK_PMU0_I2C0_SEL_200M = 0,
269
+ CLK_PMU0_I2C0_SEL_24M,
270
+ CLK_PMU0_I2C0_SEL_32K,
271
+
272
+ /* PMU1CRU_CLKSEL_CON02 */
273
+ CLK_PMU1_UART0_SRC_DIV_SHIFT = 0,
274
+ CLK_PMU1_UART0_SRC_DIV_MASK = 0xf << CLK_PMU1_UART0_SRC_DIV_SHIFT,
275
+ CLK_PMU1_UART0_SEL_SHIFT = 6,
276
+ CLK_PMU1_UART0_SEL_MASK = 0x3 << CLK_PMU1_UART0_SEL_SHIFT,
277
+
278
+ /* PMU1CRU_CLKSEL_CON04 */
279
+ CLK_PMU1_SPI0_DIV_SHIFT = 0,
280
+ CLK_PMU1_SPI0_DIV_MASK = 0x3 << CLK_PMU1_SPI0_DIV_SHIFT,
281
+ CLK_PMU1_SPI0_SEL_SHIFT = 6,
282
+ CLK_PMU1_SPI0_SEL_MASK = 0x3 << CLK_PMU1_SPI0_SEL_SHIFT,
283
+ CLK_PMU1_SPI0_SEL_200M = 0,
284
+ CLK_PMU1_SPI0_SEL_24M,
285
+ CLK_PMU1_SPI0_SEL_32K,
286
+ CLK_PMU1_PWM0_DIV_SHIFT = 8,
287
+ CLK_PMU1_PWM0_DIV_MASK = 0x3 << CLK_PMU1_PWM0_DIV_SHIFT,
288
+ CLK_PMU1_PWM0_SEL_SHIFT = 14,
289
+ CLK_PMU1_PWM0_SEL_MASK = 0x3 << CLK_PMU1_PWM0_SEL_SHIFT,
290
+ CLK_PMU1_PWM0_SEL_200M = 0,
291
+ CLK_PMU1_PWM0_SEL_24M,
292
+ CLK_PMU1_PWM0_SEL_32K,
293
+
294
+ /* PERICRU_CLKSEL_CON00 */
295
+ ACLK_PERI_DIV_SHIFT = 0,
296
+ ACLK_PERI_DIV_MASK = 0x1f << ACLK_PERI_DIV_SHIFT,
297
+ ACLK_PERI_SEL_SHIFT = 7,
298
+ ACLK_PERI_SEL_MASK = 0x1 << ACLK_PERI_SEL_SHIFT,
299
+ ACLK_PERI_SEL_GPLL = 0,
300
+ ACLK_PERI_SEL_CPLL,
301
+ HCLK_PERI_DIV_SHIFT = 8,
302
+ HCLK_PERI_DIV_MASK = 0x3f << HCLK_PERI_DIV_SHIFT,
303
+ HCLK_PERI_SEL_SHIFT = 15,
304
+ HCLK_PERI_SEL_MASK = 0x1 << HCLK_PERI_SEL_SHIFT,
305
+
306
+ /* PERICRU_CLKSEL_CON01 */
307
+ PCLK_PERI_DIV_SHIFT = 0,
308
+ PCLK_PERI_DIV_MASK = 0x1f << PCLK_PERI_DIV_SHIFT,
309
+ PCLK_PERI_SEL_SHIFT = 7,
310
+ PCLK_PERI_SEL_MASK = 0x1 << PCLK_PERI_SEL_SHIFT,
311
+ CLK_SAI0_SRC_DIV_SHIFT = 8,
312
+ CLK_SAI0_SRC_DIV_MASK = 0x3f << CLK_SAI0_SRC_DIV_SHIFT,
313
+ CLK_SAI0_SRC_SEL_SHIFT = 14,
314
+ CLK_SAI0_SRC_SEL_MASK = 0x3 << CLK_SAI0_SRC_SEL_SHIFT,
315
+
316
+ /* PERICRU_CLKSEL_CON16 */
317
+ CCLK_SDMMC0_DIV_SHIFT = 0,
318
+ CCLK_SDMMC0_DIV_MASK = 0xff << CCLK_SDMMC0_DIV_SHIFT,
319
+ CCLK_SDMMC0_SEL_SHIFT = 14,
320
+ CCLK_SDMMC0_SEL_MASK = 0x3 << CCLK_SDMMC0_SEL_SHIFT,
321
+ CCLK_SDMMC_SEL_GPLL = 0,
322
+ CCLK_SDMMC_SEL_CPLL,
323
+ CCLK_SDMMC_SEL_24M,
324
+ CCLK_SDMMC_SEL_HPLL,
325
+
326
+ /* PERICRU_CLKSEL_CON17 */
327
+ CCLK_SDMMC1_DIV_SHIFT = 0,
328
+ CCLK_SDMMC1_DIV_MASK = 0xff << CCLK_SDMMC1_DIV_SHIFT,
329
+ CCLK_SDMMC1_SEL_SHIFT = 14,
330
+ CCLK_SDMMC1_SEL_MASK = 0x3 << CCLK_SDMMC1_SEL_SHIFT,
331
+
332
+ /* PERICRU_CLKSEL_CON18 */
333
+ CCLK_EMMC_DIV_SHIFT = 0,
334
+ CCLK_EMMC_DIV_MASK = 0xff << CCLK_EMMC_DIV_SHIFT,
335
+ CCLK_EMMC_SEL_SHIFT = 14,
336
+ CCLK_EMMC_SEL_MASK = 0x3 << CCLK_EMMC_SEL_SHIFT,
337
+ CCLK_EMMC_SEL_GPLL = 0,
338
+ CCLK_EMMC_SEL_CPLL,
339
+ CCLK_EMMC_SEL_24M,
340
+ CCLK_EMMC_SEL_HPLL,
341
+
342
+ /* PERICRU_CLKSEL_CON19 */
343
+ BCLK_EMMC_DIV_SHIFT = 8,
344
+ BCLK_EMMC_DIV_MASK = 0x7f << BCLK_EMMC_DIV_SHIFT,
345
+ BCLK_EMMC_SEL_SHIFT = 15,
346
+ BCLK_EMMC_SEL_MASK = 0x1 << BCLK_EMMC_SEL_SHIFT,
347
+ BCLK_EMMC_SEL_GPLL = 0,
348
+ BCLK_EMMC_SEL_CPLL,
349
+
350
+ /* PERICRU_CLKSEL_CON20 */
351
+ SCLK_SFC_DIV_SHIFT = 0,
352
+ SCLK_SFC_DIV_MASK = 0xff << SCLK_SFC_DIV_SHIFT,
353
+ SCLK_SFC_SEL_SHIFT = 8,
354
+ SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT,
355
+ SCLK_SFC_SRC_SEL_GPLL = 0,
356
+ SCLK_SFC_SRC_SEL_CPLL,
357
+ SCLK_SFC_SRC_SEL_24M,
358
+ CLK_SPI1_SEL_SHIFT = 12,
359
+ CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT,
360
+ CLK_SPI_SEL_200M = 0,
361
+ CLK_SPI_SEL_100M,
362
+ CLK_SPI_SEL_50M,
363
+ CLK_SPI_SEL_24M,
364
+ CLK_SPI2_SEL_SHIFT = 14,
365
+ CLK_SPI2_SEL_MASK = 0x3 << CLK_SPI2_SEL_SHIFT,
366
+
367
+ /* PERICRU_CLKSEL_CON21 */
368
+ CLK_UART_SRC_DIV_SHIFT = 0,
369
+ CLK_UART_SRC_DIV_MASK = 0x7f << CLK_UART_SRC_DIV_SHIFT,
370
+ CLK_UART_SRC_SEL_SHIFT = 8,
371
+ CLK_UART_SRC_SEL_MASK = 0x1 << CLK_UART_SRC_SEL_SHIFT,
372
+ CLK_UART_SRC_SEL_GPLL = 0,
373
+ CLK_UART_SRC_SEL_CPLL,
374
+ CLK_UART_SEL_SHIFT = 14,
375
+ CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT,
376
+ CLK_UART_SEL_SRC = 0,
377
+ CLK_UART_SEL_FRAC,
378
+ CLK_UART_SEL_XIN24M,
379
+
380
+ /* PERICRU_CLKSEL_CON22 */
381
+ CLK_UART_FRAC_NUMERATOR_SHIFT = 16,
382
+ CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16,
383
+ CLK_UART_FRAC_DENOMINATOR_SHIFT = 0,
384
+ CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff,
385
+
386
+ /* PERICRU_CLKSEL_CON40 */
387
+ CLK_PWM1_PERI_SEL_SHIFT = 0,
388
+ CLK_PWM1_PERI_SEL_MASK = 0x3 << CLK_PWM1_PERI_SEL_SHIFT,
389
+ CLK_PWM_SEL_100M = 0,
390
+ CLK_PWM_SEL_50M,
391
+ CLK_PWM_SEL_24M,
392
+ CLK_PWM2_PERI_SEL_SHIFT = 6,
393
+ CLK_PWM2_PERI_SEL_MASK = 0x3 << CLK_PWM2_PERI_SEL_SHIFT,
394
+ CLK_PWM3_PERI_SEL_SHIFT = 8,
395
+ CLK_PWM3_PERI_SEL_MASK = 0x3 << CLK_PWM3_PERI_SEL_SHIFT,
396
+
397
+ /* PERICRU_CLKSEL_CON43 */
398
+ CLK_CORE_CRYPTO_SEL_SHIFT = 0,
399
+ CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT,
400
+ CLK_CORE_CRYPTO_SEL_200M = 0,
401
+ CLK_CORE_CRYPTO_SEL_100M,
402
+ CLK_CORE_CRYPTO_SEL_24M,
403
+ CLK_PKA_CRYPTO_SEL_SHIFT = 6,
404
+ CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT,
405
+ CLK_PKA_CRYPTO_SEL_300M = 0,
406
+ CLK_PKA_CRYPTO_SEL_200M,
407
+ CLK_PKA_CRYPTO_SEL_100M,
408
+ CLK_PKA_CRYPTO_SEL_24M,
409
+ TCLK_PERI_WDT_SEL_SHIFT = 15,
410
+ TCLK_PERI_WDT_SEL_MASK = 0x1 << TCLK_PERI_WDT_SEL_SHIFT,
411
+
412
+ /* PERICRU_CLKSEL_CON46 */
413
+ CLK_SARADC_DIV_SHIFT = 0,
414
+ CLK_SARADC_DIV_MASK = 0xfff << CLK_SARADC_DIV_SHIFT,
415
+};
416
+#endif
u-boot/arch/arm/include/asm/arch-rockchip/fit.h
....@@ -14,7 +14,7 @@
1414
1515 int fit_image_pre_process(const void *fit);
1616 int fit_image_fail_process(const void *fit);
17
-int fit_image_init_resource(void);
1817 int fit_image_read_dtb(void *fdt_addr);
18
+ulong fit_image_init_resource(struct blk_desc *dev_desc);
1919
2020 #endif
u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3528.h
....@@ -0,0 +1,89 @@
1
+/*
2
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd.
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+#ifndef _ASM_ARCH_GRF_RK3528_H
7
+#define _ASM_ARCH_GRF_RK3528_H
8
+
9
+#include <common.h>
10
+
11
+struct rk3528_grf {
12
+ uint32_t reserved0[0x40018 / 4];
13
+
14
+ /* vpugrf*/
15
+ uint32_t gmac1_con0; /* Address Offset: 0x40018 */
16
+ uint32_t gmac1_con1; /* Address Offset: 0x4001c */
17
+ uint32_t reserved1[(0x60018 - 0x4001c) / 4 - 1];
18
+
19
+ /* vogrf */
20
+ uint32_t gmac0_con; /* Address Offset: 0x60018 */
21
+ uint32_t macphy_con0; /* Address Offset: 0x6001c */
22
+ uint32_t macphy_con1; /* Address Offset: 0x60020 */
23
+ uint32_t sdmmc_con0; /* Address Offset: 0x60024 */
24
+ uint32_t sdmmc_con1; /* Address Offset: 0x60028 */
25
+ uint32_t reserved2[(0x70000 - 0x60028) / 4 - 1];
26
+
27
+ /* pmugrf */
28
+ uint32_t soc_con[8]; /* Address Offset: 0x70000 */
29
+ uint32_t soc_status; /* Address Offset: 0x70020 */
30
+ uint32_t reserved3[3]; /* Address Offset: 0x70024 */
31
+ uint32_t pmuio_vsel; /* Address Offset: 0x70030 */
32
+ uint32_t reserved4[3]; /* Address Offset: 0x70034 */
33
+ uint32_t mem_con; /* Address Offset: 0x70040 */
34
+ uint32_t reserved5[47]; /* Address Offset: 0x70044 */
35
+ uint32_t rstfunc_status; /* Address Offset: 0x70100 */
36
+ uint32_t rstfunc_clr; /* Address Offset: 0x70104 */
37
+ uint32_t reserved6[62]; /* Address Offset: 0x70108 */
38
+ uint32_t os_reg0; /* Address Offset: 0x70200 */
39
+ uint32_t os_reg1; /* Address Offset: 0x70204 */
40
+ uint32_t os_reg2; /* Address Offset: 0x70208 */
41
+ uint32_t os_reg3; /* Address Offset: 0x7020C */
42
+ uint32_t os_reg4; /* Address Offset: 0x70210 */
43
+ uint32_t os_reg5; /* Address Offset: 0x70214 */
44
+ uint32_t os_reg6; /* Address Offset: 0x70218 */
45
+ uint32_t os_reg7; /* Address Offset: 0x7021C */
46
+ uint32_t os_reg8; /* Address Offset: 0x70220 */
47
+ uint32_t os_reg9; /* Address Offset: 0x70224 */
48
+ uint32_t os_reg10; /* Address Offset: 0x70228 */
49
+ uint32_t os_reg11; /* Address Offset: 0x7022C */
50
+ uint32_t os_reg12; /* Address Offset: 0x70230 */
51
+ uint32_t os_reg13; /* Address Offset: 0x70234 */
52
+ uint32_t os_reg14; /* Address Offset: 0x70238 */
53
+ uint32_t os_reg15; /* Address Offset: 0x7023C */
54
+ uint32_t os_reg16; /* Address Offset: 0x70240 */
55
+ uint32_t os_reg17; /* Address Offset: 0x70244 */
56
+ uint32_t os_reg18; /* Address Offset: 0x70248 */
57
+ uint32_t os_reg19; /* Address Offset: 0x7024C */
58
+ uint32_t os_reg20; /* Address Offset: 0x70250 */
59
+ uint32_t os_reg21; /* Address Offset: 0x70254 */
60
+ uint32_t os_reg22; /* Address Offset: 0x70258 */
61
+ uint32_t os_reg23; /* Address Offset: 0x7025C */
62
+ uint32_t reserved7[(0x80000 - 0x7025C) / 4 - 1];
63
+
64
+ uint32_t grf_sys_con[2]; /* Address Offset: 0x80000 */
65
+ uint32_t reserved8[2]; /* Address Offset: 0x80008 */
66
+ uint32_t grf_sys_status; /* Address Offset: 0x80010 */
67
+ uint32_t reserved9[3]; /* Address Offset: 0x80014 */
68
+ uint32_t grf_biu_con[2]; /* Address Offset: 0x80020 */
69
+ uint32_t reserved10[2]; /* Address Offset: 0x80028 */
70
+ uint32_t grf_biu_status[3]; /* Address Offset: 0x80030 */
71
+ uint32_t reserved11[17]; /* Address Offset: 0x8003C */
72
+ uint32_t grf_sys_mem_con[5]; /* Address Offset: 0x80080 */
73
+ uint32_t reserved12[59]; /* Address Offset: 0x80094 */
74
+ uint32_t grf_soc_code; /* Address Offset: 0x80180 */
75
+ uint32_t reserved13[3]; /* Address Offset: 0x80184 */
76
+ uint32_t grf_soc_version; /* Address Offset: 0x80190 */
77
+ uint32_t reserved14[3]; /* Address Offset: 0x80194 */
78
+ uint32_t grf_chip_id; /* Address Offset: 0x801A0 */
79
+ uint32_t reserved15[3]; /* Address Offset: 0x801A4 */
80
+ uint32_t grf_chip_version; /* Address Offset: 0x801B0 */
81
+ uint32_t reserved16[(0x10000 - 0x81b0) / 4 - 1];
82
+
83
+};
84
+
85
+check_member(rk3528_grf, sdmmc_con1, 0x60028);
86
+check_member(rk3528_grf, os_reg23, 0x7025C);
87
+check_member(rk3528_grf, grf_chip_version, 0x801B0);
88
+
89
+#endif
u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3562.h
....@@ -0,0 +1,76 @@
1
+/*
2
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd.
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+#ifndef _ASM_ARCH_GRF_RK3562_H
7
+#define _ASM_ARCH_GRF_RK3562_H
8
+
9
+#include <common.h>
10
+
11
+struct rk3562_pmu_grf {
12
+ /* pmugrf */
13
+ uint32_t reserved1[(0x0100 - 0x0000) / 4]; /* address offset: 0x0000 */
14
+ uint32_t soc_con[13]; /* address offset: 0x0100 */
15
+ uint32_t soc_status[1]; /* address offset: 0x0134 */
16
+ uint32_t reserved2[(0x0180 - 0x0134) / 4 - 1]; /* address offset: 0x0138 */
17
+ uint32_t pvtm_con[1]; /* address offset: 0x0180 */
18
+ uint32_t reserved3[(0x0200 - 0x0180) / 4 - 1]; /* address offset: 0x0184 */
19
+ uint32_t os_reg[12]; /* address offset: 0x0200 */
20
+ uint32_t reset_function_status; /* address offset: 0x0230 */
21
+ uint32_t reset_function_clr; /* address offset: 0x0234 */
22
+ uint32_t reserved4[(0x0380 - 0x0234) / 4 - 1]; /* address offset: 0x0238 */
23
+ uint32_t sig_detect_con; /* address offset: 0x0380 */
24
+ uint32_t reserved5[(0x0390 - 0x0380) / 4 - 1]; /* address offset: 0x0384 */
25
+ uint32_t sig_detect_status; /* address offset: 0x0390 */
26
+ uint32_t reserved6[(0x03a0 - 0x0390) / 4 - 1]; /* address offset: 0x0394 */
27
+ uint32_t sig_detect_status_clear; /* address offset: 0x03a0 */
28
+ uint32_t reserved7[(0x03b0 - 0x03a0) / 4 - 1]; /* address offset: 0x03a4 */
29
+ uint32_t sdmmc_det_counter; /* address offset: 0x03b0 */
30
+};
31
+
32
+check_member(rk3562_pmu_grf, sdmmc_det_counter, 0x03b0);
33
+
34
+struct rk3562_grf {
35
+ /* sysgrf */
36
+ uint32_t reserved1[(0x0400 - 0x0000) / 4]; /* address offset: 0x0000 */
37
+ uint32_t soc_con[7]; /* address offset: 0x0400 */
38
+ uint32_t reserved2[(0x0430 - 0x0400) / 4 - 7]; /* address offset: 0x041c */
39
+ uint32_t soc_status[3]; /* address offset: 0x0430 */
40
+ uint32_t reserved3; /* address offset: 0x043c */
41
+ uint32_t biu_con[2]; /* address offset: 0x0440 */
42
+ uint32_t reserved4[(0x0460 - 0x0440) / 4 - 2]; /* address offset: 0x0448 */
43
+ uint32_t ram_con; /* address offset: 0x0460 */
44
+ uint32_t core_ram_con; /* address offset: 0x0464 */
45
+ uint32_t reserved5[(0x0500 - 0x0464) / 4 - 1]; /* address offset: 0x0468 */
46
+ uint32_t cpu_con[2]; /* address offset: 0x0500 */
47
+ uint32_t reserved6[(0x0510 - 0x0500) / 4 - 2]; /* address offset: 0x0508 */
48
+ uint32_t cpu_status[2]; /* address offset: 0x0510 */
49
+ uint32_t reserved7[(0x0520 - 0x0510) / 4 - 2]; /* address offset: 0x0518 */
50
+ uint32_t vi_con[2]; /* address offset: 0x0520 */
51
+ uint32_t reserved8[(0x0530 - 0x0520) / 4 - 2]; /* address offset: 0x0528 */
52
+ uint32_t vi_status[1]; /* address offset: 0x0530 */
53
+ uint32_t reserved9[(0x0570 - 0x0530) / 4 - 1]; /* address offset: 0x0534 */
54
+ uint32_t gpu_con[2]; /* address offset: 0x0570 */
55
+ uint32_t reserved10[(0x0580 - 0x0570) / 4 - 2]; /* address offset: 0x0578 */
56
+ uint32_t tsadc_con; /* address offset: 0x0580 */
57
+ uint32_t reserved11[(0x05d0 - 0x0580) / 4 - 1]; /* address offset: 0x0584 */
58
+ uint32_t vo_con[2]; /* address offset: 0x05d0 */
59
+ uint32_t reserved12[(0x0600 - 0x05d0) / 4 - 2]; /* address offset: 0x05d8 */
60
+ uint32_t top_pvtpll_con[4]; /* address offset: 0x0600 */
61
+ uint32_t top_pvtpll_status[2]; /* address offset: 0x0610 */
62
+ uint32_t reserved13[(0x0620 - 0x0610) / 4 - 2]; /* address offset: 0x0618 */
63
+ uint32_t cpu_pvtpll_con[4]; /* address offset: 0x0620 */
64
+ uint32_t cpu_pvtpll_status[2]; /* address offset: 0x0630 */
65
+ uint32_t reserved14[(0x0640 - 0x0630) / 4 - 2]; /* address offset: 0x0638 */
66
+ uint32_t gpu_pvtpll_con[4]; /* address offset: 0x0640 */
67
+ uint32_t gpu_pvtpll_status[2]; /* address offset: 0x0650 */
68
+ uint32_t reserved15[(0x0660 - 0x0650) / 4 - 2]; /* address offset: 0x0658 */
69
+ uint32_t npu_pvtpll_con[4]; /* address offset: 0x0660 */
70
+ uint32_t npu_pvtpll_status[2]; /* address offset: 0x0670 */
71
+ uint32_t reserved16[(0x0800 - 0x0670) / 4 - 2]; /* address offset: 0x0678 */
72
+ uint32_t chip_id; /* address offset: 0x0800 */
73
+};
74
+check_member(rk3562_grf, chip_id, 0x0800);
75
+
76
+#endif
u-boot/arch/arm/include/asm/arch-rockchip/ioc_rk3528.h
....@@ -0,0 +1,196 @@
1
+/*
2
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd.
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+#ifndef _ASM_ARCH_IOC_RK3528_H
7
+#define _ASM_ARCH_IOC_RK3528_H
8
+
9
+#include <common.h>
10
+
11
+struct rk3528_gpio0_ioc {
12
+ uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */
13
+ uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */
14
+ uint32_t reserved0008[62]; /* Address Offset: 0x0008 */
15
+ uint32_t gpio0a_ds[3]; /* Address Offset: 0x0100 */
16
+ uint32_t reserved010c[61]; /* Address Offset: 0x010C */
17
+ uint32_t gpio0a_pull; /* Address Offset: 0x0200 */
18
+ uint32_t reserved0204[63]; /* Address Offset: 0x0204 */
19
+ uint32_t gpio0a_ie; /* Address Offset: 0x0300 */
20
+ uint32_t reserved0304[63]; /* Address Offset: 0x0304 */
21
+ uint32_t gpio0a_smt; /* Address Offset: 0x0400 */
22
+ uint32_t reserved0404[63]; /* Address Offset: 0x0404 */
23
+ uint32_t gpio0a_sus; /* Address Offset: 0x0500 */
24
+ uint32_t reserved0504[63]; /* Address Offset: 0x0504 */
25
+ uint32_t gpio0a_sl; /* Address Offset: 0x0600 */
26
+ uint32_t reserved0604[63]; /* Address Offset: 0x0604 */
27
+ uint32_t gpio0a_od; /* Address Offset: 0x0700 */
28
+ uint32_t vcc5vio_ctrl; /* Address Offset: 0x0704 */
29
+};
30
+check_member(rk3528_gpio0_ioc, vcc5vio_ctrl, 0x0704);
31
+
32
+struct rk3528_gpio1_ioc {
33
+ uint32_t reserved0000[8]; /* Address Offset: 0x0000 */
34
+ uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */
35
+ uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */
36
+ uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */
37
+ uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x002C */
38
+ uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0030 */
39
+ uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0034 */
40
+ uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0038 */
41
+ uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x003C */
42
+ uint32_t reserved0040[56]; /* Address Offset: 0x0040 */
43
+ uint32_t gpio1a_ds[4]; /* Address Offset: 0x0120 */
44
+ uint32_t gpio1b_ds[4]; /* Address Offset: 0x0130 */
45
+ uint32_t gpio1c_ds[4]; /* Address Offset: 0x0140 */
46
+ uint32_t gpio1d_ds[4]; /* Address Offset: 0x0150 */
47
+ uint32_t reserved0160[44]; /* Address Offset: 0x0160 */
48
+ uint32_t gpio1a_pull; /* Address Offset: 0x0210 */
49
+ uint32_t gpio1b_pull; /* Address Offset: 0x0214 */
50
+ uint32_t gpio1c_pull; /* Address Offset: 0x0218 */
51
+ uint32_t gpio1d_pull; /* Address Offset: 0x021C */
52
+ uint32_t reserved0220[60]; /* Address Offset: 0x0220 */
53
+ uint32_t gpio1a_ie; /* Address Offset: 0x0310 */
54
+ uint32_t gpio1b_ie; /* Address Offset: 0x0314 */
55
+ uint32_t gpio1c_ie; /* Address Offset: 0x0318 */
56
+ uint32_t gpio1d_ie; /* Address Offset: 0x031C */
57
+ uint32_t reserved0320[60]; /* Address Offset: 0x0320 */
58
+ uint32_t gpio1a_smt; /* Address Offset: 0x0410 */
59
+ uint32_t gpio1b_smt; /* Address Offset: 0x0414 */
60
+ uint32_t gpio1c_smt; /* Address Offset: 0x0418 */
61
+ uint32_t gpio1d_smt; /* Address Offset: 0x041C */
62
+ uint32_t reserved0420[60]; /* Address Offset: 0x0420 */
63
+ uint32_t gpio1a_sus; /* Address Offset: 0x0510 */
64
+ uint32_t gpio1b_sus; /* Address Offset: 0x0514 */
65
+ uint32_t gpio1c_sus; /* Address Offset: 0x0518 */
66
+ uint32_t gpio1d_sus; /* Address Offset: 0x051C */
67
+ uint32_t reserved0520[60]; /* Address Offset: 0x0520 */
68
+ uint32_t gpio1a_sl; /* Address Offset: 0x0610 */
69
+ uint32_t gpio1b_sl; /* Address Offset: 0x0614 */
70
+ uint32_t gpio1c_sl; /* Address Offset: 0x0618 */
71
+ uint32_t gpio1d_sl; /* Address Offset: 0x061C */
72
+ uint32_t reserved0620[60]; /* Address Offset: 0x0620 */
73
+ uint32_t gpio1a_od; /* Address Offset: 0x0710 */
74
+ uint32_t gpio1b_od; /* Address Offset: 0x0714 */
75
+ uint32_t gpio1c_od; /* Address Offset: 0x0718 */
76
+ uint32_t gpio1d_od; /* Address Offset: 0x071C */
77
+ uint32_t reserved0720[60]; /* Address Offset: 0x0720 */
78
+ uint32_t vccio0_poc; /* Address Offset: 0x0810 */
79
+ uint32_t reserved0814[3]; /* Address Offset: 0x0814 */
80
+ uint32_t vccio1_poc; /* Address Offset: 0x0820 */
81
+};
82
+check_member(rk3528_gpio1_ioc, vccio1_poc, 0x0820);
83
+
84
+struct rk3528_gpio2_ioc {
85
+ uint32_t reserved0000[16]; /* Address Offset: 0x0000 */
86
+ uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0040 */
87
+ uint32_t gpio2a_iomux_sel_h; /* Address Offset: 0x0044 */
88
+ uint32_t reserved0048[70]; /* Address Offset: 0x0048 */
89
+ uint32_t gpio2a_ds[4]; /* Address Offset: 0x0160 */
90
+ uint32_t reserved0170[44]; /* Address Offset: 0x0170 */
91
+ uint32_t gpio2a_pull; /* Address Offset: 0x0220 */
92
+ uint32_t reserved0224[63]; /* Address Offset: 0x0224 */
93
+ uint32_t gpio2a_ie; /* Address Offset: 0x0320 */
94
+ uint32_t reserved0324[63]; /* Address Offset: 0x0324 */
95
+ uint32_t gpio2a_smt; /* Address Offset: 0x0420 */
96
+ uint32_t reserved0424[63]; /* Address Offset: 0x0424 */
97
+ uint32_t gpio2a_sus; /* Address Offset: 0x0520 */
98
+ uint32_t reserved0524[63]; /* Address Offset: 0x0524 */
99
+ uint32_t gpio2a_sl; /* Address Offset: 0x0620 */
100
+ uint32_t reserved0624[63]; /* Address Offset: 0x0624 */
101
+ uint32_t gpio2a_od; /* Address Offset: 0x0720 */
102
+ uint32_t reserved0724[67]; /* Address Offset: 0x0724 */
103
+ uint32_t vccio2_poc; /* Address Offset: 0x0830 */
104
+};
105
+check_member(rk3528_gpio2_ioc, vccio2_poc, 0x0830);
106
+
107
+struct rk3528_gpio3_ioc {
108
+ uint32_t reserved0000[24]; /* Address Offset: 0x0000 */
109
+ uint32_t gpio3a_iomux_sel_l; /* Address Offset: 0x0060 */
110
+ uint32_t gpio3a_iomux_sel_h; /* Address Offset: 0x0064 */
111
+ uint32_t gpio3b_iomux_sel_l; /* Address Offset: 0x0068 */
112
+ uint32_t gpio3b_iomux_sel_h; /* Address Offset: 0x006C */
113
+ uint32_t gpio3c_iomux_sel_l; /* Address Offset: 0x0070 */
114
+ uint32_t reserved0074[71]; /* Address Offset: 0x0074 */
115
+ uint32_t gpio3a_ds[4]; /* Address Offset: 0x0190 */
116
+ uint32_t gpio3b_ds[4]; /* Address Offset: 0x01A0 */
117
+ uint32_t gpio3c_ds[2]; /* Address Offset: 0x01B0 */
118
+ uint32_t reserved01b8[30]; /* Address Offset: 0x01B8 */
119
+ uint32_t gpio3a_pull; /* Address Offset: 0x0230 */
120
+ uint32_t gpio3b_pull; /* Address Offset: 0x0234 */
121
+ uint32_t gpio3c_pull; /* Address Offset: 0x0238 */
122
+ uint32_t reserved023c[61]; /* Address Offset: 0x023C */
123
+ uint32_t gpio3a_ie; /* Address Offset: 0x0330 */
124
+ uint32_t gpio3b_ie; /* Address Offset: 0x0334 */
125
+ uint32_t gpio3c_ie; /* Address Offset: 0x0338 */
126
+ uint32_t reserved033c[61]; /* Address Offset: 0x033C */
127
+ uint32_t gpio3a_smt; /* Address Offset: 0x0430 */
128
+ uint32_t gpio3b_smt; /* Address Offset: 0x0434 */
129
+ uint32_t gpio3c_smt; /* Address Offset: 0x0438 */
130
+ uint32_t reserved043c[61]; /* Address Offset: 0x043C */
131
+ uint32_t gpio3a_sus; /* Address Offset: 0x0530 */
132
+ uint32_t gpio3b_sus; /* Address Offset: 0x0534 */
133
+ uint32_t gpio3c_sus; /* Address Offset: 0x0538 */
134
+ uint32_t reserved053c[61]; /* Address Offset: 0x053C */
135
+ uint32_t gpio3a_sl; /* Address Offset: 0x0630 */
136
+ uint32_t gpio3b_sl; /* Address Offset: 0x0634 */
137
+ uint32_t gpio3c_sl; /* Address Offset: 0x0638 */
138
+ uint32_t reserved063c[61]; /* Address Offset: 0x063C */
139
+ uint32_t gpio3a_od; /* Address Offset: 0x0730 */
140
+ uint32_t gpio3b_od; /* Address Offset: 0x0734 */
141
+ uint32_t gpio3c_od; /* Address Offset: 0x0738 */
142
+ uint32_t reserved073c[65]; /* Address Offset: 0x073C */
143
+ uint32_t vccio3_poc; /* Address Offset: 0x0840 */
144
+};
145
+check_member(rk3528_gpio3_ioc, vccio3_poc, 0x0840);
146
+
147
+struct rk3528_gpio4_ioc {
148
+ uint32_t reserved0000[32]; /* Address Offset: 0x0000 */
149
+ uint32_t gpio4a_iomux_sel_l; /* Address Offset: 0x0080 */
150
+ uint32_t gpio4a_iomux_sel_h; /* Address Offset: 0x0084 */
151
+ uint32_t gpio4b_iomux_sel_l; /* Address Offset: 0x0088 */
152
+ uint32_t gpio4b_iomux_sel_h; /* Address Offset: 0x008C */
153
+ uint32_t gpio4c_iomux_sel_l; /* Address Offset: 0x0090 */
154
+ uint32_t gpio4c_iomux_sel_h; /* Address Offset: 0x0094 */
155
+ uint32_t gpio4d_iomux_sel_l; /* Address Offset: 0x0098 */
156
+ uint32_t reserved009c[73]; /* Address Offset: 0x009C */
157
+ uint32_t gpio4a_ds[4]; /* Address Offset: 0x01C0 */
158
+ uint32_t gpio4b_ds[4]; /* Address Offset: 0x01D0 */
159
+ uint32_t gpio4c_ds[4]; /* Address Offset: 0x01E0 */
160
+ uint32_t gpio4d_ds[1]; /* Address Offset: 0x01F0 */
161
+ uint32_t reserved01f4[19]; /* Address Offset: 0x01F4 */
162
+ uint32_t gpio4a_pull; /* Address Offset: 0x0240 */
163
+ uint32_t gpio4b_pull; /* Address Offset: 0x0244 */
164
+ uint32_t gpio4c_pull; /* Address Offset: 0x0248 */
165
+ uint32_t gpio4d_pull; /* Address Offset: 0x024C */
166
+ uint32_t reserved0250[60]; /* Address Offset: 0x0250 */
167
+ uint32_t gpio4a_ie; /* Address Offset: 0x0340 */
168
+ uint32_t gpio4b_ie; /* Address Offset: 0x0344 */
169
+ uint32_t gpio4c_ie; /* Address Offset: 0x0348 */
170
+ uint32_t gpio4d_ie; /* Address Offset: 0x034C */
171
+ uint32_t reserved0350[60]; /* Address Offset: 0x0350 */
172
+ uint32_t gpio4a_smt; /* Address Offset: 0x0440 */
173
+ uint32_t gpio4b_smt; /* Address Offset: 0x0444 */
174
+ uint32_t gpio4c_smt; /* Address Offset: 0x0448 */
175
+ uint32_t gpio4d_smt; /* Address Offset: 0x044C */
176
+ uint32_t reserved0450[60]; /* Address Offset: 0x0450 */
177
+ uint32_t gpio4a_sus; /* Address Offset: 0x0540 */
178
+ uint32_t gpio4b_sus; /* Address Offset: 0x0544 */
179
+ uint32_t gpio4c_sus; /* Address Offset: 0x0548 */
180
+ uint32_t gpio4d_sus; /* Address Offset: 0x054C */
181
+ uint32_t reserved0550[60]; /* Address Offset: 0x0550 */
182
+ uint32_t gpio4a_sl; /* Address Offset: 0x0640 */
183
+ uint32_t gpio4b_sl; /* Address Offset: 0x0644 */
184
+ uint32_t gpio4c_sl; /* Address Offset: 0x0648 */
185
+ uint32_t gpio4d_sl; /* Address Offset: 0x064C */
186
+ uint32_t reserved0650[60]; /* Address Offset: 0x0650 */
187
+ uint32_t gpio4a_od; /* Address Offset: 0x0740 */
188
+ uint32_t gpio4b_od; /* Address Offset: 0x0744 */
189
+ uint32_t gpio4c_od; /* Address Offset: 0x0748 */
190
+ uint32_t gpio4d_od; /* Address Offset: 0x074C */
191
+ uint32_t reserved0750[64]; /* Address Offset: 0x0750 */
192
+ uint32_t vccio4_poc; /* Address Offset: 0x0850 */
193
+};
194
+check_member(rk3528_gpio4_ioc, vccio4_poc, 0x0850);
195
+#endif
196
+
u-boot/arch/arm/include/asm/arch-rockchip/ioc_rk3562.h
....@@ -0,0 +1,211 @@
1
+/*
2
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd.
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+#ifndef _ASM_ARCH_IOC_RK3562_H
7
+#define _ASM_ARCH_IOC_RK3562_H
8
+
9
+#include <common.h>
10
+
11
+struct rk3562_ioc {
12
+ uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0000 */
13
+ uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0004 */
14
+ uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0008 */
15
+ uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x000C */
16
+ uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0010 */
17
+ uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0014 */
18
+ uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0018 */
19
+ uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x001C */
20
+ uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0020 */
21
+ uint32_t reserved0024[23]; /* Address Offset: 0x0024 */
22
+ uint32_t gpio1a_p; /* Address Offset: 0x0080 */
23
+ uint32_t gpio1b_p; /* Address Offset: 0x0084 */
24
+ uint32_t gpio1c_p; /* Address Offset: 0x0088 */
25
+ uint32_t gpio1d_p; /* Address Offset: 0x008C */
26
+ uint32_t gpio2a_p; /* Address Offset: 0x0090 */
27
+ uint32_t reserved0094[11]; /* Address Offset: 0x0094 */
28
+ uint32_t gpio1a_ie; /* Address Offset: 0x00C0 */
29
+ uint32_t gpio1b_ie; /* Address Offset: 0x00C4 */
30
+ uint32_t gpio1c_ie; /* Address Offset: 0x00C8 */
31
+ uint32_t gpio1d_ie; /* Address Offset: 0x00CC */
32
+ uint32_t gpio2a_ie; /* Address Offset: 0x00D0 */
33
+ uint32_t reserved00d4[11]; /* Address Offset: 0x00D4 */
34
+ uint32_t gpio1a_od; /* Address Offset: 0x0100 */
35
+ uint32_t gpio1b_od; /* Address Offset: 0x0104 */
36
+ uint32_t gpio1c_od; /* Address Offset: 0x0108 */
37
+ uint32_t gpio1d_od; /* Address Offset: 0x010C */
38
+ uint32_t gpio2a_od; /* Address Offset: 0x0110 */
39
+ uint32_t reserved0114[11]; /* Address Offset: 0x0114 */
40
+ uint32_t gpio1a_sus; /* Address Offset: 0x0140 */
41
+ uint32_t gpio1b_sus; /* Address Offset: 0x0144 */
42
+ uint32_t gpio1c_sus; /* Address Offset: 0x0148 */
43
+ uint32_t gpio1d_sus; /* Address Offset: 0x014C */
44
+ uint32_t gpio2a_sus; /* Address Offset: 0x0150 */
45
+ uint32_t reserved0154[11]; /* Address Offset: 0x0154 */
46
+ uint32_t gpio1a_sl; /* Address Offset: 0x0180 */
47
+ uint32_t gpio1b_sl; /* Address Offset: 0x0184 */
48
+ uint32_t gpio1c_sl; /* Address Offset: 0x0188 */
49
+ uint32_t gpio1d_sl; /* Address Offset: 0x018C */
50
+ uint32_t gpio2a_sl; /* Address Offset: 0x0190 */
51
+ uint32_t reserved0194[27]; /* Address Offset: 0x0194 */
52
+ uint32_t gpio1a_ds0; /* Address Offset: 0x0200 */
53
+ uint32_t gpio1a_ds1; /* Address Offset: 0x0204 */
54
+ uint32_t gpio1a_ds2; /* Address Offset: 0x0208 */
55
+ uint32_t gpio1a_ds3; /* Address Offset: 0x020C */
56
+ uint32_t gpio1b_ds0; /* Address Offset: 0x0210 */
57
+ uint32_t gpio1b_ds1; /* Address Offset: 0x0214 */
58
+ uint32_t gpio1b_ds2; /* Address Offset: 0x0218 */
59
+ uint32_t gpio1b_ds3; /* Address Offset: 0x021C */
60
+ uint32_t gpio1c_ds0; /* Address Offset: 0x0220 */
61
+ uint32_t gpio1c_ds1; /* Address Offset: 0x0224 */
62
+ uint32_t gpio1c_ds2; /* Address Offset: 0x0228 */
63
+ uint32_t gpio1c_ds3; /* Address Offset: 0x022C */
64
+ uint32_t gpio1d_ds0; /* Address Offset: 0x0230 */
65
+ uint32_t gpio1d_ds1; /* Address Offset: 0x0234 */
66
+ uint32_t gpio1d_ds2; /* Address Offset: 0x0238 */
67
+ uint32_t gpio1d_ds3; /* Address Offset: 0x023C */
68
+ uint32_t gpio2a_ds0; /* Address Offset: 0x0240 */
69
+ uint32_t reserved0244[47]; /* Address Offset: 0x0244 */
70
+ uint32_t io_vsel0; /* Address Offset: 0x0300 */
71
+ uint32_t reserved0304[63]; /* Address Offset: 0x0304 */
72
+ uint32_t mac1_io_con0; /* Address Offset: 0x0400 */
73
+ uint32_t mac1_io_con1; /* Address Offset: 0x0404 */
74
+ uint32_t reserved0408[62]; /* Address Offset: 0x0408 */
75
+ uint32_t sdcard0_io_con; /* Address Offset: 0x0500 */
76
+ uint32_t jtag_m1_con; /* Address Offset: 0x0504 */
77
+ uint32_t reserved0508[16078]; /* Address Offset: 0x0508 */
78
+ uint32_t gpio3a_iomux_sel_l; /* Address Offset: 0x10040 */
79
+ uint32_t gpio3a_iomux_sel_h; /* Address Offset: 0x10044 */
80
+ uint32_t gpio3b_iomux_sel_l; /* Address Offset: 0x10048 */
81
+ uint32_t gpio3b_iomux_sel_h; /* Address Offset: 0x1004C */
82
+ uint32_t gpio3c_iomux_sel_l; /* Address Offset: 0x10050 */
83
+ uint32_t gpio3c_iomux_sel_h; /* Address Offset: 0x10054 */
84
+ uint32_t gpio3d_iomux_sel_l; /* Address Offset: 0x10058 */
85
+ uint32_t gpio3d_iomux_sel_h; /* Address Offset: 0x1005C */
86
+ uint32_t gpio4a_iomux_sel_l; /* Address Offset: 0x10060 */
87
+ uint32_t gpio4a_iomux_sel_h; /* Address Offset: 0x10064 */
88
+ uint32_t gpio4b_iomux_sel_l; /* Address Offset: 0x10068 */
89
+ uint32_t gpio4b_iomux_sel_h; /* Address Offset: 0x1006C */
90
+ uint32_t reserved10070[12]; /* Address Offset: 0x10070 */
91
+ uint32_t gpio3a_p; /* Address Offset: 0x100A0 */
92
+ uint32_t gpio3b_p; /* Address Offset: 0x100A4 */
93
+ uint32_t gpio3c_p; /* Address Offset: 0x100A8 */
94
+ uint32_t gpio3d_p; /* Address Offset: 0x100AC */
95
+ uint32_t gpio4a_p; /* Address Offset: 0x100B0 */
96
+ uint32_t gpio4b_p; /* Address Offset: 0x100B4 */
97
+ uint32_t reserved100b8[10]; /* Address Offset: 0x100B8 */
98
+ uint32_t gpio3a_ie; /* Address Offset: 0x100E0 */
99
+ uint32_t gpio3b_ie; /* Address Offset: 0x100E4 */
100
+ uint32_t gpio3c_ie; /* Address Offset: 0x100E8 */
101
+ uint32_t gpio3d_ie; /* Address Offset: 0x100EC */
102
+ uint32_t gpio4a_ie; /* Address Offset: 0x100F0 */
103
+ uint32_t gpio4b_ie; /* Address Offset: 0x100F4 */
104
+ uint32_t reserved100f8[10]; /* Address Offset: 0x100F8 */
105
+ uint32_t gpio3a_od; /* Address Offset: 0x10120 */
106
+ uint32_t gpio3b_od; /* Address Offset: 0x10124 */
107
+ uint32_t gpio3c_od; /* Address Offset: 0x10128 */
108
+ uint32_t gpio3d_od; /* Address Offset: 0x1012C */
109
+ uint32_t gpio4a_od; /* Address Offset: 0x10130 */
110
+ uint32_t gpio4b_od; /* Address Offset: 0x10134 */
111
+ uint32_t reserved10138[10]; /* Address Offset: 0x10138 */
112
+ uint32_t gpio3a_sus; /* Address Offset: 0x10160 */
113
+ uint32_t gpio3b_sus; /* Address Offset: 0x10164 */
114
+ uint32_t gpio3c_sus; /* Address Offset: 0x10168 */
115
+ uint32_t gpio3d_sus; /* Address Offset: 0x1016C */
116
+ uint32_t gpio4a_sus; /* Address Offset: 0x10170 */
117
+ uint32_t gpio4b_sus; /* Address Offset: 0x10174 */
118
+ uint32_t reserved10178[10]; /* Address Offset: 0x10178 */
119
+ uint32_t gpio3a_sl; /* Address Offset: 0x101A0 */
120
+ uint32_t gpio3b_sl; /* Address Offset: 0x101A4 */
121
+ uint32_t gpio3c_sl; /* Address Offset: 0x101A8 */
122
+ uint32_t gpio3d_sl; /* Address Offset: 0x101AC */
123
+ uint32_t gpio4a_sl; /* Address Offset: 0x101B0 */
124
+ uint32_t gpio4b_sl; /* Address Offset: 0x101B4 */
125
+ uint32_t reserved101b8[50]; /* Address Offset: 0x101B8 */
126
+ uint32_t gpio3a_ds0; /* Address Offset: 0x10280 */
127
+ uint32_t gpio3a_ds1; /* Address Offset: 0x10284 */
128
+ uint32_t gpio3a_ds2; /* Address Offset: 0x10288 */
129
+ uint32_t gpio3a_ds3; /* Address Offset: 0x1028C */
130
+ uint32_t gpio3b_ds0; /* Address Offset: 0x10290 */
131
+ uint32_t gpio3b_ds1; /* Address Offset: 0x10294 */
132
+ uint32_t gpio3b_ds2; /* Address Offset: 0x10298 */
133
+ uint32_t gpio3b_ds3; /* Address Offset: 0x1029C */
134
+ uint32_t gpio3c_ds0; /* Address Offset: 0x102A0 */
135
+ uint32_t gpio3c_ds1; /* Address Offset: 0x102A4 */
136
+ uint32_t gpio3c_ds2; /* Address Offset: 0x102A8 */
137
+ uint32_t gpio3c_ds3; /* Address Offset: 0x102AC */
138
+ uint32_t gpio3d_ds0; /* Address Offset: 0x102B0 */
139
+ uint32_t gpio3d_ds1; /* Address Offset: 0x102B4 */
140
+ uint32_t gpio3d_ds2; /* Address Offset: 0x102B8 */
141
+ uint32_t gpio3d_ds3; /* Address Offset: 0x102BC */
142
+ uint32_t gpio4a_ds0; /* Address Offset: 0x102C0 */
143
+ uint32_t gpio4a_ds1; /* Address Offset: 0x102C4 */
144
+ uint32_t gpio4a_ds2; /* Address Offset: 0x102C8 */
145
+ uint32_t gpio4a_ds3; /* Address Offset: 0x102CC */
146
+ uint32_t gpio4b_ds0; /* Address Offset: 0x102D0 */
147
+ uint32_t gpio4b_ds1; /* Address Offset: 0x102D4 */
148
+ uint32_t gpio4b_ds2; /* Address Offset: 0x102D8 */
149
+ uint32_t gpio4b_ds3; /* Address Offset: 0x102DC */
150
+ uint32_t reserved102e0[8]; /* Address Offset: 0x102E0 */
151
+ uint32_t io_vsel1; /* Address Offset: 0x10300 */
152
+ uint32_t reserved10304[63]; /* Address Offset: 0x10304 */
153
+ uint32_t mac0_io_con0; /* Address Offset: 0x10400 */
154
+ uint32_t mac0_io_con1; /* Address Offset: 0x10404 */
155
+ uint32_t reserved10408[62]; /* Address Offset: 0x10408 */
156
+ uint32_t vo_io_con; /* Address Offset: 0x10500 */
157
+ uint32_t reserved10504[35]; /* Address Offset: 0x10504 */
158
+ uint32_t saradc1_con; /* Address Offset: 0x10590 */
159
+ uint32_t reserved10594[16027]; /* Address Offset: 0x10594 */
160
+ uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x20000 */
161
+ uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x20004 */
162
+ uint32_t gpio0b_iomux_sel_l; /* Address Offset: 0x20008 */
163
+ uint32_t gpio0b_iomux_sel_h; /* Address Offset: 0x2000C */
164
+ uint32_t gpio0c_iomux_sel_l; /* Address Offset: 0x20010 */
165
+ uint32_t gpio0c_iomux_sel_h; /* Address Offset: 0x20014 */
166
+ uint32_t gpio0d_iomux_sel_l; /* Address Offset: 0x20018 */
167
+ uint32_t reserved2001c; /* Address Offset: 0x2001C */
168
+ uint32_t gpio0a_p; /* Address Offset: 0x20020 */
169
+ uint32_t gpio0b_p; /* Address Offset: 0x20024 */
170
+ uint32_t gpio0c_p; /* Address Offset: 0x20028 */
171
+ uint32_t gpio0d_p; /* Address Offset: 0x2002C */
172
+ uint32_t gpio0a_ie; /* Address Offset: 0x20030 */
173
+ uint32_t gpio0b_ie; /* Address Offset: 0x20034 */
174
+ uint32_t gpio0c_ie; /* Address Offset: 0x20038 */
175
+ uint32_t gpio0d_ie; /* Address Offset: 0x2003C */
176
+ uint32_t gpio0a_od; /* Address Offset: 0x20040 */
177
+ uint32_t gpio0b_od; /* Address Offset: 0x20044 */
178
+ uint32_t gpio0c_od; /* Address Offset: 0x20048 */
179
+ uint32_t gpio0d_od; /* Address Offset: 0x2004C */
180
+ uint32_t gpio0a_sus; /* Address Offset: 0x20050 */
181
+ uint32_t gpio0b_sus; /* Address Offset: 0x20054 */
182
+ uint32_t gpio0c_sus; /* Address Offset: 0x20058 */
183
+ uint32_t gpio0d_sus; /* Address Offset: 0x2005C */
184
+ uint32_t gpio0a_sl; /* Address Offset: 0x20060 */
185
+ uint32_t gpio0b_sl; /* Address Offset: 0x20064 */
186
+ uint32_t gpio0c_sl; /* Address Offset: 0x20068 */
187
+ uint32_t gpio0d_sl; /* Address Offset: 0x2006C */
188
+ uint32_t gpio0a_ds0; /* Address Offset: 0x20070 */
189
+ uint32_t gpio0a_ds1; /* Address Offset: 0x20074 */
190
+ uint32_t gpio0a_ds2; /* Address Offset: 0x20078 */
191
+ uint32_t gpio0a_ds3; /* Address Offset: 0x2007C */
192
+ uint32_t gpio0b_ds0; /* Address Offset: 0x20080 */
193
+ uint32_t gpio0b_ds1; /* Address Offset: 0x20084 */
194
+ uint32_t gpio0b_ds2; /* Address Offset: 0x20088 */
195
+ uint32_t gpio0b_ds3; /* Address Offset: 0x2008C */
196
+ uint32_t gpio0c_ds0; /* Address Offset: 0x20090 */
197
+ uint32_t gpio0c_ds1; /* Address Offset: 0x20094 */
198
+ uint32_t gpio0c_ds2; /* Address Offset: 0x20098 */
199
+ uint32_t gpio0c_ds3; /* Address Offset: 0x2009C */
200
+ uint32_t gpio0d_ds0; /* Address Offset: 0x200A0 */
201
+ uint32_t reserved200a4[23]; /* Address Offset: 0x200A4 */
202
+ uint32_t jtag_m0_con; /* Address Offset: 0x20100 */
203
+ uint32_t uart_io_con; /* Address Offset: 0x20104 */
204
+ uint32_t reserved20108[16]; /* Address Offset: 0x20108 */
205
+ uint32_t io_vsel2; /* Address Offset: 0x20148 */
206
+ uint32_t xin_con; /* Address Offset: 0x2014C */
207
+};
208
+check_member(rk3562_ioc, xin_con, 0x2014c);
209
+
210
+#endif
211
+
u-boot/arch/arm/include/asm/arch-rockchip/pcie_ep_boot.h
....@@ -0,0 +1,11 @@
1
+/* SPDX-License-Identifier: GPL-2.0+ */
2
+/*
3
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd
4
+ */
5
+
6
+#ifndef __ASM_PCIE_EP_BOOT_H
7
+#define __ASM_PCIE_EP_BOOT_H
8
+
9
+void rockchip_pcie_ep_init(void);
10
+void rockchip_pcie_ep_get_firmware(void);
11
+#endif
u-boot/arch/arm/include/asm/arch-rockchip/resource_img.h
....@@ -11,55 +11,42 @@
1111
1212 #define MAX_FILE_NAME_LEN 220
1313 #define MAX_HASH_LEN 32
14
-#define ROOT_COMPAT_PROP_OFFSET 0x4c /* Property: "/compatible" */
1514 #define DTB_SUFFIX ".dtb"
1615
1716 struct resource_file {
1817 char name[MAX_FILE_NAME_LEN];
18
+ uint32_t blk_start;
19
+ uint32_t blk_offset;
1920 char hash[MAX_HASH_LEN];
2021 uint32_t hash_size;
21
- uint32_t f_offset; /* Sector offset */
22
- uint32_t f_size; /* Bytes */
22
+ uint32_t size; /* in byte */
23
+ bool in_ram;
2324 struct list_head link;
24
- struct list_head dtbs;
25
- /* Sector base of resource when ram=false, byte base when ram=true */
26
- uint32_t rsce_base;
27
- bool ram;
2825 };
2926
30
-extern struct list_head entrys_head;
31
-extern struct list_head entrys_dtbs_head;
27
+extern struct list_head entry_head;
3228
3329 /*
34
- * resource_image_check_header - check resource image header
30
+ * resource_setup_ram_list() - setup resource file list by given resource image.
3531 *
36
- * @rsce_hdr: resource file hdr
32
+ * @dev_desc: boot device
33
+ * @hdr: resource file hdr
3734 *
38
- * return 0 on header okay, otherwise failed
35
+ * return 0 on success, otherwise fail.
3936 */
40
-int resource_image_check_header(void *rsce_hdr);
37
+int resource_setup_ram_list(struct blk_desc *dev_desc, void *hdr);
4138
4239 /*
43
- * resource_create_ram_list - create resource file list by data from memory
44
- *
45
- * @dev_desc: blk dev descritpion
46
- * @rsce_hdr: resource file hdr
47
- *
48
- * return 0 on header okay, otherwise failed
49
- */
50
-int resource_create_ram_list(struct blk_desc *dev_desc, void *rsce_hdr);
51
-
52
-/*
53
- * rockchip_read_resource_file - read file from resource partition
40
+ * rockchip_read_resource_file() - read file from resource.
5441 *
5542 * @buf: destination buf to store file data
5643 * @name: file name
57
- * @offset: blocks offset in the file, 1 block = 512 bytes
58
- * @len: the size(by bytes) of file to read.
44
+ * @blk_offset: blocks offset in the file, 1 block = 512 bytes
45
+ * @len: the size(by bytes) of file to read
5946 *
60
- * return negative num on failed, otherwise the file size
47
+ * return the length of read data.
6148 */
62
-int rockchip_read_resource_file(void *buf, const char *name, int offset, int len);
49
+int rockchip_read_resource_file(void *buf, const char *name, int blk_offset, int len);
6350
6451 /*
6552 * rockchip_read_resource_dtb() - read dtb file
....@@ -69,43 +56,5 @@
6956 * @hash_size: hash value length
7057 */
7158 int rockchip_read_resource_dtb(void *fdt_addr, char **hash, int *hash_size);
72
-
73
-/*
74
- * resource_init_list - init resource list of android image from storage
75
- */
76
-int resource_init_list(void);
77
-
78
-/*
79
- * resource_replace_entry - replace resource entry, override if find exist one
80
- */
81
-int resource_replace_entry(const char *f_name, uint32_t base,
82
- uint32_t f_offset, uint32_t f_size);
83
-
84
-/*
85
- * resource_read_logo_bmps() - read logo bmp from "logo" partition
86
- */
87
-int resource_read_logo_bmps(void);
88
-
89
-/*
90
- * resource_read_hwid_dtb() - read hwid dtb
91
- */
92
-struct resource_file *resource_read_hwid_dtb(void);
93
-
94
-/*
95
- * resource_is_empty() - return if resource is empty
96
- */
97
-int resource_is_empty(void);
98
-
99
-/*
100
- * resource_traverse_init_list() - traverse all image(android/fit/uimage)
101
- */
102
-int resource_traverse_init_list(void);
103
-
104
-/*
105
- * board_resource_dtb_accepted() - check if this dtb is accepted
106
- *
107
- * return 0 if not accepted, otherwise accepted.
108
- */
109
-int board_resource_dtb_accepted(char *dtb_name);
11059
11160 #endif
u-boot/arch/arm/include/asm/arch-rockchip/rk_meta.h
....@@ -64,7 +64,7 @@
6464 #define ITEM_SIZE (1 * 1024)
6565 #define MAX_CMDLINE_LENGTH (1024 / 2)
6666 #define MAX_HEAD_SIZE 4
67
-#define MAX_META_SEGMENT_SIZE (16 * 1024)
67
+#define MAX_META_SEGMENT_SIZE (64 * 1024)
6868 #define BACKUP_META_SIZE (MAX_META_SEGMENT_SIZE / 2)
6969 #define META_INFO_HEAD_OFFSET 0
7070 #define META_INFO_SIZE ITEM_SIZE
....@@ -80,13 +80,17 @@
8080 #define APP_PARAM_OFFSET (AE_TABLE_OFFSET + AE_TABLE_MAX_SIZE)
8181 #define APP_PARAM_MAX_SIZE ITEM_SIZE
8282
83
+#define SECONDARY_SENSOR_INIT_OFFSET (APP_PARAM_OFFSET + APP_PARAM_MAX_SIZE)
84
+#define SECONDARY_SENSOR_INIT_MAX_SIZE ITEM_SIZE
85
+
8386 #define SENSOR_IQ_BIN_OFFSET (MAX_META_SEGMENT_SIZE)
8487 #define SENSOR_IQ_BIN_MAX_SIZE (320 * 1024)
85
-#define MAX_META_BIN_SIZE (MAX_META_SEGMENT_SIZE + SENSOR_IQ_BIN_MAX_SIZE)
86
-#define META_SIZE MAX_META_BIN_SIZE
8788
88
-/* 512 - sizeof(tag/load/size/comp_type/comp_size/comp_off/crc32/meta_flags) */
89
-#define META_HEAD_RESERVED_SIZE (120*4)
89
+#define SECONDARY_SENSOR_IQ_BIN_OFFSET (SENSOR_IQ_BIN_OFFSET + SENSOR_IQ_BIN_MAX_SIZE)
90
+#define SECONDARY_SENSOR_IQ_BIN_MAX_SIZE (SENSOR_IQ_BIN_MAX_SIZE)
91
+
92
+/* 512 - sizeof(tag/load/size/comp_type/comp_size/comp_off/crc32/meta_flags/iq_item_size) */
93
+#define META_HEAD_RESERVED_SIZE (119*4)
9094 #define META_READ_DONE_FLAG (1 << 0)
9195
9296 #define AE_TABLE_SHARE2KERNEL_OFFSET (PARAM_SHARE2KERNEL_OFFSET)
....@@ -100,6 +104,7 @@
100104 uint32_t comp_type;
101105 uint32_t comp_size;
102106 uint32_t comp_off;
107
+ uint32_t iq_item_size;
103108 uint8_t reserved[META_HEAD_RESERVED_SIZE];
104109 uint32_t crc32;
105110 uint32_t meta_flags;
u-boot/arch/arm/include/asm/arch-rockchip/rockchip_smccc.h
....@@ -29,6 +29,7 @@
2929 #define SIP_LAST_LOG 0x8200000e
3030 #define SIP_AMP_CFG 0x82000022
3131 #define SIP_HDCP_CONFIG 0x82000025
32
+#define SIP_MCU_CFG 0x82000028
3233
3334 #define ROCKCHIP_SIP_CONFIG_DRAM_INIT 0x00
3435 #define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE 0x01
....@@ -46,6 +47,19 @@
4647 #define ROCKCHIP_SIP_CONFIG_DRAM_ECC 0x0d
4748 #define ROCKCHIP_SIP_CONFIG_DRAM_GET_FREQ_INFO 0x0e
4849 #define ROCKCHIP_SIP_CONFIG_DRAM_FSP_INIT 0x0f
50
+
51
+/* RK_SIP_MCU_CFG child configs, MCU ID */
52
+#define ROCKCHIP_SIP_CONFIG_BUSMCU_0_ID 0x00
53
+#define ROCKCHIP_SIP_CONFIG_BUSMCU_1_ID 0x01
54
+#define ROCKCHIP_SIP_CONFIG_PMUMCU_0_ID 0x10
55
+#define ROCKCHIP_SIP_CONFIG_DDRMCU_0_ID 0x20
56
+#define ROCKCHIP_SIP_CONFIG_NPUMCU_0_ID 0x30
57
+
58
+/* RK_SIP_MCU_CFG child configs */
59
+#define ROCKCHIP_SIP_CONFIG_MCU_CODE_START_ADDR 0x01
60
+#define ROCKCHIP_SIP_CONFIG_MCU_EXPERI_START_ADDR 0x02
61
+#define ROCKCHIP_SIP_CONFIG_MCU_SRAM_START_ADDR 0x03
62
+#define ROCKCHIP_SIP_CONFIG_MCU_EXSRAM_START_ADDR 0x04
4963
5064 /* Rockchip Sip version */
5165 #define SIP_IMPLEMENT_V1 (1)
....@@ -100,6 +114,8 @@
100114 int sip_smc_set_suspend_mode(unsigned long ctrl,
101115 unsigned long config1,
102116 unsigned long config2);
117
+
118
+int sip_smc_remotectl_config(unsigned long func, unsigned long data);
103119
104120 /*
105121 * sip_smc_amp_cfg() - config AMP
....@@ -172,6 +188,13 @@
172188 unsigned long arg1, unsigned long arg2);
173189
174190 /*
191
+ * sip_smc_mcu_config() - handle mcu.
192
+ *
193
+ * @return 0 on success, otherwise failed.
194
+ */
195
+int sip_smc_mcu_config(unsigned long mcu_id, unsigned long func, unsigned long arg2);
196
+
197
+/*
175198 * psci_cpu_on() - Standard ARM PSCI cpu on call.
176199 *
177200 * @cpuid: cpu id
u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3528.h
....@@ -0,0 +1,12 @@
1
+/* SPDX-License-Identifier: GPL-2.0+ */
2
+/*
3
+ * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
4
+ */
5
+
6
+#ifndef _ASM_ARCH_SDRAM_RK3528_H
7
+#define _ASM_ARCH_SDRAM_RK3528_H
8
+
9
+#include <asm/arch-rockchip/sdram.h>
10
+#include <asm/arch-rockchip/sdram_common.h>
11
+
12
+#endif /* _ASM_ARCH_SDRAM_RK3528_H */
u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3562.h
....@@ -0,0 +1,12 @@
1
+/* SPDX-License-Identifier: GPL-2.0+ */
2
+/*
3
+ * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
4
+ */
5
+
6
+#ifndef _ASM_ARCH_SDRAM_RK3562_H
7
+#define _ASM_ARCH_SDRAM_RK3562_H
8
+
9
+#include <asm/arch-rockchip/sdram.h>
10
+#include <asm/arch-rockchip/sdram_common.h>
11
+
12
+#endif /* _ASM_ARCH_SDRAM_RK3562_H */
u-boot/arch/arm/include/asm/arch-rockchip/uimage.h
....@@ -12,7 +12,6 @@
1212 void *uimage_load_bootables(void);
1313 int uimage_sysmem_free_each(image_header_t *img, u32 ramdisk_sz);
1414 int uimage_sysmem_reserve_each(image_header_t *hdr, u32 *ramdisk_sz);
15
-int uimage_init_resource(void);
16
-
15
+int uimage_init_resource(struct blk_desc *dev_desc);
1716 #endif
1817
u-boot/arch/arm/include/asm/arch-rockchip/vendor.h
....@@ -46,4 +46,7 @@
4646 void *p_data));
4747
4848 int vendor_handle_hdcp(struct vendor_item *vhead);
49
+
50
+void vendor_storage_fixup(void *blob);
51
+
4952 #endif /* _ROCKCHIP_VENDOR_ */
u-boot/arch/arm/include/asm/system.h
....@@ -257,6 +257,7 @@
257257 void wait_for_wakeup(void);
258258 void protect_secure_region(void);
259259 void smp_kick_all_cpus(void);
260
+void smp_entry(u32 cpu);
260261
261262 void flush_l3_cache(void);
262263 void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
u-boot/arch/arm/lib/bootm-fdt.c
....@@ -46,6 +46,9 @@
4646 if (ret)
4747 return ret;
4848
49
+ /* Show "/reserved-memory" */
50
+ boot_mem_rsv_regions(NULL, blob);
51
+
4952 #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_OF_LIBFDT)
5053 bd_t *bd = gd->bd;
5154 int bank;
u-boot/arch/arm/lib/bootm.c
....@@ -22,6 +22,7 @@
2222 #include <asm/byteorder.h>
2323 #include <linux/libfdt.h>
2424 #include <mapmem.h>
25
+#include <mp_boot.h>
2526 #include <fdt_support.h>
2627 #include <asm/bootm.h>
2728 #include <asm/secure.h>
....@@ -80,7 +81,7 @@
8081 */
8182 static void announce_and_cleanup(bootm_headers_t *images, int fake)
8283 {
83
- ulong us;
84
+ ulong us, tt_us;
8485
8586 bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
8687 #ifdef CONFIG_BOOTSTAGE_FDT
....@@ -108,8 +109,12 @@
108109
109110 cleanup_before_linux();
110111
112
+#ifdef CONFIG_MP_BOOT
113
+ mpb_post(4);
114
+#endif
111115 us = (get_ticks() - gd->sys_start_tick) / (COUNTER_FREQUENCY / 1000000);
112
- printf("Total: %ld.%ld ms\n", us / 1000, us % 1000);
116
+ tt_us = get_ticks() / (COUNTER_FREQUENCY / 1000000);
117
+ printf("Total: %ld.%ld/%ld.%ld ms\n", us / 1000, us % 1000, tt_us / 1000, tt_us % 1000);
113118
114119 printf("\nStarting kernel ...%s\n\n", fake ?
115120 "(fake run for tracing)" : "");
u-boot/arch/arm/lib/crt0_64.S
....@@ -66,42 +66,6 @@
6666 */
6767
6868 ENTRY(_main)
69
- /*
70
- * Enable instruction cache (if required), stack pointer,
71
- * data access alignment checks and SError.
72
- */
73
-#ifdef CONFIG_SPL_BUILD
74
- mov x1, #CR_I
75
-#else
76
- mov x1, #0
77
-#endif
78
- switch_el x2, 3f, 2f, 1f
79
-3: mrs x0, sctlr_el3
80
- orr x0, x0, x1
81
- msr sctlr_el3, x0
82
-#ifndef CONFIG_SUPPORT_USBPLUG
83
- msr daifclr, #4 /* Enable SError. SCR_EL3.EA=1 was already set in start.S */
84
-#endif
85
- b 0f
86
-2: mrs x0, sctlr_el2
87
- orr x0, x0, x1
88
- msr sctlr_el2, x0
89
-
90
- mrs x0, hcr_el2
91
- orr x0, x0, #HCR_EL2_TGE
92
- orr x0, x0, #HCR_EL2_AMO
93
-#if CONFIG_IS_ENABLED(IRQ)
94
- orr x0, x0, #HCR_EL2_IMO
95
-#endif
96
- msr hcr_el2, x0
97
- msr daifclr, #4
98
- b 0f
99
-1: mrs x0, sctlr_el1
100
- orr x0, x0, x1
101
- msr sctlr_el1, x0
102
- msr daifclr, #4
103
-0:
104
- isb
10569
10670 /*
10771 * Set up initial C runtime environment and call board_init_f(0).
u-boot/arch/arm/mach-rockchip/Kconfig
....@@ -381,6 +381,61 @@
381381
382382 endif
383383
384
+config ROCKCHIP_RK3528
385
+ bool "Support Rockchip RK3528"
386
+ select ARM64 if !ARM64_BOOT_AARCH32
387
+ select GICV2 if !ARM64_BOOT_AARCH32
388
+ select SUPPORT_TPL if !ARM64_BOOT_AARCH32
389
+ select SUPPORT_SPL if !ARM64_BOOT_AARCH32
390
+ select TPL_TINY_FRAMEWORK if TPL
391
+ select DEBUG_UART_BOARD_INIT
392
+ imply TPL if !ARM64_BOOT_AARCH32
393
+ imply SPL if !ARM64_BOOT_AARCH32
394
+ imply TPL_SERIAL_SUPPORT
395
+ help
396
+ The Rockchip RK3528 is a ARM-based SoC with a quad-core Cortex-A53.
397
+
398
+if ROCKCHIP_RK3528
399
+
400
+config TPL_LDSCRIPT
401
+ default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
402
+
403
+config TPL_TEXT_BASE
404
+ default 0xfe481000
405
+
406
+config TPL_MAX_SIZE
407
+ default 61440
408
+
409
+endif
410
+
411
+config ROCKCHIP_RK3562
412
+ bool "Support Rockchip RK3562"
413
+ select GICV2
414
+ select ARM64
415
+ select ARM_SMCCC
416
+ select SUPPORT_TPL
417
+ select SUPPORT_SPL
418
+ select TPL_TINY_FRAMEWORK if TPL
419
+ select DEBUG_UART_BOARD_INIT
420
+ imply TPL
421
+ imply SPL
422
+ imply TPL_SERIAL_SUPPORT
423
+ help
424
+ The Rockchip RK3562 is a ARM-based SoC with a quad-core Cortex-A53.
425
+
426
+if ROCKCHIP_RK3562
427
+
428
+config TPL_LDSCRIPT
429
+ default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
430
+
431
+config TPL_TEXT_BASE
432
+ default 0xfe481000
433
+
434
+config TPL_MAX_SIZE
435
+ default 61440
436
+
437
+endif
438
+
384439 config ROCKCHIP_RK3568
385440 bool "Support Rockchip RK3568"
386441 select ARM64 if !ARM64_BOOT_AARCH32
....@@ -597,6 +652,8 @@
597652 default 0xff1005c8 if ROCKCHIP_RK3328
598653 default 0xff738200 if ROCKCHIP_RK3368
599654 default 0xff320300 if ROCKCHIP_RK3399
655
+ default 0xff370200 if ROCKCHIP_RK3528
656
+ default 0xff010220 if ROCKCHIP_RK3562
600657 default 0xfdc20200 if ROCKCHIP_RK3568
601658 default 0xfd588080 if ROCKCHIP_RK3588
602659 default 0xfe020200 if ROCKCHIP_RK1808
....@@ -622,6 +679,8 @@
622679 default 0xff1d0020 if ROCKCHIP_RK3328
623680 default 0xff830020 if ROCKCHIP_RK3368
624681 default 0xff8680a0 if ROCKCHIP_RK3399
682
+ default 0xff620000 if ROCKCHIP_RK3528
683
+ default 0xffa90020 if ROCKCHIP_RK3562
625684 default 0xfdd1c020 if ROCKCHIP_RK3568
626685 default 0xfd8c8000 if ROCKCHIP_RK3588
627686 default 0xff590020 if ROCKCHIP_RV1106
....@@ -644,6 +703,8 @@
644703 default 0xff091000 if ROCKCHIP_RK3328
645704 default 0xff8c0000 if ROCKCHIP_RK3368
646705 default 0xff8c0000 if ROCKCHIP_RK3399
706
+ default 0xfe480000 if ROCKCHIP_RK3528
707
+ default 0xfe480000 if ROCKCHIP_RK3562
647708 default 0xfdcc0000 if ROCKCHIP_RK3568
648709 default 0xff000000 if ROCKCHIP_RK3588
649710 default 0xff6c0000 if ROCKCHIP_RV1106
....@@ -813,16 +874,22 @@
813874 - U-Boot: only some necessary U-Boot devices(storage, crypto...) in dm tree.
814875 - kernel: all the devices(except the U-Boot only) in dm tree.
815876
877
+config EMBED_KERNEL_DTB
878
+ bool "Enable embedded dtb support"
879
+ default n
880
+ help
881
+ Enable embedded dtb support.
882
+
816883 config EMBED_KERNEL_DTB_PATH
817
- string "Embeded kernel dtb file path"
818
- depends on USING_KERNEL_DTB
884
+ string "Embedded kernel dtb file path"
885
+ depends on EMBED_KERNEL_DTB && USING_KERNEL_DTB
819886 default "dts/kern.dtb"
820887 help
821888 This file will auto be appended to the u-boot.bin.
822889
823890 config EMBED_KERNEL_DTB_ALWAYS
824
- bool "Always using embed kernel dtb"
825
- depends on USING_KERNEL_DTB
891
+ bool "Always using embedded kernel dtb"
892
+ depends on EMBED_KERNEL_DTB && USING_KERNEL_DTB
826893 default n
827894 help
828895 Allow fallback to always use a prepared kernel dtb even USING_KERNEL_DTB
....@@ -914,6 +981,16 @@
914981 default y
915982 help
916983 Define a lot of hotkeys for debug.
984
+
985
+config ROCKCHIP_CMD
986
+ string "Rockchip specific command"
987
+ default ""
988
+ help
989
+ It defines a command to be run when the key is pressed if assigned.
990
+ String format: "cmd key".
991
+ @cmd: any U-Boot cmd.
992
+ @key: any key map id, '-' standard for ignore.
993
+ e.g. "sd_update 115", 115 is KEY_VOLUMEUP.
917994
918995 config GICV2
919996 bool "ARM GICv2"
....@@ -1013,14 +1090,16 @@
10131090 default 0x0
10141091 depends on PSTORE
10151092 help
1016
- This select linux pstore buffer address for uboot.
1093
+ This select linux pstore buffer address for U-Boot. When value is
1094
+ 0, U-Boot auto gets this address from preloader atags.
10171095
10181096 config PERSISTENT_RAM_SIZE
10191097 hex "Linux pstore buffer size"
10201098 default 0x0
1021
- depends on PSTORE
1099
+ depends on (PERSISTENT_RAM_ADDR != 0)
10221100 help
1023
- This select linux pstore buffer size for uboot.
1101
+ This select linux pstore buffer size for U-Boot, the value must be
1102
+ set if PERSISTENT_RAM_ADDR != 0.
10241103
10251104 source "arch/arm/mach-rockchip/px30/Kconfig"
10261105 source "arch/arm/mach-rockchip/rk3036/Kconfig"
....@@ -1033,6 +1112,8 @@
10331112 source "arch/arm/mach-rockchip/rk3328/Kconfig"
10341113 source "arch/arm/mach-rockchip/rk3368/Kconfig"
10351114 source "arch/arm/mach-rockchip/rk3399/Kconfig"
1115
+source "arch/arm/mach-rockchip/rk3528/Kconfig"
1116
+source "arch/arm/mach-rockchip/rk3562/Kconfig"
10361117 source "arch/arm/mach-rockchip/rk3568/Kconfig"
10371118 source "arch/arm/mach-rockchip/rk3588/Kconfig"
10381119 source "arch/arm/mach-rockchip/rk1808/Kconfig"
u-boot/arch/arm/mach-rockchip/Makefile
....@@ -49,7 +49,7 @@
4949 obj-$(CONFIG_ROCKCHIP_UIMAGE) += uimage.o
5050 obj-$(CONFIG_ROCKCHIP_SMCCC) += rockchip_smccc.o
5151 obj-$(CONFIG_ROCKCHIP_VENDOR_PARTITION) += vendor.o vendor_misc.o
52
-obj-$(CONFIG_ROCKCHIP_RESOURCE_IMAGE) += resource_img.o resource_logo.o
52
+obj-$(CONFIG_ROCKCHIP_RESOURCE_IMAGE) += resource_img.o
5353 obj-$(CONFIG_ROCKCHIP_HWID_DTB) += resource_hwid.o
5454 obj-$(CONFIG_ROCKCHIP_DEBUGGER) += rockchip_debugger.o
5555 endif
....@@ -58,6 +58,7 @@
5858 obj-$(CONFIG_RAM) += param.o
5959 obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o
6060 obj-$(CONFIG_SPL_KERNEL_BOOT) += spl_resource_img.o
61
+obj-$(CONFIG_SPL_PCIE_EP_SUPPORT) += spl_pcie_ep_boot.o
6162
6263 obj-$(CONFIG_ROCKCHIP_PX30) += px30/
6364 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
....@@ -72,6 +73,8 @@
7273 obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
7374 obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
7475 obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
76
+obj-$(CONFIG_ROCKCHIP_RK3528) += rk3528/
77
+obj-$(CONFIG_ROCKCHIP_RK3562) += rk3562/
7578 obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
7679 obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
7780 obj-$(CONFIG_ROCKCHIP_RK1808) += rk1808/
u-boot/arch/arm/mach-rockchip/board.c
....@@ -56,6 +56,10 @@
5656
5757 DECLARE_GLOBAL_DATA_PTR;
5858
59
+#ifdef CONFIG_ARM64
60
+static ulong orig_images_ep;
61
+#endif
62
+
5963 __weak int rk_board_late_init(void)
6064 {
6165 return 0;
....@@ -246,30 +250,48 @@
246250 static int boot_from_udisk(void)
247251 {
248252 struct blk_desc *desc;
249
- char *devtype;
250
- char *devnum;
251
-
252
- devtype = env_get("devtype");
253
- devnum = env_get("devnum");
253
+ struct udevice *dev;
254
+ int devnum = -1;
255
+ char buf[32];
254256
255257 /* Booting priority: mmc1 > udisk */
256
- if (!strcmp(devtype, "mmc") && !strcmp(devnum, "1"))
258
+ if (!strcmp(env_get("devtype"), "mmc") && !strcmp(env_get("devnum"), "1"))
257259 return 0;
258260
259261 if (!run_command("usb start", -1)) {
260
- desc = blk_get_devnum_by_type(IF_TYPE_USB, 0);
261
- if (!desc) {
262
- printf("No usb device found\n");
262
+ for (blk_first_device(IF_TYPE_USB, &dev);
263
+ dev;
264
+ blk_next_device(&dev)) {
265
+ desc = dev_get_uclass_platdata(dev);
266
+ printf("Scanning usb %d ...\n", desc->devnum);
267
+ if (desc->type == DEV_TYPE_UNKNOWN)
268
+ continue;
269
+
270
+ if (desc->lba > 0L && desc->blksz > 0L) {
271
+ devnum = desc->devnum;
272
+ break;
273
+ }
274
+ }
275
+ if (devnum < 0) {
276
+ printf("No usb mass storage found\n");
263277 return -ENODEV;
264278 }
265279
266
- if (!run_command("rkimgtest usb 0", -1)) {
280
+ desc = blk_get_devnum_by_type(IF_TYPE_USB, devnum);
281
+ if (!desc) {
282
+ printf("No usb %d found\n", devnum);
283
+ return -ENODEV;
284
+ }
285
+
286
+ snprintf(buf, 32, "rkimgtest usb %d", devnum);
287
+ if (!run_command(buf, -1)) {
288
+ snprintf(buf, 32, "%d", devnum);
267289 rockchip_set_bootdev(desc);
268290 env_set("devtype", "usb");
269
- env_set("devnum", "0");
270
- printf("Boot from usb 0\n");
291
+ env_set("devnum", buf);
292
+ printf("=== Booting from usb %d ===\n", devnum);
271293 } else {
272
- printf("No usb dev 0 found\n");
294
+ printf("No available udisk image on usb %d\n", devnum);
273295 return -ENODEV;
274296 }
275297 }
....@@ -358,6 +380,8 @@
358380 static void cmdline_handle(void)
359381 {
360382 struct blk_desc *dev_desc;
383
+ int if_type;
384
+ int devnum;
361385
362386 param_parse_pubkey_fuse_programmed();
363387
....@@ -373,19 +397,51 @@
373397 * rockchip_get_boot_mode() actually only read once,
374398 * we need to update boot mode according to udisk BCB.
375399 */
376
- if ((dev_desc->if_type == IF_TYPE_MMC && dev_desc->devnum == 1) ||
377
- (dev_desc->if_type == IF_TYPE_USB && dev_desc->devnum == 0)) {
400
+ if_type = dev_desc->if_type;
401
+ devnum = dev_desc->devnum;
402
+ if ((if_type == IF_TYPE_MMC && devnum == 1) || (if_type == IF_TYPE_USB)) {
378403 if (get_bcb_recovery_msg() == BCB_MSG_RECOVERY_RK_FWUPDATE) {
379
- if (dev_desc->if_type == IF_TYPE_MMC && dev_desc->devnum == 1) {
404
+ if (if_type == IF_TYPE_MMC && devnum == 1) {
380405 env_update("bootargs", "sdfwupdate");
381
- } else if (dev_desc->if_type == IF_TYPE_USB && dev_desc->devnum == 0) {
406
+ } else if (if_type == IF_TYPE_USB) {
382407 env_update("bootargs", "usbfwupdate");
383408 env_set("reboot_mode", "recovery-usb");
384409 }
385410 } else {
386
- if (dev_desc->if_type == IF_TYPE_USB && dev_desc->devnum == 0)
411
+ if (if_type == IF_TYPE_USB)
387412 env_set("reboot_mode", "normal");
388413 }
414
+ }
415
+
416
+ if (rockchip_get_boot_mode() == BOOT_MODE_QUIESCENT)
417
+ env_update("bootargs", "androidboot.quiescent=1 pwm_bl.quiescent=1");
418
+}
419
+
420
+static void scan_run_cmd(void)
421
+{
422
+ char *config = CONFIG_ROCKCHIP_CMD;
423
+ char *cmd, *key;
424
+
425
+ key = strchr(config, ' ');
426
+ if (!key)
427
+ return;
428
+
429
+ cmd = strdup(config);
430
+ cmd[key - config] = 0;
431
+ key++;
432
+
433
+ if (!strcmp(key, "-")) {
434
+ run_command(cmd, 0);
435
+ } else {
436
+#ifdef CONFIG_DM_KEY
437
+ ulong map;
438
+
439
+ map = simple_strtoul(key, NULL, 10);
440
+ if (key_is_pressed(key_read(map))) {
441
+ printf("## Key<%ld> pressed... run cmd '%s'\n", map, cmd);
442
+ run_command(cmd, 0);
443
+ }
444
+#endif
389445 }
390446 }
391447
....@@ -398,7 +454,7 @@
398454 rockchip_set_serialno();
399455 #endif
400456 setup_download_mode();
401
-
457
+ scan_run_cmd();
402458 #ifdef CONFIG_ROCKCHIP_USB_BOOT
403459 boot_from_udisk();
404460 #endif
....@@ -406,7 +462,8 @@
406462 charge_display();
407463 #endif
408464 #ifdef CONFIG_DRM_ROCKCHIP
409
- rockchip_show_logo();
465
+ if (rockchip_get_boot_mode() != BOOT_MODE_QUIESCENT)
466
+ rockchip_show_logo();
410467 #endif
411468 #ifdef CONFIG_ROCKCHIP_EINK_DISPLAY
412469 rockchip_eink_show_uboot_logo();
....@@ -458,57 +515,31 @@
458515 printf("Cmd interface: disabled\n");
459516 }
460517
461
-#if defined(CONFIG_MTD_BLK) && defined(CONFIG_USING_KERNEL_DTB)
462
-static void board_mtd_blk_map_partitions(void)
463
-{
464
- struct blk_desc *dev_desc;
465
-
466
- dev_desc = rockchip_get_bootdev();
467
- if (dev_desc)
468
- mtd_blk_map_partitions(dev_desc);
469
-}
470
-#endif
471
-
472518 int board_init(void)
473519 {
474520 board_debug_init();
475
- /* optee select security level */
476
-#ifdef CONFIG_OPTEE_CLIENT
477
- trusty_select_security_level();
478
-#endif
479
-
480521 #ifdef DEBUG
481522 soc_clk_dump();
482523 #endif
483
-
484
-#ifdef CONFIG_USING_KERNEL_DTB
485
-#ifdef CONFIG_MTD_BLK
486
- board_mtd_blk_map_partitions();
524
+#ifdef CONFIG_OPTEE_CLIENT
525
+ trusty_select_security_level();
487526 #endif
527
+#ifdef CONFIG_USING_KERNEL_DTB
488528 init_kernel_dtb();
489529 #endif
490530 early_download();
491531
492
- /*
493
- * pmucru isn't referenced on some platforms, so pmucru driver can't
494
- * probe that the "assigned-clocks" is unused.
495
- */
496532 clks_probe();
497533 #ifdef CONFIG_DM_REGULATOR
498
- if (regulators_enable_boot_on(is_hotkey(HK_REGULATOR)))
499
- debug("%s: Can't enable boot on regulator\n", __func__);
534
+ regulators_enable_boot_on(is_hotkey(HK_REGULATOR));
500535 #endif
501
-
502536 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN
503537 io_domain_init();
504538 #endif
505
-
506539 set_armclk_rate();
507
-
508540 #ifdef CONFIG_DM_DVFS
509541 dvfs_init(true);
510542 #endif
511
-
512543 #ifdef CONFIG_ANDROID_AB
513544 if (ab_decrease_tries())
514545 printf("Decrease ab tries count fail!\n");
....@@ -537,6 +568,10 @@
537568 /* Common fixup for DRM */
538569 #ifdef CONFIG_DRM_ROCKCHIP
539570 rockchip_display_fixup(blob);
571
+#endif
572
+
573
+#ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
574
+ vendor_storage_fixup(blob);
540575 #endif
541576
542577 return rk_board_fdt_fixup(blob);
....@@ -603,6 +638,9 @@
603638 * But relocation is in board_quiesce_devices() until all decompress
604639 * done, mainly for saving boot time.
605640 */
641
+
642
+ orig_images_ep = images->ep;
643
+
606644 if (data[10] == 0x00) {
607645 if (round_down(images->ep, SZ_2M) != images->ep)
608646 images->ep = round_down(images->ep, SZ_2M);
....@@ -736,9 +774,10 @@
736774 return boot_flags;
737775 }
738776
739
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
740
-#include <fdt_support.h>
777
+#if defined(CONFIG_USB_GADGET)
741778 #include <usb.h>
779
+#if defined(CONFIG_USB_GADGET_DWC2_OTG)
780
+#include <fdt_support.h>
742781 #include <usb/dwc2_udc.h>
743782
744783 static struct dwc2_plat_otg_data otg_data = {
....@@ -808,7 +847,17 @@
808847 {
809848 return 0;
810849 }
811
-#endif
850
+#elif defined(CONFIG_USB_DWC3_GADGET) /* CONFIG_USB_GADGET_DWC2_OTG */
851
+#include <dwc3-uboot.h>
852
+
853
+int board_usb_cleanup(int index, enum usb_init_type init)
854
+{
855
+ dwc3_uboot_exit(index);
856
+ return 0;
857
+}
858
+
859
+#endif /* CONFIG_USB_DWC3_GADGET */
860
+#endif /* CONFIG_USB_GADGET */
812861
813862 static void bootm_no_reloc(void)
814863 {
....@@ -1049,15 +1098,13 @@
10491098 #endif
10501099 #ifdef CONFIG_ARM64
10511100 bootm_headers_t *bootm_images = (bootm_headers_t *)images;
1052
- ulong kernel_addr;
10531101
10541102 /* relocate kernel after decompress cleanup */
1055
- kernel_addr = env_get_ulong("kernel_addr_r", 16, 0);
1056
- if (kernel_addr != bootm_images->ep) {
1057
- memmove((char *)bootm_images->ep, (const char *)kernel_addr,
1103
+ if (orig_images_ep && orig_images_ep != bootm_images->ep) {
1104
+ memmove((char *)bootm_images->ep, (const char *)orig_images_ep,
10581105 bootm_images->os.image_len);
10591106 printf("== DO RELOCATE == Kernel from 0x%08lx to 0x%08lx\n",
1060
- kernel_addr, bootm_images->ep);
1107
+ orig_images_ep, bootm_images->ep);
10611108 }
10621109 #endif
10631110
....@@ -1109,16 +1156,39 @@
11091156 #endif
11101157 }
11111158
1112
-#ifdef CONFIG_ENVF
1113
- char * sys_bootargs;
1159
+#if defined(CONFIG_ENVF) || defined(CONFIG_ENV_PARTITION)
1160
+ char *part_type[] = { "mtdparts", "blkdevparts" };
1161
+ char *part_list;
1162
+ char *env;
1163
+ int id = 0;
11141164
1115
- sys_bootargs = env_get("sys_bootargs");
1116
- if (sys_bootargs) {
1117
- env_update("bootargs", sys_bootargs);
1165
+ env = env_get(part_type[id]);
1166
+ if (!env)
1167
+ env = env_get(part_type[++id]);
1168
+ if (env) {
1169
+ if (!strstr(env, part_type[id])) {
1170
+ part_list = calloc(1, strlen(env) + strlen(part_type[id]) + 2);
1171
+ if (part_list) {
1172
+ strcat(part_list, part_type[id]);
1173
+ strcat(part_list, "=");
1174
+ strcat(part_list, env);
1175
+ }
1176
+ } else {
1177
+ part_list = env;
1178
+ }
1179
+ env_update("bootargs", part_list);
11181180 if (dump)
1119
- printf("## sys_bootargs: %s\n\n", sys_bootargs);
1181
+ printf("## parts: %s\n\n", part_list);
1182
+ }
1183
+
1184
+ env = env_get("sys_bootargs");
1185
+ if (env) {
1186
+ env_update("bootargs", env);
1187
+ if (dump)
1188
+ printf("## sys_bootargs: %s\n\n", env);
11201189 }
11211190 #endif
1191
+
11221192 #ifdef CONFIG_MTD_BLK
11231193 if (!env_get("mtdparts")) {
11241194 char *mtd_par_info = mtd_part_parse(NULL);
....@@ -1129,6 +1199,10 @@
11291199 }
11301200 }
11311201 #endif
1202
+
1203
+#ifdef CONFIG_ANDROID_AB
1204
+ ab_update_root_partition();
1205
+#endif
11321206 /*
11331207 * Initrd fixup: remove unused "initrd=0x...,0x...",
11341208 * this for compatible with legacy parameter.txt
u-boot/arch/arm/mach-rockchip/boot_mode.c
....@@ -202,6 +202,10 @@
202202 printf("boot mode: watchdog\n");
203203 boot_mode[PL] = BOOT_MODE_WATCHDOG;
204204 break;
205
+ case BOOT_QUIESCENT:
206
+ printf("boot mode: quiescent\n");
207
+ boot_mode[PL] = BOOT_MODE_QUIESCENT;
208
+ break;
205209 default:
206210 printf("boot mode: None\n");
207211 boot_mode[PL] = BOOT_MODE_UNDEFINE;
u-boot/arch/arm/mach-rockchip/boot_rkimg.c
....@@ -19,6 +19,8 @@
1919 #include <key.h>
2020 #include <mmc.h>
2121 #include <malloc.h>
22
+#include <mp_boot.h>
23
+#include <mtd_blk.h>
2224 #include <nvme.h>
2325 #include <scsi.h>
2426 #include <stdlib.h>
....@@ -91,6 +93,10 @@
9193
9294 if (done)
9395 return;
96
+
97
+#ifdef CONFIG_MP_BOOT
98
+ mpb_post(0);
99
+#endif
94100
95101 /* configuration */
96102 if (!param_parse_assign_bootdev(&devtype, &devnum)) {
....@@ -269,6 +275,9 @@
269275
270276 printf("PartType: %s\n", part_get_type(dev_desc));
271277
278
+#ifdef CONFIG_MTD_BLK
279
+ mtd_blk_map_partitions(dev_desc);
280
+#endif
272281 return dev_desc;
273282 }
274283
....@@ -512,7 +521,7 @@
512521 LOCATE_END,
513522 };
514523
515
-static int rkimg_traverse_read_dtb(void *fdt, int where)
524
+static int dtb_scan(void *fdt, int where)
516525 {
517526 if (where == LOCATE_DISTRO) {
518527 #ifdef CONFIG_ROCKCHIP_EARLY_DISTRO_DTB
....@@ -557,19 +566,13 @@
557566 int locate, ret;
558567 int size;
559568
560
- /* init resource list */
561
-#ifdef CONFIG_ROCKCHIP_RESOURCE_IMAGE
562
- resource_traverse_init_list();
563
-#endif
564
-
565
- /* traverse location */
566569 for (locate = 0; locate < LOCATE_END; locate++) {
567
- ret = rkimg_traverse_read_dtb(fdt, locate);
570
+ ret = dtb_scan(fdt, locate);
568571 if (!ret)
569572 break;
570573 }
571574 if (ret) {
572
- printf("No find valid DTB, ret=%d\n", ret);
575
+ printf("No valid DTB, ret=%d\n", ret);
573576 return ret;
574577 }
575578
....@@ -608,7 +611,7 @@
608611 offset = hdr->page_size + ALIGN(hdr->kernel_size, hdr->page_size) +
609612 ALIGN(hdr->ramdisk_size, hdr->page_size);
610613 #ifdef CONFIG_ROCKCHIP_RESOURCE_IMAGE
611
- ret = resource_create_ram_list(dev_desc, (void *)hdr + offset);
614
+ ret = resource_setup_ram_list(dev_desc, (void *)hdr + offset);
612615 if (ret)
613616 return ret;
614617
....@@ -650,9 +653,9 @@
650653 if (!dev_desc)
651654 return -ENODEV;
652655
653
- ret = resource_create_ram_list(dev_desc, (void *)data);
656
+ ret = resource_setup_ram_list(dev_desc, (void *)data);
654657 if (ret) {
655
- printf("resource_create_ram_list fail, ret=%d\n", ret);
658
+ printf("resource_setup_ram_list fail, ret=%d\n", ret);
656659 return ret;
657660 }
658661
u-boot/arch/arm/mach-rockchip/chip_info.c
....@@ -63,6 +63,10 @@
6363 chip_info[0] = 0x33333236;
6464 #elif defined(CONFIG_ROCKCHIP_PX30)
6565 chip_info[0] = 0x50583330;
66
+#elif defined(CONFIG_ROCKCHIP_RK3528)
67
+ chip_info[0] = 0x33353238;
68
+#elif defined(CONFIG_ROCKCHIP_RK3562)
69
+ chip_info[0] = 0x33353632;
6670 #elif defined(CONFIG_ROCKCHIP_RK3568)
6771 chip_info[0] = 0x33353638;
6872 #elif defined(CONFIG_ROCKCHIP_RK3588)
u-boot/arch/arm/mach-rockchip/fit.c
....@@ -142,14 +142,14 @@
142142 {
143143 __maybe_unused int conf_noffset;
144144 disk_partition_t part;
145
- char *part_name;
145
+ char *part_name = PART_BOOT;
146146 void *fit, *fdt;
147147 int blk_num;
148148
149
+#ifndef CONFIG_ANDROID_AB
149150 if (rockchip_get_boot_mode() == BOOT_MODE_RECOVERY)
150151 part_name = PART_RECOVERY;
151
- else
152
- part_name = PART_BOOT;
152
+#endif
153153
154154 if (part_get_info_by_name(dev_desc, part_name, &part) < 0) {
155155 FIT_I("No %s partition\n", part_name);
....@@ -201,6 +201,7 @@
201201 printf("%s: ", fdt_get_name(fit, conf_noffset, NULL));
202202 if (fit_config_verify(fit, conf_noffset)) {
203203 puts("\n");
204
+ /* don't remove this failure handle */
204205 run_command("download", 0);
205206 hang();
206207 }
....@@ -246,6 +247,7 @@
246247 {
247248 int ret;
248249
250
+ /* free for fit_image_fixup_alloc(FIT_FDT_PROP) to re-alloc */
249251 if ((gd->flags & GD_FLG_KDTB_READY) && !gd->fdt_blob_kern)
250252 sysmem_free((phys_addr_t)gd->fdt_blob);
251253
....@@ -404,65 +406,45 @@
404406 }
405407
406408 #ifdef CONFIG_ROCKCHIP_RESOURCE_IMAGE
407
-static int fit_image_load_resource(const void *fit, struct blk_desc *dev_desc,
408
- disk_partition_t *part, ulong *addr)
409
+ulong fit_image_init_resource(struct blk_desc *dev_desc)
409410 {
410
- int offset, size;
411
- int ret;
412
- void *data;
413
-
414
- ret = fdt_image_get_offset_size(fit, FIT_MULTI_PROP, &offset, &size);
415
- if (ret)
416
- return ret;
417
-
418
- data = malloc(ALIGN(size, dev_desc->blksz));
419
- if (!data)
420
- return -ENOMEM;
421
-
422
- *addr = (ulong)data;
423
-
424
- return fit_image_load_one(fit, dev_desc, part, FIT_MULTI_PROP,
425
- data, IS_ENABLED(CONFIG_FIT_SIGNATURE));
426
-}
427
-
428
-int fit_image_init_resource(void)
429
-{
430
- struct blk_desc *dev_desc;
431411 disk_partition_t part;
412
+ void *fit, *buf;
413
+ int offset, size;
432414 int ret = 0;
433
- void *fit;
434415
435
- dev_desc = rockchip_get_bootdev();
436
- if (!dev_desc) {
437
- FIT_I("No dev_desc!\n");
416
+ if (!dev_desc)
438417 return -ENODEV;
439
- }
440418
441419 fit = fit_get_blob(dev_desc, &part, true);
442420 if (!fit)
421
+ return -EAGAIN;
422
+
423
+ ret = fdt_image_get_offset_size(fit, FIT_MULTI_PROP, &offset, &size);
424
+ if (ret)
443425 return -EINVAL;
444426
445
-#ifdef CONFIG_ROCKCHIP_RESOURCE_IMAGE
446
- ulong rsce;
427
+ buf = memalign(ARCH_DMA_MINALIGN, ALIGN(size, dev_desc->blksz));
428
+ if (!buf)
429
+ return -ENOMEM;
447430
448
- ret = fit_image_load_resource(fit, dev_desc, &part, &rsce);
431
+ printf("RESC: '%s', blk@0x%08lx\n", part.name,
432
+ part.start + ((FIT_ALIGN(fdt_totalsize(fit)) + offset) / dev_desc->blksz));
433
+ ret = fit_image_load_one(fit, dev_desc, &part, FIT_MULTI_PROP, buf, 1);
434
+ if (ret)
435
+ return ret;
436
+
437
+ ret = resource_setup_ram_list(dev_desc, buf);
449438 if (ret) {
450
- FIT_I("Failed to load resource\n");
439
+ FIT_I("Failed to setup resource ram list, ret=%d\n", ret);
451440 free(fit);
452441 return ret;
453442 }
454443
455
- ret = resource_create_ram_list(dev_desc, (void *)rsce);
456
- if (ret) {
457
- FIT_I("Failed to create resource list\n");
458
- free(fit);
459
- return ret;
460
- }
461
-#endif
462444 fit_msg(fit);
463445 free(fit);
464446
465
- return ret;
447
+ return 0;
466448 }
467449 #else
468450 int fit_image_read_dtb(void *fdt_addr)
u-boot/arch/arm/mach-rockchip/fit_args.sh
....@@ -107,7 +107,9 @@
107107
108108 # Base
109109 DARM_BASE=`sed -n "/CONFIG_SYS_SDRAM_BASE=/s/CONFIG_SYS_SDRAM_BASE=//p" ${srctree}/include/autoconf.mk|tr -d '\r'`
110
-UBOOT_LOAD_ADDR=`sed -n "/CONFIG_SYS_TEXT_BASE=/s/CONFIG_SYS_TEXT_BASE=//p" ${srctree}/include/autoconf.mk|tr -d '\r'`
110
+if ! grep -q '^CONFIG_FIT_OMIT_UBOOT=y' .config ; then
111
+ UBOOT_LOAD_ADDR=`sed -n "/CONFIG_SYS_TEXT_BASE=/s/CONFIG_SYS_TEXT_BASE=//p" ${srctree}/include/autoconf.mk|tr -d '\r'`
112
+fi
111113
112114 # ARCH
113115 U_ARCH="arm"
u-boot/arch/arm/mach-rockchip/fit_misc.c
....@@ -6,6 +6,7 @@
66
77 #include <common.h>
88 #include <boot_rkimg.h>
9
+#include <malloc.h>
910 #include <misc.h>
1011 #ifdef CONFIG_SPL_BUILD
1112 #include <spl.h>
....@@ -25,7 +26,7 @@
2526 #if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
2627
2728 #define FIT_UNCOMP_HASH_NODENAME "digest"
28
-#if CONFIG_IS_ENABLED(MISC_DECOMPRESS) || CONFIG_IS_ENABLED(GZIP)
29
+#if CONFIG_IS_ENABLED(MISC_DECOMPRESS) || CONFIG_IS_ENABLED(GZIP) || CONFIG_IS_ENABLED(LZMA)
2930 static int fit_image_get_uncomp_digest(const void *fit, int parent_noffset)
3031 {
3132 const char *name;
....@@ -126,8 +127,10 @@
126127 else
127128 misc_decompress_sync(comp);
128129 #else
130
+#if CONFIG_IS_ENABLED(GZIP)
129131 ret = gunzip((void *)(*load_addr), ALIGN(len, FIT_MAX_SPL_IMAGE_SZ),
130132 (void *)(*src_addr), (void *)(&len));
133
+#endif
131134 #endif
132135 }
133136
....@@ -154,7 +157,7 @@
154157 void board_fit_image_post_process(void *fit, int node, ulong *load_addr,
155158 ulong **src_addr, size_t *src_len, void *spec)
156159 {
157
-#if CONFIG_IS_ENABLED(MISC_DECOMPRESS) || CONFIG_IS_ENABLED(GZIP)
160
+#if CONFIG_IS_ENABLED(MISC_DECOMPRESS) || CONFIG_IS_ENABLED(GZIP) || CONFIG_IS_ENABLED(LZMA)
158161 fit_decomp_image(fit, node, load_addr, src_addr, src_len, spec);
159162 #endif
160163
....@@ -169,6 +172,33 @@
169172 }
170173 }
171174 #endif
175
+
176
+#ifndef CONFIG_SPL_BUILD
177
+ if (fit_image_check_type(fit, node, IH_TYPE_FIRMWARE)) {
178
+ const char *uname;
179
+ char *old, *new;
180
+ size_t len;
181
+
182
+ uname = fdt_get_name(fit, node, NULL);
183
+ if (strcmp("bootargs", uname))
184
+ return;
185
+
186
+ old = env_get("bootargs");
187
+ if (!old)
188
+ return;
189
+
190
+ len = strlen(old) + (*src_len) + 2;
191
+ new = calloc(1, len);
192
+ if (new) {
193
+ strcpy(new, old);
194
+ strcat(new, " ");
195
+ strcat(new, (char *)(*src_addr));
196
+ env_set("bootargs", new);
197
+ free(new);
198
+ }
199
+
200
+ }
201
+#endif
172202 }
173203 #endif /* FIT_IMAGE_POST_PROCESS */
174204 /*
u-boot/arch/arm/mach-rockchip/fit_nodes.sh
....@@ -27,6 +27,10 @@
2727 # nodes
2828 function gen_uboot_node()
2929 {
30
+ if [ -z ${UBOOT_LOAD_ADDR} ]; then
31
+ return
32
+ fi
33
+
3034 UBOOT="u-boot-nodtb.bin"
3135 echo " uboot {
3236 description = \"U-Boot\";
....@@ -53,10 +57,16 @@
5357 algo = \"sha256\";
5458 };
5559 };"
60
+
61
+ LOADABLE_UBOOT="\"uboot\", "
5662 }
5763
5864 function gen_fdt_node()
5965 {
66
+ if [ -z ${UBOOT_LOAD_ADDR} ]; then
67
+ return
68
+ fi
69
+
6070 echo " fdt {
6171 description = \"U-Boot dtb\";
6272 data = /incbin/(\"./u-boot.dtb\");
....@@ -67,12 +77,19 @@
6777 algo = \"sha256\";
6878 };
6979 };"
80
+
81
+ FDT_SIGN=", \"fdt\""
82
+ FDT="fdt = \"fdt\"${PROP_KERN_DTB};"
7083 };
7184
7285 function gen_kfdt_node()
7386 {
87
+ if [ -z ${UBOOT_LOAD_ADDR} ]; then
88
+ return
89
+ fi
90
+
7491 KERN_DTB=`sed -n "/CONFIG_EMBED_KERNEL_DTB_PATH=/s/CONFIG_EMBED_KERNEL_DTB_PATH=//p" .config | tr -d '"'`
75
- if [ -z "${KERN_DTB}" ]; then
92
+ if [ -z ${KERN_DTB} ]; then
7693 return;
7794 fi
7895
....@@ -96,7 +113,7 @@
96113 ${srctree}/arch/arm/mach-rockchip/decode_bl31.py
97114
98115 NUM=1
99
- for ATF in `ls -l bl31_0x*.bin | sort --key=5 -nr | awk '{ print $9 }'`
116
+ for ATF in `ls -1 -S bl31_0x*.bin`
100117 do
101118 ATF_LOAD_ADDR=`echo ${ATF} | awk -F "_" '{ printf $2 }' | awk -F "." '{ printf $1 }'`
102119 # only atf-1 support compress
....@@ -135,7 +152,9 @@
135152 };"
136153 fi
137154
138
- if [ ${NUM} -gt 1 ]; then
155
+ if [ ${NUM} -eq 2 ]; then
156
+ LOADABLE_ATF=${LOADABLE_ATF}"\"atf-${NUM}\""
157
+ elif [ ${NUM} -gt 2 ]; then
139158 LOADABLE_ATF=${LOADABLE_ATF}", \"atf-${NUM}\""
140159 fi
141160 NUM=`expr ${NUM} + 1`
....@@ -152,6 +171,12 @@
152171 # If not AArch32 mode
153172 if ! grep -q '^CONFIG_ARM64_BOOT_AARCH32=y' .config ; then
154173 ENTRY="entry = <"${TEE_LOAD_ADDR}">;"
174
+
175
+ # if disable packing tee.bin
176
+ if ! grep -q '^CONFIG_SPL_OPTEE=y' .config ; then
177
+ return
178
+ fi
179
+
155180 fi
156181 fi
157182
....@@ -179,7 +204,7 @@
179204 };"
180205 LOADABLE_OPTEE=", \"optee\""
181206 FIRMWARE_OPTEE="firmware = \"optee\";"
182
- FIRMWARE_SIGN=", \"firmware\""
207
+ FIRMWARE_SIGN="\"firmware\""
183208 }
184209
185210 function gen_mcu_node()
....@@ -314,8 +339,13 @@
314339 function gen_arm64_configurations()
315340 {
316341 PLATFORM=`sed -n "/CONFIG_DEFAULT_DEVICE_TREE/p" .config | awk -F "=" '{ print $2 }' | tr -d '"'`
317
-if grep -q '^CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y' .config ; then
342
+if grep -q '^CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y' .config ; then
318343 ALGO_PADDING=" padding = \"pss\";"
344
+fi
345
+if grep -q '^CONFIG_FIT_ENABLE_RSA4096_SUPPORT=y' .config ; then
346
+ ALGO_NAME=" algo = \"sha256,rsa4096\";"
347
+else
348
+ ALGO_NAME=" algo = \"sha256,rsa2048\";"
319349 fi
320350 echo " };
321351
....@@ -325,14 +355,14 @@
325355 description = \"${PLATFORM}\";
326356 rollback-index = <0x0>;
327357 firmware = \"atf-1\";
328
- loadables = \"uboot\"${LOADABLE_ATF}${LOADABLE_OPTEE}${LOADABLE_OTHER};
358
+ loadables = ${LOADABLE_UBOOT}${LOADABLE_ATF}${LOADABLE_OPTEE}${LOADABLE_OTHER};
329359 ${STANDALONE_MCU}
330
- fdt = \"fdt\"${PROP_KERN_DTB};
360
+ ${FDT}
331361 signature {
332
- algo = \"sha256,rsa2048\";
362
+ ${ALGO_NAME}
333363 ${ALGO_PADDING}
334364 key-name-hint = \"dev\";
335
- sign-images = \"fdt\", \"firmware\", \"loadables\"${STANDALONE_SIGN};
365
+ sign-images = \"firmware\", \"loadables\"${FDT_SIGN}${STANDALONE_SIGN};
336366 };
337367 };
338368 };
....@@ -343,9 +373,24 @@
343373 function gen_arm_configurations()
344374 {
345375 PLATFORM=`sed -n "/CONFIG_DEFAULT_DEVICE_TREE/p" .config | awk -F "=" '{ print $2 }' | tr -d '"'`
346
-if grep -q '^CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y' .config ; then
376
+if grep -q '^CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y' .config ; then
347377 ALGO_PADDING=" padding = \"pss\";"
348378 fi
379
+if grep -q '^CONFIG_FIT_ENABLE_RSA4096_SUPPORT=y' .config ; then
380
+ ALGO_NAME=" algo = \"sha256,rsa4096\";"
381
+else
382
+ ALGO_NAME=" algo = \"sha256,rsa2048\";"
383
+fi
384
+if [ ! -z "${LOADABLE_UBOOT}" ] || [ ! -z "${LOADABLE_OTHER}" ]; then
385
+ LOADABLE_UBOOT="\"uboot\""
386
+ LOADABLES="loadables = ${LOADABLE_UBOOT}${LOADABLE_OTHER};"
387
+ if [ -z ${FIRMWARE_SIGN} ]; then
388
+ LOADABLES_SIGN="\"loadables\""
389
+ else
390
+ LOADABLES_SIGN=", \"loadables\""
391
+ fi
392
+fi
393
+
349394 echo " };
350395
351396 configurations {
....@@ -354,14 +399,14 @@
354399 description = \"${PLATFORM}\";
355400 rollback-index = <0x0>;
356401 ${FIRMWARE_OPTEE}
357
- loadables = \"uboot\"${LOADABLE_OTHER};
402
+ ${LOADABLES}
358403 ${STANDALONE_MCU}
359
- fdt = \"fdt\"${PROP_KERN_DTB};
404
+ ${FDT}
360405 signature {
361
- algo = \"sha256,rsa2048\";
406
+ ${ALGO_NAME}
362407 ${ALGO_PADDING}
363408 key-name-hint = \"dev\";
364
- sign-images = \"fdt\", \"loadables\"${FIRMWARE_SIGN}${STANDALONE_SIGN};
409
+ sign-images = ${FIRMWARE_SIGN}${LOADABLES_SIGN}${FDT_SIGN}${STANDALONE_SIGN};
365410 };
366411 };
367412 };
u-boot/arch/arm/mach-rockchip/hotkey.c
....@@ -17,10 +17,10 @@
1717 #define CTRL_D 0x04 /* download mde */
1818 #define CTRL_F 0x06 /* fastboot mode */
1919 #define CTRL_I 0x09 /* inicall debug for kernel */
20
+#define CTRL_L 0x0c /* late shell(cli) on BOOTM_STATE_OS_GO */
2021 #define CTRL_M 0x0d /* memory(sysmem/bidram) */
2122 #define CTRL_P 0x10 /* parameter(cmdline) dump */
2223 #define CTRL_R 0x12 /* regulator initial state dump */
23
-#define CTRL_S 0x13 /* shell(cli) on BOOTM_STATE_OS_GO */
2424 #define CTRL_T 0x14 /* print fdt */
2525
2626 bool is_hotkey(enum hotkey_t id)
....@@ -75,7 +75,7 @@
7575 cli_loop();
7676 break;
7777 case HK_CLI_OS_GO:
78
- if (gd->console_evt == CTRL_S)
78
+ if (gd->console_evt == CTRL_L)
7979 cli_loop();
8080 break;
8181 default:
u-boot/arch/arm/mach-rockchip/kernel_dtb.c
old mode 100755new mode 100644
....@@ -16,503 +16,6 @@
1616
1717 DECLARE_GLOBAL_DATA_PTR;
1818
19
-
20
-#if 1
21
-struct display_fixup_data {
22
- int type;
23
-
24
- int delay_prepare;
25
- int delay_enable;
26
- int delay_disable;
27
- int delay_unprepare;
28
- int delay_reset;
29
- int delay_init;
30
- int size_width;
31
- int size_height;
32
-
33
- int clock_frequency;
34
- int hactive;
35
- int hfront_porch;
36
- int hsync_len;
37
- int hback_porch;
38
- int vactive;
39
- int vfront_porch;
40
- int vsync_len;
41
- int vback_porch;
42
- int hsync_active;
43
- int vsync_active;
44
- int de_active;
45
- int pixelclk_active;
46
-
47
- /* for DSI Panel */
48
- int flags;
49
- int format;
50
- int lanes;
51
- int init_cmd_length;
52
- u8 *init_cmd;
53
-
54
- int nodka_lvds;
55
-};
56
-enum {
57
- PANEL_TYPE_DSI,
58
- PANEL_TYPE_EDP,
59
- PANEL_TYPE_LVDS,
60
-};
61
-
62
-#define CUSTOM_PARTITION_NAME "baseparameter"
63
-#define LCD_PARAM_MAX_COUNT 27
64
-
65
-int lcdParam[LCD_PARAM_MAX_COUNT];
66
-char param_buf_temp[4*1024] = {0};
67
-
68
-void set_lcdparam_test_edp(struct display_fixup_data *data)
69
-{
70
-
71
- data->type = PANEL_TYPE_DSI;
72
- data->delay_prepare = 100;
73
- data->delay_enable = 100;
74
- data->delay_disable = 100;
75
- data->delay_unprepare = 100;
76
- data->delay_reset = 100;
77
- data->delay_init = 100;
78
- data->size_width = 240;
79
- data->size_height = 300;
80
- data->clock_frequency = 60000000;
81
- data->hactive = 1024;
82
- data->hfront_porch = 12;
83
- data->hsync_len = 16;
84
- data->hback_porch = 48;
85
- data->vactive = 600;
86
- data->vfront_porch = 8;
87
- data->vsync_len = 4;
88
- data->vback_porch = 8;
89
- data->hsync_active = 0;
90
- data->vsync_active = 0;
91
- data->de_active = 0;
92
- data->pixelclk_active = 0;
93
- data->flags = 0;
94
- data->format = 0;
95
- data->lanes = 4;
96
- *(data->init_cmd + 0) = 0x05;
97
- *(data->init_cmd + 1) = 0x00;
98
- *(data->init_cmd + 2) = 0x01;
99
- *(data->init_cmd + 3) = 0x01;
100
-
101
- *(data->init_cmd + 4) = 0x05;
102
- *(data->init_cmd + 5) = 0x00;
103
- *(data->init_cmd + 6) = 0x01;
104
- *(data->init_cmd + 7) = 0x02;
105
-
106
- *(data->init_cmd + 8) = 0x05;
107
- *(data->init_cmd + 9) = 0x00;
108
- *(data->init_cmd + 10) = 0x01;
109
- *(data->init_cmd + 11) = 0x03;
110
-
111
- *(data->init_cmd + 12) = 0x05;
112
- *(data->init_cmd + 13) = 0x00;
113
- *(data->init_cmd + 14) = 0x01;
114
- *(data->init_cmd + 15) = 0x05;
115
-
116
-}
117
-
118
-int get_lcdparam_info_from_custom_partition(struct display_fixup_data *data)
119
-{
120
-
121
- struct blk_desc *dev_desc;
122
- disk_partition_t part_info;
123
- char *boot_partname = CUSTOM_PARTITION_NAME;
124
- int ret,i;
125
-
126
- dev_desc = rockchip_get_bootdev();
127
- if (!dev_desc) {
128
- printf("%s: dev_desc is NULL!\n", __func__);
129
- return -ENODEV;
130
- }
131
-
132
- ret = part_get_info_by_name(dev_desc, boot_partname, &part_info);
133
- if (ret < 0) {
134
- printf("%s: failed to get %s part, ret=%d\n",
135
- __func__, boot_partname, ret);
136
- /* RKIMG can support part table without 'boot' */
137
- return -1;
138
- }
139
-
140
- printf("block num: %lu, name %s ,type %s,block size :%lu\n",part_info.size,part_info.name,part_info.type,part_info.blksz);
141
-
142
- ret = blk_dread(dev_desc, part_info.start + 512, 1, param_buf_temp);
143
- if (ret != 1) {
144
- printf("%s: failed to read screen parameter, ret=%d\n",
145
- __func__, ret);
146
- return -1;
147
- }
148
-
149
- for (i = 0; i < LCD_PARAM_MAX_COUNT; i++) {
150
- lcdParam[i] = param_buf_temp[i * 4];
151
- lcdParam[i] = (lcdParam[i] << 8) + param_buf_temp[i * 4 + 1];
152
- lcdParam[i] = (lcdParam[i] << 8) + param_buf_temp[i * 4 + 2];
153
- lcdParam[i] = (lcdParam[i] << 8) + param_buf_temp[i * 4 + 3];
154
- if(lcdParam[i] < 0){
155
- lcdParam[i] = -lcdParam[i];
156
- }
157
- if(lcdParam[i] > 100000 && i != 9){
158
- lcdParam[i] = 0;
159
- }
160
- printf("--get-- lcd_param %d\n",lcdParam[i]);
161
- }
162
-
163
- if(lcdParam[14] == 0 || lcdParam[10] == 0){
164
- return -1;
165
- }
166
- printf("-get- crc32 = 0X%02X%02X%02X%02X\n",
167
- param_buf_temp[LCD_PARAM_MAX_COUNT * 4], param_buf_temp[LCD_PARAM_MAX_COUNT * 4 + 1],
168
- param_buf_temp[LCD_PARAM_MAX_COUNT * 4 + 2], param_buf_temp[LCD_PARAM_MAX_COUNT * 4 + 3]);
169
-
170
- data->type = lcdParam[0];
171
- data->delay_prepare = lcdParam[4];
172
- data->delay_enable = lcdParam[2];
173
- data->delay_disable = lcdParam[3];
174
- data->delay_unprepare = lcdParam[1];
175
- data->delay_reset = lcdParam[5];
176
- data->delay_init = lcdParam[6];
177
- data->size_width = lcdParam[7];
178
- data->size_height = lcdParam[8];
179
- data->clock_frequency = lcdParam[9];
180
- data->hactive = lcdParam[10];
181
- data->hfront_porch = lcdParam[11];
182
- data->hsync_len = lcdParam[12];
183
- data->hback_porch = lcdParam[13];
184
- data->vactive = lcdParam[14];
185
- data->vfront_porch = lcdParam[15];
186
- data->vsync_len = lcdParam[16];
187
- data->vback_porch = lcdParam[17];
188
- data->hsync_active = lcdParam[18];
189
- data->vsync_active = lcdParam[19];
190
- data->de_active = lcdParam[20];
191
- data->pixelclk_active = lcdParam[21];
192
- data->flags = lcdParam[22];
193
- data->format = lcdParam[23];
194
- data->lanes = lcdParam[24];
195
- data->init_cmd_length = lcdParam[25] = 16;
196
- data->nodka_lvds = lcdParam[26];
197
- data->init_cmd = malloc(sizeof(*(data->init_cmd)) * data->init_cmd_length);
198
- for(i = 0; i < data->init_cmd_length; i++){
199
- *(data->init_cmd + i) = param_buf_temp[100 + i];
200
- // printf("init cmd = %x\n",param_buf_temp[100 + i]);
201
-
202
- }
203
-
204
-// set_lcdparam_test_edp(data);
205
-
206
- return 0;
207
-}
208
-
209
-#endif
210
-
211
-
212
-static int find_connector_node(const void *blob, int node)
213
-{
214
- int phandle, remote;
215
- int nodedepth;
216
-
217
- phandle = fdt_getprop_u32_default_node(blob, node, 0,
218
- "remote-endpoint", -1);
219
- remote = fdt_node_offset_by_phandle(blob, phandle);
220
- nodedepth = fdt_node_depth(blob, remote);
221
-
222
- return fdt_supernode_atdepth_offset(blob, remote,
223
- nodedepth - 3, NULL);
224
-}
225
-
226
-static int get_panel_node(const void *blob, int conn_node)
227
-{
228
- int panel, ports, port, ep, remote, ph, nodedepth;
229
-
230
- panel = fdt_subnode_offset(blob, conn_node, "panel");
231
- printf("panel_1=%d\n",panel);
232
- if (panel > 0) {
233
- return panel;
234
- }
235
-
236
- ports = fdt_subnode_offset(blob, conn_node, "ports");
237
- if (ports < 0)
238
- {
239
- return -ENODEV;
240
- }
241
-
242
- fdt_for_each_subnode(port, blob, ports) {
243
- fdt_for_each_subnode(ep, blob, port) {
244
- ph = fdt_getprop_u32_default_node(blob, ep, 0,
245
- "remote-endpoint", 0);
246
- if (!ph)
247
- continue;
248
-
249
- remote = fdt_node_offset_by_phandle(blob, ph);
250
-
251
- nodedepth = fdt_node_depth(blob, remote);
252
- if (nodedepth < 2)
253
- continue;
254
-
255
- panel = fdt_supernode_atdepth_offset(blob, remote,
256
- nodedepth - 2,
257
- NULL);
258
- break;
259
- }
260
- }
261
- printf("panel_2=%d\n",panel);
262
- return panel;
263
-}
264
-
265
-static int fdt_fixup_node_status(void *blob, int node, enum fdt_status status)
266
-{
267
- int ret;
268
-
269
-// printf("My fixup %s %d\n", fdt_get_name(blob, node, NULL), status);
270
-
271
-set_status:
272
- ret = fdt_set_node_status(blob, node, status, 0);
273
- if (ret == -FDT_ERR_NOSPACE) {
274
- ret = fdt_increase_size(blob, 512);
275
- if (!ret)
276
- goto set_status;
277
- else
278
- goto err_size;
279
- } else if (ret < 0) {
280
- printf("Can't set node status: %s\n", fdt_strerror(ret));
281
- return ret;
282
- }
283
-
284
- return 0;
285
-
286
-err_size:
287
- printf("Can't increase blob size: %s\n", fdt_strerror(ret));
288
- return ret;
289
-}
290
-#if 0
291
-static int fdt_fixup_panel_init_sequence(void *fdt, int node,const struct display_fixup_data *data)
292
-{
293
- #if 0
294
- u8 init_buf[] = {0x05, 0x00, 0x01, 0x78, 0x15, 0x01, 0x02, 0x03, 0x04, 0x05, 0x05, 0x01, 0x14,0x39, 0x01, 0x03, 0x02, 0x29, 0x11};
295
- u8 exit_buf[] = {0x05, 0x64, 0x01, 0x29, 0x05, 0x64, 0x01, 0x11};
296
- #endif
297
- int ret;
298
-
299
-add_seq:
300
- ret = fdt_setprop(fdt, node, "panel-init-sequence", data->init_cmd, data->init_cmd_length);
301
- if (ret == -FDT_ERR_NOSPACE) {
302
- printf(" init sequence FDT_ERR_NOSPACE\n");
303
- ret = fdt_increase_size(fdt, data->init_cmd_length * 4);//gln the length needs precision
304
- if (!ret)
305
- goto add_seq;
306
- else
307
- goto err_size;
308
- } else if (ret < 0) {
309
- printf("Can't add property: %s\n", fdt_strerror(ret));
310
- return ret;
311
- }
312
-
313
-#if 0
314
-add_init_seq:
315
- ret = fdt_setprop(fdt, node, "panel-init-sequence", init_buf, sizeof(init_buf));
316
- if (ret == -FDT_ERR_NOSPACE) {
317
- printf(" init sequence FDT_ERR_NOSPACE\n");
318
- ret = fdt_increase_size(fdt, 512);//gln the length needs precision
319
- if (!ret)
320
- goto add_init_seq;
321
- else
322
- goto err_size;
323
- } else if (ret < 0) {
324
- printf("Can't add property: %s\n", fdt_strerror(ret));
325
- return ret;
326
- }
327
-add_exit_seq:
328
- ret = fdt_setprop(fdt, node, "panel-exit-sequence", exit_buf, sizeof(exit_buf));
329
- if (ret == -FDT_ERR_NOSPACE) {
330
- printf(" init sequence FDT_ERR_NOSPACE\n");
331
- ret = fdt_increase_size(fdt, 512);//gln the length needs precision
332
- if (!ret)
333
- goto add_exit_seq;
334
- else
335
- goto err_size;
336
- } else if (ret < 0) {
337
- printf("Can't add property: %s\n", fdt_strerror(ret));
338
- return ret;
339
- }
340
-#endif
341
-
342
- return 0;
343
-
344
-err_size:
345
- printf("Can't increase blob size: %s\n", fdt_strerror(ret));
346
- return ret;
347
-}
348
-#endif
349
-
350
-static int fdt_fixup_setprop_u32(void *fdt, int node, const char *name, u32 data)
351
-{
352
- int ret;
353
-
354
-set_prop:
355
- ret = fdt_setprop_u32(fdt, node, name, data);
356
- if (ret == -FDT_ERR_NOSPACE) {
357
- ret = fdt_increase_size(fdt, 512);
358
- if (!ret)
359
- goto set_prop;
360
- else
361
- goto err_size;
362
- } else if (ret < 0) {
363
- printf("Can't add property: %s\n", fdt_strerror(ret));
364
- return ret;
365
- }
366
-
367
- return 0;
368
-
369
-err_size:
370
- printf("Can't increase blob size: %s\n", fdt_strerror(ret));
371
- return ret;
372
-}
373
-
374
-static void fdt_fixup_display_timing(void *blob, int node,
375
- const struct display_fixup_data *data)
376
-{
377
- fdt_fixup_setprop_u32(blob, node, "clock-frequency", data->clock_frequency);
378
- fdt_fixup_setprop_u32(blob, node, "hactive", data->hactive);
379
- fdt_fixup_setprop_u32(blob, node, "hfront-porch", data->hfront_porch);
380
- fdt_fixup_setprop_u32(blob, node, "hsync-len", data->hsync_len);
381
- fdt_fixup_setprop_u32(blob, node, "hback-porch", data->hback_porch);
382
- fdt_fixup_setprop_u32(blob, node, "vactive", data->vactive);
383
- fdt_fixup_setprop_u32(blob, node, "vfront-porch", data->vfront_porch);
384
- fdt_fixup_setprop_u32(blob, node, "vsync-len", data->vsync_len);
385
- fdt_fixup_setprop_u32(blob, node, "vback-porch", data->vback_porch);
386
- fdt_fixup_setprop_u32(blob, node, "hsync-active", data->hsync_active);
387
- fdt_fixup_setprop_u32(blob, node, "vsync-active", data->vsync_active);
388
- fdt_fixup_setprop_u32(blob, node, "de-active", data->de_active);
389
- fdt_fixup_setprop_u32(blob, node, "pixelclk-active", data->pixelclk_active);
390
-}
391
-
392
-static void fdt_fixup_panel_node(void *blob, int node, const char *name,
393
- const struct display_fixup_data *data)
394
-{
395
-/*
396
- if (!strcmp(name, "dsi")) {
397
- fdt_setprop_u32(blob, node, "dsi,flags", data->flags);
398
- fdt_setprop_u32(blob, node, "dsi,format", data->format);
399
- fdt_setprop_u32(blob, node, "dsi,lanes", data->lanes);
400
- fdt_fixup_panel_init_sequence(blob, node,data);
401
- }
402
-*/
403
- fdt_fixup_setprop_u32(blob, node, "prepare-delay-ms", data->delay_prepare);
404
- fdt_fixup_setprop_u32(blob, node, "enable-delay-ms", data->delay_enable);
405
- fdt_fixup_setprop_u32(blob, node, "disable-delay-ms", data->delay_disable);
406
- fdt_fixup_setprop_u32(blob, node, "unprepare-delay-ms", data->delay_unprepare);
407
- fdt_fixup_setprop_u32(blob, node, "reset-delay-ms", data->delay_reset);
408
- fdt_fixup_setprop_u32(blob, node, "init-delay-ms", data->delay_init);
409
- fdt_fixup_setprop_u32(blob, node, "width-mm", data->size_width);
410
- fdt_fixup_setprop_u32(blob, node, "height-mm", data->size_height);
411
-
412
-}
413
-static void fdt_fixup_nodka_lvds(void *blob, int node,
414
- const struct display_fixup_data *data)
415
-{
416
- if ( data->nodka_lvds != 0 )
417
- fdt_fixup_setprop_u32(blob, node, "nodka-lvds", data->nodka_lvds);
418
-}
419
-
420
-
421
-static int fdt_fixup_display_sub_route(void *blob, const char *name,
422
- enum fdt_status status,
423
- const struct display_fixup_data *data)
424
-{
425
- int route, phandle, connect, connector, panel, dt, timing, route_lvds;
426
- char path[64];
427
- char path_lvds[16] = "/panel";
428
- int ret;
429
- sprintf(path, "/display-subsystem/route/route-%s", name);
430
-
431
-
432
- route = fdt_path_offset(blob, path);
433
- printf("route : %d \n",route);
434
- if (route < 0)
435
- return route;
436
-
437
- route_lvds = fdt_path_offset(blob, path_lvds);
438
- if (route_lvds < 0)
439
- {
440
- printf("can not get route_lvds = %d\n",route_lvds);
441
- return route_lvds;
442
- }
443
- /* fixup lvds gpio channel*/
444
- fdt_fixup_nodka_lvds(blob, route_lvds, data);
445
-
446
- /* fixup route status */
447
- ret = fdt_fixup_node_status(blob, route, status);
448
- if (ret < 0)
449
- return ret;
450
- phandle = fdt_getprop_u32_default_node(blob, route, 0, "connect", -1);
451
- if (phandle < 0)
452
- return phandle;
453
- connect = fdt_node_offset_by_phandle(blob, phandle);
454
- if (connect < 0)
455
- return connect;
456
- connector = find_connector_node(blob, connect);
457
- if (connector < 0)
458
- return connector;
459
- /* fixup connector status */
460
- ret = fdt_fixup_node_status(blob, connector, status);
461
- if (ret < 0)
462
- return ret;
463
- if (status != FDT_STATUS_OKAY) {
464
- return 0;
465
- }
466
- panel = get_panel_node(blob, connector);
467
- if (panel < 0)
468
- return panel;
469
- /* fixup panel info */
470
- fdt_fixup_panel_node(blob, panel, name, data);
471
- dt = fdt_subnode_offset(blob, panel, "display-timings");
472
- if (dt < 0) {
473
- return dt;
474
- }
475
- timing = fdt_subnode_offset(blob, dt, "timing");
476
- if (timing < 0) {
477
- phandle = fdt_getprop_u32_default_node(blob, dt, 0, "native-mode", -1);
478
- if (phandle < 0)
479
- return phandle;
480
-
481
- timing = fdt_node_offset_by_phandle(blob, phandle);
482
- if (timing < 0)
483
- return timing;
484
- }
485
-
486
- /* fixup panel display timing */
487
- fdt_fixup_display_timing(blob, timing, data);
488
- return 0;
489
-}
490
-
491
-static void fdt_fixup_display_route(void *blob, const struct display_fixup_data *data)
492
-{
493
- if (data->type == PANEL_TYPE_DSI) {
494
- fdt_fixup_display_sub_route(blob, "dsi1", FDT_STATUS_OKAY, data);
495
- fdt_fixup_display_sub_route(blob, "edp", FDT_STATUS_DISABLED, data);
496
- fdt_fixup_display_sub_route(blob, "lvds", FDT_STATUS_DISABLED, data);
497
- } else if (data->type == PANEL_TYPE_EDP) {
498
- fdt_fixup_display_sub_route(blob, "dsi1", FDT_STATUS_DISABLED, data);
499
- fdt_fixup_display_sub_route(blob, "edp", FDT_STATUS_OKAY, data);
500
- fdt_fixup_display_sub_route(blob, "lvds", FDT_STATUS_DISABLED, data);
501
- } else if (data->type == PANEL_TYPE_LVDS) {
502
- fdt_fixup_display_sub_route(blob, "lvds", FDT_STATUS_OKAY, data);
503
- fdt_fixup_display_sub_route(blob, "dsi1", FDT_STATUS_DISABLED, data);
504
- fdt_fixup_display_sub_route(blob, "edp", FDT_STATUS_DISABLED, data);
505
- }
506
-}
507
-
508
-
509
-
510
-
511
-
512
-
513
-
514
-
515
-
51619 #ifdef CONFIG_USING_KERNEL_DTB_V2
51720 static int dm_rm_kernel_dev(void)
51821 {
....@@ -798,7 +301,6 @@
798301 #endif
799302 ulong fdt_addr = 0;
800303 int ret = -ENODEV;
801
- struct display_fixup_data fix_data;
802304
803305 printf("DM: v%d\n", IS_ENABLED(CONFIG_USING_KERNEL_DTB_V2) ? 2 : 1);
804306
....@@ -815,12 +317,10 @@
815317 return -ENODEV;
816318 }
817319
818
- if (IS_ENABLED(CONFIG_EMBED_KERNEL_DTB_ALWAYS)) {
819
- resource_init_list();
820
- printf("Always embed kernel dtb\n");
821
- goto dtb_embed;
822
- }
823
-
320
+#ifdef CONFIG_EMBED_KERNEL_DTB_ALWAYS
321
+ printf("Always embed kernel dtb\n");
322
+ goto dtb_embed;
323
+#endif
824324 ret = rockchip_read_dtb_file((void *)fdt_addr);
825325 if (!ret) {
826326 if (!dtb_check_ok((void *)fdt_addr, (void *)gd->fdt_blob)) {
....@@ -831,7 +331,10 @@
831331 }
832332 }
833333
334
+#ifdef CONFIG_EMBED_KERNEL_DTB
335
+#ifdef CONFIG_EMBED_KERNEL_DTB_ALWAYS
834336 dtb_embed:
337
+#endif
835338 if (gd->fdt_blob_kern) {
836339 if (!dtb_check_ok((void *)gd->fdt_blob_kern, (void *)gd->fdt_blob)) {
837340 printf("Embedded kernel dtb mismatch this platform!\n");
....@@ -850,7 +353,9 @@
850353 memcpy((void *)fdt_addr, gd->fdt_blob_kern,
851354 fdt_totalsize(gd->fdt_blob_kern));
852355 printf("DTB: %s\n", CONFIG_EMBED_KERNEL_DTB_PATH);
853
- } else {
356
+ } else
357
+#endif
358
+ {
854359 printf("Failed to get kernel dtb, ret=%d\n", ret);
855360 return -ENOENT;
856361 }
....@@ -870,8 +375,6 @@
870375 phandles_fixup_cru((void *)gd->fdt_blob);
871376 phandles_fixup_gpio((void *)gd->fdt_blob, (void *)ufdt_blob);
872377 #endif
873
- if (!get_lcdparam_info_from_custom_partition(&fix_data))
874
- fdt_fixup_display_route((void *)fdt_addr, &fix_data);
875378
876379 gd->flags |= GD_FLG_KDTB_READY;
877380 gd->of_root_f = gd->of_root;
u-boot/arch/arm/mach-rockchip/make_fit_uboot.sh
deleted file mode 100755
....@@ -1,16 +0,0 @@
1
-#!/bin/bash
2
-#
3
-# Copyright (C) 2022 Rockchip Electronics Co., Ltd
4
-#
5
-# SPDX-License-Identifier: GPL-2.0+
6
-#
7
-
8
-source ./${srctree}/arch/arm/mach-rockchip/fit_nodes.sh
9
-gen_header
10
-gen_uboot_node
11
-gen_mcu_node
12
-gen_kfdt_node
13
-gen_fdt_node
14
-gen_loadable_node
15
-gen_arm_configurations
16
-
u-boot/arch/arm/mach-rockchip/pstore.c
....@@ -103,6 +103,8 @@
103103 gd->pstore_addr = t->u.pstore.buf[LOG_UBOOT].addr;
104104 gd->pstore_size = t->u.pstore.buf[LOG_UBOOT].size - sizeof(struct persistent_ram_buffer);
105105 }
106
+#elif (CONFIG_PERSISTENT_RAM_ADDR == 0 || CONFIG_PERSISTENT_RAM_SIZE == 0)
107
+ #error: CONFIG_PERSISTENT_RAM_SIZE and CONFIG_PERSISTENT_RAM_ADDR value should not be 0.
106108 #else
107109 gd->pstore_addr = CONFIG_PERSISTENT_RAM_ADDR;
108110 gd->pstore_size = CONFIG_PERSISTENT_RAM_SIZE - sizeof(struct persistent_ram_buffer);
u-boot/arch/arm/mach-rockchip/resource_hwid.c
....@@ -267,13 +267,8 @@
267267
268268 hwid_init_data();
269269
270
- if (list_empty(&entrys_head)) {
271
- if (resource_init_list())
272
- return NULL;
273
- }
274
-
275
- list_for_each(node, &entrys_dtbs_head) {
276
- file = list_entry(node, struct resource_file, dtbs);
270
+ list_for_each(node, &entry_head) {
271
+ file = list_entry(node, struct resource_file, link);
277272 if (!strstr(file->name, DTB_SUFFIX))
278273 continue;
279274
u-boot/arch/arm/mach-rockchip/resource_img.c
....@@ -4,28 +4,21 @@
44 * SPDX-License-Identifier: GPL-2.0+
55 */
66 #include <common.h>
7
-#include <adc.h>
8
-#include <android_ab.h>
9
-#include <android_bootloader.h>
10
-#include <android_image.h>
117 #include <boot_rkimg.h>
128 #include <bmp_layout.h>
139 #include <malloc.h>
14
-#include <asm/io.h>
1510 #include <asm/unaligned.h>
16
-#include <dm/ofnode.h>
11
+#include <linux/libfdt.h>
1712 #include <linux/list.h>
18
-#include <asm/arch/fit.h>
19
-#include <asm/arch/uimage.h>
2013 #include <asm/arch/resource_img.h>
14
+#include <asm/arch/uimage.h>
15
+#include <asm/arch/fit.h>
2116
2217 DECLARE_GLOBAL_DATA_PTR;
2318
2419 #define PART_RESOURCE "resource"
2520 #define RESOURCE_MAGIC "RSCE"
2621 #define RESOURCE_MAGIC_SIZE 4
27
-#define RESOURCE_VERSION 0
28
-#define CONTENT_VERSION 0
2922 #define ENTRY_TAG "ENTR"
3023 #define ENTRY_TAG_SIZE 4
3124 #define MAX_FILE_NAME_LEN 220
....@@ -70,7 +63,7 @@
7063 */
7164
7265 /**
73
- * struct resource_image_header
66
+ * struct resource_img_hdr
7467 *
7568 * @magic: should be "RSCE"
7669 * @version: resource image version, current is 0
....@@ -80,7 +73,6 @@
8073 * @e_blks: the size(by block) of the entry in the contents
8174 * @e_num: numbers of the entrys.
8275 */
83
-
8476 struct resource_img_hdr {
8577 char magic[4];
8678 uint16_t version;
....@@ -96,499 +88,406 @@
9688 char name[MAX_FILE_NAME_LEN];
9789 char hash[MAX_HASH_LEN];
9890 uint32_t hash_size;
99
- uint32_t f_offset; /* Sector offset */
100
- uint32_t f_size; /* Bytes */
91
+ uint32_t blk_offset;
92
+ uint32_t size; /* in byte */
10193 };
10294
103
-LIST_HEAD(entrys_head);
104
-LIST_HEAD(entrys_dtbs_head);
95
+LIST_HEAD(entry_head);
10596
106
-__weak int board_resource_dtb_accepted(char *dtb_name)
97
+static int resource_check_header(struct resource_img_hdr *hdr)
10798 {
108
- return 1;
99
+ return memcmp(RESOURCE_MAGIC, hdr->magic, RESOURCE_MAGIC_SIZE);
109100 }
110101
111
-int resource_image_check_header(void *rsce_hdr)
102
+static void resource_dump(struct resource_file *f)
112103 {
113
- struct resource_img_hdr *hdr = rsce_hdr;
114
- int ret;
115
-
116
- ret = memcmp(RESOURCE_MAGIC, hdr->magic, RESOURCE_MAGIC_SIZE);
117
- if (ret) {
118
- debug("bad resource image magic: %s\n",
119
- hdr->magic ? hdr->magic : "none");
120
- ret = -EINVAL;
121
- }
122
-
123
- debug("resource image header:\n");
124
- debug("magic:%s\n", hdr->magic);
125
- debug("version:%d\n", hdr->version);
126
- debug("c_version:%d\n", hdr->c_version);
127
- debug("blks:%d\n", hdr->blks);
128
- debug("c_offset:%d\n", hdr->c_offset);
129
- debug("e_blks:%d\n", hdr->e_blks);
130
- debug("e_num:%d\n", hdr->e_nums);
131
-
132
- return ret;
104
+ printf("%s\n", f->name);
105
+ printf(" blk_start: 0x%08lx\n", (ulong)f->blk_start);
106
+ printf(" blk_offset: 0x%08lx\n", (ulong)f->blk_offset);
107
+ printf(" size: 0x%08x\n", f->size);
108
+ printf(" in_ram: %d\n", f->in_ram);
109
+ printf(" hash_size: %d\n\n", f->hash_size);
133110 }
134111
135
-static int add_file_to_list(struct resource_entry *entry, int rsce_base, bool ram)
112
+static int resource_add_file(const char *name, u32 size,
113
+ u32 blk_start, u32 blk_offset,
114
+ char *hash, u32 hash_size,
115
+ bool in_ram)
136116 {
137
- struct resource_file *file;
138
-
139
- if (memcmp(entry->tag, ENTRY_TAG, ENTRY_TAG_SIZE)) {
140
- debug("invalid entry tag\n");
141
- return -ENOENT;
142
- }
143
-
144
- file = malloc(sizeof(*file));
145
- if (!file) {
146
- debug("out of memory\n");
147
- return -ENOMEM;
148
- }
149
-
150
- strcpy(file->name, entry->name);
151
- file->rsce_base = rsce_base;
152
- file->f_offset = entry->f_offset;
153
- file->f_size = entry->f_size;
154
- file->hash_size = entry->hash_size;
155
- file->ram = ram;
156
- memcpy(file->hash, entry->hash, entry->hash_size);
157
- INIT_LIST_HEAD(&file->dtbs);
158
- list_add_tail(&file->link, &entrys_head);
159
- if (strstr(file->name, DTB_SUFFIX) && board_resource_dtb_accepted(file->name))
160
- list_add_tail(&file->dtbs, &entrys_dtbs_head);
161
- debug("ENTRY: addr: %p, name: %18s, base: 0x%08x, offset: 0x%08x, size: 0x%08x\n",
162
- entry, file->name, file->rsce_base, file->f_offset, file->f_size);
163
-
164
- return 0;
165
-}
166
-
167
-int resource_replace_entry(const char *f_name, uint32_t base,
168
- uint32_t f_offset, uint32_t f_size)
169
-{
170
- struct resource_entry *entry;
171
- struct resource_file *file;
117
+ struct resource_file *f;
172118 struct list_head *node;
119
+ bool _new = true;
173120
174
- if (!f_name || !f_size)
175
- return -EINVAL;
176
-
177
- entry = calloc(1, sizeof(*entry));
178
- if (!entry)
179
- return -ENOMEM;
180
-
181
- strcpy(entry->tag, ENTRY_TAG);
182
- strcpy(entry->name, f_name);
183
- entry->f_offset = f_offset;
184
- entry->f_size = f_size;
185
- entry->hash_size = 0;
186
-
187
- /* Delete exist entry, then add this new */
188
- list_for_each(node, &entrys_head) {
189
- file = list_entry(node, struct resource_file, link);
190
- if (!strcmp(file->name, entry->name)) {
191
- list_del(&file->link);
192
- list_del(&file->dtbs);
193
- free(file);
121
+ /* old one ? */
122
+ list_for_each(node, &entry_head) {
123
+ f = list_entry(node, struct resource_file, link);
124
+ if (!strcmp(f->name, name)) {
125
+ _new = false;
194126 break;
195127 }
196128 }
197129
198
- add_file_to_list(entry, base, false);
199
- free(entry);
130
+ if (_new) {
131
+ f = calloc(1, sizeof(*f));
132
+ if (!f)
133
+ return -ENOMEM;
134
+
135
+ list_add_tail(&f->link, &entry_head);
136
+ }
137
+
138
+ strcpy(f->name, name);
139
+ f->size = size;
140
+ f->in_ram = in_ram;
141
+ f->blk_start = blk_start;
142
+ f->blk_offset = blk_offset;
143
+ f->hash_size = hash_size;
144
+ memcpy(f->hash, hash, hash_size);
145
+#ifdef DEBUG
146
+ resource_dump(f);
147
+#endif
148
+ return 0;
149
+}
150
+
151
+static int resource_setup_list(struct blk_desc *desc, ulong blk_start,
152
+ void *resc_hdr, bool in_ram)
153
+{
154
+ struct resource_img_hdr *hdr = resc_hdr;
155
+ struct resource_entry *et;
156
+ u32 i, stride;
157
+ void *pos;
158
+
159
+ pos = (void *)hdr + hdr->c_offset * desc->blksz;
160
+ stride = hdr->e_blks * desc->blksz;
161
+
162
+ for (i = 0; i < hdr->e_nums; i++) {
163
+ et = pos + (i * stride);
164
+ if (memcmp(et->tag, ENTRY_TAG, ENTRY_TAG_SIZE))
165
+ continue;
166
+
167
+ resource_add_file(et->name, et->size,
168
+ blk_start, et->blk_offset,
169
+ et->hash, et->hash_size, in_ram);
170
+ }
200171
201172 return 0;
202173 }
203174
204
-int resource_create_ram_list(struct blk_desc *dev_desc, void *rsce_hdr)
175
+int resource_setup_ram_list(struct blk_desc *desc, void *hdr)
205176 {
206
- struct resource_img_hdr *hdr = rsce_hdr;
207
- struct resource_entry *entry;
208
- int e_num, size;
209
- void *data;
210
- int ret = 0;
177
+ if (!desc)
178
+ return -ENODEV;
211179
212
- if (resource_image_check_header(hdr)) {
213
- ret = -EINVAL;
214
- goto out;
180
+ if (resource_check_header(hdr)) {
181
+ printf("RESC: invalid\n");
182
+ return -EINVAL;
215183 }
216184
217
- list_del_init(&entrys_head);
218
- list_del_init(&entrys_dtbs_head);
219
- data = (void *)((ulong)hdr + hdr->c_offset * dev_desc->blksz);
220
- for (e_num = 0; e_num < hdr->e_nums; e_num++) {
221
- size = e_num * hdr->e_blks * dev_desc->blksz;
222
- entry = (struct resource_entry *)(data + size);
223
- add_file_to_list(entry, (ulong)hdr, true);
185
+ /* @blk_start: set as 'hdr' point addr, to be used in byte */
186
+ return resource_setup_list(desc, (ulong)hdr, hdr, true);
187
+}
188
+
189
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
190
+/*
191
+ * Add logo.bmp and logo_kernel.bmp from "logo" parititon
192
+ *
193
+ * Provide a "logo" partition for user to store logo.bmp and
194
+ * logo_kernel.bmp, so that the user can update them from
195
+ * kernel or user-space dynamically.
196
+ *
197
+ * "logo" partition layout, do not change order:
198
+ *
199
+ * |----------------------| 0x00
200
+ * | raw logo.bmp |
201
+ * |----------------------| -> 512-byte aligned
202
+ * | raw logo_kernel.bmp |
203
+ * |----------------------|
204
+ *
205
+ * N: the sector count of logo.bmp
206
+ *
207
+ * How to generate:
208
+ * cat logo.bmp > logo.img && truncate -s %512 logo.img && cat logo_kernel.bmp >> logo.img
209
+ */
210
+static int resource_setup_logo_bmp(struct blk_desc *desc)
211
+{
212
+ struct bmp_header *header;
213
+ const char *name[] = { "logo.bmp", "logo_kernel.bmp" };
214
+ disk_partition_t part;
215
+ u32 blk_offset = 0;
216
+ u32 filesz;
217
+ int ret, i;
218
+
219
+ if (part_get_info_by_name(desc, PART_LOGO, &part) < 0)
220
+ return 0;
221
+
222
+ header = memalign(ARCH_DMA_MINALIGN, desc->blksz);
223
+ if (!header)
224
+ return -ENOMEM;
225
+
226
+ for (i = 0; i < ARRAY_SIZE(name); i++) {
227
+ if (blk_dread(desc, part.start + blk_offset, 1, header) != 1) {
228
+ ret = -EIO;
229
+ break;
230
+ }
231
+
232
+ if (header->signature[0] != 'B' || header->signature[1] != 'M') {
233
+ ret = -EINVAL;
234
+ break;
235
+ }
236
+
237
+ filesz = get_unaligned_le32(&header->file_size);
238
+ ret = resource_add_file(name[i], filesz, part.start, blk_offset,
239
+ NULL, 0, false);
240
+ if (ret)
241
+ break;
242
+
243
+ /* move to next file */
244
+ blk_offset += DIV_ROUND_UP(filesz, desc->blksz);
245
+
246
+ printf("LOGO: %s\n", name[i]);
247
+
224248 }
225
-out:
226
- resource_read_logo_bmps();
249
+
250
+ free(header);
227251
228252 return ret;
229253 }
230254
231
-static int resource_create_list(struct blk_desc *dev_desc, int rsce_base)
255
+static int resource_setup_blk_list(struct blk_desc *desc, ulong blk_start)
232256 {
233257 struct resource_img_hdr *hdr;
234
- struct resource_entry *entry;
235
- int blknum, e_num;
236
- void *data = NULL;
258
+ int blk_cnt;
237259 int ret = 0;
238
- int size;
260
+ void *buf;
239261
240
- hdr = memalign(ARCH_DMA_MINALIGN, dev_desc->blksz);
262
+ hdr = memalign(ARCH_DMA_MINALIGN, desc->blksz);
241263 if (!hdr)
242264 return -ENOMEM;
243265
244
- if (blk_dread(dev_desc, rsce_base, 1, hdr) != 1) {
245
- printf("Failed to read resource hdr\n");
266
+ if (blk_dread(desc, blk_start, 1, hdr) != 1) {
246267 ret = -EIO;
247
- goto err;
268
+ goto out;
248269 }
249270
250
- if (resource_image_check_header(hdr)) {
271
+ if (resource_check_header(hdr)) {
272
+ printf("RESC: invalid\n");
251273 if (fdt_check_header(hdr)) {
252
- printf("No valid resource or dtb file\n");
253274 ret = -EINVAL;
254
- goto err;
275
+ goto out;
255276 } else {
256
- free(hdr);
257
- return resource_replace_entry(DEFAULT_DTB_FILE, rsce_base,
258
- 0, fdt_totalsize(hdr));
277
+ /* this is a dtb file */
278
+ printf("RESC: this is dtb\n");
279
+ ret = resource_add_file(DEFAULT_DTB_FILE,
280
+ fdt_totalsize(hdr),
281
+ blk_start, 0, NULL, 0, false);
282
+ goto out;
259283 }
260284 }
261285
262
- blknum = hdr->e_blks * hdr->e_nums;
263
- data = memalign(ARCH_DMA_MINALIGN, blknum * dev_desc->blksz);
264
- if (!data) {
286
+ blk_cnt = hdr->e_blks * hdr->e_nums;
287
+ hdr = realloc(hdr, (1 + blk_cnt) * desc->blksz);
288
+ if (!hdr) {
265289 ret = -ENOMEM;
266
- goto err;
290
+ goto out;
267291 }
268292
269
- if (blk_dread(dev_desc, rsce_base + hdr->c_offset,
270
- blknum, data) != blknum) {
271
- printf("Failed to read resource entries\n");
293
+ buf = (void *)hdr + desc->blksz;
294
+ if (blk_dread(desc, blk_start + hdr->c_offset, blk_cnt, buf) != blk_cnt) {
272295 ret = -EIO;
273
- goto err;
296
+ goto out;
274297 }
275298
276
- /*
277
- * Add all file into resource file list, and load what we want from
278
- * storage when we really need it.
279
- */
280
- for (e_num = 0; e_num < hdr->e_nums; e_num++) {
281
- size = e_num * hdr->e_blks * dev_desc->blksz;
282
- entry = (struct resource_entry *)(data + size);
283
- add_file_to_list(entry, rsce_base, false);
284
- }
285
-
286
-err:
287
- if (data)
288
- free(data);
289
- if (hdr)
290
- free(hdr);
291
-
292
- resource_read_logo_bmps();
299
+ resource_setup_list(desc, blk_start, hdr, false);
300
+ resource_setup_logo_bmp(desc);
301
+out:
302
+ free(hdr);
293303
294304 return ret;
295305 }
296306
297
-static int read_dtb_from_android(struct blk_desc *dev_desc,
298
- struct andr_img_hdr *hdr,
299
- ulong rsce_base)
307
+static int resource_init(struct blk_desc *desc,
308
+ disk_partition_t *part,
309
+ ulong blk_offset)
300310 {
301
- ulong dtb_offset = 0;
302
- ulong dtb_size = 0;
311
+ printf("RESC: '%s', blk@0x%08lx\n", part->name, part->start + blk_offset);
303312
304
- if (!hdr || hdr->header_version <= 1) {
305
- return 0;
306
- } else if (hdr->header_version == 2) {
307
- dtb_offset += hdr->page_size;
308
- dtb_offset += ALIGN(hdr->kernel_size, hdr->page_size);
309
- dtb_offset += ALIGN(hdr->ramdisk_size, hdr->page_size);
310
- dtb_offset += ALIGN(hdr->recovery_dtbo_size, hdr->page_size) +
311
- ALIGN(hdr->second_size, hdr->page_size);
312
- dtb_size = hdr->dtb_size;
313
- } else if (hdr->header_version >= 3) {
314
- ulong vendor_boot_hdr_size = (hdr->header_version == 3) ?
315
- VENDOR_BOOT_HDRv3_SIZE : VENDOR_BOOT_HDRv4_SIZE;
313
+#ifdef CONFIG_ANDROID_AVB
314
+ char hdr[512];
315
+ ulong resc_buf = 0;
316
+ int ret;
316317
317
- dtb_offset += ALIGN(vendor_boot_hdr_size,
318
- hdr->vendor_page_size) +
319
- ALIGN(hdr->vendor_ramdisk_size,
320
- hdr->vendor_page_size);
321
- dtb_size = hdr->dtb_size;
318
+ if (blk_dread(desc, part->start, 1, hdr) != 1)
319
+ return -EIO;
320
+
321
+ /* only handle android boot/recovery.img and resource.img, ignore fit */
322
+ if (!android_image_check_header((void *)hdr) ||
323
+ !resource_check_header((void *)hdr)) {
324
+ ret = android_image_verify_resource((const char *)part->name, &resc_buf);
325
+ if (ret) {
326
+ printf("RESC: '%s', avb verify fail: %d\n", part->name, ret);
327
+ return ret;
328
+ }
329
+
330
+ /*
331
+ * unlock=0: resc_buf is valid and file was already full load in ram.
332
+ * unlock=1: resc_buf is 0.
333
+ */
334
+ if (resc_buf && !resource_check_header((void *)resc_buf))
335
+ return resource_setup_ram_list(desc, (void *)resc_buf);
322336 }
337
+#endif
323338
324
- if (!dtb_size)
325
- return 0;
339
+ return resource_setup_blk_list(desc, part->start + blk_offset);
340
+}
326341
327
- /*
328
- * boot_img_hdr_v234 feature.
329
- *
330
- * If dtb position is present, replace the old with new one if
331
- * we don't need to verify DTB hash from resource.img file entry.
332
- */
333
- dtb_offset = DIV_ROUND_UP(dtb_offset, dev_desc->blksz);
334
- env_update("bootargs", "androidboot.dtb_idx=0");
342
+static int resource_default(struct blk_desc *desc,
343
+ disk_partition_t *out_part,
344
+ ulong *out_blk_offset)
345
+{
346
+ disk_partition_t part;
347
+
348
+ if (part_get_info_by_name(desc, PART_RESOURCE, &part) < 0)
349
+ return -ENODEV;
350
+
351
+ *out_part = part;
352
+ *out_blk_offset = 0;
335353
336354 return 0;
337355 }
356
+#endif
338357
339
-static int get_resource_base_sector(struct blk_desc *dev_desc,
340
- struct andr_img_hdr **ret_hdr)
358
+static int resource_scan(void)
341359 {
360
+ struct blk_desc *desc = rockchip_get_bootdev();
361
+ __maybe_unused int ret;
362
+
363
+ if (!desc) {
364
+ printf("RESC: No bootdev\n");
365
+ return -ENODEV;
366
+ }
367
+
368
+ if (!list_empty(&entry_head))
369
+ return 0;
370
+
371
+#ifdef CONFIG_ROCKCHIP_FIT_IMAGE
372
+ ret = fit_image_init_resource(desc);
373
+ if (!ret || ret != -EAGAIN)
374
+ return ret;
375
+#endif
376
+#ifdef CONFIG_ROCKCHIP_UIMAGE
377
+ ret = uimage_init_resource(desc);
378
+ if (!ret || ret != -EAGAIN)
379
+ return ret;
380
+#endif
381
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
342382 disk_partition_t part;
343
- int rsce_base = 0;
344
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
345
- struct andr_img_hdr *hdr;
346
- u32 os_ver = 0, os_lvl;
347
- const char *part_boot = PART_BOOT;
383
+ ulong blk_offset;
384
+ char hdr[512];
385
+ char name[32];
348386
349
- /*
350
- * Anyway, we must read android hdr firstly from boot/recovery partition
351
- * to get the 'os_version' for android_bcb_msg_sector_offset(), in order
352
- * to confirm BCB message offset of *MISC* partition.
353
- */
354
-#ifdef CONFIG_ANDROID_AB
355
- part_boot = ab_can_find_recovery_part() ? PART_RECOVERY : PART_BOOT;
356
-#endif
387
+ /* partition priority: boot/recovery > resource */
388
+ if (!android_image_init_resource(desc, &part, &blk_offset)) {
389
+ if (blk_dread(desc, part.start + blk_offset, 1, hdr) != 1)
390
+ return -EIO;
357391
358
- if (part_get_info_by_name(dev_desc, part_boot, &part) < 0)
359
- goto resource_part;
392
+ if (resource_check_header((void *)hdr)) {
393
+ strcpy(name, (char *)part.name);
394
+ if (resource_default(desc, &part, &blk_offset))
395
+ return -ENOENT;
360396
361
- hdr = populate_andr_img_hdr(dev_desc, &part);
362
- if (hdr) {
363
- os_ver = hdr->os_version >> 11;
364
- os_lvl = hdr->os_version & ((1U << 11) - 1);
365
- if (os_ver)
366
- gd->bd->bi_andr_version = hdr->os_version;
367
- }
368
-
369
-#ifndef CONFIG_ANDROID_AB
370
- /* Get boot mode from misc and read if recovery mode */
371
- if (rockchip_get_boot_mode() == BOOT_MODE_RECOVERY) {
372
- if (hdr)
373
- free(hdr);
374
-
375
- if (part_get_info_by_name(dev_desc, PART_RECOVERY, &part) < 0)
376
- goto resource_part;
377
-
378
- hdr = populate_andr_img_hdr(dev_desc, &part);
379
- if (!hdr)
380
- goto resource_part;
381
- }
382
-#endif
383
- /* If Android v012, getting resource from second position ! */
384
- if (hdr) {
385
- if (os_ver)
386
- printf("Android %u.%u, Build %u.%u, v%d\n",
387
- (os_ver >> 14) & 0x7F, (os_ver >> 7) & 0x7F,
388
- (os_lvl >> 4) + 2000, os_lvl & 0x0F,
389
- hdr->header_version);
390
- *ret_hdr = hdr;
391
- if (hdr->header_version < 3) {
392
- rsce_base = part.start * dev_desc->blksz;
393
- rsce_base += hdr->page_size;
394
- rsce_base += ALIGN(hdr->kernel_size, hdr->page_size);
395
- rsce_base += ALIGN(hdr->ramdisk_size, hdr->page_size);
396
- rsce_base = DIV_ROUND_UP(rsce_base, dev_desc->blksz);
397
- goto finish;
397
+ printf("RESC: '%s' -> '%s'\n", name, part.name);
398398 }
399
- }
400
-resource_part:
401
-#endif
402
- /* resource partition */
403
- if (part_get_info_by_name(dev_desc, PART_RESOURCE, &part) < 0) {
404
- printf("No resource partition\n");
405
- return -ENODEV;
406399 } else {
407
- rsce_base = part.start;
400
+ if (resource_default(desc, &part, &blk_offset))
401
+ return -ENOENT;
408402 }
409
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
410
-finish:
403
+
404
+ /* now, 'part' can be boot/recovery/resource */
405
+ return resource_init(desc, &part, blk_offset);
411406 #endif
412
- printf("Found DTB in %s part\n", part.name);
413
-
414
- return rsce_base;
407
+ return -ENOENT;
415408 }
416409
417
-/*
418
- * There are: logo/battery pictures and dtb file in the resource image by default.
419
- *
420
- * This function does:
421
- *
422
- * 1. Get resource image base sector from: boot/recovery(AOSP) > resource(RK)
423
- * 2. Create resource files list(addition: add logo bmps)
424
- * 3. Add dtb from android v2 dtb pos, override the old one from resource file
425
- */
426
-int resource_init_list(void)
410
+static struct resource_file *resource_get_file(const char *name)
427411 {
428
- struct andr_img_hdr *hdr = NULL;
429
- struct blk_desc *dev_desc;
430
- int rsce_base;
431
-
432
- dev_desc = rockchip_get_bootdev();
433
- if (!dev_desc) {
434
- printf("No dev_desc!\n");
435
- return -ENODEV;
436
- }
437
-
438
- rsce_base = get_resource_base_sector(dev_desc, &hdr);
439
- if (rsce_base > 0) {
440
- if (resource_create_list(dev_desc, rsce_base))
441
- printf("Failed to create resource list\n");
442
- }
443
-
444
- /* override the resource dtb with android dtb if need */
445
- return read_dtb_from_android(dev_desc, hdr, rsce_base);
446
-}
447
-
448
-int resource_is_empty(void)
449
-{
450
- return list_empty(&entrys_head);
451
-}
452
-
453
-static struct resource_file *get_file_info(const char *name)
454
-{
455
- struct resource_file *file;
412
+ struct resource_file *f;
456413 struct list_head *node;
457414
458
- if (list_empty(&entrys_head)) {
459
- if (resource_init_list())
460
- return NULL;
461
- }
415
+ if (resource_scan())
416
+ return NULL;
462417
463
- list_for_each(node, &entrys_head) {
464
- file = list_entry(node, struct resource_file, link);
465
- if (!strcmp(file->name, name))
466
- return file;
418
+ list_for_each(node, &entry_head) {
419
+ f = list_entry(node, struct resource_file, link);
420
+ if (!strcmp(f->name, name))
421
+ return f;
467422 }
468423
469424 return NULL;
470425 }
471426
472
-/*
473
- * read file from resource partition
474
- * @buf: destination buf to store file data;
475
- * @name: file name
476
- * @offset: blocks offset in the file, 1 block = 512 bytes
477
- * @len: the size(by bytes) of file to read.
478
- */
479
-int rockchip_read_resource_file(void *buf, const char *name, int offset, int len)
427
+int rockchip_read_resource_file(void *buf, const char *name, int blk_offset, int len)
480428 {
481
- struct resource_file *file;
482
- struct blk_desc *dev_desc;
483
- int ret = 0;
484
- int blks;
485
- ulong src;
429
+ struct blk_desc *desc = rockchip_get_bootdev();
430
+ struct resource_file *f;
431
+ int blk_cnt;
432
+ ulong pos;
486433
487
- file = get_file_info(name);
488
- if (!file) {
489
- printf("No file: %s\n", name);
434
+ if (!desc)
435
+ return -ENODEV;
436
+
437
+ f = resource_get_file(name);
438
+ if (!f) {
439
+ printf("No resource file: %s\n", name);
490440 return -ENOENT;
491441 }
492442
493
- dev_desc = rockchip_get_bootdev();
494
- if (!dev_desc) {
495
- printf("No dev_desc!\n");
496
- return -ENODEV;
497
- }
443
+ if (len <= 0 || len > f->size)
444
+ len = f->size;
498445
499
- if (len <= 0 || len > file->f_size)
500
- len = file->f_size;
501
-
502
- if (file->ram) {
503
- src = file->rsce_base +
504
- (file->f_offset + offset) * dev_desc->blksz;
505
- memcpy(buf, (char *)src, len);
506
- ret = len;
446
+ if (f->in_ram) {
447
+ pos = f->blk_start + (f->blk_offset + blk_offset) * desc->blksz;
448
+ memcpy(buf, (char *)pos, len);
507449 } else {
508
- blks = DIV_ROUND_UP(len, dev_desc->blksz);
509
- ret = blk_dread(dev_desc,
510
- file->rsce_base + file->f_offset + offset,
511
- blks, buf);
512
- ret = (ret != blks) ? -EIO : len;
450
+ blk_cnt = DIV_ROUND_UP(len, desc->blksz);
451
+ if (blk_dread(desc,
452
+ f->blk_start + f->blk_offset + blk_offset,
453
+ blk_cnt, buf) != blk_cnt)
454
+ len = -EIO;
513455 }
514456
515
- return ret;
457
+ return len;
516458 }
517459
518
-static struct resource_file *get_default_dtb(void)
519
-{
520
- struct resource_file *target_file = NULL;
521
- struct resource_file *file;
522
- struct list_head *node;
523
- int num = 0;
524
-
525
- if (list_empty(&entrys_head)) {
526
- if (resource_init_list())
527
- return NULL;
528
- }
529
-
530
- list_for_each(node, &entrys_dtbs_head) {
531
- num++;
532
- file = list_entry(node, struct resource_file, dtbs);
533
- if (strcmp(file->name, DEFAULT_DTB_FILE))
534
- target_file = file;
535
- }
536
-
537
- /*
538
- * two possible case:
539
- * case 1. rk-kernel.dtb only
540
- * case 2. targe_file(s) + rk-kernel.dtb(maybe they are the same),
541
- * use (last)target_file as result one.
542
- */
543
- if (num > 2)
544
- printf("Error: find duplicate(%d) dtbs\n", num);
545
-
546
- return target_file ? : get_file_info(DEFAULT_DTB_FILE);
547
-}
460
+extern struct resource_file *resource_read_hwid_dtb(void);
548461
549462 int rockchip_read_resource_dtb(void *fdt_addr, char **hash, int *hash_size)
550463 {
551
- struct resource_file *file = NULL;
464
+ struct resource_file *f = NULL;
552465 int ret;
553466
554467 #ifdef CONFIG_ROCKCHIP_HWID_DTB
555
- file = resource_read_hwid_dtb();
556
-#endif
557
- /* If no dtb matches hardware id(GPIO/ADC), use the default */
558
- if (!file)
559
- file = get_default_dtb();
468
+ if (resource_scan())
469
+ return -ENOENT;
560470
561
- if (!file)
471
+ f = resource_read_hwid_dtb();
472
+#endif
473
+ /* If no dtb match hardware id(GPIO/ADC), use the default */
474
+ if (!f)
475
+ f = resource_get_file(DEFAULT_DTB_FILE);
476
+
477
+ if (!f)
562478 return -ENODEV;
563479
564
- ret = rockchip_read_resource_file(fdt_addr, file->name, 0, 0);
480
+ ret = rockchip_read_resource_file(fdt_addr, f->name, 0, 0);
565481 if (ret < 0)
566482 return ret;
567483
568484 if (fdt_check_header(fdt_addr))
569485 return -EBADF;
570486
571
- *hash = file->hash;
572
- *hash_size = file->hash_size;
573
- printf("DTB: %s\n", file->name);
487
+ *hash = f->hash;
488
+ *hash_size = f->hash_size;
574489
575
- return 0;
576
-}
577
-
578
-int resource_traverse_init_list(void)
579
-{
580
- if (!resource_is_empty())
581
- return 0;
582
-
583
-#ifdef CONFIG_ROCKCHIP_FIT_IMAGE
584
- if (!fit_image_init_resource())
585
- return 0;
586
-#endif
587
-#ifdef CONFIG_ROCKCHIP_UIMAGE
588
- if (!uimage_init_resource())
589
- return 0;
590
-#endif
591
- /* Android image is default supported within resource core */
490
+ printf("DTB: %s\n", f->name);
592491
593492 return 0;
594493 }
....@@ -596,30 +495,20 @@
596495 static int do_dump_resource(cmd_tbl_t *cmdtp, int flag,
597496 int argc, char *const argv[])
598497 {
599
- struct resource_file *file;
498
+ struct resource_file *f;
600499 struct list_head *node;
601500
602
- printf("Resources:\n");
603
- list_for_each(node, &entrys_head) {
604
- file = list_entry(node, struct resource_file, link);
605
- printf(" %s: 0x%08x(sector), 0x%08x(bytes)\n",
606
- file->name, file->rsce_base + file->f_offset, file->f_size);
501
+ list_for_each(node, &entry_head) {
502
+ f = list_entry(node, struct resource_file, link);
503
+ resource_dump(f);
607504 }
608505
609
-#ifdef CONFIG_ROCKCHIP_HWID_DTB
610
- printf("DTBs:\n");
611
- list_for_each(node, &entrys_dtbs_head) {
612
- file = list_entry(node, struct resource_file, dtbs);
613
- printf(" %s: 0x%08x(sector),0x%08x(bytes)\n",
614
- file->name, file->rsce_base + file->f_offset, file->f_size);
615
- }
616
-#endif
617506 return 0;
618507 }
619508
620509 U_BOOT_CMD(
621510 dump_resource, 1, 1, do_dump_resource,
622
- "dump resource list",
511
+ "dump resource files",
623512 ""
624513 );
625514
u-boot/arch/arm/mach-rockchip/resource_logo.c
deleted file mode 100644
....@@ -1,95 +0,0 @@
1
-/*
2
- * (C) Copyright 2021 Rockchip Electronics Co., Ltd
3
- *
4
- * SPDX-License-Identifier: GPL-2.0+
5
- */
6
-#include <common.h>
7
-#include <adc.h>
8
-#include <boot_rkimg.h>
9
-#include <bmp_layout.h>
10
-#include <malloc.h>
11
-#include <asm/io.h>
12
-#include <asm/unaligned.h>
13
-#include <asm/arch/resource_img.h>
14
-#include <dm/ofnode.h>
15
-
16
-static int read_bmp(struct blk_desc *dev_desc, const char *name,
17
- disk_partition_t *part, uint32_t offset,
18
- uint32_t *size)
19
-{
20
- struct bmp_header *header;
21
- u32 blk_offset;
22
- u32 filesz;
23
- int ret;
24
-
25
- blk_offset = DIV_ROUND_UP(offset, dev_desc->blksz);
26
- header = memalign(ARCH_DMA_MINALIGN, dev_desc->blksz);
27
- if (!header) {
28
- ret = -ENOMEM;
29
- goto out;
30
- }
31
-
32
- if (blk_dread(dev_desc, part->start + blk_offset, 1, header) != 1) {
33
- ret = -EIO;
34
- goto out;
35
- }
36
-
37
- if (header->signature[0] != 'B' || header->signature[1] != 'M') {
38
- ret = -EINVAL;
39
- goto out;
40
- }
41
-
42
- filesz = get_unaligned_le32(&header->file_size);
43
- ret = resource_replace_entry(name, part->start, blk_offset, filesz);
44
- if (!ret) {
45
- printf("LOGO: %s\n", name);
46
- if (size)
47
- *size = filesz;
48
- }
49
-out:
50
- free(header);
51
-
52
- return ret;
53
-}
54
-
55
-/*
56
- * Add logo.bmp and logo_kernel.bmp from "logo" parititon
57
- *
58
- * Provide a "logo" partition for user to store logo.bmp and
59
- * logo_kernel.bmp, so that the user can update them from
60
- * kernel or user-space dynamically.
61
- *
62
- * "logo" partition layout, do not change order:
63
- *
64
- * |----------------------| 0x00
65
- * | raw logo.bmp |
66
- * |----------------------| N*512-byte aligned
67
- * | raw logo_kernel.bmp |
68
- * |----------------------|
69
- *
70
- * N: the sector count of logo.bmp
71
- *
72
- * How to generate:
73
- * cat logo.bmp > logo.img && truncate -s %512 logo.img && cat logo_kernel.bmp >> logo.img
74
- */
75
-int resource_read_logo_bmps(void)
76
-{
77
- struct blk_desc *dev_desc;
78
- disk_partition_t part;
79
- u32 filesz;
80
-
81
- dev_desc = rockchip_get_bootdev();
82
- if (!dev_desc) {
83
- printf("No dev_desc!\n");
84
- return -ENODEV;
85
- }
86
-
87
- if (part_get_info_by_name(dev_desc, PART_LOGO, &part) < 0)
88
- return -ENODEV;
89
-
90
- if (!read_bmp(dev_desc, "logo.bmp", &part, 0, &filesz))
91
- read_bmp(dev_desc, "logo_kernel.bmp", &part, filesz, NULL);
92
-
93
- return 0;
94
-}
95
-
u-boot/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c
....@@ -18,4 +18,7 @@
1818 .name = "rk3036_syscon",
1919 .id = UCLASS_SYSCON,
2020 .of_match = rk3036_syscon_ids,
21
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
22
+ .bind = dm_scan_fdt_dev,
23
+#endif
2124 };
u-boot/arch/arm/mach-rockchip/rk3528/Kconfig
....@@ -0,0 +1,17 @@
1
+if ROCKCHIP_RK3528
2
+
3
+config TARGET_EVB_RK3528
4
+ bool "EVB_RK3528"
5
+ select BOARD_LATE_INIT
6
+ help
7
+ RK3528 EVB is a evaluation board for Rockchp RK3528.
8
+
9
+config SYS_SOC
10
+ default "rockchip"
11
+
12
+config SYS_MALLOC_F_LEN
13
+ default 0x400
14
+
15
+source board/rockchip/evb_rk3528/Kconfig
16
+
17
+endif
u-boot/arch/arm/mach-rockchip/rk3528/Makefile
....@@ -0,0 +1,11 @@
1
+#
2
+# (C) Copyright 2020 Rockchip Electronics Co., Ltd
3
+#
4
+# SPDX-License-Identifier: GPL-2.0+
5
+#
6
+
7
+ifneq ($(CONFIG_TPL_BUILD)$(CONFIG_TPL_TINY_FRAMEWORK),yy)
8
+obj-y += syscon_rk3528.o
9
+endif
10
+obj-y += rk3528.o
11
+obj-y += clk_rk3528.o
u-boot/arch/arm/mach-rockchip/rk3528/clk_rk3528.c
....@@ -0,0 +1,41 @@
1
+/*
2
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd.
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+
7
+#include <common.h>
8
+#include <dm.h>
9
+#include <syscon.h>
10
+#include <asm/arch/clock.h>
11
+#include <asm/arch/cru_rk3528.h>
12
+
13
+int rockchip_get_clk(struct udevice **devp)
14
+{
15
+ return uclass_get_device_by_driver(UCLASS_CLK,
16
+ DM_GET_DRIVER(rockchip_rk3528_cru), devp);
17
+}
18
+
19
+#if CONFIG_IS_ENABLED(CLK_SCMI)
20
+int rockchip_get_scmi_clk(struct udevice **devp)
21
+{
22
+ return uclass_get_device_by_driver(UCLASS_CLK,
23
+ DM_GET_DRIVER(scmi_clock), devp);
24
+}
25
+#endif
26
+
27
+void *rockchip_get_cru(void)
28
+{
29
+ struct rk3528_clk_priv *priv;
30
+ struct udevice *dev;
31
+ int ret;
32
+
33
+ ret = rockchip_get_clk(&dev);
34
+ if (ret)
35
+ return ERR_PTR(ret);
36
+
37
+ priv = dev_get_priv(dev);
38
+
39
+ return priv->cru;
40
+}
41
+
u-boot/arch/arm/mach-rockchip/rk3528/rk3528.c
....@@ -0,0 +1,494 @@
1
+/*
2
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+#include <common.h>
7
+#include <dm.h>
8
+#include <asm/io.h>
9
+#include <asm/arch/cpu.h>
10
+#include <asm/arch/hardware.h>
11
+#include <asm/arch/grf_rk3528.h>
12
+#include <asm/arch/ioc_rk3528.h>
13
+
14
+DECLARE_GLOBAL_DATA_PTR;
15
+
16
+#define FIREWALL_DDR_BASE 0xff2e0000
17
+#define FW_DDR_MST1_REG 0x44
18
+#define FW_DDR_MST6_REG 0x58
19
+#define FW_DDR_MST7_REG 0x5c
20
+#define FW_DDR_MST11_REG 0x6c
21
+#define FW_DDR_MST14_REG 0x78
22
+#define FW_DDR_MST16_REG 0x80
23
+#define FW_DDR_MST_REG 0xf0
24
+
25
+#define VENC_GRF_BASE 0xff320000
26
+#define VENC_GRF_CON1 0x4
27
+
28
+#define VPU_GRF_BASE 0xff340000
29
+#define VPU_GRF_CON4 0x14
30
+
31
+#define PMU_SGRF_BASE 0xff440000
32
+#define PMU_SGRF_SOC_CON4 0x10
33
+#define PMU_SGRF_SOC_CON5 0x14
34
+#define PMU_SGRF_SOC_CON6 0x18
35
+#define PMU_SGRF_SOC_CON8 0x20
36
+#define PMU_SGRF_SOC_CON11 0x2c
37
+
38
+#define PMU_CRU_BASE 0xff4b0000
39
+#define PMU_CRU_GATE_CON00 0x800
40
+#define PMU_CRU_SOFTRST_CON00 0xa00
41
+
42
+#define GPIO1C_IOMUX_SEL_H 0x034
43
+#define GPIO1D_IOMUX_SEL_L 0x038
44
+#define GPIO1D_IOMUX_SEL_H 0x03c
45
+
46
+#define CPU_PRIORITY_REG 0xff210008
47
+#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7))
48
+
49
+#ifdef CONFIG_ARM64
50
+#include <asm/armv8/mmu.h>
51
+
52
+static struct mm_region rk3528_mem_map[] = {
53
+ {
54
+ .virt = 0x0UL,
55
+ .phys = 0x0UL,
56
+ .size = 0xfc000000UL,
57
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
58
+ PTE_BLOCK_INNER_SHARE
59
+ }, {
60
+ .virt = 0xfc000000UL,
61
+ .phys = 0xfc000000UL,
62
+ .size = 0x04000000UL,
63
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
64
+ PTE_BLOCK_NON_SHARE |
65
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
66
+ }, {
67
+ /* List terminator */
68
+ 0,
69
+ }
70
+};
71
+
72
+struct mm_region *mem_map = rk3528_mem_map;
73
+#endif
74
+
75
+#define GPIO0_IOC_BASE 0xFF540000
76
+#define GPIO1_IOC_BASE 0xFF560000
77
+#define GPIO2_IOC_BASE 0xFF570000
78
+#define GPIO3_IOC_BASE 0xFF560000
79
+#define GPIO4_IOC_BASE 0xFF550000
80
+
81
+#define GPIO1_IOC_GPIO1D_IOMUX_SEL_L (GPIO1_IOC_BASE + 0x38)
82
+#define GPIO1_IOC_GPIO1C_DS_2 (GPIO1_IOC_BASE + 0x148)
83
+#define GPIO1_IOC_GPIO1C_DS_3 (GPIO1_IOC_BASE + 0x14C)
84
+#define GPIO1_IOC_GPIO1D_DS_0 (GPIO1_IOC_BASE + 0x150)
85
+#define GPIO1_IOC_GPIO1D_DS_1 (GPIO1_IOC_BASE + 0x154)
86
+#define GPIO1_IOC_GPIO1D_DS_2 (GPIO1_IOC_BASE + 0x158)
87
+
88
+/* uart0 iomux */
89
+/* gpio4c7 */
90
+#define UART0_RX_M0 1
91
+#define UART0_RX_M0_OFFSET 12
92
+#define UART0_RX_M0_ADDR (GPIO4_IOC_BASE + 0x94)
93
+/* gpio4d0 */
94
+#define UART0_TX_M0 1
95
+#define UART0_TX_M0_OFFSET 0
96
+#define UART0_TX_M0_ADDR (GPIO4_IOC_BASE + 0x98)
97
+
98
+/* gpio2a0 */
99
+#define UART0_RX_M1 2
100
+#define UART0_RX_M1_OFFSET 0
101
+#define UART0_RX_M1_ADDR (GPIO2_IOC_BASE + 0x40)
102
+/* gpio2a1 */
103
+#define UART0_TX_M1 2
104
+#define UART0_TX_M1_OFFSET 4
105
+#define UART0_TX_M1_ADDR (GPIO2_IOC_BASE + 0x40)
106
+
107
+/* uart1 iomux */
108
+/* gpio4a7 */
109
+#define UART1_RX_M0 2
110
+#define UART1_RX_M0_OFFSET 12
111
+#define UART1_RX_M0_ADDR (GPIO1_IOC_BASE + 0x84)
112
+/* gpio4a6 */
113
+#define UART1_TX_M0 2
114
+#define UART1_TX_M0_OFFSET 8
115
+#define UART1_TX_M0_ADDR (GPIO1_IOC_BASE + 0x84)
116
+
117
+/* gpio4c6 */
118
+#define UART1_RX_M1 2
119
+#define UART1_RX_M1_OFFSET 8
120
+#define UART1_RX_M1_ADDR (GPIO4_IOC_BASE + 0x94)
121
+/* gpio4c5 */
122
+#define UART1_TX_M1 2
123
+#define UART1_TX_M1_OFFSET 4
124
+#define UART1_TX_M1_ADDR (GPIO4_IOC_BASE + 0x94)
125
+
126
+/* uart2 iomux */
127
+/* gpio3a0 */
128
+#define UART2_RX_M0 1
129
+#define UART2_RX_M0_OFFSET 0
130
+#define UART2_RX_M0_ADDR (GPIO3_IOC_BASE + 0x60)
131
+/* gpio3a1 */
132
+#define UART2_TX_M0 1
133
+#define UART2_TX_M0_OFFSET 4
134
+#define UART2_TX_M0_ADDR (GPIO3_IOC_BASE + 0x60)
135
+
136
+/* gpio1b0 */
137
+#define UART2_RX_M1 1
138
+#define UART2_RX_M1_OFFSET 0
139
+#define UART2_RX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
140
+/* gpio1b1 */
141
+#define UART2_TX_M1 1
142
+#define UART2_TX_M1_OFFSET 4
143
+#define UART2_TX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
144
+
145
+/* uart3 iomux */
146
+/* gpio4b0 */
147
+#define UART3_RX_M0 2
148
+#define UART3_RX_M0_OFFSET 0
149
+#define UART3_RX_M0_ADDR (GPIO4_IOC_BASE + 0x88)
150
+/* gpio4b1 */
151
+#define UART3_TX_M0 2
152
+#define UART3_TX_M0_OFFSET 4
153
+#define UART3_TX_M0_ADDR (GPIO4_IOC_BASE + 0x88)
154
+
155
+/* gpio4b7 */
156
+#define UART3_RX_M1 3
157
+#define UART3_RX_M1_OFFSET 12
158
+#define UART3_RX_M1_ADDR (GPIO4_IOC_BASE + 0x8C)
159
+/* gpio4c0 */
160
+#define UART3_TX_M1 3
161
+#define UART3_TX_M1_OFFSET 0
162
+#define UART3_TX_M1_ADDR (GPIO4_IOC_BASE + 0x90)
163
+
164
+/* uart4 iomux */
165
+/* gpio2a2 */
166
+#define UART4_RX_M0 3
167
+#define UART4_RX_M0_OFFSET 8
168
+#define UART4_RX_M0_ADDR (GPIO2_IOC_BASE + 0x40)
169
+/* gpio2a3 */
170
+#define UART4_TX_M0 3
171
+#define UART4_TX_M0_OFFSET 12
172
+#define UART4_TX_M0_ADDR (GPIO2_IOC_BASE + 0x40)
173
+
174
+/* uart5 iomux */
175
+/* gpio1a2 */
176
+#define UART5_RX_M0 2
177
+#define UART5_RX_M0_OFFSET 8
178
+#define UART5_RX_M0_ADDR (GPIO1_IOC_BASE + 0x20)
179
+/* gpio1a3 */
180
+#define UART5_TX_M0 2
181
+#define UART5_TX_M0_OFFSET 12
182
+#define UART5_TX_M0_ADDR (GPIO1_IOC_BASE + 0x20)
183
+
184
+/* gpio1d4 */
185
+#define UART5_RX_M1 2
186
+#define UART5_RX_M1_OFFSET 0
187
+#define UART5_RX_M1_ADDR (GPIO1_IOC_BASE + 0x3c)
188
+/* gpio1d7 */
189
+#define UART5_TX_M1 2
190
+#define UART5_TX_M1_OFFSET 12
191
+#define UART5_TX_M1_ADDR (GPIO1_IOC_BASE + 0x3c)
192
+
193
+/* uart6 iomux */
194
+/* gpio3a7 */
195
+#define UART6_RX_M0 4
196
+#define UART6_RX_M0_OFFSET 12
197
+#define UART6_RX_M0_ADDR (GPIO3_IOC_BASE + 0x64)
198
+/* gpio3a6 */
199
+#define UART6_TX_M0 4
200
+#define UART6_TX_M0_OFFSET 8
201
+#define UART6_TX_M0_ADDR (GPIO3_IOC_BASE + 0x64)
202
+
203
+/* gpio3c3 */
204
+#define UART6_RX_M1 4
205
+#define UART6_RX_M1_OFFSET 12
206
+#define UART6_RX_M1_ADDR (GPIO3_IOC_BASE + 0x70)
207
+/* gpio3c1 */
208
+#define UART6_TX_M1 4
209
+#define UART6_TX_M1_OFFSET 4
210
+#define UART6_TX_M1_ADDR (GPIO3_IOC_BASE + 0x70)
211
+
212
+/* uart7 iomux */
213
+/* gpio3b3 */
214
+#define UART7_RX_M0 4
215
+#define UART7_RX_M0_OFFSET 12
216
+#define UART7_RX_M0_ADDR (GPIO3_IOC_BASE + 0x68)
217
+/* gpio3b2 */
218
+#define UART7_TX_M0 4
219
+#define UART7_TX_M0_OFFSET 8
220
+#define UART7_TX_M0_ADDR (GPIO3_IOC_BASE + 0x68)
221
+
222
+/* gpio1b3 */
223
+#define UART7_RX_M1 4
224
+#define UART7_RX_M1_OFFSET 12
225
+#define UART7_RX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
226
+/* gpio1b2 */
227
+#define UART7_TX_M1 4
228
+#define UART7_TX_M1_OFFSET 8
229
+#define UART7_TX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
230
+
231
+
232
+#define set_uart_iomux(bits_offset, bits_val, addr) \
233
+ writel(GENMASK(bits_offset + 19, bits_offset + 16) | (bits_val << bits_offset) , addr)
234
+
235
+#define set_uart_iomux_rx(ID, MODE) \
236
+ set_uart_iomux(UART##ID##_RX_M##MODE##_OFFSET, UART##ID##_RX_M##MODE, UART##ID##_RX_M##MODE##_ADDR);
237
+#define set_uart_iomux_tx(ID, MODE) \
238
+ set_uart_iomux(UART##ID##_TX_M##MODE##_OFFSET, UART##ID##_TX_M##MODE, UART##ID##_TX_M##MODE##_ADDR);
239
+
240
+void board_debug_uart_init(void)
241
+{
242
+/* UART 0 */
243
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff9f0000)
244
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
245
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
246
+
247
+ /* UART0_M0 Switch iomux */
248
+ set_uart_iomux_rx(0, 0);
249
+ set_uart_iomux_tx(0, 0);
250
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
251
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
252
+
253
+ /* UART0_M1 Switch iomux */
254
+ set_uart_iomux_rx(0, 1);
255
+ set_uart_iomux_tx(0, 1);
256
+#endif
257
+/* UART 1 */
258
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff9f8000)
259
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
260
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
261
+
262
+ /* UART1_M0 Switch iomux */
263
+ set_uart_iomux_rx(1, 0);
264
+ set_uart_iomux_tx(1, 0);
265
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
266
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
267
+
268
+ /* UART1_M1 Switch iomux */
269
+ set_uart_iomux_rx(1, 1);
270
+ set_uart_iomux_tx(1, 1);
271
+#endif
272
+/* UART 2 */
273
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa00000)
274
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
275
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
276
+
277
+ /* UART2_M0 Switch iomux */
278
+ set_uart_iomux_rx(2, 0);
279
+ set_uart_iomux_tx(2, 0);
280
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
281
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
282
+
283
+ /* UART2_M1 Switch iomux */
284
+ set_uart_iomux_rx(2, 1);
285
+ set_uart_iomux_tx(2, 1);
286
+#endif
287
+/* UART 3 */
288
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa08000)
289
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
290
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
291
+
292
+ /* UART3_M0 Switch iomux */
293
+ set_uart_iomux_rx(3, 0);
294
+ set_uart_iomux_tx(3, 0);
295
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
296
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
297
+
298
+ /* UART3_M1 Switch iomux */
299
+ set_uart_iomux_rx(3, 1);
300
+ set_uart_iomux_tx(3, 1);
301
+#endif
302
+/* UART 4 */
303
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa10000)
304
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
305
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
306
+
307
+ /* UART4_M0 Switch iomux */
308
+ set_uart_iomux_rx(4, 0);
309
+ set_uart_iomux_tx(4, 0);
310
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
311
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
312
+
313
+ /* UART4_M1 Switch iomux */
314
+ set_uart_iomux_rx(4, 1);
315
+ set_uart_iomux_tx(4, 1);
316
+#endif
317
+/* UART 5 */
318
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa18000)
319
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
320
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
321
+
322
+ /* UART5_M0 Switch iomux */
323
+ set_uart_iomux_rx(5, 0);
324
+ set_uart_iomux_tx(5, 0);
325
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
326
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
327
+
328
+ /* UART5_M1 Switch iomux */
329
+ set_uart_iomux_rx(5, 1);
330
+ set_uart_iomux_tx(5, 1);
331
+#endif
332
+/* UART 6 */
333
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa20000)
334
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
335
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
336
+
337
+ /* UART6_M0 Switch iomux */
338
+ set_uart_iomux_rx(6, 0);
339
+ set_uart_iomux_tx(6, 0);
340
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
341
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
342
+
343
+ /* UART6_M1 Switch iomux */
344
+ set_uart_iomux_rx(6, 1);
345
+ set_uart_iomux_tx(6, 1);
346
+#endif
347
+/* UART 7 */
348
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa28000)
349
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
350
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
351
+
352
+ /* UART7_M0 Switch iomux */
353
+ set_uart_iomux_rx(7, 0);
354
+ set_uart_iomux_tx(7, 0);
355
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
356
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
357
+
358
+ /* UART7_M1 Switch iomux */
359
+ set_uart_iomux_rx(7, 1);
360
+ set_uart_iomux_tx(7, 1);
361
+#endif
362
+#endif
363
+}
364
+
365
+#ifdef CONFIG_SPL_BUILD
366
+void rockchip_stimer_init(void)
367
+{
368
+ /* If Timer already enabled, don't re-init it */
369
+ u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
370
+
371
+ if (reg & 0x1)
372
+ return;
373
+
374
+ asm volatile("msr CNTFRQ_EL0, %0" : : "r" (COUNTER_FREQUENCY));
375
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
376
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
377
+ dsb();
378
+ writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
379
+}
380
+#endif
381
+
382
+int arch_cpu_init(void)
383
+{
384
+#if defined(CONFIG_SPL_BUILD)
385
+ u32 val;
386
+
387
+ /*
388
+ * Select clk_tx source as default for i2s2/i2s3
389
+ * Set I2Sx_MCLK as input default
390
+ *
391
+ * It's safe to set mclk as input default to avoid high freq glitch
392
+ * which may make devices work unexpected. And then enabled by
393
+ * kernel stage or any state where user use it.
394
+ */
395
+ writel(0x00020002, VPU_GRF_BASE + VPU_GRF_CON4);
396
+ writel(0x40004000, VENC_GRF_BASE + VENC_GRF_CON1);
397
+
398
+ /* Set the emmc to access ddr memory */
399
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
400
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
401
+
402
+ /* Set the sdmmc to access ddr memory */
403
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
404
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
405
+
406
+ /* Set the crypto to access ddr memory */
407
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
408
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
409
+
410
+#if defined(CONFIG_ROCKCHIP_SFC)
411
+ /* Set the fspi to access ddr memory */
412
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
413
+ writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
414
+#endif
415
+
416
+#ifndef CONFIG_TPL_BUILD
417
+ /* Set cpu qos priority, then
418
+ * Peri > VOP > CPU = RKVDEC/RKVENC/VPU > GPU/RGA/Other
419
+ */
420
+ writel(QOS_PRIORITY_LEVEL(2, 2), CPU_PRIORITY_REG);
421
+#endif
422
+
423
+ if (readl(GPIO1_IOC_GPIO1D_IOMUX_SEL_L) == 0x1111) {
424
+ /*
425
+ * set the emmc io drive strength:
426
+ * data and cmd: level 3
427
+ * clock: level 5
428
+ */
429
+ writel(0x3F3F0F0F, GPIO1_IOC_GPIO1C_DS_2);
430
+ writel(0x3F3F0F0F, GPIO1_IOC_GPIO1C_DS_3);
431
+ writel(0x3F3F0F0F, GPIO1_IOC_GPIO1D_DS_0);
432
+ writel(0x3F3F0F0F, GPIO1_IOC_GPIO1D_DS_1);
433
+ writel(0x3F3F3F0F, GPIO1_IOC_GPIO1D_DS_2);
434
+ }
435
+
436
+#elif defined(CONFIG_SUPPORT_USBPLUG)
437
+ u32 val;
438
+
439
+ /* Set the usb to access ddr memory */
440
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
441
+ writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
442
+
443
+ /* Set the emmc to access ddr memory */
444
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
445
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
446
+
447
+ /* Set emmc iomux */
448
+ writel(0xffff1111, GPIO1_IOC_BASE + GPIO1C_IOMUX_SEL_H);
449
+ writel(0xffff1111, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_L);
450
+ writel(0xffff1111, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_H);
451
+
452
+#if defined(CONFIG_ROCKCHIP_SFC)
453
+ /* Set the fspi to access ddr memory */
454
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
455
+ writel(val & 0xFFFF0000uL, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
456
+
457
+ /* Set fspi iomux */
458
+ writel(0xffff2222, GPIO1_IOC_BASE + GPIO1C_IOMUX_SEL_H);
459
+ writel(0x000f0002, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_L);
460
+ writel(0x00f00020, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_H);
461
+#endif
462
+
463
+#endif
464
+ return 0;
465
+}
466
+
467
+#ifdef CONFIG_SPL_BUILD
468
+int spl_fit_standalone_release(char *id, uintptr_t entry_point)
469
+{
470
+ u32 val;
471
+
472
+ /* open clk_pmu_mcu_jtag / clk_mcu_32k_en / fclk_mcu_en */
473
+ writel(0x05800000, PMU_CRU_BASE + PMU_CRU_GATE_CON00);
474
+ /* set the mcu to access ddr memory */
475
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST11_REG);
476
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST11_REG);
477
+ /* writel(0x00000000, FIREWALL_DDR_BASE + FW_DDR_MST_REG); */
478
+ /* set the mcu to secure */
479
+ writel(0x00200000, PMU_SGRF_BASE + PMU_SGRF_SOC_CON4);
480
+ /* open mcu_debug_en / mcu_dclk_en / mcu_hclk_en / mcu_sclk_en */
481
+ writel(0x000f000f, PMU_SGRF_BASE + PMU_SGRF_SOC_CON5);
482
+ /* set start addr, mcu_code_addr_start */
483
+ writel(0xffff0000 | (entry_point >> 16), PMU_SGRF_BASE + PMU_SGRF_SOC_CON6);
484
+ /* mcu_tcm_addr_start, multiplex pmu sram address */
485
+ writel(0xffffff10, PMU_SGRF_BASE + PMU_SGRF_SOC_CON11);
486
+ /* jtag_mcu_m0 gpio2a4/gpio2a5 iomux */
487
+ /* writel(0x00ff0022, GPIO2_IOC_BASE + 0x44); */
488
+ /* release the mcu */
489
+ writel(0x00800000, PMU_CRU_BASE + PMU_CRU_SOFTRST_CON00);
490
+
491
+ return 0;
492
+}
493
+#endif
494
+
u-boot/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c
....@@ -0,0 +1,24 @@
1
+/*
2
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+
7
+#include <common.h>
8
+#include <dm.h>
9
+#include <syscon.h>
10
+#include <asm/arch/clock.h>
11
+
12
+static const struct udevice_id rk3528_syscon_ids[] = {
13
+ { .compatible = "rockchip,rk3528-grf", .data = ROCKCHIP_SYSCON_GRF },
14
+ { }
15
+};
16
+
17
+U_BOOT_DRIVER(syscon_rk3528) = {
18
+ .name = "rk3528_syscon",
19
+ .id = UCLASS_SYSCON,
20
+ .of_match = rk3528_syscon_ids,
21
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
22
+ .bind = dm_scan_fdt_dev,
23
+#endif
24
+};
u-boot/arch/arm/mach-rockchip/rk3562/Kconfig
....@@ -0,0 +1,17 @@
1
+if ROCKCHIP_RK3562
2
+
3
+config TARGET_EVB_RK3562
4
+ bool "EVB_RK3562"
5
+ select BOARD_LATE_INIT
6
+ help
7
+ RK3562 EVB is a evaluation board for Rockchp RK3562.
8
+
9
+config SYS_SOC
10
+ default "rockchip"
11
+
12
+config SYS_MALLOC_F_LEN
13
+ default 0x400
14
+
15
+source board/rockchip/evb_rk3562/Kconfig
16
+
17
+endif
u-boot/arch/arm/mach-rockchip/rk3562/Makefile
....@@ -0,0 +1,11 @@
1
+#
2
+# (C) Copyright 2022 Rockchip Electronics Co., Ltd
3
+#
4
+# SPDX-License-Identifier: GPL-2.0+
5
+#
6
+
7
+ifneq ($(CONFIG_TPL_BUILD)$(CONFIG_TPL_TINY_FRAMEWORK),yy)
8
+obj-y += syscon_rk3562.o
9
+endif
10
+obj-y += rk3562.o
11
+obj-y += clk_rk3562.o
u-boot/arch/arm/mach-rockchip/rk3562/clk_rk3562.c
....@@ -0,0 +1,41 @@
1
+/*
2
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd.
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+
7
+#include <common.h>
8
+#include <dm.h>
9
+#include <syscon.h>
10
+#include <asm/arch/clock.h>
11
+#include <asm/arch/cru_rk3562.h>
12
+
13
+int rockchip_get_clk(struct udevice **devp)
14
+{
15
+ return uclass_get_device_by_driver(UCLASS_CLK,
16
+ DM_GET_DRIVER(rockchip_rk3562_cru), devp);
17
+}
18
+
19
+#if CONFIG_IS_ENABLED(CLK_SCMI)
20
+int rockchip_get_scmi_clk(struct udevice **devp)
21
+{
22
+ return uclass_get_device_by_driver(UCLASS_CLK,
23
+ DM_GET_DRIVER(scmi_clock), devp);
24
+}
25
+#endif
26
+
27
+void *rockchip_get_cru(void)
28
+{
29
+ struct rk3562_clk_priv *priv;
30
+ struct udevice *dev;
31
+ int ret;
32
+
33
+ ret = rockchip_get_clk(&dev);
34
+ if (ret)
35
+ return ERR_PTR(ret);
36
+
37
+ priv = dev_get_priv(dev);
38
+
39
+ return priv->cru;
40
+}
41
+
u-boot/arch/arm/mach-rockchip/rk3562/rk3562.c
....@@ -0,0 +1,661 @@
1
+/*
2
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+#include <common.h>
7
+#include <clk.h>
8
+#include <dm.h>
9
+#include <asm/io.h>
10
+#include <asm/arch/cpu.h>
11
+#include <asm/arch/hardware.h>
12
+#include <asm/arch/grf_rk3562.h>
13
+#include <asm/arch/ioc_rk3562.h>
14
+#include <asm/arch/rk_atags.h>
15
+#include <linux/libfdt.h>
16
+#include <fdt_support.h>
17
+#include <asm/arch/clock.h>
18
+#include <dt-bindings/clock/rk3562-cru.h>
19
+#include <asm/arch-rockchip/rockchip_smccc.h>
20
+
21
+DECLARE_GLOBAL_DATA_PTR;
22
+
23
+#define FIREWALL_DDR_BASE 0xfef00000
24
+#define FW_DDR_MST3_REG 0x2c /* usb */
25
+#define FW_DDR_MST4_REG 0x30 /* emmc */
26
+#define FW_DDR_MST5_REG 0x34 /* fspi */
27
+#define FW_DDR_MST6_REG 0x38 /* sdmmc mcu */
28
+#define FW_DDR_CON_REG 0x80
29
+
30
+#define PMU_GRF_BASE 0xff010000
31
+#define PMU_GRF_SOC_CON9 0x0124
32
+
33
+#define SYS_GRF_BASE 0xff030000
34
+#define SYS_GRF_SOC_CON5 0x0414
35
+#define SYS_GRF_SOC_CON6 0x0418
36
+
37
+#define PERI_GRF_BASE 0xff040000
38
+#define PERI_GRF_AUDIO_CON 0x0070
39
+
40
+#define PIPEPHY_GRF_BASE 0xff098000
41
+#define PIPEPHY_PIPE_CON5 0x0014
42
+
43
+#define TOP_CRU_BASE 0xff100000
44
+#define TOP_CRU_GATE_CON23 0x035c
45
+#define TOP_CRU_SOFTRST_CON23 0x045c
46
+#define TOP_CRU_CM0_GATEMASK 0x0680
47
+
48
+#define PMU0_CRU_BASE 0xff110000
49
+
50
+#define PMU1_CRU_BASE 0xff118000
51
+#define PMU1_CRU_GATE_CON02 0x0188
52
+#define PMU1_CRU_SOFTRST_CON02 0x0208
53
+#define PMU1_CRU_CM0_GATEMASK 0x0420
54
+
55
+#define PMU_BASE_ADDR 0xff258000
56
+#define PMU2_BIU_IDLE_SFTCON0 0x110
57
+#define PMU2_BIU_IDLE_ACK_STS0 0x120
58
+#define PMU2_BIT_IDLE_STS0 0x128
59
+#define PMU2_PWR_GATE_SFTCON0 0x210
60
+#define PMU2_PWR_GATE_STS0 0x230
61
+#define PMU2_MEM_SD_SFTCON0 0x300
62
+/* PMU2_PWR_GATE_SFTCON0 */
63
+#define PD_GPU_DWN_SFTENA BIT(0)
64
+#define PD_VI_DWN_SFTENA BIT(5)
65
+#define PD_VO_DWN_SFTENA BIT(6)
66
+/* PMU2_BIU_IDLE_SFTCON0 */
67
+#define IDLE_REQ_GPU_SFTENA BIT(1)
68
+#define IDLE_REQ_VI_SFTENA BIT(3)
69
+#define IDLE_REQ_VO_SFTENA BIT(4)
70
+/* PMU2_BIU_IDLE_ACK_STS0 */
71
+#define IDLE_ACK_GPU BIT(1)
72
+#define IDLE_ACK_VI BIT(3)
73
+#define IDLE_ACK_VO BIT(4)
74
+/* PMU2_BIT_IDLE_STS0 */
75
+#define IDLE_GPU BIT(1)
76
+#define IDLE_VI BIT(3)
77
+#define IDLE_VO BIT(4)
78
+
79
+#define CRYPTO_PRIORITY_REG 0xfeeb0108
80
+#define DCF_PRIORITY_REG 0xfee10408
81
+#define DMA2DDR_PRIORITY_REG 0xfee03808
82
+#define DMAC_PRIORITY_REG 0xfeeb0208
83
+#define EMMC_PRIORITY_REG 0xfeeb0308
84
+#define FSPI_PRIORITY_REG 0xfeeb0408
85
+#define GMAC_PRIORITY_REG 0xfee10208
86
+#define GPU_PRIORITY_REG 0xfee30008
87
+#define ISP_PRIORITY_REG 0xfee70008
88
+#define MAC100_PRIORITY_REG 0xfee10308
89
+#define MCU_PRIORITY_REG 0xfee10008
90
+#define PCIE_PRIORITY_REG 0xfeea0008
91
+#define RKDMA_PRIORITY_REG 0xfeeb0508
92
+#define SDMMC0_PRIORITY_REG 0xfeeb0608
93
+#define SDMMC1_PRIORITY_REG 0xfeeb0708
94
+#define USB2_PRIORITY_REG 0xfeeb0808
95
+#define USB3_PRIORITY_REG 0xfeea0108
96
+#define VICAP_PRIORITY_REG 0xfee70108
97
+#define VOP_PRIORITY_REG 0xfee80008
98
+
99
+#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7))
100
+
101
+#ifdef CONFIG_ARM64
102
+#include <asm/armv8/mmu.h>
103
+
104
+static struct mm_region rk3562_mem_map[] = {
105
+ {
106
+ .virt = 0x0UL,
107
+ .phys = 0x0UL,
108
+ .size = 0xfc000000UL,
109
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
110
+ PTE_BLOCK_INNER_SHARE
111
+ }, {
112
+ .virt = 0xfc000000UL,
113
+ .phys = 0xfc000000UL,
114
+ .size = 0x04000000UL,
115
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
116
+ PTE_BLOCK_NON_SHARE |
117
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
118
+ }, {
119
+ /* List terminator */
120
+ 0,
121
+ }
122
+};
123
+
124
+struct mm_region *mem_map = rk3562_mem_map;
125
+#endif
126
+
127
+#define GPIO0_IOC_BASE 0xFF080000
128
+#define GPIO1_IOC_BASE 0xFF060000
129
+#define GPIO1A_IOMUX_SEL_L 0x0
130
+#define GPIO1A_IOMUX_SEL_H 0x4
131
+#define GPIO1B_IOMUX_SEL_L 0x8
132
+#define GPIO1_IOC_GPIO1A_DS0 0x200
133
+#define GPIO1_IOC_GPIO1A_DS1 0x204
134
+#define GPIO1_IOC_GPIO1B_DS0 0x210
135
+
136
+#define GPIO2_IOC_BASE 0xFF060000
137
+#define GPIO2_IOC_IO_VSEL0 0x300
138
+/* GPIO2_IOC_IO_VSEL0 */
139
+#define POC_VCCIO2_VD_3V3 BIT(12)
140
+
141
+#define GPIO3_IOC_BASE 0xFF070000
142
+#define GPIO4_IOC_BASE 0xFF070000
143
+
144
+/* UART0 iomux */
145
+/* gpio0d0_sel */
146
+#define UART0_RX_M0 1
147
+#define UART0_RX_M0_OFFSET 0
148
+#define UART0_RX_M0_ADDR (GPIO0_IOC_BASE + 0x18)
149
+/* gpio0d1_sel */
150
+#define UART0_TX_M0 1
151
+#define UART0_TX_M0_OFFSET 4
152
+#define UART0_TX_M0_ADDR (GPIO0_IOC_BASE + 0x18)
153
+
154
+/* gpio1b3_sel */
155
+#define UART0_RX_M1 2
156
+#define UART0_RX_M1_OFFSET 12
157
+#define UART0_RX_M1_ADDR (GPIO1_IOC_BASE + 0x08)
158
+/* gpio1b4_sel */
159
+#define UART0_TX_M1 2
160
+#define UART0_TX_M1_OFFSET 0
161
+#define UART0_TX_M1_ADDR (GPIO1_IOC_BASE + 0x0C)
162
+
163
+/* UART1 iomux */
164
+/* gpio1d1_sel */
165
+#define UART1_RX_M0 1
166
+#define UART1_RX_M0_OFFSET 4
167
+#define UART1_RX_M0_ADDR (GPIO1_IOC_BASE + 0x18)
168
+/* gpio1d2_sel */
169
+#define UART1_TX_M0 1
170
+#define UART1_TX_M0_OFFSET 8
171
+#define UART1_TX_M0_ADDR (GPIO1_IOC_BASE + 0x18)
172
+
173
+/* gpio4a6_sel */
174
+#define UART1_RX_M1 4
175
+#define UART1_RX_M1_OFFSET 8
176
+#define UART1_RX_M1_ADDR (GPIO4_IOC_BASE + 0x64)
177
+/* gpio4a5_sel */
178
+#define UART1_TX_M1 4
179
+#define UART1_TX_M1_OFFSET 4
180
+#define UART1_TX_M1_ADDR (GPIO4_IOC_BASE + 0x64)
181
+
182
+/* UART2 iomux */
183
+/* gpio0c1_sel */
184
+#define UART2_RX_M0 1
185
+#define UART2_RX_M0_OFFSET 4
186
+#define UART2_RX_M0_ADDR (GPIO0_IOC_BASE + 0x10)
187
+/* gpio0c0_sel */
188
+#define UART2_TX_M0 1
189
+#define UART2_TX_M0_OFFSET 0
190
+#define UART2_TX_M0_ADDR (GPIO0_IOC_BASE + 0x10)
191
+
192
+/* gpio3a1_sel */
193
+#define UART2_RX_M1 2
194
+#define UART2_RX_M1_OFFSET 4
195
+#define UART2_RX_M1_ADDR (GPIO3_IOC_BASE + 0x40)
196
+/* gpio3a0_sel */
197
+#define UART2_TX_M1 2
198
+#define UART2_TX_M1_OFFSET 0
199
+#define UART2_TX_M1_ADDR (GPIO3_IOC_BASE + 0x40)
200
+
201
+/* UART3 iomux */
202
+/* gpio4b5_sel */
203
+#define UART3_RX_M0 7
204
+#define UART3_RX_M0_OFFSET 4
205
+#define UART3_RX_M0_ADDR (GPIO4_IOC_BASE + 0x6C)
206
+/* gpio4b4_sel */
207
+#define UART3_TX_M0 7
208
+#define UART3_TX_M0_OFFSET 0
209
+#define UART3_TX_M0_ADDR (GPIO4_IOC_BASE + 0x6C)
210
+
211
+/* gpio3c0_sel */
212
+#define UART3_RX_M1 3
213
+#define UART3_RX_M1_OFFSET 0
214
+#define UART3_RX_M1_ADDR (GPIO3_IOC_BASE + 0x50)
215
+/* gpio3b7_sel */
216
+#define UART3_TX_M1 3
217
+#define UART3_TX_M1_OFFSET 12
218
+#define UART3_TX_M1_ADDR (GPIO3_IOC_BASE + 0x4C)
219
+
220
+/* UART4 iomux */
221
+/* gpio3d1_sel */
222
+#define UART4_RX_M0 4
223
+#define UART4_RX_M0_OFFSET 4
224
+#define UART4_RX_M0_ADDR (GPIO3_IOC_BASE + 0x58)
225
+/* gpio3d0_sel */
226
+#define UART4_TX_M0 4
227
+#define UART4_TX_M0_OFFSET 0
228
+#define UART4_TX_M0_ADDR (GPIO3_IOC_BASE + 0x58)
229
+
230
+/* gpio1d5_sel */
231
+#define UART4_RX_M1 3
232
+#define UART4_RX_M1_OFFSET 4
233
+#define UART4_RX_M1_ADDR (GPIO1_IOC_BASE + 0x1C)
234
+/* gpio1d6_sel */
235
+#define UART4_TX_M1 3
236
+#define UART4_TX_M1_OFFSET 8
237
+#define UART4_TX_M1_ADDR (GPIO1_IOC_BASE + 0x1C)
238
+
239
+/* UART5 iomux */
240
+/* gpio1b7_sel */
241
+#define UART5_RX_M0 3
242
+#define UART5_RX_M0_OFFSET 12
243
+#define UART5_RX_M0_ADDR (GPIO1_IOC_BASE + 0xC)
244
+/* gpio1c0_sel */
245
+#define UART5_TX_M0 3
246
+#define UART5_TX_M0_OFFSET 0
247
+#define UART5_TX_M0_ADDR (GPIO1_IOC_BASE + 0x10)
248
+
249
+/* gpio3a7_sel */
250
+#define UART5_RX_M1 5
251
+#define UART5_RX_M1_OFFSET 12
252
+#define UART5_RX_M1_ADDR (GPIO3_IOC_BASE + 0x44)
253
+/* gpio3a6_sel */
254
+#define UART5_TX_M1 5
255
+#define UART5_TX_M1_OFFSET 8
256
+#define UART5_TX_M1_ADDR (GPIO3_IOC_BASE + 0x44)
257
+
258
+/* UART6 iomux */
259
+/* gpio0c7_sel */
260
+#define UART6_RX_M0 1
261
+#define UART6_RX_M0_OFFSET 12
262
+#define UART6_RX_M0_ADDR (GPIO0_IOC_BASE + 0x14)
263
+/* gpio0c6_sel */
264
+#define UART6_TX_M0 1
265
+#define UART6_TX_M0_OFFSET 8
266
+#define UART6_TX_M0_ADDR (GPIO0_IOC_BASE + 0x14)
267
+
268
+/* gpio4b0_sel */
269
+#define UART6_RX_M1 6
270
+#define UART6_RX_M1_OFFSET 0
271
+#define UART6_RX_M1_ADDR (GPIO4_IOC_BASE + 0x68)
272
+/* gpio4a7_sel */
273
+#define UART6_TX_M1 6
274
+#define UART6_TX_M1_OFFSET 12
275
+#define UART6_TX_M1_ADDR (GPIO4_IOC_BASE + 0x64)
276
+
277
+/* UART7 iomux */
278
+/* gpio3c7_sel */
279
+#define UART7_RX_M0 4
280
+#define UART7_RX_M0_OFFSET 12
281
+#define UART7_RX_M0_ADDR (GPIO3_IOC_BASE + 0x54)
282
+/* gpio3c4_sel */
283
+#define UART7_TX_M0 4
284
+#define UART7_TX_M0_OFFSET 0
285
+#define UART7_TX_M0_ADDR (GPIO3_IOC_BASE + 0x54)
286
+
287
+/* gpio1b3_sel */
288
+#define UART7_RX_M1 3
289
+#define UART7_RX_M1_OFFSET 12
290
+#define UART7_RX_M1_ADDR (GPIO1_IOC_BASE + 0x08)
291
+/* gpio1b4_sel */
292
+#define UART7_TX_M1 3
293
+#define UART7_TX_M1_OFFSET 0
294
+#define UART7_TX_M1_ADDR (GPIO1_IOC_BASE + 0x0C)
295
+
296
+/* UART8 iomux */
297
+/* gpio3b3_sel */
298
+#define UART8_RX_M0 3
299
+#define UART8_RX_M0_OFFSET 12
300
+#define UART8_RX_M0_ADDR (GPIO3_IOC_BASE + 0x48)
301
+/* gpio3b2_sel */
302
+#define UART8_TX_M0 3
303
+#define UART8_TX_M0_OFFSET 8
304
+#define UART8_TX_M0_ADDR (GPIO3_IOC_BASE + 0x48)
305
+
306
+/* gpio3d5_sel */
307
+#define UART8_RX_M1 4
308
+#define UART8_RX_M1_OFFSET 4
309
+#define UART8_RX_M1_ADDR (GPIO3_IOC_BASE + 0x5C)
310
+/* gpio3d4_sel */
311
+#define UART8_TX_M1 4
312
+#define UART8_TX_M1_OFFSET 0
313
+#define UART8_TX_M1_ADDR (GPIO3_IOC_BASE + 0x5C)
314
+
315
+/* UART9 iomux */
316
+/* gpio4b3_sel */
317
+#define UART9_RX_M0 4
318
+#define UART9_RX_M0_OFFSET 12
319
+#define UART9_RX_M0_ADDR (GPIO4_IOC_BASE + 0x68)
320
+/* gpio4b2_sel */
321
+#define UART9_TX_M0 4
322
+#define UART9_TX_M0_OFFSET 8
323
+#define UART9_TX_M0_ADDR (GPIO4_IOC_BASE + 0x68)
324
+
325
+/* gpio3c3_sel */
326
+#define UART9_RX_M1 3
327
+#define UART9_RX_M1_OFFSET 12
328
+#define UART9_RX_M1_ADDR (GPIO3_IOC_BASE + 0x50)
329
+/* gpio3c2_sel */
330
+#define UART9_TX_M1 3
331
+#define UART9_TX_M1_OFFSET 8
332
+#define UART9_TX_M1_ADDR (GPIO3_IOC_BASE + 0x50)
333
+
334
+#define set_uart_iomux(bits_offset, bits_val, addr) \
335
+ writel(GENMASK(bits_offset + 19, bits_offset + 16) | (bits_val << bits_offset) , addr)
336
+
337
+#define set_uart_iomux_rx(ID, MODE) \
338
+ set_uart_iomux(UART##ID##_RX_M##MODE##_OFFSET, UART##ID##_RX_M##MODE, UART##ID##_RX_M##MODE##_ADDR);
339
+#define set_uart_iomux_tx(ID, MODE) \
340
+ set_uart_iomux(UART##ID##_TX_M##MODE##_OFFSET, UART##ID##_TX_M##MODE, UART##ID##_TX_M##MODE##_ADDR);
341
+
342
+void board_debug_uart_init(void)
343
+{
344
+/* UART 0 */
345
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff210000)
346
+
347
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
348
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
349
+
350
+ /* UART0_M0 Switch iomux */
351
+ set_uart_iomux_rx(0, 0);
352
+ set_uart_iomux_tx(0, 0);
353
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
354
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
355
+
356
+ /* UART0_M1 Switch iomux */
357
+ set_uart_iomux_rx(0, 1);
358
+ set_uart_iomux_tx(0, 1);
359
+#endif
360
+/* UART 1 */
361
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff670000)
362
+
363
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
364
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
365
+
366
+ /* UART1_M0 Switch iomux */
367
+ set_uart_iomux_rx(1, 0);
368
+ set_uart_iomux_tx(1, 0);
369
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
370
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
371
+
372
+ /* UART1_M1 Switch iomux */
373
+ set_uart_iomux_rx(1, 1);
374
+ set_uart_iomux_tx(1, 1);
375
+#endif
376
+/* UART 2 */
377
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff680000)
378
+
379
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
380
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
381
+
382
+ /* UART2_M0 Switch iomux */
383
+ set_uart_iomux_rx(2, 0);
384
+ set_uart_iomux_tx(2, 0);
385
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
386
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
387
+
388
+ /* UART2_M1 Switch iomux */
389
+ set_uart_iomux_rx(2, 1);
390
+ set_uart_iomux_tx(2, 1);
391
+#endif
392
+/* UART 3 */
393
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
394
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
395
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
396
+
397
+ /* UART3_M0 Switch iomux */
398
+ set_uart_iomux_rx(3, 0);
399
+ set_uart_iomux_tx(3, 0);
400
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
401
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
402
+
403
+ /* UART3_M1 Switch iomux */
404
+ set_uart_iomux_rx(3, 1);
405
+ set_uart_iomux_tx(3, 1);
406
+#endif
407
+/* UART 4 */
408
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6a0000)
409
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
410
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
411
+
412
+ /* UART4_M0 Switch iomux */
413
+ set_uart_iomux_rx(4, 0);
414
+ set_uart_iomux_tx(4, 0);
415
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
416
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
417
+
418
+ /* UART4_M1 Switch iomux */
419
+ set_uart_iomux_rx(4, 1);
420
+ set_uart_iomux_tx(4, 1);
421
+#endif
422
+/* UART 5 */
423
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6b0000)
424
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
425
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
426
+
427
+ /* UART5_M0 Switch iomux */
428
+ set_uart_iomux_rx(5, 0);
429
+ set_uart_iomux_tx(5, 0);
430
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
431
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
432
+
433
+ /* UART5_M1 Switch iomux */
434
+ set_uart_iomux_rx(5, 1);
435
+ set_uart_iomux_tx(5, 1);
436
+#endif
437
+/* UART 6 */
438
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6c0000)
439
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
440
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
441
+
442
+ /* UART6_M0 Switch iomux */
443
+ set_uart_iomux_rx(6, 0);
444
+ set_uart_iomux_tx(6, 0);
445
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
446
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
447
+
448
+ /* UART6_M1 Switch iomux */
449
+ set_uart_iomux_rx(6, 1);
450
+ set_uart_iomux_tx(6, 1);
451
+#endif
452
+/* UART 7 */
453
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6d0000)
454
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
455
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
456
+
457
+ /* UART7_M0 Switch iomux */
458
+ set_uart_iomux_rx(7, 0);
459
+ set_uart_iomux_tx(7, 0);
460
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
461
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
462
+
463
+ /* UART7_M1 Switch iomux */
464
+ set_uart_iomux_rx(7, 1);
465
+ set_uart_iomux_tx(7, 1);
466
+#endif
467
+/* UART 8 */
468
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6e0000)
469
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
470
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
471
+
472
+ /* UART8_M0 Switch iomux */
473
+ set_uart_iomux_rx(8, 0);
474
+ set_uart_iomux_tx(8, 0);
475
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
476
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
477
+
478
+ /* UART8_M1 Switch iomux */
479
+ set_uart_iomux_rx(8, 1);
480
+ set_uart_iomux_tx(8, 1);
481
+#endif
482
+/* UART 9 */
483
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6f0000)
484
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
485
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
486
+
487
+ /* UART9_M0 Switch iomux */
488
+ set_uart_iomux_rx(9, 0);
489
+ set_uart_iomux_tx(9, 0);
490
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
491
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
492
+
493
+ /* UART9_M1 Switch iomux */
494
+ set_uart_iomux_rx(9, 1);
495
+ set_uart_iomux_tx(9, 1);
496
+#endif
497
+#endif
498
+}
499
+
500
+int fit_standalone_release(char *id, uintptr_t entry_point)
501
+{
502
+ /* bus m0 configuration: */
503
+ /* open hclk_dcache / hclk_icache / clk_bus m0 rtc / fclk_bus_m0_core */
504
+ writel(0x03180000, TOP_CRU_BASE + TOP_CRU_GATE_CON23);
505
+
506
+ /* open bus m0 sclk / bus m0 hclk / bus m0 dclk */
507
+ writel(0x00070000, TOP_CRU_BASE + TOP_CRU_CM0_GATEMASK);
508
+
509
+ /* mcu_cache_peripheral_addr */
510
+ writel(0xa0000000, SYS_GRF_BASE + SYS_GRF_SOC_CON5);
511
+ writel(0xffb40000, SYS_GRF_BASE + SYS_GRF_SOC_CON6);
512
+
513
+ sip_smc_mcu_config(ROCKCHIP_SIP_CONFIG_BUSMCU_0_ID,
514
+ ROCKCHIP_SIP_CONFIG_MCU_CODE_START_ADDR,
515
+ 0xffff0000 | (entry_point >> 16));
516
+ sip_smc_mcu_config(ROCKCHIP_SIP_CONFIG_BUSMCU_0_ID,
517
+ ROCKCHIP_SIP_CONFIG_MCU_EXPERI_START_ADDR, 0xffffa000);
518
+
519
+ /* release dcache / icache / bus m0 jtag / bus m0 */
520
+ writel(0x03280000, TOP_CRU_BASE + TOP_CRU_SOFTRST_CON23);
521
+
522
+ /* release pmu m0 jtag / pmu m0 */
523
+ /* writel(0x00050000, PMU1_CRU_BASE + PMU1_CRU_SOFTRST_CON02); */
524
+
525
+ return 0;
526
+}
527
+
528
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
529
+static void qos_priority_init(void)
530
+{
531
+ u32 delay;
532
+ u32 i;
533
+
534
+ /* power up vo,vi,gpu */
535
+ rk_clrreg(PMU_BASE_ADDR + PMU2_PWR_GATE_SFTCON0,
536
+ PD_VO_DWN_SFTENA | PD_VI_DWN_SFTENA);
537
+ delay = 1000;
538
+ do {
539
+ udelay(1);
540
+ delay--;
541
+ if (delay == 0) {
542
+ printf("Fail to set domain. PMU2_PWR_GATE_STS0=0x%x\n",
543
+ readl(PMU_BASE_ADDR + PMU2_PWR_GATE_STS0));
544
+ hang();
545
+ }
546
+ } while (readl(PMU_BASE_ADDR + PMU2_PWR_GATE_STS0) &
547
+ (PD_VO_DWN_SFTENA | PD_VI_DWN_SFTENA));
548
+ /* power up vop memory */
549
+ for (i = 0; i < 16; i++)
550
+ rk_clrreg(PMU_BASE_ADDR + PMU2_MEM_SD_SFTCON0, BIT(i));
551
+
552
+ /* release vo,vi,gpu idle request */
553
+ rk_clrreg(PMU_BASE_ADDR + PMU2_BIU_IDLE_SFTCON0,
554
+ (IDLE_REQ_VO_SFTENA | IDLE_REQ_VI_SFTENA));
555
+
556
+ delay = 1000;
557
+ /* wait ack status */
558
+ do {
559
+ udelay(1);
560
+ delay--;
561
+ if (delay == 0) {
562
+ printf("Fail to get ack on domain. PMU2_BIU_IDLE_ACK_STS0=0x%x\n",
563
+ readl(PMU_BASE_ADDR + PMU2_BIU_IDLE_ACK_STS0));
564
+ hang();
565
+ }
566
+ } while (readl(PMU_BASE_ADDR + PMU2_BIU_IDLE_ACK_STS0) &
567
+ (IDLE_ACK_VO | IDLE_ACK_VI));
568
+
569
+ delay = 1000;
570
+ /* wait idle status */
571
+ do {
572
+ udelay(1);
573
+ delay--;
574
+ if (delay == 0) {
575
+ printf("Fail to set idle on domain. PMU2_BIT_IDLE_STS0=0x%x\n",
576
+ readl(PMU_BASE_ADDR + PMU2_BIT_IDLE_STS0));
577
+ hang();
578
+ }
579
+ } while (readl(PMU_BASE_ADDR + PMU2_BIT_IDLE_STS0) &
580
+ (IDLE_VO | IDLE_VI));
581
+
582
+ /*
583
+ * modify default qos priority setting, then
584
+ * Peri > VOP/ISP/VICAP > CPU > GPU/NPU/RKVDEC/RGA/Other
585
+ * (5) (4) (3) (2)
586
+ *
587
+ * NOTE: GPU qos init is in kernel, in case that vdd gpu is off now.
588
+ */
589
+ writel(QOS_PRIORITY_LEVEL(5, 5), CRYPTO_PRIORITY_REG);
590
+ writel(QOS_PRIORITY_LEVEL(5, 5), DMAC_PRIORITY_REG);
591
+ writel(QOS_PRIORITY_LEVEL(5, 5), EMMC_PRIORITY_REG);
592
+ writel(QOS_PRIORITY_LEVEL(5, 5), FSPI_PRIORITY_REG);
593
+ writel(QOS_PRIORITY_LEVEL(5, 5), GMAC_PRIORITY_REG);
594
+ writel(QOS_PRIORITY_LEVEL(5, 5), MAC100_PRIORITY_REG);
595
+ writel(QOS_PRIORITY_LEVEL(5, 5), MCU_PRIORITY_REG);
596
+ writel(QOS_PRIORITY_LEVEL(5, 5), RKDMA_PRIORITY_REG);
597
+ writel(QOS_PRIORITY_LEVEL(5, 5), SDMMC0_PRIORITY_REG);
598
+ writel(QOS_PRIORITY_LEVEL(5, 5), SDMMC1_PRIORITY_REG);
599
+ writel(QOS_PRIORITY_LEVEL(5, 5), USB2_PRIORITY_REG);
600
+ writel(QOS_PRIORITY_LEVEL(5, 5), USB3_PRIORITY_REG);
601
+ writel(QOS_PRIORITY_LEVEL(4, 4), ISP_PRIORITY_REG);
602
+ writel(QOS_PRIORITY_LEVEL(4, 4), VICAP_PRIORITY_REG);
603
+ writel(QOS_PRIORITY_LEVEL(4, 4), VOP_PRIORITY_REG);
604
+ writel(QOS_PRIORITY_LEVEL(2, 2), DCF_PRIORITY_REG);
605
+ writel(QOS_PRIORITY_LEVEL(2, 2), DMA2DDR_PRIORITY_REG);
606
+ writel(QOS_PRIORITY_LEVEL(2, 2), PCIE_PRIORITY_REG);
607
+}
608
+
609
+int arch_cpu_init(void)
610
+{
611
+ u32 val;
612
+
613
+ /* Set the emmc to access ddr memory */
614
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST4_REG);
615
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST4_REG);
616
+
617
+ /* Set the sdmmc to access ddr memory */
618
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
619
+ writel(val & 0xff0000ff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
620
+
621
+ /*
622
+ * Set SAIx_MCLK as input default
623
+ *
624
+ * It's safe to set mclk as input default to avoid high freq glitch
625
+ * which may make devices work unexpected. And then enabled by
626
+ * kernel stage or any state where user use it.
627
+ */
628
+ writel(0x0a100000, PERI_GRF_BASE + PERI_GRF_AUDIO_CON);
629
+
630
+ /* Assert reset the pipe phy to save power and de-assert when in use */
631
+ writel(0x00030001, PIPEPHY_GRF_BASE + PIPEPHY_PIPE_CON5);
632
+
633
+#if defined(CONFIG_ROCKCHIP_SFC)
634
+ /* Set the fspi to access ddr memory */
635
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
636
+ writel(val & 0x00ffffff, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
637
+
638
+ /*
639
+ * Fix fspi io ds level:
640
+ *
641
+ * level 2 for 1V8
642
+ * level 3 for 3V3
643
+ */
644
+ if (readl(GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L) == 0x2222) {
645
+ if (readl(GPIO2_IOC_BASE + GPIO2_IOC_IO_VSEL0) & POC_VCCIO2_VD_3V3) {
646
+ writel(0x3f3f0f0f, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS0);
647
+ writel(0x3f3f0f0f, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS1);
648
+ writel(0x3f3f0f0f, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_DS0);
649
+ } else {
650
+ writel(0x3f3f0707, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS0);
651
+ writel(0x3f3f0707, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS1);
652
+ writel(0x3f3f0707, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_DS0);
653
+ }
654
+ }
655
+#endif
656
+
657
+ qos_priority_init();
658
+
659
+ return 0;
660
+}
661
+#endif
u-boot/arch/arm/mach-rockchip/rk3562/syscon_rk3562.c
....@@ -0,0 +1,26 @@
1
+/*
2
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+
7
+#include <common.h>
8
+#include <dm.h>
9
+#include <syscon.h>
10
+#include <asm/arch/clock.h>
11
+
12
+static const struct udevice_id rk3562_syscon_ids[] = {
13
+ { .compatible = "rockchip,rk3562-sys-grf", .data = ROCKCHIP_SYSCON_GRF },
14
+ { .compatible = "rockchip,rk3562-pmu-grf", .data = ROCKCHIP_SYSCON_PMUGRF },
15
+ { .compatible = "rockchip,rk3562-ioc-grf", .data = ROCKCHIP_SYSCON_IOC },
16
+ { }
17
+};
18
+
19
+U_BOOT_DRIVER(syscon_rk3562) = {
20
+ .name = "rk3562_syscon",
21
+ .id = UCLASS_SYSCON,
22
+ .of_match = rk3562_syscon_ids,
23
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
24
+ .bind = dm_scan_fdt_dev,
25
+#endif
26
+};
u-boot/arch/arm/mach-rockchip/rk3568/rk3568.c
....@@ -777,6 +777,23 @@
777777 #endif
778778 }
779779
780
+int fit_standalone_release(char *id, uintptr_t entry_point)
781
+{
782
+ /* risc-v configuration: */
783
+ /* Reset the scr1 */
784
+ writel(0x04000400, CRU_BASE + CRU_SOFTRST_CON26);
785
+ udelay(100);
786
+
787
+ /* set the scr1 addr */
788
+ writel((0xffff0000) | (entry_point >> 16), GRF_BASE + GRF_SOC_CON4);
789
+ udelay(10);
790
+
791
+ /* release the scr1 */
792
+ writel(0x04000000, CRU_BASE + CRU_SOFTRST_CON26);
793
+
794
+ return 0;
795
+}
796
+
780797 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
781798 static void qos_priority_init(void)
782799 {
u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c
....@@ -19,20 +19,31 @@
1919 #define FIREWALL_DDR_BASE 0xfe030000
2020 #define FW_DDR_MST5_REG 0x54
2121 #define FW_DDR_MST13_REG 0x74
22
+#define FW_DDR_MST19_REG 0x8c
2223 #define FW_DDR_MST21_REG 0x94
2324 #define FW_DDR_MST26_REG 0xa8
2425 #define FW_DDR_MST27_REG 0xac
2526 #define FIREWALL_SYSMEM_BASE 0xfe038000
2627 #define FW_SYSM_MST5_REG 0x54
2728 #define FW_SYSM_MST13_REG 0x74
29
+#define FW_SYSM_MST19_REG 0x8c
2830 #define FW_SYSM_MST21_REG 0x94
2931 #define FW_SYSM_MST26_REG 0xa8
3032 #define FW_SYSM_MST27_REG 0xac
33
+#define PMU1_SGRF_BASE 0xfd582000
34
+#define PMU1_SGRF_SOC_CON0 0x0
35
+#define PMU1_SGRF_SOC_CON6 0x18
36
+#define PMU1_SGRF_SOC_CON7 0x1c
37
+#define PMU1_SGRF_SOC_CON8 0x20
38
+#define PMU1_SGRF_SOC_CON9 0x24
39
+#define PMU1_SGRF_SOC_CON10 0x28
40
+#define PMU1_SGRF_SOC_CON13 0x34
3141 #define SYS_GRF_BASE 0xfd58c000
3242 #define SYS_GRF_SOC_CON6 0x0318
3343 #define USBGRF_BASE 0xfd5ac000
3444 #define USB_GRF_USB3OTG0_CON1 0x001c
3545 #define BUS_SGRF_BASE 0xfd586000
46
+#define BUS_SGRF_SOC_CON2 0x08
3647 #define BUS_SGRF_FIREWALL_CON18 0x288
3748 #define PMU_BASE 0xfd8d0000
3849 #define PMU_PWR_GATE_SFTCON1 0x8150
....@@ -66,14 +77,21 @@
6677 #define EMMC_IOC_GPIO2D_DS_H 0x5c
6778
6879 #define CRU_BASE 0xfd7c0000
80
+#define CRU_GPLL_CON1 0x01c4
6981 #define CRU_SOFTRST_CON77 0x0b34
82
+#define CRU_GLB_RST_CON 0x0c10
7083
7184 #define PMU1CRU_BASE 0xfd7f0000
85
+#define PMU1CRU_SOFTRST_CON00 0x0a00
7286 #define PMU1CRU_SOFTRST_CON03 0x0a0c
7387 #define PMU1CRU_SOFTRST_CON04 0x0a10
7488
7589 #define HDMIRX_NODE_FDT_PATH "/hdmirx-controller@fdee0000"
7690 #define RK3588_PHY_CONFIG 0xfdee00c0
91
+
92
+#define VOP_M0_PRIORITY_REG 0xfdf82008
93
+#define VOP_M1_PRIORITY_REG 0xfdf82208
94
+#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7))
7795
7896 #ifdef CONFIG_ARM64
7997 #include <asm/armv8/mmu.h>
....@@ -865,8 +883,15 @@
865883 secure_reg &= 0xffff0000;
866884 writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
867885
868
- /* Select clk_tx source as default for i2s2/i2s3 */
869
- writel(0x03400340, SYS_GRF_BASE + SYS_GRF_SOC_CON6);
886
+ /*
887
+ * Select clk_tx source as default for i2s2/i2s3
888
+ * Set I2Sx_MCLK as input default
889
+ *
890
+ * It's safe to set mclk as input default to avoid high freq glitch
891
+ * which may make devices work unexpected. And then enabled by
892
+ * kernel stage or any state where user use it.
893
+ */
894
+ writel(0x03c703c7, SYS_GRF_BASE + SYS_GRF_SOC_CON6);
870895
871896 if (readl(BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L) == 0x2222) {
872897 /* Set the fspi m0 io ds level to 55ohm */
....@@ -922,7 +947,14 @@
922947 writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L);
923948 writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_H);
924949 #endif
925
-
950
+ /*
951
+ * set VOP M0 and VOP M1 to priority 0x303,then
952
+ * Peri > VOP/MCU > ISP/VICAP > other
953
+ * Note: VOP priority can only be modified during the u-boot stage,
954
+ * as VOP default power down, and power up after trust.
955
+ */
956
+ writel(QOS_PRIORITY_LEVEL(3, 3), VOP_M0_PRIORITY_REG);
957
+ writel(QOS_PRIORITY_LEVEL(3, 3), VOP_M1_PRIORITY_REG);
926958 #endif
927959
928960 /* Select usb otg0 phy status to 0 that make rockusb can work at high-speed */
....@@ -1245,31 +1277,36 @@
12451277 #ifdef CONFIG_SPL_BUILD
12461278 int spl_fit_standalone_release(char *id, uintptr_t entry_point)
12471279 {
1248
- /* gpll enable */
1249
- writel(0x00f00042, 0xfd7c01c4);
1280
+ u32 val;
1281
+
1282
+ /* pmu m0 configuration: */
1283
+ /* set gpll */
1284
+ writel(0x00f00042, CRU_BASE + CRU_GPLL_CON1);
1285
+ /* set pmu mcu to access ddr memory */
1286
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST19_REG);
1287
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST19_REG);
1288
+ /* set pmu mcu to access system memory */
1289
+ val = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST19_REG);
1290
+ writel(val & 0x000000ff, FIREWALL_SYSMEM_BASE + FW_SYSM_MST19_REG);
1291
+ /* set pmu mcu to secure */
1292
+ writel(0x00080000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON0);
12501293 /* set start addr, pmu_mcu_code_addr_start */
1251
- writel(0xFFFF0000 | (entry_point >> 16), 0xFD582024);
1252
- /* pmu_mcu_sram_addr_start */
1253
- writel(0xFFFF2000, 0xFD582028);
1254
- /* pmu_mcu_tcm_addr_start */
1255
- writel(0xFFFF2000, 0xFD582034);
1256
- /* set mcu secure */
1257
- writel(0x00080000, 0xFD582000);
1294
+ writel(0xFFFF0000 | (entry_point >> 16), PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON9);
1295
+ /* set pmu_mcu_sram_addr_start */
1296
+ writel(0xFFFF2000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON10);
1297
+ /* set pmu_mcu_tcm_addr_start */
1298
+ writel(0xFFFF2000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON13);
12581299 /* set cache cache_peripheral_addr */
1259
- writel(0xffff0000, 0xFD582018);
1260
- writel(0xffffee00, 0xFD58201c);
1261
- writel(0x00ff00ff, 0xFD582020); /* 0xf0000000 ~ 0xfee00000 */
1262
- /* mcupmu access DDR secure control, each bit for a region. */
1263
- writel(0x0000ffff, 0xFE03008C);
1264
- /* mcupmu access DDR secure control, each bit for a region. */
1265
- writel(0x000000ff, 0xFE03808C);
1266
- /* PMU WDT reset system enable */
1267
- writel(0x02000200, 0xFD586008);
1268
- /* WDT trigger global reset. */
1269
- writel(0x08400840, 0xFD7C0C10);
1270
- /* Spl helps to load the mcu image, but not need to release
1271
- * mcu for rk3588.
1272
- */
1300
+ /* 0xf0000000 ~ 0xfee00000 */
1301
+ writel(0xffff0000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON6);
1302
+ writel(0xffffee00, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON7);
1303
+ writel(0x00ff00ff, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON8);
1304
+ /* enable PMU WDT reset system */
1305
+ writel(0x02000200, BUS_SGRF_BASE + BUS_SGRF_SOC_CON2);
1306
+ /* select WDT trigger global reset. */
1307
+ writel(0x08400840, CRU_BASE + CRU_GLB_RST_CON);
1308
+ /* release pmu mcu */
1309
+ /* writel(0x20000000, PMU1CRU_BASE + PMU1CRU_SOFTRST_CON00); */
12731310
12741311 return 0;
12751312 }
u-boot/arch/arm/mach-rockchip/rk_meta.c
....@@ -50,6 +50,7 @@
5050 ulong sector;
5151 char *data;
5252 u64 len;
53
+ int meta_iq_item_size = 0;
5354
5455 if (part_get_info_by_name(info->dev, part_name, &part_info) <= 0) {
5556 debug("%s: no partition\n", __func__);
....@@ -91,32 +92,31 @@
9192
9293 /* load compress data */
9394 data = (char *)COMPRESS_LOAD_ADDR;
95
+ meta_iq_item_size = meta_p->iq_item_size + meta.comp_size;
9496 if (meta_p->comp_type == META_COMPRESS_TYPE_GZ) {
9597 if (info->read(info, sector + (MAX_META_SEGMENT_SIZE / info->bl_len),
96
- DIV_ROUND_UP(meta.comp_size, info->bl_len), data)
97
- != DIV_ROUND_UP(meta.comp_size, info->bl_len)) {
98
- debug("%s: Failed to read compress data.\n", __func__);
98
+ DIV_ROUND_UP(meta_iq_item_size, info->bl_len), data)
99
+ != DIV_ROUND_UP(meta_iq_item_size, info->bl_len)) {
100
+ printf("%s: Failed to read compress data.\n", __func__);
99101 return -EIO;
100102 }
103
+
104
+ memcpy((void *)(meta_p->load + SENSOR_IQ_BIN_OFFSET), data, meta_p->iq_item_size);
101105
102106 if (rk_meta_iq_decom((meta_p->load + meta_p->comp_off),
103107 (unsigned long)(data + meta_p->comp_off -
104108 MAX_META_SEGMENT_SIZE),
105109 meta.comp_size, &len)) {
106
- debug("%s: Failed to decompress.\n", __func__);
110
+ printf("%s: Failed to decompress.\n", __func__);
107111 return -EIO;
108112 }
109
- /* update decompress gz's file size */
110
- unsigned int *p_len = (unsigned int *)
111
- (meta_p->load + MAX_META_SEGMENT_SIZE + MAX_HEAD_SIZE);
112
- *p_len = (u32)len;
113
- /* TODO: update decompress gz's file crc32 */
113
+
114114 } else {
115115 if (info->read(info, sector + (MAX_META_SEGMENT_SIZE / info->bl_len),
116
- DIV_ROUND_UP(meta.comp_size, info->bl_len),
116
+ DIV_ROUND_UP(meta_iq_item_size, info->bl_len),
117117 (void *)(meta_p->load + MAX_META_SEGMENT_SIZE))
118
- != DIV_ROUND_UP(meta.comp_size, info->bl_len)) {
119
- debug("%s: Failed to read\n", __func__);
118
+ != DIV_ROUND_UP(meta_iq_item_size, info->bl_len)) {
119
+ printf("%s: Failed to read\n", __func__);
120120 return -EIO;
121121 }
122122 }
....@@ -125,6 +125,7 @@
125125 flush_cache(meta_p->load, meta_p->size);
126126 rk_meta_process();
127127
128
+ printf("\nMeta: ok\n");
128129 return 0;
129130 }
130131
u-boot/arch/arm/mach-rockchip/rockchip_smccc.c
....@@ -61,6 +61,15 @@
6161 return res.a0;
6262 }
6363
64
+int sip_smc_remotectl_config(unsigned long func, unsigned long data)
65
+{
66
+ struct arm_smccc_res res;
67
+
68
+ res = __invoke_sip_fn_smc(SIP_REMOTECTL_CFG, func, data, 0);
69
+
70
+ return res.a0;
71
+}
72
+
6473 int sip_smc_amp_cfg(unsigned long func, unsigned long arg0, unsigned long arg1,
6574 unsigned long arg2)
6675 {
....@@ -142,3 +151,11 @@
142151
143152 return 0;
144153 }
154
+
155
+int sip_smc_mcu_config(unsigned long mcu_id, unsigned long func, unsigned long arg2)
156
+{
157
+ struct arm_smccc_res res;
158
+
159
+ res = __invoke_sip_fn_smc(SIP_MCU_CFG, mcu_id, func, arg2);
160
+ return res.a0;
161
+}
u-boot/arch/arm/mach-rockchip/rv1106/rv1106.c
....@@ -7,6 +7,9 @@
77 #include <boot_rkimg.h>
88 #include <cli.h>
99 #include <debug_uart.h>
10
+#include <miiphy.h>
11
+#include <syscon.h>
12
+#include <asm/arch/clock.h>
1013 #include <asm/io.h>
1114 #include <asm/arch/hardware.h>
1215 #include <asm/arch/grf_rv1106.h>
....@@ -538,15 +541,65 @@
538541 }
539542 #endif
540543
541
-int rk_board_late_init(void)
542
-{
543
-#if defined(CONFIG_CMD_SCRIPT_UPDATE)
544
- struct blk_desc *desc;
544
+#if (defined CONFIG_MII || defined CONFIG_CMD_MII || defined CONFIG_PHYLIB)
545
+#define GMAC_NODE_FDT_PATH "/ethernet@ffa80000"
546
+#define RK630_MII_NAME "ethernet@ffa80000"
547
+#define PHY_ADDR 2
548
+#define PAGE_SWITCH 0x1f
549
+#define DISABLE_APS_REG 0x12
550
+#define DISABLE_APS_VAL 0x4824
551
+#define PHYAFE_PDCW_REG 0x1c
552
+#define PHYAFE_PDCW_VAL 0x8880
553
+#define PD_ANALOG_REG 0x0
554
+#define PD_ANALOG_VAL 0x3900
555
+#define RV1106_MACPHY_SHUTDOWN BIT(1)
556
+#define RV1106_MACPHY_ENABLE_MASK BIT(1)
545557
546
- desc = rockchip_get_bootdev();
547
- if (desc && desc->if_type == IF_TYPE_MMC && desc->devnum == 1)
548
- run_command("sd_update", 0);
549
-#endif
558
+static int rk_board_fdt_pwrdn_gmac(const void *blob)
559
+{
560
+ void *fdt = (void *)gd->fdt_blob;
561
+ struct rv1106_grf *grf;
562
+ int gmac_node;
563
+
564
+ /* Turn off GMAC FEPHY to reduce chip power consumption at uboot level,
565
+ * if the gmac node is disabled at kernel dtb. RV1106/1103 has the
566
+ * internal gmac phy, u-boot.dtb defines and enables the gmac node
567
+ * by default, so even if the gmac node of the kernel dts is disabled,
568
+ * U-Boot will enable and initialize the gmac phy. So it is not okay
569
+ * to turn off gmac phy by default in arch_cpu_init(), need to turn off
570
+ * gmac phy in the current function.
571
+ */
572
+ gmac_node = fdt_path_offset(gd->fdt_blob, GMAC_NODE_FDT_PATH);
573
+ if (fdt_stringlist_search(fdt, gmac_node, "status", "disabled") >= 0) {
574
+ /* switch to page 1 */
575
+ miiphy_write(RK630_MII_NAME, PHY_ADDR, PAGE_SWITCH, 0x0100);
576
+ miiphy_write(RK630_MII_NAME, PHY_ADDR, DISABLE_APS_REG,
577
+ DISABLE_APS_VAL);
578
+ /* switch to pae 6 */
579
+ miiphy_write(RK630_MII_NAME, PHY_ADDR, PAGE_SWITCH, 0x0600);
580
+ miiphy_write(RK630_MII_NAME, PHY_ADDR, PHYAFE_PDCW_REG,
581
+ PHYAFE_PDCW_VAL);
582
+ /* switch to page 0 */
583
+ miiphy_write(RK630_MII_NAME, PHY_ADDR, PAGE_SWITCH, 0x0000);
584
+ miiphy_write(RK630_MII_NAME, PHY_ADDR, PD_ANALOG_REG,
585
+ PD_ANALOG_VAL);
586
+
587
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
588
+ if (grf)
589
+ rk_clrsetreg(&grf->macphy_con0,
590
+ RV1106_MACPHY_ENABLE_MASK,
591
+ RV1106_MACPHY_SHUTDOWN);
592
+ }
593
+
550594 return 0;
551595 }
596
+#endif
552597
598
+int rk_board_fdt_fixup(const void *blob)
599
+{
600
+#if (defined CONFIG_MII || defined CONFIG_CMD_MII || defined CONFIG_PHYLIB)
601
+ rk_board_fdt_pwrdn_gmac(blob);
602
+#endif
603
+
604
+ return 0;
605
+}
u-boot/arch/arm/mach-rockchip/rv1126/rv1126.c
....@@ -63,6 +63,9 @@
6363 #define PMU_PWR_DWN_ST (0x108)
6464 #define PMU_PWR_GATE_SFTCON (0x110)
6565
66
+#define PMU_BUS_IDLE_NPU BIT(18)
67
+#define PMU_BUS_IDLE_VEPU BIT(9)
68
+
6669 #define CRU_BASE 0xFF490000
6770 #define CRU_CLKSEL_CON02 0x108
6871 #define CRU_CLKSEL_CON03 0x10c
....@@ -548,6 +551,7 @@
548551 * CONFIG_DM_RAMDISK: for ramboot that without SPL.
549552 */
550553 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DM_RAMDISK)
554
+ u32 pd_st, idle_st;
551555 int delay;
552556
553557 /*
....@@ -624,11 +628,7 @@
624628 do {
625629 udelay(1);
626630 delay--;
627
- if (delay == 0) {
628
- printf("Fail to set domain.");
629
- hang();
630
- }
631
- } while (readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST));
631
+ } while (delay && readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST));
632632
633633 /* release all idle request */
634634 writel(0xffff0000, PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON(0));
....@@ -639,22 +639,30 @@
639639 do {
640640 udelay(1);
641641 delay--;
642
- if (delay == 0) {
643
- printf("Fail to get ack on domain.\n");
644
- hang();
645
- }
646
- } while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ACK));
642
+ } while (delay && readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ACK));
647643
648644 delay = 1000;
649645 /* wait idle status */
650646 do {
651647 udelay(1);
652648 delay--;
653
- if (delay == 0) {
654
- printf("Fail to set idle on domain.\n");
655
- hang();
656
- }
657
- } while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST));
649
+ } while (delay && readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST));
650
+
651
+ pd_st = readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST);
652
+ idle_st = readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST);
653
+
654
+ if (pd_st || idle_st) {
655
+ printf("PMU_PWR_DOWN_ST: 0x%08x\n", pd_st);
656
+ printf("PMU_BUS_IDLE_ST: 0x%08x\n", idle_st);
657
+
658
+ if (idle_st & PMU_BUS_IDLE_NPU)
659
+ printf("Failed to enable PD_NPU, please check VDD_NPU is supplied\n");
660
+
661
+ if (idle_st & PMU_BUS_IDLE_VEPU)
662
+ printf("Failed to enable PD_VEPU, please check VDD_VEPU is supplied\n");
663
+
664
+ hang();
665
+ }
658666
659667 writel(0x303, USB_HOST_PRIORITY_REG);
660668 writel(0x303, USB_OTG_PRIORITY_REG);
u-boot/arch/arm/mach-rockchip/spl.c
....@@ -19,6 +19,7 @@
1919 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
2020 #include <asm/arch/rk_atags.h>
2121 #endif
22
+#include <asm/arch/pcie_ep_boot.h>
2223 #include <asm/arch/sdram.h>
2324 #include <asm/arch/boot_mode.h>
2425 #include <asm/arch-rockchip/sys_proto.h>
....@@ -175,6 +176,9 @@
175176 printascii("U-Boot SPL board init");
176177 #endif
177178 gd->sys_start_tick = get_ticks();
179
+#ifdef CONFIG_SPL_PCIE_EP_SUPPORT
180
+ rockchip_pcie_ep_init();
181
+#endif
178182 #ifdef CONFIG_SPL_FRAMEWORK
179183 ret = spl_early_init();
180184 if (ret) {
....@@ -197,6 +201,9 @@
197201
198202 arch_cpu_init();
199203 rk_board_init_f();
204
+#ifdef CONFIG_SPL_RAM_DEVICE
205
+ rockchip_pcie_ep_get_firmware();
206
+#endif
200207 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
201208 back_to_bootrom(BROM_BOOT_NEXTSTAGE);
202209 #endif
....@@ -368,7 +375,10 @@
368375 spl->next_stage = SPL_NEXT_STAGE_KERNEL;
369376 break;
370377 default:
371
- spl->next_stage = SPL_NEXT_STAGE_UBOOT;
378
+ if ((reg_boot_mode & REBOOT_FLAG) != REBOOT_FLAG)
379
+ spl->next_stage = SPL_NEXT_STAGE_KERNEL;
380
+ else
381
+ spl->next_stage = SPL_NEXT_STAGE_UBOOT;
372382 }
373383 }
374384 #endif
u-boot/arch/arm/mach-rockchip/spl_pcie_ep_boot.c
....@@ -0,0 +1,689 @@
1
+// SPDX-License-Identifier: GPL-2.0+
2
+/*
3
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd
4
+ */
5
+
6
+#include <common.h>
7
+#include <spl.h>
8
+#include <asm/io.h>
9
+#include <asm/arch/cpu.h>
10
+#include <asm/arch/hardware.h>
11
+#include <asm/arch/ioc_rk3588.h>
12
+#include <dt-bindings/clock/rk3588-cru.h>
13
+#include <pci.h>
14
+#include <asm/arch/rk_atags.h>
15
+
16
+#ifndef CONFIG_SPL_LOAD_FIT_ADDRESS
17
+#error "SPL_LOAD_FIT_ADDRESS not defined!"
18
+#endif
19
+
20
+#define printep(fmt, ...) \
21
+ do { \
22
+ printf("RKEP: %d - ", readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x2c) / 24); \
23
+ printf(fmt, ##__VA_ARGS__); \
24
+ } while (0)
25
+
26
+#ifdef CONFIG_ROCKCHIP_RK3588
27
+#define PCIE_SNPS_DBI_BASE 0xf5000000
28
+#define PCIE_SNPS_APB_BASE 0xfe150000
29
+#define PCIE_SNPS_IATU_BASE 0xa40300000
30
+
31
+#define PCI_RESBAR 0x2e8
32
+#elif CONFIG_ROCKCHIP_RK3568
33
+#define PCIE_SNPS_DBI_BASE 0xf6000000
34
+#define PCIE_SNPS_APB_BASE 0xfe280000
35
+#define PCIE_SNPS_IATU_BASE 0x3c0b00000
36
+
37
+#define PCI_RESBAR 0x2b8
38
+#else
39
+#error "this soc is not support pcie ep!"
40
+#endif
41
+
42
+#define RKEP_BAR0_ADDR 0x3c000000
43
+#define RKEP_BAR2_ADDR CONFIG_SPL_LOAD_FIT_ADDRESS
44
+#define RKEP_BAR0_CMD_ADDR (RKEP_BAR0_ADDR + 0x400)
45
+#define RKEP_BOOT_MAGIC 0x524b4550 /* RKEP */
46
+#define RKEP_CMD_LOADER_RUN 0x524b4501
47
+
48
+#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
49
+#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
50
+#define PCI_EXP_LNKCTL2_TLS 0x000f
51
+#define PCI_EXP_LNKCAP_SLS 0x0000000f
52
+
53
+#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
54
+#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
55
+#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
56
+
57
+/* Synopsys-specific PCIe configuration registers */
58
+#define PCIE_PORT_LINK_CONTROL 0x710
59
+#define PORT_LINK_MODE_MASK (0x3f << 16)
60
+#define PORT_LINK_MODE_1_LANES (0x1 << 16)
61
+#define PORT_LINK_MODE_2_LANES (0x3 << 16)
62
+#define PORT_LINK_MODE_4_LANES (0x7 << 16)
63
+#define PORT_LINK_MODE_8_LANES (0xf << 16)
64
+
65
+#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
66
+#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
67
+#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
68
+#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
69
+#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
70
+#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
71
+#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
72
+
73
+#define PCIE_DIRECT_SPEED_CHANGE (0x1 << 17)
74
+
75
+#define LINK_WAIT_IATU 10000
76
+#define PCIE_ATU_ENABLE (0x1 << 31)
77
+#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30 | 1 << 19)
78
+#define PCIE_ATU_UNR_REGION_CTRL1 0x00
79
+#define PCIE_ATU_UNR_REGION_CTRL2 0x04
80
+#define PCIE_ATU_CPU_ADDR_LOW 0x14
81
+#define PCIE_ATU_CPU_ADDR_HIGH 0x18
82
+
83
+/* SRNS: Use Separate refclk(internal clock) instead of from RC */
84
+// #define PCIE_ENABLE_SRNS_PLL_REFCLK
85
+
86
+struct rkpcie_cmd {
87
+ u32 cmd;
88
+ u32 size;
89
+ u32 data[6];
90
+};
91
+
92
+/* rkep device mode status definition */
93
+#define RKEP_MODE_BOOTROM 1
94
+#define RKEP_MODE_LOADER 2
95
+#define RKEP_MODE_KERNEL 3
96
+
97
+/* Common status */
98
+#define RKEP_SMODE_INIT 0
99
+#define RKEP_SMODE_LNKRDY 1
100
+#define RKEP_SMODE_LNKUP 2
101
+#define RKEP_SMODE_ERR 0xff
102
+/* Firmware download status */
103
+#define RKEP_SMODE_FWDLRDY 0x10
104
+#define RKEP_SMODE_FWDLDONE 0x11
105
+/* Application status*/
106
+#define RKEP_SMODE_APPRDY 0x20
107
+
108
+struct rkpcie_boot {
109
+ /* magic: "RKEP" */
110
+ u32 magic;
111
+ u32 version;
112
+ struct {
113
+ u16 mode;
114
+ u16 submode;
115
+ } devmode;
116
+ /* Size of ATAGS for cap */
117
+ u32 cap_size;
118
+ struct {
119
+ u8 cmd;
120
+ u8 status;
121
+ /* Error code for current CMD */
122
+ u16 opcode;
123
+ } cmd_status;
124
+ u32 reserved[2];
125
+ /* RK ATAGS, for mem and other info */
126
+ struct tag cap;
127
+ /* offset 0x400 */
128
+ struct rkpcie_cmd cmd;
129
+};
130
+
131
+static void pcie_inbound_config(void)
132
+{
133
+ u64 base = PCIE_SNPS_IATU_BASE + 0x100;
134
+ u32 val;
135
+ char i;
136
+
137
+ /* BAR0: RKEP_BAR0_ADDR */
138
+ writel(RKEP_BAR0_ADDR, base + PCIE_ATU_CPU_ADDR_LOW);
139
+ writel(0, base + PCIE_ATU_CPU_ADDR_HIGH);
140
+ writel(0, base + PCIE_ATU_UNR_REGION_CTRL1);
141
+ /* PCIE_ATU_UNR_REGION_CTRL2 */
142
+ writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | (0 << 8),
143
+ base + PCIE_ATU_UNR_REGION_CTRL2);
144
+ for (i = 0; i < 5; i++) {
145
+ val = readl(base + PCIE_ATU_UNR_REGION_CTRL2);
146
+ if (val & PCIE_ATU_ENABLE)
147
+ break;
148
+ udelay(LINK_WAIT_IATU);
149
+ }
150
+ printep("BAR0: 0x%x\n", RKEP_BAR0_ADDR);
151
+
152
+ /* BAR2: RKEP_BAR2_ADDR */
153
+ writel(RKEP_BAR2_ADDR, base + PCIE_ATU_CPU_ADDR_LOW + 0x200);
154
+ writel(0, base + PCIE_ATU_CPU_ADDR_HIGH + 0x200);
155
+ writel(0, base + PCIE_ATU_UNR_REGION_CTRL1 + 0x200);
156
+ writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | (2 << 8),
157
+ base + PCIE_ATU_UNR_REGION_CTRL2 + 0x200);
158
+ for (i = 0; i < 5; i++) {
159
+ val = readl(base + PCIE_ATU_UNR_REGION_CTRL2 + 0x200);
160
+ if (val & PCIE_ATU_ENABLE)
161
+ break;
162
+ udelay(LINK_WAIT_IATU);
163
+ }
164
+ printep("BAR2: 0x%x%x\n", 0, RKEP_BAR2_ADDR);
165
+
166
+ /* BAR4 is wired reg, no need iATU */
167
+}
168
+
169
+static int rockchip_pcie_ep_set_bar_flag(void *dbi_base, u32 barno, int flags)
170
+{
171
+ u32 reg;
172
+
173
+ reg = PCI_BASE_ADDRESS_0 + (4 * barno);
174
+
175
+ /* Disabled the upper 32bits BAR to make a 64bits bar pair */
176
+ if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
177
+ writel(0, dbi_base + reg + 0x100000 + 4);
178
+
179
+ writel(flags, dbi_base + reg);
180
+ if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
181
+ writel(0, dbi_base + reg + 4);
182
+
183
+ return 0;
184
+}
185
+
186
+static void pcie_bar_init(void *dbi_base)
187
+{
188
+ void *resbar_base;
189
+
190
+ writel(0, dbi_base + 0x10);
191
+ writel(0, dbi_base + 0x14);
192
+ writel(0, dbi_base + 0x18);
193
+ writel(0, dbi_base + 0x1c);
194
+ writel(0, dbi_base + 0x20);
195
+ writel(0, dbi_base + 0x24);
196
+
197
+ /* Resize BAR0 to support 4M 32bits */
198
+ resbar_base = dbi_base + PCI_RESBAR;
199
+ writel(0xfffff0, resbar_base + 0x4);
200
+ writel(0x2c0, resbar_base + 0x8);
201
+ /* BAR2: 64M 64bits */
202
+ writel(0xfffff0, resbar_base + 0x14);
203
+ writel(0x6c0, resbar_base + 0x18);
204
+ /* BAR4: Fixed for EP wired register, 1M 32bits */
205
+ writel(0xfffff0, resbar_base + 0x24);
206
+ writel(0xc0, resbar_base + 0x28);
207
+ /* Set flags */
208
+ rockchip_pcie_ep_set_bar_flag(dbi_base, 0, PCI_BASE_ADDRESS_MEM_TYPE_32);
209
+ rockchip_pcie_ep_set_bar_flag(dbi_base, 2,
210
+ PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64);
211
+ rockchip_pcie_ep_set_bar_flag(dbi_base, 4, PCI_BASE_ADDRESS_MEM_TYPE_32);
212
+
213
+ /* Close bar1 bar3 bar5 */
214
+ writel(0x0, dbi_base + 0x100000 + 0x14);
215
+ //writel(0x0, dbi_base + 0x100000 + 0x18);
216
+ writel(0x0, dbi_base + 0x100000 + 0x1c);
217
+ //writel(0x0, dbi_base + 0x100000 + 0x20);
218
+ writel(0x0, dbi_base + 0x100000 + 0x24);
219
+ /* Close ROM BAR */
220
+ writel(0x0, dbi_base + 0x100000 + 0x30);
221
+}
222
+
223
+static void pcie_bar0_header_init(void)
224
+{
225
+ struct rkpcie_boot *bh = (struct rkpcie_boot *)RKEP_BAR0_ADDR;
226
+
227
+ bh->magic = RKEP_BOOT_MAGIC;
228
+ bh->version = 0x100;
229
+ bh->devmode.mode = RKEP_MODE_LOADER;
230
+ bh->devmode.submode = RKEP_SMODE_INIT;
231
+ bh->cap_size = 0;
232
+
233
+ memset((char *)RKEP_BAR0_CMD_ADDR, 0, sizeof(struct rkpcie_cmd));
234
+}
235
+
236
+static void pcie_link_set_max_speed(void *dbi_base, u32 link_gen)
237
+{
238
+ u32 cap, ctrl2, link_speed;
239
+ u8 offset = 0x70;
240
+
241
+ cap = readl(dbi_base + offset + PCI_EXP_LNKCAP);
242
+ ctrl2 = readl(dbi_base + offset + PCI_EXP_LNKCTL2);
243
+ ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
244
+
245
+ link_speed = link_gen;
246
+
247
+ cap &= ~((u32)PCI_EXP_LNKCAP_SLS);
248
+ writel(ctrl2 | link_speed, dbi_base + offset + PCI_EXP_LNKCTL2);
249
+ writel(cap | link_speed, dbi_base + offset + PCI_EXP_LNKCAP);
250
+}
251
+
252
+static void pcie_link_set_lanes(void *dbi_base, u32 lanes)
253
+{
254
+ u32 val;
255
+
256
+ /* Set the number of lanes */
257
+ val = readl(dbi_base + PCIE_PORT_LINK_CONTROL);
258
+ val &= ~PORT_LINK_MODE_MASK;
259
+ switch (lanes) {
260
+ case 1:
261
+ val |= PORT_LINK_MODE_1_LANES;
262
+ break;
263
+ case 2:
264
+ val |= PORT_LINK_MODE_2_LANES;
265
+ break;
266
+ case 4:
267
+ val |= PORT_LINK_MODE_4_LANES;
268
+ break;
269
+ default:
270
+ printf("RKEP: num-lanes %u: invalid value\n", lanes);
271
+ return;
272
+ }
273
+ writel(val, dbi_base + PCIE_PORT_LINK_CONTROL);
274
+
275
+ /* Set link width speed control register */
276
+ val = readl(dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
277
+ val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
278
+ switch (lanes) {
279
+ case 1:
280
+ val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
281
+ break;
282
+ case 2:
283
+ val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
284
+ break;
285
+ case 4:
286
+ val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
287
+ break;
288
+ }
289
+
290
+ val |= PCIE_DIRECT_SPEED_CHANGE;
291
+
292
+ writel(val, dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
293
+}
294
+
295
+static void pcie_devmode_update(int mode, int submode)
296
+{
297
+ struct rkpcie_boot *bh = (struct rkpcie_boot *)RKEP_BAR0_ADDR;
298
+
299
+ bh->devmode.mode = mode;
300
+ bh->devmode.submode = submode;
301
+ flush_dcache_range(RKEP_BAR0_ADDR, RKEP_BAR0_ADDR + 64);
302
+}
303
+
304
+#ifdef CONFIG_SPL_RAM_DEVICE
305
+static void pcie_wait_for_fw(void)
306
+{
307
+ struct rkpcie_cmd *cmd = (struct rkpcie_cmd *)(RKEP_BAR0_CMD_ADDR);
308
+ int val;
309
+ int i = 0;
310
+
311
+ printep("Link ready! Waiting RC to download Firmware:\n");
312
+ printep("Download uboot.img to BAR2+0\n");
313
+ printep("Download boot.img to BAR2+0x400000\n");
314
+ printep("Send CMD_LOADER_RUN to BAR0+0x400\n");
315
+ while (1) {
316
+ invalidate_dcache_range(RKEP_BAR0_CMD_ADDR,
317
+ RKEP_BAR0_CMD_ADDR + 32);
318
+ val = readl(&cmd->cmd);
319
+ if (val == RKEP_CMD_LOADER_RUN)
320
+ break;
321
+ i++;
322
+ if (!(i % 10))
323
+ printep("Waiting for FW, CMD: %x\n", val);
324
+ mdelay(100);
325
+ }
326
+ /* Invalidate Cache for firmware area: BAR2, 64MB */
327
+ invalidate_dcache_range(RKEP_BAR2_ADDR, RKEP_BAR2_ADDR + 0x4000000);
328
+ printep("Firmware Download complete!\n");
329
+}
330
+
331
+static void pcie_update_atags(void)
332
+{
333
+ struct tag_ram_partition t_ram_part;
334
+
335
+ if (!atags_is_available()) {
336
+ printf("RKEP: No ATAGS data found, create new!\n");
337
+ atags_destroy();
338
+ }
339
+
340
+ /* ram partition */
341
+ memset(&t_ram_part, 0, sizeof(t_ram_part));
342
+ t_ram_part.version = 0;
343
+ t_ram_part.count = 1;
344
+ strcpy(t_ram_part.part[0].name, "boot");
345
+ t_ram_part.part[0].start = RKEP_BAR2_ADDR + 0x400000; /* 4M offset */
346
+ t_ram_part.part[0].size = 0x3c00000; /* 60M size */
347
+ atags_set_tag(ATAG_RAM_PARTITION, &t_ram_part);
348
+}
349
+
350
+void rockchip_pcie_ep_get_firmware(void)
351
+{
352
+ pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_FWDLRDY);
353
+ pcie_wait_for_fw();
354
+ pcie_update_atags();
355
+ pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_FWDLDONE);
356
+}
357
+#endif
358
+
359
+#ifdef CONFIG_ROCKCHIP_RK3588
360
+#define BUS_IOC_GPIO3D_IOMUX_SEL_H 0xfd5f807c
361
+#define GPIO3_BASE 0xfec40000
362
+#define GPIO3_SWPORT_DR_H (GPIO3_BASE + 0x4)
363
+#define GPIO3_SWPORT_DDR_H (GPIO3_BASE + 0xc)
364
+
365
+static void pcie_board_init(void)
366
+{
367
+ /* Enable AU5426 buffer chip on EVB4v10 */
368
+ /* Set GPIO3D4 to gpio output HIGH mode PCIE20_CLK_PWREN */
369
+ writel(0xf << 16, BUS_IOC_GPIO3D_IOMUX_SEL_H);
370
+ writel(0x10001000, GPIO3_SWPORT_DDR_H);
371
+ writel(0x10001000, GPIO3_SWPORT_DR_H);
372
+ udelay(100);
373
+}
374
+
375
+#define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */
376
+#define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */
377
+#define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */
378
+#define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */
379
+#define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */
380
+
381
+#define CRU_BASE_ADDR 0xfd7c0000
382
+#define CRU_SOFTRST_CON32 (CRU_BASE_ADDR + 0x0a80)
383
+#define CRU_SOFTRST_CON33 (CRU_BASE_ADDR + 0x0a84)
384
+#define CRU_SOFTRST_CON34 (CRU_BASE_ADDR + 0x0a88)
385
+#define CRU_GATE_CON32 (CRU_BASE_ADDR + 0x0880)
386
+#define CRU_GATE_CON33 (CRU_BASE_ADDR + 0x0884)
387
+#define CRU_GATE_CON34 (CRU_BASE_ADDR + 0x0888)
388
+#define CRU_GATE_CON38 (CRU_BASE_ADDR + 0x0898)
389
+#define CRU_GATE_CON39 (CRU_BASE_ADDR + 0x089c)
390
+#define PHPTOPCRU_BASE_ADDR 0xfd7c8000
391
+#define PHPTOPCRU_SOFTRST_CON00 (PHPTOPCRU_BASE_ADDR + 0x0a00)
392
+#define PHPTOPCRU_GATE_CON00 (PHPTOPCRU_BASE_ADDR + 0x0800)
393
+#define PCIE3PHY_GRF_BASE 0xfd5b8000
394
+#define RK3588_PCIE3PHY_GRF_CMN_CON0 (PCIE3PHY_GRF_BASE + 0x0000)
395
+#define PCIE3PHY_GRF_PHY0_CON6 (PCIE3PHY_GRF_BASE + 0x0118)
396
+#define PCIE3PHY_GRF_PHY1_CON6 (PCIE3PHY_GRF_BASE + 0x0218)
397
+#define PCIE3PHY_GRF_PHY0_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x1004)
398
+#define PCIE3PHY_GRF_PHY0_LN1_CON1 (PCIE3PHY_GRF_BASE + 0x1104)
399
+#define PCIE3PHY_GRF_PHY1_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x2004)
400
+#define PCIE3PHY_GRF_PHY1_LN1_CON1 (PCIE3PHY_GRF_BASE + 0x2104)
401
+#define FIREWALL_PCIE_MASTER_SEC 0xfe0300f0
402
+#define FIREWALL_PCIE_ACCESS 0xfe586040
403
+#define CRU_PHYREF_ALT_GATE_CON (CRU_BASE_ADDR + 0x0c38)
404
+#define PMU_PWR_GATE_SFTCON1 0xfd8d8150
405
+static void pcie_cru_init(void)
406
+{
407
+ u32 phy0_mplla, phy1_mplla, t0 = 0, t1 = 0;
408
+ u32 i, timeout = 500;
409
+
410
+ /* Enable power domain: PD_PCIE & PD_PHP */
411
+ writel(0x1 << 23 | 0x1 << 21, PMU_PWR_GATE_SFTCON1);
412
+
413
+ /* FixMe init 3.0 PHY */
414
+ /* Phy mode: Aggregation NBNB */
415
+ writel((0x7 << 16) | PHY_MODE_PCIE_AGGREGATION, RK3588_PCIE3PHY_GRF_CMN_CON0);
416
+ printep("PHY Mode 0x%x\n", readl(RK3588_PCIE3PHY_GRF_CMN_CON0) & 7);
417
+ /* Enable clock and sfreset for Controller and PHY */
418
+ writel(0xffff0000, CRU_SOFTRST_CON32);
419
+ writel(0xffff0000, CRU_SOFTRST_CON33);
420
+ writel(0xffff0000, CRU_SOFTRST_CON34);
421
+ writel(0xffff0000, CRU_GATE_CON32);
422
+ writel(0xffff0000, CRU_GATE_CON33);
423
+ writel(0xffff0000, CRU_GATE_CON34);
424
+ writel(0xffff0000, CRU_GATE_CON38);
425
+ writel(0xffff0000, CRU_GATE_CON39);
426
+
427
+ writel((0x1 << 24), PHPTOPCRU_SOFTRST_CON00);
428
+ writel(0xffff0000, PHPTOPCRU_GATE_CON00);
429
+
430
+ /* PHY Reset */
431
+ writel((0x1 << 10) | (0x1 << 26), PHPTOPCRU_SOFTRST_CON00);
432
+
433
+ udelay(1);
434
+
435
+#ifdef PCIE_ENABLE_SRNS_PLL_REFCLK
436
+ writel(0x000f0000, CRU_PHYREF_ALT_GATE_CON);
437
+
438
+ /* PHY0 & PHY1 use internal clock */
439
+ writel(0x0 | (0x1 << 18), PCIE3PHY_GRF_PHY0_CON6);
440
+ writel(0x0 | (0x1 << 18), PCIE3PHY_GRF_PHY1_CON6);
441
+
442
+ /* phy0_rx0_cmn_refclk_mod */
443
+ writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN0_CON1);
444
+ /* phy1_rx0_cmn_refclk_mod */
445
+ writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN1_CON1);
446
+ /* phy0_rx0_cmn_refclk_mod */
447
+ writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY1_LN0_CON1);
448
+ /* phy1_rx0_cmn_refclk_mod */
449
+ writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY1_LN1_CON1);
450
+#endif
451
+
452
+ udelay(1000);
453
+
454
+ /* Deassert PCIe PMA output clamp mode */
455
+ writel((0x1 << 8) | (0x1 << 24), RK3588_PCIE3PHY_GRF_CMN_CON0);
456
+
457
+ /* Deassert PHY Reset */
458
+ writel((0x1 << 26), PHPTOPCRU_SOFTRST_CON00);
459
+
460
+ /* S-Phy: waiting for phy locked */
461
+ for (i = 0; i < timeout; i++) {
462
+ phy0_mplla = readl(PCIE3PHY_GRF_BASE + 0x904);
463
+ phy1_mplla = readl(PCIE3PHY_GRF_BASE + 0xA04);
464
+
465
+ if (phy0_mplla != t0 || phy1_mplla != t1) {
466
+ printf("RKEP: GRF:904=%x, a04=%x...\n", phy0_mplla, phy1_mplla);
467
+
468
+ t0 = phy0_mplla;
469
+ t1 = phy1_mplla;
470
+ if (phy0_mplla == 0xF && phy1_mplla == 0xF)
471
+ break;
472
+ }
473
+
474
+ udelay(10);
475
+ }
476
+
477
+ /* PHY config: no config need for snps3.0phy */
478
+
479
+ /* Enable PCIe Access in firewall and master secure mode */
480
+ writel(0xffff0000, FIREWALL_PCIE_MASTER_SEC);
481
+ writel(0x01800000, FIREWALL_PCIE_ACCESS);
482
+}
483
+#elif CONFIG_ROCKCHIP_RK3568
484
+
485
+static void pcie_board_init(void)
486
+{
487
+ /* to-do */
488
+}
489
+
490
+static const u16 phy_fw[] = {
491
+ #include "./../../../drivers/phy/phy-rockchip-snps-pcie3.fw"
492
+};
493
+
494
+#define GRF_PCIE30PHY_RK3568_CON1 0x4
495
+#define GRF_PCIE30PHY_RK3568_CON3 0xC
496
+#define GRF_PCIE30PHY_RK3568_CON4 0x10
497
+#define GRF_PCIE30PHY_RK3568_CON5 0x14
498
+#define GRF_PCIE30PHY_RK3568_CON6 0x18
499
+#define GRF_PCIE30PHY_RK3568_CON9 0x24
500
+#define GRF_PCIE30PHY_RK3568_STATUS0 0x80
501
+#define RK3568_SRAM_INIT_DONE(reg) ((reg) & BIT(14))
502
+
503
+#define PMUCRU_BASE 0xFDD00000
504
+#define PMUCRU_PMUGATE_CON02 (PMUCRU_BASE + 0x188)
505
+
506
+#define CRU_BASE 0xFDD20000
507
+#define CRU_GATE_CON12 (CRU_BASE + 0x330)
508
+#define CRU_GATE_CON13 (CRU_BASE + 0x334)
509
+#define CRU_GATE_CON33 (CRU_BASE + 0x384)
510
+#define CRU_SOFTRST_CON12 (CRU_BASE + 0x430)
511
+#define CRU_SOFTRST_CON27 (CRU_BASE + 0x46c)
512
+
513
+#define PCIE30_PHY_GRF 0xFDCB8000
514
+
515
+void pcie_cru_init(void)
516
+{
517
+ u32 i, reg;
518
+ void __iomem *mmio = (void __iomem *)0xFE8C0000;
519
+
520
+ /* Enable phy and controoler clk */
521
+ writel(0xffff0000, PMUCRU_PMUGATE_CON02);
522
+ writel(0xffff0000, CRU_GATE_CON12);
523
+ writel(0xffff0000, CRU_GATE_CON13);
524
+ writel(0xffff0000, CRU_GATE_CON33);
525
+ writel(0xffff0000, CRU_SOFTRST_CON27);
526
+
527
+ writel(0x40004000, CRU_SOFTRST_CON27);
528
+ writel(0x80008000, PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9);
529
+
530
+ writel((0x1 << 15) | (0x1 << 31),
531
+ PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); //map to access sram
532
+
533
+#ifdef PCIE_ENABLE_SRNS_PLL_REFCLK
534
+ /* use internal clock */
535
+ writel(0x0 | (0x1 << 31), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON3);
536
+
537
+ /* rx0_cmn_refclk_mode disabled */
538
+ writel((0x0) | (0x1 << 25), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON5);
539
+ /* rx1_cmn_refclk_mode disabled */
540
+ writel((0x0) | (0x1 << 25), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON6);
541
+#endif
542
+
543
+ writel((0x0 << 14) | (0x1 << (14 + 16)),
544
+ PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_ld_done
545
+ writel((0x0 << 13) | (0x1 << (13 + 16)),
546
+ PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_bypass
547
+
548
+ writel(0x40000000, CRU_SOFTRST_CON27);
549
+
550
+ udelay(5);
551
+ printf("RKEP: sram initial\n");
552
+ while (1) {
553
+ reg = readl(PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_STATUS0);
554
+ if (RK3568_SRAM_INIT_DONE(reg))
555
+ break;
556
+ }
557
+ printf("RKEP: sram init done\n");
558
+
559
+ writel((0x3 << 8) | (0x3 << (8 + 16)),
560
+ PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); //map to access sram
561
+ for (i = 0; i < ARRAY_SIZE(phy_fw); i++)
562
+ writel(phy_fw[i], mmio + (i << 2));
563
+
564
+ printf("RKEP: snps pcie3phy FW update! size %ld\n", ARRAY_SIZE(phy_fw));
565
+ writel((0x0 << 8) | (0x3 << (8 + 16)),
566
+ PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9);
567
+ writel((0x1 << 14) | (0x1 << (14 + 16)),
568
+ PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_ld_done
569
+
570
+ writel(0xffff0000, CRU_SOFTRST_CON12);
571
+ writel(0x100010, PCIE_SNPS_APB_BASE + 0x180);
572
+
573
+ udelay(1);
574
+}
575
+#endif
576
+
577
+static void pcie_ep_init(void)
578
+{
579
+ u32 val;
580
+ void *dbi_base = (void *)PCIE_SNPS_DBI_BASE;
581
+ u64 apb_base = PCIE_SNPS_APB_BASE;
582
+ int i, retries = 0;
583
+
584
+#ifdef PCIE_ENABLE_SRNS_PLL_REFCLK
585
+ printep("RefClock in SRNS clock mode\n");
586
+#else
587
+ printep("RefClock in common clock_mode\n");
588
+#endif
589
+
590
+ /*
591
+ * ltssm_enable enhance mode and enable delaying the link training
592
+ * after Hot Reset
593
+ */
594
+ writel(0x120012, apb_base + 0x180);
595
+
596
+ /* Unmask pm_turnoff_int */
597
+ writel(0x04000000, apb_base + 0x18);
598
+
599
+ /* PortLorgic DBI_RO_WR_EN */
600
+ val = readl((dbi_base + 0x8bc));
601
+ val |= 0x1;
602
+ writel(val, dbi_base + 0x8bc);
603
+
604
+reinit:
605
+ pcie_bar_init(dbi_base);
606
+ pcie_inbound_config();
607
+
608
+ /* Device PID, DID */
609
+ writel(0x1d87, dbi_base + 0x00);
610
+ writel(0x356a, dbi_base + 0x02);
611
+ /* Device Class: Processing accelerators */
612
+ writel(0x1200, dbi_base + 0x0a);
613
+
614
+ pcie_link_set_max_speed(dbi_base, PCI_EXP_LNKCTL2_TLS_8_0GT);
615
+
616
+#ifdef CONFIG_ROCKCHIP_RK3588
617
+ pcie_link_set_lanes(dbi_base, 4);
618
+#elif CONFIG_ROCKCHIP_RK3568
619
+ pcie_link_set_lanes(dbi_base, 2);
620
+#endif
621
+
622
+ /* EP mode */
623
+ writel(0xf00000, apb_base);
624
+ udelay(100);
625
+
626
+ /* Enable EP mem/io access */
627
+ val = readl(dbi_base + 0x4);
628
+ writel(val | 0x6, dbi_base + 0x4);
629
+
630
+ if (retries) /* Set app_dly2_done to enable app_ltssm_enable */
631
+ writel(0x80008, apb_base + 0x180);
632
+ else /* Enable LTSSM */
633
+ writel(0xc000c, apb_base);
634
+ printep("init PCIe fast Link up\n");
635
+ pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKRDY);
636
+
637
+ /* Waiting for Link up */
638
+ while (1) {
639
+ val = readl(apb_base + 0x300);
640
+ if (((val & 0x3ffff) & ((0x3 << 16) | 0x11)) == 0x30011)
641
+ break;
642
+ mdelay(1);
643
+ }
644
+ printep("Link up %x\n", val);
645
+ mdelay(3);
646
+
647
+ /* Wait for link stable */
648
+ for (i = 0; i < 10000; i++) {
649
+ val = readl(apb_base + 0x10);
650
+ if (val & 0x4) {
651
+ writel(0x4, apb_base + 0x10);
652
+ printep("Link is reset, int status misc=%x\n", val);
653
+ if (retries < 3) {
654
+ retries++;
655
+ goto reinit;
656
+ } else {
657
+ break;
658
+ }
659
+ }
660
+ udelay(1);
661
+ }
662
+ printep("Done\n");
663
+ pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKUP);
664
+}
665
+
666
+void rockchip_pcie_ep_init(void)
667
+{
668
+ u32 val;
669
+
670
+ printf("\nRKEP: Init PCIe EP\n");
671
+ pcie_bar0_header_init();
672
+
673
+#ifdef CONFIG_ROCKCHIP_RK3588
674
+ writel(0x1 << 23 | 0x1 << 21, PMU_PWR_GATE_SFTCON1);
675
+ udelay(10);
676
+#endif
677
+ /* Re-in pcie initial */
678
+ val = readl(PCIE_SNPS_APB_BASE + 0x300);
679
+ if (((val & 0x3ffff) & ((0x3 << 16))) == 0x30000) {
680
+ printf("RKEP: already link up\n");
681
+ return;
682
+ }
683
+
684
+ pcie_board_init();
685
+ /* CRU and PHY Init */
686
+ pcie_cru_init();
687
+
688
+ pcie_ep_init();
689
+}
u-boot/arch/arm/mach-rockchip/uimage.c
....@@ -12,8 +12,8 @@
1212 #include <asm/arch/resource_img.h>
1313 #include <asm/arch/uimage.h>
1414
15
-static int uimage_load_one(struct blk_desc *dev_desc, disk_partition_t *part,
16
- int pos_off, int size, void *dst)
15
+int uimage_load_one(struct blk_desc *dev_desc, disk_partition_t *part,
16
+ int pos_off, int size, void *dst)
1717 {
1818 u32 blknum, blkoff;
1919 u32 unused;
....@@ -183,31 +183,23 @@
183183 return 0;
184184 }
185185
186
-int uimage_init_resource(void)
187
-{
188
- struct blk_desc *dev_desc;
189
- disk_partition_t part;
190
- image_header_t *hdr;
191
- char *part_name;
192
- ulong data, offset;
193
- ulong size;
194186 #ifdef CONFIG_ROCKCHIP_RESOURCE_IMAGE
195
- ulong dst;
196
- int idx = 3;
197
-#endif
198
- int ret;
187
+int uimage_init_resource(struct blk_desc *dev_desc)
188
+{
189
+ disk_partition_t part;
190
+ ulong data, offset, size;
191
+ image_header_t *hdr;
192
+ char *part_name = PART_BOOT;
193
+ int ret, idx = 3;
194
+ void *buf;
199195
200
- dev_desc = rockchip_get_bootdev();
201
- if (!dev_desc) {
202
- printf("No dev_desc!\n");
203
- return ENODEV;
204
- }
196
+ if (!dev_desc)
197
+ return -ENODEV;
205198
199
+#ifndef CONFIG_ANDROID_AB
206200 if (rockchip_get_boot_mode() == BOOT_MODE_RECOVERY)
207201 part_name = PART_RECOVERY;
208
- else
209
- part_name = PART_BOOT;
210
-
202
+#endif
211203 if (part_get_info_by_name(dev_desc, part_name, &part) < 0) {
212204 UIMG_I("No %s partition\n", part_name);
213205 return -ENODEV;
....@@ -215,35 +207,28 @@
215207
216208 hdr = uimage_get_hdr(dev_desc, &part);
217209 if (!hdr)
218
- return -ENODEV;
210
+ return -EAGAIN;
219211
220212 image_multi_getimg(hdr, idx, &data, &size);
221213 offset = data - (ulong)hdr;
222214 free(hdr);
223215
224
-#ifdef CONFIG_ROCKCHIP_RESOURCE_IMAGE
225
- ulong fdt_addr;
226
-
227
- /* reserve enough space before fdt */
228
- fdt_addr = env_get_ulong("fdt_addr_r", 16, 0);
229
- dst = (ulong)fdt_addr -
230
- ALIGN(size, dev_desc->blksz) - CONFIG_SYS_FDT_PAD;
231
- ret = uimage_load_one(dev_desc, &part, offset, size, (void *)dst);
232
- if (ret) {
233
- UIMG_I("Failed to load resource file, ret=%d\n", ret);
234
- return ret;
235
- }
236
-
237
- if (!sysmem_alloc_base(MEM_RESOURCE, (phys_addr_t)dst,
238
- ALIGN(size, RK_BLK_SIZE)))
216
+ buf = memalign(ARCH_DMA_MINALIGN, ALIGN(size, dev_desc->blksz));
217
+ if (!buf)
239218 return -ENOMEM;
240219
241
- ret = resource_create_ram_list(dev_desc, (void *)dst);
220
+ printf("RESC: '%s', blk@0x%08lx\n", part.name,
221
+ part.start + (offset / dev_desc->blksz));
222
+ ret = uimage_load_one(dev_desc, &part, offset, size, buf);
223
+ if (ret)
224
+ return ret;
225
+
226
+ ret = resource_setup_ram_list(dev_desc, buf);
242227 if (ret) {
243
- UIMG_I("Failed to create resource list, ret=%d\n", ret);
228
+ UIMG_I("Failed to setup resource ram list, ret=%d\n", ret);
244229 return ret;
245230 }
246
-#endif
247231
248232 return 0;
249233 }
234
+#endif
u-boot/arch/arm/mach-rockchip/vendor.c
....@@ -10,6 +10,7 @@
1010 #include <boot_rkimg.h>
1111 #include <nand.h>
1212 #include <part.h>
13
+#include <fdt_support.h>
1314
1415 /* tag for vendor check */
1516 #define VENDOR_TAG 0x524B5644
....@@ -20,6 +21,9 @@
2021 /* align to 64 bytes */
2122 #define VENDOR_BTYE_ALIGN 0x3F
2223 #define VENDOR_BLOCK_SIZE 512
24
+
25
+#define PAGE_ALGIN_SIZE (4096uL)
26
+#define PAGE_ALGIN_MASK (~(PAGE_ALGIN_SIZE - 1))
2327
2428 /* --- Emmc define --- */
2529 /* Starting address of the Vendor in memory. */
....@@ -493,13 +497,14 @@
493497 /* Initialize */
494498 bootdev_type = dev_desc->if_type;
495499
496
- /* Always use, no need to release */
497
- buffer = (u8 *)malloc(size);
500
+ /* Always use, no need to release, align to page size for kerenl reserved memory */
501
+ buffer = (u8 *)memalign(PAGE_ALGIN_SIZE, size);
498502 if (!buffer) {
499503 printf("[Vendor ERROR]:Malloc failed!\n");
500504 ret = -ENOMEM;
501505 goto out;
502506 }
507
+
503508 /* Pointer initialization */
504509 vendor_info.hdr = (struct vendor_hdr *)buffer;
505510 vendor_info.item = (struct vendor_item *)(buffer + sizeof(struct vendor_hdr));
....@@ -566,6 +571,29 @@
566571 return ret;
567572 }
568573
574
+void vendor_storage_fixup(void *blob)
575
+{
576
+ unsigned long size;
577
+ unsigned long start;
578
+ ulong offset;
579
+
580
+ /* init vendor storage */
581
+ if (!bootdev_type) {
582
+ if (vendor_storage_init() < 0)
583
+ return;
584
+ }
585
+
586
+ offset = fdt_node_offset_by_compatible(blob, 0, "rockchip,vendor-storage-rm");
587
+ if (offset >= 0) {
588
+ start = (unsigned long)vendor_info.hdr;
589
+ size = (unsigned long)((void *)vendor_info.version2 - (void *)vendor_info.hdr);
590
+ size += 4;
591
+ fdt_update_reserved_memory(blob, "rockchip,vendor-storage-rm",
592
+ (u64)start,
593
+ (u64)size);
594
+ }
595
+}
596
+
569597 /*
570598 * @id: item id, first 4 id is occupied:
571599 * VENDOR_SN_ID
u-boot/board/rockchip/evb_rk3528/Kconfig
....@@ -0,0 +1,15 @@
1
+if TARGET_EVB_RK3528
2
+
3
+config SYS_BOARD
4
+ default "evb_rk3528"
5
+
6
+config SYS_VENDOR
7
+ default "rockchip"
8
+
9
+config SYS_CONFIG_NAME
10
+ default "evb_rk3528"
11
+
12
+config BOARD_SPECIFIC_OPTIONS # dummy
13
+ def_bool y
14
+
15
+endif
u-boot/board/rockchip/evb_rk3528/Makefile
....@@ -0,0 +1,7 @@
1
+#
2
+# SPDX-License-Identifier: GPL-2.0+
3
+#
4
+# Copyright (c) 2020 Rockchip Electronics Co., Ltd
5
+#
6
+
7
+obj-y += evb_rk3528.o
u-boot/board/rockchip/evb_rk3528/evb_rk3528.c
....@@ -0,0 +1,33 @@
1
+/*
2
+ * SPDX-License-Identifier: GPL-2.0+
3
+ *
4
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
5
+ */
6
+
7
+#include <common.h>
8
+#include <dwc3-uboot.h>
9
+#include <usb.h>
10
+
11
+DECLARE_GLOBAL_DATA_PTR;
12
+
13
+#ifdef CONFIG_USB_DWC3
14
+static struct dwc3_device dwc3_device_data = {
15
+ .maximum_speed = USB_SPEED_HIGH,
16
+ .base = 0xfe500000,
17
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
18
+ .index = 0,
19
+ .dis_u2_susphy_quirk = 1,
20
+ .usb2_phyif_utmi_width = 16,
21
+};
22
+
23
+int usb_gadget_handle_interrupts(void)
24
+{
25
+ dwc3_uboot_handle_interrupt(0);
26
+ return 0;
27
+}
28
+
29
+int board_usb_init(int index, enum usb_init_type init)
30
+{
31
+ return dwc3_uboot_init(&dwc3_device_data);
32
+}
33
+#endif
u-boot/board/rockchip/evb_rk3562/Kconfig
....@@ -0,0 +1,15 @@
1
+if TARGET_EVB_RK3562
2
+
3
+config SYS_BOARD
4
+ default "evb_rk3562"
5
+
6
+config SYS_VENDOR
7
+ default "rockchip"
8
+
9
+config SYS_CONFIG_NAME
10
+ default "evb_rk3562"
11
+
12
+config BOARD_SPECIFIC_OPTIONS # dummy
13
+ def_bool y
14
+
15
+endif
u-boot/board/rockchip/evb_rk3562/Makefile
....@@ -0,0 +1,7 @@
1
+#
2
+# SPDX-License-Identifier: GPL-2.0+
3
+#
4
+# Copyright (c) 2022 Rockchip Electronics Co., Ltd
5
+#
6
+
7
+obj-y += evb_rk3562.o
u-boot/board/rockchip/evb_rk3562/evb_rk3562.c
....@@ -0,0 +1,33 @@
1
+/*
2
+ * SPDX-License-Identifier: GPL-2.0+
3
+ *
4
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
5
+ */
6
+
7
+#include <common.h>
8
+#include <dwc3-uboot.h>
9
+#include <usb.h>
10
+
11
+DECLARE_GLOBAL_DATA_PTR;
12
+
13
+#ifdef CONFIG_USB_DWC3
14
+static struct dwc3_device dwc3_device_data = {
15
+ .maximum_speed = USB_SPEED_HIGH,
16
+ .base = 0xfe500000,
17
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
18
+ .index = 0,
19
+ .dis_u2_susphy_quirk = 1,
20
+ .usb2_phyif_utmi_width = 16,
21
+};
22
+
23
+int usb_gadget_handle_interrupts(void)
24
+{
25
+ dwc3_uboot_handle_interrupt(0);
26
+ return 0;
27
+}
28
+
29
+int board_usb_init(int index, enum usb_init_type init)
30
+{
31
+ return dwc3_uboot_init(&dwc3_device_data);
32
+}
33
+#endif
u-boot/cmd/Kconfig
....@@ -1020,6 +1020,13 @@
10201020 This provides various sub-commands to initialise and configure the
10211021 Turndra tsi148 device. See the command help for full details.
10221022
1023
+config CMD_UFS
1024
+ bool "Enable UFS - Universal Flash Subsystem commands"
1025
+ depends on UFS
1026
+ help
1027
+ "This provides commands to initialise and configure universal flash
1028
+ subsystem devices"
1029
+
10231030 config CMD_UNIVERSE
10241031 bool "universe - Command to set up the Turndra Universe controller"
10251032 help
....@@ -1181,15 +1188,7 @@
11811188
11821189 endmenu
11831190
1184
-config CMD_MEMTESTER
1185
- bool "Enable memtester for ddr"
1186
- help
1187
- This enables memtester for ddr.
1188
-
1189
-config CMD_DDR_TEST_TOOL
1190
- bool "Enable ddr test tool"
1191
- help
1192
- This enable ddr test tool code.
1191
+source "cmd/ddr_tool/Kconfig"
11931192
11941193 menu "Misc commands"
11951194
u-boot/cmd/Makefile
....@@ -91,8 +91,7 @@
9191 obj-$(CONFIG_ID_EEPROM) += mac.o
9292 obj-$(CONFIG_CMD_MD5SUM) += md5sum.o
9393 obj-$(CONFIG_CMD_MEMORY) += mem.o
94
-obj-$(CONFIG_CMD_MEMTESTER) += memtester/
95
-obj-$(CONFIG_CMD_DDR_TEST_TOOL) += ddr_tool/
94
+obj-$(CONFIG_CMD_DDR_TOOL) += ddr_tool/
9695 obj-$(CONFIG_CMD_IO) += io.o
9796 obj-$(CONFIG_CMD_MFSL) += mfsl.o
9897 obj-$(CONFIG_CMD_MII) += mii.o
....@@ -149,6 +148,7 @@
149148 obj-$(CONFIG_CMD_UNZIP) += unzip.o
150149 obj-$(CONFIG_CMD_LZMADEC) += lzmadec.o
151150 obj-$(CONFIG_CMD_SCRIPT_UPDATE) += script_update.o
151
+obj-$(CONFIG_CMD_UFS) += ufs.o
152152 obj-$(CONFIG_CMD_USB) += usb.o disk.o
153153 obj-$(CONFIG_CMD_FASTBOOT) += fastboot.o
154154 obj-$(CONFIG_CMD_FS_UUID) += fs_uuid.o
u-boot/cmd/boot_android.c
....@@ -13,6 +13,7 @@
1313 #include <common.h>
1414 #include <bootm.h>
1515 #include <command.h>
16
+#include <mp_boot.h>
1617 #include <android_bootloader_message.h>
1718 #include <android_avb/rk_avb_ops_user.h>
1819 #include <android_avb/avb_atx_ops.h>
....@@ -30,6 +31,9 @@
3031 if (argc > 5)
3132 return CMD_RET_USAGE;
3233
34
+#ifdef CONFIG_MP_BOOT_BOOTM
35
+ mpb_post(5);
36
+#endif
3337 if (argc >= 5) {
3438 load_address = simple_strtoul(argv[4], &addr_arg_endp, 16);
3539 if (addr_arg_endp == argv[4] || *addr_arg_endp != '\0')
u-boot/cmd/bootfit.c
....@@ -103,7 +103,6 @@
103103
104104 strcat(slot_info, slot_suffix);
105105 env_update("bootargs", slot_info);
106
- ab_update_root_uuid();
107106 #endif
108107
109108 ret = do_bootm_states(NULL, 0, ARRAY_SIZE(bootm_args), bootm_args,
u-boot/cmd/cache.c
....@@ -54,7 +54,24 @@
5454
5555 static int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
5656 {
57
+ ulong start, size;
58
+
5759 switch (argc) {
60
+ case 4:
61
+ start = simple_strtoul(argv[2], NULL, 16);
62
+ size = simple_strtoul(argv[3], NULL, 16);
63
+
64
+ switch (parse_argv(argv[1])) {
65
+ case 2:
66
+ printf("flush dcache: 0x%08lx - 0x%08lx\n", start, start + size);
67
+ flush_dcache_range(start, start + size);
68
+ break;
69
+ case 3:
70
+ printf("invalidate dcache: 0x%08lx - 0x%08lx\n", start, start + size);
71
+ invalidate_dcache_range(start, start + size);
72
+ break;
73
+ }
74
+ break;
5875 case 2: /* on / off */
5976 switch (parse_argv(argv[1])) {
6077 case 0:
....@@ -65,6 +82,9 @@
6582 break;
6683 case 2:
6784 flush_dcache_all();
85
+ break;
86
+ case 3:
87
+ printf("error: dcache invalidate require [start] [size]\n");
6888 break;
6989 }
7090 break;
....@@ -80,7 +100,9 @@
80100
81101 static int parse_argv(const char *s)
82102 {
83
- if (strcmp(s, "flush") == 0)
103
+ if (strcmp(s, "invalidate") == 0)
104
+ return 3;
105
+ else if (strcmp(s, "flush") == 0)
84106 return 2;
85107 else if (strcmp(s, "on") == 0)
86108 return 1;
....@@ -99,8 +121,8 @@
99121 );
100122
101123 U_BOOT_CMD(
102
- dcache, 2, 1, do_dcache,
124
+ dcache, 4, 1, do_dcache,
103125 "enable or disable data cache",
104
- "[on, off, flush]\n"
126
+ "[on, off, flush, invalidate] [start] [size]\n"
105127 " - enable, disable, or flush data (writethrough) cache"
106128 );
u-boot/cmd/ddr_tool/Kconfig
....@@ -0,0 +1,32 @@
1
+menu "DDR Tool"
2
+
3
+config CMD_DDR_TOOL
4
+ bool "Enable DDR Tool"
5
+ help
6
+ This enable ddr tool such as ddr dq eye, ddr test tool, memtester and stressapptest.
7
+
8
+config CMD_DDR_DQ_EYE
9
+ bool "Enable DDR DQ eye fuction"
10
+ depends on CMD_DDR_TOOL
11
+ help
12
+ This enable ddr dq eye fuction.
13
+
14
+config CMD_DDR_TEST
15
+ bool "Enable ddr test tool"
16
+ depends on CMD_DDR_TOOL
17
+ help
18
+ This enable ddr test tool code.
19
+
20
+config CMD_MEMTESTER
21
+ bool "Enable memtester for ddr"
22
+ depends on CMD_DDR_TOOL
23
+ help
24
+ This enables memtester for ddr.
25
+
26
+config CMD_STRESSAPPTEST
27
+ bool "Enable stressapptest for ddr"
28
+ depends on CMD_DDR_TOOL
29
+ help
30
+ This enables stressapptest for ddr.
31
+
32
+endmenu
u-boot/cmd/ddr_tool/Makefile
....@@ -1,25 +1,12 @@
11 #
2
-# (C) Copyright 2018 Rockchip Electronics Co., Ltd.
2
+# (C) Copyright 2023 Rockchip Electronics Co., Ltd.
33 #
44 # SPDX-License-Identifier: GPL-2.0+
55 #
66
7
-# We don't want the bootrom-helper present in a full U-Boot build, as
8
-# this may have entered from ATF with the stack-pointer pointing to
9
-# inaccessible/protected memory (and the bootrom-helper assumes that
10
-# the stack-pointer is valid before switching to the U-Boot stack).
11
-ifdef CONFIG_ROCKCHIP_PX30
12
-obj-$(CONFIG_CMD_DDR_TEST_TOOL) = ddr_test_px30.o
13
-endif
14
-ifdef CONFIG_ROCKCHIP_RK3328
15
-obj-$(CONFIG_CMD_DDR_TEST_TOOL) = ddr_test_rk3328.o
16
-endif
17
-ifdef CONFIG_ROCKCHIP_RK1808
18
-obj-$(CONFIG_CMD_DDR_TEST_TOOL) = ddr_test_rk1808.o
19
-endif
20
-ifndef CONFIG_CMD_MEMTESTER
21
-obj-$(CONFIG_CMD_DDR_TEST_TOOL) += ../memtester/ddr_tester_common.o
22
-obj-$(CONFIG_CMD_DDR_TEST_TOOL) += ../memtester/io_map.o
23
-endif
24
-obj-$(CONFIG_CMD_DDR_TEST_TOOL) += ddr_dq_eye.o
7
+obj-$(CONFIG_CMD_DDR_TOOL) += ddr_tool_common.o ddr_tool_mp.o io_map.o
258
9
+obj-$(CONFIG_CMD_DDR_DQ_EYE) += ddr_dq_eye/
10
+obj-$(CONFIG_CMD_DDR_TEST) += ddr_test/
11
+obj-$(CONFIG_CMD_MEMTESTER) += memtester/
12
+obj-$(CONFIG_CMD_STRESSAPPTEST) += stressapptest/
u-boot/cmd/ddr_tool/ddr_dq_eye/Makefile
....@@ -0,0 +1,7 @@
1
+#
2
+# (C) Copyright 2023 Rockchip Electronics Co., Ltd.
3
+#
4
+# SPDX-License-Identifier: GPL-2.0+
5
+#
6
+
7
+obj-$(CONFIG_CMD_DDR_DQ_EYE) += ddr_dq_eye.o
u-boot/cmd/ddr_tool/ddr_dq_eye.c
similarity index 100%rename from u-boot/cmd/ddr_tool/ddr_dq_eye.crename to u-boot/cmd/ddr_tool/ddr_dq_eye/ddr_dq_eye.c
u-boot/cmd/ddr_tool/ddr_test/Makefile
....@@ -0,0 +1,20 @@
1
+#
2
+# (C) Copyright 2018 Rockchip Electronics Co., Ltd.
3
+#
4
+# SPDX-License-Identifier: GPL-2.0+
5
+#
6
+
7
+# We don't want the bootrom-helper present in a full U-Boot build, as
8
+# this may have entered from ATF with the stack-pointer pointing to
9
+# inaccessible/protected memory (and the bootrom-helper assumes that
10
+# the stack-pointer is valid before switching to the U-Boot stack).
11
+
12
+ifdef CONFIG_ROCKCHIP_PX30
13
+obj-$(CONFIG_CMD_DDR_TEST) = ddr_test_px30.o
14
+endif
15
+ifdef CONFIG_ROCKCHIP_RK1808
16
+obj-$(CONFIG_CMD_DDR_TEST) = ddr_test_rk1808.o
17
+endif
18
+ifdef CONFIG_ROCKCHIP_RK3328
19
+obj-$(CONFIG_CMD_DDR_TEST) = ddr_test_rk3328.o
20
+endif
u-boot/cmd/ddr_tool/ddr_test_px30.S
similarity index 99%rename from u-boot/cmd/ddr_tool/ddr_test_px30.Srename to u-boot/cmd/ddr_tool/ddr_test/ddr_test_px30.S
....@@ -1814,8 +1814,8 @@
18141814 .file 36 "include/log.h"
18151815 .file 37 "include/stdio.h"
18161816 .file 38 "./arch/arm/include/asm/arch/sdram.h"
1817
- .file 39 "cmd/ddr_tool/../memtester/io_map.h"
1818
- .file 40 "cmd/ddr_tool/../memtester/ddr_tester_common.h"
1817
+ .file 39 "cmd/ddr_tool/io_map.h"
1818
+ .file 40 "cmd/ddr_tool/ddr_tool_common.h"
18191819 .file 41 "include/vsprintf.h"
18201820 .section .debug_info,"",@progbits
18211821 .Ldebug_info0:
u-boot/cmd/ddr_tool/ddr_test_rk1808.S
similarity index 99%rename from u-boot/cmd/ddr_tool/ddr_test_rk1808.Srename to u-boot/cmd/ddr_tool/ddr_test/ddr_test_rk1808.S
....@@ -1604,8 +1604,8 @@
16041604 .file 34 "include/log.h"
16051605 .file 35 "include/stdio.h"
16061606 .file 36 "./arch/arm/include/asm/arch/sdram.h"
1607
- .file 37 "cmd/ddr_tool/../memtester/io_map.h"
1608
- .file 38 "cmd/ddr_tool/../memtester/ddr_tester_common.h"
1607
+ .file 37 "cmd/ddr_tool/io_map.h"
1608
+ .file 38 "cmd/ddr_tool/ddr_tool_common.h"
16091609 .file 39 "include/vsprintf.h"
16101610 .section .debug_info,"",@progbits
16111611 .Ldebug_info0:
u-boot/cmd/ddr_tool/ddr_test_px30.S
similarity index 99%copy from u-boot/cmd/ddr_tool/ddr_test_px30.Scopy to u-boot/cmd/ddr_tool/ddr_test/ddr_test_rk3328.S
....@@ -1814,8 +1814,8 @@
18141814 .file 36 "include/log.h"
18151815 .file 37 "include/stdio.h"
18161816 .file 38 "./arch/arm/include/asm/arch/sdram.h"
1817
- .file 39 "cmd/ddr_tool/../memtester/io_map.h"
1818
- .file 40 "cmd/ddr_tool/../memtester/ddr_tester_common.h"
1817
+ .file 39 "cmd/ddr_tool/io_map.h"
1818
+ .file 40 "cmd/ddr_tool/ddr_tool_common.h"
18191819 .file 41 "include/vsprintf.h"
18201820 .section .debug_info,"",@progbits
18211821 .Ldebug_info0:
u-boot/cmd/ddr_tool/ddr_test_rk3328.S
deleted file mode 100644
....@@ -1,9940 +0,0 @@
1
-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
2
-/*
3
- * Copyright (C) 2019 Rockchip Electronics Co., Ltd.
4
- */
5
-
6
- .arch armv8-a+nosimd
7
- .file "ddr_test_code.c"
8
- .text
9
-.Ltext0:
10
- .cfi_sections .debug_frame
11
- .section .text.crosstalk,"ax",@progbits
12
- .align 2
13
- .global crosstalk
14
- .type crosstalk, %function
15
-crosstalk:
16
-.LFB200:
17
- .file 1 "cmd/ddr_tool/crosstalk.c"
18
- .loc 1 46 0
19
- .cfi_startproc
20
-.LVL0:
21
- stp x29, x30, [sp, -144]!
22
- .cfi_def_cfa_offset 144
23
- .cfi_offset 29, -144
24
- .cfi_offset 30, -136
25
- add x29, sp, 0
26
- .cfi_def_cfa_register 29
27
- stp x21, x22, [sp, 32]
28
- .cfi_offset 21, -112
29
- .cfi_offset 22, -104
30
- .loc 1 66 0
31
- adrp x22, .LC2
32
- .loc 1 46 0
33
- stp x23, x24, [sp, 48]
34
- .cfi_offset 23, -96
35
- .cfi_offset 24, -88
36
- mov x23, x0
37
- stp x19, x20, [sp, 16]
38
- mov x24, x1
39
- stp x25, x26, [sp, 64]
40
- .loc 1 63 0
41
- adrp x0, .LC1
42
-.LVL1:
43
- .loc 1 46 0
44
- stp x27, x28, [sp, 80]
45
- .cfi_offset 19, -128
46
- .cfi_offset 20, -120
47
- .cfi_offset 25, -80
48
- .cfi_offset 26, -72
49
- .cfi_offset 27, -64
50
- .cfi_offset 28, -56
51
- .loc 1 63 0
52
- add x0, x0, :lo12:.LC1
53
- bl printf
54
-.LVL2:
55
- .loc 1 71 0
56
- add x21, x29, 112
57
- .loc 1 66 0
58
- add x0, x22, :lo12:.LC2
59
- .loc 1 68 0
60
- adrp x25, .LC3
61
- .loc 1 66 0
62
- str x0, [x29, 104]
63
- .loc 1 64 0
64
- mov w20, 0
65
- .loc 1 68 0
66
- add x0, x25, :lo12:.LC3
67
- str x0, [x29, 96]
68
-.LVL3:
69
-.L6:
70
- .loc 1 66 0
71
- ldr x0, [x29, 104]
72
- .loc 1 71 0
73
- mov w26, 1
74
- .loc 1 66 0
75
- mov w1, w20
76
- .loc 1 71 0
77
- lsl w26, w26, w20
78
- .loc 1 65 0
79
- mov w28, -1
80
- .loc 1 67 0
81
- mov w27, 0
82
- .loc 1 66 0
83
- bl printf
84
-.LVL4:
85
-.L5:
86
- .loc 1 68 0
87
- ldr x0, [x29, 96]
88
- mov w1, w27
89
- .loc 1 69 0
90
- mvn w28, w28
91
-.LVL5:
92
- mov x19, 0
93
- .loc 1 68 0
94
- bl printf
95
-.LVL6:
96
-.L2:
97
- .loc 1 71 0 discriminator 3
98
- eor w0, w26, w28
99
- str w0, [x19, x21]
100
- add x19, x19, 4
101
- .loc 1 72 0 discriminator 3
102
- mvn w28, w28
103
-.LVL7:
104
- .loc 1 70 0 discriminator 3
105
- cmp x19, 32
106
- bne .L2
107
- .loc 1 74 0
108
- mov w1, w19
109
- mov x0, x21
110
- bl data_cpu_2_io
111
-.LVL8:
112
- .loc 1 75 0
113
- mov x3, x24
114
- mov x2, x23
115
- mov w1, w19
116
- mov x0, x21
117
- bl write_buf_to_ddr
118
-.LVL9:
119
- .loc 1 76 0
120
- mov w4, 1
121
- mov x3, x24
122
- mov x2, x23
123
- mov w1, w19
124
- mov x0, x21
125
- bl cmp_buf_data
126
-.LVL10:
127
- cbz x0, .L3
128
-.LVL11:
129
-.L11:
130
- .loc 1 78 0
131
- mov w0, -1
132
-.L1:
133
- .loc 1 111 0
134
- ldp x19, x20, [sp, 16]
135
- ldp x21, x22, [sp, 32]
136
- ldp x23, x24, [sp, 48]
137
-.LVL12:
138
- ldp x25, x26, [sp, 64]
139
- ldp x27, x28, [sp, 80]
140
- ldp x29, x30, [sp], 144
141
- .cfi_remember_state
142
- .cfi_restore 30
143
- .cfi_restore 29
144
- .cfi_restore 27
145
- .cfi_restore 28
146
- .cfi_restore 25
147
- .cfi_restore 26
148
- .cfi_restore 23
149
- .cfi_restore 24
150
- .cfi_restore 21
151
- .cfi_restore 22
152
- .cfi_restore 19
153
- .cfi_restore 20
154
- .cfi_def_cfa 31, 0
155
- ret
156
-.LVL13:
157
-.L3:
158
- .cfi_restore_state
159
- .loc 1 67 0 discriminator 2
160
- add w27, w27, 1
161
-.LVL14:
162
- cmp w27, 2
163
- bne .L5
164
- .loc 1 64 0 discriminator 2
165
- add w20, w20, 1
166
-.LVL15:
167
- cmp w20, 32
168
- bne .L6
169
- .loc 1 85 0
170
- adrp x0, .LC4
171
- add x0, x0, :lo12:.LC4
172
- bl printf
173
-.LVL16:
174
- .loc 1 86 0
175
- mov x0, 128
176
- bl malloc
177
-.LVL17:
178
- mov x21, x0
179
-.LVL18:
180
- .loc 1 87 0
181
- cbnz x0, .L7
182
- .loc 1 88 0
183
- adrp x0, .LC5
184
-.LVL19:
185
- mov x1, 128
186
- add x0, x0, :lo12:.LC5
187
- bl printf
188
-.LVL20:
189
-.L7:
190
- adrp x26, .LANCHOR0
191
- .loc 1 91 0
192
- add x27, x22, :lo12:.LC2
193
-.LVL21:
194
- .loc 1 93 0
195
- add x25, x25, :lo12:.LC3
196
- .loc 1 98 0
197
- add x26, x26, :lo12:.LANCHOR0
198
- .loc 1 69 0
199
- mov w20, 0
200
-.LVL22:
201
-.L14:
202
- .loc 1 92 0
203
- mov w22, 0
204
- .loc 1 96 0
205
- mov w28, 1
206
- .loc 1 91 0
207
- mov w1, w20
208
- mov x0, x27
209
- bl printf
210
-.LVL23:
211
-.L13:
212
- .loc 1 93 0
213
- mov w1, w22
214
- mov x0, x25
215
- bl printf
216
-.LVL24:
217
- .loc 1 96 0
218
- mov x19, 0
219
- lsl w1, w28, w22
220
-.LVL25:
221
-.L10:
222
- ldr w0, [x19, x26]
223
- .loc 1 95 0
224
- cbz w20, .L8
225
- .loc 1 96 0
226
- eor w0, w0, w1
227
-.L8:
228
- .loc 1 98 0
229
- str w0, [x21, x19]
230
- add x19, x19, 4
231
- .loc 1 94 0
232
- cmp x19, 128
233
- bne .L10
234
- .loc 1 100 0
235
- mov w1, w19
236
- mov x0, x21
237
- bl data_cpu_2_io
238
-.LVL26:
239
- .loc 1 101 0
240
- mov x3, x24
241
- mov x2, x23
242
- mov w1, w19
243
- mov x0, x21
244
- bl write_buf_to_ddr
245
-.LVL27:
246
- .loc 1 103 0
247
- mov w4, 1
248
- mov x3, x24
249
- mov x2, x23
250
- mov w1, w19
251
- mov x0, x21
252
- bl cmp_buf_data
253
-.LVL28:
254
- cbnz x0, .L11
255
- .loc 1 106 0
256
- cbz w20, .L12
257
- .loc 1 92 0 discriminator 2
258
- add w22, w22, 1
259
-.LVL29:
260
- cmp w22, 32
261
- bne .L13
262
-.L12:
263
- .loc 1 90 0 discriminator 2
264
- add w20, w20, 1
265
-.LVL30:
266
- cmp w20, 2
267
- bne .L14
268
- .loc 1 110 0
269
- mov w0, 0
270
- b .L1
271
- .cfi_endproc
272
-.LFE200:
273
- .size crosstalk, .-crosstalk
274
- .section .text.set_ddr_freq,"ax",@progbits
275
- .align 2
276
- .weak set_ddr_freq
277
- .type set_ddr_freq, %function
278
-set_ddr_freq:
279
-.LFB253:
280
- .file 2 "cmd/ddr_tool/ddr_tool.c"
281
- .loc 2 45 0
282
- .cfi_startproc
283
-.LVL31:
284
- .loc 2 47 0
285
- mov w0, 0
286
-.LVL32:
287
- ret
288
- .cfi_endproc
289
-.LFE253:
290
- .size set_ddr_freq, .-set_ddr_freq
291
- .section .text.set_vdd_logic,"ax",@progbits
292
- .align 2
293
- .weak set_vdd_logic
294
- .type set_vdd_logic, %function
295
-set_vdd_logic:
296
-.LFB254:
297
- .loc 2 50 0
298
- .cfi_startproc
299
-.LVL33:
300
- .loc 2 52 0
301
- mov w0, -1
302
-.LVL34:
303
- ret
304
- .cfi_endproc
305
-.LFE254:
306
- .size set_vdd_logic, .-set_vdd_logic
307
- .section .text.diagonalscan,"ax",@progbits
308
- .align 2
309
- .global diagonalscan
310
- .type diagonalscan, %function
311
-diagonalscan:
312
-.LFB268:
313
- .file 3 "cmd/ddr_tool/diagonalscan.c"
314
- .loc 3 16 0
315
- .cfi_startproc
316
-.LVL35:
317
- stp x29, x30, [sp, -112]!
318
- .cfi_def_cfa_offset 112
319
- .cfi_offset 29, -112
320
- .cfi_offset 30, -104
321
- .loc 3 19 0
322
- mov x2, 32
323
- .loc 3 16 0
324
- add x29, sp, 0
325
- .cfi_def_cfa_register 29
326
- stp x21, x22, [sp, 32]
327
- .cfi_offset 21, -80
328
- .cfi_offset 22, -72
329
- mov x22, x1
330
- stp x23, x24, [sp, 48]
331
- .cfi_offset 23, -64
332
- .cfi_offset 24, -56
333
- sub x23, x1, #32
334
- .loc 3 19 0
335
- adrp x1, .LANCHOR1
336
-.LVL36:
337
- add x1, x1, :lo12:.LANCHOR1
338
- .loc 3 16 0
339
- stp x19, x20, [sp, 16]
340
- stp x25, x26, [sp, 64]
341
- .cfi_offset 19, -96
342
- .cfi_offset 20, -88
343
- .cfi_offset 25, -48
344
- .cfi_offset 26, -40
345
- .loc 3 16 0
346
- mov x25, x0
347
- .loc 3 19 0
348
- add x0, x29, 80
349
-.LVL37:
350
- bl memcpy
351
-.LVL38:
352
- .loc 3 24 0
353
- adrp x0, .LC6
354
- add x0, x0, :lo12:.LC6
355
- bl printf
356
-.LVL39:
357
- .loc 3 25 0
358
- bl get_page_size
359
-.LVL40:
360
- sxtw x19, w0
361
-.LVL41:
362
- .loc 3 27 0
363
- tbz w19, #31, .L28
364
- .loc 3 28 0
365
- mov w1, w19
366
- adrp x0, .LC7
367
- add x0, x0, :lo12:.LC7
368
- bl printf
369
-.LVL42:
370
- .loc 3 29 0
371
- mov w0, -1
372
-.L31:
373
-.LVL43:
374
-.L27:
375
- .loc 3 64 0
376
- ldp x19, x20, [sp, 16]
377
-.LVL44:
378
- ldp x21, x22, [sp, 32]
379
- ldp x23, x24, [sp, 48]
380
- ldp x25, x26, [sp, 64]
381
-.LVL45:
382
- ldp x29, x30, [sp], 112
383
- .cfi_remember_state
384
- .cfi_restore 30
385
- .cfi_restore 29
386
- .cfi_restore 25
387
- .cfi_restore 26
388
- .cfi_restore 23
389
- .cfi_restore 24
390
- .cfi_restore 21
391
- .cfi_restore 22
392
- .cfi_restore 19
393
- .cfi_restore 20
394
- .cfi_def_cfa 31, 0
395
- ret
396
-.LVL46:
397
-.L28:
398
- .cfi_restore_state
399
- .loc 3 40 0
400
- lsr x22, x22, 1
401
-.LVL47:
402
- add x23, x25, x23
403
-.LVL48:
404
- mov w21, 0
405
- mov x20, 0
406
- .loc 3 37 0
407
- mov w1, 32
408
- add x0, x29, 80
409
- bl data_cpu_2_io
410
-.LVL49:
411
- .loc 3 39 0
412
- mov x2, 32
413
- add x1, x29, 80
414
- mov x0, x25
415
- bl memcpy
416
-.LVL50:
417
-.L30:
418
- .loc 3 40 0 discriminator 1
419
- cmp x20, x22
420
- bcc .L34
421
- mov x0, 0
422
-.LVL51:
423
- .loc 3 63 0
424
- b .L27
425
-.LVL52:
426
-.L34:
427
- .loc 3 41 0
428
- uxtw x24, w21
429
- mov x2, 32
430
- sub x26, x23, x24
431
- add x1, x29, 80
432
- mov x0, x26
433
- bl memcpy
434
-.LVL53:
435
- .loc 3 44 0
436
- add x2, x20, x25
437
- .loc 3 43 0
438
- mov x3, 32
439
- mov w4, 1
440
- add x2, x2, x24
441
- mov w1, w3
442
- add x0, x29, 80
443
- bl cmp_buf_data
444
-.LVL54:
445
- .loc 3 45 0
446
- cbnz x0, .L27
447
- .loc 3 48 0
448
- add x24, x24, 40
449
- add x20, x20, x19
450
-.LVL55:
451
- cmp x19, x24
452
- add w21, w21, 8
453
-.LVL56:
454
- csel w21, w21, wzr, cs
455
-.LVL57:
456
- .loc 3 50 0
457
- cmp x22, x20
458
- bls .L33
459
- .loc 3 51 0
460
- add x0, x25, x20
461
-.LVL58:
462
- mov x2, 32
463
- add x1, x29, 80
464
- add x0, x0, x21, uxtw
465
- bl memcpy
466
-.LVL59:
467
-.L33:
468
- .loc 3 53 0
469
- mov x3, 32
470
- mov w4, 1
471
- mov x2, x26
472
- mov w1, w3
473
- add x0, x29, 80
474
- sub x23, x23, x19
475
- bl cmp_buf_data
476
-.LVL60:
477
- .loc 3 56 0
478
- cbz x0, .L30
479
- b .L27
480
- .cfi_endproc
481
-.LFE268:
482
- .size diagonalscan, .-diagonalscan
483
- .section .text.random_test,"ax",@progbits
484
- .align 2
485
- .global random_test
486
- .type random_test, %function
487
-random_test:
488
-.LFB271:
489
- .file 4 "cmd/ddr_tool/random_test.c"
490
- .loc 4 97 0
491
- .cfi_startproc
492
-.LVL61:
493
- stp x29, x30, [sp, -112]!
494
- .cfi_def_cfa_offset 112
495
- .cfi_offset 29, -112
496
- .cfi_offset 30, -104
497
-.LBB6:
498
-.LBB7:
499
- .loc 4 19 0
500
- mov x2, x1
501
-.LBE7:
502
-.LBE6:
503
- .loc 4 97 0
504
- add x29, sp, 0
505
- .cfi_def_cfa_register 29
506
- stp x19, x20, [sp, 16]
507
- .cfi_offset 19, -96
508
- .cfi_offset 20, -88
509
- mov x20, x1
510
- stp x21, x22, [sp, 32]
511
- mov x19, x0
512
-.LVL62:
513
- stp x23, x24, [sp, 48]
514
-.LBB12:
515
-.LBB8:
516
- .loc 4 19 0
517
- mov w1, -2139062144
518
-.LVL63:
519
-.LBE8:
520
-.LBE12:
521
- .loc 4 97 0
522
- stp x27, x28, [sp, 80]
523
- .cfi_offset 21, -80
524
- .cfi_offset 22, -72
525
- .cfi_offset 23, -64
526
- .cfi_offset 24, -56
527
- .cfi_offset 27, -32
528
- .cfi_offset 28, -24
529
-.LBB13:
530
-.LBB9:
531
- .loc 4 24 0
532
- adrp x24, .LC8
533
-.LBE9:
534
-.LBE13:
535
- .loc 4 97 0
536
- stp x25, x26, [sp, 64]
537
- .cfi_offset 25, -48
538
- .cfi_offset 26, -40
539
-.LBB14:
540
-.LBB10:
541
- .loc 4 19 0
542
- bl memset
543
-.LVL64:
544
- .loc 4 25 0
545
- lsr x0, x20, 2
546
- .loc 4 24 0
547
- add x24, x24, :lo12:.LC8
548
- .loc 4 25 0
549
- str x0, [x29, 104]
550
- .loc 4 15 0
551
- mov w27, 0
552
- .loc 4 41 0
553
- adrp x0, .LC9
554
- .loc 4 21 0
555
- mov w23, 1077952576
556
- .loc 4 41 0
557
- add x0, x0, :lo12:.LC9
558
- .loc 4 20 0
559
- mov w21, -2139062144
560
- .loc 4 23 0
561
- mov w22, 0
562
- .loc 4 41 0
563
- str x0, [x29, 96]
564
-.LVL65:
565
-.L43:
566
- .loc 4 24 0
567
- mov w1, w22
568
- mov x0, x24
569
- bl printf
570
-.LVL66:
571
- .loc 4 25 0
572
- mov w1, 0
573
-.LVL67:
574
-.L38:
575
- ldr x2, [x29, 104]
576
- uxtw x0, w1
577
- cmp x0, x2
578
- bcc .L42
579
-.LVL68:
580
-.L41:
581
- .loc 4 41 0
582
- ldr x0, [x29, 96]
583
- .loc 4 23 0
584
- add w22, w22, 1
585
-.LVL69:
586
- .loc 4 39 0
587
- lsr w23, w23, 1
588
-.LVL70:
589
- .loc 4 40 0
590
- lsr w21, w21, 1
591
-.LVL71:
592
- .loc 4 41 0
593
- bl printf
594
-.LVL72:
595
- .loc 4 23 0
596
- cmp w22, 8
597
- bne .L43
598
- mov x28, -1
599
- b .L40
600
-.LVL73:
601
-.L42:
602
- .loc 4 26 0
603
- lsl x0, x0, 2
604
- add x5, x19, x0
605
- ldr w26, [x19, x0]
606
- .loc 4 27 0
607
- cmp w26, w21
608
- beq .L39
609
- .loc 4 28 0
610
- mov x28, x5
611
-.LVL74:
612
- .loc 4 29 0
613
- add x1, x5, 4
614
-.LVL75:
615
- mov x0, x5
616
- bl flush_dcache_range
617
-.LVL76:
618
- .loc 4 37 0
619
- cmn x28, #1
620
- .loc 4 32 0
621
- ldr w27, [x28]
622
- .loc 4 37 0
623
- beq .L41
624
-.LVL77:
625
-.L40:
626
- .loc 4 43 0
627
- adrp x0, .LC10
628
- add x0, x0, :lo12:.LC10
629
- bl printf
630
-.LVL78:
631
- .loc 4 44 0
632
- cmn x28, #1
633
- beq .L44
634
- .loc 4 45 0
635
- adrp x0, .LC11
636
- mov w4, w21
637
- mov w3, w27
638
- mov w2, w26
639
- mov x1, x28
640
- add x0, x0, :lo12:.LC11
641
- bl printf
642
-.LVL79:
643
-.L57:
644
-.LBE10:
645
-.LBE14:
646
-.LBB15:
647
-.LBB16:
648
- .loc 4 91 0
649
- mov w0, -1
650
-.L37:
651
-.LBE16:
652
-.LBE15:
653
- .loc 4 105 0
654
- ldp x19, x20, [sp, 16]
655
-.LVL80:
656
- ldp x21, x22, [sp, 32]
657
- ldp x23, x24, [sp, 48]
658
- ldp x25, x26, [sp, 64]
659
- ldp x27, x28, [sp, 80]
660
- ldp x29, x30, [sp], 112
661
- .cfi_remember_state
662
- .cfi_restore 30
663
- .cfi_restore 29
664
- .cfi_restore 27
665
- .cfi_restore 28
666
- .cfi_restore 25
667
- .cfi_restore 26
668
- .cfi_restore 23
669
- .cfi_restore 24
670
- .cfi_restore 21
671
- .cfi_restore 22
672
- .cfi_restore 19
673
- .cfi_restore 20
674
- .cfi_def_cfa 31, 0
675
- ret
676
-.LVL81:
677
-.L39:
678
- .cfi_restore_state
679
-.LBB18:
680
-.LBB11:
681
- .loc 4 35 0
682
- str w23, [x19, x0]
683
- .loc 4 25 0
684
- add w1, w1, 1
685
-.LVL82:
686
- b .L38
687
-.LVL83:
688
-.L44:
689
-.LBE11:
690
-.LBE18:
691
-.LBB19:
692
-.LBB17:
693
- .loc 4 64 0
694
- adrp x26, .LC12
695
- .loc 4 84 0
696
- adrp x24, .LC13
697
- .loc 4 72 0
698
- lsr x28, x20, 3
699
- .loc 4 64 0
700
- add x26, x26, :lo12:.LC12
701
- .loc 4 84 0
702
- add x24, x24, :lo12:.LC13
703
- .loc 4 72 0
704
- mov x27, 0
705
- mov x21, 0
706
-.LVL84:
707
-.L51:
708
- .loc 4 64 0
709
- mov x1, x21
710
- mov x0, x26
711
- bl printf
712
-.LVL85:
713
- .loc 4 66 0
714
- lsl x22, x21, 24
715
- lsl x0, x21, 8
716
- orr x22, x22, x21, lsl 32
717
- orr x0, x0, x21, lsl 16
718
- .loc 4 70 0
719
- mov x2, x20
720
- .loc 4 66 0
721
- orr x22, x22, x0
722
- lsl x0, x21, 40
723
- orr x0, x0, x21, lsl 48
724
- orr x22, x22, x0
725
- orr x0, x21, x21, lsl 56
726
- orr x22, x22, x0
727
-.LVL86:
728
- .loc 4 70 0
729
- mov x0, x19
730
- mov w1, w22
731
- bl memset
732
-.LVL87:
733
- .loc 4 72 0
734
- mov x0, 0
735
-.LVL88:
736
-.L46:
737
- cmp x0, x28
738
- bne .L50
739
-.LVL89:
740
-.L49:
741
- .loc 4 84 0
742
- mov x0, x24
743
- .loc 4 63 0
744
- add x21, x21, 1
745
-.LVL90:
746
- .loc 4 84 0
747
- bl printf
748
-.LVL91:
749
- .loc 4 63 0
750
- cmp x21, 256
751
- bne .L51
752
- mov x23, -1
753
- b .L48
754
-.LVL92:
755
-.L50:
756
- lsl x1, x0, 3
757
- add x23, x1, x19
758
- .loc 4 73 0
759
- ldr x25, [x1, x19]
760
-.LVL93:
761
- .loc 4 74 0
762
- cmp x22, x25
763
- beq .L47
764
-.LVL94:
765
- .loc 4 76 0
766
- add x1, x23, 4
767
- mov x0, x23
768
-.LVL95:
769
- bl flush_dcache_range
770
-.LVL96:
771
- .loc 4 78 0
772
- ldr x27, [x23]
773
-.LVL97:
774
- .loc 4 82 0
775
- cmn x23, #1
776
- beq .L49
777
-.LVL98:
778
-.L48:
779
- .loc 4 86 0
780
- adrp x0, .LC14
781
- add x0, x0, :lo12:.LC14
782
- bl printf
783
-.LVL99:
784
- .loc 4 93 0
785
- mov w0, 0
786
- .loc 4 87 0
787
- cmn x23, #1
788
- beq .L37
789
- .loc 4 88 0
790
- mov x4, x22
791
- mov x3, x27
792
- mov x2, x25
793
- mov x1, x23
794
- adrp x0, .LC15
795
- add x0, x0, :lo12:.LC15
796
- bl printf
797
-.LVL100:
798
- b .L57
799
-.LVL101:
800
-.L47:
801
- .loc 4 72 0
802
- add x0, x0, 1
803
-.LVL102:
804
- b .L46
805
-.LBE17:
806
-.LBE19:
807
- .cfi_endproc
808
-.LFE271:
809
- .size random_test, .-random_test
810
- .section .text.scan_freq,"ax",@progbits
811
- .align 2
812
- .type scan_freq, %function
813
-scan_freq:
814
-.LFB255:
815
- .loc 2 55 0
816
- .cfi_startproc
817
-.LVL103:
818
- stp x29, x30, [sp, -80]!
819
- .cfi_def_cfa_offset 80
820
- .cfi_offset 29, -80
821
- .cfi_offset 30, -72
822
- add x29, sp, 0
823
- .cfi_def_cfa_register 29
824
- stp x19, x20, [sp, 16]
825
- .cfi_offset 19, -64
826
- .cfi_offset 20, -56
827
- mov w19, w0
828
- stp x21, x22, [sp, 32]
829
- .loc 2 61 0
830
- mov w0, 16960
831
-.LVL104:
832
- .loc 2 55 0
833
- stp x23, x24, [sp, 48]
834
- .loc 2 61 0
835
- movk w0, 0xf, lsl 16
836
- .loc 2 55 0
837
- stp x25, x26, [sp, 64]
838
- .cfi_offset 21, -48
839
- .cfi_offset 22, -40
840
- .cfi_offset 23, -32
841
- .cfi_offset 24, -24
842
- .cfi_offset 25, -16
843
- .cfi_offset 26, -8
844
- .loc 2 55 0
845
- mov x22, x2
846
- .loc 2 61 0
847
- cmp w19, w0
848
- bls .L59
849
- .loc 2 62 0
850
- udiv w19, w19, w0
851
-.LVL105:
852
-.L59:
853
- .loc 2 63 0
854
- cmp w1, w0
855
- bls .L60
856
- .loc 2 64 0
857
- udiv w1, w1, w0
858
-.LVL106:
859
-.L60:
860
- .loc 2 66 0
861
- cmp w19, w1
862
- bls .L61
863
- mov w0, w19
864
- mov w19, w1
865
-.LVL107:
866
- mov w1, w0
867
-.LVL108:
868
-.L61:
869
- .loc 2 75 0
870
- mov w25, 16960
871
- adrp x24, .LC16
872
- .loc 2 71 0
873
- sub w21, w1, w19
874
-.LVL109:
875
- .loc 2 75 0
876
- add x24, x24, :lo12:.LC16
877
- .loc 2 73 0
878
- mov w23, 0
879
- .loc 2 75 0
880
- movk w25, 0xf, lsl 16
881
-.LVL110:
882
-.L62:
883
- .loc 2 73 0 discriminator 1
884
- cmp x22, x23, uxtw
885
- bhi .L66
886
- .loc 2 73 0 is_stmt 0 discriminator 3
887
- cbnz x22, .L67
888
-.L66:
889
- .loc 2 74 0 is_stmt 1
890
- bl rand
891
-.LVL111:
892
- udiv w20, w0, w21
893
- .loc 2 75 0
894
- mov w1, w23
895
- .loc 2 74 0
896
- msub w20, w20, w21, w0
897
- .loc 2 75 0
898
- mov x0, x24
899
-.LVL112:
900
- .loc 2 74 0
901
- add w20, w20, w19
902
- .loc 2 75 0
903
- mul w20, w20, w25
904
- mov w2, w20
905
- bl printf
906
-.LVL113:
907
- .loc 2 76 0
908
- and x0, x20, 4294967232
909
- bl set_ddr_freq
910
-.LVL114:
911
- mov w26, w0
912
-.LVL115:
913
- .loc 2 79 0
914
- ldr x0, [x18]
915
-.LVL116:
916
- mov x1, 1048576
917
- ldr x0, [x0, 136]
918
- bl random_test
919
-.LVL117:
920
- mov w20, w0
921
-.LVL118:
922
- .loc 2 80 0
923
- cbz w0, .L63
924
- .loc 2 81 0
925
- adrp x0, .LC17
926
-.LVL119:
927
- mov w1, w26
928
- add x0, x0, :lo12:.LC17
929
- bl printf
930
-.LVL120:
931
-.L58:
932
- .loc 2 91 0
933
- mov w0, w20
934
- ldp x19, x20, [sp, 16]
935
-.LVL121:
936
- ldp x21, x22, [sp, 32]
937
-.LVL122:
938
- ldp x23, x24, [sp, 48]
939
-.LVL123:
940
- ldp x25, x26, [sp, 64]
941
- ldp x29, x30, [sp], 80
942
- .cfi_remember_state
943
- .cfi_restore 30
944
- .cfi_restore 29
945
- .cfi_restore 25
946
- .cfi_restore 26
947
- .cfi_restore 23
948
- .cfi_restore 24
949
- .cfi_restore 21
950
- .cfi_restore 22
951
- .cfi_restore 19
952
- .cfi_restore 20
953
- .cfi_def_cfa 31, 0
954
- ret
955
-.LVL124:
956
-.L63:
957
- .cfi_restore_state
958
- .loc 2 84 0
959
- bl ctrlc
960
-.LVL125:
961
- cbz w0, .L65
962
-.LVL126:
963
-.L67:
964
- .loc 2 73 0
965
- mov w20, 0
966
- b .L58
967
-.LVL127:
968
-.L65:
969
- .loc 2 73 0 is_stmt 0 discriminator 2
970
- add w23, w23, 1
971
-.LVL128:
972
- b .L62
973
- .cfi_endproc
974
-.LFE255:
975
- .size scan_freq, .-scan_freq
976
- .section .text.do_ddr_test,"ax",@progbits
977
- .align 2
978
- .type do_ddr_test, %function
979
-do_ddr_test:
980
-.LFB256:
981
- .loc 2 100 0 is_stmt 1
982
- .cfi_startproc
983
-.LVL129:
984
- stp x29, x30, [sp, -224]!
985
- .cfi_def_cfa_offset 224
986
- .cfi_offset 29, -224
987
- .cfi_offset 30, -216
988
- .loc 2 113 0
989
- adrp x0, .LC18
990
-.LVL130:
991
- add x0, x0, :lo12:.LC18
992
- .loc 2 100 0
993
- add x29, sp, 0
994
- .cfi_def_cfa_register 29
995
- stp x19, x20, [sp, 16]
996
- .cfi_offset 19, -208
997
- .cfi_offset 20, -200
998
- .loc 2 115 0
999
- add x20, x29, 152
1000
- .loc 2 100 0
1001
- stp x21, x22, [sp, 32]
1002
- .cfi_offset 21, -192
1003
- .cfi_offset 22, -184
1004
- .loc 2 115 0
1005
- add x21, x29, 120
1006
- .loc 2 100 0
1007
- stp x23, x24, [sp, 48]
1008
- .cfi_offset 23, -176
1009
- .cfi_offset 24, -168
1010
- mov w23, w2
1011
- stp x25, x26, [sp, 64]
1012
- .cfi_offset 25, -160
1013
- .cfi_offset 26, -152
1014
- mov x26, x3
1015
- stp x27, x28, [sp, 80]
1016
- .cfi_offset 27, -144
1017
- .cfi_offset 28, -136
1018
- .loc 2 103 0
1019
- stp xzr, xzr, [x29, 184]
1020
- stp xzr, xzr, [x29, 200]
1021
- str xzr, [x29, 216]
1022
-.LVL131:
1023
- .loc 2 113 0
1024
- bl printf
1025
-.LVL132:
1026
- .loc 2 115 0
1027
- mov w2, 1
1028
- mov x1, x20
1029
- mov x0, x21
1030
- bl get_print_available_addr
1031
-.LVL133:
1032
- .loc 2 117 0
1033
- cmp w23, 1
1034
- ble .L160
1035
- .loc 2 121 0
1036
- adrp x24, .LANCHOR2
1037
- add x27, x24, :lo12:.LANCHOR2
1038
- mov x25, 0
1039
- str x24, [x29, 104]
1040
-.L75:
1041
- ldr x1, [x27, x25, lsl 3]
1042
- mov w19, w25
1043
-.LVL134:
1044
- ldr x0, [x26, 8]
1045
- bl strcasecmp
1046
-.LVL135:
1047
- cbz w0, .L74
1048
-.LVL136:
1049
- add x25, x25, 1
1050
- .loc 2 120 0 discriminator 2
1051
- cmp x25, 7
1052
- bne .L75
1053
- .loc 2 128 0
1054
- adrp x0, .LC27
1055
- add x0, x0, :lo12:.LC27
1056
- b .L161
1057
-.LVL137:
1058
-.L112:
1059
- .loc 2 133 0
1060
- adrp x0, .LC19
1061
- add x0, x0, :lo12:.LC19
1062
-.LVL138:
1063
-.L161:
1064
- .loc 2 128 0
1065
- bl printf
1066
-.LVL139:
1067
-.L160:
1068
- .loc 2 129 0
1069
- mov w23, -1
1070
- b .L72
1071
-.LVL140:
1072
-.L78:
1073
- .loc 2 138 0
1074
- add x0, x26, x27
1075
- add x1, x29, 184
1076
- add x2, x1, x27
1077
- mov w1, 0
1078
- add x27, x27, 8
1079
- ldr x0, [x0, 16]
1080
- bl strict_strtoul
1081
-.LVL141:
1082
- tbz w0, #31, .L77
1083
- .loc 2 139 0
1084
- adrp x0, .LC20
1085
- add x0, x0, :lo12:.LC20
1086
- b .L161
1087
-.LVL142:
1088
-.L79:
1089
- .loc 2 157 0
1090
- bl data_cpu_2_io_init
1091
-.LVL143:
1092
- .loc 2 159 0
1093
- cbnz w19, .L80
1094
- .loc 2 161 0
1095
- ldr x0, [x29, 192]
1096
- cbz x0, .L81
1097
- .loc 2 162 0
1098
- bl set_vdd_logic
1099
-.LVL144:
1100
-.L81:
1101
- .loc 2 163 0
1102
- ldr x0, [x29, 184]
1103
- bl set_ddr_freq
1104
-.LVL145:
1105
-.L82:
1106
- .loc 2 305 0
1107
- adrp x0, .LC26
1108
- add x0, x0, :lo12:.LC26
1109
- bl printf
1110
-.LVL146:
1111
- b .L72
1112
-.LVL147:
1113
-.L80:
1114
- .loc 2 164 0
1115
- cmp w19, 1
1116
- bne .L83
1117
- .loc 2 166 0
1118
- ldr x0, [x29, 208]
1119
- cbz x0, .L84
1120
- .loc 2 167 0
1121
- bl set_vdd_logic
1122
-.LVL148:
1123
-.L84:
1124
- .loc 2 168 0
1125
- ldr w0, [x29, 184]
1126
- ldr w1, [x29, 192]
1127
- ldr x2, [x29, 200]
1128
- bl scan_freq
1129
-.LVL149:
1130
- b .L82
1131
-.L83:
1132
- .loc 2 169 0
1133
- sub w25, w25, #5
1134
- cmp w25, 1
1135
- bhi .L85
1136
- .loc 2 171 0
1137
- ldr x0, [x29, 208]
1138
- cbz x0, .L86
1139
- .loc 2 172 0
1140
- bl set_vdd_logic
1141
-.LVL150:
1142
-.L86:
1143
- .loc 2 173 0
1144
- cmp w19, 5
1145
- bne .L114
1146
- .loc 2 175 0
1147
- mov x1, 65535
1148
- mov x0, 0
1149
- movk x1, 0x9f, lsl 16
1150
-.L90:
1151
-.LVL151:
1152
- ldr x2, [x20, x0, lsl 3]
1153
- cmp x2, x1
1154
- bls .L88
1155
- .loc 2 176 0
1156
- mov w1, w0
1157
-.LVL152:
1158
- .loc 2 185 0
1159
- mov x2, 10485760
1160
- str x2, [x20, w0, uxtw 3]
1161
-.LVL153:
1162
-.L89:
1163
- .loc 2 108 0 discriminator 1
1164
- mov x0, 0
1165
-.LVL154:
1166
-.L93:
1167
- .loc 2 188 0
1168
- cmp w1, w0
1169
- beq .L92
1170
- .loc 2 190 0
1171
- str xzr, [x21, x0, lsl 3]
1172
- .loc 2 191 0
1173
- str xzr, [x20, x0, lsl 3]
1174
-.L92:
1175
-.LVL155:
1176
- add x0, x0, 1
1177
-.LVL156:
1178
- .loc 2 187 0 discriminator 2
1179
- cmp x0, 4
1180
- bne .L93
1181
- .loc 2 193 0
1182
- mov w28, 60
1183
-.L87:
1184
-.LVL157:
1185
- .loc 2 201 0
1186
- adrp x26, .LC22
1187
-.LVL158:
1188
- .loc 2 205 0
1189
- adrp x27, .LC23
1190
- .loc 2 201 0
1191
- add x26, x26, :lo12:.LC22
1192
- .loc 2 205 0
1193
- add x27, x27, :lo12:.LC23
1194
- .loc 2 198 0
1195
- mov w25, 0
1196
-.LVL159:
1197
-.L94:
1198
- .loc 2 199 0
1199
- ldr x0, [x29, 200]
1200
- cbz x0, .L100
1201
- .loc 2 199 0 is_stmt 0 discriminator 1
1202
- cmp x0, x25, uxtw
1203
- bls .L82
1204
-.L100:
1205
- .loc 2 201 0 is_stmt 1
1206
- mov x19, 0
1207
- .loc 2 200 0
1208
- add w25, w25, 1
1209
-.LVL160:
1210
- .loc 2 201 0
1211
- mov w1, w25
1212
- mov x0, x26
1213
- bl printf
1214
-.LVL161:
1215
-.L98:
1216
- .loc 2 203 0
1217
- ldr x3, [x20, x19, lsl 3]
1218
- cbz x3, .L95
1219
- .loc 2 205 0
1220
- ldr x2, [x21, x19, lsl 3]
1221
- mov w1, w19
1222
- mov x0, x27
1223
- bl printf
1224
-.LVL162:
1225
- .loc 2 207 0
1226
- ldr x0, [x29, 192]
1227
- bl set_ddr_freq
1228
-.LVL163:
1229
- .loc 2 208 0
1230
- ldr x1, [x20, x19, lsl 3]
1231
- ldr x0, [x21, x19, lsl 3]
1232
- bl random_test
1233
-.LVL164:
1234
- mov w24, w0
1235
-.LVL165:
1236
- .loc 2 210 0
1237
- cbnz w0, .L115
1238
- .loc 2 211 0
1239
- ldr x1, [x20, x19, lsl 3]
1240
- ldr x0, [x21, x19, lsl 3]
1241
-.LVL166:
1242
- bl crosstalk
1243
-.LVL167:
1244
- mov w24, w0
1245
-.LVL168:
1246
- .loc 2 215 0
1247
- cbnz w0, .L116
1248
- .loc 2 216 0
1249
- ldr x1, [x20, x19, lsl 3]
1250
- ldr x0, [x21, x19, lsl 3]
1251
-.LVL169:
1252
- bl diagonalscan
1253
-.LVL170:
1254
- mov w24, w0
1255
-.LVL171:
1256
- .loc 2 220 0
1257
- cbnz w0, .L117
1258
- .loc 2 221 0
1259
- ldr w0, [x29, 184]
1260
-.LVL172:
1261
- and x2, x28, 1020
1262
- ldr w1, [x29, 192]
1263
- .loc 2 224 0
1264
- mov w22, 1
1265
- .loc 2 221 0
1266
- bl scan_freq
1267
-.LVL173:
1268
- mov w24, w0
1269
-.LVL174:
1270
-.L96:
1271
- .loc 2 226 0
1272
- ldr x0, [x29, 184]
1273
-.LVL175:
1274
- bl set_ddr_freq
1275
-.LVL176:
1276
- .loc 2 227 0
1277
- cbnz w24, .L118
1278
- .loc 2 228 0
1279
- ldr x1, [x20, x19, lsl 3]
1280
- ldr x0, [x21, x19, lsl 3]
1281
- bl random_test
1282
-.LVL177:
1283
- mov w2, w0
1284
-.LVL178:
1285
- .loc 2 232 0
1286
- cbnz w0, .L119
1287
- .loc 2 233 0
1288
- ldr x1, [x20, x19, lsl 3]
1289
- ldr x0, [x21, x19, lsl 3]
1290
-.LVL179:
1291
- str w2, [x29, 100]
1292
- bl crosstalk
1293
-.LVL180:
1294
- mov w22, w0
1295
-.LVL181:
1296
- .loc 2 237 0
1297
- ldr w2, [x29, 100]
1298
- cbnz w0, .L120
1299
- .loc 2 238 0
1300
- ldr x1, [x20, x19, lsl 3]
1301
- ldr x0, [x21, x19, lsl 3]
1302
-.LVL182:
1303
- bl diagonalscan
1304
-.LVL183:
1305
- mov w24, w0
1306
-.LVL184:
1307
- .loc 2 243 0
1308
- cbnz w0, .L121
1309
- .loc 2 245 0
1310
- bl ctrlc
1311
-.LVL185:
1312
- cbnz w0, .L122
1313
- .loc 2 240 0
1314
- mov w22, 4
1315
-.LVL186:
1316
-.L95:
1317
- add x19, x19, 1
1318
-.LVL187:
1319
- .loc 2 202 0 discriminator 2
1320
- cmp x19, 4
1321
- bne .L98
1322
- mov w2, 0
1323
- mov w24, 0
1324
-.LVL188:
1325
-.L97:
1326
- .loc 2 250 0
1327
- orr w2, w24, w2
1328
-.LVL189:
1329
- cbz w2, .L94
1330
-.LVL190:
1331
-.L99:
1332
- .loc 2 302 0
1333
- cbz w24, .L82
1334
- .loc 2 303 0
1335
- ldr x0, [x29, 104]
1336
- add x24, x0, :lo12:.LANCHOR2
1337
-.LVL191:
1338
- adrp x0, .LC25
1339
- add x0, x0, :lo12:.LC25
1340
- ldr x1, [x24, w22, sxtw 3]
1341
- bl printf
1342
-.LVL192:
1343
- b .L72
1344
-.LVL193:
1345
-.L88:
1346
- add x0, x0, 1
1347
-.LVL194:
1348
- .loc 2 174 0 discriminator 2
1349
- cmp x0, 4
1350
- bne .L90
1351
- .loc 2 181 0
1352
- ldr x2, [x29, 152]
1353
- mov w1, 10
1354
- adrp x0, .LC28
1355
- add x0, x0, :lo12:.LC28
1356
- lsr x2, x2, 20
1357
- bl printf
1358
-.LVL195:
1359
- .loc 2 108 0
1360
- mov w1, 0
1361
- b .L89
1362
-.L114:
1363
- .loc 2 195 0
1364
- mov w28, 1000
1365
- b .L87
1366
-.LVL196:
1367
-.L115:
1368
- .loc 2 209 0
1369
- mov w22, 2
1370
- b .L96
1371
-.LVL197:
1372
-.L116:
1373
- .loc 2 213 0
1374
- mov w22, 3
1375
- b .L96
1376
-.LVL198:
1377
-.L117:
1378
- .loc 2 218 0
1379
- mov w22, 4
1380
- b .L96
1381
-.LVL199:
1382
-.L118:
1383
- mov w2, 0
1384
- b .L97
1385
-.LVL200:
1386
-.L119:
1387
- .loc 2 228 0
1388
- mov w24, w0
1389
- mov w2, 0
1390
- .loc 2 230 0
1391
- mov w22, 2
1392
- b .L97
1393
-.LVL201:
1394
-.L120:
1395
- .loc 2 233 0
1396
- mov w24, w0
1397
- .loc 2 235 0
1398
- mov w22, 3
1399
- b .L97
1400
-.LVL202:
1401
-.L121:
1402
- mov w2, w22
1403
-.LVL203:
1404
-.L158:
1405
- .loc 2 240 0
1406
- mov w22, 4
1407
- b .L97
1408
-.L122:
1409
- .loc 2 246 0
1410
- mov w2, -1
1411
- b .L158
1412
-.LVL204:
1413
-.L85:
1414
- .loc 2 259 0
1415
- mov x2, x20
1416
- mov x1, x21
1417
- add x0, x29, 200
1418
- bl judge_test_addr
1419
-.LVL205:
1420
- mov w27, w0
1421
-.LVL206:
1422
- .loc 2 260 0
1423
- cbz w0, .L123
1424
- .loc 2 263 0
1425
- ldr x0, [x29, 184]
1426
-.LVL207:
1427
- bl set_ddr_freq
1428
-.LVL208:
1429
- .loc 2 265 0
1430
- ldr x0, [x29, 216]
1431
- cbz x0, .L102
1432
- .loc 2 266 0
1433
- bl set_vdd_logic
1434
-.LVL209:
1435
-.L102:
1436
- .loc 2 270 0
1437
- adrp x26, .LC24
1438
-.LVL210:
1439
- mov w25, 0
1440
- add x26, x26, :lo12:.LC24
1441
- b .L110
1442
-.LVL211:
1443
-.L111:
1444
- .loc 2 271 0
1445
- mov x28, 0
1446
- .loc 2 269 0
1447
- add w25, w25, 1
1448
-.LVL212:
1449
- .loc 2 270 0
1450
- mov w1, w25
1451
- mov x0, x26
1452
- bl printf
1453
-.LVL213:
1454
-.L103:
1455
- .loc 2 271 0 discriminator 1
1456
- cmp w27, w28
1457
- bhi .L109
1458
- mov w0, 0
1459
- mov w24, 0
1460
-.LVL214:
1461
-.L108:
1462
- .loc 2 297 0
1463
- orr w0, w24, w0
1464
-.LVL215:
1465
- cbnz w0, .L99
1466
-.LVL216:
1467
-.L110:
1468
- .loc 2 268 0
1469
- ldr x0, [x29, 192]
1470
- cbz x0, .L111
1471
- .loc 2 268 0 is_stmt 0 discriminator 1
1472
- cmp x0, x25, uxtw
1473
- bhi .L111
1474
- b .L82
1475
-.LVL217:
1476
-.L109:
1477
- .loc 2 278 0 is_stmt 1
1478
- ldr x1, [x20, x28, lsl 3]
1479
- .loc 2 272 0
1480
- cmp w19, 3
1481
- .loc 2 278 0
1482
- ldr x0, [x21, x28, lsl 3]
1483
- .loc 2 272 0
1484
- beq .L105
1485
- cmp w19, 4
1486
- beq .L106
1487
- .loc 2 274 0
1488
- bl random_test
1489
-.LVL218:
1490
-.L159:
1491
- .loc 2 282 0
1492
- mov w24, w0
1493
-.LVL219:
1494
- .loc 2 290 0
1495
- bl ctrlc
1496
-.LVL220:
1497
- cbnz w0, .L124
1498
- add x28, x28, 1
1499
-.LVL221:
1500
- mov w22, w19
1501
- .loc 2 294 0
1502
- cbz w24, .L103
1503
- mov w22, w19
1504
- b .L108
1505
-.LVL222:
1506
-.L105:
1507
- .loc 2 278 0
1508
- bl crosstalk
1509
-.LVL223:
1510
- b .L159
1511
-.L106:
1512
- .loc 2 282 0
1513
- bl diagonalscan
1514
-.LVL224:
1515
- b .L159
1516
-.LVL225:
1517
-.L124:
1518
- mov w22, w19
1519
- .loc 2 291 0
1520
- mov w0, -1
1521
- b .L108
1522
-.LVL226:
1523
-.L123:
1524
- .loc 2 261 0
1525
- mov w23, 1
1526
-.LVL227:
1527
- b .L72
1528
-.LVL228:
1529
-.L74:
1530
- .loc 2 132 0
1531
- adrp x0, .LANCHOR3
1532
- add x0, x0, :lo12:.LANCHOR3
1533
- ldrb w0, [x0, w25, sxtw]
1534
- cmp w23, w0
1535
- blt .L112
1536
- sub w23, w23, #2
1537
-.LVL229:
1538
- .loc 2 132 0 is_stmt 0 discriminator 1
1539
- mov x27, 0
1540
- lsl x23, x23, 3
1541
-.LVL230:
1542
-.L77:
1543
- .loc 2 137 0 is_stmt 1 discriminator 1
1544
- cmp x27, x23
1545
- bne .L78
1546
- .loc 2 147 0
1547
- add x2, x29, 112
1548
- mov w1, 0
1549
- mov w0, 53
1550
- bl uclass_get_device
1551
-.LVL231:
1552
- mov w23, w0
1553
-.LVL232:
1554
- .loc 2 148 0
1555
- cbz w0, .L79
1556
- .loc 2 149 0
1557
- mov w1, w0
1558
- adrp x0, .LC21
1559
-.LVL233:
1560
- add x0, x0, :lo12:.LC21
1561
- bl printf
1562
-.LVL234:
1563
-.L72:
1564
- .loc 2 308 0
1565
- mov w0, w23
1566
- ldp x19, x20, [sp, 16]
1567
- ldp x21, x22, [sp, 32]
1568
- ldp x23, x24, [sp, 48]
1569
- ldp x25, x26, [sp, 64]
1570
- ldp x27, x28, [sp, 80]
1571
- ldp x29, x30, [sp], 224
1572
- .cfi_restore 30
1573
- .cfi_restore 29
1574
- .cfi_restore 27
1575
- .cfi_restore 28
1576
- .cfi_restore 25
1577
- .cfi_restore 26
1578
- .cfi_restore 23
1579
- .cfi_restore 24
1580
- .cfi_restore 21
1581
- .cfi_restore 22
1582
- .cfi_restore 19
1583
- .cfi_restore 20
1584
- .cfi_def_cfa 31, 0
1585
- ret
1586
- .cfi_endproc
1587
-.LFE256:
1588
- .size do_ddr_test, .-do_ddr_test
1589
- .global _u_boot_list_2_cmd_2_ddr_test
1590
- .section .rodata
1591
- .align 3
1592
- .set .LANCHOR1,. + 0
1593
-.LC0:
1594
- .word 1437226410
1595
- .word -1437226411
1596
- .word 1515890085
1597
- .word -1515890086
1598
- .word -267448336
1599
- .word 267448335
1600
- .word 0
1601
- .word -1
1602
- .section .rodata.crosstalk.str1.1,"aMS",@progbits,1
1603
-.LC1:
1604
- .string "\nbitflip: \n"
1605
-.LC2:
1606
- .string "\b\b\b%3u"
1607
-.LC3:
1608
- .string "%3u\b\b\b"
1609
-.LC4:
1610
- .string "\nISI:\n"
1611
-.LC5:
1612
- .string "malloc %lu byte fail\n"
1613
- .section .rodata.diagonalscan.str1.1,"aMS",@progbits,1
1614
-.LC6:
1615
- .string "\nDiagonalScan\n"
1616
-.LC7:
1617
- .string "get page size fail:0x%x\n"
1618
- .section .rodata.do_ddr_test.str1.1,"aMS",@progbits,1
1619
-.LC18:
1620
- .string "ddr tester version 1.0.1\n"
1621
-.LC19:
1622
- .string "test parameters error\n"
1623
-.LC20:
1624
- .string "test pattern error\n"
1625
-.LC21:
1626
- .string "rockchip dmc probe fail: %d\n"
1627
-.LC22:
1628
- .string "\rtimes:%08u:\n"
1629
-.LC23:
1630
- .string "loop:%d, start:0x%lx, len:0x%lx\n"
1631
-.LC24:
1632
- .string "\rtimes:%08u, "
1633
-.LC25:
1634
- .string "\n%s test fail\n"
1635
-.LC26:
1636
- .string "\ntest pass\n"
1637
-.LC27:
1638
- .string "test pattern unsupported\n"
1639
-.LC28:
1640
- .string "fasttest need %uMB, but actually only %luMB\n"
1641
- .section .rodata.g_isi_pattern,"a",@progbits
1642
- .align 3
1643
- .set .LANCHOR0,. + 0
1644
- .type g_isi_pattern, %object
1645
- .size g_isi_pattern, 128
1646
-g_isi_pattern:
1647
- .word -1
1648
- .word 0
1649
- .word -1
1650
- .word 0
1651
- .word -1
1652
- .word 0
1653
- .word -1
1654
- .word -1
1655
- .word -1
1656
- .word -1
1657
- .word 0
1658
- .word -1
1659
- .word -1
1660
- .word -1
1661
- .word -1
1662
- .word 0
1663
- .word -1
1664
- .word 0
1665
- .word -1
1666
- .word 0
1667
- .word -1
1668
- .word 0
1669
- .word 0
1670
- .word 0
1671
- .word 0
1672
- .word -1
1673
- .word 0
1674
- .word 0
1675
- .word 0
1676
- .word 0
1677
- .word 0
1678
- .word 0
1679
- .section .rodata.random_test.str1.1,"aMS",@progbits,1
1680
-.LC8:
1681
- .string "%u"
1682
-.LC9:
1683
- .string "\b"
1684
-.LC10:
1685
- .string " "
1686
-.LC11:
1687
- .string "\nrandom test1 fail:address:0x%lx,read:0x%x,reread:0x%x,expect:0x%x\n"
1688
-.LC12:
1689
- .string "%4lu"
1690
-.LC13:
1691
- .string "\b\b\b\b"
1692
-.LC14:
1693
- .string " "
1694
-.LC15:
1695
- .string "\nrandom test2 fail:address:0x%lx,read:0x%lx,reread:0x%lx,expect:0x%lx\n"
1696
- .section .rodata.scan_freq.str1.1,"aMS",@progbits,1
1697
-.LC16:
1698
- .string "% d:change freq to %d Hz\n"
1699
-.LC17:
1700
- .string "check data fail at %d Hz\n"
1701
- .section .rodata.str1.1,"aMS",@progbits,1
1702
-.LC29:
1703
- .string "ddr_test"
1704
-.LC30:
1705
- .string "for dram simple test\n"
1706
-.LC31:
1707
- .ascii "arg1: test pattern include:\n\tchangefreq\n\tscanfreq\n\tran"
1708
- .ascii "dom\n\tcrosstalk\n\tdiagonalscan\n\tfast_test\n\tfull_test\n"
1709
- .ascii "for changereq: arg2:freq(Hz),arg3[option]:volt\nfor scanfreq"
1710
- .ascii ": arg2:minfreq(Hz),arg3:maxfreq(Hz),\n\targ4:scanfreq times,"
1711
- .ascii " arg5[option]:volt\nfor random, crosstalk and diagonalscan:a"
1712
- .ascii "rg2:freq(Hz), arg3:test times,\n\targ4: start addr, arg5:len"
1713
- .ascii "gth, arg6[option]:volt\nfor fast_test and full_test:arg2: mi"
1714
- .ascii "n_freq(Hz), arg3: max_freq(Hz)\n\targ4: test times, arg5[opt"
1715
- .ascii "ion]:volt\n\nfreq: means dram's target frequency,unit:Hz, if"
1716
- .ascii " 0:keep current freq\nminfreq, maxfreq: means min and max fr"
1717
- .ascii "equency for dram test,unit:Hz\ntest times: test loop, if 0: "
1718
- .ascii "endless loop\nstart_adr: start address of memory space for t"
1719
- .ascii "esting,unit:physical address\nlength: length of memory space"
1720
- .ascii " for testing,unit:Byte, if 0: full memory space test\nvolt: "
1721
- .ascii "means target voltage of vdd_logic\n\nexample:\nddr freq chan"
1722
- .ascii "ge to:786MHz, vdd_logic:1.05v:\n\t 'ddr_test changefreq 7860"
1723
- .ascii "00000 1050000'\nddr freq change to:786MHz, with default vdd_"
1724
- .ascii "logic:\n\t 'ddr_test changefreq 786000000'\nscanning ddr fre"
1725
- .ascii "quency between 200 and 786MHz for 10 times:\n\t 'ddr_test sc"
1726
- .ascii "anfreq 200000000 786000000 100'\ndoing random test 10 times "
1727
- .ascii "start from"
1728
- .string " physical address 0x200000 and\nlength is 128MB, freq:786MHz, if freq=0 may keep current freq:\n\t 'ddr_test random 786000000 10 0x200000 0x8000000'\ndoing fast test for dram between 200MHz to 786MHz with 10 times:\n\t 'ddr_test fast_test 200000000 786000000 10'"
1729
-.LC32:
1730
- .string "changefreq"
1731
-.LC33:
1732
- .string "scanfreq"
1733
-.LC34:
1734
- .string "random"
1735
-.LC35:
1736
- .string "crosstalk"
1737
-.LC36:
1738
- .string "diagonalscan"
1739
-.LC37:
1740
- .string "fast_test"
1741
-.LC38:
1742
- .string "full_test"
1743
- .section .rodata.test_pat_param,"a",@progbits
1744
- .align 3
1745
- .set .LANCHOR3,. + 0
1746
- .type test_pat_param, %object
1747
- .size test_pat_param, 7
1748
-test_pat_param:
1749
- .byte 3
1750
- .byte 5
1751
- .byte 6
1752
- .byte 6
1753
- .byte 6
1754
- .byte 5
1755
- .byte 5
1756
- .section .rodata.test_pattern,"a",@progbits
1757
- .align 3
1758
- .set .LANCHOR2,. + 0
1759
- .type test_pattern, %object
1760
- .size test_pattern, 56
1761
-test_pattern:
1762
- .xword .LC32
1763
- .xword .LC33
1764
- .xword .LC34
1765
- .xword .LC35
1766
- .xword .LC36
1767
- .xword .LC37
1768
- .xword .LC38
1769
- .section .u_boot_list_2_cmd_2_ddr_test,"aw",@progbits
1770
- .align 2
1771
- .type _u_boot_list_2_cmd_2_ddr_test, %object
1772
- .size _u_boot_list_2_cmd_2_ddr_test, 48
1773
-_u_boot_list_2_cmd_2_ddr_test:
1774
- .8byte .LC29
1775
- .word 7
1776
- .word 1
1777
- .8byte do_ddr_test
1778
- .8byte .LC30
1779
- .8byte .LC31
1780
- .8byte 0
1781
- .text
1782
-.Letext0:
1783
- .file 5 "include/common.h"
1784
- .file 6 "./arch/arm/include/asm/types.h"
1785
- .file 7 "include/linux/types.h"
1786
- .file 8 "include/errno.h"
1787
- .file 9 "include/linux/string.h"
1788
- .file 10 "include/efi.h"
1789
- .file 11 "include/dm/device.h"
1790
- .file 12 "include/ide.h"
1791
- .file 13 "include/linux/list.h"
1792
- .file 14 "include/part.h"
1793
- .file 15 "include/flash.h"
1794
- .file 16 "include/lmb.h"
1795
- .file 17 "include/asm-generic/u-boot.h"
1796
- .file 18 "./arch/arm/include/asm/u-boot-arm.h"
1797
- .file 19 "include/command.h"
1798
- .file 20 "include/linux/libfdt_env.h"
1799
- .file 21 "include/linux/../../scripts/dtc/libfdt/fdt.h"
1800
- .file 22 "include/linux/libfdt.h"
1801
- .file 23 "include/image.h"
1802
- .file 24 "include/dm/uclass-id.h"
1803
- .file 25 "./arch/arm/include/asm/global_data.h"
1804
- .file 26 "include/asm-generic/global_data.h"
1805
- .file 27 "include/dm/of.h"
1806
- .file 28 "include/net.h"
1807
- .file 29 "include/malloc.h"
1808
- .file 30 "include/dm/ofnode.h"
1809
- .file 31 "include/linux/compat.h"
1810
- .file 32 "include/dm/uclass.h"
1811
- .file 33 "include/console.h"
1812
- .file 34 "include/stdio_dev.h"
1813
- .file 35 "include/iomux.h"
1814
- .file 36 "include/log.h"
1815
- .file 37 "include/stdio.h"
1816
- .file 38 "./arch/arm/include/asm/arch/sdram.h"
1817
- .file 39 "cmd/ddr_tool/../memtester/io_map.h"
1818
- .file 40 "cmd/ddr_tool/../memtester/ddr_tester_common.h"
1819
- .file 41 "include/vsprintf.h"
1820
- .section .debug_info,"",@progbits
1821
-.Ldebug_info0:
1822
- .4byte 0x27ad
1823
- .2byte 0x4
1824
- .4byte .Ldebug_abbrev0
1825
- .byte 0x8
1826
- .uleb128 0x1
1827
- .4byte .LASF478
1828
- .byte 0xc
1829
- .4byte .LASF479
1830
- .4byte .LASF480
1831
- .4byte .Ldebug_ranges0+0x90
1832
- .8byte 0
1833
- .4byte .Ldebug_line0
1834
- .uleb128 0x2
1835
- .4byte .LASF4
1836
- .byte 0x5
1837
- .byte 0xd
1838
- .4byte 0x34
1839
- .uleb128 0x3
1840
- .byte 0x1
1841
- .byte 0x8
1842
- .4byte .LASF0
1843
- .uleb128 0x3
1844
- .byte 0x8
1845
- .byte 0x7
1846
- .4byte .LASF1
1847
- .uleb128 0x4
1848
- .4byte 0x3b
1849
- .uleb128 0x3
1850
- .byte 0x2
1851
- .byte 0x7
1852
- .4byte .LASF2
1853
- .uleb128 0x5
1854
- .4byte .LASF21
1855
- .byte 0x8
1856
- .byte 0xc
1857
- .4byte 0x59
1858
- .uleb128 0x6
1859
- .byte 0x4
1860
- .byte 0x5
1861
- .string "int"
1862
- .uleb128 0x3
1863
- .byte 0x1
1864
- .byte 0x6
1865
- .4byte .LASF3
1866
- .uleb128 0x2
1867
- .4byte .LASF5
1868
- .byte 0x6
1869
- .byte 0xc
1870
- .4byte 0x34
1871
- .uleb128 0x3
1872
- .byte 0x2
1873
- .byte 0x5
1874
- .4byte .LASF6
1875
- .uleb128 0x2
1876
- .4byte .LASF7
1877
- .byte 0x6
1878
- .byte 0x12
1879
- .4byte 0x84
1880
- .uleb128 0x3
1881
- .byte 0x4
1882
- .byte 0x7
1883
- .4byte .LASF8
1884
- .uleb128 0x3
1885
- .byte 0x8
1886
- .byte 0x5
1887
- .4byte .LASF9
1888
- .uleb128 0x3
1889
- .byte 0x8
1890
- .byte 0x7
1891
- .4byte .LASF10
1892
- .uleb128 0x7
1893
- .string "u8"
1894
- .byte 0x6
1895
- .byte 0x1f
1896
- .4byte 0x34
1897
- .uleb128 0x8
1898
- .4byte 0x99
1899
- .uleb128 0x7
1900
- .string "u32"
1901
- .byte 0x6
1902
- .byte 0x25
1903
- .4byte 0x84
1904
- .uleb128 0x4
1905
- .4byte 0xa8
1906
- .uleb128 0x2
1907
- .4byte .LASF11
1908
- .byte 0x6
1909
- .byte 0x31
1910
- .4byte 0x92
1911
- .uleb128 0x2
1912
- .4byte .LASF12
1913
- .byte 0x6
1914
- .byte 0x32
1915
- .4byte 0x92
1916
- .uleb128 0x3
1917
- .byte 0x8
1918
- .byte 0x7
1919
- .4byte .LASF13
1920
- .uleb128 0x9
1921
- .byte 0x8
1922
- .4byte 0xe7
1923
- .uleb128 0x8
1924
- .4byte 0xd5
1925
- .uleb128 0x3
1926
- .byte 0x1
1927
- .byte 0x8
1928
- .4byte .LASF14
1929
- .uleb128 0x8
1930
- .4byte 0xe0
1931
- .uleb128 0x3
1932
- .byte 0x8
1933
- .byte 0x5
1934
- .4byte .LASF15
1935
- .uleb128 0x9
1936
- .byte 0x8
1937
- .4byte 0xe0
1938
- .uleb128 0x8
1939
- .4byte 0xf3
1940
- .uleb128 0x2
1941
- .4byte .LASF16
1942
- .byte 0x7
1943
- .byte 0x59
1944
- .4byte 0x47
1945
- .uleb128 0x2
1946
- .4byte .LASF17
1947
- .byte 0x7
1948
- .byte 0x5b
1949
- .4byte 0x3b
1950
- .uleb128 0x2
1951
- .4byte .LASF18
1952
- .byte 0x7
1953
- .byte 0x69
1954
- .4byte 0x67
1955
- .uleb128 0x2
1956
- .4byte .LASF19
1957
- .byte 0x7
1958
- .byte 0x6b
1959
- .4byte 0x79
1960
- .uleb128 0x2
1961
- .4byte .LASF20
1962
- .byte 0x7
1963
- .byte 0x97
1964
- .4byte 0x79
1965
- .uleb128 0xa
1966
- .byte 0x8
1967
- .uleb128 0x5
1968
- .4byte .LASF22
1969
- .byte 0x9
1970
- .byte 0xb
1971
- .4byte 0xf3
1972
- .uleb128 0x3
1973
- .byte 0x1
1974
- .byte 0x2
1975
- .4byte .LASF23
1976
- .uleb128 0xb
1977
- .4byte 0xe0
1978
- .4byte 0x154
1979
- .uleb128 0xc
1980
- .byte 0
1981
- .uleb128 0xd
1982
- .4byte .LASF24
1983
- .byte 0xa
1984
- .2byte 0x140
1985
- .4byte 0x149
1986
- .uleb128 0xd
1987
- .4byte .LASF25
1988
- .byte 0xa
1989
- .2byte 0x143
1990
- .4byte 0x149
1991
- .uleb128 0xd
1992
- .4byte .LASF26
1993
- .byte 0xa
1994
- .2byte 0x143
1995
- .4byte 0x149
1996
- .uleb128 0xe
1997
- .4byte .LASF45
1998
- .byte 0xa0
1999
- .byte 0xb
2000
- .byte 0x80
2001
- .4byte 0x25d
2002
- .uleb128 0xf
2003
- .4byte .LASF27
2004
- .byte 0xb
2005
- .byte 0x81
2006
- .4byte 0x1517
2007
- .byte 0
2008
- .uleb128 0xf
2009
- .4byte .LASF28
2010
- .byte 0xb
2011
- .byte 0x82
2012
- .4byte 0xd5
2013
- .byte 0x8
2014
- .uleb128 0xf
2015
- .4byte .LASF29
2016
- .byte 0xb
2017
- .byte 0x83
2018
- .4byte 0x135
2019
- .byte 0x10
2020
- .uleb128 0xf
2021
- .4byte .LASF30
2022
- .byte 0xb
2023
- .byte 0x84
2024
- .4byte 0x135
2025
- .byte 0x18
2026
- .uleb128 0xf
2027
- .4byte .LASF31
2028
- .byte 0xb
2029
- .byte 0x85
2030
- .4byte 0x135
2031
- .byte 0x20
2032
- .uleb128 0xf
2033
- .4byte .LASF32
2034
- .byte 0xb
2035
- .byte 0x86
2036
- .4byte 0x14e2
2037
- .byte 0x28
2038
- .uleb128 0xf
2039
- .4byte .LASF33
2040
- .byte 0xb
2041
- .byte 0x87
2042
- .4byte 0x109
2043
- .byte 0x30
2044
- .uleb128 0xf
2045
- .4byte .LASF34
2046
- .byte 0xb
2047
- .byte 0x88
2048
- .4byte 0x25d
2049
- .byte 0x38
2050
- .uleb128 0xf
2051
- .4byte .LASF35
2052
- .byte 0xb
2053
- .byte 0x89
2054
- .4byte 0x135
2055
- .byte 0x40
2056
- .uleb128 0xf
2057
- .4byte .LASF36
2058
- .byte 0xb
2059
- .byte 0x8a
2060
- .4byte 0x155a
2061
- .byte 0x48
2062
- .uleb128 0xf
2063
- .4byte .LASF37
2064
- .byte 0xb
2065
- .byte 0x8b
2066
- .4byte 0x135
2067
- .byte 0x50
2068
- .uleb128 0xf
2069
- .4byte .LASF38
2070
- .byte 0xb
2071
- .byte 0x8c
2072
- .4byte 0x135
2073
- .byte 0x58
2074
- .uleb128 0xf
2075
- .4byte .LASF39
2076
- .byte 0xb
2077
- .byte 0x8d
2078
- .4byte 0x290
2079
- .byte 0x60
2080
- .uleb128 0xf
2081
- .4byte .LASF40
2082
- .byte 0xb
2083
- .byte 0x8e
2084
- .4byte 0x290
2085
- .byte 0x70
2086
- .uleb128 0xf
2087
- .4byte .LASF41
2088
- .byte 0xb
2089
- .byte 0x8f
2090
- .4byte 0x290
2091
- .byte 0x80
2092
- .uleb128 0xf
2093
- .4byte .LASF42
2094
- .byte 0xb
2095
- .byte 0x90
2096
- .4byte 0x11f
2097
- .byte 0x90
2098
- .uleb128 0xf
2099
- .4byte .LASF43
2100
- .byte 0xb
2101
- .byte 0x91
2102
- .4byte 0x59
2103
- .byte 0x94
2104
- .uleb128 0x10
2105
- .string "seq"
2106
- .byte 0xb
2107
- .byte 0x92
2108
- .4byte 0x59
2109
- .byte 0x98
2110
- .byte 0
2111
- .uleb128 0x9
2112
- .byte 0x8
2113
- .4byte 0x178
2114
- .uleb128 0x9
2115
- .byte 0x8
2116
- .4byte 0x269
2117
- .uleb128 0x11
2118
- .uleb128 0xb
2119
- .4byte 0x109
2120
- .4byte 0x275
2121
- .uleb128 0xc
2122
- .byte 0
2123
- .uleb128 0x5
2124
- .4byte .LASF44
2125
- .byte 0xc
2126
- .byte 0x10
2127
- .4byte 0x26a
2128
- .uleb128 0xb
2129
- .4byte 0x34
2130
- .4byte 0x290
2131
- .uleb128 0x12
2132
- .4byte 0xce
2133
- .byte 0x5
2134
- .byte 0
2135
- .uleb128 0xe
2136
- .4byte .LASF46
2137
- .byte 0x10
2138
- .byte 0xd
2139
- .byte 0x16
2140
- .4byte 0x2b5
2141
- .uleb128 0xf
2142
- .4byte .LASF47
2143
- .byte 0xd
2144
- .byte 0x17
2145
- .4byte 0x2b5
2146
- .byte 0
2147
- .uleb128 0xf
2148
- .4byte .LASF48
2149
- .byte 0xd
2150
- .byte 0x17
2151
- .4byte 0x2b5
2152
- .byte 0x8
2153
- .byte 0
2154
- .uleb128 0x9
2155
- .byte 0x8
2156
- .4byte 0x290
2157
- .uleb128 0xe
2158
- .4byte .LASF49
2159
- .byte 0x10
2160
- .byte 0xe
2161
- .byte 0xf
2162
- .4byte 0x2e0
2163
- .uleb128 0xf
2164
- .4byte .LASF28
2165
- .byte 0xe
2166
- .byte 0x10
2167
- .4byte 0xf3
2168
- .byte 0
2169
- .uleb128 0xf
2170
- .4byte .LASF50
2171
- .byte 0xe
2172
- .byte 0x11
2173
- .4byte 0x2f9
2174
- .byte 0x8
2175
- .byte 0
2176
- .uleb128 0x8
2177
- .4byte 0x2bb
2178
- .uleb128 0x13
2179
- .4byte 0x59
2180
- .4byte 0x2f9
2181
- .uleb128 0x14
2182
- .4byte 0x59
2183
- .uleb128 0x14
2184
- .4byte 0x59
2185
- .byte 0
2186
- .uleb128 0x9
2187
- .byte 0x8
2188
- .4byte 0x2e5
2189
- .uleb128 0xb
2190
- .4byte 0x2e0
2191
- .4byte 0x30a
2192
- .uleb128 0xc
2193
- .byte 0
2194
- .uleb128 0x8
2195
- .4byte 0x2ff
2196
- .uleb128 0x5
2197
- .4byte .LASF49
2198
- .byte 0xe
2199
- .byte 0xce
2200
- .4byte 0x30a
2201
- .uleb128 0x15
2202
- .2byte 0x1218
2203
- .byte 0xf
2204
- .byte 0x13
2205
- .4byte 0x361
2206
- .uleb128 0xf
2207
- .4byte .LASF51
2208
- .byte 0xf
2209
- .byte 0x14
2210
- .4byte 0x109
2211
- .byte 0
2212
- .uleb128 0xf
2213
- .4byte .LASF52
2214
- .byte 0xf
2215
- .byte 0x15
2216
- .4byte 0xfe
2217
- .byte 0x8
2218
- .uleb128 0xf
2219
- .4byte .LASF53
2220
- .byte 0xf
2221
- .byte 0x16
2222
- .4byte 0x109
2223
- .byte 0x10
2224
- .uleb128 0xf
2225
- .4byte .LASF54
2226
- .byte 0xf
2227
- .byte 0x17
2228
- .4byte 0x361
2229
- .byte 0x18
2230
- .uleb128 0x16
2231
- .4byte .LASF55
2232
- .byte 0xf
2233
- .byte 0x18
2234
- .4byte 0x372
2235
- .2byte 0x1018
2236
- .byte 0
2237
- .uleb128 0xb
2238
- .4byte 0x109
2239
- .4byte 0x372
2240
- .uleb128 0x17
2241
- .4byte 0xce
2242
- .2byte 0x1ff
2243
- .byte 0
2244
- .uleb128 0xb
2245
- .4byte 0x29
2246
- .4byte 0x383
2247
- .uleb128 0x17
2248
- .4byte 0xce
2249
- .2byte 0x1ff
2250
- .byte 0
2251
- .uleb128 0x2
2252
- .4byte .LASF56
2253
- .byte 0xf
2254
- .byte 0x32
2255
- .4byte 0x31a
2256
- .uleb128 0xb
2257
- .4byte 0x383
2258
- .4byte 0x399
2259
- .uleb128 0xc
2260
- .byte 0
2261
- .uleb128 0x5
2262
- .4byte .LASF57
2263
- .byte 0xf
2264
- .byte 0x34
2265
- .4byte 0x38e
2266
- .uleb128 0x3
2267
- .byte 0x10
2268
- .byte 0x4
2269
- .4byte .LASF58
2270
- .uleb128 0xe
2271
- .4byte .LASF59
2272
- .byte 0x10
2273
- .byte 0x10
2274
- .byte 0x10
2275
- .4byte 0x3d0
2276
- .uleb128 0xf
2277
- .4byte .LASF60
2278
- .byte 0x10
2279
- .byte 0x11
2280
- .4byte 0xb8
2281
- .byte 0
2282
- .uleb128 0xf
2283
- .4byte .LASF51
2284
- .byte 0x10
2285
- .byte 0x12
2286
- .4byte 0xc3
2287
- .byte 0x8
2288
- .byte 0
2289
- .uleb128 0xe
2290
- .4byte .LASF61
2291
- .byte 0xa0
2292
- .byte 0x10
2293
- .byte 0x15
2294
- .4byte 0x401
2295
- .uleb128 0x10
2296
- .string "cnt"
2297
- .byte 0x10
2298
- .byte 0x16
2299
- .4byte 0x3b
2300
- .byte 0
2301
- .uleb128 0xf
2302
- .4byte .LASF51
2303
- .byte 0x10
2304
- .byte 0x17
2305
- .4byte 0xc3
2306
- .byte 0x8
2307
- .uleb128 0xf
2308
- .4byte .LASF62
2309
- .byte 0x10
2310
- .byte 0x18
2311
- .4byte 0x401
2312
- .byte 0x10
2313
- .byte 0
2314
- .uleb128 0xb
2315
- .4byte 0x3ab
2316
- .4byte 0x411
2317
- .uleb128 0x12
2318
- .4byte 0xce
2319
- .byte 0x8
2320
- .byte 0
2321
- .uleb128 0x18
2322
- .string "lmb"
2323
- .2byte 0x140
2324
- .byte 0x10
2325
- .byte 0x1b
2326
- .4byte 0x437
2327
- .uleb128 0xf
2328
- .4byte .LASF63
2329
- .byte 0x10
2330
- .byte 0x1c
2331
- .4byte 0x3d0
2332
- .byte 0
2333
- .uleb128 0xf
2334
- .4byte .LASF64
2335
- .byte 0x10
2336
- .byte 0x1d
2337
- .4byte 0x3d0
2338
- .byte 0xa0
2339
- .byte 0
2340
- .uleb128 0x19
2341
- .string "lmb"
2342
- .byte 0x10
2343
- .byte 0x20
2344
- .4byte 0x411
2345
- .uleb128 0x1a
2346
- .byte 0x10
2347
- .byte 0x11
2348
- .byte 0x5a
2349
- .4byte 0x463
2350
- .uleb128 0xf
2351
- .4byte .LASF54
2352
- .byte 0x11
2353
- .byte 0x5b
2354
- .4byte 0xb8
2355
- .byte 0
2356
- .uleb128 0xf
2357
- .4byte .LASF51
2358
- .byte 0x11
2359
- .byte 0x5c
2360
- .4byte 0xc3
2361
- .byte 0x8
2362
- .byte 0
2363
- .uleb128 0xe
2364
- .4byte .LASF65
2365
- .byte 0xc8
2366
- .byte 0x11
2367
- .byte 0x1b
2368
- .4byte 0x554
2369
- .uleb128 0xf
2370
- .4byte .LASF66
2371
- .byte 0x11
2372
- .byte 0x1c
2373
- .4byte 0x3b
2374
- .byte 0
2375
- .uleb128 0xf
2376
- .4byte .LASF67
2377
- .byte 0x11
2378
- .byte 0x1d
2379
- .4byte 0xc3
2380
- .byte 0x8
2381
- .uleb128 0xf
2382
- .4byte .LASF68
2383
- .byte 0x11
2384
- .byte 0x1e
2385
- .4byte 0x3b
2386
- .byte 0x10
2387
- .uleb128 0xf
2388
- .4byte .LASF69
2389
- .byte 0x11
2390
- .byte 0x1f
2391
- .4byte 0x3b
2392
- .byte 0x18
2393
- .uleb128 0xf
2394
- .4byte .LASF70
2395
- .byte 0x11
2396
- .byte 0x20
2397
- .4byte 0x3b
2398
- .byte 0x20
2399
- .uleb128 0xf
2400
- .4byte .LASF71
2401
- .byte 0x11
2402
- .byte 0x21
2403
- .4byte 0x3b
2404
- .byte 0x28
2405
- .uleb128 0xf
2406
- .4byte .LASF72
2407
- .byte 0x11
2408
- .byte 0x22
2409
- .4byte 0x3b
2410
- .byte 0x30
2411
- .uleb128 0xf
2412
- .4byte .LASF73
2413
- .byte 0x11
2414
- .byte 0x24
2415
- .4byte 0x3b
2416
- .byte 0x38
2417
- .uleb128 0xf
2418
- .4byte .LASF74
2419
- .byte 0x11
2420
- .byte 0x25
2421
- .4byte 0x3b
2422
- .byte 0x40
2423
- .uleb128 0xf
2424
- .4byte .LASF75
2425
- .byte 0x11
2426
- .byte 0x26
2427
- .4byte 0x3b
2428
- .byte 0x48
2429
- .uleb128 0xf
2430
- .4byte .LASF76
2431
- .byte 0x11
2432
- .byte 0x31
2433
- .4byte 0x3b
2434
- .byte 0x50
2435
- .uleb128 0xf
2436
- .4byte .LASF77
2437
- .byte 0x11
2438
- .byte 0x32
2439
- .4byte 0x3b
2440
- .byte 0x58
2441
- .uleb128 0xf
2442
- .4byte .LASF78
2443
- .byte 0x11
2444
- .byte 0x33
2445
- .4byte 0x280
2446
- .byte 0x60
2447
- .uleb128 0xf
2448
- .4byte .LASF79
2449
- .byte 0x11
2450
- .byte 0x34
2451
- .4byte 0x47
2452
- .byte 0x66
2453
- .uleb128 0xf
2454
- .4byte .LASF80
2455
- .byte 0x11
2456
- .byte 0x35
2457
- .4byte 0x3b
2458
- .byte 0x68
2459
- .uleb128 0xf
2460
- .4byte .LASF81
2461
- .byte 0x11
2462
- .byte 0x36
2463
- .4byte 0x3b
2464
- .byte 0x70
2465
- .uleb128 0xf
2466
- .4byte .LASF82
2467
- .byte 0x11
2468
- .byte 0x57
2469
- .4byte 0x109
2470
- .byte 0x78
2471
- .uleb128 0xf
2472
- .4byte .LASF83
2473
- .byte 0x11
2474
- .byte 0x58
2475
- .4byte 0x109
2476
- .byte 0x80
2477
- .uleb128 0xf
2478
- .4byte .LASF84
2479
- .byte 0x11
2480
- .byte 0x5d
2481
- .4byte 0x554
2482
- .byte 0x88
2483
- .byte 0
2484
- .uleb128 0xb
2485
- .4byte 0x442
2486
- .4byte 0x564
2487
- .uleb128 0x12
2488
- .4byte 0xce
2489
- .byte 0x3
2490
- .byte 0
2491
- .uleb128 0x2
2492
- .4byte .LASF85
2493
- .byte 0x11
2494
- .byte 0x5f
2495
- .4byte 0x463
2496
- .uleb128 0x5
2497
- .4byte .LASF86
2498
- .byte 0x12
2499
- .byte 0x13
2500
- .4byte 0x109
2501
- .uleb128 0x5
2502
- .4byte .LASF87
2503
- .byte 0x12
2504
- .byte 0x14
2505
- .4byte 0x109
2506
- .uleb128 0x5
2507
- .4byte .LASF88
2508
- .byte 0x12
2509
- .byte 0x15
2510
- .4byte 0x109
2511
- .uleb128 0x5
2512
- .4byte .LASF89
2513
- .byte 0x12
2514
- .byte 0x16
2515
- .4byte 0x109
2516
- .uleb128 0x5
2517
- .4byte .LASF90
2518
- .byte 0x12
2519
- .byte 0x17
2520
- .4byte 0x109
2521
- .uleb128 0x5
2522
- .4byte .LASF91
2523
- .byte 0x12
2524
- .byte 0x18
2525
- .4byte 0x109
2526
- .uleb128 0x5
2527
- .4byte .LASF92
2528
- .byte 0x12
2529
- .byte 0x19
2530
- .4byte 0x109
2531
- .uleb128 0xe
2532
- .4byte .LASF93
2533
- .byte 0x30
2534
- .byte 0x13
2535
- .byte 0x1e
2536
- .4byte 0x61d
2537
- .uleb128 0xf
2538
- .4byte .LASF28
2539
- .byte 0x13
2540
- .byte 0x1f
2541
- .4byte 0xf3
2542
- .byte 0
2543
- .uleb128 0xf
2544
- .4byte .LASF94
2545
- .byte 0x13
2546
- .byte 0x20
2547
- .4byte 0x59
2548
- .byte 0x8
2549
- .uleb128 0xf
2550
- .4byte .LASF95
2551
- .byte 0x13
2552
- .byte 0x21
2553
- .4byte 0x59
2554
- .byte 0xc
2555
- .uleb128 0x10
2556
- .string "cmd"
2557
- .byte 0x13
2558
- .byte 0x23
2559
- .4byte 0x647
2560
- .byte 0x10
2561
- .uleb128 0xf
2562
- .4byte .LASF96
2563
- .byte 0x13
2564
- .byte 0x24
2565
- .4byte 0xf3
2566
- .byte 0x18
2567
- .uleb128 0xf
2568
- .4byte .LASF97
2569
- .byte 0x13
2570
- .byte 0x26
2571
- .4byte 0xf3
2572
- .byte 0x20
2573
- .uleb128 0xf
2574
- .4byte .LASF98
2575
- .byte 0x13
2576
- .byte 0x2a
2577
- .4byte 0x676
2578
- .byte 0x28
2579
- .byte 0
2580
- .uleb128 0x13
2581
- .4byte 0x59
2582
- .4byte 0x63b
2583
- .uleb128 0x14
2584
- .4byte 0x63b
2585
- .uleb128 0x14
2586
- .4byte 0x59
2587
- .uleb128 0x14
2588
- .4byte 0x59
2589
- .uleb128 0x14
2590
- .4byte 0x641
2591
- .byte 0
2592
- .uleb128 0x9
2593
- .byte 0x8
2594
- .4byte 0x5bc
2595
- .uleb128 0x9
2596
- .byte 0x8
2597
- .4byte 0xf9
2598
- .uleb128 0x9
2599
- .byte 0x8
2600
- .4byte 0x61d
2601
- .uleb128 0x13
2602
- .4byte 0x59
2603
- .4byte 0x670
2604
- .uleb128 0x14
2605
- .4byte 0x59
2606
- .uleb128 0x14
2607
- .4byte 0x641
2608
- .uleb128 0x14
2609
- .4byte 0xe0
2610
- .uleb128 0x14
2611
- .4byte 0x59
2612
- .uleb128 0x14
2613
- .4byte 0x670
2614
- .byte 0
2615
- .uleb128 0x9
2616
- .byte 0x8
2617
- .4byte 0xf3
2618
- .uleb128 0x9
2619
- .byte 0x8
2620
- .4byte 0x64d
2621
- .uleb128 0x2
2622
- .4byte .LASF99
2623
- .byte 0x13
2624
- .byte 0x2e
2625
- .4byte 0x5bc
2626
- .uleb128 0x1b
2627
- .4byte .LASF167
2628
- .byte 0x4
2629
- .4byte 0x59
2630
- .byte 0x13
2631
- .byte 0x7a
2632
- .4byte 0x6aa
2633
- .uleb128 0x1c
2634
- .4byte .LASF100
2635
- .byte 0
2636
- .uleb128 0x1c
2637
- .4byte .LASF101
2638
- .byte 0x1
2639
- .uleb128 0x1d
2640
- .4byte .LASF102
2641
- .sleb128 -1
2642
- .byte 0
2643
- .uleb128 0x2
2644
- .4byte .LASF103
2645
- .byte 0x14
2646
- .byte 0x11
2647
- .4byte 0x12a
2648
- .uleb128 0xe
2649
- .4byte .LASF104
2650
- .byte 0x28
2651
- .byte 0x15
2652
- .byte 0x39
2653
- .4byte 0x73a
2654
- .uleb128 0xf
2655
- .4byte .LASF105
2656
- .byte 0x15
2657
- .byte 0x3a
2658
- .4byte 0x6aa
2659
- .byte 0
2660
- .uleb128 0xf
2661
- .4byte .LASF106
2662
- .byte 0x15
2663
- .byte 0x3b
2664
- .4byte 0x6aa
2665
- .byte 0x4
2666
- .uleb128 0xf
2667
- .4byte .LASF107
2668
- .byte 0x15
2669
- .byte 0x3c
2670
- .4byte 0x6aa
2671
- .byte 0x8
2672
- .uleb128 0xf
2673
- .4byte .LASF108
2674
- .byte 0x15
2675
- .byte 0x3d
2676
- .4byte 0x6aa
2677
- .byte 0xc
2678
- .uleb128 0xf
2679
- .4byte .LASF109
2680
- .byte 0x15
2681
- .byte 0x3e
2682
- .4byte 0x6aa
2683
- .byte 0x10
2684
- .uleb128 0xf
2685
- .4byte .LASF110
2686
- .byte 0x15
2687
- .byte 0x3f
2688
- .4byte 0x6aa
2689
- .byte 0x14
2690
- .uleb128 0xf
2691
- .4byte .LASF111
2692
- .byte 0x15
2693
- .byte 0x40
2694
- .4byte 0x6aa
2695
- .byte 0x18
2696
- .uleb128 0xf
2697
- .4byte .LASF112
2698
- .byte 0x15
2699
- .byte 0x43
2700
- .4byte 0x6aa
2701
- .byte 0x1c
2702
- .uleb128 0xf
2703
- .4byte .LASF113
2704
- .byte 0x15
2705
- .byte 0x46
2706
- .4byte 0x6aa
2707
- .byte 0x20
2708
- .uleb128 0xf
2709
- .4byte .LASF114
2710
- .byte 0x15
2711
- .byte 0x49
2712
- .4byte 0x6aa
2713
- .byte 0x24
2714
- .byte 0
2715
- .uleb128 0xd
2716
- .4byte .LASF115
2717
- .byte 0x16
2718
- .2byte 0x136
2719
- .4byte 0x746
2720
- .uleb128 0x9
2721
- .byte 0x8
2722
- .4byte 0x6b5
2723
- .uleb128 0x1e
2724
- .4byte .LASF116
2725
- .byte 0x40
2726
- .byte 0x17
2727
- .2byte 0x134
2728
- .4byte 0x7f6
2729
- .uleb128 0x1f
2730
- .4byte .LASF117
2731
- .byte 0x17
2732
- .2byte 0x135
2733
- .4byte 0x12a
2734
- .byte 0
2735
- .uleb128 0x1f
2736
- .4byte .LASF118
2737
- .byte 0x17
2738
- .2byte 0x136
2739
- .4byte 0x12a
2740
- .byte 0x4
2741
- .uleb128 0x1f
2742
- .4byte .LASF119
2743
- .byte 0x17
2744
- .2byte 0x137
2745
- .4byte 0x12a
2746
- .byte 0x8
2747
- .uleb128 0x1f
2748
- .4byte .LASF120
2749
- .byte 0x17
2750
- .2byte 0x138
2751
- .4byte 0x12a
2752
- .byte 0xc
2753
- .uleb128 0x1f
2754
- .4byte .LASF121
2755
- .byte 0x17
2756
- .2byte 0x139
2757
- .4byte 0x12a
2758
- .byte 0x10
2759
- .uleb128 0x1f
2760
- .4byte .LASF122
2761
- .byte 0x17
2762
- .2byte 0x13a
2763
- .4byte 0x12a
2764
- .byte 0x14
2765
- .uleb128 0x1f
2766
- .4byte .LASF123
2767
- .byte 0x17
2768
- .2byte 0x13b
2769
- .4byte 0x12a
2770
- .byte 0x18
2771
- .uleb128 0x1f
2772
- .4byte .LASF124
2773
- .byte 0x17
2774
- .2byte 0x13c
2775
- .4byte 0x114
2776
- .byte 0x1c
2777
- .uleb128 0x1f
2778
- .4byte .LASF125
2779
- .byte 0x17
2780
- .2byte 0x13d
2781
- .4byte 0x114
2782
- .byte 0x1d
2783
- .uleb128 0x1f
2784
- .4byte .LASF126
2785
- .byte 0x17
2786
- .2byte 0x13e
2787
- .4byte 0x114
2788
- .byte 0x1e
2789
- .uleb128 0x1f
2790
- .4byte .LASF127
2791
- .byte 0x17
2792
- .2byte 0x13f
2793
- .4byte 0x114
2794
- .byte 0x1f
2795
- .uleb128 0x1f
2796
- .4byte .LASF128
2797
- .byte 0x17
2798
- .2byte 0x140
2799
- .4byte 0x7f6
2800
- .byte 0x20
2801
- .byte 0
2802
- .uleb128 0xb
2803
- .4byte 0x114
2804
- .4byte 0x806
2805
- .uleb128 0x12
2806
- .4byte 0xce
2807
- .byte 0x1f
2808
- .byte 0
2809
- .uleb128 0x20
2810
- .4byte .LASF129
2811
- .byte 0x17
2812
- .2byte 0x141
2813
- .4byte 0x74c
2814
- .uleb128 0x1e
2815
- .4byte .LASF130
2816
- .byte 0x30
2817
- .byte 0x17
2818
- .2byte 0x143
2819
- .4byte 0x894
2820
- .uleb128 0x1f
2821
- .4byte .LASF54
2822
- .byte 0x17
2823
- .2byte 0x144
2824
- .4byte 0x109
2825
- .byte 0
2826
- .uleb128 0x21
2827
- .string "end"
2828
- .byte 0x17
2829
- .2byte 0x144
2830
- .4byte 0x109
2831
- .byte 0x8
2832
- .uleb128 0x1f
2833
- .4byte .LASF131
2834
- .byte 0x17
2835
- .2byte 0x145
2836
- .4byte 0x109
2837
- .byte 0x10
2838
- .uleb128 0x1f
2839
- .4byte .LASF132
2840
- .byte 0x17
2841
- .2byte 0x145
2842
- .4byte 0x109
2843
- .byte 0x18
2844
- .uleb128 0x1f
2845
- .4byte .LASF133
2846
- .byte 0x17
2847
- .2byte 0x146
2848
- .4byte 0x109
2849
- .byte 0x20
2850
- .uleb128 0x1f
2851
- .4byte .LASF134
2852
- .byte 0x17
2853
- .2byte 0x147
2854
- .4byte 0x114
2855
- .byte 0x28
2856
- .uleb128 0x1f
2857
- .4byte .LASF135
2858
- .byte 0x17
2859
- .2byte 0x147
2860
- .4byte 0x114
2861
- .byte 0x29
2862
- .uleb128 0x21
2863
- .string "os"
2864
- .byte 0x17
2865
- .2byte 0x147
2866
- .4byte 0x114
2867
- .byte 0x2a
2868
- .uleb128 0x1f
2869
- .4byte .LASF136
2870
- .byte 0x17
2871
- .2byte 0x148
2872
- .4byte 0x114
2873
- .byte 0x2b
2874
- .byte 0
2875
- .uleb128 0x20
2876
- .4byte .LASF137
2877
- .byte 0x17
2878
- .2byte 0x149
2879
- .4byte 0x812
2880
- .uleb128 0x22
2881
- .4byte .LASF138
2882
- .2byte 0x280
2883
- .byte 0x17
2884
- .2byte 0x14f
2885
- .4byte 0xa3d
2886
- .uleb128 0x1f
2887
- .4byte .LASF139
2888
- .byte 0x17
2889
- .2byte 0x155
2890
- .4byte 0xa3d
2891
- .byte 0
2892
- .uleb128 0x1f
2893
- .4byte .LASF140
2894
- .byte 0x17
2895
- .2byte 0x156
2896
- .4byte 0x806
2897
- .byte 0x8
2898
- .uleb128 0x1f
2899
- .4byte .LASF141
2900
- .byte 0x17
2901
- .2byte 0x157
2902
- .4byte 0x109
2903
- .byte 0x48
2904
- .uleb128 0x1f
2905
- .4byte .LASF142
2906
- .byte 0x17
2907
- .2byte 0x15a
2908
- .4byte 0xd5
2909
- .byte 0x50
2910
- .uleb128 0x1f
2911
- .4byte .LASF143
2912
- .byte 0x17
2913
- .2byte 0x15c
2914
- .4byte 0x135
2915
- .byte 0x58
2916
- .uleb128 0x1f
2917
- .4byte .LASF144
2918
- .byte 0x17
2919
- .2byte 0x15d
2920
- .4byte 0xd5
2921
- .byte 0x60
2922
- .uleb128 0x1f
2923
- .4byte .LASF145
2924
- .byte 0x17
2925
- .2byte 0x15e
2926
- .4byte 0x59
2927
- .byte 0x68
2928
- .uleb128 0x1f
2929
- .4byte .LASF146
2930
- .byte 0x17
2931
- .2byte 0x160
2932
- .4byte 0x135
2933
- .byte 0x70
2934
- .uleb128 0x1f
2935
- .4byte .LASF147
2936
- .byte 0x17
2937
- .2byte 0x161
2938
- .4byte 0xd5
2939
- .byte 0x78
2940
- .uleb128 0x1f
2941
- .4byte .LASF148
2942
- .byte 0x17
2943
- .2byte 0x162
2944
- .4byte 0x59
2945
- .byte 0x80
2946
- .uleb128 0x1f
2947
- .4byte .LASF149
2948
- .byte 0x17
2949
- .2byte 0x164
2950
- .4byte 0x135
2951
- .byte 0x88
2952
- .uleb128 0x1f
2953
- .4byte .LASF150
2954
- .byte 0x17
2955
- .2byte 0x165
2956
- .4byte 0xd5
2957
- .byte 0x90
2958
- .uleb128 0x1f
2959
- .4byte .LASF151
2960
- .byte 0x17
2961
- .2byte 0x166
2962
- .4byte 0x59
2963
- .byte 0x98
2964
- .uleb128 0x1f
2965
- .4byte .LASF152
2966
- .byte 0x17
2967
- .2byte 0x168
2968
- .4byte 0x135
2969
- .byte 0xa0
2970
- .uleb128 0x1f
2971
- .4byte .LASF153
2972
- .byte 0x17
2973
- .2byte 0x169
2974
- .4byte 0xd5
2975
- .byte 0xa8
2976
- .uleb128 0x1f
2977
- .4byte .LASF154
2978
- .byte 0x17
2979
- .2byte 0x16a
2980
- .4byte 0x59
2981
- .byte 0xb0
2982
- .uleb128 0x21
2983
- .string "os"
2984
- .byte 0x17
2985
- .2byte 0x16e
2986
- .4byte 0x894
2987
- .byte 0xb8
2988
- .uleb128 0x21
2989
- .string "ep"
2990
- .byte 0x17
2991
- .2byte 0x16f
2992
- .4byte 0x109
2993
- .byte 0xe8
2994
- .uleb128 0x1f
2995
- .4byte .LASF155
2996
- .byte 0x17
2997
- .2byte 0x171
2998
- .4byte 0x109
2999
- .byte 0xf0
3000
- .uleb128 0x1f
3001
- .4byte .LASF156
3002
- .byte 0x17
3003
- .2byte 0x171
3004
- .4byte 0x109
3005
- .byte 0xf8
3006
- .uleb128 0x23
3007
- .4byte .LASF157
3008
- .byte 0x17
3009
- .2byte 0x173
3010
- .4byte 0xf3
3011
- .2byte 0x100
3012
- .uleb128 0x23
3013
- .4byte .LASF158
3014
- .byte 0x17
3015
- .2byte 0x174
3016
- .4byte 0x109
3017
- .2byte 0x108
3018
- .uleb128 0x23
3019
- .4byte .LASF159
3020
- .byte 0x17
3021
- .2byte 0x176
3022
- .4byte 0x109
3023
- .2byte 0x110
3024
- .uleb128 0x23
3025
- .4byte .LASF160
3026
- .byte 0x17
3027
- .2byte 0x177
3028
- .4byte 0x109
3029
- .2byte 0x118
3030
- .uleb128 0x23
3031
- .4byte .LASF161
3032
- .byte 0x17
3033
- .2byte 0x178
3034
- .4byte 0x109
3035
- .2byte 0x120
3036
- .uleb128 0x23
3037
- .4byte .LASF162
3038
- .byte 0x17
3039
- .2byte 0x179
3040
- .4byte 0x109
3041
- .2byte 0x128
3042
- .uleb128 0x24
3043
- .string "kbd"
3044
- .byte 0x17
3045
- .2byte 0x17a
3046
- .4byte 0xa43
3047
- .2byte 0x130
3048
- .uleb128 0x23
3049
- .4byte .LASF163
3050
- .byte 0x17
3051
- .2byte 0x17d
3052
- .4byte 0x59
3053
- .2byte 0x138
3054
- .uleb128 0x23
3055
- .4byte .LASF164
3056
- .byte 0x17
3057
- .2byte 0x18a
3058
- .4byte 0x59
3059
- .2byte 0x13c
3060
- .uleb128 0x24
3061
- .string "lmb"
3062
- .byte 0x17
3063
- .2byte 0x18d
3064
- .4byte 0x411
3065
- .2byte 0x140
3066
- .byte 0
3067
- .uleb128 0x9
3068
- .byte 0x8
3069
- .4byte 0x806
3070
- .uleb128 0x9
3071
- .byte 0x8
3072
- .4byte 0x564
3073
- .uleb128 0x20
3074
- .4byte .LASF165
3075
- .byte 0x17
3076
- .2byte 0x18f
3077
- .4byte 0x8a0
3078
- .uleb128 0xd
3079
- .4byte .LASF166
3080
- .byte 0x17
3081
- .2byte 0x191
3082
- .4byte 0xa49
3083
- .uleb128 0x1b
3084
- .4byte .LASF168
3085
- .byte 0x4
3086
- .4byte 0x59
3087
- .byte 0x18
3088
- .byte 0xe
3089
- .4byte 0xc7c
3090
- .uleb128 0x1c
3091
- .4byte .LASF169
3092
- .byte 0
3093
- .uleb128 0x1c
3094
- .4byte .LASF170
3095
- .byte 0x1
3096
- .uleb128 0x1c
3097
- .4byte .LASF171
3098
- .byte 0x2
3099
- .uleb128 0x1c
3100
- .4byte .LASF172
3101
- .byte 0x3
3102
- .uleb128 0x1c
3103
- .4byte .LASF173
3104
- .byte 0x4
3105
- .uleb128 0x1c
3106
- .4byte .LASF174
3107
- .byte 0x5
3108
- .uleb128 0x1c
3109
- .4byte .LASF175
3110
- .byte 0x6
3111
- .uleb128 0x1c
3112
- .4byte .LASF176
3113
- .byte 0x7
3114
- .uleb128 0x1c
3115
- .4byte .LASF177
3116
- .byte 0x8
3117
- .uleb128 0x1c
3118
- .4byte .LASF178
3119
- .byte 0x9
3120
- .uleb128 0x1c
3121
- .4byte .LASF179
3122
- .byte 0xa
3123
- .uleb128 0x1c
3124
- .4byte .LASF180
3125
- .byte 0xb
3126
- .uleb128 0x1c
3127
- .4byte .LASF181
3128
- .byte 0xc
3129
- .uleb128 0x1c
3130
- .4byte .LASF182
3131
- .byte 0xd
3132
- .uleb128 0x1c
3133
- .4byte .LASF183
3134
- .byte 0xe
3135
- .uleb128 0x1c
3136
- .4byte .LASF184
3137
- .byte 0xf
3138
- .uleb128 0x1c
3139
- .4byte .LASF185
3140
- .byte 0x10
3141
- .uleb128 0x1c
3142
- .4byte .LASF186
3143
- .byte 0x11
3144
- .uleb128 0x1c
3145
- .4byte .LASF187
3146
- .byte 0x12
3147
- .uleb128 0x1c
3148
- .4byte .LASF188
3149
- .byte 0x13
3150
- .uleb128 0x1c
3151
- .4byte .LASF189
3152
- .byte 0x14
3153
- .uleb128 0x1c
3154
- .4byte .LASF190
3155
- .byte 0x15
3156
- .uleb128 0x1c
3157
- .4byte .LASF191
3158
- .byte 0x16
3159
- .uleb128 0x1c
3160
- .4byte .LASF192
3161
- .byte 0x17
3162
- .uleb128 0x1c
3163
- .4byte .LASF193
3164
- .byte 0x18
3165
- .uleb128 0x1c
3166
- .4byte .LASF194
3167
- .byte 0x19
3168
- .uleb128 0x1c
3169
- .4byte .LASF195
3170
- .byte 0x1a
3171
- .uleb128 0x1c
3172
- .4byte .LASF196
3173
- .byte 0x1b
3174
- .uleb128 0x1c
3175
- .4byte .LASF197
3176
- .byte 0x1c
3177
- .uleb128 0x1c
3178
- .4byte .LASF198
3179
- .byte 0x1d
3180
- .uleb128 0x1c
3181
- .4byte .LASF199
3182
- .byte 0x1e
3183
- .uleb128 0x1c
3184
- .4byte .LASF200
3185
- .byte 0x1f
3186
- .uleb128 0x1c
3187
- .4byte .LASF201
3188
- .byte 0x20
3189
- .uleb128 0x1c
3190
- .4byte .LASF202
3191
- .byte 0x21
3192
- .uleb128 0x1c
3193
- .4byte .LASF203
3194
- .byte 0x22
3195
- .uleb128 0x1c
3196
- .4byte .LASF204
3197
- .byte 0x23
3198
- .uleb128 0x1c
3199
- .4byte .LASF205
3200
- .byte 0x24
3201
- .uleb128 0x1c
3202
- .4byte .LASF206
3203
- .byte 0x25
3204
- .uleb128 0x1c
3205
- .4byte .LASF207
3206
- .byte 0x26
3207
- .uleb128 0x1c
3208
- .4byte .LASF208
3209
- .byte 0x27
3210
- .uleb128 0x1c
3211
- .4byte .LASF209
3212
- .byte 0x28
3213
- .uleb128 0x1c
3214
- .4byte .LASF210
3215
- .byte 0x29
3216
- .uleb128 0x1c
3217
- .4byte .LASF211
3218
- .byte 0x2a
3219
- .uleb128 0x1c
3220
- .4byte .LASF212
3221
- .byte 0x2b
3222
- .uleb128 0x1c
3223
- .4byte .LASF213
3224
- .byte 0x2c
3225
- .uleb128 0x1c
3226
- .4byte .LASF214
3227
- .byte 0x2d
3228
- .uleb128 0x1c
3229
- .4byte .LASF215
3230
- .byte 0x2e
3231
- .uleb128 0x1c
3232
- .4byte .LASF216
3233
- .byte 0x2f
3234
- .uleb128 0x1c
3235
- .4byte .LASF217
3236
- .byte 0x30
3237
- .uleb128 0x1c
3238
- .4byte .LASF218
3239
- .byte 0x31
3240
- .uleb128 0x1c
3241
- .4byte .LASF219
3242
- .byte 0x32
3243
- .uleb128 0x1c
3244
- .4byte .LASF220
3245
- .byte 0x33
3246
- .uleb128 0x1c
3247
- .4byte .LASF221
3248
- .byte 0x34
3249
- .uleb128 0x1c
3250
- .4byte .LASF222
3251
- .byte 0x35
3252
- .uleb128 0x1c
3253
- .4byte .LASF223
3254
- .byte 0x36
3255
- .uleb128 0x1c
3256
- .4byte .LASF224
3257
- .byte 0x37
3258
- .uleb128 0x1c
3259
- .4byte .LASF225
3260
- .byte 0x38
3261
- .uleb128 0x1c
3262
- .4byte .LASF226
3263
- .byte 0x39
3264
- .uleb128 0x1c
3265
- .4byte .LASF227
3266
- .byte 0x3a
3267
- .uleb128 0x1c
3268
- .4byte .LASF228
3269
- .byte 0x3b
3270
- .uleb128 0x1c
3271
- .4byte .LASF229
3272
- .byte 0x3c
3273
- .uleb128 0x1c
3274
- .4byte .LASF230
3275
- .byte 0x3d
3276
- .uleb128 0x1c
3277
- .4byte .LASF231
3278
- .byte 0x3e
3279
- .uleb128 0x1c
3280
- .4byte .LASF232
3281
- .byte 0x3f
3282
- .uleb128 0x1c
3283
- .4byte .LASF233
3284
- .byte 0x40
3285
- .uleb128 0x1c
3286
- .4byte .LASF234
3287
- .byte 0x41
3288
- .uleb128 0x1c
3289
- .4byte .LASF235
3290
- .byte 0x42
3291
- .uleb128 0x1c
3292
- .4byte .LASF236
3293
- .byte 0x43
3294
- .uleb128 0x1c
3295
- .4byte .LASF237
3296
- .byte 0x44
3297
- .uleb128 0x1c
3298
- .4byte .LASF238
3299
- .byte 0x45
3300
- .uleb128 0x1c
3301
- .4byte .LASF239
3302
- .byte 0x46
3303
- .uleb128 0x1c
3304
- .4byte .LASF240
3305
- .byte 0x47
3306
- .uleb128 0x1c
3307
- .4byte .LASF241
3308
- .byte 0x48
3309
- .uleb128 0x1c
3310
- .4byte .LASF242
3311
- .byte 0x49
3312
- .uleb128 0x1c
3313
- .4byte .LASF243
3314
- .byte 0x4a
3315
- .uleb128 0x1c
3316
- .4byte .LASF244
3317
- .byte 0x4b
3318
- .uleb128 0x1c
3319
- .4byte .LASF245
3320
- .byte 0x4c
3321
- .uleb128 0x1c
3322
- .4byte .LASF246
3323
- .byte 0x4d
3324
- .uleb128 0x1c
3325
- .4byte .LASF247
3326
- .byte 0x4e
3327
- .uleb128 0x1c
3328
- .4byte .LASF248
3329
- .byte 0x4f
3330
- .uleb128 0x1c
3331
- .4byte .LASF249
3332
- .byte 0x50
3333
- .uleb128 0x1c
3334
- .4byte .LASF250
3335
- .byte 0x51
3336
- .uleb128 0x1c
3337
- .4byte .LASF251
3338
- .byte 0x52
3339
- .uleb128 0x1c
3340
- .4byte .LASF252
3341
- .byte 0x53
3342
- .uleb128 0x1c
3343
- .4byte .LASF253
3344
- .byte 0x54
3345
- .uleb128 0x1c
3346
- .4byte .LASF254
3347
- .byte 0x55
3348
- .uleb128 0x1d
3349
- .4byte .LASF255
3350
- .sleb128 -1
3351
- .byte 0
3352
- .uleb128 0x25
3353
- .byte 0x4
3354
- .4byte 0x84
3355
- .byte 0x24
3356
- .byte 0xe0
3357
- .4byte 0xc8f
3358
- .uleb128 0x1c
3359
- .4byte .LASF256
3360
- .byte 0x5
3361
- .byte 0
3362
- .uleb128 0xe
3363
- .4byte .LASF257
3364
- .byte 0x40
3365
- .byte 0x19
3366
- .byte 0xc
3367
- .4byte 0xd08
3368
- .uleb128 0xf
3369
- .4byte .LASF258
3370
- .byte 0x19
3371
- .byte 0x22
3372
- .4byte 0x3b
3373
- .byte 0
3374
- .uleb128 0x10
3375
- .string "tbu"
3376
- .byte 0x19
3377
- .byte 0x23
3378
- .4byte 0x84
3379
- .byte 0x8
3380
- .uleb128 0x10
3381
- .string "tbl"
3382
- .byte 0x19
3383
- .byte 0x24
3384
- .4byte 0x84
3385
- .byte 0xc
3386
- .uleb128 0xf
3387
- .4byte .LASF259
3388
- .byte 0x19
3389
- .byte 0x25
3390
- .4byte 0x3b
3391
- .byte 0x10
3392
- .uleb128 0xf
3393
- .4byte .LASF260
3394
- .byte 0x19
3395
- .byte 0x26
3396
- .4byte 0x92
3397
- .byte 0x18
3398
- .uleb128 0xf
3399
- .4byte .LASF261
3400
- .byte 0x19
3401
- .byte 0x28
3402
- .4byte 0x3b
3403
- .byte 0x20
3404
- .uleb128 0xf
3405
- .4byte .LASF262
3406
- .byte 0x19
3407
- .byte 0x29
3408
- .4byte 0x3b
3409
- .byte 0x28
3410
- .uleb128 0xf
3411
- .4byte .LASF263
3412
- .byte 0x19
3413
- .byte 0x2b
3414
- .4byte 0x3b
3415
- .byte 0x30
3416
- .uleb128 0xf
3417
- .4byte .LASF264
3418
- .byte 0x19
3419
- .byte 0x2c
3420
- .4byte 0x3b
3421
- .byte 0x38
3422
- .byte 0
3423
- .uleb128 0xe
3424
- .4byte .LASF265
3425
- .byte 0x18
3426
- .byte 0x1a
3427
- .byte 0x22
3428
- .4byte 0xd44
3429
- .uleb128 0xf
3430
- .4byte .LASF266
3431
- .byte 0x1a
3432
- .byte 0x23
3433
- .4byte 0xa8
3434
- .byte 0
3435
- .uleb128 0x10
3436
- .string "id"
3437
- .byte 0x1a
3438
- .byte 0x24
3439
- .4byte 0xa8
3440
- .byte 0x4
3441
- .uleb128 0xf
3442
- .4byte .LASF267
3443
- .byte 0x1a
3444
- .byte 0x25
3445
- .4byte 0xa8
3446
- .byte 0x8
3447
- .uleb128 0xf
3448
- .4byte .LASF268
3449
- .byte 0x1a
3450
- .byte 0x26
3451
- .4byte 0x109
3452
- .byte 0x10
3453
- .byte 0
3454
- .uleb128 0x26
3455
- .4byte .LASF269
3456
- .2byte 0x1a0
3457
- .byte 0x1a
3458
- .byte 0x29
3459
- .4byte 0xf3c
3460
- .uleb128 0x10
3461
- .string "bd"
3462
- .byte 0x1a
3463
- .byte 0x2a
3464
- .4byte 0xa43
3465
- .byte 0
3466
- .uleb128 0xf
3467
- .4byte .LASF42
3468
- .byte 0x1a
3469
- .byte 0x2b
3470
- .4byte 0x3b
3471
- .byte 0x8
3472
- .uleb128 0xf
3473
- .4byte .LASF267
3474
- .byte 0x1a
3475
- .byte 0x2c
3476
- .4byte 0x84
3477
- .byte 0x10
3478
- .uleb128 0xf
3479
- .4byte .LASF270
3480
- .byte 0x1a
3481
- .byte 0x2d
3482
- .4byte 0x3b
3483
- .byte 0x18
3484
- .uleb128 0xf
3485
- .4byte .LASF271
3486
- .byte 0x1a
3487
- .byte 0x2e
3488
- .4byte 0x3b
3489
- .byte 0x20
3490
- .uleb128 0xf
3491
- .4byte .LASF272
3492
- .byte 0x1a
3493
- .byte 0x30
3494
- .4byte 0x3b
3495
- .byte 0x28
3496
- .uleb128 0xf
3497
- .4byte .LASF273
3498
- .byte 0x1a
3499
- .byte 0x31
3500
- .4byte 0x3b
3501
- .byte 0x30
3502
- .uleb128 0xf
3503
- .4byte .LASF274
3504
- .byte 0x1a
3505
- .byte 0x33
3506
- .4byte 0x3b
3507
- .byte 0x38
3508
- .uleb128 0xf
3509
- .4byte .LASF275
3510
- .byte 0x1a
3511
- .byte 0x3d
3512
- .4byte 0x3b
3513
- .byte 0x40
3514
- .uleb128 0xf
3515
- .4byte .LASF276
3516
- .byte 0x1a
3517
- .byte 0x41
3518
- .4byte 0x3b
3519
- .byte 0x48
3520
- .uleb128 0xf
3521
- .4byte .LASF277
3522
- .byte 0x1a
3523
- .byte 0x42
3524
- .4byte 0x3b
3525
- .byte 0x50
3526
- .uleb128 0xf
3527
- .4byte .LASF278
3528
- .byte 0x1a
3529
- .byte 0x44
3530
- .4byte 0x3b
3531
- .byte 0x58
3532
- .uleb128 0xf
3533
- .4byte .LASF279
3534
- .byte 0x1a
3535
- .byte 0x45
3536
- .4byte 0x3b
3537
- .byte 0x60
3538
- .uleb128 0xf
3539
- .4byte .LASF280
3540
- .byte 0x1a
3541
- .byte 0x46
3542
- .4byte 0xc3
3543
- .byte 0x68
3544
- .uleb128 0xf
3545
- .4byte .LASF281
3546
- .byte 0x1a
3547
- .byte 0x47
3548
- .4byte 0x3b
3549
- .byte 0x70
3550
- .uleb128 0xf
3551
- .4byte .LASF282
3552
- .byte 0x1a
3553
- .byte 0x48
3554
- .4byte 0x3b
3555
- .byte 0x78
3556
- .uleb128 0xf
3557
- .4byte .LASF283
3558
- .byte 0x1a
3559
- .byte 0x49
3560
- .4byte 0x3b
3561
- .byte 0x80
3562
- .uleb128 0xf
3563
- .4byte .LASF284
3564
- .byte 0x1a
3565
- .byte 0x4a
3566
- .4byte 0x3b
3567
- .byte 0x88
3568
- .uleb128 0xf
3569
- .4byte .LASF285
3570
- .byte 0x1a
3571
- .byte 0x4b
3572
- .4byte 0xf3c
3573
- .byte 0x90
3574
- .uleb128 0xf
3575
- .4byte .LASF286
3576
- .byte 0x1a
3577
- .byte 0x4e
3578
- .4byte 0x25d
3579
- .byte 0x98
3580
- .uleb128 0xf
3581
- .4byte .LASF287
3582
- .byte 0x1a
3583
- .byte 0x4f
3584
- .4byte 0x25d
3585
- .byte 0xa0
3586
- .uleb128 0xf
3587
- .4byte .LASF288
3588
- .byte 0x1a
3589
- .byte 0x50
3590
- .4byte 0x290
3591
- .byte 0xa8
3592
- .uleb128 0xf
3593
- .4byte .LASF289
3594
- .byte 0x1a
3595
- .byte 0x56
3596
- .4byte 0x263
3597
- .byte 0xb8
3598
- .uleb128 0xf
3599
- .4byte .LASF290
3600
- .byte 0x1a
3601
- .byte 0x57
3602
- .4byte 0x135
3603
- .byte 0xc0
3604
- .uleb128 0xf
3605
- .4byte .LASF291
3606
- .byte 0x1a
3607
- .byte 0x58
3608
- .4byte 0x3b
3609
- .byte 0xc8
3610
- .uleb128 0xf
3611
- .4byte .LASF292
3612
- .byte 0x1a
3613
- .byte 0x5a
3614
- .4byte 0xfb4
3615
- .byte 0xd0
3616
- .uleb128 0x10
3617
- .string "jt"
3618
- .byte 0x1a
3619
- .byte 0x5c
3620
- .4byte 0xfbf
3621
- .byte 0xd8
3622
- .uleb128 0xf
3623
- .4byte .LASF293
3624
- .byte 0x1a
3625
- .byte 0x5d
3626
- .4byte 0xfc5
3627
- .byte 0xe0
3628
- .uleb128 0x16
3629
- .4byte .LASF294
3630
- .byte 0x1a
3631
- .byte 0x67
3632
- .4byte 0x84
3633
- .2byte 0x100
3634
- .uleb128 0x16
3635
- .4byte .LASF295
3636
- .byte 0x1a
3637
- .byte 0x68
3638
- .4byte 0x84
3639
- .2byte 0x104
3640
- .uleb128 0x16
3641
- .4byte .LASF296
3642
- .byte 0x1a
3643
- .byte 0x6a
3644
- .4byte 0x3b
3645
- .2byte 0x108
3646
- .uleb128 0x16
3647
- .4byte .LASF297
3648
- .byte 0x1a
3649
- .byte 0x6b
3650
- .4byte 0x3b
3651
- .2byte 0x110
3652
- .uleb128 0x16
3653
- .4byte .LASF298
3654
- .byte 0x1a
3655
- .byte 0x6c
3656
- .4byte 0x3b
3657
- .2byte 0x118
3658
- .uleb128 0x16
3659
- .4byte .LASF299
3660
- .byte 0x1a
3661
- .byte 0x75
3662
- .4byte 0x25d
3663
- .2byte 0x120
3664
- .uleb128 0x16
3665
- .4byte .LASF136
3666
- .byte 0x1a
3667
- .byte 0x76
3668
- .4byte 0xc8f
3669
- .2byte 0x128
3670
- .uleb128 0x16
3671
- .4byte .LASF300
3672
- .byte 0x1a
3673
- .byte 0x7c
3674
- .4byte 0x109
3675
- .2byte 0x168
3676
- .uleb128 0x16
3677
- .4byte .LASF301
3678
- .byte 0x1a
3679
- .byte 0x7d
3680
- .4byte 0x109
3681
- .2byte 0x170
3682
- .uleb128 0x16
3683
- .4byte .LASF302
3684
- .byte 0x1a
3685
- .byte 0x83
3686
- .4byte 0xb8
3687
- .2byte 0x178
3688
- .uleb128 0x16
3689
- .4byte .LASF303
3690
- .byte 0x1a
3691
- .byte 0x88
3692
- .4byte 0xd08
3693
- .2byte 0x180
3694
- .uleb128 0x16
3695
- .4byte .LASF304
3696
- .byte 0x1a
3697
- .byte 0x89
3698
- .4byte 0x109
3699
- .2byte 0x198
3700
- .byte 0
3701
- .uleb128 0x9
3702
- .byte 0x8
3703
- .4byte 0xd44
3704
- .uleb128 0xe
3705
- .4byte .LASF305
3706
- .byte 0x40
3707
- .byte 0x1b
3708
- .byte 0x2c
3709
- .4byte 0xfaf
3710
- .uleb128 0xf
3711
- .4byte .LASF28
3712
- .byte 0x1b
3713
- .byte 0x2d
3714
- .4byte 0xd5
3715
- .byte 0
3716
- .uleb128 0xf
3717
- .4byte .LASF135
3718
- .byte 0x1b
3719
- .byte 0x2e
3720
- .4byte 0xd5
3721
- .byte 0x8
3722
- .uleb128 0xf
3723
- .4byte .LASF306
3724
- .byte 0x1b
3725
- .byte 0x2f
3726
- .4byte 0x145c
3727
- .byte 0x10
3728
- .uleb128 0xf
3729
- .4byte .LASF307
3730
- .byte 0x1b
3731
- .byte 0x30
3732
- .4byte 0xd5
3733
- .byte 0x18
3734
- .uleb128 0xf
3735
- .4byte .LASF308
3736
- .byte 0x1b
3737
- .byte 0x32
3738
- .4byte 0x14a4
3739
- .byte 0x20
3740
- .uleb128 0xf
3741
- .4byte .LASF34
3742
- .byte 0x1b
3743
- .byte 0x33
3744
- .4byte 0xfb4
3745
- .byte 0x28
3746
- .uleb128 0xf
3747
- .4byte .LASF309
3748
- .byte 0x1b
3749
- .byte 0x34
3750
- .4byte 0xfb4
3751
- .byte 0x30
3752
- .uleb128 0xf
3753
- .4byte .LASF310
3754
- .byte 0x1b
3755
- .byte 0x35
3756
- .4byte 0xfb4
3757
- .byte 0x38
3758
- .byte 0
3759
- .uleb128 0x8
3760
- .4byte 0xf42
3761
- .uleb128 0x9
3762
- .byte 0x8
3763
- .4byte 0xf42
3764
- .uleb128 0x27
3765
- .4byte .LASF481
3766
- .uleb128 0x9
3767
- .byte 0x8
3768
- .4byte 0xfba
3769
- .uleb128 0xb
3770
- .4byte 0xe0
3771
- .4byte 0xfd5
3772
- .uleb128 0x12
3773
- .4byte 0xce
3774
- .byte 0x1f
3775
- .byte 0
3776
- .uleb128 0x2
3777
- .4byte .LASF311
3778
- .byte 0x1a
3779
- .byte 0x8f
3780
- .4byte 0xd44
3781
- .uleb128 0x4
3782
- .4byte 0xfd5
3783
- .uleb128 0x5
3784
- .4byte .LASF312
3785
- .byte 0x5
3786
- .byte 0xab
3787
- .4byte 0x109
3788
- .uleb128 0xb
3789
- .4byte 0x99
3790
- .4byte 0xffb
3791
- .uleb128 0xc
3792
- .byte 0
3793
- .uleb128 0x5
3794
- .4byte .LASF313
3795
- .byte 0x5
3796
- .byte 0xad
3797
- .4byte 0xff0
3798
- .uleb128 0x5
3799
- .4byte .LASF314
3800
- .byte 0x5
3801
- .byte 0xae
3802
- .4byte 0xff0
3803
- .uleb128 0x5
3804
- .4byte .LASF315
3805
- .byte 0x5
3806
- .byte 0xfc
3807
- .4byte 0x109
3808
- .uleb128 0x5
3809
- .4byte .LASF316
3810
- .byte 0x5
3811
- .byte 0xfd
3812
- .4byte 0x109
3813
- .uleb128 0x5
3814
- .4byte .LASF317
3815
- .byte 0x5
3816
- .byte 0xfe
3817
- .4byte 0x109
3818
- .uleb128 0xe
3819
- .4byte .LASF318
3820
- .byte 0x4
3821
- .byte 0x1c
3822
- .byte 0x2e
3823
- .4byte 0x104b
3824
- .uleb128 0xf
3825
- .4byte .LASF319
3826
- .byte 0x1c
3827
- .byte 0x2f
3828
- .4byte 0x12a
3829
- .byte 0
3830
- .byte 0
3831
- .uleb128 0x9
3832
- .byte 0x8
3833
- .4byte 0x29
3834
- .uleb128 0xe
3835
- .4byte .LASF320
3836
- .byte 0x68
3837
- .byte 0x1c
3838
- .byte 0xa6
3839
- .4byte 0x10ee
3840
- .uleb128 0xf
3841
- .4byte .LASF28
3842
- .byte 0x1c
3843
- .byte 0xa8
3844
- .4byte 0x10ee
3845
- .byte 0
3846
- .uleb128 0xf
3847
- .4byte .LASF321
3848
- .byte 0x1c
3849
- .byte 0xa9
3850
- .4byte 0x280
3851
- .byte 0x10
3852
- .uleb128 0xf
3853
- .4byte .LASF322
3854
- .byte 0x1c
3855
- .byte 0xaa
3856
- .4byte 0xb8
3857
- .byte 0x18
3858
- .uleb128 0xf
3859
- .4byte .LASF164
3860
- .byte 0x1c
3861
- .byte 0xab
3862
- .4byte 0x59
3863
- .byte 0x20
3864
- .uleb128 0xf
3865
- .4byte .LASF323
3866
- .byte 0x1c
3867
- .byte 0xad
3868
- .4byte 0x1118
3869
- .byte 0x28
3870
- .uleb128 0xf
3871
- .4byte .LASF324
3872
- .byte 0x1c
3873
- .byte 0xae
3874
- .4byte 0x1137
3875
- .byte 0x30
3876
- .uleb128 0xf
3877
- .4byte .LASF325
3878
- .byte 0x1c
3879
- .byte 0xaf
3880
- .4byte 0x114c
3881
- .byte 0x38
3882
- .uleb128 0xf
3883
- .4byte .LASF326
3884
- .byte 0x1c
3885
- .byte 0xb0
3886
- .4byte 0x115d
3887
- .byte 0x40
3888
- .uleb128 0xf
3889
- .4byte .LASF327
3890
- .byte 0x1c
3891
- .byte 0xb4
3892
- .4byte 0x114c
3893
- .byte 0x48
3894
- .uleb128 0xf
3895
- .4byte .LASF47
3896
- .byte 0x1c
3897
- .byte 0xb5
3898
- .4byte 0x1112
3899
- .byte 0x50
3900
- .uleb128 0xf
3901
- .4byte .LASF328
3902
- .byte 0x1c
3903
- .byte 0xb6
3904
- .4byte 0x59
3905
- .byte 0x58
3906
- .uleb128 0xf
3907
- .4byte .LASF35
3908
- .byte 0x1c
3909
- .byte 0xb7
3910
- .4byte 0x135
3911
- .byte 0x60
3912
- .byte 0
3913
- .uleb128 0xb
3914
- .4byte 0xe0
3915
- .4byte 0x10fe
3916
- .uleb128 0x12
3917
- .4byte 0xce
3918
- .byte 0xf
3919
- .byte 0
3920
- .uleb128 0x13
3921
- .4byte 0x59
3922
- .4byte 0x1112
3923
- .uleb128 0x14
3924
- .4byte 0x1112
3925
- .uleb128 0x14
3926
- .4byte 0xa43
3927
- .byte 0
3928
- .uleb128 0x9
3929
- .byte 0x8
3930
- .4byte 0x1051
3931
- .uleb128 0x9
3932
- .byte 0x8
3933
- .4byte 0x10fe
3934
- .uleb128 0x13
3935
- .4byte 0x59
3936
- .4byte 0x1137
3937
- .uleb128 0x14
3938
- .4byte 0x1112
3939
- .uleb128 0x14
3940
- .4byte 0x135
3941
- .uleb128 0x14
3942
- .4byte 0x59
3943
- .byte 0
3944
- .uleb128 0x9
3945
- .byte 0x8
3946
- .4byte 0x111e
3947
- .uleb128 0x13
3948
- .4byte 0x59
3949
- .4byte 0x114c
3950
- .uleb128 0x14
3951
- .4byte 0x1112
3952
- .byte 0
3953
- .uleb128 0x9
3954
- .byte 0x8
3955
- .4byte 0x113d
3956
- .uleb128 0x28
3957
- .4byte 0x115d
3958
- .uleb128 0x14
3959
- .4byte 0x1112
3960
- .byte 0
3961
- .uleb128 0x9
3962
- .byte 0x8
3963
- .4byte 0x1152
3964
- .uleb128 0x5
3965
- .4byte .LASF329
3966
- .byte 0x1c
3967
- .byte 0xbd
3968
- .4byte 0x1112
3969
- .uleb128 0x28
3970
- .4byte 0x117e
3971
- .uleb128 0x14
3972
- .4byte 0x135
3973
- .uleb128 0x14
3974
- .4byte 0x59
3975
- .byte 0
3976
- .uleb128 0xd
3977
- .4byte .LASF330
3978
- .byte 0x1c
3979
- .2byte 0x11e
3980
- .4byte 0x118a
3981
- .uleb128 0x9
3982
- .byte 0x8
3983
- .4byte 0x116e
3984
- .uleb128 0xb
3985
- .4byte 0x99
3986
- .4byte 0x11a0
3987
- .uleb128 0x12
3988
- .4byte 0xce
3989
- .byte 0x5
3990
- .byte 0
3991
- .uleb128 0xd
3992
- .4byte .LASF331
3993
- .byte 0x1c
3994
- .2byte 0x1fd
3995
- .4byte 0x1032
3996
- .uleb128 0xd
3997
- .4byte .LASF332
3998
- .byte 0x1c
3999
- .2byte 0x1fe
4000
- .4byte 0x1032
4001
- .uleb128 0xd
4002
- .4byte .LASF333
4003
- .byte 0x1c
4004
- .2byte 0x200
4005
- .4byte 0x1032
4006
- .uleb128 0xd
4007
- .4byte .LASF334
4008
- .byte 0x1c
4009
- .2byte 0x205
4010
- .4byte 0xfc5
4011
- .uleb128 0xd
4012
- .4byte .LASF335
4013
- .byte 0x1c
4014
- .2byte 0x206
4015
- .4byte 0xfc5
4016
- .uleb128 0xb
4017
- .4byte 0xe0
4018
- .4byte 0x11ec
4019
- .uleb128 0x12
4020
- .4byte 0xce
4021
- .byte 0x3f
4022
- .byte 0
4023
- .uleb128 0xd
4024
- .4byte .LASF336
4025
- .byte 0x1c
4026
- .2byte 0x207
4027
- .4byte 0x11dc
4028
- .uleb128 0xd
4029
- .4byte .LASF337
4030
- .byte 0x1c
4031
- .2byte 0x209
4032
- .4byte 0x1190
4033
- .uleb128 0xd
4034
- .4byte .LASF338
4035
- .byte 0x1c
4036
- .2byte 0x20a
4037
- .4byte 0x1190
4038
- .uleb128 0xd
4039
- .4byte .LASF339
4040
- .byte 0x1c
4041
- .2byte 0x20b
4042
- .4byte 0x1032
4043
- .uleb128 0xd
4044
- .4byte .LASF340
4045
- .byte 0x1c
4046
- .2byte 0x20c
4047
- .4byte 0x1032
4048
- .uleb128 0xd
4049
- .4byte .LASF341
4050
- .byte 0x1c
4051
- .2byte 0x20d
4052
- .4byte 0x104b
4053
- .uleb128 0xb
4054
- .4byte 0x104b
4055
- .4byte 0x1244
4056
- .uleb128 0x12
4057
- .4byte 0xce
4058
- .byte 0x3
4059
- .byte 0
4060
- .uleb128 0xd
4061
- .4byte .LASF342
4062
- .byte 0x1c
4063
- .2byte 0x20e
4064
- .4byte 0x1234
4065
- .uleb128 0xd
4066
- .4byte .LASF343
4067
- .byte 0x1c
4068
- .2byte 0x20f
4069
- .4byte 0x104b
4070
- .uleb128 0xd
4071
- .4byte .LASF344
4072
- .byte 0x1c
4073
- .2byte 0x210
4074
- .4byte 0x59
4075
- .uleb128 0xb
4076
- .4byte 0xa3
4077
- .4byte 0x1278
4078
- .uleb128 0x12
4079
- .4byte 0xce
4080
- .byte 0x5
4081
- .byte 0
4082
- .uleb128 0x8
4083
- .4byte 0x1268
4084
- .uleb128 0xd
4085
- .4byte .LASF345
4086
- .byte 0x1c
4087
- .2byte 0x211
4088
- .4byte 0x1278
4089
- .uleb128 0xd
4090
- .4byte .LASF346
4091
- .byte 0x1c
4092
- .2byte 0x212
4093
- .4byte 0x1278
4094
- .uleb128 0xd
4095
- .4byte .LASF347
4096
- .byte 0x1c
4097
- .2byte 0x216
4098
- .4byte 0xfe
4099
- .uleb128 0xd
4100
- .4byte .LASF348
4101
- .byte 0x1c
4102
- .2byte 0x217
4103
- .4byte 0xfe
4104
- .uleb128 0xd
4105
- .4byte .LASF349
4106
- .byte 0x1c
4107
- .2byte 0x219
4108
- .4byte 0x59
4109
- .uleb128 0xb
4110
- .4byte 0xe0
4111
- .4byte 0x12ca
4112
- .uleb128 0x17
4113
- .4byte 0xce
4114
- .2byte 0x3ff
4115
- .byte 0
4116
- .uleb128 0xd
4117
- .4byte .LASF350
4118
- .byte 0x1c
4119
- .2byte 0x220
4120
- .4byte 0x12b9
4121
- .uleb128 0xd
4122
- .4byte .LASF351
4123
- .byte 0x1c
4124
- .2byte 0x222
4125
- .4byte 0xa8
4126
- .uleb128 0xd
4127
- .4byte .LASF352
4128
- .byte 0x1c
4129
- .2byte 0x224
4130
- .4byte 0xa8
4131
- .uleb128 0xd
4132
- .4byte .LASF353
4133
- .byte 0x1c
4134
- .2byte 0x230
4135
- .4byte 0x1032
4136
- .uleb128 0x29
4137
- .4byte .LASF354
4138
- .byte 0x4
4139
- .4byte 0x84
4140
- .byte 0x1c
4141
- .2byte 0x286
4142
- .4byte 0x1324
4143
- .uleb128 0x1c
4144
- .4byte .LASF355
4145
- .byte 0
4146
- .uleb128 0x1c
4147
- .4byte .LASF356
4148
- .byte 0x1
4149
- .uleb128 0x1c
4150
- .4byte .LASF357
4151
- .byte 0x2
4152
- .uleb128 0x1c
4153
- .4byte .LASF358
4154
- .byte 0x3
4155
- .byte 0
4156
- .uleb128 0xd
4157
- .4byte .LASF359
4158
- .byte 0x1c
4159
- .2byte 0x28c
4160
- .4byte 0x12fa
4161
- .uleb128 0xd
4162
- .4byte .LASF360
4163
- .byte 0x1d
4164
- .2byte 0x3ba
4165
- .4byte 0x109
4166
- .uleb128 0xd
4167
- .4byte .LASF361
4168
- .byte 0x1d
4169
- .2byte 0x3bb
4170
- .4byte 0x109
4171
- .uleb128 0xd
4172
- .4byte .LASF362
4173
- .byte 0x1d
4174
- .2byte 0x3bc
4175
- .4byte 0x109
4176
- .uleb128 0xb
4177
- .4byte 0xa8
4178
- .4byte 0x1364
4179
- .uleb128 0x12
4180
- .4byte 0xce
4181
- .byte 0x1f
4182
- .byte 0
4183
- .uleb128 0x2a
4184
- .4byte .LASF379
4185
- .byte 0x1
4186
- .byte 0xa
4187
- .4byte 0x1354
4188
- .uleb128 0x9
4189
- .byte 0x3
4190
- .8byte g_isi_pattern
4191
- .uleb128 0x9
4192
- .byte 0x8
4193
- .4byte 0xa8
4194
- .uleb128 0xe
4195
- .4byte .LASF27
4196
- .byte 0x78
4197
- .byte 0xb
4198
- .byte 0xee
4199
- .4byte 0x1457
4200
- .uleb128 0xf
4201
- .4byte .LASF28
4202
- .byte 0xb
4203
- .byte 0xef
4204
- .4byte 0xf3
4205
- .byte 0
4206
- .uleb128 0x10
4207
- .string "id"
4208
- .byte 0xb
4209
- .byte 0xf0
4210
- .4byte 0xa61
4211
- .byte 0x8
4212
- .uleb128 0xf
4213
- .4byte .LASF363
4214
- .byte 0xb
4215
- .byte 0xf1
4216
- .4byte 0x158a
4217
- .byte 0x10
4218
- .uleb128 0xf
4219
- .4byte .LASF364
4220
- .byte 0xb
4221
- .byte 0xf2
4222
- .4byte 0x159f
4223
- .byte 0x18
4224
- .uleb128 0xf
4225
- .4byte .LASF365
4226
- .byte 0xb
4227
- .byte 0xf3
4228
- .4byte 0x159f
4229
- .byte 0x20
4230
- .uleb128 0xf
4231
- .4byte .LASF366
4232
- .byte 0xb
4233
- .byte 0xf4
4234
- .4byte 0x159f
4235
- .byte 0x28
4236
- .uleb128 0xf
4237
- .4byte .LASF367
4238
- .byte 0xb
4239
- .byte 0xf5
4240
- .4byte 0x159f
4241
- .byte 0x30
4242
- .uleb128 0xf
4243
- .4byte .LASF368
4244
- .byte 0xb
4245
- .byte 0xf6
4246
- .4byte 0x159f
4247
- .byte 0x38
4248
- .uleb128 0xf
4249
- .4byte .LASF369
4250
- .byte 0xb
4251
- .byte 0xf7
4252
- .4byte 0x159f
4253
- .byte 0x40
4254
- .uleb128 0xf
4255
- .4byte .LASF370
4256
- .byte 0xb
4257
- .byte 0xf8
4258
- .4byte 0x159f
4259
- .byte 0x48
4260
- .uleb128 0xf
4261
- .4byte .LASF371
4262
- .byte 0xb
4263
- .byte 0xf9
4264
- .4byte 0x159f
4265
- .byte 0x50
4266
- .uleb128 0xf
4267
- .4byte .LASF372
4268
- .byte 0xb
4269
- .byte 0xfa
4270
- .4byte 0x59
4271
- .byte 0x58
4272
- .uleb128 0xf
4273
- .4byte .LASF373
4274
- .byte 0xb
4275
- .byte 0xfb
4276
- .4byte 0x59
4277
- .byte 0x5c
4278
- .uleb128 0xf
4279
- .4byte .LASF374
4280
- .byte 0xb
4281
- .byte 0xfc
4282
- .4byte 0x59
4283
- .byte 0x60
4284
- .uleb128 0xf
4285
- .4byte .LASF375
4286
- .byte 0xb
4287
- .byte 0xfd
4288
- .4byte 0x59
4289
- .byte 0x64
4290
- .uleb128 0x10
4291
- .string "ops"
4292
- .byte 0xb
4293
- .byte 0xfe
4294
- .4byte 0x263
4295
- .byte 0x68
4296
- .uleb128 0xf
4297
- .4byte .LASF42
4298
- .byte 0xb
4299
- .byte 0xff
4300
- .4byte 0x11f
4301
- .byte 0x70
4302
- .byte 0
4303
- .uleb128 0x8
4304
- .4byte 0x137f
4305
- .uleb128 0x2
4306
- .4byte .LASF306
4307
- .byte 0x1b
4308
- .byte 0xf
4309
- .4byte 0xa8
4310
- .uleb128 0xe
4311
- .4byte .LASF376
4312
- .byte 0x20
4313
- .byte 0x1b
4314
- .byte 0x19
4315
- .4byte 0x14a4
4316
- .uleb128 0xf
4317
- .4byte .LASF28
4318
- .byte 0x1b
4319
- .byte 0x1a
4320
- .4byte 0xf3
4321
- .byte 0
4322
- .uleb128 0xf
4323
- .4byte .LASF377
4324
- .byte 0x1b
4325
- .byte 0x1b
4326
- .4byte 0x59
4327
- .byte 0x8
4328
- .uleb128 0xf
4329
- .4byte .LASF378
4330
- .byte 0x1b
4331
- .byte 0x1c
4332
- .4byte 0x135
4333
- .byte 0x10
4334
- .uleb128 0xf
4335
- .4byte .LASF47
4336
- .byte 0x1b
4337
- .byte 0x1d
4338
- .4byte 0x14a4
4339
- .byte 0x18
4340
- .byte 0
4341
- .uleb128 0x9
4342
- .byte 0x8
4343
- .4byte 0x1467
4344
- .uleb128 0x2b
4345
- .string "gd"
4346
- .byte 0x1b
4347
- .byte 0x57
4348
- .4byte 0x14b4
4349
- .uleb128 0x9
4350
- .byte 0x8
4351
- .4byte 0xfe0
4352
- .uleb128 0x2c
4353
- .4byte .LASF482
4354
- .byte 0x8
4355
- .byte 0x1e
4356
- .byte 0x33
4357
- .4byte 0x14dc
4358
- .uleb128 0x2d
4359
- .string "np"
4360
- .byte 0x1e
4361
- .byte 0x34
4362
- .4byte 0x14dc
4363
- .uleb128 0x2e
4364
- .4byte .LASF380
4365
- .byte 0x1e
4366
- .byte 0x35
4367
- .4byte 0xec
4368
- .byte 0
4369
- .uleb128 0x9
4370
- .byte 0x8
4371
- .4byte 0xfaf
4372
- .uleb128 0x2
4373
- .4byte .LASF381
4374
- .byte 0x1e
4375
- .byte 0x36
4376
- .4byte 0x14ba
4377
- .uleb128 0xe
4378
- .4byte .LASF382
4379
- .byte 0x4
4380
- .byte 0x1f
4381
- .byte 0xc
4382
- .4byte 0x1506
4383
- .uleb128 0x10
4384
- .string "pid"
4385
- .byte 0x1f
4386
- .byte 0xd
4387
- .4byte 0x59
4388
- .byte 0
4389
- .byte 0
4390
- .uleb128 0x5
4391
- .4byte .LASF383
4392
- .byte 0x1f
4393
- .byte 0x10
4394
- .4byte 0x1511
4395
- .uleb128 0x9
4396
- .byte 0x8
4397
- .4byte 0x14ed
4398
- .uleb128 0x9
4399
- .byte 0x8
4400
- .4byte 0x1457
4401
- .uleb128 0xe
4402
- .4byte .LASF36
4403
- .byte 0x30
4404
- .byte 0x20
4405
- .byte 0x23
4406
- .4byte 0x155a
4407
- .uleb128 0xf
4408
- .4byte .LASF35
4409
- .byte 0x20
4410
- .byte 0x24
4411
- .4byte 0x135
4412
- .byte 0
4413
- .uleb128 0xf
4414
- .4byte .LASF384
4415
- .byte 0x20
4416
- .byte 0x25
4417
- .4byte 0x1689
4418
- .byte 0x8
4419
- .uleb128 0xf
4420
- .4byte .LASF385
4421
- .byte 0x20
4422
- .byte 0x26
4423
- .4byte 0x290
4424
- .byte 0x10
4425
- .uleb128 0xf
4426
- .4byte .LASF41
4427
- .byte 0x20
4428
- .byte 0x27
4429
- .4byte 0x290
4430
- .byte 0x20
4431
- .byte 0
4432
- .uleb128 0x9
4433
- .byte 0x8
4434
- .4byte 0x151d
4435
- .uleb128 0xe
4436
- .4byte .LASF386
4437
- .byte 0x10
4438
- .byte 0xb
4439
- .byte 0xb5
4440
- .4byte 0x1585
4441
- .uleb128 0xf
4442
- .4byte .LASF387
4443
- .byte 0xb
4444
- .byte 0xb6
4445
- .4byte 0xd5
4446
- .byte 0
4447
- .uleb128 0xf
4448
- .4byte .LASF388
4449
- .byte 0xb
4450
- .byte 0xb7
4451
- .4byte 0x109
4452
- .byte 0x8
4453
- .byte 0
4454
- .uleb128 0x8
4455
- .4byte 0x1560
4456
- .uleb128 0x9
4457
- .byte 0x8
4458
- .4byte 0x1585
4459
- .uleb128 0x13
4460
- .4byte 0x59
4461
- .4byte 0x159f
4462
- .uleb128 0x14
4463
- .4byte 0x25d
4464
- .byte 0
4465
- .uleb128 0x9
4466
- .byte 0x8
4467
- .4byte 0x1590
4468
- .uleb128 0xe
4469
- .4byte .LASF389
4470
- .byte 0x80
4471
- .byte 0x20
4472
- .byte 0x54
4473
- .4byte 0x1689
4474
- .uleb128 0xf
4475
- .4byte .LASF28
4476
- .byte 0x20
4477
- .byte 0x55
4478
- .4byte 0xd5
4479
- .byte 0
4480
- .uleb128 0x10
4481
- .string "id"
4482
- .byte 0x20
4483
- .byte 0x56
4484
- .4byte 0xa61
4485
- .byte 0x8
4486
- .uleb128 0xf
4487
- .4byte .LASF390
4488
- .byte 0x20
4489
- .byte 0x57
4490
- .4byte 0x159f
4491
- .byte 0x10
4492
- .uleb128 0xf
4493
- .4byte .LASF391
4494
- .byte 0x20
4495
- .byte 0x58
4496
- .4byte 0x159f
4497
- .byte 0x18
4498
- .uleb128 0xf
4499
- .4byte .LASF392
4500
- .byte 0x20
4501
- .byte 0x59
4502
- .4byte 0x159f
4503
- .byte 0x20
4504
- .uleb128 0xf
4505
- .4byte .LASF393
4506
- .byte 0x20
4507
- .byte 0x5a
4508
- .4byte 0x159f
4509
- .byte 0x28
4510
- .uleb128 0xf
4511
- .4byte .LASF394
4512
- .byte 0x20
4513
- .byte 0x5b
4514
- .4byte 0x159f
4515
- .byte 0x30
4516
- .uleb128 0xf
4517
- .4byte .LASF369
4518
- .byte 0x20
4519
- .byte 0x5c
4520
- .4byte 0x159f
4521
- .byte 0x38
4522
- .uleb128 0xf
4523
- .4byte .LASF370
4524
- .byte 0x20
4525
- .byte 0x5d
4526
- .4byte 0x159f
4527
- .byte 0x40
4528
- .uleb128 0xf
4529
- .4byte .LASF323
4530
- .byte 0x20
4531
- .byte 0x5e
4532
- .4byte 0x169e
4533
- .byte 0x48
4534
- .uleb128 0xf
4535
- .4byte .LASF395
4536
- .byte 0x20
4537
- .byte 0x5f
4538
- .4byte 0x169e
4539
- .byte 0x50
4540
- .uleb128 0xf
4541
- .4byte .LASF372
4542
- .byte 0x20
4543
- .byte 0x60
4544
- .4byte 0x59
4545
- .byte 0x58
4546
- .uleb128 0xf
4547
- .4byte .LASF396
4548
- .byte 0x20
4549
- .byte 0x61
4550
- .4byte 0x59
4551
- .byte 0x5c
4552
- .uleb128 0xf
4553
- .4byte .LASF397
4554
- .byte 0x20
4555
- .byte 0x62
4556
- .4byte 0x59
4557
- .byte 0x60
4558
- .uleb128 0xf
4559
- .4byte .LASF374
4560
- .byte 0x20
4561
- .byte 0x63
4562
- .4byte 0x59
4563
- .byte 0x64
4564
- .uleb128 0xf
4565
- .4byte .LASF375
4566
- .byte 0x20
4567
- .byte 0x64
4568
- .4byte 0x59
4569
- .byte 0x68
4570
- .uleb128 0x10
4571
- .string "ops"
4572
- .byte 0x20
4573
- .byte 0x65
4574
- .4byte 0x263
4575
- .byte 0x70
4576
- .uleb128 0xf
4577
- .4byte .LASF42
4578
- .byte 0x20
4579
- .byte 0x66
4580
- .4byte 0x11f
4581
- .byte 0x78
4582
- .byte 0
4583
- .uleb128 0x9
4584
- .byte 0x8
4585
- .4byte 0x15a5
4586
- .uleb128 0x13
4587
- .4byte 0x59
4588
- .4byte 0x169e
4589
- .uleb128 0x14
4590
- .4byte 0x155a
4591
- .byte 0
4592
- .uleb128 0x9
4593
- .byte 0x8
4594
- .4byte 0x168f
4595
- .uleb128 0x5
4596
- .4byte .LASF398
4597
- .byte 0x21
4598
- .byte 0xb
4599
- .4byte 0x149
4600
- .uleb128 0xe
4601
- .4byte .LASF399
4602
- .byte 0x70
4603
- .byte 0x22
4604
- .byte 0x16
4605
- .4byte 0x1740
4606
- .uleb128 0xf
4607
- .4byte .LASF42
4608
- .byte 0x22
4609
- .byte 0x17
4610
- .4byte 0x59
4611
- .byte 0
4612
- .uleb128 0x10
4613
- .string "ext"
4614
- .byte 0x22
4615
- .byte 0x18
4616
- .4byte 0x59
4617
- .byte 0x4
4618
- .uleb128 0xf
4619
- .4byte .LASF28
4620
- .byte 0x22
4621
- .byte 0x19
4622
- .4byte 0xfc5
4623
- .byte 0x8
4624
- .uleb128 0xf
4625
- .4byte .LASF54
4626
- .byte 0x22
4627
- .byte 0x1d
4628
- .4byte 0x1755
4629
- .byte 0x28
4630
- .uleb128 0xf
4631
- .4byte .LASF400
4632
- .byte 0x22
4633
- .byte 0x1e
4634
- .4byte 0x1755
4635
- .byte 0x30
4636
- .uleb128 0xf
4637
- .4byte .LASF401
4638
- .byte 0x22
4639
- .byte 0x23
4640
- .4byte 0x176b
4641
- .byte 0x38
4642
- .uleb128 0xf
4643
- .4byte .LASF402
4644
- .byte 0x22
4645
- .byte 0x25
4646
- .4byte 0x1781
4647
- .byte 0x40
4648
- .uleb128 0xf
4649
- .4byte .LASF403
4650
- .byte 0x22
4651
- .byte 0x2a
4652
- .4byte 0x1755
4653
- .byte 0x48
4654
- .uleb128 0xf
4655
- .4byte .LASF404
4656
- .byte 0x22
4657
- .byte 0x2b
4658
- .4byte 0x1755
4659
- .byte 0x50
4660
- .uleb128 0xf
4661
- .4byte .LASF35
4662
- .byte 0x22
4663
- .byte 0x2f
4664
- .4byte 0x135
4665
- .byte 0x58
4666
- .uleb128 0xf
4667
- .4byte .LASF405
4668
- .byte 0x22
4669
- .byte 0x30
4670
- .4byte 0x290
4671
- .byte 0x60
4672
- .byte 0
4673
- .uleb128 0x13
4674
- .4byte 0x59
4675
- .4byte 0x174f
4676
- .uleb128 0x14
4677
- .4byte 0x174f
4678
- .byte 0
4679
- .uleb128 0x9
4680
- .byte 0x8
4681
- .4byte 0x16af
4682
- .uleb128 0x9
4683
- .byte 0x8
4684
- .4byte 0x1740
4685
- .uleb128 0x28
4686
- .4byte 0x176b
4687
- .uleb128 0x14
4688
- .4byte 0x174f
4689
- .uleb128 0x14
4690
- .4byte 0xe7
4691
- .byte 0
4692
- .uleb128 0x9
4693
- .byte 0x8
4694
- .4byte 0x175b
4695
- .uleb128 0x28
4696
- .4byte 0x1781
4697
- .uleb128 0x14
4698
- .4byte 0x174f
4699
- .uleb128 0x14
4700
- .4byte 0xd5
4701
- .byte 0
4702
- .uleb128 0x9
4703
- .byte 0x8
4704
- .4byte 0x1771
4705
- .uleb128 0xb
4706
- .4byte 0x174f
4707
- .4byte 0x1792
4708
- .uleb128 0xc
4709
- .byte 0
4710
- .uleb128 0x5
4711
- .4byte .LASF406
4712
- .byte 0x22
4713
- .byte 0x48
4714
- .4byte 0x1787
4715
- .uleb128 0xb
4716
- .4byte 0xf3
4717
- .4byte 0x17ad
4718
- .uleb128 0x12
4719
- .4byte 0xce
4720
- .byte 0x2
4721
- .byte 0
4722
- .uleb128 0x5
4723
- .4byte .LASF407
4724
- .byte 0x22
4725
- .byte 0x49
4726
- .4byte 0x179d
4727
- .uleb128 0xb
4728
- .4byte 0x17c8
4729
- .4byte 0x17c8
4730
- .uleb128 0x12
4731
- .4byte 0xce
4732
- .byte 0x2
4733
- .byte 0
4734
- .uleb128 0x9
4735
- .byte 0x8
4736
- .4byte 0x174f
4737
- .uleb128 0x5
4738
- .4byte .LASF408
4739
- .byte 0x23
4740
- .byte 0x15
4741
- .4byte 0x17b8
4742
- .uleb128 0xb
4743
- .4byte 0x59
4744
- .4byte 0x17e9
4745
- .uleb128 0x12
4746
- .4byte 0xce
4747
- .byte 0x2
4748
- .byte 0
4749
- .uleb128 0x5
4750
- .4byte .LASF409
4751
- .byte 0x23
4752
- .byte 0x1a
4753
- .4byte 0x17d9
4754
- .uleb128 0x25
4755
- .byte 0x4
4756
- .4byte 0x84
4757
- .byte 0x2
4758
- .byte 0x13
4759
- .4byte 0x1831
4760
- .uleb128 0x1c
4761
- .4byte .LASF410
4762
- .byte 0
4763
- .uleb128 0x1c
4764
- .4byte .LASF411
4765
- .byte 0x1
4766
- .uleb128 0x1c
4767
- .4byte .LASF412
4768
- .byte 0x2
4769
- .uleb128 0x1c
4770
- .4byte .LASF413
4771
- .byte 0x3
4772
- .uleb128 0x1c
4773
- .4byte .LASF414
4774
- .byte 0x4
4775
- .uleb128 0x1c
4776
- .4byte .LASF415
4777
- .byte 0x5
4778
- .uleb128 0x1c
4779
- .4byte .LASF416
4780
- .byte 0x6
4781
- .uleb128 0x1c
4782
- .4byte .LASF417
4783
- .byte 0x7
4784
- .byte 0
4785
- .uleb128 0xb
4786
- .4byte 0xdb
4787
- .4byte 0x1841
4788
- .uleb128 0x12
4789
- .4byte 0xce
4790
- .byte 0x6
4791
- .byte 0
4792
- .uleb128 0x8
4793
- .4byte 0x1831
4794
- .uleb128 0x2a
4795
- .4byte .LASF418
4796
- .byte 0x2
4797
- .byte 0x1e
4798
- .4byte 0x1841
4799
- .uleb128 0x9
4800
- .byte 0x3
4801
- .8byte test_pattern
4802
- .uleb128 0xb
4803
- .4byte 0xa3
4804
- .4byte 0x186b
4805
- .uleb128 0x12
4806
- .4byte 0xce
4807
- .byte 0x6
4808
- .byte 0
4809
- .uleb128 0x8
4810
- .4byte 0x185b
4811
- .uleb128 0x2a
4812
- .4byte .LASF419
4813
- .byte 0x2
4814
- .byte 0x28
4815
- .4byte 0x186b
4816
- .uleb128 0x9
4817
- .byte 0x3
4818
- .8byte test_pat_param
4819
- .uleb128 0x2f
4820
- .4byte .LASF420
4821
- .byte 0x2
4822
- .2byte 0x136
4823
- .4byte 0x67c
4824
- .uleb128 0x9
4825
- .byte 0x3
4826
- .8byte _u_boot_list_2_cmd_2_ddr_test
4827
- .uleb128 0x30
4828
- .4byte .LASF429
4829
- .byte 0x4
4830
- .byte 0x60
4831
- .4byte 0x59
4832
- .8byte .LFB271
4833
- .8byte .LFE271-.LFB271
4834
- .uleb128 0x1
4835
- .byte 0x9c
4836
- .4byte 0x1b4f
4837
- .uleb128 0x31
4838
- .4byte .LASF421
4839
- .byte 0x4
4840
- .byte 0x60
4841
- .4byte 0x109
4842
- .4byte .LLST15
4843
- .uleb128 0x31
4844
- .4byte .LASF422
4845
- .byte 0x4
4846
- .byte 0x60
4847
- .4byte 0x109
4848
- .4byte .LLST16
4849
- .uleb128 0x32
4850
- .string "ret"
4851
- .byte 0x4
4852
- .byte 0x62
4853
- .4byte 0x59
4854
- .uleb128 0x1
4855
- .byte 0x50
4856
- .uleb128 0x33
4857
- .4byte 0x1bc3
4858
- .8byte .LBB6
4859
- .4byte .Ldebug_ranges0+0
4860
- .byte 0x4
4861
- .byte 0x64
4862
- .4byte 0x1a2b
4863
- .uleb128 0x34
4864
- .4byte 0x1bde
4865
- .4byte .LLST17
4866
- .uleb128 0x34
4867
- .4byte 0x1bd3
4868
- .4byte .LLST18
4869
- .uleb128 0x35
4870
- .4byte .Ldebug_ranges0+0
4871
- .uleb128 0x36
4872
- .4byte 0x1be9
4873
- .4byte .LLST19
4874
- .uleb128 0x36
4875
- .4byte 0x1bf2
4876
- .4byte .LLST20
4877
- .uleb128 0x36
4878
- .4byte 0x1bfb
4879
- .4byte .LLST21
4880
- .uleb128 0x36
4881
- .4byte 0x1c06
4882
- .4byte .LLST22
4883
- .uleb128 0x37
4884
- .4byte 0x1c11
4885
- .uleb128 0x36
4886
- .4byte 0x1c1c
4887
- .4byte .LLST23
4888
- .uleb128 0x36
4889
- .4byte 0x1c27
4890
- .4byte .LLST24
4891
- .uleb128 0x36
4892
- .4byte 0x1c32
4893
- .4byte .LLST25
4894
- .uleb128 0x38
4895
- .8byte .LVL64
4896
- .4byte 0x26e7
4897
- .4byte 0x1981
4898
- .uleb128 0x39
4899
- .uleb128 0x1
4900
- .byte 0x50
4901
- .uleb128 0x2
4902
- .byte 0x83
4903
- .sleb128 0
4904
- .uleb128 0x39
4905
- .uleb128 0x1
4906
- .byte 0x51
4907
- .uleb128 0x6
4908
- .byte 0x11
4909
- .sleb128 -2139062144
4910
- .uleb128 0x39
4911
- .uleb128 0x1
4912
- .byte 0x52
4913
- .uleb128 0x2
4914
- .byte 0x84
4915
- .sleb128 0
4916
- .byte 0
4917
- .uleb128 0x38
4918
- .8byte .LVL66
4919
- .4byte 0x26f3
4920
- .4byte 0x199f
4921
- .uleb128 0x39
4922
- .uleb128 0x1
4923
- .byte 0x50
4924
- .uleb128 0x2
4925
- .byte 0x88
4926
- .sleb128 0
4927
- .uleb128 0x39
4928
- .uleb128 0x1
4929
- .byte 0x51
4930
- .uleb128 0x2
4931
- .byte 0x86
4932
- .sleb128 0
4933
- .byte 0
4934
- .uleb128 0x38
4935
- .8byte .LVL72
4936
- .4byte 0x26f3
4937
- .4byte 0x19b9
4938
- .uleb128 0x39
4939
- .uleb128 0x1
4940
- .byte 0x50
4941
- .uleb128 0x4
4942
- .byte 0x8f
4943
- .sleb128 192
4944
- .byte 0x6
4945
- .byte 0
4946
- .uleb128 0x38
4947
- .8byte .LVL76
4948
- .4byte 0x26fe
4949
- .4byte 0x19d7
4950
- .uleb128 0x39
4951
- .uleb128 0x1
4952
- .byte 0x50
4953
- .uleb128 0x2
4954
- .byte 0x8c
4955
- .sleb128 0
4956
- .uleb128 0x39
4957
- .uleb128 0x1
4958
- .byte 0x51
4959
- .uleb128 0x2
4960
- .byte 0x8c
4961
- .sleb128 4
4962
- .byte 0
4963
- .uleb128 0x38
4964
- .8byte .LVL78
4965
- .4byte 0x26f3
4966
- .4byte 0x19f6
4967
- .uleb128 0x39
4968
- .uleb128 0x1
4969
- .byte 0x50
4970
- .uleb128 0x9
4971
- .byte 0x3
4972
- .8byte .LC10
4973
- .byte 0
4974
- .uleb128 0x3a
4975
- .8byte .LVL79
4976
- .4byte 0x26f3
4977
- .uleb128 0x39
4978
- .uleb128 0x1
4979
- .byte 0x50
4980
- .uleb128 0x9
4981
- .byte 0x3
4982
- .8byte .LC11
4983
- .uleb128 0x39
4984
- .uleb128 0x1
4985
- .byte 0x51
4986
- .uleb128 0x2
4987
- .byte 0x8c
4988
- .sleb128 0
4989
- .uleb128 0x39
4990
- .uleb128 0x1
4991
- .byte 0x52
4992
- .uleb128 0x2
4993
- .byte 0x8a
4994
- .sleb128 0
4995
- .uleb128 0x39
4996
- .uleb128 0x1
4997
- .byte 0x53
4998
- .uleb128 0x2
4999
- .byte 0x8b
5000
- .sleb128 0
5001
- .uleb128 0x39
5002
- .uleb128 0x1
5003
- .byte 0x54
5004
- .uleb128 0x2
5005
- .byte 0x85
5006
- .sleb128 0
5007
- .byte 0
5008
- .byte 0
5009
- .byte 0
5010
- .uleb128 0x3b
5011
- .4byte 0x1b4f
5012
- .8byte .LBB15
5013
- .4byte .Ldebug_ranges0+0x60
5014
- .byte 0x4
5015
- .byte 0x66
5016
- .uleb128 0x3c
5017
- .4byte 0x1b6a
5018
- .uleb128 0x3c
5019
- .4byte 0x1b5f
5020
- .uleb128 0x35
5021
- .4byte .Ldebug_ranges0+0x60
5022
- .uleb128 0x36
5023
- .4byte 0x1b75
5024
- .4byte .LLST26
5025
- .uleb128 0x36
5026
- .4byte 0x1b7e
5027
- .4byte .LLST27
5028
- .uleb128 0x3d
5029
- .4byte 0x1b87
5030
- .uleb128 0x1
5031
- .byte 0x66
5032
- .uleb128 0x3d
5033
- .4byte 0x1b92
5034
- .uleb128 0x1
5035
- .byte 0x69
5036
- .uleb128 0x3d
5037
- .4byte 0x1b9d
5038
- .uleb128 0x1
5039
- .byte 0x6b
5040
- .uleb128 0x37
5041
- .4byte 0x1ba8
5042
- .uleb128 0x36
5043
- .4byte 0x1bb1
5044
- .4byte .LLST28
5045
- .uleb128 0x38
5046
- .8byte .LVL85
5047
- .4byte 0x26f3
5048
- .4byte 0x1aa0
5049
- .uleb128 0x39
5050
- .uleb128 0x1
5051
- .byte 0x50
5052
- .uleb128 0x2
5053
- .byte 0x8a
5054
- .sleb128 0
5055
- .uleb128 0x39
5056
- .uleb128 0x1
5057
- .byte 0x51
5058
- .uleb128 0x2
5059
- .byte 0x85
5060
- .sleb128 0
5061
- .byte 0
5062
- .uleb128 0x38
5063
- .8byte .LVL87
5064
- .4byte 0x26e7
5065
- .4byte 0x1ac4
5066
- .uleb128 0x39
5067
- .uleb128 0x1
5068
- .byte 0x50
5069
- .uleb128 0x2
5070
- .byte 0x83
5071
- .sleb128 0
5072
- .uleb128 0x39
5073
- .uleb128 0x1
5074
- .byte 0x51
5075
- .uleb128 0x2
5076
- .byte 0x86
5077
- .sleb128 0
5078
- .uleb128 0x39
5079
- .uleb128 0x1
5080
- .byte 0x52
5081
- .uleb128 0x2
5082
- .byte 0x84
5083
- .sleb128 0
5084
- .byte 0
5085
- .uleb128 0x38
5086
- .8byte .LVL91
5087
- .4byte 0x26f3
5088
- .4byte 0x1adc
5089
- .uleb128 0x39
5090
- .uleb128 0x1
5091
- .byte 0x50
5092
- .uleb128 0x2
5093
- .byte 0x88
5094
- .sleb128 0
5095
- .byte 0
5096
- .uleb128 0x38
5097
- .8byte .LVL96
5098
- .4byte 0x26fe
5099
- .4byte 0x1afa
5100
- .uleb128 0x39
5101
- .uleb128 0x1
5102
- .byte 0x50
5103
- .uleb128 0x2
5104
- .byte 0x87
5105
- .sleb128 0
5106
- .uleb128 0x39
5107
- .uleb128 0x1
5108
- .byte 0x51
5109
- .uleb128 0x2
5110
- .byte 0x87
5111
- .sleb128 4
5112
- .byte 0
5113
- .uleb128 0x38
5114
- .8byte .LVL99
5115
- .4byte 0x26f3
5116
- .4byte 0x1b19
5117
- .uleb128 0x39
5118
- .uleb128 0x1
5119
- .byte 0x50
5120
- .uleb128 0x9
5121
- .byte 0x3
5122
- .8byte .LC14
5123
- .byte 0
5124
- .uleb128 0x3a
5125
- .8byte .LVL100
5126
- .4byte 0x26f3
5127
- .uleb128 0x39
5128
- .uleb128 0x1
5129
- .byte 0x50
5130
- .uleb128 0x9
5131
- .byte 0x3
5132
- .8byte .LC15
5133
- .uleb128 0x39
5134
- .uleb128 0x1
5135
- .byte 0x51
5136
- .uleb128 0x2
5137
- .byte 0x87
5138
- .sleb128 0
5139
- .uleb128 0x39
5140
- .uleb128 0x1
5141
- .byte 0x52
5142
- .uleb128 0x2
5143
- .byte 0x89
5144
- .sleb128 0
5145
- .uleb128 0x39
5146
- .uleb128 0x1
5147
- .byte 0x53
5148
- .uleb128 0x2
5149
- .byte 0x8b
5150
- .sleb128 0
5151
- .uleb128 0x39
5152
- .uleb128 0x1
5153
- .byte 0x54
5154
- .uleb128 0x2
5155
- .byte 0x86
5156
- .sleb128 0
5157
- .byte 0
5158
- .byte 0
5159
- .byte 0
5160
- .byte 0
5161
- .uleb128 0x3e
5162
- .4byte .LASF426
5163
- .byte 0x4
5164
- .byte 0x36
5165
- .4byte 0x59
5166
- .byte 0x1
5167
- .4byte 0x1bbd
5168
- .uleb128 0x3f
5169
- .4byte .LASF421
5170
- .byte 0x4
5171
- .byte 0x36
5172
- .4byte 0x109
5173
- .uleb128 0x3f
5174
- .4byte .LASF422
5175
- .byte 0x4
5176
- .byte 0x36
5177
- .4byte 0x109
5178
- .uleb128 0x40
5179
- .string "i"
5180
- .byte 0x4
5181
- .byte 0x38
5182
- .4byte 0x109
5183
- .uleb128 0x40
5184
- .string "j"
5185
- .byte 0x4
5186
- .byte 0x38
5187
- .4byte 0x109
5188
- .uleb128 0x41
5189
- .4byte .LASF423
5190
- .byte 0x4
5191
- .byte 0x39
5192
- .4byte 0x109
5193
- .uleb128 0x41
5194
- .4byte .LASF378
5195
- .byte 0x4
5196
- .byte 0x39
5197
- .4byte 0x109
5198
- .uleb128 0x41
5199
- .4byte .LASF424
5200
- .byte 0x4
5201
- .byte 0x3a
5202
- .4byte 0x109
5203
- .uleb128 0x40
5204
- .string "p"
5205
- .byte 0x4
5206
- .byte 0x3b
5207
- .4byte 0x1bbd
5208
- .uleb128 0x41
5209
- .4byte .LASF425
5210
- .byte 0x4
5211
- .byte 0x3c
5212
- .4byte 0x109
5213
- .byte 0
5214
- .uleb128 0x9
5215
- .byte 0x8
5216
- .4byte 0x42
5217
- .uleb128 0x3e
5218
- .4byte .LASF427
5219
- .byte 0x4
5220
- .byte 0xb
5221
- .4byte 0x59
5222
- .byte 0x1
5223
- .4byte 0x1c3e
5224
- .uleb128 0x3f
5225
- .4byte .LASF421
5226
- .byte 0x4
5227
- .byte 0xb
5228
- .4byte 0x109
5229
- .uleb128 0x3f
5230
- .4byte .LASF422
5231
- .byte 0x4
5232
- .byte 0xb
5233
- .4byte 0x109
5234
- .uleb128 0x40
5235
- .string "i"
5236
- .byte 0x4
5237
- .byte 0xd
5238
- .4byte 0xa8
5239
- .uleb128 0x40
5240
- .string "j"
5241
- .byte 0x4
5242
- .byte 0xd
5243
- .4byte 0xa8
5244
- .uleb128 0x41
5245
- .4byte .LASF428
5246
- .byte 0x4
5247
- .byte 0xe
5248
- .4byte 0xa8
5249
- .uleb128 0x41
5250
- .4byte .LASF423
5251
- .byte 0x4
5252
- .byte 0xe
5253
- .4byte 0xa8
5254
- .uleb128 0x41
5255
- .4byte .LASF378
5256
- .byte 0x4
5257
- .byte 0xe
5258
- .4byte 0xa8
5259
- .uleb128 0x41
5260
- .4byte .LASF424
5261
- .byte 0x4
5262
- .byte 0xf
5263
- .4byte 0xa8
5264
- .uleb128 0x40
5265
- .string "p32"
5266
- .byte 0x4
5267
- .byte 0x10
5268
- .4byte 0x1c3e
5269
- .uleb128 0x41
5270
- .4byte .LASF425
5271
- .byte 0x4
5272
- .byte 0x11
5273
- .4byte 0x109
5274
- .byte 0
5275
- .uleb128 0x9
5276
- .byte 0x8
5277
- .4byte 0xb3
5278
- .uleb128 0x30
5279
- .4byte .LASF430
5280
- .byte 0x3
5281
- .byte 0xf
5282
- .4byte 0x59
5283
- .8byte .LFB268
5284
- .8byte .LFE268-.LFB268
5285
- .uleb128 0x1
5286
- .byte 0x9c
5287
- .4byte 0x1e70
5288
- .uleb128 0x31
5289
- .4byte .LASF431
5290
- .byte 0x3
5291
- .byte 0xf
5292
- .4byte 0x109
5293
- .4byte .LLST9
5294
- .uleb128 0x31
5295
- .4byte .LASF377
5296
- .byte 0x3
5297
- .byte 0xf
5298
- .4byte 0x109
5299
- .4byte .LLST10
5300
- .uleb128 0x42
5301
- .4byte .LASF268
5302
- .byte 0x3
5303
- .byte 0x11
5304
- .4byte 0x109
5305
- .4byte .LLST11
5306
- .uleb128 0x2a
5307
- .4byte .LASF432
5308
- .byte 0x3
5309
- .byte 0x11
5310
- .4byte 0x109
5311
- .uleb128 0x1
5312
- .byte 0x64
5313
- .uleb128 0x42
5314
- .4byte .LASF433
5315
- .byte 0x3
5316
- .byte 0x12
5317
- .4byte 0x59
5318
- .4byte .LLST12
5319
- .uleb128 0x2a
5320
- .4byte .LASF434
5321
- .byte 0x3
5322
- .byte 0x13
5323
- .4byte 0x1e70
5324
- .uleb128 0x2
5325
- .byte 0x91
5326
- .sleb128 -32
5327
- .uleb128 0x43
5328
- .string "col"
5329
- .byte 0x3
5330
- .byte 0x15
5331
- .4byte 0xa8
5332
- .4byte .LLST13
5333
- .uleb128 0x2a
5334
- .4byte .LASF435
5335
- .byte 0x3
5336
- .byte 0x15
5337
- .4byte 0xa8
5338
- .uleb128 0x1
5339
- .byte 0x65
5340
- .uleb128 0x42
5341
- .4byte .LASF436
5342
- .byte 0x3
5343
- .byte 0x16
5344
- .4byte 0x109
5345
- .4byte .LLST14
5346
- .uleb128 0x44
5347
- .4byte .LASF483
5348
- .byte 0x3
5349
- .byte 0x3e
5350
- .8byte .L31
5351
- .uleb128 0x38
5352
- .8byte .LVL38
5353
- .4byte 0x270a
5354
- .4byte 0x1d22
5355
- .uleb128 0x39
5356
- .uleb128 0x1
5357
- .byte 0x50
5358
- .uleb128 0x3
5359
- .byte 0x8f
5360
- .sleb128 144
5361
- .uleb128 0x39
5362
- .uleb128 0x1
5363
- .byte 0x51
5364
- .uleb128 0x9
5365
- .byte 0x3
5366
- .8byte .LANCHOR1
5367
- .uleb128 0x39
5368
- .uleb128 0x1
5369
- .byte 0x52
5370
- .uleb128 0x2
5371
- .byte 0x8
5372
- .byte 0x20
5373
- .byte 0
5374
- .uleb128 0x38
5375
- .8byte .LVL39
5376
- .4byte 0x26f3
5377
- .4byte 0x1d41
5378
- .uleb128 0x39
5379
- .uleb128 0x1
5380
- .byte 0x50
5381
- .uleb128 0x9
5382
- .byte 0x3
5383
- .8byte .LC6
5384
- .byte 0
5385
- .uleb128 0x45
5386
- .8byte .LVL40
5387
- .4byte 0x2713
5388
- .uleb128 0x38
5389
- .8byte .LVL42
5390
- .4byte 0x26f3
5391
- .4byte 0x1d73
5392
- .uleb128 0x39
5393
- .uleb128 0x1
5394
- .byte 0x50
5395
- .uleb128 0x9
5396
- .byte 0x3
5397
- .8byte .LC7
5398
- .uleb128 0x39
5399
- .uleb128 0x1
5400
- .byte 0x51
5401
- .uleb128 0x2
5402
- .byte 0x83
5403
- .sleb128 0
5404
- .byte 0
5405
- .uleb128 0x38
5406
- .8byte .LVL49
5407
- .4byte 0x271e
5408
- .4byte 0x1d92
5409
- .uleb128 0x39
5410
- .uleb128 0x1
5411
- .byte 0x50
5412
- .uleb128 0x3
5413
- .byte 0x8f
5414
- .sleb128 144
5415
- .uleb128 0x39
5416
- .uleb128 0x1
5417
- .byte 0x51
5418
- .uleb128 0x2
5419
- .byte 0x8
5420
- .byte 0x20
5421
- .byte 0
5422
- .uleb128 0x38
5423
- .8byte .LVL50
5424
- .4byte 0x2729
5425
- .4byte 0x1db7
5426
- .uleb128 0x39
5427
- .uleb128 0x1
5428
- .byte 0x50
5429
- .uleb128 0x2
5430
- .byte 0x89
5431
- .sleb128 0
5432
- .uleb128 0x39
5433
- .uleb128 0x1
5434
- .byte 0x51
5435
- .uleb128 0x3
5436
- .byte 0x8f
5437
- .sleb128 144
5438
- .uleb128 0x39
5439
- .uleb128 0x1
5440
- .byte 0x52
5441
- .uleb128 0x2
5442
- .byte 0x8
5443
- .byte 0x20
5444
- .byte 0
5445
- .uleb128 0x38
5446
- .8byte .LVL53
5447
- .4byte 0x2729
5448
- .4byte 0x1ddc
5449
- .uleb128 0x39
5450
- .uleb128 0x1
5451
- .byte 0x50
5452
- .uleb128 0x2
5453
- .byte 0x8a
5454
- .sleb128 0
5455
- .uleb128 0x39
5456
- .uleb128 0x1
5457
- .byte 0x51
5458
- .uleb128 0x3
5459
- .byte 0x8f
5460
- .sleb128 144
5461
- .uleb128 0x39
5462
- .uleb128 0x1
5463
- .byte 0x52
5464
- .uleb128 0x2
5465
- .byte 0x8
5466
- .byte 0x20
5467
- .byte 0
5468
- .uleb128 0x38
5469
- .8byte .LVL54
5470
- .4byte 0x2735
5471
- .4byte 0x1e12
5472
- .uleb128 0x39
5473
- .uleb128 0x1
5474
- .byte 0x50
5475
- .uleb128 0x3
5476
- .byte 0x8f
5477
- .sleb128 144
5478
- .uleb128 0x39
5479
- .uleb128 0x1
5480
- .byte 0x51
5481
- .uleb128 0x2
5482
- .byte 0x8
5483
- .byte 0x20
5484
- .uleb128 0x39
5485
- .uleb128 0x1
5486
- .byte 0x52
5487
- .uleb128 0x8
5488
- .byte 0x84
5489
- .sleb128 0
5490
- .byte 0x88
5491
- .sleb128 0
5492
- .byte 0x22
5493
- .byte 0x89
5494
- .sleb128 0
5495
- .byte 0x22
5496
- .uleb128 0x39
5497
- .uleb128 0x1
5498
- .byte 0x53
5499
- .uleb128 0x2
5500
- .byte 0x8
5501
- .byte 0x20
5502
- .uleb128 0x39
5503
- .uleb128 0x1
5504
- .byte 0x54
5505
- .uleb128 0x1
5506
- .byte 0x31
5507
- .byte 0
5508
- .uleb128 0x38
5509
- .8byte .LVL59
5510
- .4byte 0x2729
5511
- .4byte 0x1e43
5512
- .uleb128 0x39
5513
- .uleb128 0x1
5514
- .byte 0x50
5515
- .uleb128 0xe
5516
- .byte 0x85
5517
- .sleb128 0
5518
- .byte 0xc
5519
- .4byte 0xffffffff
5520
- .byte 0x1a
5521
- .byte 0x84
5522
- .sleb128 0
5523
- .byte 0x22
5524
- .byte 0x89
5525
- .sleb128 0
5526
- .byte 0x22
5527
- .uleb128 0x39
5528
- .uleb128 0x1
5529
- .byte 0x51
5530
- .uleb128 0x3
5531
- .byte 0x8f
5532
- .sleb128 144
5533
- .uleb128 0x39
5534
- .uleb128 0x1
5535
- .byte 0x52
5536
- .uleb128 0x2
5537
- .byte 0x8
5538
- .byte 0x20
5539
- .byte 0
5540
- .uleb128 0x3a
5541
- .8byte .LVL60
5542
- .4byte 0x2735
5543
- .uleb128 0x39
5544
- .uleb128 0x1
5545
- .byte 0x50
5546
- .uleb128 0x3
5547
- .byte 0x8f
5548
- .sleb128 144
5549
- .uleb128 0x39
5550
- .uleb128 0x1
5551
- .byte 0x51
5552
- .uleb128 0x2
5553
- .byte 0x8
5554
- .byte 0x20
5555
- .uleb128 0x39
5556
- .uleb128 0x1
5557
- .byte 0x52
5558
- .uleb128 0x2
5559
- .byte 0x8a
5560
- .sleb128 0
5561
- .uleb128 0x39
5562
- .uleb128 0x1
5563
- .byte 0x53
5564
- .uleb128 0x2
5565
- .byte 0x8
5566
- .byte 0x20
5567
- .uleb128 0x39
5568
- .uleb128 0x1
5569
- .byte 0x54
5570
- .uleb128 0x1
5571
- .byte 0x31
5572
- .byte 0
5573
- .byte 0
5574
- .uleb128 0xb
5575
- .4byte 0xa8
5576
- .4byte 0x1e80
5577
- .uleb128 0x12
5578
- .4byte 0xce
5579
- .byte 0x7
5580
- .byte 0
5581
- .uleb128 0x46
5582
- .4byte .LASF448
5583
- .byte 0x2
5584
- .byte 0x62
5585
- .4byte 0x59
5586
- .8byte .LFB256
5587
- .8byte .LFE256-.LFB256
5588
- .uleb128 0x1
5589
- .byte 0x9c
5590
- .4byte 0x2293
5591
- .uleb128 0x31
5592
- .4byte .LASF437
5593
- .byte 0x2
5594
- .byte 0x62
5595
- .4byte 0x2293
5596
- .4byte .LLST37
5597
- .uleb128 0x31
5598
- .4byte .LASF438
5599
- .byte 0x2
5600
- .byte 0x62
5601
- .4byte 0x59
5602
- .4byte .LLST38
5603
- .uleb128 0x31
5604
- .4byte .LASF439
5605
- .byte 0x2
5606
- .byte 0x62
5607
- .4byte 0x59
5608
- .4byte .LLST39
5609
- .uleb128 0x31
5610
- .4byte .LASF440
5611
- .byte 0x2
5612
- .byte 0x63
5613
- .4byte 0x641
5614
- .4byte .LLST40
5615
- .uleb128 0x43
5616
- .string "i"
5617
- .byte 0x2
5618
- .byte 0x65
5619
- .4byte 0x59
5620
- .4byte .LLST41
5621
- .uleb128 0x42
5622
- .4byte .LASF441
5623
- .byte 0x2
5624
- .byte 0x66
5625
- .4byte 0x59
5626
- .4byte .LLST42
5627
- .uleb128 0x42
5628
- .4byte .LASF442
5629
- .byte 0x2
5630
- .byte 0x66
5631
- .4byte 0x59
5632
- .4byte .LLST43
5633
- .uleb128 0x32
5634
- .string "arg"
5635
- .byte 0x2
5636
- .byte 0x67
5637
- .4byte 0x2299
5638
- .uleb128 0x2
5639
- .byte 0x91
5640
- .sleb128 -40
5641
- .uleb128 0x2a
5642
- .4byte .LASF431
5643
- .byte 0x2
5644
- .byte 0x68
5645
- .4byte 0x22a9
5646
- .uleb128 0x3
5647
- .byte 0x91
5648
- .sleb128 -104
5649
- .uleb128 0x2a
5650
- .4byte .LASF377
5651
- .byte 0x2
5652
- .byte 0x69
5653
- .4byte 0x22a9
5654
- .uleb128 0x3
5655
- .byte 0x91
5656
- .sleb128 -72
5657
- .uleb128 0x42
5658
- .4byte .LASF443
5659
- .byte 0x2
5660
- .byte 0x6a
5661
- .4byte 0xa8
5662
- .4byte .LLST44
5663
- .uleb128 0x42
5664
- .4byte .LASF444
5665
- .byte 0x2
5666
- .byte 0x6b
5667
- .4byte 0xa8
5668
- .4byte .LLST45
5669
- .uleb128 0x42
5670
- .4byte .LASF445
5671
- .byte 0x2
5672
- .byte 0x6c
5673
- .4byte 0xa8
5674
- .4byte .LLST46
5675
- .uleb128 0x43
5676
- .string "ret"
5677
- .byte 0x2
5678
- .byte 0x6d
5679
- .4byte 0x59
5680
- .4byte .LLST47
5681
- .uleb128 0x42
5682
- .4byte .LASF446
5683
- .byte 0x2
5684
- .byte 0x6e
5685
- .4byte 0x59
5686
- .4byte .LLST48
5687
- .uleb128 0x42
5688
- .4byte .LASF447
5689
- .byte 0x2
5690
- .byte 0x6f
5691
- .4byte 0xa8
5692
- .4byte .LLST49
5693
- .uleb128 0x32
5694
- .string "dev"
5695
- .byte 0x2
5696
- .byte 0x91
5697
- .4byte 0x25d
5698
- .uleb128 0x3
5699
- .byte 0x91
5700
- .sleb128 -112
5701
- .uleb128 0x38
5702
- .8byte .LVL132
5703
- .4byte 0x26f3
5704
- .4byte 0x1fbc
5705
- .uleb128 0x39
5706
- .uleb128 0x1
5707
- .byte 0x50
5708
- .uleb128 0x9
5709
- .byte 0x3
5710
- .8byte .LC18
5711
- .byte 0
5712
- .uleb128 0x38
5713
- .8byte .LVL133
5714
- .4byte 0x2740
5715
- .4byte 0x1fdf
5716
- .uleb128 0x39
5717
- .uleb128 0x1
5718
- .byte 0x50
5719
- .uleb128 0x2
5720
- .byte 0x85
5721
- .sleb128 0
5722
- .uleb128 0x39
5723
- .uleb128 0x1
5724
- .byte 0x51
5725
- .uleb128 0x2
5726
- .byte 0x84
5727
- .sleb128 0
5728
- .uleb128 0x39
5729
- .uleb128 0x1
5730
- .byte 0x52
5731
- .uleb128 0x1
5732
- .byte 0x31
5733
- .byte 0
5734
- .uleb128 0x38
5735
- .8byte .LVL135
5736
- .4byte 0x274b
5737
- .4byte 0x1ffd
5738
- .uleb128 0x39
5739
- .uleb128 0x1
5740
- .byte 0x51
5741
- .uleb128 0x8
5742
- .byte 0x89
5743
- .sleb128 0
5744
- .byte 0x33
5745
- .byte 0x24
5746
- .byte 0x8b
5747
- .sleb128 0
5748
- .byte 0x22
5749
- .byte 0x6
5750
- .byte 0
5751
- .uleb128 0x45
5752
- .8byte .LVL139
5753
- .4byte 0x26f3
5754
- .uleb128 0x38
5755
- .8byte .LVL141
5756
- .4byte 0x2756
5757
- .4byte 0x202d
5758
- .uleb128 0x39
5759
- .uleb128 0x1
5760
- .byte 0x51
5761
- .uleb128 0x1
5762
- .byte 0x30
5763
- .uleb128 0x39
5764
- .uleb128 0x1
5765
- .byte 0x52
5766
- .uleb128 0x8
5767
- .byte 0x8f
5768
- .sleb128 0
5769
- .byte 0x8b
5770
- .sleb128 0
5771
- .byte 0x22
5772
- .byte 0x23
5773
- .uleb128 0x110
5774
- .byte 0
5775
- .uleb128 0x45
5776
- .8byte .LVL143
5777
- .4byte 0x2761
5778
- .uleb128 0x45
5779
- .8byte .LVL144
5780
- .4byte 0x23eb
5781
- .uleb128 0x45
5782
- .8byte .LVL145
5783
- .4byte 0x241b
5784
- .uleb128 0x38
5785
- .8byte .LVL146
5786
- .4byte 0x26f3
5787
- .4byte 0x2073
5788
- .uleb128 0x39
5789
- .uleb128 0x1
5790
- .byte 0x50
5791
- .uleb128 0x9
5792
- .byte 0x3
5793
- .8byte .LC26
5794
- .byte 0
5795
- .uleb128 0x45
5796
- .8byte .LVL148
5797
- .4byte 0x23eb
5798
- .uleb128 0x45
5799
- .8byte .LVL149
5800
- .4byte 0x22b9
5801
- .uleb128 0x45
5802
- .8byte .LVL150
5803
- .4byte 0x23eb
5804
- .uleb128 0x38
5805
- .8byte .LVL161
5806
- .4byte 0x26f3
5807
- .4byte 0x20b8
5808
- .uleb128 0x39
5809
- .uleb128 0x1
5810
- .byte 0x50
5811
- .uleb128 0x2
5812
- .byte 0x8a
5813
- .sleb128 0
5814
- .uleb128 0x39
5815
- .uleb128 0x1
5816
- .byte 0x51
5817
- .uleb128 0x2
5818
- .byte 0x89
5819
- .sleb128 0
5820
- .byte 0
5821
- .uleb128 0x38
5822
- .8byte .LVL162
5823
- .4byte 0x26f3
5824
- .4byte 0x20d6
5825
- .uleb128 0x39
5826
- .uleb128 0x1
5827
- .byte 0x50
5828
- .uleb128 0x2
5829
- .byte 0x8b
5830
- .sleb128 0
5831
- .uleb128 0x39
5832
- .uleb128 0x1
5833
- .byte 0x51
5834
- .uleb128 0x2
5835
- .byte 0x83
5836
- .sleb128 0
5837
- .byte 0
5838
- .uleb128 0x45
5839
- .8byte .LVL163
5840
- .4byte 0x241b
5841
- .uleb128 0x45
5842
- .8byte .LVL164
5843
- .4byte 0x189b
5844
- .uleb128 0x45
5845
- .8byte .LVL167
5846
- .4byte 0x244c
5847
- .uleb128 0x45
5848
- .8byte .LVL170
5849
- .4byte 0x1c44
5850
- .uleb128 0x38
5851
- .8byte .LVL173
5852
- .4byte 0x22b9
5853
- .4byte 0x2126
5854
- .uleb128 0x39
5855
- .uleb128 0x1
5856
- .byte 0x52
5857
- .uleb128 0x6
5858
- .byte 0x8c
5859
- .sleb128 0
5860
- .byte 0xa
5861
- .2byte 0x3fc
5862
- .byte 0x1a
5863
- .byte 0
5864
- .uleb128 0x45
5865
- .8byte .LVL176
5866
- .4byte 0x241b
5867
- .uleb128 0x45
5868
- .8byte .LVL177
5869
- .4byte 0x189b
5870
- .uleb128 0x45
5871
- .8byte .LVL180
5872
- .4byte 0x244c
5873
- .uleb128 0x45
5874
- .8byte .LVL183
5875
- .4byte 0x1c44
5876
- .uleb128 0x45
5877
- .8byte .LVL185
5878
- .4byte 0x276c
5879
- .uleb128 0x38
5880
- .8byte .LVL192
5881
- .4byte 0x26f3
5882
- .4byte 0x2198
5883
- .uleb128 0x39
5884
- .uleb128 0x1
5885
- .byte 0x50
5886
- .uleb128 0x9
5887
- .byte 0x3
5888
- .8byte .LC25
5889
- .uleb128 0x39
5890
- .uleb128 0x1
5891
- .byte 0x51
5892
- .uleb128 0xe
5893
- .byte 0x86
5894
- .sleb128 0
5895
- .byte 0x33
5896
- .byte 0x24
5897
- .byte 0x9
5898
- .byte 0xe5
5899
- .byte 0x24
5900
- .byte 0x9
5901
- .byte 0xe5
5902
- .byte 0x26
5903
- .byte 0x88
5904
- .sleb128 0
5905
- .byte 0x22
5906
- .byte 0x6
5907
- .byte 0
5908
- .uleb128 0x38
5909
- .8byte .LVL195
5910
- .4byte 0x26f3
5911
- .4byte 0x21bc
5912
- .uleb128 0x39
5913
- .uleb128 0x1
5914
- .byte 0x50
5915
- .uleb128 0x9
5916
- .byte 0x3
5917
- .8byte .LC28
5918
- .uleb128 0x39
5919
- .uleb128 0x1
5920
- .byte 0x51
5921
- .uleb128 0x1
5922
- .byte 0x3a
5923
- .byte 0
5924
- .uleb128 0x38
5925
- .8byte .LVL205
5926
- .4byte 0x2777
5927
- .4byte 0x21e1
5928
- .uleb128 0x39
5929
- .uleb128 0x1
5930
- .byte 0x50
5931
- .uleb128 0x3
5932
- .byte 0x8f
5933
- .sleb128 296
5934
- .uleb128 0x39
5935
- .uleb128 0x1
5936
- .byte 0x51
5937
- .uleb128 0x2
5938
- .byte 0x85
5939
- .sleb128 0
5940
- .uleb128 0x39
5941
- .uleb128 0x1
5942
- .byte 0x52
5943
- .uleb128 0x2
5944
- .byte 0x84
5945
- .sleb128 0
5946
- .byte 0
5947
- .uleb128 0x45
5948
- .8byte .LVL208
5949
- .4byte 0x241b
5950
- .uleb128 0x45
5951
- .8byte .LVL209
5952
- .4byte 0x23eb
5953
- .uleb128 0x38
5954
- .8byte .LVL213
5955
- .4byte 0x26f3
5956
- .4byte 0x2219
5957
- .uleb128 0x39
5958
- .uleb128 0x1
5959
- .byte 0x50
5960
- .uleb128 0x2
5961
- .byte 0x8a
5962
- .sleb128 0
5963
- .uleb128 0x39
5964
- .uleb128 0x1
5965
- .byte 0x51
5966
- .uleb128 0x2
5967
- .byte 0x89
5968
- .sleb128 0
5969
- .byte 0
5970
- .uleb128 0x45
5971
- .8byte .LVL218
5972
- .4byte 0x189b
5973
- .uleb128 0x45
5974
- .8byte .LVL220
5975
- .4byte 0x276c
5976
- .uleb128 0x45
5977
- .8byte .LVL223
5978
- .4byte 0x244c
5979
- .uleb128 0x45
5980
- .8byte .LVL224
5981
- .4byte 0x1c44
5982
- .uleb128 0x38
5983
- .8byte .LVL231
5984
- .4byte 0x2782
5985
- .4byte 0x2271
5986
- .uleb128 0x39
5987
- .uleb128 0x1
5988
- .byte 0x50
5989
- .uleb128 0x2
5990
- .byte 0x8
5991
- .byte 0x35
5992
- .uleb128 0x39
5993
- .uleb128 0x1
5994
- .byte 0x51
5995
- .uleb128 0x1
5996
- .byte 0x30
5997
- .uleb128 0x39
5998
- .uleb128 0x1
5999
- .byte 0x52
6000
- .uleb128 0x3
6001
- .byte 0x8f
6002
- .sleb128 208
6003
- .byte 0
6004
- .uleb128 0x3a
6005
- .8byte .LVL234
6006
- .4byte 0x26f3
6007
- .uleb128 0x39
6008
- .uleb128 0x1
6009
- .byte 0x50
6010
- .uleb128 0x9
6011
- .byte 0x3
6012
- .8byte .LC21
6013
- .uleb128 0x39
6014
- .uleb128 0x1
6015
- .byte 0x51
6016
- .uleb128 0x2
6017
- .byte 0x87
6018
- .sleb128 0
6019
- .byte 0
6020
- .byte 0
6021
- .uleb128 0x9
6022
- .byte 0x8
6023
- .4byte 0x67c
6024
- .uleb128 0xb
6025
- .4byte 0x109
6026
- .4byte 0x22a9
6027
- .uleb128 0x12
6028
- .4byte 0xce
6029
- .byte 0x4
6030
- .byte 0
6031
- .uleb128 0xb
6032
- .4byte 0x109
6033
- .4byte 0x22b9
6034
- .uleb128 0x12
6035
- .4byte 0xce
6036
- .byte 0x3
6037
- .byte 0
6038
- .uleb128 0x46
6039
- .4byte .LASF449
6040
- .byte 0x2
6041
- .byte 0x36
6042
- .4byte 0x59
6043
- .8byte .LFB255
6044
- .8byte .LFE255-.LFB255
6045
- .uleb128 0x1
6046
- .byte 0x9c
6047
- .4byte 0x23eb
6048
- .uleb128 0x31
6049
- .4byte .LASF450
6050
- .byte 0x2
6051
- .byte 0x36
6052
- .4byte 0xa8
6053
- .4byte .LLST29
6054
- .uleb128 0x31
6055
- .4byte .LASF451
6056
- .byte 0x2
6057
- .byte 0x36
6058
- .4byte 0xa8
6059
- .4byte .LLST30
6060
- .uleb128 0x31
6061
- .4byte .LASF452
6062
- .byte 0x2
6063
- .byte 0x36
6064
- .4byte 0x109
6065
- .4byte .LLST31
6066
- .uleb128 0x43
6067
- .string "i"
6068
- .byte 0x2
6069
- .byte 0x39
6070
- .4byte 0xa8
6071
- .4byte .LLST32
6072
- .uleb128 0x42
6073
- .4byte .LASF453
6074
- .byte 0x2
6075
- .byte 0x3a
6076
- .4byte 0xa8
6077
- .4byte .LLST33
6078
- .uleb128 0x42
6079
- .4byte .LASF454
6080
- .byte 0x2
6081
- .byte 0x3a
6082
- .4byte 0xa8
6083
- .4byte .LLST34
6084
- .uleb128 0x42
6085
- .4byte .LASF455
6086
- .byte 0x2
6087
- .byte 0x3a
6088
- .4byte 0xa8
6089
- .4byte .LLST35
6090
- .uleb128 0x43
6091
- .string "ret"
6092
- .byte 0x2
6093
- .byte 0x3b
6094
- .4byte 0x59
6095
- .4byte .LLST36
6096
- .uleb128 0x45
6097
- .8byte .LVL111
6098
- .4byte 0x278d
6099
- .uleb128 0x38
6100
- .8byte .LVL113
6101
- .4byte 0x26f3
6102
- .4byte 0x2381
6103
- .uleb128 0x39
6104
- .uleb128 0x1
6105
- .byte 0x50
6106
- .uleb128 0x2
6107
- .byte 0x88
6108
- .sleb128 0
6109
- .uleb128 0x39
6110
- .uleb128 0x1
6111
- .byte 0x51
6112
- .uleb128 0x2
6113
- .byte 0x87
6114
- .sleb128 0
6115
- .uleb128 0x39
6116
- .uleb128 0x1
6117
- .byte 0x52
6118
- .uleb128 0x2
6119
- .byte 0x84
6120
- .sleb128 0
6121
- .byte 0
6122
- .uleb128 0x38
6123
- .8byte .LVL114
6124
- .4byte 0x241b
6125
- .4byte 0x239f
6126
- .uleb128 0x39
6127
- .uleb128 0x1
6128
- .byte 0x50
6129
- .uleb128 0x8
6130
- .byte 0x84
6131
- .sleb128 0
6132
- .byte 0xc
6133
- .4byte 0xffffffc0
6134
- .byte 0x1a
6135
- .byte 0
6136
- .uleb128 0x38
6137
- .8byte .LVL117
6138
- .4byte 0x189b
6139
- .4byte 0x23b8
6140
- .uleb128 0x39
6141
- .uleb128 0x1
6142
- .byte 0x51
6143
- .uleb128 0x3
6144
- .byte 0x40
6145
- .byte 0x40
6146
- .byte 0x24
6147
- .byte 0
6148
- .uleb128 0x38
6149
- .8byte .LVL120
6150
- .4byte 0x26f3
6151
- .4byte 0x23dd
6152
- .uleb128 0x39
6153
- .uleb128 0x1
6154
- .byte 0x50
6155
- .uleb128 0x9
6156
- .byte 0x3
6157
- .8byte .LC17
6158
- .uleb128 0x39
6159
- .uleb128 0x1
6160
- .byte 0x51
6161
- .uleb128 0x2
6162
- .byte 0x8a
6163
- .sleb128 0
6164
- .byte 0
6165
- .uleb128 0x45
6166
- .8byte .LVL125
6167
- .4byte 0x276c
6168
- .byte 0
6169
- .uleb128 0x30
6170
- .4byte .LASF456
6171
- .byte 0x2
6172
- .byte 0x31
6173
- .4byte 0x59
6174
- .8byte .LFB254
6175
- .8byte .LFE254-.LFB254
6176
- .uleb128 0x1
6177
- .byte 0x9c
6178
- .4byte 0x241b
6179
- .uleb128 0x47
6180
- .string "uv"
6181
- .byte 0x2
6182
- .byte 0x31
6183
- .4byte 0xa8
6184
- .4byte .LLST8
6185
- .byte 0
6186
- .uleb128 0x30
6187
- .4byte .LASF457
6188
- .byte 0x2
6189
- .byte 0x2c
6190
- .4byte 0x59
6191
- .8byte .LFB253
6192
- .8byte .LFE253-.LFB253
6193
- .uleb128 0x1
6194
- .byte 0x9c
6195
- .4byte 0x244c
6196
- .uleb128 0x31
6197
- .4byte .LASF455
6198
- .byte 0x2
6199
- .byte 0x2c
6200
- .4byte 0x109
6201
- .4byte .LLST7
6202
- .byte 0
6203
- .uleb128 0x30
6204
- .4byte .LASF458
6205
- .byte 0x1
6206
- .byte 0x2d
6207
- .4byte 0x59
6208
- .8byte .LFB200
6209
- .8byte .LFE200-.LFB200
6210
- .uleb128 0x1
6211
- .byte 0x9c
6212
- .4byte 0x26d2
6213
- .uleb128 0x31
6214
- .4byte .LASF431
6215
- .byte 0x1
6216
- .byte 0x2d
6217
- .4byte 0x109
6218
- .4byte .LLST0
6219
- .uleb128 0x31
6220
- .4byte .LASF377
6221
- .byte 0x1
6222
- .byte 0x2d
6223
- .4byte 0x109
6224
- .4byte .LLST1
6225
- .uleb128 0x42
6226
- .4byte .LASF459
6227
- .byte 0x1
6228
- .byte 0x2f
6229
- .4byte 0xa8
6230
- .4byte .LLST2
6231
- .uleb128 0x43
6232
- .string "i"
6233
- .byte 0x1
6234
- .byte 0x2f
6235
- .4byte 0xa8
6236
- .4byte .LLST3
6237
- .uleb128 0x43
6238
- .string "j"
6239
- .byte 0x1
6240
- .byte 0x2f
6241
- .4byte 0xa8
6242
- .4byte .LLST4
6243
- .uleb128 0x43
6244
- .string "q"
6245
- .byte 0x1
6246
- .byte 0x2f
6247
- .4byte 0xa8
6248
- .4byte .LLST5
6249
- .uleb128 0x32
6250
- .string "buf"
6251
- .byte 0x1
6252
- .byte 0x30
6253
- .4byte 0x1e70
6254
- .uleb128 0x2
6255
- .byte 0x91
6256
- .sleb128 -32
6257
- .uleb128 0x43
6258
- .string "p"
6259
- .byte 0x1
6260
- .byte 0x31
6261
- .4byte 0x1379
6262
- .4byte .LLST6
6263
- .uleb128 0x48
6264
- .4byte .LASF460
6265
- .4byte 0x26e2
6266
- .uleb128 0x9
6267
- .byte 0x3
6268
- .8byte .LC35
6269
- .uleb128 0x38
6270
- .8byte .LVL2
6271
- .4byte 0x26f3
6272
- .4byte 0x250e
6273
- .uleb128 0x39
6274
- .uleb128 0x1
6275
- .byte 0x50
6276
- .uleb128 0x9
6277
- .byte 0x3
6278
- .8byte .LC1
6279
- .byte 0
6280
- .uleb128 0x38
6281
- .8byte .LVL4
6282
- .4byte 0x26f3
6283
- .4byte 0x252e
6284
- .uleb128 0x39
6285
- .uleb128 0x1
6286
- .byte 0x50
6287
- .uleb128 0x4
6288
- .byte 0x8f
6289
- .sleb128 200
6290
- .byte 0x6
6291
- .uleb128 0x39
6292
- .uleb128 0x1
6293
- .byte 0x51
6294
- .uleb128 0x2
6295
- .byte 0x84
6296
- .sleb128 0
6297
- .byte 0
6298
- .uleb128 0x38
6299
- .8byte .LVL6
6300
- .4byte 0x26f3
6301
- .4byte 0x254e
6302
- .uleb128 0x39
6303
- .uleb128 0x1
6304
- .byte 0x50
6305
- .uleb128 0x4
6306
- .byte 0x8f
6307
- .sleb128 192
6308
- .byte 0x6
6309
- .uleb128 0x39
6310
- .uleb128 0x1
6311
- .byte 0x51
6312
- .uleb128 0x2
6313
- .byte 0x8b
6314
- .sleb128 0
6315
- .byte 0
6316
- .uleb128 0x38
6317
- .8byte .LVL8
6318
- .4byte 0x271e
6319
- .4byte 0x256c
6320
- .uleb128 0x39
6321
- .uleb128 0x1
6322
- .byte 0x50
6323
- .uleb128 0x2
6324
- .byte 0x85
6325
- .sleb128 0
6326
- .uleb128 0x39
6327
- .uleb128 0x1
6328
- .byte 0x51
6329
- .uleb128 0x2
6330
- .byte 0x83
6331
- .sleb128 0
6332
- .byte 0
6333
- .uleb128 0x38
6334
- .8byte .LVL9
6335
- .4byte 0x2799
6336
- .4byte 0x2596
6337
- .uleb128 0x39
6338
- .uleb128 0x1
6339
- .byte 0x50
6340
- .uleb128 0x2
6341
- .byte 0x85
6342
- .sleb128 0
6343
- .uleb128 0x39
6344
- .uleb128 0x1
6345
- .byte 0x51
6346
- .uleb128 0x2
6347
- .byte 0x83
6348
- .sleb128 0
6349
- .uleb128 0x39
6350
- .uleb128 0x1
6351
- .byte 0x52
6352
- .uleb128 0x2
6353
- .byte 0x87
6354
- .sleb128 0
6355
- .uleb128 0x39
6356
- .uleb128 0x1
6357
- .byte 0x53
6358
- .uleb128 0x2
6359
- .byte 0x88
6360
- .sleb128 0
6361
- .byte 0
6362
- .uleb128 0x38
6363
- .8byte .LVL10
6364
- .4byte 0x2735
6365
- .4byte 0x25c5
6366
- .uleb128 0x39
6367
- .uleb128 0x1
6368
- .byte 0x50
6369
- .uleb128 0x2
6370
- .byte 0x85
6371
- .sleb128 0
6372
- .uleb128 0x39
6373
- .uleb128 0x1
6374
- .byte 0x51
6375
- .uleb128 0x2
6376
- .byte 0x83
6377
- .sleb128 0
6378
- .uleb128 0x39
6379
- .uleb128 0x1
6380
- .byte 0x52
6381
- .uleb128 0x2
6382
- .byte 0x87
6383
- .sleb128 0
6384
- .uleb128 0x39
6385
- .uleb128 0x1
6386
- .byte 0x53
6387
- .uleb128 0x2
6388
- .byte 0x88
6389
- .sleb128 0
6390
- .uleb128 0x39
6391
- .uleb128 0x1
6392
- .byte 0x54
6393
- .uleb128 0x1
6394
- .byte 0x31
6395
- .byte 0
6396
- .uleb128 0x38
6397
- .8byte .LVL16
6398
- .4byte 0x26f3
6399
- .4byte 0x25e4
6400
- .uleb128 0x39
6401
- .uleb128 0x1
6402
- .byte 0x50
6403
- .uleb128 0x9
6404
- .byte 0x3
6405
- .8byte .LC4
6406
- .byte 0
6407
- .uleb128 0x38
6408
- .8byte .LVL17
6409
- .4byte 0x27a4
6410
- .4byte 0x25fc
6411
- .uleb128 0x39
6412
- .uleb128 0x1
6413
- .byte 0x50
6414
- .uleb128 0x2
6415
- .byte 0x8
6416
- .byte 0x80
6417
- .byte 0
6418
- .uleb128 0x38
6419
- .8byte .LVL20
6420
- .4byte 0x26f3
6421
- .4byte 0x2621
6422
- .uleb128 0x39
6423
- .uleb128 0x1
6424
- .byte 0x50
6425
- .uleb128 0x9
6426
- .byte 0x3
6427
- .8byte .LC5
6428
- .uleb128 0x39
6429
- .uleb128 0x1
6430
- .byte 0x51
6431
- .uleb128 0x2
6432
- .byte 0x8
6433
- .byte 0x80
6434
- .byte 0
6435
- .uleb128 0x38
6436
- .8byte .LVL23
6437
- .4byte 0x26f3
6438
- .4byte 0x263f
6439
- .uleb128 0x39
6440
- .uleb128 0x1
6441
- .byte 0x50
6442
- .uleb128 0x2
6443
- .byte 0x8b
6444
- .sleb128 0
6445
- .uleb128 0x39
6446
- .uleb128 0x1
6447
- .byte 0x51
6448
- .uleb128 0x2
6449
- .byte 0x84
6450
- .sleb128 0
6451
- .byte 0
6452
- .uleb128 0x38
6453
- .8byte .LVL24
6454
- .4byte 0x26f3
6455
- .4byte 0x265d
6456
- .uleb128 0x39
6457
- .uleb128 0x1
6458
- .byte 0x50
6459
- .uleb128 0x2
6460
- .byte 0x89
6461
- .sleb128 0
6462
- .uleb128 0x39
6463
- .uleb128 0x1
6464
- .byte 0x51
6465
- .uleb128 0x2
6466
- .byte 0x86
6467
- .sleb128 0
6468
- .byte 0
6469
- .uleb128 0x38
6470
- .8byte .LVL26
6471
- .4byte 0x271e
6472
- .4byte 0x267b
6473
- .uleb128 0x39
6474
- .uleb128 0x1
6475
- .byte 0x50
6476
- .uleb128 0x2
6477
- .byte 0x85
6478
- .sleb128 0
6479
- .uleb128 0x39
6480
- .uleb128 0x1
6481
- .byte 0x51
6482
- .uleb128 0x2
6483
- .byte 0x83
6484
- .sleb128 0
6485
- .byte 0
6486
- .uleb128 0x38
6487
- .8byte .LVL27
6488
- .4byte 0x2799
6489
- .4byte 0x26a5
6490
- .uleb128 0x39
6491
- .uleb128 0x1
6492
- .byte 0x50
6493
- .uleb128 0x2
6494
- .byte 0x85
6495
- .sleb128 0
6496
- .uleb128 0x39
6497
- .uleb128 0x1
6498
- .byte 0x51
6499
- .uleb128 0x2
6500
- .byte 0x83
6501
- .sleb128 0
6502
- .uleb128 0x39
6503
- .uleb128 0x1
6504
- .byte 0x52
6505
- .uleb128 0x2
6506
- .byte 0x87
6507
- .sleb128 0
6508
- .uleb128 0x39
6509
- .uleb128 0x1
6510
- .byte 0x53
6511
- .uleb128 0x2
6512
- .byte 0x88
6513
- .sleb128 0
6514
- .byte 0
6515
- .uleb128 0x3a
6516
- .8byte .LVL28
6517
- .4byte 0x2735
6518
- .uleb128 0x39
6519
- .uleb128 0x1
6520
- .byte 0x50
6521
- .uleb128 0x2
6522
- .byte 0x85
6523
- .sleb128 0
6524
- .uleb128 0x39
6525
- .uleb128 0x1
6526
- .byte 0x51
6527
- .uleb128 0x2
6528
- .byte 0x83
6529
- .sleb128 0
6530
- .uleb128 0x39
6531
- .uleb128 0x1
6532
- .byte 0x52
6533
- .uleb128 0x2
6534
- .byte 0x87
6535
- .sleb128 0
6536
- .uleb128 0x39
6537
- .uleb128 0x1
6538
- .byte 0x53
6539
- .uleb128 0x2
6540
- .byte 0x88
6541
- .sleb128 0
6542
- .uleb128 0x39
6543
- .uleb128 0x1
6544
- .byte 0x54
6545
- .uleb128 0x2
6546
- .byte 0x8c
6547
- .sleb128 0
6548
- .byte 0
6549
- .byte 0
6550
- .uleb128 0xb
6551
- .4byte 0xe7
6552
- .4byte 0x26e2
6553
- .uleb128 0x12
6554
- .4byte 0xce
6555
- .byte 0x9
6556
- .byte 0
6557
- .uleb128 0x8
6558
- .4byte 0x26d2
6559
- .uleb128 0x49
6560
- .4byte .LASF461
6561
- .4byte .LASF461
6562
- .byte 0x1d
6563
- .2byte 0x16c
6564
- .uleb128 0x4a
6565
- .4byte .LASF462
6566
- .4byte .LASF462
6567
- .byte 0x25
6568
- .byte 0x12
6569
- .uleb128 0x49
6570
- .4byte .LASF463
6571
- .4byte .LASF463
6572
- .byte 0x5
6573
- .2byte 0x258
6574
- .uleb128 0x4b
6575
- .4byte .LASF466
6576
- .4byte .LASF466
6577
- .uleb128 0x4a
6578
- .4byte .LASF464
6579
- .4byte .LASF464
6580
- .byte 0x26
6581
- .byte 0x5f
6582
- .uleb128 0x4a
6583
- .4byte .LASF465
6584
- .4byte .LASF465
6585
- .byte 0x27
6586
- .byte 0xb
6587
- .uleb128 0x49
6588
- .4byte .LASF466
6589
- .4byte .LASF466
6590
- .byte 0x1d
6591
- .2byte 0x16d
6592
- .uleb128 0x4a
6593
- .4byte .LASF467
6594
- .4byte .LASF467
6595
- .byte 0x28
6596
- .byte 0xe
6597
- .uleb128 0x4a
6598
- .4byte .LASF468
6599
- .4byte .LASF468
6600
- .byte 0x28
6601
- .byte 0x11
6602
- .uleb128 0x4a
6603
- .4byte .LASF469
6604
- .4byte .LASF469
6605
- .byte 0x9
6606
- .byte 0x2d
6607
- .uleb128 0x4a
6608
- .4byte .LASF470
6609
- .4byte .LASF470
6610
- .byte 0x29
6611
- .byte 0x29
6612
- .uleb128 0x4a
6613
- .4byte .LASF471
6614
- .4byte .LASF471
6615
- .byte 0x27
6616
- .byte 0xc
6617
- .uleb128 0x4a
6618
- .4byte .LASF472
6619
- .4byte .LASF472
6620
- .byte 0x21
6621
- .byte 0x11
6622
- .uleb128 0x4a
6623
- .4byte .LASF473
6624
- .4byte .LASF473
6625
- .byte 0x28
6626
- .byte 0x12
6627
- .uleb128 0x4a
6628
- .4byte .LASF474
6629
- .4byte .LASF474
6630
- .byte 0x20
6631
- .byte 0x94
6632
- .uleb128 0x49
6633
- .4byte .LASF475
6634
- .4byte .LASF475
6635
- .byte 0x5
6636
- .2byte 0x2b9
6637
- .uleb128 0x4a
6638
- .4byte .LASF476
6639
- .4byte .LASF476
6640
- .byte 0x28
6641
- .byte 0xd
6642
- .uleb128 0x49
6643
- .4byte .LASF477
6644
- .4byte .LASF477
6645
- .byte 0x1d
6646
- .2byte 0x398
6647
- .byte 0
6648
- .section .debug_abbrev,"",@progbits
6649
-.Ldebug_abbrev0:
6650
- .uleb128 0x1
6651
- .uleb128 0x11
6652
- .byte 0x1
6653
- .uleb128 0x25
6654
- .uleb128 0xe
6655
- .uleb128 0x13
6656
- .uleb128 0xb
6657
- .uleb128 0x3
6658
- .uleb128 0xe
6659
- .uleb128 0x1b
6660
- .uleb128 0xe
6661
- .uleb128 0x55
6662
- .uleb128 0x17
6663
- .uleb128 0x11
6664
- .uleb128 0x1
6665
- .uleb128 0x10
6666
- .uleb128 0x17
6667
- .byte 0
6668
- .byte 0
6669
- .uleb128 0x2
6670
- .uleb128 0x16
6671
- .byte 0
6672
- .uleb128 0x3
6673
- .uleb128 0xe
6674
- .uleb128 0x3a
6675
- .uleb128 0xb
6676
- .uleb128 0x3b
6677
- .uleb128 0xb
6678
- .uleb128 0x49
6679
- .uleb128 0x13
6680
- .byte 0
6681
- .byte 0
6682
- .uleb128 0x3
6683
- .uleb128 0x24
6684
- .byte 0
6685
- .uleb128 0xb
6686
- .uleb128 0xb
6687
- .uleb128 0x3e
6688
- .uleb128 0xb
6689
- .uleb128 0x3
6690
- .uleb128 0xe
6691
- .byte 0
6692
- .byte 0
6693
- .uleb128 0x4
6694
- .uleb128 0x35
6695
- .byte 0
6696
- .uleb128 0x49
6697
- .uleb128 0x13
6698
- .byte 0
6699
- .byte 0
6700
- .uleb128 0x5
6701
- .uleb128 0x34
6702
- .byte 0
6703
- .uleb128 0x3
6704
- .uleb128 0xe
6705
- .uleb128 0x3a
6706
- .uleb128 0xb
6707
- .uleb128 0x3b
6708
- .uleb128 0xb
6709
- .uleb128 0x49
6710
- .uleb128 0x13
6711
- .uleb128 0x3f
6712
- .uleb128 0x19
6713
- .uleb128 0x3c
6714
- .uleb128 0x19
6715
- .byte 0
6716
- .byte 0
6717
- .uleb128 0x6
6718
- .uleb128 0x24
6719
- .byte 0
6720
- .uleb128 0xb
6721
- .uleb128 0xb
6722
- .uleb128 0x3e
6723
- .uleb128 0xb
6724
- .uleb128 0x3
6725
- .uleb128 0x8
6726
- .byte 0
6727
- .byte 0
6728
- .uleb128 0x7
6729
- .uleb128 0x16
6730
- .byte 0
6731
- .uleb128 0x3
6732
- .uleb128 0x8
6733
- .uleb128 0x3a
6734
- .uleb128 0xb
6735
- .uleb128 0x3b
6736
- .uleb128 0xb
6737
- .uleb128 0x49
6738
- .uleb128 0x13
6739
- .byte 0
6740
- .byte 0
6741
- .uleb128 0x8
6742
- .uleb128 0x26
6743
- .byte 0
6744
- .uleb128 0x49
6745
- .uleb128 0x13
6746
- .byte 0
6747
- .byte 0
6748
- .uleb128 0x9
6749
- .uleb128 0xf
6750
- .byte 0
6751
- .uleb128 0xb
6752
- .uleb128 0xb
6753
- .uleb128 0x49
6754
- .uleb128 0x13
6755
- .byte 0
6756
- .byte 0
6757
- .uleb128 0xa
6758
- .uleb128 0xf
6759
- .byte 0
6760
- .uleb128 0xb
6761
- .uleb128 0xb
6762
- .byte 0
6763
- .byte 0
6764
- .uleb128 0xb
6765
- .uleb128 0x1
6766
- .byte 0x1
6767
- .uleb128 0x49
6768
- .uleb128 0x13
6769
- .uleb128 0x1
6770
- .uleb128 0x13
6771
- .byte 0
6772
- .byte 0
6773
- .uleb128 0xc
6774
- .uleb128 0x21
6775
- .byte 0
6776
- .byte 0
6777
- .byte 0
6778
- .uleb128 0xd
6779
- .uleb128 0x34
6780
- .byte 0
6781
- .uleb128 0x3
6782
- .uleb128 0xe
6783
- .uleb128 0x3a
6784
- .uleb128 0xb
6785
- .uleb128 0x3b
6786
- .uleb128 0x5
6787
- .uleb128 0x49
6788
- .uleb128 0x13
6789
- .uleb128 0x3f
6790
- .uleb128 0x19
6791
- .uleb128 0x3c
6792
- .uleb128 0x19
6793
- .byte 0
6794
- .byte 0
6795
- .uleb128 0xe
6796
- .uleb128 0x13
6797
- .byte 0x1
6798
- .uleb128 0x3
6799
- .uleb128 0xe
6800
- .uleb128 0xb
6801
- .uleb128 0xb
6802
- .uleb128 0x3a
6803
- .uleb128 0xb
6804
- .uleb128 0x3b
6805
- .uleb128 0xb
6806
- .uleb128 0x1
6807
- .uleb128 0x13
6808
- .byte 0
6809
- .byte 0
6810
- .uleb128 0xf
6811
- .uleb128 0xd
6812
- .byte 0
6813
- .uleb128 0x3
6814
- .uleb128 0xe
6815
- .uleb128 0x3a
6816
- .uleb128 0xb
6817
- .uleb128 0x3b
6818
- .uleb128 0xb
6819
- .uleb128 0x49
6820
- .uleb128 0x13
6821
- .uleb128 0x38
6822
- .uleb128 0xb
6823
- .byte 0
6824
- .byte 0
6825
- .uleb128 0x10
6826
- .uleb128 0xd
6827
- .byte 0
6828
- .uleb128 0x3
6829
- .uleb128 0x8
6830
- .uleb128 0x3a
6831
- .uleb128 0xb
6832
- .uleb128 0x3b
6833
- .uleb128 0xb
6834
- .uleb128 0x49
6835
- .uleb128 0x13
6836
- .uleb128 0x38
6837
- .uleb128 0xb
6838
- .byte 0
6839
- .byte 0
6840
- .uleb128 0x11
6841
- .uleb128 0x26
6842
- .byte 0
6843
- .byte 0
6844
- .byte 0
6845
- .uleb128 0x12
6846
- .uleb128 0x21
6847
- .byte 0
6848
- .uleb128 0x49
6849
- .uleb128 0x13
6850
- .uleb128 0x2f
6851
- .uleb128 0xb
6852
- .byte 0
6853
- .byte 0
6854
- .uleb128 0x13
6855
- .uleb128 0x15
6856
- .byte 0x1
6857
- .uleb128 0x27
6858
- .uleb128 0x19
6859
- .uleb128 0x49
6860
- .uleb128 0x13
6861
- .uleb128 0x1
6862
- .uleb128 0x13
6863
- .byte 0
6864
- .byte 0
6865
- .uleb128 0x14
6866
- .uleb128 0x5
6867
- .byte 0
6868
- .uleb128 0x49
6869
- .uleb128 0x13
6870
- .byte 0
6871
- .byte 0
6872
- .uleb128 0x15
6873
- .uleb128 0x13
6874
- .byte 0x1
6875
- .uleb128 0xb
6876
- .uleb128 0x5
6877
- .uleb128 0x3a
6878
- .uleb128 0xb
6879
- .uleb128 0x3b
6880
- .uleb128 0xb
6881
- .uleb128 0x1
6882
- .uleb128 0x13
6883
- .byte 0
6884
- .byte 0
6885
- .uleb128 0x16
6886
- .uleb128 0xd
6887
- .byte 0
6888
- .uleb128 0x3
6889
- .uleb128 0xe
6890
- .uleb128 0x3a
6891
- .uleb128 0xb
6892
- .uleb128 0x3b
6893
- .uleb128 0xb
6894
- .uleb128 0x49
6895
- .uleb128 0x13
6896
- .uleb128 0x38
6897
- .uleb128 0x5
6898
- .byte 0
6899
- .byte 0
6900
- .uleb128 0x17
6901
- .uleb128 0x21
6902
- .byte 0
6903
- .uleb128 0x49
6904
- .uleb128 0x13
6905
- .uleb128 0x2f
6906
- .uleb128 0x5
6907
- .byte 0
6908
- .byte 0
6909
- .uleb128 0x18
6910
- .uleb128 0x13
6911
- .byte 0x1
6912
- .uleb128 0x3
6913
- .uleb128 0x8
6914
- .uleb128 0xb
6915
- .uleb128 0x5
6916
- .uleb128 0x3a
6917
- .uleb128 0xb
6918
- .uleb128 0x3b
6919
- .uleb128 0xb
6920
- .uleb128 0x1
6921
- .uleb128 0x13
6922
- .byte 0
6923
- .byte 0
6924
- .uleb128 0x19
6925
- .uleb128 0x34
6926
- .byte 0
6927
- .uleb128 0x3
6928
- .uleb128 0x8
6929
- .uleb128 0x3a
6930
- .uleb128 0xb
6931
- .uleb128 0x3b
6932
- .uleb128 0xb
6933
- .uleb128 0x49
6934
- .uleb128 0x13
6935
- .uleb128 0x3f
6936
- .uleb128 0x19
6937
- .uleb128 0x3c
6938
- .uleb128 0x19
6939
- .byte 0
6940
- .byte 0
6941
- .uleb128 0x1a
6942
- .uleb128 0x13
6943
- .byte 0x1
6944
- .uleb128 0xb
6945
- .uleb128 0xb
6946
- .uleb128 0x3a
6947
- .uleb128 0xb
6948
- .uleb128 0x3b
6949
- .uleb128 0xb
6950
- .uleb128 0x1
6951
- .uleb128 0x13
6952
- .byte 0
6953
- .byte 0
6954
- .uleb128 0x1b
6955
- .uleb128 0x4
6956
- .byte 0x1
6957
- .uleb128 0x3
6958
- .uleb128 0xe
6959
- .uleb128 0xb
6960
- .uleb128 0xb
6961
- .uleb128 0x49
6962
- .uleb128 0x13
6963
- .uleb128 0x3a
6964
- .uleb128 0xb
6965
- .uleb128 0x3b
6966
- .uleb128 0xb
6967
- .uleb128 0x1
6968
- .uleb128 0x13
6969
- .byte 0
6970
- .byte 0
6971
- .uleb128 0x1c
6972
- .uleb128 0x28
6973
- .byte 0
6974
- .uleb128 0x3
6975
- .uleb128 0xe
6976
- .uleb128 0x1c
6977
- .uleb128 0xb
6978
- .byte 0
6979
- .byte 0
6980
- .uleb128 0x1d
6981
- .uleb128 0x28
6982
- .byte 0
6983
- .uleb128 0x3
6984
- .uleb128 0xe
6985
- .uleb128 0x1c
6986
- .uleb128 0xd
6987
- .byte 0
6988
- .byte 0
6989
- .uleb128 0x1e
6990
- .uleb128 0x13
6991
- .byte 0x1
6992
- .uleb128 0x3
6993
- .uleb128 0xe
6994
- .uleb128 0xb
6995
- .uleb128 0xb
6996
- .uleb128 0x3a
6997
- .uleb128 0xb
6998
- .uleb128 0x3b
6999
- .uleb128 0x5
7000
- .uleb128 0x1
7001
- .uleb128 0x13
7002
- .byte 0
7003
- .byte 0
7004
- .uleb128 0x1f
7005
- .uleb128 0xd
7006
- .byte 0
7007
- .uleb128 0x3
7008
- .uleb128 0xe
7009
- .uleb128 0x3a
7010
- .uleb128 0xb
7011
- .uleb128 0x3b
7012
- .uleb128 0x5
7013
- .uleb128 0x49
7014
- .uleb128 0x13
7015
- .uleb128 0x38
7016
- .uleb128 0xb
7017
- .byte 0
7018
- .byte 0
7019
- .uleb128 0x20
7020
- .uleb128 0x16
7021
- .byte 0
7022
- .uleb128 0x3
7023
- .uleb128 0xe
7024
- .uleb128 0x3a
7025
- .uleb128 0xb
7026
- .uleb128 0x3b
7027
- .uleb128 0x5
7028
- .uleb128 0x49
7029
- .uleb128 0x13
7030
- .byte 0
7031
- .byte 0
7032
- .uleb128 0x21
7033
- .uleb128 0xd
7034
- .byte 0
7035
- .uleb128 0x3
7036
- .uleb128 0x8
7037
- .uleb128 0x3a
7038
- .uleb128 0xb
7039
- .uleb128 0x3b
7040
- .uleb128 0x5
7041
- .uleb128 0x49
7042
- .uleb128 0x13
7043
- .uleb128 0x38
7044
- .uleb128 0xb
7045
- .byte 0
7046
- .byte 0
7047
- .uleb128 0x22
7048
- .uleb128 0x13
7049
- .byte 0x1
7050
- .uleb128 0x3
7051
- .uleb128 0xe
7052
- .uleb128 0xb
7053
- .uleb128 0x5
7054
- .uleb128 0x3a
7055
- .uleb128 0xb
7056
- .uleb128 0x3b
7057
- .uleb128 0x5
7058
- .uleb128 0x1
7059
- .uleb128 0x13
7060
- .byte 0
7061
- .byte 0
7062
- .uleb128 0x23
7063
- .uleb128 0xd
7064
- .byte 0
7065
- .uleb128 0x3
7066
- .uleb128 0xe
7067
- .uleb128 0x3a
7068
- .uleb128 0xb
7069
- .uleb128 0x3b
7070
- .uleb128 0x5
7071
- .uleb128 0x49
7072
- .uleb128 0x13
7073
- .uleb128 0x38
7074
- .uleb128 0x5
7075
- .byte 0
7076
- .byte 0
7077
- .uleb128 0x24
7078
- .uleb128 0xd
7079
- .byte 0
7080
- .uleb128 0x3
7081
- .uleb128 0x8
7082
- .uleb128 0x3a
7083
- .uleb128 0xb
7084
- .uleb128 0x3b
7085
- .uleb128 0x5
7086
- .uleb128 0x49
7087
- .uleb128 0x13
7088
- .uleb128 0x38
7089
- .uleb128 0x5
7090
- .byte 0
7091
- .byte 0
7092
- .uleb128 0x25
7093
- .uleb128 0x4
7094
- .byte 0x1
7095
- .uleb128 0xb
7096
- .uleb128 0xb
7097
- .uleb128 0x49
7098
- .uleb128 0x13
7099
- .uleb128 0x3a
7100
- .uleb128 0xb
7101
- .uleb128 0x3b
7102
- .uleb128 0xb
7103
- .uleb128 0x1
7104
- .uleb128 0x13
7105
- .byte 0
7106
- .byte 0
7107
- .uleb128 0x26
7108
- .uleb128 0x13
7109
- .byte 0x1
7110
- .uleb128 0x3
7111
- .uleb128 0xe
7112
- .uleb128 0xb
7113
- .uleb128 0x5
7114
- .uleb128 0x3a
7115
- .uleb128 0xb
7116
- .uleb128 0x3b
7117
- .uleb128 0xb
7118
- .uleb128 0x1
7119
- .uleb128 0x13
7120
- .byte 0
7121
- .byte 0
7122
- .uleb128 0x27
7123
- .uleb128 0x13
7124
- .byte 0
7125
- .uleb128 0x3
7126
- .uleb128 0xe
7127
- .uleb128 0x3c
7128
- .uleb128 0x19
7129
- .byte 0
7130
- .byte 0
7131
- .uleb128 0x28
7132
- .uleb128 0x15
7133
- .byte 0x1
7134
- .uleb128 0x27
7135
- .uleb128 0x19
7136
- .uleb128 0x1
7137
- .uleb128 0x13
7138
- .byte 0
7139
- .byte 0
7140
- .uleb128 0x29
7141
- .uleb128 0x4
7142
- .byte 0x1
7143
- .uleb128 0x3
7144
- .uleb128 0xe
7145
- .uleb128 0xb
7146
- .uleb128 0xb
7147
- .uleb128 0x49
7148
- .uleb128 0x13
7149
- .uleb128 0x3a
7150
- .uleb128 0xb
7151
- .uleb128 0x3b
7152
- .uleb128 0x5
7153
- .uleb128 0x1
7154
- .uleb128 0x13
7155
- .byte 0
7156
- .byte 0
7157
- .uleb128 0x2a
7158
- .uleb128 0x34
7159
- .byte 0
7160
- .uleb128 0x3
7161
- .uleb128 0xe
7162
- .uleb128 0x3a
7163
- .uleb128 0xb
7164
- .uleb128 0x3b
7165
- .uleb128 0xb
7166
- .uleb128 0x49
7167
- .uleb128 0x13
7168
- .uleb128 0x2
7169
- .uleb128 0x18
7170
- .byte 0
7171
- .byte 0
7172
- .uleb128 0x2b
7173
- .uleb128 0x34
7174
- .byte 0
7175
- .uleb128 0x3
7176
- .uleb128 0x8
7177
- .uleb128 0x3a
7178
- .uleb128 0xb
7179
- .uleb128 0x3b
7180
- .uleb128 0xb
7181
- .uleb128 0x49
7182
- .uleb128 0x13
7183
- .uleb128 0x3f
7184
- .uleb128 0x19
7185
- .byte 0
7186
- .byte 0
7187
- .uleb128 0x2c
7188
- .uleb128 0x17
7189
- .byte 0x1
7190
- .uleb128 0x3
7191
- .uleb128 0xe
7192
- .uleb128 0xb
7193
- .uleb128 0xb
7194
- .uleb128 0x3a
7195
- .uleb128 0xb
7196
- .uleb128 0x3b
7197
- .uleb128 0xb
7198
- .uleb128 0x1
7199
- .uleb128 0x13
7200
- .byte 0
7201
- .byte 0
7202
- .uleb128 0x2d
7203
- .uleb128 0xd
7204
- .byte 0
7205
- .uleb128 0x3
7206
- .uleb128 0x8
7207
- .uleb128 0x3a
7208
- .uleb128 0xb
7209
- .uleb128 0x3b
7210
- .uleb128 0xb
7211
- .uleb128 0x49
7212
- .uleb128 0x13
7213
- .byte 0
7214
- .byte 0
7215
- .uleb128 0x2e
7216
- .uleb128 0xd
7217
- .byte 0
7218
- .uleb128 0x3
7219
- .uleb128 0xe
7220
- .uleb128 0x3a
7221
- .uleb128 0xb
7222
- .uleb128 0x3b
7223
- .uleb128 0xb
7224
- .uleb128 0x49
7225
- .uleb128 0x13
7226
- .byte 0
7227
- .byte 0
7228
- .uleb128 0x2f
7229
- .uleb128 0x34
7230
- .byte 0
7231
- .uleb128 0x3
7232
- .uleb128 0xe
7233
- .uleb128 0x3a
7234
- .uleb128 0xb
7235
- .uleb128 0x3b
7236
- .uleb128 0x5
7237
- .uleb128 0x49
7238
- .uleb128 0x13
7239
- .uleb128 0x3f
7240
- .uleb128 0x19
7241
- .uleb128 0x2
7242
- .uleb128 0x18
7243
- .byte 0
7244
- .byte 0
7245
- .uleb128 0x30
7246
- .uleb128 0x2e
7247
- .byte 0x1
7248
- .uleb128 0x3f
7249
- .uleb128 0x19
7250
- .uleb128 0x3
7251
- .uleb128 0xe
7252
- .uleb128 0x3a
7253
- .uleb128 0xb
7254
- .uleb128 0x3b
7255
- .uleb128 0xb
7256
- .uleb128 0x27
7257
- .uleb128 0x19
7258
- .uleb128 0x49
7259
- .uleb128 0x13
7260
- .uleb128 0x11
7261
- .uleb128 0x1
7262
- .uleb128 0x12
7263
- .uleb128 0x7
7264
- .uleb128 0x40
7265
- .uleb128 0x18
7266
- .uleb128 0x2117
7267
- .uleb128 0x19
7268
- .uleb128 0x1
7269
- .uleb128 0x13
7270
- .byte 0
7271
- .byte 0
7272
- .uleb128 0x31
7273
- .uleb128 0x5
7274
- .byte 0
7275
- .uleb128 0x3
7276
- .uleb128 0xe
7277
- .uleb128 0x3a
7278
- .uleb128 0xb
7279
- .uleb128 0x3b
7280
- .uleb128 0xb
7281
- .uleb128 0x49
7282
- .uleb128 0x13
7283
- .uleb128 0x2
7284
- .uleb128 0x17
7285
- .byte 0
7286
- .byte 0
7287
- .uleb128 0x32
7288
- .uleb128 0x34
7289
- .byte 0
7290
- .uleb128 0x3
7291
- .uleb128 0x8
7292
- .uleb128 0x3a
7293
- .uleb128 0xb
7294
- .uleb128 0x3b
7295
- .uleb128 0xb
7296
- .uleb128 0x49
7297
- .uleb128 0x13
7298
- .uleb128 0x2
7299
- .uleb128 0x18
7300
- .byte 0
7301
- .byte 0
7302
- .uleb128 0x33
7303
- .uleb128 0x1d
7304
- .byte 0x1
7305
- .uleb128 0x31
7306
- .uleb128 0x13
7307
- .uleb128 0x52
7308
- .uleb128 0x1
7309
- .uleb128 0x55
7310
- .uleb128 0x17
7311
- .uleb128 0x58
7312
- .uleb128 0xb
7313
- .uleb128 0x59
7314
- .uleb128 0xb
7315
- .uleb128 0x1
7316
- .uleb128 0x13
7317
- .byte 0
7318
- .byte 0
7319
- .uleb128 0x34
7320
- .uleb128 0x5
7321
- .byte 0
7322
- .uleb128 0x31
7323
- .uleb128 0x13
7324
- .uleb128 0x2
7325
- .uleb128 0x17
7326
- .byte 0
7327
- .byte 0
7328
- .uleb128 0x35
7329
- .uleb128 0xb
7330
- .byte 0x1
7331
- .uleb128 0x55
7332
- .uleb128 0x17
7333
- .byte 0
7334
- .byte 0
7335
- .uleb128 0x36
7336
- .uleb128 0x34
7337
- .byte 0
7338
- .uleb128 0x31
7339
- .uleb128 0x13
7340
- .uleb128 0x2
7341
- .uleb128 0x17
7342
- .byte 0
7343
- .byte 0
7344
- .uleb128 0x37
7345
- .uleb128 0x34
7346
- .byte 0
7347
- .uleb128 0x31
7348
- .uleb128 0x13
7349
- .byte 0
7350
- .byte 0
7351
- .uleb128 0x38
7352
- .uleb128 0x4109
7353
- .byte 0x1
7354
- .uleb128 0x11
7355
- .uleb128 0x1
7356
- .uleb128 0x31
7357
- .uleb128 0x13
7358
- .uleb128 0x1
7359
- .uleb128 0x13
7360
- .byte 0
7361
- .byte 0
7362
- .uleb128 0x39
7363
- .uleb128 0x410a
7364
- .byte 0
7365
- .uleb128 0x2
7366
- .uleb128 0x18
7367
- .uleb128 0x2111
7368
- .uleb128 0x18
7369
- .byte 0
7370
- .byte 0
7371
- .uleb128 0x3a
7372
- .uleb128 0x4109
7373
- .byte 0x1
7374
- .uleb128 0x11
7375
- .uleb128 0x1
7376
- .uleb128 0x31
7377
- .uleb128 0x13
7378
- .byte 0
7379
- .byte 0
7380
- .uleb128 0x3b
7381
- .uleb128 0x1d
7382
- .byte 0x1
7383
- .uleb128 0x31
7384
- .uleb128 0x13
7385
- .uleb128 0x52
7386
- .uleb128 0x1
7387
- .uleb128 0x55
7388
- .uleb128 0x17
7389
- .uleb128 0x58
7390
- .uleb128 0xb
7391
- .uleb128 0x59
7392
- .uleb128 0xb
7393
- .byte 0
7394
- .byte 0
7395
- .uleb128 0x3c
7396
- .uleb128 0x5
7397
- .byte 0
7398
- .uleb128 0x31
7399
- .uleb128 0x13
7400
- .byte 0
7401
- .byte 0
7402
- .uleb128 0x3d
7403
- .uleb128 0x34
7404
- .byte 0
7405
- .uleb128 0x31
7406
- .uleb128 0x13
7407
- .uleb128 0x2
7408
- .uleb128 0x18
7409
- .byte 0
7410
- .byte 0
7411
- .uleb128 0x3e
7412
- .uleb128 0x2e
7413
- .byte 0x1
7414
- .uleb128 0x3
7415
- .uleb128 0xe
7416
- .uleb128 0x3a
7417
- .uleb128 0xb
7418
- .uleb128 0x3b
7419
- .uleb128 0xb
7420
- .uleb128 0x27
7421
- .uleb128 0x19
7422
- .uleb128 0x49
7423
- .uleb128 0x13
7424
- .uleb128 0x20
7425
- .uleb128 0xb
7426
- .uleb128 0x1
7427
- .uleb128 0x13
7428
- .byte 0
7429
- .byte 0
7430
- .uleb128 0x3f
7431
- .uleb128 0x5
7432
- .byte 0
7433
- .uleb128 0x3
7434
- .uleb128 0xe
7435
- .uleb128 0x3a
7436
- .uleb128 0xb
7437
- .uleb128 0x3b
7438
- .uleb128 0xb
7439
- .uleb128 0x49
7440
- .uleb128 0x13
7441
- .byte 0
7442
- .byte 0
7443
- .uleb128 0x40
7444
- .uleb128 0x34
7445
- .byte 0
7446
- .uleb128 0x3
7447
- .uleb128 0x8
7448
- .uleb128 0x3a
7449
- .uleb128 0xb
7450
- .uleb128 0x3b
7451
- .uleb128 0xb
7452
- .uleb128 0x49
7453
- .uleb128 0x13
7454
- .byte 0
7455
- .byte 0
7456
- .uleb128 0x41
7457
- .uleb128 0x34
7458
- .byte 0
7459
- .uleb128 0x3
7460
- .uleb128 0xe
7461
- .uleb128 0x3a
7462
- .uleb128 0xb
7463
- .uleb128 0x3b
7464
- .uleb128 0xb
7465
- .uleb128 0x49
7466
- .uleb128 0x13
7467
- .byte 0
7468
- .byte 0
7469
- .uleb128 0x42
7470
- .uleb128 0x34
7471
- .byte 0
7472
- .uleb128 0x3
7473
- .uleb128 0xe
7474
- .uleb128 0x3a
7475
- .uleb128 0xb
7476
- .uleb128 0x3b
7477
- .uleb128 0xb
7478
- .uleb128 0x49
7479
- .uleb128 0x13
7480
- .uleb128 0x2
7481
- .uleb128 0x17
7482
- .byte 0
7483
- .byte 0
7484
- .uleb128 0x43
7485
- .uleb128 0x34
7486
- .byte 0
7487
- .uleb128 0x3
7488
- .uleb128 0x8
7489
- .uleb128 0x3a
7490
- .uleb128 0xb
7491
- .uleb128 0x3b
7492
- .uleb128 0xb
7493
- .uleb128 0x49
7494
- .uleb128 0x13
7495
- .uleb128 0x2
7496
- .uleb128 0x17
7497
- .byte 0
7498
- .byte 0
7499
- .uleb128 0x44
7500
- .uleb128 0xa
7501
- .byte 0
7502
- .uleb128 0x3
7503
- .uleb128 0xe
7504
- .uleb128 0x3a
7505
- .uleb128 0xb
7506
- .uleb128 0x3b
7507
- .uleb128 0xb
7508
- .uleb128 0x11
7509
- .uleb128 0x1
7510
- .byte 0
7511
- .byte 0
7512
- .uleb128 0x45
7513
- .uleb128 0x4109
7514
- .byte 0
7515
- .uleb128 0x11
7516
- .uleb128 0x1
7517
- .uleb128 0x31
7518
- .uleb128 0x13
7519
- .byte 0
7520
- .byte 0
7521
- .uleb128 0x46
7522
- .uleb128 0x2e
7523
- .byte 0x1
7524
- .uleb128 0x3
7525
- .uleb128 0xe
7526
- .uleb128 0x3a
7527
- .uleb128 0xb
7528
- .uleb128 0x3b
7529
- .uleb128 0xb
7530
- .uleb128 0x27
7531
- .uleb128 0x19
7532
- .uleb128 0x49
7533
- .uleb128 0x13
7534
- .uleb128 0x11
7535
- .uleb128 0x1
7536
- .uleb128 0x12
7537
- .uleb128 0x7
7538
- .uleb128 0x40
7539
- .uleb128 0x18
7540
- .uleb128 0x2117
7541
- .uleb128 0x19
7542
- .uleb128 0x1
7543
- .uleb128 0x13
7544
- .byte 0
7545
- .byte 0
7546
- .uleb128 0x47
7547
- .uleb128 0x5
7548
- .byte 0
7549
- .uleb128 0x3
7550
- .uleb128 0x8
7551
- .uleb128 0x3a
7552
- .uleb128 0xb
7553
- .uleb128 0x3b
7554
- .uleb128 0xb
7555
- .uleb128 0x49
7556
- .uleb128 0x13
7557
- .uleb128 0x2
7558
- .uleb128 0x17
7559
- .byte 0
7560
- .byte 0
7561
- .uleb128 0x48
7562
- .uleb128 0x34
7563
- .byte 0
7564
- .uleb128 0x3
7565
- .uleb128 0xe
7566
- .uleb128 0x49
7567
- .uleb128 0x13
7568
- .uleb128 0x34
7569
- .uleb128 0x19
7570
- .uleb128 0x2
7571
- .uleb128 0x18
7572
- .byte 0
7573
- .byte 0
7574
- .uleb128 0x49
7575
- .uleb128 0x2e
7576
- .byte 0
7577
- .uleb128 0x3f
7578
- .uleb128 0x19
7579
- .uleb128 0x3c
7580
- .uleb128 0x19
7581
- .uleb128 0x6e
7582
- .uleb128 0xe
7583
- .uleb128 0x3
7584
- .uleb128 0xe
7585
- .uleb128 0x3a
7586
- .uleb128 0xb
7587
- .uleb128 0x3b
7588
- .uleb128 0x5
7589
- .byte 0
7590
- .byte 0
7591
- .uleb128 0x4a
7592
- .uleb128 0x2e
7593
- .byte 0
7594
- .uleb128 0x3f
7595
- .uleb128 0x19
7596
- .uleb128 0x3c
7597
- .uleb128 0x19
7598
- .uleb128 0x6e
7599
- .uleb128 0xe
7600
- .uleb128 0x3
7601
- .uleb128 0xe
7602
- .uleb128 0x3a
7603
- .uleb128 0xb
7604
- .uleb128 0x3b
7605
- .uleb128 0xb
7606
- .byte 0
7607
- .byte 0
7608
- .uleb128 0x4b
7609
- .uleb128 0x2e
7610
- .byte 0
7611
- .uleb128 0x3f
7612
- .uleb128 0x19
7613
- .uleb128 0x3c
7614
- .uleb128 0x19
7615
- .uleb128 0x6e
7616
- .uleb128 0xe
7617
- .uleb128 0x3
7618
- .uleb128 0xe
7619
- .byte 0
7620
- .byte 0
7621
- .byte 0
7622
- .section .debug_loc,"",@progbits
7623
-.Ldebug_loc0:
7624
-.LLST15:
7625
- .8byte .LVL61
7626
- .8byte .LVL64-1
7627
- .2byte 0x1
7628
- .byte 0x50
7629
- .8byte .LVL64-1
7630
- .8byte .LVL80
7631
- .2byte 0x1
7632
- .byte 0x63
7633
- .8byte .LVL80
7634
- .8byte .LVL81
7635
- .2byte 0x4
7636
- .byte 0xf3
7637
- .uleb128 0x1
7638
- .byte 0x50
7639
- .byte 0x9f
7640
- .8byte .LVL81
7641
- .8byte .LFE271
7642
- .2byte 0x1
7643
- .byte 0x63
7644
- .8byte 0
7645
- .8byte 0
7646
-.LLST16:
7647
- .8byte .LVL61
7648
- .8byte .LVL63
7649
- .2byte 0x1
7650
- .byte 0x51
7651
- .8byte .LVL63
7652
- .8byte .LVL64-1
7653
- .2byte 0x1
7654
- .byte 0x52
7655
- .8byte .LVL64-1
7656
- .8byte .LVL80
7657
- .2byte 0x1
7658
- .byte 0x64
7659
- .8byte .LVL80
7660
- .8byte .LVL81
7661
- .2byte 0x4
7662
- .byte 0xf3
7663
- .uleb128 0x1
7664
- .byte 0x51
7665
- .byte 0x9f
7666
- .8byte .LVL81
7667
- .8byte .LFE271
7668
- .2byte 0x1
7669
- .byte 0x64
7670
- .8byte 0
7671
- .8byte 0
7672
-.LLST17:
7673
- .8byte .LVL62
7674
- .8byte .LVL63
7675
- .2byte 0x1
7676
- .byte 0x51
7677
- .8byte .LVL63
7678
- .8byte .LVL64-1
7679
- .2byte 0x1
7680
- .byte 0x52
7681
- .8byte .LVL64-1
7682
- .8byte .LVL79
7683
- .2byte 0x1
7684
- .byte 0x64
7685
- .8byte .LVL81
7686
- .8byte .LFE271
7687
- .2byte 0x1
7688
- .byte 0x64
7689
- .8byte 0
7690
- .8byte 0
7691
-.LLST18:
7692
- .8byte .LVL62
7693
- .8byte .LVL64-1
7694
- .2byte 0x1
7695
- .byte 0x50
7696
- .8byte .LVL64-1
7697
- .8byte .LVL79
7698
- .2byte 0x1
7699
- .byte 0x63
7700
- .8byte .LVL81
7701
- .8byte .LFE271
7702
- .2byte 0x1
7703
- .byte 0x63
7704
- .8byte 0
7705
- .8byte 0
7706
-.LLST19:
7707
- .8byte .LVL66
7708
- .8byte .LVL67
7709
- .2byte 0x2
7710
- .byte 0x30
7711
- .byte 0x9f
7712
- .8byte .LVL67
7713
- .8byte .LVL68
7714
- .2byte 0x1
7715
- .byte 0x51
7716
- .8byte .LVL73
7717
- .8byte .LVL75
7718
- .2byte 0x1
7719
- .byte 0x51
7720
- .8byte .LVL81
7721
- .8byte .LVL83
7722
- .2byte 0x1
7723
- .byte 0x51
7724
- .8byte 0
7725
- .8byte 0
7726
-.LLST20:
7727
- .8byte .LVL64
7728
- .8byte .LVL65
7729
- .2byte 0x2
7730
- .byte 0x30
7731
- .byte 0x9f
7732
- .8byte .LVL65
7733
- .8byte .LVL69
7734
- .2byte 0x1
7735
- .byte 0x66
7736
- .8byte .LVL69
7737
- .8byte .LVL72
7738
- .2byte 0x3
7739
- .byte 0x86
7740
- .sleb128 -1
7741
- .byte 0x9f
7742
- .8byte .LVL72
7743
- .8byte .LVL79
7744
- .2byte 0x1
7745
- .byte 0x66
7746
- .8byte .LVL81
7747
- .8byte .LVL84
7748
- .2byte 0x1
7749
- .byte 0x66
7750
- .8byte 0
7751
- .8byte 0
7752
-.LLST21:
7753
- .8byte .LVL64
7754
- .8byte .LVL65
7755
- .2byte 0x6
7756
- .byte 0x9e
7757
- .uleb128 0x4
7758
- .4byte 0x80808080
7759
- .8byte .LVL65
7760
- .8byte .LVL79
7761
- .2byte 0x1
7762
- .byte 0x65
7763
- .8byte .LVL81
7764
- .8byte .LVL84
7765
- .2byte 0x1
7766
- .byte 0x65
7767
- .8byte 0
7768
- .8byte 0
7769
-.LLST22:
7770
- .8byte .LVL64
7771
- .8byte .LVL65
7772
- .2byte 0x6
7773
- .byte 0xc
7774
- .4byte 0x40404040
7775
- .byte 0x9f
7776
- .8byte .LVL65
7777
- .8byte .LVL79
7778
- .2byte 0x1
7779
- .byte 0x67
7780
- .8byte .LVL81
7781
- .8byte .LVL84
7782
- .2byte 0x1
7783
- .byte 0x67
7784
- .8byte 0
7785
- .8byte 0
7786
-.LLST23:
7787
- .8byte .LVL62
7788
- .8byte .LVL65
7789
- .2byte 0x2
7790
- .byte 0x30
7791
- .byte 0x9f
7792
- .8byte 0
7793
- .8byte 0
7794
-.LLST24:
7795
- .8byte .LVL64
7796
- .8byte .LVL80
7797
- .2byte 0x1
7798
- .byte 0x63
7799
- .8byte .LVL80
7800
- .8byte .LVL81
7801
- .2byte 0x4
7802
- .byte 0xf3
7803
- .uleb128 0x1
7804
- .byte 0x50
7805
- .byte 0x9f
7806
- .8byte .LVL81
7807
- .8byte .LFE271
7808
- .2byte 0x1
7809
- .byte 0x63
7810
- .8byte 0
7811
- .8byte 0
7812
-.LLST25:
7813
- .8byte .LVL62
7814
- .8byte .LVL68
7815
- .2byte 0x3
7816
- .byte 0x9
7817
- .byte 0xff
7818
- .byte 0x9f
7819
- .8byte .LVL72
7820
- .8byte .LVL74
7821
- .2byte 0x3
7822
- .byte 0x9
7823
- .byte 0xff
7824
- .byte 0x9f
7825
- .8byte .LVL74
7826
- .8byte .LVL76-1
7827
- .2byte 0x1
7828
- .byte 0x55
7829
- .8byte .LVL76-1
7830
- .8byte .LVL79
7831
- .2byte 0x1
7832
- .byte 0x6c
7833
- .8byte .LVL81
7834
- .8byte .LFE271
7835
- .2byte 0x3
7836
- .byte 0x9
7837
- .byte 0xff
7838
- .byte 0x9f
7839
- .8byte 0
7840
- .8byte 0
7841
-.LLST26:
7842
- .8byte .LVL87
7843
- .8byte .LVL88
7844
- .2byte 0x2
7845
- .byte 0x30
7846
- .byte 0x9f
7847
- .8byte .LVL88
7848
- .8byte .LVL89
7849
- .2byte 0x1
7850
- .byte 0x50
7851
- .8byte .LVL92
7852
- .8byte .LVL95
7853
- .2byte 0x1
7854
- .byte 0x50
7855
- .8byte .LVL101
7856
- .8byte .LFE271
7857
- .2byte 0x1
7858
- .byte 0x50
7859
- .8byte 0
7860
- .8byte 0
7861
-.LLST27:
7862
- .8byte .LVL84
7863
- .8byte .LVL90
7864
- .2byte 0x1
7865
- .byte 0x65
7866
- .8byte .LVL90
7867
- .8byte .LVL91
7868
- .2byte 0x3
7869
- .byte 0x85
7870
- .sleb128 -1
7871
- .byte 0x9f
7872
- .8byte .LVL91
7873
- .8byte .LFE271
7874
- .2byte 0x1
7875
- .byte 0x65
7876
- .8byte 0
7877
- .8byte 0
7878
-.LLST28:
7879
- .8byte .LVL84
7880
- .8byte .LVL89
7881
- .2byte 0x3
7882
- .byte 0x9
7883
- .byte 0xff
7884
- .byte 0x9f
7885
- .8byte .LVL91
7886
- .8byte .LVL94
7887
- .2byte 0x3
7888
- .byte 0x9
7889
- .byte 0xff
7890
- .byte 0x9f
7891
- .8byte .LVL94
7892
- .8byte .LVL101
7893
- .2byte 0x1
7894
- .byte 0x67
7895
- .8byte .LVL101
7896
- .8byte .LFE271
7897
- .2byte 0x3
7898
- .byte 0x9
7899
- .byte 0xff
7900
- .byte 0x9f
7901
- .8byte 0
7902
- .8byte 0
7903
-.LLST9:
7904
- .8byte .LVL35
7905
- .8byte .LVL37
7906
- .2byte 0x1
7907
- .byte 0x50
7908
- .8byte .LVL37
7909
- .8byte .LVL45
7910
- .2byte 0x1
7911
- .byte 0x69
7912
- .8byte .LVL45
7913
- .8byte .LVL46
7914
- .2byte 0x4
7915
- .byte 0xf3
7916
- .uleb128 0x1
7917
- .byte 0x50
7918
- .byte 0x9f
7919
- .8byte .LVL46
7920
- .8byte .LFE268
7921
- .2byte 0x1
7922
- .byte 0x69
7923
- .8byte 0
7924
- .8byte 0
7925
-.LLST10:
7926
- .8byte .LVL35
7927
- .8byte .LVL36
7928
- .2byte 0x1
7929
- .byte 0x51
7930
- .8byte .LVL36
7931
- .8byte .LVL43
7932
- .2byte 0x1
7933
- .byte 0x66
7934
- .8byte .LVL43
7935
- .8byte .LVL46
7936
- .2byte 0x4
7937
- .byte 0xf3
7938
- .uleb128 0x1
7939
- .byte 0x51
7940
- .byte 0x9f
7941
- .8byte .LVL46
7942
- .8byte .LVL47
7943
- .2byte 0x1
7944
- .byte 0x66
7945
- .8byte .LVL47
7946
- .8byte .LVL48
7947
- .2byte 0x3
7948
- .byte 0x87
7949
- .sleb128 32
7950
- .byte 0x9f
7951
- .8byte .LVL48
7952
- .8byte .LFE268
7953
- .2byte 0x4
7954
- .byte 0xf3
7955
- .uleb128 0x1
7956
- .byte 0x51
7957
- .byte 0x9f
7958
- .8byte 0
7959
- .8byte 0
7960
-.LLST11:
7961
- .8byte .LVL50
7962
- .8byte .LVL55
7963
- .2byte 0x1
7964
- .byte 0x64
7965
- .8byte 0
7966
- .8byte 0
7967
-.LLST12:
7968
- .8byte .LVL41
7969
- .8byte .LVL44
7970
- .2byte 0x1
7971
- .byte 0x63
7972
- .8byte .LVL46
7973
- .8byte .LFE268
7974
- .2byte 0x1
7975
- .byte 0x63
7976
- .8byte 0
7977
- .8byte 0
7978
-.LLST13:
7979
- .8byte .LVL50
7980
- .8byte .LVL56
7981
- .2byte 0x1
7982
- .byte 0x65
7983
- .8byte .LVL56
7984
- .8byte .LVL57
7985
- .2byte 0x3
7986
- .byte 0x85
7987
- .sleb128 -8
7988
- .byte 0x9f
7989
- .8byte .LVL57
7990
- .8byte .LFE268
7991
- .2byte 0x3
7992
- .byte 0x88
7993
- .sleb128 -40
7994
- .byte 0x9f
7995
- .8byte 0
7996
- .8byte 0
7997
-.LLST14:
7998
- .8byte .LVL38
7999
- .8byte .LVL43
8000
- .2byte 0x2
8001
- .byte 0x30
8002
- .byte 0x9f
8003
- .8byte .LVL46
8004
- .8byte .LVL51
8005
- .2byte 0x2
8006
- .byte 0x30
8007
- .byte 0x9f
8008
- .8byte .LVL51
8009
- .8byte .LVL52
8010
- .2byte 0x1
8011
- .byte 0x50
8012
- .8byte .LVL52
8013
- .8byte .LVL54
8014
- .2byte 0x2
8015
- .byte 0x30
8016
- .byte 0x9f
8017
- .8byte .LVL54
8018
- .8byte .LVL58
8019
- .2byte 0x1
8020
- .byte 0x50
8021
- .8byte .LVL60
8022
- .8byte .LFE268
8023
- .2byte 0x1
8024
- .byte 0x50
8025
- .8byte 0
8026
- .8byte 0
8027
-.LLST37:
8028
- .8byte .LVL129
8029
- .8byte .LVL130
8030
- .2byte 0x1
8031
- .byte 0x50
8032
- .8byte .LVL130
8033
- .8byte .LFE256
8034
- .2byte 0x4
8035
- .byte 0xf3
8036
- .uleb128 0x1
8037
- .byte 0x50
8038
- .byte 0x9f
8039
- .8byte 0
8040
- .8byte 0
8041
-.LLST38:
8042
- .8byte .LVL129
8043
- .8byte .LVL132-1
8044
- .2byte 0x1
8045
- .byte 0x51
8046
- .8byte .LVL132-1
8047
- .8byte .LFE256
8048
- .2byte 0x4
8049
- .byte 0xf3
8050
- .uleb128 0x1
8051
- .byte 0x51
8052
- .byte 0x9f
8053
- .8byte 0
8054
- .8byte 0
8055
-.LLST39:
8056
- .8byte .LVL129
8057
- .8byte .LVL132-1
8058
- .2byte 0x1
8059
- .byte 0x52
8060
- .8byte .LVL132-1
8061
- .8byte .LVL138
8062
- .2byte 0x1
8063
- .byte 0x67
8064
- .8byte .LVL138
8065
- .8byte .LVL228
8066
- .2byte 0x4
8067
- .byte 0xf3
8068
- .uleb128 0x1
8069
- .byte 0x52
8070
- .byte 0x9f
8071
- .8byte .LVL228
8072
- .8byte .LVL229
8073
- .2byte 0x1
8074
- .byte 0x67
8075
- .8byte .LVL229
8076
- .8byte .LFE256
8077
- .2byte 0x4
8078
- .byte 0xf3
8079
- .uleb128 0x1
8080
- .byte 0x52
8081
- .byte 0x9f
8082
- .8byte 0
8083
- .8byte 0
8084
-.LLST40:
8085
- .8byte .LVL129
8086
- .8byte .LVL132-1
8087
- .2byte 0x1
8088
- .byte 0x53
8089
- .8byte .LVL132-1
8090
- .8byte .LVL145
8091
- .2byte 0x1
8092
- .byte 0x6a
8093
- .8byte .LVL145
8094
- .8byte .LVL147
8095
- .2byte 0x4
8096
- .byte 0xf3
8097
- .uleb128 0x1
8098
- .byte 0x53
8099
- .byte 0x9f
8100
- .8byte .LVL147
8101
- .8byte .LVL158
8102
- .2byte 0x1
8103
- .byte 0x6a
8104
- .8byte .LVL158
8105
- .8byte .LVL193
8106
- .2byte 0x4
8107
- .byte 0xf3
8108
- .uleb128 0x1
8109
- .byte 0x53
8110
- .byte 0x9f
8111
- .8byte .LVL193
8112
- .8byte .LVL196
8113
- .2byte 0x1
8114
- .byte 0x6a
8115
- .8byte .LVL196
8116
- .8byte .LVL204
8117
- .2byte 0x4
8118
- .byte 0xf3
8119
- .uleb128 0x1
8120
- .byte 0x53
8121
- .byte 0x9f
8122
- .8byte .LVL204
8123
- .8byte .LVL210
8124
- .2byte 0x1
8125
- .byte 0x6a
8126
- .8byte .LVL210
8127
- .8byte .LVL226
8128
- .2byte 0x4
8129
- .byte 0xf3
8130
- .uleb128 0x1
8131
- .byte 0x53
8132
- .byte 0x9f
8133
- .8byte .LVL226
8134
- .8byte .LVL234
8135
- .2byte 0x1
8136
- .byte 0x6a
8137
- .8byte .LVL234
8138
- .8byte .LFE256
8139
- .2byte 0x4
8140
- .byte 0xf3
8141
- .uleb128 0x1
8142
- .byte 0x53
8143
- .byte 0x9f
8144
- .8byte 0
8145
- .8byte 0
8146
-.LLST41:
8147
- .8byte .LVL134
8148
- .8byte .LVL136
8149
- .2byte 0x1
8150
- .byte 0x63
8151
- .8byte .LVL136
8152
- .8byte .LVL137
8153
- .2byte 0x3
8154
- .byte 0x83
8155
- .sleb128 1
8156
- .byte 0x9f
8157
- .8byte .LVL137
8158
- .8byte .LVL138
8159
- .2byte 0x1
8160
- .byte 0x63
8161
- .8byte .LVL151
8162
- .8byte .LVL153
8163
- .2byte 0x1
8164
- .byte 0x50
8165
- .8byte .LVL153
8166
- .8byte .LVL154
8167
- .2byte 0x2
8168
- .byte 0x30
8169
- .byte 0x9f
8170
- .8byte .LVL154
8171
- .8byte .LVL155
8172
- .2byte 0x1
8173
- .byte 0x50
8174
- .8byte .LVL155
8175
- .8byte .LVL156
8176
- .2byte 0x3
8177
- .byte 0x70
8178
- .sleb128 1
8179
- .byte 0x9f
8180
- .8byte .LVL161
8181
- .8byte .LVL186
8182
- .2byte 0x1
8183
- .byte 0x63
8184
- .8byte .LVL186
8185
- .8byte .LVL187
8186
- .2byte 0x3
8187
- .byte 0x83
8188
- .sleb128 1
8189
- .byte 0x9f
8190
- .8byte .LVL193
8191
- .8byte .LVL194
8192
- .2byte 0x3
8193
- .byte 0x70
8194
- .sleb128 1
8195
- .byte 0x9f
8196
- .8byte .LVL196
8197
- .8byte .LVL204
8198
- .2byte 0x1
8199
- .byte 0x63
8200
- .8byte .LVL213
8201
- .8byte .LVL214
8202
- .2byte 0x1
8203
- .byte 0x6c
8204
- .8byte .LVL217
8205
- .8byte .LVL221
8206
- .2byte 0x1
8207
- .byte 0x6c
8208
- .8byte .LVL222
8209
- .8byte .LVL226
8210
- .2byte 0x1
8211
- .byte 0x6c
8212
- .8byte .LVL228
8213
- .8byte .LVL230
8214
- .2byte 0x1
8215
- .byte 0x63
8216
- .8byte 0
8217
- .8byte 0
8218
-.LLST42:
8219
- .8byte .LVL137
8220
- .8byte .LVL138
8221
- .2byte 0x1
8222
- .byte 0x63
8223
- .8byte .LVL140
8224
- .8byte .LVL145
8225
- .2byte 0x1
8226
- .byte 0x63
8227
- .8byte .LVL147
8228
- .8byte .LVL159
8229
- .2byte 0x1
8230
- .byte 0x63
8231
- .8byte .LVL193
8232
- .8byte .LVL196
8233
- .2byte 0x1
8234
- .byte 0x63
8235
- .8byte .LVL204
8236
- .8byte .LVL234
8237
- .2byte 0x1
8238
- .byte 0x63
8239
- .8byte 0
8240
- .8byte 0
8241
-.LLST43:
8242
- .8byte .LVL165
8243
- .8byte .LVL168
8244
- .2byte 0x2
8245
- .byte 0x32
8246
- .byte 0x9f
8247
- .8byte .LVL168
8248
- .8byte .LVL171
8249
- .2byte 0x2
8250
- .byte 0x33
8251
- .byte 0x9f
8252
- .8byte .LVL171
8253
- .8byte .LVL174
8254
- .2byte 0x2
8255
- .byte 0x34
8256
- .byte 0x9f
8257
- .8byte .LVL178
8258
- .8byte .LVL181
8259
- .2byte 0x2
8260
- .byte 0x32
8261
- .byte 0x9f
8262
- .8byte .LVL181
8263
- .8byte .LVL184
8264
- .2byte 0x2
8265
- .byte 0x33
8266
- .byte 0x9f
8267
- .8byte .LVL184
8268
- .8byte .LVL186
8269
- .2byte 0x2
8270
- .byte 0x34
8271
- .byte 0x9f
8272
- .8byte .LVL196
8273
- .8byte .LVL197
8274
- .2byte 0x2
8275
- .byte 0x32
8276
- .byte 0x9f
8277
- .8byte .LVL197
8278
- .8byte .LVL198
8279
- .2byte 0x2
8280
- .byte 0x33
8281
- .byte 0x9f
8282
- .8byte .LVL198
8283
- .8byte .LVL199
8284
- .2byte 0x2
8285
- .byte 0x34
8286
- .byte 0x9f
8287
- .8byte .LVL200
8288
- .8byte .LVL201
8289
- .2byte 0x2
8290
- .byte 0x32
8291
- .byte 0x9f
8292
- .8byte .LVL201
8293
- .8byte .LVL202
8294
- .2byte 0x2
8295
- .byte 0x33
8296
- .byte 0x9f
8297
- .8byte .LVL202
8298
- .8byte .LVL204
8299
- .2byte 0x2
8300
- .byte 0x34
8301
- .byte 0x9f
8302
- .8byte .LVL219
8303
- .8byte .LVL222
8304
- .2byte 0x1
8305
- .byte 0x63
8306
- .8byte .LVL225
8307
- .8byte .LVL226
8308
- .2byte 0x1
8309
- .byte 0x63
8310
- .8byte 0
8311
- .8byte 0
8312
-.LLST44:
8313
- .8byte .LVL157
8314
- .8byte .LVL159
8315
- .2byte 0x2
8316
- .byte 0x30
8317
- .byte 0x9f
8318
- .8byte .LVL159
8319
- .8byte .LVL193
8320
- .2byte 0x1
8321
- .byte 0x69
8322
- .8byte .LVL196
8323
- .8byte .LVL204
8324
- .2byte 0x1
8325
- .byte 0x69
8326
- .8byte .LVL211
8327
- .8byte .LVL226
8328
- .2byte 0x1
8329
- .byte 0x69
8330
- .8byte 0
8331
- .8byte 0
8332
-.LLST45:
8333
- .8byte .LVL131
8334
- .8byte .LVL145
8335
- .2byte 0x2
8336
- .byte 0x31
8337
- .byte 0x9f
8338
- .8byte .LVL147
8339
- .8byte .LVL190
8340
- .2byte 0x2
8341
- .byte 0x31
8342
- .byte 0x9f
8343
- .8byte .LVL193
8344
- .8byte .LVL206
8345
- .2byte 0x2
8346
- .byte 0x31
8347
- .byte 0x9f
8348
- .8byte .LVL206
8349
- .8byte .LVL207
8350
- .2byte 0x1
8351
- .byte 0x50
8352
- .8byte .LVL207
8353
- .8byte .LVL226
8354
- .2byte 0x1
8355
- .byte 0x6b
8356
- .8byte .LVL226
8357
- .8byte .LVL228
8358
- .2byte 0x1
8359
- .byte 0x50
8360
- .8byte .LVL228
8361
- .8byte .LVL234
8362
- .2byte 0x2
8363
- .byte 0x31
8364
- .byte 0x9f
8365
- .8byte 0
8366
- .8byte 0
8367
-.LLST46:
8368
- .8byte .LVL131
8369
- .8byte .LVL145
8370
- .2byte 0x2
8371
- .byte 0x30
8372
- .byte 0x9f
8373
- .8byte .LVL147
8374
- .8byte .LVL152
8375
- .2byte 0x2
8376
- .byte 0x30
8377
- .byte 0x9f
8378
- .8byte .LVL152
8379
- .8byte .LVL153
8380
- .2byte 0x1
8381
- .byte 0x50
8382
- .8byte .LVL193
8383
- .8byte .LVL196
8384
- .2byte 0x2
8385
- .byte 0x30
8386
- .byte 0x9f
8387
- .8byte .LVL204
8388
- .8byte .LVL234
8389
- .2byte 0x2
8390
- .byte 0x30
8391
- .byte 0x9f
8392
- .8byte 0
8393
- .8byte 0
8394
-.LLST47:
8395
- .8byte .LVL131
8396
- .8byte .LVL142
8397
- .2byte 0x2
8398
- .byte 0x30
8399
- .byte 0x9f
8400
- .8byte .LVL142
8401
- .8byte .LVL143-1
8402
- .2byte 0x1
8403
- .byte 0x50
8404
- .8byte .LVL143-1
8405
- .8byte .LVL145
8406
- .2byte 0x1
8407
- .byte 0x67
8408
- .8byte .LVL147
8409
- .8byte .LVL159
8410
- .2byte 0x1
8411
- .byte 0x67
8412
- .8byte .LVL159
8413
- .8byte .LVL165
8414
- .2byte 0x2
8415
- .byte 0x30
8416
- .byte 0x9f
8417
- .8byte .LVL165
8418
- .8byte .LVL166
8419
- .2byte 0x1
8420
- .byte 0x50
8421
- .8byte .LVL166
8422
- .8byte .LVL168
8423
- .2byte 0x1
8424
- .byte 0x68
8425
- .8byte .LVL168
8426
- .8byte .LVL169
8427
- .2byte 0x1
8428
- .byte 0x50
8429
- .8byte .LVL169
8430
- .8byte .LVL171
8431
- .2byte 0x1
8432
- .byte 0x68
8433
- .8byte .LVL171
8434
- .8byte .LVL172
8435
- .2byte 0x1
8436
- .byte 0x50
8437
- .8byte .LVL172
8438
- .8byte .LVL174
8439
- .2byte 0x1
8440
- .byte 0x68
8441
- .8byte .LVL174
8442
- .8byte .LVL175
8443
- .2byte 0x1
8444
- .byte 0x50
8445
- .8byte .LVL175
8446
- .8byte .LVL178
8447
- .2byte 0x1
8448
- .byte 0x68
8449
- .8byte .LVL178
8450
- .8byte .LVL179
8451
- .2byte 0x1
8452
- .byte 0x50
8453
- .8byte .LVL179
8454
- .8byte .LVL180-1
8455
- .2byte 0x1
8456
- .byte 0x52
8457
- .8byte .LVL180-1
8458
- .8byte .LVL181
8459
- .2byte 0x3
8460
- .byte 0x8f
8461
- .sleb128 196
8462
- .8byte .LVL181
8463
- .8byte .LVL182
8464
- .2byte 0x1
8465
- .byte 0x50
8466
- .8byte .LVL182
8467
- .8byte .LVL184
8468
- .2byte 0x1
8469
- .byte 0x66
8470
- .8byte .LVL184
8471
- .8byte .LVL185-1
8472
- .2byte 0x1
8473
- .byte 0x50
8474
- .8byte .LVL185-1
8475
- .8byte .LVL186
8476
- .2byte 0x1
8477
- .byte 0x68
8478
- .8byte .LVL186
8479
- .8byte .LVL188
8480
- .2byte 0x2
8481
- .byte 0x30
8482
- .byte 0x9f
8483
- .8byte .LVL188
8484
- .8byte .LVL191
8485
- .2byte 0x1
8486
- .byte 0x68
8487
- .8byte .LVL193
8488
- .8byte .LVL196
8489
- .2byte 0x1
8490
- .byte 0x67
8491
- .8byte .LVL196
8492
- .8byte .LVL199
8493
- .2byte 0x1
8494
- .byte 0x50
8495
- .8byte .LVL199
8496
- .8byte .LVL200
8497
- .2byte 0x1
8498
- .byte 0x68
8499
- .8byte .LVL200
8500
- .8byte .LVL203
8501
- .2byte 0x1
8502
- .byte 0x50
8503
- .8byte .LVL203
8504
- .8byte .LVL204
8505
- .2byte 0x1
8506
- .byte 0x68
8507
- .8byte .LVL204
8508
- .8byte .LVL211
8509
- .2byte 0x1
8510
- .byte 0x67
8511
- .8byte .LVL211
8512
- .8byte .LVL214
8513
- .2byte 0x2
8514
- .byte 0x30
8515
- .byte 0x9f
8516
- .8byte .LVL214
8517
- .8byte .LVL216
8518
- .2byte 0x1
8519
- .byte 0x68
8520
- .8byte .LVL216
8521
- .8byte .LVL219
8522
- .2byte 0x2
8523
- .byte 0x30
8524
- .byte 0x9f
8525
- .8byte .LVL219
8526
- .8byte .LVL220-1
8527
- .2byte 0x1
8528
- .byte 0x50
8529
- .8byte .LVL220-1
8530
- .8byte .LVL222
8531
- .2byte 0x1
8532
- .byte 0x68
8533
- .8byte .LVL222
8534
- .8byte .LVL225
8535
- .2byte 0x2
8536
- .byte 0x30
8537
- .byte 0x9f
8538
- .8byte .LVL225
8539
- .8byte .LVL226
8540
- .2byte 0x1
8541
- .byte 0x68
8542
- .8byte .LVL226
8543
- .8byte .LVL227
8544
- .2byte 0x1
8545
- .byte 0x67
8546
- .8byte .LVL228
8547
- .8byte .LVL232
8548
- .2byte 0x2
8549
- .byte 0x30
8550
- .byte 0x9f
8551
- .8byte .LVL232
8552
- .8byte .LVL233
8553
- .2byte 0x1
8554
- .byte 0x50
8555
- .8byte .LVL233
8556
- .8byte .LVL234-1
8557
- .2byte 0x1
8558
- .byte 0x51
8559
- .8byte .LVL234-1
8560
- .8byte .LVL234
8561
- .2byte 0x1
8562
- .byte 0x67
8563
- .8byte 0
8564
- .8byte 0
8565
-.LLST48:
8566
- .8byte .LVL131
8567
- .8byte .LVL145
8568
- .2byte 0x2
8569
- .byte 0x30
8570
- .byte 0x9f
8571
- .8byte .LVL147
8572
- .8byte .LVL188
8573
- .2byte 0x2
8574
- .byte 0x30
8575
- .byte 0x9f
8576
- .8byte .LVL188
8577
- .8byte .LVL189
8578
- .2byte 0x1
8579
- .byte 0x52
8580
- .8byte .LVL193
8581
- .8byte .LVL214
8582
- .2byte 0x2
8583
- .byte 0x30
8584
- .byte 0x9f
8585
- .8byte .LVL214
8586
- .8byte .LVL215
8587
- .2byte 0x1
8588
- .byte 0x50
8589
- .8byte .LVL216
8590
- .8byte .LVL234
8591
- .2byte 0x2
8592
- .byte 0x30
8593
- .byte 0x9f
8594
- .8byte 0
8595
- .8byte 0
8596
-.LLST49:
8597
- .8byte .LVL157
8598
- .8byte .LVL190
8599
- .2byte 0x1
8600
- .byte 0x6c
8601
- .8byte .LVL196
8602
- .8byte .LVL204
8603
- .2byte 0x1
8604
- .byte 0x6c
8605
- .8byte 0
8606
- .8byte 0
8607
-.LLST29:
8608
- .8byte .LVL103
8609
- .8byte .LVL104
8610
- .2byte 0x1
8611
- .byte 0x50
8612
- .8byte .LVL104
8613
- .8byte .LVL107
8614
- .2byte 0x1
8615
- .byte 0x63
8616
- .8byte .LVL107
8617
- .8byte .LVL108
8618
- .2byte 0x1
8619
- .byte 0x50
8620
- .8byte .LVL108
8621
- .8byte .LVL121
8622
- .2byte 0x1
8623
- .byte 0x63
8624
- .8byte .LVL124
8625
- .8byte .LFE255
8626
- .2byte 0x1
8627
- .byte 0x63
8628
- .8byte 0
8629
- .8byte 0
8630
-.LLST30:
8631
- .8byte .LVL103
8632
- .8byte .LVL106
8633
- .2byte 0x1
8634
- .byte 0x51
8635
- .8byte .LVL106
8636
- .8byte .LVL110
8637
- .2byte 0x1
8638
- .byte 0x51
8639
- .8byte 0
8640
- .8byte 0
8641
-.LLST31:
8642
- .8byte .LVL103
8643
- .8byte .LVL110
8644
- .2byte 0x1
8645
- .byte 0x52
8646
- .8byte .LVL110
8647
- .8byte .LVL122
8648
- .2byte 0x1
8649
- .byte 0x66
8650
- .8byte .LVL122
8651
- .8byte .LVL124
8652
- .2byte 0x4
8653
- .byte 0xf3
8654
- .uleb128 0x1
8655
- .byte 0x52
8656
- .byte 0x9f
8657
- .8byte .LVL124
8658
- .8byte .LFE255
8659
- .2byte 0x1
8660
- .byte 0x66
8661
- .8byte 0
8662
- .8byte 0
8663
-.LLST32:
8664
- .8byte .LVL109
8665
- .8byte .LVL110
8666
- .2byte 0x2
8667
- .byte 0x30
8668
- .byte 0x9f
8669
- .8byte .LVL110
8670
- .8byte .LVL123
8671
- .2byte 0x1
8672
- .byte 0x67
8673
- .8byte .LVL124
8674
- .8byte .LFE255
8675
- .2byte 0x1
8676
- .byte 0x67
8677
- .8byte 0
8678
- .8byte 0
8679
-.LLST33:
8680
- .8byte .LVL109
8681
- .8byte .LVL122
8682
- .2byte 0x1
8683
- .byte 0x65
8684
- .8byte .LVL124
8685
- .8byte .LFE255
8686
- .2byte 0x1
8687
- .byte 0x65
8688
- .8byte 0
8689
- .8byte 0
8690
-.LLST34:
8691
- .8byte .LVL111
8692
- .8byte .LVL112
8693
- .2byte 0x9
8694
- .byte 0x70
8695
- .sleb128 0
8696
- .byte 0x85
8697
- .sleb128 0
8698
- .byte 0x1d
8699
- .byte 0x83
8700
- .sleb128 0
8701
- .byte 0x22
8702
- .byte 0x9f
8703
- .8byte 0
8704
- .8byte 0
8705
-.LLST35:
8706
- .8byte .LVL115
8707
- .8byte .LVL116
8708
- .2byte 0x1
8709
- .byte 0x50
8710
- .8byte .LVL116
8711
- .8byte .LVL120
8712
- .2byte 0x1
8713
- .byte 0x6a
8714
- .8byte .LVL124
8715
- .8byte .LVL126
8716
- .2byte 0x1
8717
- .byte 0x6a
8718
- .8byte .LVL127
8719
- .8byte .LFE255
8720
- .2byte 0x1
8721
- .byte 0x6a
8722
- .8byte 0
8723
- .8byte 0
8724
-.LLST36:
8725
- .8byte .LVL103
8726
- .8byte .LVL118
8727
- .2byte 0x2
8728
- .byte 0x30
8729
- .byte 0x9f
8730
- .8byte .LVL118
8731
- .8byte .LVL119
8732
- .2byte 0x1
8733
- .byte 0x50
8734
- .8byte .LVL119
8735
- .8byte .LVL120
8736
- .2byte 0x1
8737
- .byte 0x64
8738
- .8byte .LVL124
8739
- .8byte .LVL125-1
8740
- .2byte 0x1
8741
- .byte 0x50
8742
- .8byte .LVL125-1
8743
- .8byte .LVL126
8744
- .2byte 0x1
8745
- .byte 0x64
8746
- .8byte .LVL127
8747
- .8byte .LFE255
8748
- .2byte 0x1
8749
- .byte 0x64
8750
- .8byte 0
8751
- .8byte 0
8752
-.LLST8:
8753
- .8byte .LVL33
8754
- .8byte .LVL34
8755
- .2byte 0x1
8756
- .byte 0x50
8757
- .8byte .LVL34
8758
- .8byte .LFE254
8759
- .2byte 0x4
8760
- .byte 0xf3
8761
- .uleb128 0x1
8762
- .byte 0x50
8763
- .byte 0x9f
8764
- .8byte 0
8765
- .8byte 0
8766
-.LLST7:
8767
- .8byte .LVL31
8768
- .8byte .LVL32
8769
- .2byte 0x1
8770
- .byte 0x50
8771
- .8byte .LVL32
8772
- .8byte .LFE253
8773
- .2byte 0x4
8774
- .byte 0xf3
8775
- .uleb128 0x1
8776
- .byte 0x50
8777
- .byte 0x9f
8778
- .8byte 0
8779
- .8byte 0
8780
-.LLST0:
8781
- .8byte .LVL0
8782
- .8byte .LVL1
8783
- .2byte 0x1
8784
- .byte 0x50
8785
- .8byte .LVL1
8786
- .8byte .LVL12
8787
- .2byte 0x1
8788
- .byte 0x67
8789
- .8byte .LVL12
8790
- .8byte .LVL13
8791
- .2byte 0x4
8792
- .byte 0xf3
8793
- .uleb128 0x1
8794
- .byte 0x50
8795
- .byte 0x9f
8796
- .8byte .LVL13
8797
- .8byte .LFE200
8798
- .2byte 0x1
8799
- .byte 0x67
8800
- .8byte 0
8801
- .8byte 0
8802
-.LLST1:
8803
- .8byte .LVL0
8804
- .8byte .LVL2-1
8805
- .2byte 0x1
8806
- .byte 0x51
8807
- .8byte .LVL2-1
8808
- .8byte .LVL12
8809
- .2byte 0x1
8810
- .byte 0x68
8811
- .8byte .LVL12
8812
- .8byte .LVL13
8813
- .2byte 0x4
8814
- .byte 0xf3
8815
- .uleb128 0x1
8816
- .byte 0x51
8817
- .byte 0x9f
8818
- .8byte .LVL13
8819
- .8byte .LFE200
8820
- .2byte 0x1
8821
- .byte 0x68
8822
- .8byte 0
8823
- .8byte 0
8824
-.LLST2:
8825
- .8byte .LVL2
8826
- .8byte .LVL3
8827
- .2byte 0x2
8828
- .byte 0x30
8829
- .byte 0x9f
8830
- .8byte .LVL3
8831
- .8byte .LVL11
8832
- .2byte 0x1
8833
- .byte 0x64
8834
- .8byte .LVL13
8835
- .8byte .LVL22
8836
- .2byte 0x1
8837
- .byte 0x64
8838
- .8byte .LVL23
8839
- .8byte .LFE200
8840
- .2byte 0x1
8841
- .byte 0x66
8842
- .8byte 0
8843
- .8byte 0
8844
-.LLST3:
8845
- .8byte .LVL24
8846
- .8byte .LVL25
8847
- .2byte 0x2
8848
- .byte 0x30
8849
- .byte 0x9f
8850
- .8byte 0
8851
- .8byte 0
8852
-.LLST4:
8853
- .8byte .LVL4
8854
- .8byte .LVL11
8855
- .2byte 0x1
8856
- .byte 0x6b
8857
- .8byte .LVL13
8858
- .8byte .LVL21
8859
- .2byte 0x1
8860
- .byte 0x6b
8861
- .8byte .LVL22
8862
- .8byte .LFE200
8863
- .2byte 0x1
8864
- .byte 0x64
8865
- .8byte 0
8866
- .8byte 0
8867
-.LLST5:
8868
- .8byte .LVL3
8869
- .8byte .LVL4
8870
- .2byte 0x3
8871
- .byte 0x9
8872
- .byte 0xff
8873
- .byte 0x9f
8874
- .8byte .LVL4
8875
- .8byte .LVL5
8876
- .2byte 0x1
8877
- .byte 0x6c
8878
- .8byte .LVL5
8879
- .8byte .LVL6
8880
- .2byte 0x4
8881
- .byte 0x8c
8882
- .sleb128 0
8883
- .byte 0x20
8884
- .byte 0x9f
8885
- .8byte .LVL6
8886
- .8byte .LVL11
8887
- .2byte 0x1
8888
- .byte 0x6c
8889
- .8byte .LVL13
8890
- .8byte .LVL22
8891
- .2byte 0x1
8892
- .byte 0x6c
8893
- .8byte 0
8894
- .8byte 0
8895
-.LLST6:
8896
- .8byte .LVL18
8897
- .8byte .LVL19
8898
- .2byte 0x1
8899
- .byte 0x50
8900
- .8byte .LVL19
8901
- .8byte .LFE200
8902
- .2byte 0x1
8903
- .byte 0x65
8904
- .8byte 0
8905
- .8byte 0
8906
- .section .debug_aranges,"",@progbits
8907
- .4byte 0x8c
8908
- .2byte 0x2
8909
- .4byte .Ldebug_info0
8910
- .byte 0x8
8911
- .byte 0
8912
- .2byte 0
8913
- .2byte 0
8914
- .8byte .LFB200
8915
- .8byte .LFE200-.LFB200
8916
- .8byte .LFB253
8917
- .8byte .LFE253-.LFB253
8918
- .8byte .LFB254
8919
- .8byte .LFE254-.LFB254
8920
- .8byte .LFB268
8921
- .8byte .LFE268-.LFB268
8922
- .8byte .LFB271
8923
- .8byte .LFE271-.LFB271
8924
- .8byte .LFB255
8925
- .8byte .LFE255-.LFB255
8926
- .8byte .LFB256
8927
- .8byte .LFE256-.LFB256
8928
- .8byte 0
8929
- .8byte 0
8930
- .section .debug_ranges,"",@progbits
8931
-.Ldebug_ranges0:
8932
- .8byte .LBB6
8933
- .8byte .LBE6
8934
- .8byte .LBB12
8935
- .8byte .LBE12
8936
- .8byte .LBB13
8937
- .8byte .LBE13
8938
- .8byte .LBB14
8939
- .8byte .LBE14
8940
- .8byte .LBB18
8941
- .8byte .LBE18
8942
- .8byte 0
8943
- .8byte 0
8944
- .8byte .LBB15
8945
- .8byte .LBE15
8946
- .8byte .LBB19
8947
- .8byte .LBE19
8948
- .8byte 0
8949
- .8byte 0
8950
- .8byte .LFB200
8951
- .8byte .LFE200
8952
- .8byte .LFB253
8953
- .8byte .LFE253
8954
- .8byte .LFB254
8955
- .8byte .LFE254
8956
- .8byte .LFB268
8957
- .8byte .LFE268
8958
- .8byte .LFB271
8959
- .8byte .LFE271
8960
- .8byte .LFB255
8961
- .8byte .LFE255
8962
- .8byte .LFB256
8963
- .8byte .LFE256
8964
- .8byte 0
8965
- .8byte 0
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9580
-.LASF325:
9581
- .string "recv"
9582
-.LASF135:
9583
- .string "type"
9584
-.LASF146:
9585
- .string "fit_hdr_rd"
9586
-.LASF276:
9587
- .string "env_addr"
9588
-.LASF72:
9589
- .string "bi_sramsize"
9590
-.LASF449:
9591
- .string "scan_freq"
9592
-.LASF431:
9593
- .string "start_adr"
9594
-.LASF288:
9595
- .string "uclass_root"
9596
-.LASF190:
9597
- .string "UCLASS_GPIO"
9598
-.LASF219:
9599
- .string "UCLASS_PWM"
9600
-.LASF444:
9601
- .string "test_banks"
9602
-.LASF58:
9603
- .string "long double"
9604
-.LASF278:
9605
- .string "ram_top"
9606
-.LASF421:
9607
- .string "baseaddr"
9608
-.LASF480:
9609
- .string "/home/typ/src/u-boot_gerrit/u-boot-ddr"
9610
-.LASF155:
9611
- .string "rd_start"
9612
-.LASF220:
9613
- .string "UCLASS_POWER_DOMAIN"
9614
-.LASF223:
9615
- .string "UCLASS_REGULATOR"
9616
-.LASF317:
9617
- .string "save_size"
9618
-.LASF183:
9619
- .string "UCLASS_CLK"
9620
-.LASF31:
9621
- .string "uclass_platdata"
9622
-.LASF322:
9623
- .string "iobase"
9624
-.LASF429:
9625
- .string "random_test"
9626
-.LASF88:
9627
- .string "_datarel_start_ofs"
9628
-.LASF265:
9629
- .string "pre_serial"
9630
-.LASF128:
9631
- .string "ih_name"
9632
-.LASF435:
9633
- .string "next_col"
9634
-.LASF124:
9635
- .string "ih_os"
9636
-.LASF162:
9637
- .string "cmdline_end"
9638
-.LASF343:
9639
- .string "net_rx_packet"
9640
-.LASF256:
9641
- .string "LOGF_MAX_CATEGORIES"
9642
-.LASF289:
9643
- .string "fdt_blob"
9644
-.LASF386:
9645
- .string "udevice_id"
9646
-.LASF51:
9647
- .string "size"
9648
-.LASF10:
9649
- .string "long long unsigned int"
9650
-.LASF395:
9651
- .string "destroy"
9652
-.LASF116:
9653
- .string "image_header"
9654
-.LASF377:
9655
- .string "length"
9656
-.LASF20:
9657
- .string "__be32"
9658
-.LASF68:
9659
- .string "bi_flashstart"
9660
-.LASF145:
9661
- .string "fit_noffset_os"
9662
-.LASF205:
9663
- .string "UCLASS_MMC"
9664
-.LASF327:
9665
- .string "write_hwaddr"
9666
-.LASF479:
9667
- .string "cmd/ddr_tool/ddr_test_code.c"
9668
-.LASF255:
9669
- .string "UCLASS_INVALID"
9670
-.LASF471:
9671
- .string "data_cpu_2_io_init"
9672
-.LASF94:
9673
- .string "maxargs"
9674
-.LASF242:
9675
- .string "UCLASS_USB_HUB"
9676
-.LASF414:
9677
- .string "DIAGONALSCAN"
9678
-.LASF371:
9679
- .string "child_post_remove"
9680
-.LASF93:
9681
- .string "cmd_tbl_s"
9682
-.LASF99:
9683
- .string "cmd_tbl_t"
9684
-.LASF41:
9685
- .string "sibling_node"
9686
-.LASF292:
9687
- .string "of_root"
9688
-.LASF461:
9689
- .string "memset"
9690
-.LASF57:
9691
- .string "flash_info"
9692
-.LASF110:
9693
- .string "version"
9694
-.LASF326:
9695
- .string "halt"
9696
-.LASF62:
9697
- .string "region"
9698
-.LASF114:
9699
- .string "size_dt_struct"
9700
-.LASF286:
9701
- .string "dm_root"
9702
-.LASF304:
9703
- .string "sys_start_tick"
9704
-.LASF308:
9705
- .string "properties"
9706
-.LASF207:
9707
- .string "UCLASS_MTD"
9708
-.LASF103:
9709
- .string "fdt32_t"
9710
-.LASF285:
9711
- .string "new_gd"
9712
-.LASF468:
9713
- .string "get_print_available_addr"
9714
-.LASF208:
9715
- .string "UCLASS_NORTHBRIDGE"
9716
-.LASF78:
9717
- .string "bi_enetaddr"
9718
-.LASF477:
9719
- .string "malloc"
9720
-.LASF369:
9721
- .string "child_post_bind"
9722
-.LASF483:
9723
- .string "exit"
9724
-.LASF318:
9725
- .string "in_addr"
9726
-.LASF344:
9727
- .string "net_rx_packet_len"
9728
-.LASF323:
9729
- .string "init"
9730
-.LASF102:
9731
- .string "CMD_RET_USAGE"
9732
-.LASF313:
9733
- .string "__dtb_dt_begin"
9734
-.LASF225:
9735
- .string "UCLASS_RESET"
9736
-.LASF148:
9737
- .string "fit_noffset_rd"
9738
-.LASF436:
9739
- .string "err_adr"
9740
-.LASF181:
9741
- .string "UCLASS_AHCI"
9742
-.LASF12:
9743
- .string "phys_size_t"
9744
-.LASF27:
9745
- .string "driver"
9746
-.LASF87:
9747
- .string "FIQ_STACK_START"
9748
-.LASF163:
9749
- .string "verify"
9750
-.LASF381:
9751
- .string "ofnode"
9752
-.LASF28:
9753
- .string "name"
9754
-.LASF441:
9755
- .string "test_case"
9756
-.LASF211:
9757
- .string "UCLASS_PANEL_BACKLIGHT"
9758
-.LASF238:
9759
- .string "UCLASS_TIMER"
9760
-.LASF233:
9761
- .string "UCLASS_SPI_FLASH"
9762
-.LASF424:
9763
- .string "reread_val"
9764
-.LASF275:
9765
- .string "have_console"
9766
-.LASF81:
9767
- .string "bi_busfreq"
9768
-.LASF6:
9769
- .string "short int"
9770
-.LASF217:
9771
- .string "UCLASS_PINCTRL"
9772
-.LASF227:
9773
- .string "UCLASS_RAMDISK"
9774
-.LASF434:
9775
- .string "pattern"
9776
-.LASF176:
9777
- .string "UCLASS_I2C_EMUL"
9778
-.LASF232:
9779
- .string "UCLASS_SPMI"
9780
-.LASF96:
9781
- .string "usage"
9782
-.LASF366:
9783
- .string "remove"
9784
-.LASF173:
9785
- .string "UCLASS_TEST_BUS"
9786
-.LASF316:
9787
- .string "save_addr"
9788
-.LASF374:
9789
- .string "per_child_auto_alloc_size"
9790
-.LASF463:
9791
- .string "flush_dcache_range"
9792
-.LASF413:
9793
- .string "CROSSTALK"
9794
-.LASF298:
9795
- .string "malloc_ptr"
9796
-.LASF160:
9797
- .string "initrd_end"
9798
-.LASF391:
9799
- .string "pre_unbind"
9800
-.LASF267:
9801
- .string "baudrate"
9802
-.LASF90:
9803
- .string "_datarellocal_start_ofs"
9804
-.LASF40:
9805
- .string "child_head"
9806
-.LASF257:
9807
- .string "arch_global_data"
9808
-.LASF254:
9809
- .string "UCLASS_COUNT"
9810
-.LASF399:
9811
- .string "stdio_dev"
9812
-.LASF272:
9813
- .string "pci_clk"
9814
-.LASF49:
9815
- .string "block_drvr"
9816
-.LASF466:
9817
- .string "memcpy"
9818
-.LASF53:
9819
- .string "flash_id"
9820
-.LASF305:
9821
- .string "device_node"
9822
-.LASF280:
9823
- .string "ram_size"
9824
-.LASF154:
9825
- .string "fit_noffset_setup"
9826
-.LASF115:
9827
- .string "working_fdt"
9828
-.LASF336:
9829
- .string "net_root_path"
9830
-.LASF188:
9831
- .string "UCLASS_DMA"
9832
-.LASF85:
9833
- .string "bd_t"
9834
-.LASF319:
9835
- .string "s_addr"
9836
-.LASF393:
9837
- .string "post_probe"
9838
-.LASF345:
9839
- .string "net_bcast_ethaddr"
9840
-.LASF83:
9841
- .string "bi_boot_params"
9842
-.LASF19:
9843
- .string "uint32_t"
9844
-.LASF362:
9845
- .string "mem_malloc_brk"
9846
-.LASF331:
9847
- .string "net_gateway"
9848
-.LASF373:
9849
- .string "platdata_auto_alloc_size"
9850
-.LASF403:
9851
- .string "tstc"
9852
-.LASF66:
9853
- .string "bi_memstart"
9854
-.LASF245:
9855
- .string "UCLASS_VIDEO_CONSOLE"
9856
-.LASF406:
9857
- .string "stdio_devices"
9858
-.LASF329:
9859
- .string "eth_current"
9860
-.LASF420:
9861
- .string "_u_boot_list_2_cmd_2_ddr_test"
9862
-.LASF368:
9863
- .string "ofdata_to_platdata"
9864
-.LASF64:
9865
- .string "reserved"
9866
-.LASF410:
9867
- .string "CHANGEFREQ"
9868
-.LASF433:
9869
- .string "page_size"
9870
-.LASF415:
9871
- .string "FASTTEST"
9872
-.LASF409:
9873
- .string "cd_count"
9874
-.LASF84:
9875
- .string "bi_dram"
9876
-.LASF2:
9877
- .string "short unsigned int"
9878
-.LASF105:
9879
- .string "magic"
9880
-.LASF152:
9881
- .string "fit_hdr_setup"
9882
-.LASF141:
9883
- .string "legacy_hdr_valid"
9884
-.LASF411:
9885
- .string "SCANFREQ"
9886
-.LASF60:
9887
- .string "base"
9888
-.LASF442:
9889
- .string "err_case"
9890
-.LASF228:
9891
- .string "UCLASS_RTC"
9892
-.LASF258:
9893
- .string "timer_rate_hz"
9894
-.LASF52:
9895
- .string "sector_count"
9896
-.LASF127:
9897
- .string "ih_comp"
9898
-.LASF390:
9899
- .string "post_bind"
9900
-.LASF367:
9901
- .string "unbind"
9902
-.LASF157:
9903
- .string "ft_addr"
9904
-.LASF474:
9905
- .string "uclass_get_device"
9906
-.LASF4:
9907
- .string "uchar"
9908
-.LASF158:
9909
- .string "ft_len"
9910
-.LASF47:
9911
- .string "next"
9912
-.LASF388:
9913
- .string "data"
9914
-.LASF100:
9915
- .string "CMD_RET_SUCCESS"
9916
-.LASF153:
9917
- .string "fit_uname_setup"
9918
-.LASF48:
9919
- .string "prev"
9920
-.LASF212:
9921
- .string "UCLASS_PCH"
9922
-.LASF213:
9923
- .string "UCLASS_PCI"
9924
-.LASF332:
9925
- .string "net_netmask"
9926
-.LASF33:
9927
- .string "driver_data"
9928
-.LASF86:
9929
- .string "IRQ_STACK_START"
9930
-.LASF180:
9931
- .string "UCLASS_ADC"
9932
-.LASF175:
9933
- .string "UCLASS_SPI_EMUL"
9934
-.LASF262:
9935
- .string "tlb_size"
9936
-.LASF150:
9937
- .string "fit_uname_fdt"
9938
- .hidden malloc
9939
- .ident "GCC: (Linaro GCC 6.3-2017.05) 6.3.1 20170404"
9940
- .section .note.GNU-stack,"",@progbits
u-boot/cmd/memtester/ddr_tester_common.c
similarity index 92%rename from u-boot/cmd/memtester/ddr_tester_common.crename to u-boot/cmd/ddr_tool/ddr_tool_common.c
....@@ -5,7 +5,7 @@
55
66 #include <common.h>
77 #include <power/regulator.h>
8
-#include "ddr_tester_common.h"
8
+#include "ddr_tool_common.h"
99
1010 DECLARE_GLOBAL_DATA_PTR;
1111
....@@ -84,6 +84,13 @@
8484 for (i = 0; i < max_bank; i++) {
8585 start_adr[i] = gd->bd->bi_dram[i].start;
8686 length[i] = gd->bd->bi_dram[i].size;
87
+#if defined(CONFIG_ROCKCHIP_RV1126)
88
+ /* On RV1126, writing data to 0x00600000 will cause a crash. */
89
+ if (start_adr[i] == 0 && length[i] > 0x00700000) {
90
+ start_adr[i] = 0x00700000;
91
+ length[i] -= 0x00700000;
92
+ }
93
+#endif
8794 }
8895
8996 length[max_bank - 1] = (gd->start_addr_sp - RESERVED_SP_SIZE -
u-boot/cmd/memtester/ddr_tester_common.h
similarity index 81%rename from u-boot/cmd/memtester/ddr_tester_common.hrename to u-boot/cmd/ddr_tool/ddr_tool_common.h
....@@ -4,8 +4,8 @@
44 */
55
66 /* Function declaration. */
7
-#ifndef _CMD_MEMTESTER_DDR_TOOL_COMMON_H
8
-#define _CMD_MEMTESTER_DDR_TOOL_COMMON_H
7
+#ifndef __CMD_DDR_TOOL_DDR_TOOL_COMMON_H
8
+#define __CMD_DDR_TOOL_DDR_TOOL_COMMON_H
99
1010 /* reserved 1MB for stack */
1111 #define RESERVED_SP_SIZE 0x100000
....@@ -17,4 +17,4 @@
1717 void get_print_available_addr(ulong *start_adr, ulong *length, int print_en);
1818 int judge_test_addr(ulong *arg, ulong *start_adr, ulong *length);
1919 int set_vdd_logic(u32 uv);
20
-#endif /* _CMD_MEMTESTER_DDR_TOOL_COMMON_H */
20
+#endif /* __CMD_DDR_TOOL_DDR_TOOL_COMMON_H */
u-boot/cmd/ddr_tool/ddr_tool_mp.S
....@@ -0,0 +1,171 @@
1
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
2
+/*
3
+ * Copyright (C) 2023 Rockchip Electronics Co., Ltd.
4
+ */
5
+
6
+ .global __sp
7
+
8
+ .global secondary_main
9
+ .global secondary_init
10
+ .global get_cpu_id
11
+ .global lock_byte_mutex
12
+ .global unlock_byte_mutex
13
+
14
+#ifndef CONFIG_ARM64
15
+ .align 7
16
+vectors_2:
17
+ ldr pc, =die_loop /* reset */
18
+ ldr pc, =die_loop /* undefine */
19
+ ldr pc, =die_loop /* swi */
20
+ ldr pc, =die_loop /* iabort */
21
+ ldr pc, =die_loop /* dabort */
22
+ ldr pc, =die_loop /* reserved */
23
+ ldr pc, =die_loop /* irq */
24
+ ldr pc, =die_loop /* fiq */
25
+
26
+ .align 7
27
+die_loop:
28
+ b die_loop
29
+
30
+ .align 7
31
+ .type secondary_init, %function
32
+secondary_init:
33
+ bl irq_disable
34
+ bl icache_invalid
35
+
36
+ /* set sp */
37
+ ldr r2, =__sp
38
+ ldr r1, [r2]
39
+ bic r1, r1, #0xf
40
+ mov sp, r1
41
+ bl icache_invalid
42
+
43
+ mrc p15, 0, r0, c1, c0, 0 /* CP15 C1 System Control Register */
44
+ bic r0, r0, #0x2000 /* clear V (bit[13], VBAR) */
45
+ mcr p15, 0, r0, c1, c0, 0 /* for remap VBAR */
46
+ ldr r0, =vectors_2
47
+ mcr p15, 0, r0, c12, c0, 0
48
+ bl icache_invalid
49
+
50
+ b secondary_main
51
+
52
+irq_disable:
53
+ mrs r0, cpsr
54
+ orr r0, r0, #0xc0
55
+ msr cpsr, r0
56
+ bx lr
57
+
58
+icache_invalid:
59
+ mov r0, #0
60
+ mcr p15, 0, r0, c7, c5, 0
61
+ bx lr
62
+
63
+ .type get_cpu_id, %function
64
+get_cpu_id:
65
+ mrc p15, 0, r0, c0, c0, 5
66
+ and r0, r0, #0x3
67
+ bx lr
68
+
69
+ .align 7
70
+ .type lock_byte_mutex, %function
71
+lock_byte_mutex:
72
+ mov r2, #0x1
73
+try:
74
+ ldrex r1, [r0]
75
+ cmp r1, #0
76
+ strexeq r1, r2, [r0]
77
+ cmpeq r1, #0
78
+ bne try
79
+ dmb
80
+ bx lr
81
+
82
+ .align 7
83
+ .type unlock_byte_mutex, %function
84
+unlock_byte_mutex:
85
+ dmb
86
+ mov r1, #0
87
+ str r1, [r0]
88
+ dsb
89
+ bx lr
90
+#else /* CONFIG_ARM64 */
91
+ .align 7
92
+el2_vectors:
93
+synchronous_sp0:
94
+ b secondary_init
95
+ .align 7
96
+irq_sp0:
97
+ b irq_sp0
98
+ .align 7
99
+fiq_sp0:
100
+ b fiq_sp0
101
+ .align 7
102
+serror_sp0:
103
+ b serror_sp0
104
+ .align 7
105
+synchronous_spx:
106
+ b synchronous_spx
107
+ .align 7
108
+irq_spx:
109
+ b irq_spx
110
+ .align 7
111
+fiq_spx:
112
+ b fiq_spx
113
+ .align 7
114
+serror_spx:
115
+ b serror_spx
116
+
117
+ .align 7
118
+ .type secondary_init, %function
119
+secondary_init:
120
+ bl irq_disable
121
+
122
+ /* set sp */
123
+ ldr x2, =__sp
124
+ ldr x1, [x2]
125
+ bic x1, x1, #0xf
126
+ mov sp, x1
127
+ bl icache_invalid
128
+
129
+ ldr w0, =el2_vectors
130
+ msr vbar_el2, x0
131
+ bl icache_invalid
132
+
133
+ bl secondary_main
134
+
135
+ .type irq_disable, %function
136
+irq_disable:
137
+ msr daifset, #0x3
138
+ ic iallu
139
+ ret
140
+
141
+ .type icache_invalid, %function
142
+icache_invalid:
143
+ ic iallu
144
+ ret
145
+
146
+ .align 7
147
+ .type lock_byte_mutex, %function
148
+lock_byte_mutex:
149
+ ldxrb w1, [x0]
150
+ cmp w1, #1
151
+ bne 1f
152
+ wfe
153
+ b lock_byte_mutex
154
+1:
155
+ mov x1, #1
156
+ stxrb w2, w1, [x0]
157
+ cmp w2, #0
158
+ bne lock_byte_mutex
159
+ dmb sy
160
+ ret
161
+
162
+ .align 7
163
+ .type unlock_byte_mutex, %function
164
+unlock_byte_mutex:
165
+ dmb sy
166
+ mov x1, #0
167
+ strb w1, [x0]
168
+ dsb sy
169
+ sev
170
+ ret
171
+#endif /* #ifdef CONFIG_ARM */
u-boot/cmd/memtester/io_map.c
similarity index 100%rename from u-boot/cmd/memtester/io_map.crename to u-boot/cmd/ddr_tool/io_map.c
u-boot/cmd/memtester/io_map.h
similarity index 64%rename from u-boot/cmd/memtester/io_map.hrename to u-boot/cmd/ddr_tool/io_map.h
....@@ -3,12 +3,12 @@
33 * Copyright (C) 2019 Rockchip Electronics Co., Ltd.
44 */
55
6
-#ifndef _CMD_MEMTESTER_IO_MAP_H
7
-#define _CMD_MEMTESTER_IO_MAP_H
6
+#ifndef __CMD_DDR_TOOL_MEMTESTER_IO_MAP_H
7
+#define __CMD_DDR_TOOL_MEMTESTER_IO_MAP_H
88
99 #define CPU_2_IO_ALIGN_LEN (16) /* 16 byte */
1010
1111 int data_cpu_2_io(void *p, u32 len);
1212 void data_cpu_2_io_init(void);
1313
14
-#endif /* _CMD_MEMTESTER_IO_MAP_H */
14
+#endif /* __CMD_DDR_TOOL_MEMTESTER_IO_MAP_H */
u-boot/cmd/ddr_tool/memtester/Makefile
....@@ -0,0 +1,8 @@
1
+#
2
+# (C) Copyright 2023 Rockchip Electronics Co., Ltd.
3
+#
4
+# SPDX-License-Identifier: GPL-2.0+
5
+#
6
+
7
+obj-$(CONFIG_CMD_MEMTESTER) += memtester.o
8
+obj-$(CONFIG_CMD_MEMTESTER) += tests.o
u-boot/cmd/memtester/memtester.c
similarity index 98%rename from u-boot/cmd/memtester/memtester.crename to u-boot/cmd/ddr_tool/memtester/memtester.c
....@@ -20,8 +20,8 @@
2020 #include "sizes.h"
2121 #include "types.h"
2222 #include "tests.h"
23
-#include "io_map.h"
24
-#include "ddr_tester_common.h"
23
+#include "../ddr_tool_common.h"
24
+#include "../io_map.h"
2525
2626 #define EXIT_FAIL_NONSTARTER 0x01
2727 #define EXIT_FAIL_ADDRESSLINES 0x02
u-boot/cmd/memtester/memtester.h
similarity index 86%rename from u-boot/cmd/memtester/memtester.hrename to u-boot/cmd/ddr_tool/memtester/memtester.h
....@@ -13,8 +13,8 @@
1313 * See other comments in that file.
1414 *
1515 */
16
-#ifndef _CMD_MEMTESTER_H
17
-#define _CMD_MEMTESTER_H
16
+#ifndef __CMD_DDR_TOOL_MEMTESTER_MEMTESTER_H
17
+#define __CMD_DDR_TOOL_MEMTESTER_MEMTESTER_H
1818 #include <linux/types.h>
1919
2020 /* extern declarations. */
....@@ -25,4 +25,4 @@
2525 int doing_memtester(unsigned long *arg, unsigned long testenable,
2626 unsigned long loops, unsigned long err_exit,
2727 unsigned long fix_bit, unsigned long fix_level);
28
-#endif /* _CMD_MEMTESTER_H */
28
+#endif /* __CMD_DDR_TOOL_MEMTESTER_MEMTESTER_H */
u-boot/cmd/memtester/sizes.h
similarity index 86%rename from u-boot/cmd/memtester/sizes.hrename to u-boot/cmd/ddr_tool/memtester/sizes.h
....@@ -12,8 +12,8 @@
1212 * This file contains some macro definitions for handling 32/64 bit platforms.
1313 *
1414 */
15
-#ifndef __MEMTESTER_SIZES_H
16
-#define __MEMTESTER_SIZES_H
15
+#ifndef __CMD_DDR_TOOL_MEMTESTER_SIZES_H
16
+#define __CMD_DDR_TOOL_MEMTESTER_SIZES_H
1717
1818 #include <common.h>
1919
....@@ -26,4 +26,4 @@
2626 #define CHECKERBOARD2 0xaaaaaaaa
2727 #define UL_BYTE(x) ((x | x << 8 | x << 16 | x << 24))
2828
29
-#endif /* __MEMTESTER_SIZES_H */
29
+#endif /* __CMD_DDR_TOOL_MEMTESTER_SIZES_H */
u-boot/cmd/memtester/tests.c
similarity index 99%rename from u-boot/cmd/memtester/tests.crename to u-boot/cmd/ddr_tool/memtester/tests.c
....@@ -17,7 +17,7 @@
1717 #include "memtester.h"
1818 #include "sizes.h"
1919 #include "types.h"
20
-#include "io_map.h"
20
+#include "../io_map.h"
2121
2222 union {
2323 unsigned char bytes[UL_LEN / 8];
u-boot/cmd/memtester/tests.h
similarity index 94%rename from u-boot/cmd/memtester/tests.hrename to u-boot/cmd/ddr_tool/memtester/tests.h
....@@ -15,6 +15,9 @@
1515 *
1616 */
1717
18
+#ifndef __CMD_DDR_TOOL_MEMTESTER_TESTS_H
19
+#define __CMD_DDR_TOOL_MEMTESTER_TESTS_H
20
+
1821 /* Function declaration. */
1922
2023 int test_stuck_address(u32v *bufa, size_t count);
....@@ -54,3 +57,5 @@
5457 int test_16bit_wide_random(u32v *bufa, u32v *bufb, size_t count,
5558 ul fix_bit, ul fix_level);
5659 #endif
60
+
61
+#endif /* __CMD_DDR_TOOL_MEMTESTER_TESTS_H */
u-boot/cmd/memtester/types.h
similarity index 100%rename from u-boot/cmd/memtester/types.hrename to u-boot/cmd/ddr_tool/memtester/types.h
u-boot/cmd/ddr_tool/stressapptest/Makefile
....@@ -0,0 +1,7 @@
1
+#
2
+# (C) Copyright 2023 Rockchip Electronics Co., Ltd.
3
+#
4
+# SPDX-License-Identifier: GPL-2.0+
5
+#
6
+
7
+obj-$(CONFIG_CMD_STRESSAPPTEST) += stressapptest.o
u-boot/cmd/ddr_tool/stressapptest/stressapptest.c
....@@ -0,0 +1,1207 @@
1
+// Copyright 2006 Google Inc. All Rights Reserved.
2
+/* Licensed under the Apache License, Version 2.0 (the "License");
3
+ * you may not use this file except in compliance with the License.
4
+ * You may obtain a copy of the License at
5
+ *
6
+ * http://www.apache.org/licenses/LICENSE-2.0
7
+ *
8
+ * Unless required by applicable law or agreed to in writing, software
9
+ * distributed under the License is distributed on an "AS IS" BASIS,
10
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
11
+ * See the License for the specific language governing permissions and
12
+ * limitations under the License.
13
+ */
14
+
15
+/* This is stressapptest for Rockchip platform in U-Boot, the design idea and
16
+ * the patterns are from code.google.com/p/stressapptest.
17
+ */
18
+
19
+#include <common.h>
20
+#include <amp.h>
21
+#include <div64.h>
22
+#include <malloc.h>
23
+#include <asm/arch/rockchip_smccc.h>
24
+#include "stressapptest.h"
25
+#include "../ddr_tool_common.h"
26
+
27
+#define __version__ "v1.2.0 20230619"
28
+
29
+#if defined(CONFIG_ARM64)
30
+/* Float operation in TOOLCHAIN_ARM32 will cause the compile error */
31
+#define WARM_CPU
32
+#endif
33
+
34
+#define PAT_NUM 26
35
+#define PATTERN_LIST_SIZE (PAT_NUM * 2 * 4)
36
+
37
+#define CPU_NUM_MAX 16
38
+
39
+static u32 walking_1_data[] = {
40
+ 0x00000001, 0x00000002, 0x00000004, 0x00000008,
41
+ 0x00000010, 0x00000020, 0x00000040, 0x00000080,
42
+ 0x00000100, 0x00000200, 0x00000400, 0x00000800,
43
+ 0x00001000, 0x00002000, 0x00004000, 0x00008000,
44
+ 0x00010000, 0x00020000, 0x00040000, 0x00080000,
45
+ 0x00100000, 0x00200000, 0x00400000, 0x00800000,
46
+ 0x01000000, 0x02000000, 0x04000000, 0x08000000,
47
+ 0x10000000, 0x20000000, 0x40000000, 0x80000000,
48
+ 0x40000000, 0x20000000, 0x10000000, 0x08000000,
49
+ 0x04000000, 0x02000000, 0x01000000, 0x00800000,
50
+ 0x00400000, 0x00200000, 0x00100000, 0x00080000,
51
+ 0x00040000, 0x00020000, 0x00010000, 0x00008000,
52
+ 0x00004000, 0x00002000, 0x00001000, 0x00000800,
53
+ 0x00000400, 0x00000200, 0x00000100, 0x00000080,
54
+ 0x00000040, 0x00000020, 0x00000010, 0x00000008,
55
+ 0x00000004, 0x00000002, 0x00000001, 0x00000000
56
+};
57
+
58
+static struct pat walking_1 = {
59
+ "walking_1",
60
+ walking_1_data,
61
+ ARRAY_SIZE(walking_1_data) - 1, /* mask */
62
+ {1, 1, 2, 1} /* weight */
63
+};
64
+
65
+static u32 walking_1_x16_data[] = {
66
+ 0x00020001, 0x00080004, 0x00200010, 0x00800040,
67
+ 0x02000100, 0x08000400, 0x20001000, 0x80004000,
68
+ 0x20004000, 0x08001000, 0x02000400, 0x00800100,
69
+ 0x00200040, 0x00080010, 0x00020004, 0x00000001
70
+};
71
+
72
+static struct pat walking_1_x16 = {
73
+ "walking_1_x16",
74
+ walking_1_x16_data,
75
+ ARRAY_SIZE(walking_1_x16_data) - 1, /* mask */
76
+ {2, 0, 0, 0} /* Weight for choosing 32/64/128/256 bit wide of this pattern */
77
+ /* Reuse for walking_0_x16, because of invert */
78
+};
79
+
80
+static u32 walking_1_x16_repeat_data[] = {
81
+ 0x00010001, 0x00020002, 0x00040004, 0x00080008,
82
+ 0x00100010, 0x00200020, 0x00400040, 0x00800080,
83
+ 0x01000100, 0x02000200, 0x04000400, 0x08000800,
84
+ 0x10001000, 0x20002000, 0x40004000, 0x80008000,
85
+ 0x40004000, 0x20002000, 0x10001000, 0x08000800,
86
+ 0x04000400, 0x02000200, 0x01000100, 0x00800080,
87
+ 0x00400040, 0x00200020, 0x00100010, 0x00080008,
88
+ 0x00040004, 0x00020002, 0x00010001, 0x00000000
89
+};
90
+
91
+static struct pat walking_1_x16_repeat = {
92
+ "walking_1_x16_repeat",
93
+ walking_1_x16_repeat_data,
94
+ ARRAY_SIZE(walking_1_x16_repeat_data) - 1, /* mask */
95
+ {2, 4, 2, 0} /* Weight for choosing 32/64/128/256 bit wide of this pattern */
96
+ /* Reuse for walking_0_x16_repeat, because of invert */
97
+};
98
+
99
+static u32 walking_inv_1_data[] = {
100
+ 0x00000001, 0xfffffffe, 0x00000002, 0xfffffffd,
101
+ 0x00000004, 0xfffffffb, 0x00000008, 0xfffffff7,
102
+ 0x00000010, 0xffffffef, 0x00000020, 0xffffffdf,
103
+ 0x00000040, 0xffffffbf, 0x00000080, 0xffffff7f,
104
+ 0x00000100, 0xfffffeff, 0x00000200, 0xfffffdff,
105
+ 0x00000400, 0xfffffbff, 0x00000800, 0xfffff7ff,
106
+ 0x00001000, 0xffffefff, 0x00002000, 0xffffdfff,
107
+ 0x00004000, 0xffffbfff, 0x00008000, 0xffff7fff,
108
+ 0x00010000, 0xfffeffff, 0x00020000, 0xfffdffff,
109
+ 0x00040000, 0xfffbffff, 0x00080000, 0xfff7ffff,
110
+ 0x00100000, 0xffefffff, 0x00200000, 0xffdfffff,
111
+ 0x00400000, 0xffbfffff, 0x00800000, 0xff7fffff,
112
+ 0x01000000, 0xfeffffff, 0x02000000, 0xfdffffff,
113
+ 0x04000000, 0xfbffffff, 0x08000000, 0xf7ffffff,
114
+ 0x10000000, 0xefffffff, 0x20000000, 0xdfffffff,
115
+ 0x40000000, 0xbfffffff, 0x80000000, 0x7fffffff,
116
+ 0x40000000, 0xbfffffff, 0x20000000, 0xdfffffff,
117
+ 0x10000000, 0xefffffff, 0x08000000, 0xf7ffffff,
118
+ 0x04000000, 0xfbffffff, 0x02000000, 0xfdffffff,
119
+ 0x01000000, 0xfeffffff, 0x00800000, 0xff7fffff,
120
+ 0x00400000, 0xffbfffff, 0x00200000, 0xffdfffff,
121
+ 0x00100000, 0xffefffff, 0x00080000, 0xfff7ffff,
122
+ 0x00040000, 0xfffbffff, 0x00020000, 0xfffdffff,
123
+ 0x00010000, 0xfffeffff, 0x00008000, 0xffff7fff,
124
+ 0x00004000, 0xffffbfff, 0x00002000, 0xffffdfff,
125
+ 0x00001000, 0xffffefff, 0x00000800, 0xfffff7ff,
126
+ 0x00000400, 0xfffffbff, 0x00000200, 0xfffffdff,
127
+ 0x00000100, 0xfffffeff, 0x00000080, 0xffffff7f,
128
+ 0x00000040, 0xffffffbf, 0x00000020, 0xffffffdf,
129
+ 0x00000010, 0xffffffef, 0x00000008, 0xfffffff7,
130
+ 0x00000004, 0xfffffffb, 0x00000002, 0xfffffffd,
131
+ 0x00000001, 0xfffffffe, 0x00000000, 0xffffffff
132
+};
133
+
134
+static struct pat walking_inv_1 = {
135
+ "walking_inv_1",
136
+ walking_inv_1_data,
137
+ ARRAY_SIZE(walking_inv_1_data) - 1, /* mask */
138
+ {2, 2, 5, 5} /* weight */
139
+};
140
+
141
+static u32 walking_inv_1_x16_data[] = {
142
+ 0xfffe0001, 0xfffd0002, 0xfffb0004, 0xfff70008,
143
+ 0xffef0010, 0xffdf0020, 0xffbf0040, 0xff7f0080,
144
+ 0xfeff0100, 0xfdff0200, 0xfbff0400, 0xf7ff0800,
145
+ 0xefff1000, 0xdfff2000, 0xbfff4000, 0x7fff8000,
146
+ 0xbfff4000, 0xdfff2000, 0xefff1000, 0xf7ff0800,
147
+ 0xfbff0400, 0xfdff0200, 0xfeff0100, 0xff7f0080,
148
+ 0xffbf0040, 0xffdf0020, 0xffef0010, 0xfff70008,
149
+ 0xfffb0004, 0xfffd0002, 0xfffe0001, 0xffff0000
150
+};
151
+
152
+static struct pat walking_inv_1_x16 = {
153
+ "walking_inv_1_x16",
154
+ walking_inv_1_x16_data,
155
+ ARRAY_SIZE(walking_inv_1_x16_data) - 1, /* mask */
156
+ {2, 0, 0, 0} /* weight */
157
+};
158
+
159
+static u32 walking_inv_1_x16_repeat_data[] = {
160
+ 0x00010001, 0xfffefffe, 0x00020002, 0xfffdfffd,
161
+ 0x00040004, 0xfffbfffb, 0x00080008, 0xfff7fff7,
162
+ 0x00100010, 0xffefffef, 0x00200020, 0xffdfffdf,
163
+ 0x00400040, 0xffbfffbf, 0x00800080, 0xff7fff7f,
164
+ 0x01000100, 0xfefffeff, 0x02000200, 0xfdfffdff,
165
+ 0x04000400, 0xfbfffbff, 0x08000800, 0xf7fff7ff,
166
+ 0x10001000, 0xefffefff, 0x20002000, 0xdfffdfff,
167
+ 0x40004000, 0xbfffbfff, 0x80008000, 0x7fff7fff,
168
+ 0x40004000, 0xbfffbfff, 0x20002000, 0xdfffdfff,
169
+ 0x10001000, 0xefffefff, 0x08000800, 0xf7fff7ff,
170
+ 0x04000400, 0xfbfffbff, 0x02000200, 0xfdfffdff,
171
+ 0x01000100, 0xfefffeff, 0x00800080, 0xff7fff7f,
172
+ 0x00400040, 0xffbfffbf, 0x00200020, 0xffdfffdf,
173
+ 0x00100010, 0xffefffef, 0x00080008, 0xfff7fff7,
174
+ 0x00040004, 0xfffbfffb, 0x00020002, 0xfffdfffd,
175
+ 0x00010001, 0xfffefffe, 0x00000000, 0xffffffff
176
+};
177
+
178
+static struct pat walking_inv_1_x16_repeat = {
179
+ "walking_inv_1_x16_repeat",
180
+ walking_inv_1_x16_repeat_data,
181
+ ARRAY_SIZE(walking_inv_1_x16_repeat_data) - 1, /* mask */
182
+ {2, 5, 5, 0} /* weight */
183
+};
184
+
185
+static u32 walking_0_data[] = {
186
+ 0xfffffffe, 0xfffffffd, 0xfffffffb, 0xfffffff7,
187
+ 0xffffffef, 0xffffffdf, 0xffffffbf, 0xffffff7f,
188
+ 0xfffffeff, 0xfffffdff, 0xfffffbff, 0xfffff7ff,
189
+ 0xffffefff, 0xffffdfff, 0xffffbfff, 0xffff7fff,
190
+ 0xfffeffff, 0xfffdffff, 0xfffbffff, 0xfff7ffff,
191
+ 0xffefffff, 0xffdfffff, 0xffbfffff, 0xff7fffff,
192
+ 0xfeffffff, 0xfdffffff, 0xfbffffff, 0xf7ffffff,
193
+ 0xefffffff, 0xdfffffff, 0xbfffffff, 0x7fffffff,
194
+ 0xbfffffff, 0xdfffffff, 0xefffffff, 0xf7ffffff,
195
+ 0xfbffffff, 0xfdffffff, 0xfeffffff, 0xff7fffff,
196
+ 0xffbfffff, 0xffdfffff, 0xffefffff, 0xfff7ffff,
197
+ 0xfffbffff, 0xfffdffff, 0xfffeffff, 0xffff7fff,
198
+ 0xffffbfff, 0xffffdfff, 0xffffefff, 0xfffff7ff,
199
+ 0xfffffbff, 0xfffffdff, 0xfffffeff, 0xffffff7f,
200
+ 0xffffffbf, 0xffffffdf, 0xffffffef, 0xfffffff7,
201
+ 0xfffffffb, 0xfffffffd, 0xfffffffe, 0xffffffff
202
+};
203
+
204
+static struct pat walking_0 = {
205
+ "walking_0",
206
+ walking_0_data,
207
+ ARRAY_SIZE(walking_0_data) - 1, /* mask */
208
+ {1, 1, 2, 1} /* weight */
209
+};
210
+
211
+static u32 one_zero_data[] = {0x00000000, 0xffffffff};
212
+
213
+static struct pat one_zero = {
214
+ "one_zero",
215
+ one_zero_data,
216
+ ARRAY_SIZE(one_zero_data) - 1, /* mask */
217
+ {5, 5, 15, 5} /* weight */
218
+};
219
+
220
+static unsigned int one_zero_x16_data[] = {0x0000ffff, 0x0000ffff};
221
+
222
+static struct pat one_zero_x16 = {
223
+ "one_zero_x16",
224
+ one_zero_x16_data,
225
+ ARRAY_SIZE(one_zero_x16_data) - 1, /* mask */
226
+ {5, 0, 0, 0} /* weight */
227
+};
228
+
229
+static u32 just_0_data[] = {0x00000000, 0x00000000};
230
+
231
+static struct pat just_0 = {
232
+ "just_0",
233
+ just_0_data,
234
+ ARRAY_SIZE(just_0_data) - 1, /* mask */
235
+ {2, 0, 0, 0} /* weight */
236
+};
237
+
238
+static u32 just_1_data[] = {0xffffffff, 0xffffffff};
239
+
240
+static struct pat just_1 = {
241
+ "just_1",
242
+ just_1_data,
243
+ ARRAY_SIZE(just_1_data) - 1, /* mask */
244
+ {2, 0, 0, 0} /* weight */
245
+};
246
+
247
+static u32 just_5_data[] = {0x55555555, 0x55555555};
248
+
249
+static struct pat just_5 = {
250
+ "just_5",
251
+ just_5_data,
252
+ ARRAY_SIZE(just_5_data) - 1, /* mask */
253
+ {2, 0, 0, 0} /* weight */
254
+};
255
+
256
+static u32 just_a_data[] = {0xaaaaaaaa, 0xaaaaaaaa};
257
+
258
+static struct pat just_a = {
259
+ "just_a",
260
+ just_a_data,
261
+ ARRAY_SIZE(just_a_data) - 1, /* mask */
262
+ {2, 0, 0, 0} /* weight */
263
+};
264
+
265
+static u32 five_a_data[] = {0x55555555, 0xaaaaaaaa};
266
+
267
+static struct pat five_a = {
268
+ "five_a",
269
+ five_a_data,
270
+ ARRAY_SIZE(five_a_data) - 1, /* mask */
271
+ {1, 1, 1, 1} /* weight */
272
+};
273
+
274
+static unsigned int five_a_x16_data[] = {0x5555aaaa, 0x5555aaaa};
275
+
276
+static struct pat five_a_x16 = {
277
+ "five_a_x16",
278
+ five_a_x16_data,
279
+ ARRAY_SIZE(five_a_x16_data) - 1, /* mask */
280
+ {1, 0, 0, 0} /* weight */
281
+};
282
+
283
+static u32 five_a8_data[] = {
284
+ 0x5aa5a55a, 0xa55a5aa5, 0xa55a5aa5, 0x5aa5a55a
285
+};
286
+
287
+static struct pat five_a8 = {
288
+ "five_a8",
289
+ five_a8_data,
290
+ ARRAY_SIZE(five_a8_data) - 1, /* mask */
291
+ {1, 1, 1, 1} /* weight */
292
+};
293
+
294
+static u32 five_a8_x16_data[] = {0x5aa5a55a, 0xa55a5aa5};
295
+
296
+static struct pat five_a8_x16 = {
297
+ "five_a8_x16",
298
+ five_a8_x16_data,
299
+ ARRAY_SIZE(five_a8_x16_data) - 1, /* mask */
300
+ {1, 0, 0, 0} /* weight */
301
+};
302
+
303
+static unsigned int five_a8_x16_repeat_data[] = {
304
+ 0x5aa55aa5, 0xa55aa55a, 0xa55aa55a, 0x5aa55aa5
305
+};
306
+
307
+static struct pat five_a8_x16_repeat = {
308
+ "five_a8_x16_repeat",
309
+ five_a8_x16_repeat_data,
310
+ ARRAY_SIZE(five_a8_x16_repeat_data) - 1, /* mask */
311
+ {1, 1, 1, 0} /* weight */
312
+};
313
+
314
+static u32 long_8b10b_data[] = {0x16161616, 0x16161616};
315
+
316
+static struct pat long_8b10b = {
317
+ "long_8b10b",
318
+ long_8b10b_data,
319
+ ARRAY_SIZE(long_8b10b_data) - 1, /* mask */
320
+ {2, 0, 0, 0} /* weight */
321
+};
322
+
323
+static u32 short_8b10b_data[] = {0xb5b5b5b5, 0xb5b5b5b5};
324
+
325
+static struct pat short_8b10b = {
326
+ "short_8b10b",
327
+ short_8b10b_data,
328
+ ARRAY_SIZE(short_8b10b_data) - 1, /* mask */
329
+ {2, 0, 0, 0} /* weight */
330
+};
331
+
332
+static u32 checker_8b10b_data[] = {0xb5b5b5b5, 0x4a4a4a4a};
333
+
334
+static struct pat checker_8b10b = {
335
+ "checker_8b10b",
336
+ checker_8b10b_data,
337
+ ARRAY_SIZE(checker_8b10b_data) - 1, /* mask */
338
+ {1, 0, 1, 1} /* weight */
339
+};
340
+
341
+static u32 checker_8b10b_x16_data[] = {0xb5b54a4a, 0xb5b54a4a};
342
+
343
+static struct pat checker_8b10b_x16 = {
344
+ "checker_8b10b_x16",
345
+ checker_8b10b_x16_data,
346
+ ARRAY_SIZE(checker_8b10b_x16_data) - 1, /* mask */
347
+ {1, 0, 0, 0} /* weight */
348
+};
349
+
350
+static u32 five_7_data[] = {0x55555557, 0x55575555};
351
+
352
+static struct pat five_7 = {
353
+ "five_7",
354
+ five_7_data,
355
+ ARRAY_SIZE(five_7_data) - 1, /* mask */
356
+ {0, 2, 0, 0} /* weight */
357
+};
358
+
359
+static u32 five_7_x16_data[] = {0x55575557, 0x57555755};
360
+
361
+static struct pat five_7_x16 = {
362
+ "five_7_x16",
363
+ five_7_x16_data,
364
+ ARRAY_SIZE(five_7_x16_data) - 1, /* mask */
365
+ {2, 0, 0, 0} /* weight */
366
+};
367
+
368
+static u32 zero2_fd_data[] = {0x00020002, 0xfffdfffd};
369
+
370
+static struct pat zero2_fd = {
371
+ "zero2_fd",
372
+ zero2_fd_data,
373
+ ARRAY_SIZE(zero2_fd_data) - 1, /* mask */
374
+ {0, 2, 0, 0} /* weight */
375
+};
376
+
377
+static u32 zero2_fd_x16_data[] = {0x02020202, 0xfdfdfdfd};
378
+
379
+static struct pat zero2_fd_x16 = {
380
+ "zero2_fd_x16",
381
+ zero2_fd_x16_data,
382
+ ARRAY_SIZE(zero2_fd_x16_data) - 1, /* mask */
383
+ {2, 0, 0, 0} /* weight */
384
+};
385
+
386
+static struct pat *pat_array[] = {
387
+ &walking_1,
388
+ &walking_1_x16,
389
+ &walking_1_x16_repeat,
390
+ &walking_inv_1,
391
+ &walking_inv_1_x16,
392
+ &walking_inv_1_x16_repeat,
393
+ &walking_0,
394
+ &one_zero,
395
+ &one_zero_x16,
396
+ &just_0,
397
+ &just_1,
398
+ &just_5,
399
+ &just_a,
400
+ &five_a,
401
+ &five_a_x16,
402
+ &five_a8,
403
+ &five_a8_x16,
404
+ &five_a8_x16_repeat,
405
+ &long_8b10b,
406
+ &short_8b10b,
407
+ &checker_8b10b,
408
+ &checker_8b10b_x16,
409
+ &five_7,
410
+ &five_7_x16,
411
+ &zero2_fd,
412
+ &zero2_fd_x16
413
+};
414
+
415
+static u32 cpu_copy_err[CPU_NUM_MAX];
416
+static u32 cpu_inv_err[CPU_NUM_MAX];
417
+
418
+static u64 start_time_us;
419
+static u64 test_time_us;
420
+
421
+static bool cpu_init_finish[CPU_NUM_MAX];
422
+static bool cpu_test_finish[CPU_NUM_MAX];
423
+static bool pattern_page_init_finish;
424
+
425
+#if (CPU_NUM_MAX > 1)
426
+static ulong test_count = 0;
427
+static ulong __gd; /* set r9/x18 of secondary cpu to gd addr */
428
+#endif
429
+ulong __sp; /* set sp of secondary cpu */
430
+
431
+u32 print_mutex; /* 0: unlock, 1: lock */
432
+
433
+static u64 get_time_us(void)
434
+{
435
+ return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000));
436
+}
437
+
438
+static u64 run_time_us(void)
439
+{
440
+ return get_time_us() - start_time_us;
441
+}
442
+
443
+static void print_time_stamp(void)
444
+{
445
+ u64 time_us;
446
+
447
+ time_us = run_time_us();
448
+
449
+ printf("[%5d.%06d] ", (u32)(time_us / 1000000), (u32)(time_us % 1000000));
450
+}
451
+
452
+static u32 pattern_get(struct pattern *pattern, u32 offset)
453
+{
454
+ u32 ret;
455
+
456
+ ret = pattern->pat->data_array[(offset >> pattern->repeat) &
457
+ pattern->pat->mask];
458
+
459
+ return pattern->inv ? ~ret : ret;
460
+}
461
+
462
+static void pattern_adler_sum_calc(struct pattern *pattern,
463
+ struct stressapptest_params *sat)
464
+{
465
+ int i = 0;
466
+ u64 a1 = 1;
467
+ u64 b1 = 0;
468
+ u64 a2 = 1;
469
+ u64 b2 = 0;
470
+
471
+ while (i < sat->block_size_byte / sizeof(u32)) {
472
+ a1 += (u64)pattern_get(pattern, i++);
473
+ b1 += a1;
474
+ a1 += pattern_get(pattern, i++);
475
+ b1 += a1;
476
+
477
+ a2 += (u64)pattern_get(pattern, i++);
478
+ b2 += a2;
479
+ a2 += pattern_get(pattern, i++);
480
+ b2 += a2;
481
+ }
482
+
483
+ pattern->adler_sum.a1 = a1;
484
+ pattern->adler_sum.b1 = b1;
485
+ pattern->adler_sum.a2 = a2;
486
+ pattern->adler_sum.b2 = b2;
487
+}
488
+
489
+static void pattern_list_init(struct pattern *pattern_list,
490
+ struct stressapptest_params *sat)
491
+{
492
+ u32 weight_count = 0;
493
+ int k = 0;
494
+
495
+ for (int i = 0; i < PAT_NUM; i++) {
496
+ for (int j = 0; j < 8; j++) {
497
+ pattern_list[k].pat = pat_array[i];
498
+ pattern_list[k].inv = j % 2;
499
+ pattern_list[k].repeat = j / 2;
500
+ pattern_list[k].weight = pattern_list[k].pat->weight[j / 2];
501
+ pattern_adler_sum_calc(&pattern_list[k], sat);
502
+ weight_count += pattern_list[k].weight;
503
+ k++;
504
+ }
505
+ }
506
+
507
+ sat->weight_count = weight_count;
508
+}
509
+
510
+static u32 get_max_page_num(ulong page_size_byte)
511
+{
512
+ ulong start_adr[CONFIG_NR_DRAM_BANKS], length[CONFIG_NR_DRAM_BANKS];
513
+ u32 page_num = 0;
514
+
515
+ get_print_available_addr(start_adr, length, 0);
516
+
517
+ page_num = 0;
518
+ for (int i = 0; i < ARRAY_SIZE(start_adr) || i < ARRAY_SIZE(length); i++) {
519
+ if ((start_adr[i] == 0 && length[i] == 0))
520
+ break;
521
+ page_num += (u32)(length[i] / page_size_byte);
522
+ }
523
+
524
+ return page_num;
525
+}
526
+
527
+static int get_page_addr(struct page *page_list,
528
+ struct stressapptest_params *sat)
529
+{
530
+ ulong start_adr[CONFIG_NR_DRAM_BANKS], length[CONFIG_NR_DRAM_BANKS];
531
+ ulong used_length;
532
+ u32 page = 0;
533
+
534
+ get_print_available_addr(start_adr, length, 0);
535
+
536
+ printf("Address for test:\n Start End Length\n");
537
+ for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
538
+ if ((start_adr[i] == 0 && length[i] == 0) || page >= sat->page_num)
539
+ break;
540
+ if (start_adr[i] + length[i] < sat->total_start_addr)
541
+ continue;
542
+ if (start_adr[i] < sat->total_start_addr) {
543
+ length[i] -= sat->total_start_addr - start_adr[i];
544
+ start_adr[i] = sat->total_start_addr;
545
+ }
546
+
547
+ used_length = 0;
548
+ while (page < sat->page_num &&
549
+ length[i] >= used_length + sat->page_size_byte) {
550
+ page_list[page].base_addr = (void *)(start_adr[i] + used_length);
551
+ used_length += sat->page_size_byte;
552
+ page++;
553
+ }
554
+ printf(" 0x%09lx - 0x%09lx 0x%09lx\n",
555
+ start_adr[i], start_adr[i] + used_length, used_length);
556
+ }
557
+
558
+ printf("page_num = %d, page_size = 0x%lx, total_test_size = 0x%lx\n",
559
+ page, sat->page_size_byte, sat->page_size_byte * page);
560
+
561
+ if (sat->total_test_size_mb == 0) {
562
+ /* No arg for total_test_size_mb, test all available space by default. */
563
+ sat->page_num = page;
564
+ } else if (page < sat->page_num || page < sat->cpu_num * 4) {
565
+ printf("ERROR: Cannot get enough pages to test.\n");
566
+ printf("Please decrease page_size or test_size\n");
567
+
568
+ return -1;
569
+ }
570
+
571
+ return 0;
572
+}
573
+
574
+static void page_init_valid(struct page *page, struct pattern *pattern_list,
575
+ struct stressapptest_params *sat)
576
+{
577
+ int target;
578
+ int i = 0;
579
+ u64 *mem;
580
+
581
+ target = (rand() % sat->weight_count) + 1;
582
+ do {
583
+ target -= pattern_list[i++].weight;
584
+ if (target <= 0)
585
+ break;
586
+ } while (i < PATTERN_LIST_SIZE);
587
+ page->pattern = &pattern_list[--i];
588
+ page->valid = 1;
589
+
590
+ mem = (u64 *)page->base_addr;
591
+ for (i = 0; i < sat->page_size_byte / sizeof(u64); i++)
592
+ mem[i] = (u64)pattern_get(page->pattern, i * 2) |
593
+ (u64)pattern_get(page->pattern, i * 2 + 1) << 32;
594
+}
595
+
596
+static void page_init_empty(struct page *page)
597
+{
598
+ page->valid = 0;
599
+}
600
+
601
+static void page_init(struct pattern *pattern_list,
602
+ struct stressapptest_params *sat)
603
+{
604
+ int i, cpu;
605
+ u32 empty_page_num;
606
+
607
+ for (cpu = 0; cpu < sat->cpu_num; cpu++) {
608
+ empty_page_num = 0;
609
+ for (i = cpu; i < sat->page_num; i += sat->cpu_num) {
610
+ if (rand() % 5 < 3) {
611
+ page_list[i].valid = 1;
612
+ } else {
613
+ page_list[i].valid = 0;
614
+ empty_page_num++;
615
+ }
616
+ }
617
+ while (empty_page_num >= sat->page_num / sat->cpu_num / 2 && i > 0) {
618
+ i -= sat->cpu_num;
619
+ if (page_list[i].valid == 0) {
620
+ page_list[i].valid = 1;
621
+ empty_page_num--;
622
+ }
623
+ }
624
+ i = cpu;
625
+ while (empty_page_num < 2 && i < sat->page_num) {
626
+ if (page_list[i].valid == 1) {
627
+ page_list[i].valid = 0;
628
+ empty_page_num++;
629
+ }
630
+ i += sat->cpu_num;
631
+ }
632
+ }
633
+
634
+ for (i = 0; i < sat->page_num; i++) {
635
+ if (page_list[i].valid == 1)
636
+ page_init_valid(&page_list[i], pattern_list, sat);
637
+ else
638
+ page_init_empty(&page_list[i]);
639
+ }
640
+ flush_dcache_all();
641
+}
642
+
643
+static u32 page_rand_pick(struct page *page_list, bool valid,
644
+ struct stressapptest_params *sat, u8 cpu_id)
645
+{
646
+ u32 pick;
647
+
648
+ pick = rand() % sat->page_num;
649
+ pick = pick / sat->cpu_num * sat->cpu_num + cpu_id;
650
+ if (pick >= sat->page_num)
651
+ pick = cpu_id;
652
+
653
+ while (page_list[pick].valid != valid) {
654
+ pick += sat->cpu_num;
655
+ if (pick >= sat->page_num)
656
+ pick = cpu_id;
657
+ }
658
+
659
+ return pick;
660
+}
661
+
662
+static u32 block_mis_search(void *dst_addr, struct pattern *src_pattern, char *item,
663
+ struct stressapptest_params *sat, u8 cpu_id)
664
+{
665
+ u32 *dst_mem;
666
+ u32 read, reread, expected;
667
+ u32 err = 0;
668
+ u32 *print_addr;
669
+ int i, j;
670
+
671
+ dst_mem = (u32 *)dst_addr;
672
+
673
+ for (i = 0; i < sat->block_size_byte / sizeof(u32); i++) {
674
+ read = dst_mem[i];
675
+ expected = pattern_get(src_pattern, i);
676
+
677
+ if (read != expected) {
678
+ flush_dcache_range((ulong)&dst_mem[i], (ulong)&dst_mem[i + 1]);
679
+ reread = dst_mem[i];
680
+
681
+ lock_byte_mutex(&print_mutex);
682
+
683
+ print_time_stamp();
684
+ printf("%s Hardware Error: miscompare on CPU %d at 0x%lx:\n",
685
+ item, cpu_id, (ulong)&dst_mem[i]);
686
+ printf(" read: 0x%08x\n", read);
687
+ printf(" reread: 0x%08x(reread^read:0x%08x)\n",
688
+ reread, reread ^ read);
689
+ printf(" expected:0x%08x(expected^read:0x%08x)\n",
690
+ expected, expected ^ read);
691
+ printf(" \'%s%s%d\'", src_pattern->pat->name,
692
+ src_pattern->inv ? "~" : "",
693
+ 32 << src_pattern->repeat);
694
+ if (reread == expected)
695
+ printf(" read error");
696
+ printf("\n");
697
+
698
+ /* Dump data around the error address */
699
+ print_addr = &dst_mem[i] - 64;
700
+ for (j = 0; j < 128; j += 8)
701
+ printf(" [0x%010lx] 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
702
+ (ulong)(print_addr + j),
703
+ *(print_addr + j), *(print_addr + j + 1),
704
+ *(print_addr + j + 2), *(print_addr + j + 3),
705
+ *(print_addr + j + 4), *(print_addr + j + 5),
706
+ *(print_addr + j + 6), *(print_addr + j + 7));
707
+
708
+ unlock_byte_mutex(&print_mutex);
709
+
710
+ /* fix the error */
711
+ dst_mem[i] = expected;
712
+ err++;
713
+ }
714
+ }
715
+ flush_dcache_all();
716
+
717
+ if (err == 0) {
718
+ lock_byte_mutex(&print_mutex);
719
+ printf("%s ERROR detected but cannot find mismatch data (maybe read error).\n", item);
720
+ unlock_byte_mutex(&print_mutex);
721
+ }
722
+
723
+ return err;
724
+}
725
+
726
+static u32 block_inv_check(void *dst_addr, struct pattern *src_pattern,
727
+ struct stressapptest_params *sat, u8 cpu_id)
728
+{
729
+ u32 *dst_mem;
730
+ u32 err = 0;
731
+ int i = 0;
732
+#if defined(WARM_CPU)
733
+ double a, b, c, d;
734
+#endif
735
+
736
+ struct adler_sum adler_sum = {
737
+ 1, 0, 1, 0
738
+ };
739
+
740
+ dst_mem = (u32 *)dst_addr;
741
+
742
+#if defined(WARM_CPU)
743
+ a = 2.0 * dst_mem[0];
744
+ b = 5.0 * dst_mem[0];
745
+ c = 7.0 * dst_mem[0];
746
+ d = 9.0 * dst_mem[0];
747
+#endif
748
+
749
+ while (i < sat->block_size_byte / sizeof(u32)) {
750
+ adler_sum.a1 += dst_mem[i++];
751
+ adler_sum.b1 += adler_sum.a1;
752
+ adler_sum.a1 += dst_mem[i++];
753
+ adler_sum.b1 += adler_sum.a1;
754
+
755
+#if defined(WARM_CPU)
756
+ a = a * b;
757
+ b = b + c;
758
+#endif
759
+
760
+ adler_sum.a2 += dst_mem[i++];
761
+ adler_sum.b2 += adler_sum.a2;
762
+ adler_sum.a2 += dst_mem[i++];
763
+ adler_sum.b2 += adler_sum.a2;
764
+#if defined(WARM_CPU)
765
+ c = c * d;
766
+ d = d + d;
767
+#endif
768
+ }
769
+
770
+#if defined(WARM_CPU)
771
+ d = a + b + c + d;
772
+ if (d == 1.0)
773
+ /* Reference the result so that it can't be discarded by the compiler. */
774
+ printf("This will probably never happen.\n");
775
+#endif
776
+
777
+ if (adler_sum.a1 != src_pattern->adler_sum.a1 ||
778
+ adler_sum.b1 != src_pattern->adler_sum.b1 ||
779
+ adler_sum.a2 != src_pattern->adler_sum.a2 ||
780
+ adler_sum.b2 != src_pattern->adler_sum.b2)
781
+ err = block_mis_search(dst_addr, src_pattern, "Inv", sat, cpu_id);
782
+
783
+ return err;
784
+}
785
+
786
+static void page_inv_up(void *src_addr, struct stressapptest_params *sat)
787
+{
788
+ void *dst_addr = src_addr;
789
+ uint data;
790
+ uint *dst_mem;
791
+
792
+ for (int i = 0; i < sat->block_num; i++) {
793
+ dst_mem = (uint *)dst_addr;
794
+ for (int j = 0; j < sat->block_size_byte / sizeof(uint); j++) {
795
+ data = dst_mem[j];
796
+ dst_mem[j] = ~data;
797
+ }
798
+ dst_addr += sat->block_size_byte;
799
+ flush_dcache_all();
800
+ }
801
+}
802
+
803
+static void page_inv_down(void *src_addr, struct stressapptest_params *sat)
804
+{
805
+ void *dst_addr = src_addr;
806
+ uint data;
807
+ uint *dst_mem;
808
+
809
+ dst_addr += sat->block_size_byte * (sat->block_num - 1);
810
+
811
+ for (int i = sat->block_num - 1; i >= 0; i--) {
812
+ dst_mem = (uint *)dst_addr;
813
+ for (int j = sat->block_size_byte / sizeof(uint) - 1; j >= 0; j--) {
814
+ data = dst_mem[j];
815
+ dst_mem[j] = ~data;
816
+ }
817
+ dst_addr -= sat->block_size_byte;
818
+ flush_dcache_all();
819
+ }
820
+}
821
+
822
+static u32 page_inv(struct stressapptest_params *sat, u8 cpu_id)
823
+{
824
+ u32 src;
825
+ void *dst_block_addr;
826
+ u32 err = 0;
827
+
828
+ src = page_rand_pick(page_list, 1, sat, cpu_id); /* pick a valid page */
829
+ dst_block_addr = page_list[src].base_addr;
830
+
831
+ for (int i = 0; i < 4; i++) {
832
+ if (rand() % 2 == 0)
833
+ page_inv_up(page_list[src].base_addr, sat);
834
+ else
835
+ page_inv_down(page_list[src].base_addr, sat);
836
+ }
837
+
838
+ for (int i = 0; i < sat->block_num; i++) {
839
+ err += block_inv_check(dst_block_addr, page_list[src].pattern, sat, cpu_id);
840
+ dst_block_addr += sat->block_size_byte;
841
+ }
842
+
843
+ flush_dcache_all();
844
+
845
+ return err;
846
+}
847
+
848
+static u32 block_copy_check(void *dst_addr, struct adler_sum *adler_sum,
849
+ struct pattern *src_pattern, struct stressapptest_params *sat,
850
+ u8 cpu_id)
851
+{
852
+ u32 err = 0;
853
+
854
+ if (adler_sum->a1 != src_pattern->adler_sum.a1 ||
855
+ adler_sum->b1 != src_pattern->adler_sum.b1 ||
856
+ adler_sum->a2 != src_pattern->adler_sum.a2 ||
857
+ adler_sum->b2 != src_pattern->adler_sum.b2)
858
+ err = block_mis_search(dst_addr, src_pattern, "Copy", sat, cpu_id);
859
+
860
+ return err;
861
+}
862
+
863
+static u32 block_copy(void *dst_addr, void *src_addr,
864
+ struct pattern *src_pattern,
865
+ struct stressapptest_params *sat, u8 cpu_id)
866
+{
867
+ u64 *dst_mem;
868
+ u64 *src_mem;
869
+ u64 data;
870
+ int i = 0;
871
+#if defined(WARM_CPU)
872
+ double a, b, c, d;
873
+#endif
874
+
875
+ struct adler_sum adler_sum = {
876
+ 1, 0, 1, 0
877
+ };
878
+
879
+ dst_mem = (u64 *)dst_addr;
880
+ src_mem = (u64 *)src_addr;
881
+
882
+#if defined(WARM_CPU)
883
+ a = 2.0 * src_mem[0];
884
+ b = 5.0 * src_mem[0];
885
+ c = 7.0 * src_mem[0];
886
+ d = 9.0 * src_mem[0];
887
+#endif
888
+
889
+ while (i < sat->block_size_byte / sizeof(u64)) {
890
+ data = src_mem[i];
891
+ adler_sum.a1 += data & 0xffffffff;
892
+ adler_sum.b1 += adler_sum.a1;
893
+ adler_sum.a1 += data >> 32;
894
+ adler_sum.b1 += adler_sum.a1;
895
+ dst_mem[i] = data;
896
+ i++;
897
+
898
+#if defined(WARM_CPU)
899
+ a = a * b;
900
+ b = b + c;
901
+#endif
902
+
903
+ data = src_mem[i];
904
+ adler_sum.a2 += data & 0xffffffff;
905
+ adler_sum.b2 += adler_sum.a2;
906
+ adler_sum.a2 += data >> 32;
907
+ adler_sum.b2 += adler_sum.a2;
908
+ dst_mem[i] = data;
909
+ i++;
910
+
911
+#if defined(WARM_CPU)
912
+ c = c * d;
913
+ d = d + d;
914
+#endif
915
+ }
916
+
917
+ flush_dcache_all();
918
+
919
+#if defined(WARM_CPU)
920
+ d = a + b + c + d;
921
+ if (d == 1.0)
922
+ /* Reference the result so that it can't be discarded by the compiler. */
923
+ printf("This will probably never happen.\n");
924
+#endif
925
+
926
+ return block_copy_check(dst_addr, &adler_sum, src_pattern, sat, cpu_id);
927
+}
928
+
929
+static u32 page_copy(struct stressapptest_params *sat, u8 cpu_id)
930
+{
931
+ u32 dst;
932
+ u32 src;
933
+ void *dst_block_addr;
934
+ void *src_block_addr;
935
+ u32 err = 0;
936
+
937
+ dst = page_rand_pick(page_list, 0, sat, cpu_id); /* pick a empty page */
938
+ dst_block_addr = page_list[dst].base_addr;
939
+ src = page_rand_pick(page_list, 1, sat, cpu_id); /* pick a valid page */
940
+ src_block_addr = page_list[src].base_addr;
941
+ flush_dcache_all();
942
+
943
+ for (int i = 0; i < sat->block_num; i++) {
944
+ err += block_copy(dst_block_addr, src_block_addr,
945
+ page_list[src].pattern, sat, cpu_id);
946
+ dst_block_addr += sat->block_size_byte;
947
+ src_block_addr += sat->block_size_byte;
948
+ }
949
+
950
+ page_list[dst].pattern = page_list[src].pattern;
951
+ page_list[dst].valid = 1;
952
+ page_list[src].valid = 0;
953
+ flush_dcache_all();
954
+
955
+ return err;
956
+}
957
+
958
+void secondary_main(void)
959
+{
960
+#if (CPU_NUM_MAX > 1)
961
+ u8 cpu_id;
962
+ ulong test = 0;
963
+
964
+#ifndef CONFIG_ARM64
965
+ asm volatile("mov r9, %0" : : "r" (__gd)); /* set r9 to gd addr */
966
+#else
967
+ asm volatile("mov x18, %0" : : "r" (__gd)); /* set x18 to gd addr */
968
+#endif
969
+ dcache_enable();
970
+ icache_enable();
971
+
972
+ udelay(100);
973
+
974
+ flush_dcache_all();
975
+
976
+ cpu_id = sat.cpu_num;
977
+ cpu_init_finish[cpu_id] = 1;
978
+ printf("CPU%d start OK.\n", cpu_id);
979
+
980
+ while (pattern_page_init_finish == 0) {
981
+ udelay(100);
982
+ flush_dcache_all();
983
+ }
984
+
985
+ while (1) {
986
+ udelay(100);
987
+ flush_dcache_all();
988
+ while (test < test_count) {
989
+ cpu_test_finish[cpu_id] = 0;
990
+ flush_dcache_all();
991
+ while (run_time_us() < test_time_us) {
992
+ if (rand() % 2 == 0)
993
+ cpu_copy_err[cpu_id] += page_copy(&sat, cpu_id);
994
+ else
995
+ cpu_inv_err[cpu_id] += page_inv(&sat, cpu_id);
996
+ }
997
+ test++;
998
+ cpu_test_finish[cpu_id] = 1;
999
+ flush_dcache_all();
1000
+ }
1001
+ }
1002
+#else
1003
+ return;
1004
+#endif
1005
+}
1006
+
1007
+static int doing_stressapptest(void)
1008
+{
1009
+ int i;
1010
+ u32 pre_10s;
1011
+ u32 now_10s;
1012
+
1013
+ struct pattern pattern_list[PATTERN_LIST_SIZE];
1014
+ void *page_info;
1015
+
1016
+ u32 all_copy_err = 0;
1017
+ u32 all_inv_err = 0;
1018
+ u32 cpu_no_response_err = 0;
1019
+
1020
+ int ret = CMD_RET_SUCCESS;
1021
+
1022
+ for (i = 0; i < CPU_NUM_MAX; i++) {
1023
+ cpu_copy_err[i] = 0;
1024
+ cpu_inv_err[i] = 0;
1025
+ cpu_init_finish[i] = 0;
1026
+ cpu_test_finish[i] = 0;
1027
+ }
1028
+ pattern_page_init_finish = 0;
1029
+ print_mutex = 0;
1030
+ asm volatile("clrex");
1031
+
1032
+#if (CPU_NUM_MAX > 1)
1033
+ if (test_count == 0) {
1034
+ __gd = (ulong)gd;
1035
+ asm volatile("mov %0, sp" : "=r" (__sp));
1036
+ printf("CPU0 sp is at 0x%lx now.\n", __sp);
1037
+ __sp &= ~(ulong)0xffff;
1038
+ for (sat.cpu_num = 1; sat.cpu_num < CPU_NUM_MAX; sat.cpu_num++) {
1039
+ __sp -= 0x10000;
1040
+ flush_dcache_all();
1041
+ if (psci_cpu_on(sat.cpu_num, (ulong)secondary_init) == 0) {
1042
+ mdelay(10);
1043
+ printf("Calling CPU%d, sp = 0x%lx\n", sat.cpu_num, __sp);
1044
+ } else {
1045
+ break;
1046
+ }
1047
+ while (cpu_init_finish[sat.cpu_num] == 0) {
1048
+ udelay(1000);
1049
+ flush_dcache_all();
1050
+ }
1051
+ }
1052
+ }
1053
+#else
1054
+ sat.cpu_num = 1;
1055
+#endif
1056
+
1057
+ if (sat.total_test_size_mb == 0)
1058
+ sat.page_num = get_max_page_num(sat.page_size_byte);
1059
+ else
1060
+ sat.page_num = (sat.total_test_size_mb << 20) / sat.page_size_byte;
1061
+ sat.block_num = sat.page_size_byte / sat.block_size_byte;
1062
+
1063
+ udelay(100);
1064
+
1065
+ page_info = malloc(sizeof(struct page) * sat.page_num);
1066
+ if (page_info == 0) {
1067
+ printf("ERROR: StressAppTest fail to malloc.\n");
1068
+ printf("Please try increasing CONFIG_SYS_MALLOC_LEN in include/configs/rxxxxx_common.h.\n");
1069
+ ret = CMD_RET_FAILURE;
1070
+ goto out;
1071
+ }
1072
+ page_list = (struct page *)page_info;
1073
+
1074
+ if (get_page_addr(page_list, &sat) < 0) {
1075
+ ret = CMD_RET_FAILURE;
1076
+ goto out;
1077
+ }
1078
+
1079
+ pattern_list_init(pattern_list, &sat);
1080
+ page_init(pattern_list, &sat);
1081
+
1082
+#if (CPU_NUM_MAX > 1)
1083
+ if (sat.cpu_num > 1) {
1084
+ pattern_page_init_finish = 1;
1085
+ test_count++;
1086
+ flush_dcache_all();
1087
+ }
1088
+#endif
1089
+
1090
+ pre_10s = (u32)(run_time_us() / 1000000 / 10);
1091
+ lock_byte_mutex(&print_mutex);
1092
+ print_time_stamp();
1093
+ printf("Start StressAppTest in U-Boot:\n");
1094
+ unlock_byte_mutex(&print_mutex);
1095
+
1096
+ while (run_time_us() < test_time_us) {
1097
+ if (rand() % 2 == 0)
1098
+ cpu_copy_err[0] += page_copy(&sat, 0);
1099
+ else
1100
+ cpu_inv_err[0] += page_inv(&sat, 0);
1101
+
1102
+ /* Print every 10 seconds */
1103
+ now_10s = (u32)(run_time_us() / 1000000 / 10);
1104
+ if (now_10s > pre_10s) {
1105
+ pre_10s = now_10s;
1106
+ lock_byte_mutex(&print_mutex);
1107
+ print_time_stamp();
1108
+ printf("Seconds remaining: %d\n", (u32)(test_time_us / 1000000 - now_10s * 10));
1109
+ unlock_byte_mutex(&print_mutex);
1110
+ }
1111
+ }
1112
+
1113
+#if (CPU_NUM_MAX > 1)
1114
+ for (i = 1; i < sat.cpu_num; i++) {
1115
+ while (cpu_test_finish[i] == 0) {
1116
+ if ((u32)(run_time_us() / 1000000 / 10) > pre_10s + 6) {
1117
+ /* wait for secondary CPU in 60s */
1118
+ lock_byte_mutex(&print_mutex);
1119
+ print_time_stamp();
1120
+ printf("ERROR: Cannot wait for CPU%d to finish!\n", i);
1121
+ unlock_byte_mutex(&print_mutex);
1122
+ cpu_no_response_err++;
1123
+ break;
1124
+ }
1125
+ mdelay(1);
1126
+ flush_dcache_all();
1127
+ }
1128
+ }
1129
+#endif
1130
+
1131
+ for (i = 0; i < sat.cpu_num; i++) {
1132
+ all_copy_err += cpu_copy_err[i];
1133
+ all_inv_err += cpu_inv_err[i];
1134
+ }
1135
+ print_time_stamp();
1136
+ printf("StressAppTest Result: ");
1137
+ if (all_copy_err == 0 && all_inv_err == 0 && cpu_no_response_err == 0)
1138
+ printf("Pass.\n");
1139
+ else
1140
+ printf("FAIL!\nStressAppTest detects %d copy errors, %d inv errors.\n",
1141
+ all_copy_err, all_inv_err);
1142
+
1143
+out:
1144
+ free(page_info);
1145
+
1146
+ return ret;
1147
+}
1148
+
1149
+static int do_stressapptest(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1150
+{
1151
+ ulong test_time_sec = 20;
1152
+ ulong page_size_kb = 1024;
1153
+
1154
+ sat.total_test_size_mb = 0;
1155
+ sat.block_size_byte = 4096;
1156
+ sat.total_start_addr = 0x0;
1157
+
1158
+ printf("StressAppTest in U-Boot, " __version__ "\n");
1159
+
1160
+ if (argc > 1) {
1161
+ if (strict_strtoul(argv[1], 0, &test_time_sec) < 0)
1162
+ return CMD_RET_USAGE;
1163
+ if (test_time_sec < 1)
1164
+ test_time_sec = 20;
1165
+ }
1166
+ if (argc > 2) {
1167
+ if (strict_strtoul(argv[2], 0, &sat.total_test_size_mb) < 0)
1168
+ return CMD_RET_USAGE;
1169
+ if (sat.total_test_size_mb < 1)
1170
+ sat.total_test_size_mb = 0;
1171
+ }
1172
+ if (argc > 3) {
1173
+ if (strict_strtoul(argv[3], 0, &sat.total_start_addr) < 0)
1174
+ return CMD_RET_USAGE;
1175
+ if (sat.total_start_addr < 0x1)
1176
+ sat.total_start_addr = 0x0;
1177
+ }
1178
+ if (argc > 4) {
1179
+ if (strict_strtoul(argv[4], 0, &page_size_kb) < 0)
1180
+ return CMD_RET_USAGE;
1181
+ if (page_size_kb < 1)
1182
+ page_size_kb = 1024;
1183
+ }
1184
+
1185
+ sat.page_size_byte = page_size_kb << 10;
1186
+
1187
+ start_time_us = get_time_us();
1188
+ test_time_us = (u64)test_time_sec * 1000000;
1189
+
1190
+ /* Change rand seed. If not do this, rand() would be same after boot.*/
1191
+ srand((unsigned int)(start_time_us & 0xffffffff));
1192
+
1193
+ return doing_stressapptest();
1194
+}
1195
+
1196
+U_BOOT_CMD(stressapptest, 5, 1, do_stressapptest,
1197
+ "StressAppTest for Rockchip\n",
1198
+ "\narg1: test time in second, default value is 20s.\n"
1199
+ "arg2: test size in MB, default value is all available space.\n"
1200
+ "arg3: start addr for test.\n"
1201
+ "arg4: test page size in kB, default value is 1024kB(1MB).\n"
1202
+ "example:\n"
1203
+ " stressapptest: test for 20s, test size is all available space, each page size is 1MB.\n"
1204
+ " stressapptest 43200 64: test for 12h, test size is 64MB, each page size is 1MB (64 pages).\n"
1205
+ " stressapptest 86400 1024 0x80000000: test for 24h, test size is 1024MB, start addr for test is 0x80000000, each page size is 1MB (1024 pages).\n"
1206
+ " stressapptest 43200 16 0x40000000 512: test for 12h, test size is 16MB, start addr for test is 0x40000000, each page size is 512kB (32 pages).\n"
1207
+);
u-boot/cmd/ddr_tool/stressapptest/stressapptest.h
....@@ -0,0 +1,70 @@
1
+/* Copyright 2006 Google Inc. All Rights Reserved. */
2
+/* Licensed under the Apache License, Version 2.0 (the "License");
3
+ * you may not use this file except in compliance with the License.
4
+ * You may obtain a copy of the License at
5
+ *
6
+ * http://www.apache.org/licenses/LICENSE-2.0
7
+ *
8
+ * Unless required by applicable law or agreed to in writing, software
9
+ * distributed under the License is distributed on an "AS IS" BASIS,
10
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
11
+ * See the License for the specific language governing permissions and
12
+ * limitations under the License.
13
+ */
14
+
15
+/* This is stressapptest for Rockchip platform in U-Boot, the design idea and
16
+ * the patterns are from code.google.com/p/stressapptest.
17
+ */
18
+
19
+#ifndef __CMD_DDR_TOOL_STRESSAPPTEST_STRESSAPPTEST_H
20
+#define __CMD_DDR_TOOL_STRESSAPPTEST_STRESSAPPTEST_H
21
+
22
+struct stressapptest_params {
23
+ ulong total_start_addr;
24
+ ulong total_test_size_mb;
25
+ /* total_test_size = page_size * page_num */
26
+ ulong page_size_byte;
27
+ u32 page_num;
28
+ /* page_size = block_size * block_num */
29
+ u32 block_size_byte;
30
+ u32 block_num;
31
+
32
+ u32 weight_count;
33
+
34
+ u8 cpu_num;
35
+} sat;
36
+
37
+struct pat {
38
+ const char *name;
39
+ const unsigned int *data_array;
40
+ /* mask = size - 1, So data_array[index & mask] is always valid. */
41
+ const unsigned int mask;
42
+ const unsigned int weight[4]; /* Weighted frequency of this pattern. */
43
+};
44
+
45
+struct adler_sum {
46
+ u64 a1;
47
+ u64 b1;
48
+ u64 a2;
49
+ u64 b2;
50
+};
51
+
52
+struct pattern {
53
+ struct pat *pat;
54
+ bool inv;
55
+ u32 repeat;
56
+ u32 weight;
57
+ struct adler_sum adler_sum;
58
+};
59
+
60
+struct page {
61
+ void *base_addr;
62
+ struct pattern *pattern;
63
+ bool valid; /* 1: valid, 0: empty */
64
+} *page_list;
65
+
66
+extern void secondary_init(void);
67
+extern void lock_byte_mutex(u32 *flag);
68
+extern u32 unlock_byte_mutex(u32 *flag);
69
+
70
+#endif /* __CMD_DDR_TOOL_STRESSAPPTEST_STRESSAPPTEST_H */
u-boot/cmd/memtester/Makefile
deleted file mode 100644
....@@ -1,4 +0,0 @@
1
-obj-$(CONFIG_CMD_MEMTESTER) += tests.o
2
-obj-$(CONFIG_CMD_MEMTESTER) += memtester.o
3
-obj-$(CONFIG_CMD_MEMTESTER) += io_map.o
4
-obj-$(CONFIG_CMD_MEMTESTER) += ddr_tester_common.o
u-boot/cmd/mmc.c
....@@ -129,6 +129,7 @@
129129 static int do_mmc_test_secure_storage(cmd_tbl_t *cmdtp,
130130 int flag, int argc, char * const argv[])
131131 {
132
+#ifdef CONFIG_MMC
132133 struct mmc *mmc;
133134
134135 if (curr_device < 0) {
....@@ -143,7 +144,8 @@
143144
144145 mmc = init_mmc_device(curr_device, false);
145146 if (!mmc)
146
- return CMD_RET_FAILURE;
147
+ printf("No mmc device\n");
148
+#endif
147149
148150 int i, count = 100;
149151
u-boot/cmd/mtd.c
....@@ -13,6 +13,10 @@
1313 #include <mapmem.h>
1414 #include <mtd.h>
1515
16
+#define DEV_NAME_MAX_LENGTH 0x40
17
+static char g_devname[DEV_NAME_MAX_LENGTH];
18
+static struct mtd_info *g_mtd;
19
+
1620 static uint mtd_len_to_pages(struct mtd_info *mtd, u64 len)
1721 {
1822 do_div(len, mtd->writesize);
....@@ -244,14 +248,20 @@
244248 return CMD_RET_USAGE;
245249
246250 mtd_name = argv[2];
247
- mtd_probe_devices();
248
- mtd = get_mtd_device_nm(mtd_name);
249
- if (IS_ERR_OR_NULL(mtd)) {
250
- printf("MTD device %s not found, ret %ld\n",
251
- mtd_name, PTR_ERR(mtd));
252
- return CMD_RET_FAILURE;
251
+ if (!strncmp(mtd_name, g_devname, strlen(mtd_name)) && g_mtd) {
252
+ mtd = g_mtd;
253
+ } else {
254
+ mtd_probe_devices();
255
+ mtd = get_mtd_device_nm(mtd_name);
256
+ if (IS_ERR_OR_NULL(mtd)) {
257
+ printf("MTD device %s not found, ret %ld\n",
258
+ mtd_name, PTR_ERR(mtd));
259
+ return CMD_RET_FAILURE;
260
+ }
261
+ put_mtd_device(mtd);
262
+ g_mtd = mtd;
263
+ strncpy(g_devname, mtd_name, strlen(mtd_name));
253264 }
254
- put_mtd_device(mtd);
255265
256266 argc -= 3;
257267 argv += 3;
u-boot/cmd/pci.c
....@@ -47,7 +47,6 @@
4747 return pci_byte_size(size) * 2;
4848 }
4949
50
-#ifdef CONFIG_DM_PCI
5150 static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
5251 {
5352 for (; regs->name; regs++) {
....@@ -59,41 +58,8 @@
5958 pci_field_width(regs->size), val);
6059 }
6160 }
62
-#else
63
-static unsigned long pci_read_config(pci_dev_t dev, int offset,
64
- enum pci_size_t size)
65
-{
66
- u32 val32;
67
- u16 val16;
68
- u8 val8;
6961
70
- switch (size) {
71
- case PCI_SIZE_8:
72
- pci_read_config_byte(dev, offset, &val8);
73
- return val8;
74
- case PCI_SIZE_16:
75
- pci_read_config_word(dev, offset, &val16);
76
- return val16;
77
- case PCI_SIZE_32:
78
- default:
79
- pci_read_config_dword(dev, offset, &val32);
80
- return val32;
81
- }
82
-}
83
-
84
-static void pci_show_regs(pci_dev_t dev, struct pci_reg_info *regs)
85
-{
86
- for (; regs->name; regs++) {
87
- printf(" %s =%*s%#.*lx\n", regs->name,
88
- (int)(28 - strlen(regs->name)), "",
89
- pci_field_width(regs->size),
90
- pci_read_config(dev, regs->offset, regs->size));
91
- }
92
-}
93
-#endif
94
-
95
-#ifdef CONFIG_DM_PCI
96
-int pci_bar_show(struct udevice *dev)
62
+static int pci_bar_show(struct udevice *dev)
9763 {
9864 u8 header_type;
9965 int bar_cnt, bar_id, mem_type;
....@@ -105,9 +71,14 @@
10571 int prefetchable;
10672
10773 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
74
+ header_type &= 0x7f;
10875
10976 if (header_type == PCI_HEADER_TYPE_CARDBUS) {
11077 printf("CardBus doesn't support BARs\n");
78
+ return -ENOSYS;
79
+ } else if (header_type != PCI_HEADER_TYPE_NORMAL &&
80
+ header_type != PCI_HEADER_TYPE_BRIDGE) {
81
+ printf("unknown header type\n");
11182 return -ENOSYS;
11283 }
11384
....@@ -149,7 +120,7 @@
149120
150121 if ((!is_64 && size_low) || (is_64 && size)) {
151122 size = ~size + 1;
152
- printf(" %d %#016llx %#016llx %d %s %s\n",
123
+ printf(" %d %#018llx %#018llx %d %s %s\n",
153124 bar_id, (unsigned long long)base,
154125 (unsigned long long)size, is_64 ? 64 : 32,
155126 is_io ? "I/O" : "MEM",
....@@ -162,7 +133,6 @@
162133
163134 return 0;
164135 }
165
-#endif
166136
167137 static struct pci_reg_info regs_start[] = {
168138 { "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
....@@ -258,29 +228,18 @@
258228 *
259229 * @dev: Bus+Device+Function number
260230 */
261
-#ifdef CONFIG_DM_PCI
262
-void pci_header_show(struct udevice *dev)
263
-#else
264
-void pci_header_show(pci_dev_t dev)
265
-#endif
231
+static void pci_header_show(struct udevice *dev)
266232 {
267
-#ifdef CONFIG_DM_PCI
268233 unsigned long class, header_type;
269234
270235 dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
271236 dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
272
-#else
273
- u8 class, header_type;
274
-
275
- pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
276
- pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
277
-#endif
278237 pci_show_regs(dev, regs_start);
279238 printf(" class code = 0x%.2x (%s)\n", (int)class,
280239 pci_class_str(class));
281240 pci_show_regs(dev, regs_rest);
282241
283
- switch (header_type & 0x03) {
242
+ switch (header_type & 0x7f) {
284243 case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
285244 pci_show_regs(dev, regs_normal);
286245 break;
....@@ -297,17 +256,14 @@
297256 }
298257 }
299258
300
-void pciinfo_header(int busnum, bool short_listing)
259
+static void pciinfo_header(bool short_listing)
301260 {
302
- printf("Scanning PCI devices on bus %d\n", busnum);
303
-
304261 if (short_listing) {
305262 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
306263 printf("_____________________________________________________________\n");
307264 }
308265 }
309266
310
-#ifdef CONFIG_DM_PCI
311267 /**
312268 * pci_header_show_brief() - Show the short-form PCI device header
313269 *
....@@ -330,11 +286,15 @@
330286 pci_class_str(class), subclass);
331287 }
332288
333
-static void pciinfo(struct udevice *bus, bool short_listing)
289
+static void pciinfo(struct udevice *bus, bool short_listing, bool multi)
334290 {
335291 struct udevice *dev;
336292
337
- pciinfo_header(bus->seq, short_listing);
293
+ if (!multi)
294
+ printf("Scanning PCI devices on bus %d\n", bus->seq);
295
+
296
+ if (!multi || bus->seq == 0)
297
+ pciinfo_header(short_listing);
338298
339299 for (device_find_first_child(bus, &dev);
340300 dev;
....@@ -353,102 +313,6 @@
353313 }
354314 }
355315 }
356
-
357
-#else
358
-
359
-/**
360
- * pci_header_show_brief() - Show the short-form PCI device header
361
- *
362
- * Reads and prints the header of the specified PCI device in short form.
363
- *
364
- * @dev: Bus+Device+Function number
365
- */
366
-void pci_header_show_brief(pci_dev_t dev)
367
-{
368
- u16 vendor, device;
369
- u8 class, subclass;
370
-
371
- pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
372
- pci_read_config_word(dev, PCI_DEVICE_ID, &device);
373
- pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
374
- pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
375
-
376
- printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
377
- vendor, device,
378
- pci_class_str(class), subclass);
379
-}
380
-
381
-/**
382
- * pciinfo() - Show a list of devices on the PCI bus
383
- *
384
- * Show information about devices on PCI bus. Depending on @short_pci_listing
385
- * the output will be more or less exhaustive.
386
- *
387
- * @bus_num: The number of the bus to be scanned
388
- * @short_pci_listing: true to use short form, showing only a brief header
389
- * for each device
390
- */
391
-void pciinfo(int bus_num, int short_pci_listing)
392
-{
393
- struct pci_controller *hose = pci_bus_to_hose(bus_num);
394
- int device;
395
- int function;
396
- unsigned char header_type;
397
- unsigned short vendor_id;
398
- pci_dev_t dev;
399
- int ret;
400
-
401
- if (!hose)
402
- return;
403
-
404
- pciinfo_header(bus_num, short_pci_listing);
405
-
406
- for (device = 0; device < PCI_MAX_PCI_DEVICES; device++) {
407
- header_type = 0;
408
- vendor_id = 0;
409
- for (function = 0; function < PCI_MAX_PCI_FUNCTIONS;
410
- function++) {
411
- /*
412
- * If this is not a multi-function device, we skip
413
- * the rest.
414
- */
415
- if (function && !(header_type & 0x80))
416
- break;
417
-
418
- dev = PCI_BDF(bus_num, device, function);
419
-
420
- if (pci_skip_dev(hose, dev))
421
- continue;
422
-
423
- ret = pci_read_config_word(dev, PCI_VENDOR_ID,
424
- &vendor_id);
425
- if (ret)
426
- goto error;
427
- if ((vendor_id == 0xFFFF) || (vendor_id == 0x0000))
428
- continue;
429
-
430
- if (!function) {
431
- pci_read_config_byte(dev, PCI_HEADER_TYPE,
432
- &header_type);
433
- }
434
-
435
- if (short_pci_listing) {
436
- printf("%02x.%02x.%02x ", bus_num, device,
437
- function);
438
- pci_header_show_brief(dev);
439
- } else {
440
- printf("\nFound PCI device %02x.%02x.%02x:\n",
441
- bus_num, device, function);
442
- pci_header_show(dev);
443
- }
444
- }
445
- }
446
-
447
- return;
448
-error:
449
- printf("Cannot read bus configuration: %d\n", ret);
450
-}
451
-#endif
452316
453317 /**
454318 * get_pci_dev() - Convert the "bus.device.function" identifier into a number
....@@ -481,13 +345,8 @@
481345 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
482346 }
483347
484
-#ifdef CONFIG_DM_PCI
485348 static int pci_cfg_display(struct udevice *dev, ulong addr,
486349 enum pci_size_t size, ulong length)
487
-#else
488
-static int pci_cfg_display(pci_dev_t bdf, ulong addr, enum pci_size_t size,
489
- ulong length)
490
-#endif
491350 {
492351 #define DISP_LINE_LEN 16
493352 ulong i, nbytes, linebytes;
....@@ -508,11 +367,7 @@
508367 for (i = 0; i < linebytes; i += byte_size) {
509368 unsigned long val;
510369
511
-#ifdef CONFIG_DM_PCI
512370 dm_pci_read_config(dev, addr, &val, size);
513
-#else
514
- val = pci_read_config(bdf, addr, size);
515
-#endif
516371 printf(" %0*lx", pci_field_width(size), val);
517372 addr += byte_size;
518373 }
....@@ -527,31 +382,8 @@
527382 return (rc);
528383 }
529384
530
-#ifndef CONFIG_DM_PCI
531
-static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
532
-{
533
- if (size == 4) {
534
- pci_write_config_dword(bdf, addr, value);
535
- }
536
- else if (size == 2) {
537
- ushort val = value & 0xffff;
538
- pci_write_config_word(bdf, addr, val);
539
- }
540
- else {
541
- u_char val = value & 0xff;
542
- pci_write_config_byte(bdf, addr, val);
543
- }
544
- return 0;
545
-}
546
-#endif
547
-
548
-#ifdef CONFIG_DM_PCI
549385 static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
550386 ulong value, int incrflag)
551
-#else
552
-static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong size, ulong value,
553
- int incrflag)
554
-#endif
555387 {
556388 ulong i;
557389 int nbytes;
....@@ -562,11 +394,7 @@
562394 */
563395 do {
564396 printf("%08lx:", addr);
565
-#ifdef CONFIG_DM_PCI
566397 dm_pci_read_config(dev, addr, &val, size);
567
-#else
568
- val = pci_read_config(bdf, addr, size);
569
-#endif
570398 printf(" %0*lx", pci_field_width(size), val);
571399
572400 nbytes = cli_readline(" ? ");
....@@ -593,11 +421,7 @@
593421 /* good enough to not time out
594422 */
595423 bootretry_reset_cmd_timeout();
596
-#ifdef CONFIG_DM_PCI
597424 dm_pci_write_config(dev, addr, i, size);
598
-#else
599
- pci_cfg_write(bdf, addr, size, i);
600
-#endif
601425 if (incrflag)
602426 addr += size;
603427 }
....@@ -607,7 +431,6 @@
607431 return 0;
608432 }
609433
610
-#ifdef CONFIG_DM_PCI
611434 static const struct pci_flag_info {
612435 uint flag;
613436 const char *name;
....@@ -621,7 +444,7 @@
621444
622445 static void pci_show_regions(struct udevice *bus)
623446 {
624
- struct pci_controller *hose = dev_get_uclass_priv(bus);
447
+ struct pci_controller *hose = dev_get_uclass_priv(pci_get_controller(bus));
625448 const struct pci_region *reg;
626449 int i, j;
627450
....@@ -630,10 +453,11 @@
630453 return;
631454 }
632455
633
- printf("# %-16s %-16s %-16s %s\n", "Bus start", "Phys start", "Size",
456
+ printf("Buses %02x-%02x\n", hose->first_busno, hose->last_busno);
457
+ printf("# %-18s %-18s %-18s %s\n", "Bus start", "Phys start", "Size",
634458 "Flags");
635459 for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
636
- printf("%d %#016llx %#016llx %#016llx ", i,
460
+ printf("%d %#018llx %#018llx %#018llx ", i,
637461 (unsigned long long)reg->bus_start,
638462 (unsigned long long)reg->phys_start,
639463 (unsigned long long)reg->size);
....@@ -646,7 +470,6 @@
646470 printf("\n");
647471 }
648472 }
649
-#endif
650473
651474 /* PCI Configuration Space access commands
652475 *
....@@ -660,15 +483,12 @@
660483 {
661484 ulong addr = 0, value = 0, cmd_size = 0;
662485 enum pci_size_t size = PCI_SIZE_32;
663
-#ifdef CONFIG_DM_PCI
664486 struct udevice *dev, *bus;
665
-#else
666
- pci_dev_t dev;
667
-#endif
668
- int busnum = 0;
487
+ int busnum = -1;
669488 pci_dev_t bdf = 0;
670489 char cmd = 's';
671490 int ret = 0;
491
+ char *endp;
672492
673493 if (argc > 1)
674494 cmd = argv[1][0];
....@@ -686,19 +506,15 @@
686506 if (argc > 4)
687507 value = simple_strtoul(argv[4], NULL, 16);
688508 case 'h': /* header */
689
-#ifdef CONFIG_DM_PCI
690509 case 'b': /* bars */
691
-#endif
692510 if (argc < 3)
693511 goto usage;
694512 if ((bdf = get_pci_dev(argv[2])) == -1)
695513 return 1;
696514 break;
697
-#if defined(CONFIG_DM_PCI)
698515 case 'e':
699516 pci_init();
700517 return 0;
701
-#endif
702518 case 'r': /* no break */
703519 default: /* scan bus */
704520 value = 1; /* short listing */
....@@ -707,10 +523,37 @@
707523 value = 0;
708524 argc--;
709525 }
710
- if (argc > 1)
711
- busnum = simple_strtoul(argv[1], NULL, 16);
526
+ if (argc > 2 || (argc > 1 && cmd != 'r' && argv[1][0] != 's')) {
527
+ if (argv[argc - 1][0] != '*') {
528
+ busnum = simple_strtoul(argv[argc - 1], &endp, 16);
529
+ if (*endp)
530
+ goto usage;
531
+ }
532
+ argc--;
533
+ }
534
+ if (cmd == 'r' && argc > 2)
535
+ goto usage;
536
+ else if (cmd != 'r' && (argc > 2 || (argc == 2 && argv[1][0] != 's')))
537
+ goto usage;
712538 }
713
-#ifdef CONFIG_DM_PCI
539
+ if (busnum == -1) {
540
+ if (cmd != 'r') {
541
+ for (busnum = 0;
542
+ uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus) == 0;
543
+ busnum++)
544
+ pciinfo(bus, value, true);
545
+ } else {
546
+ for (busnum = 0;
547
+ uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus) == 0;
548
+ busnum++) {
549
+ /* Regions are controller specific so skip non-root buses */
550
+ if (device_is_on_pci_bus(bus))
551
+ continue;
552
+ pci_show_regions(bus);
553
+ }
554
+ }
555
+ return 0;
556
+ }
714557 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
715558 if (ret) {
716559 printf("No such bus\n");
....@@ -719,22 +562,15 @@
719562 if (cmd == 'r')
720563 pci_show_regions(bus);
721564 else
722
- pciinfo(bus, value);
723
-#else
724
- pciinfo(busnum, value);
725
-#endif
565
+ pciinfo(bus, value, false);
726566 return 0;
727567 }
728568
729
-#ifdef CONFIG_DM_PCI
730569 ret = dm_pci_bus_find_bdf(bdf, &dev);
731570 if (ret) {
732571 printf("No such device\n");
733572 return CMD_RET_FAILURE;
734573 }
735
-#else
736
- dev = bdf;
737
-#endif
738574
739575 switch (argv[1][0]) {
740576 case 'h': /* header */
....@@ -755,17 +591,10 @@
755591 case 'w': /* write */
756592 if (argc < 5)
757593 goto usage;
758
-#ifdef CONFIG_DM_PCI
759594 ret = dm_pci_write_config(dev, addr, value, size);
760
-#else
761
- ret = pci_cfg_write(dev, addr, size, value);
762
-#endif
763595 break;
764
-#ifdef CONFIG_DM_PCI
765
-
766596 case 'b': /* bars */
767597 return pci_bar_show(dev);
768
-#endif
769598 default:
770599 ret = CMD_RET_USAGE;
771600 break;
....@@ -780,20 +609,16 @@
780609
781610 #ifdef CONFIG_SYS_LONGHELP
782611 static char pci_help_text[] =
783
- "[bus] [long]\n"
612
+ "[bus|*] [long]\n"
784613 " - short or long list of PCI devices on bus 'bus'\n"
785
-#if defined(CONFIG_DM_PCI)
786614 "pci enum\n"
787615 " - Enumerate PCI buses\n"
788
-#endif
789616 "pci header b.d.f\n"
790617 " - show header of PCI device 'bus.device.function'\n"
791
-#ifdef CONFIG_DM_PCI
792618 "pci bar b.d.f\n"
793619 " - show BARs base and size for device b.d.f'\n"
794
- "pci regions\n"
620
+ "pci regions [bus|*]\n"
795621 " - show PCI regions\n"
796
-#endif
797622 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
798623 " - display PCI configuration space (CFG)\n"
799624 "pci next[.b, .w, .l] b.d.f address\n"
u-boot/cmd/script_update.c
....@@ -6,6 +6,7 @@
66
77 #include <common.h>
88 #include <malloc.h>
9
+#include <dm/device.h>
910
1011 /*
1112 * Script file example:
....@@ -144,6 +145,8 @@
144145 int argc, char * const argv[])
145146 {
146147 struct blk_desc *desc;
148
+ struct udevice *dev;
149
+ int devnum = -1;
147150 int part_type;
148151 char cmd[128];
149152 char *buf;
....@@ -151,9 +154,31 @@
151154
152155 printf("## retrieving usb_update.txt ...\n");
153156
154
- desc = blk_get_devnum_by_type(IF_TYPE_USB, 0);
155
- if (!desc)
157
+ if (run_command("usb reset", 0))
156158 return CMD_RET_FAILURE;
159
+
160
+ for (blk_first_device(IF_TYPE_USB, &dev);
161
+ dev;
162
+ blk_next_device(&dev)) {
163
+ desc = dev_get_uclass_platdata(dev);
164
+ if (desc->type == DEV_TYPE_UNKNOWN)
165
+ continue;
166
+
167
+ if (desc->lba > 0L && desc->blksz > 0L) {
168
+ devnum = desc->devnum;
169
+ break;
170
+ }
171
+ }
172
+ if (devnum < 0) {
173
+ printf("No available udisk\n");
174
+ return CMD_RET_FAILURE;
175
+ }
176
+
177
+ desc = blk_get_devnum_by_type(IF_TYPE_USB, devnum);
178
+ if (!desc) {
179
+ printf("No usb %d found\n", devnum);
180
+ return CMD_RET_FAILURE;
181
+ }
157182
158183 buf = memalign(ARCH_DMA_MINALIGN, SCRIPT_FILE_MAX_SIZE * 2);
159184 if (!buf)
....@@ -162,18 +187,15 @@
162187 part_type = desc->part_type;
163188 desc->part_type = PART_TYPE_DOS;
164189
165
- snprintf(cmd, sizeof(cmd), "usb reset");
190
+ printf("## scanning usb %d\n", devnum);
191
+ snprintf(cmd, sizeof(cmd), "fatload usb %d 0x%08lx usb_update.txt",
192
+ devnum, (ulong)buf);
166193 ret = run_command(cmd, 0);
167
- if (!ret) {
168
- snprintf(cmd, sizeof(cmd), "fatload usb 0 0x%08lx usb_update.txt", (ulong)buf);
169
- ret = run_command(cmd, 0);
170
- }
171194 if (!ret) {
172195 snprintf(cmd, sizeof(cmd), "script 0x%08lx", (ulong)buf);
173196 ret = run_command(cmd, 0);
174197 }
175198 free(buf);
176
-
177199 desc->part_type = part_type;
178200
179201 return ret;
u-boot/cmd/ufs.c
....@@ -0,0 +1,37 @@
1
+// SPDX-License-Identifier: GPL-2.0+
2
+/**
3
+ * ufs.c - UFS specific U-boot commands
4
+ *
5
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
6
+ *
7
+ */
8
+#include <common.h>
9
+#include <command.h>
10
+#include <ufs.h>
11
+
12
+static int do_ufs(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
13
+{
14
+ int dev, ret;
15
+
16
+ if (argc >= 2) {
17
+ if (!strcmp(argv[1], "init")) {
18
+ if (argc == 3) {
19
+ dev = simple_strtoul(argv[2], NULL, 10);
20
+ ret = ufs_probe_dev(dev);
21
+ if (ret)
22
+ return CMD_RET_FAILURE;
23
+ } else {
24
+ ufs_probe();
25
+ }
26
+
27
+ return CMD_RET_SUCCESS;
28
+ }
29
+ }
30
+
31
+ return CMD_RET_USAGE;
32
+}
33
+
34
+U_BOOT_CMD(ufs, 3, 1, do_ufs,
35
+ "UFS sub system",
36
+ "init [dev] - init UFS subsystem\n"
37
+);
u-boot/common/Kconfig
....@@ -682,5 +682,17 @@
682682
683683 endmenu
684684
685
+menu "MT support"
686
+
687
+config MP_BOOT
688
+ bool "Support MT boot"
689
+ default n
690
+
691
+config MP_BOOT_BOOTM
692
+ bool "MT simple bootm image"
693
+ depends on MP_BOOT
694
+
695
+endmenu
696
+
685697 source "common/spl/Kconfig"
686698 source "common/usbplug/Kconfig"
u-boot/common/Makefile
....@@ -49,7 +49,6 @@
4949 obj-$(CONFIG_CONSOLE_MUX) += iomux.o
5050 obj-$(CONFIG_MTD_NOR_FLASH) += flash.o
5151 obj-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o
52
-obj-$(CONFIG_I2C_EDID) += edid.o
5352 obj-$(CONFIG_KALLSYMS) += kallsyms.o
5453 obj-y += splash.o
5554 obj-$(CONFIG_SPLASH_SOURCE) += splash_source.o
....@@ -67,6 +66,7 @@
6766
6867 endif # !CONFIG_SPL_BUILD
6968
69
+obj-$(CONFIG_$(SPL_TPL_)I2C_EDID) += edid.o
7070 obj-$(CONFIG_$(SPL_TPL_)BOOTSTAGE) += bootstage.o
7171
7272 ifdef CONFIG_SPL_BUILD
....@@ -166,3 +166,11 @@
166166 obj-$(CONFIG_ANDROID_KEYMASTER_CA) += keymaster.o
167167 obj-$(CONFIG_ANDROID_KEYMASTER_CA) += attestation_key.o
168168 endif
169
+
170
+ifdef CONFIG_MP_BOOT
171
+ifndef CONFIG_SPL_BUILD
172
+obj-$(CONFIG_ROCKCHIP_RK3528) += mp_boot_rk3528.o
173
+else
174
+obj-$(CONFIG_ROCKCHIP_RK3528) += spl_mp_boot_rk3528.o
175
+endif
176
+endif
u-boot/common/android_ab.c
....@@ -406,7 +406,7 @@
406406 return 0;
407407 }
408408
409
-void ab_update_root_uuid(void)
409
+static void ab_update_root_uuid(void)
410410 {
411411 /*
412412 * In android a/b & avb process, the system.img is mandory and the
....@@ -441,6 +441,60 @@
441441 }
442442 }
443443
444
+void ab_update_root_partition(void)
445
+{
446
+ char *boot_args = env_get("bootargs");
447
+ char root_part_dev[64] = {0};
448
+ disk_partition_t part_info;
449
+ struct blk_desc *dev_desc;
450
+ const char *part_type;
451
+ int part_num;
452
+
453
+ dev_desc = rockchip_get_bootdev();
454
+ if (!dev_desc)
455
+ return;
456
+
457
+ if (ab_is_support_dynamic_partition(dev_desc))
458
+ return;
459
+
460
+ /* Get 'system' partition device number. */
461
+ part_num = part_get_info_by_name(dev_desc, ANDROID_PARTITION_SYSTEM, &part_info);
462
+ if (part_num < 0) {
463
+ printf("%s: Failed to get partition '%s'.\n", __func__, ANDROID_PARTITION_SYSTEM);
464
+ return;
465
+ }
466
+
467
+ /* Get partition type. */
468
+ part_type = part_get_type(dev_desc);
469
+ if (!part_type)
470
+ return;
471
+
472
+ /* Judge the partition device type. */
473
+ switch (dev_desc->if_type) {
474
+ case IF_TYPE_MMC:
475
+ if (strstr(part_type, "ENV"))
476
+ snprintf(root_part_dev, 64, "root=/dev/mmcblk0p%d", part_num);
477
+ else if (strstr(part_type, "EFI"))
478
+ ab_update_root_uuid();
479
+ break;
480
+ case IF_TYPE_MTD:
481
+ if (dev_desc->devnum == BLK_MTD_NAND || dev_desc->devnum == BLK_MTD_SPI_NAND) {
482
+ if (strstr(boot_args, "rootfstype=squashfs") || strstr(boot_args, "rootfstype=erofs"))
483
+ snprintf(root_part_dev, 64, "ubi.mtd=%d root=/dev/ubiblock0_0", part_num - 1);
484
+ else if (strstr(boot_args, "rootfstype=ubifs"))
485
+ snprintf(root_part_dev, 64, "ubi.mtd=%d root=ubi0:system", part_num - 1);
486
+ } else if (dev_desc->devnum == BLK_MTD_SPI_NOR) {
487
+ snprintf(root_part_dev, 64, "root=/dev/mtdblock%d", part_num - 1);
488
+ }
489
+ break;
490
+ default:
491
+ printf("%s: Not found part type, failed to set root part device.\n", __func__);
492
+ return;
493
+ }
494
+
495
+ env_update("bootargs", root_part_dev);
496
+}
497
+
444498 int ab_get_slot_suffix(char *slot_suffix)
445499 {
446500 /* TODO: get from pre-loader or misc partition */
u-boot/common/android_bootloader.c
....@@ -18,6 +18,7 @@
1818 #include <dt_table.h>
1919 #include <image-android-dt.h>
2020 #include <malloc.h>
21
+#include <mp_boot.h>
2122 #include <fdt_support.h>
2223 #include <fs.h>
2324 #include <boot_rkimg.h>
....@@ -462,15 +463,305 @@
462463 slot->successful_boot = 0;
463464 }
464465
466
+static char *join_str(const char *a, const char *b)
467
+{
468
+ size_t len = strlen(a) + strlen(b) + 1 /* null term */;
469
+ char *ret = (char *)malloc(len);
470
+
471
+ if (!ret) {
472
+ debug("failed to alloc %zu\n", len);
473
+ return NULL;
474
+ }
475
+ strcpy(ret, a);
476
+ strcat(ret, b);
477
+
478
+ return ret;
479
+}
480
+
481
+static size_t get_partition_size(AvbOps *ops, char *name,
482
+ const char *slot_suffix)
483
+{
484
+ char *partition_name = join_str(name, slot_suffix);
485
+ uint64_t size = 0;
486
+ AvbIOResult res;
487
+
488
+ if (partition_name == NULL)
489
+ goto bail;
490
+
491
+ res = ops->get_size_of_partition(ops, partition_name, &size);
492
+ if (res != AVB_IO_RESULT_OK && res != AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION)
493
+ size = 0;
494
+bail:
495
+ if (partition_name)
496
+ free(partition_name);
497
+
498
+ return size;
499
+}
500
+
501
+static struct AvbOpsData preload_user_data;
502
+
503
+static int avb_image_distribute_prepare(AvbSlotVerifyData *slot_data,
504
+ AvbOps *ops, char *slot_suffix)
505
+{
506
+ struct AvbOpsData *data = (struct AvbOpsData *)(ops->user_data);
507
+ size_t vendor_boot_size;
508
+ size_t init_boot_size;
509
+ size_t resource_size;
510
+ size_t boot_size;
511
+ void *image_buf;
512
+
513
+ boot_size = max(get_partition_size(ops, ANDROID_PARTITION_BOOT, slot_suffix),
514
+ get_partition_size(ops, ANDROID_PARTITION_RECOVERY, slot_suffix));
515
+ init_boot_size = get_partition_size(ops,
516
+ ANDROID_PARTITION_INIT_BOOT, slot_suffix);
517
+ vendor_boot_size = get_partition_size(ops,
518
+ ANDROID_PARTITION_VENDOR_BOOT, slot_suffix);
519
+ resource_size = get_partition_size(ops,
520
+ ANDROID_PARTITION_RESOURCE, slot_suffix);
521
+ image_buf = sysmem_alloc(MEM_AVB_ANDROID,
522
+ boot_size + init_boot_size +
523
+ vendor_boot_size + resource_size);
524
+ if (!image_buf) {
525
+ printf("avb: sysmem alloc failed\n");
526
+ return -ENOMEM;
527
+ }
528
+
529
+ /* layout: | boot/recovery | vendor_boot | init_boot | resource | */
530
+ data->slot_suffix = slot_suffix;
531
+ data->boot.addr = image_buf;
532
+ data->boot.size = 0;
533
+ data->vendor_boot.addr = data->boot.addr + boot_size;
534
+ data->vendor_boot.size = 0;
535
+ data->init_boot.addr = data->vendor_boot.addr + vendor_boot_size;
536
+ data->init_boot.size = 0;
537
+ data->resource.addr = data->init_boot.addr + init_boot_size;
538
+ data->resource.size = 0;
539
+
540
+ return 0;
541
+}
542
+
543
+static int avb_image_distribute_finish(AvbSlotVerifyData *slot_data,
544
+ AvbSlotVerifyFlags flags,
545
+ ulong *load_address)
546
+{
547
+ struct andr_img_hdr *hdr;
548
+ ulong load_addr = *load_address;
549
+ void *vendor_boot_hdr = NULL;
550
+ void *init_boot_hdr = NULL;
551
+ void *boot_hdr = NULL;
552
+ char *part_name;
553
+ int i, ret;
554
+
555
+ for (i = 0; i < slot_data->num_loaded_partitions; i++) {
556
+ part_name = slot_data->loaded_partitions[i].partition_name;
557
+ if (!strncmp(ANDROID_PARTITION_BOOT, part_name, 4) ||
558
+ !strncmp(ANDROID_PARTITION_RECOVERY, part_name, 8)) {
559
+ boot_hdr = slot_data->loaded_partitions[i].data;
560
+ } else if (!strncmp(ANDROID_PARTITION_INIT_BOOT, part_name, 9)) {
561
+ init_boot_hdr = slot_data->loaded_partitions[i].data;
562
+ } else if (!strncmp(ANDROID_PARTITION_VENDOR_BOOT, part_name, 11)) {
563
+ vendor_boot_hdr = slot_data->loaded_partitions[i].data;
564
+ }
565
+ }
566
+
567
+ /*
568
+ * populate boot_img_hdr_v34
569
+ *
570
+ * If allow verification error: the images are loaded by
571
+ * ops->get_preloaded_partition() which auto populates
572
+ * boot_img_hdr_v34.
573
+ *
574
+ * If not allow verification error: the images are full loaded
575
+ * by ops->read_from_partition() which doesn't populate
576
+ * boot_img_hdr_v34, we need to fix it here for bootm and
577
+ */
578
+
579
+ hdr = boot_hdr;
580
+ if (hdr->header_version >= 3 &&
581
+ !(flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR)) {
582
+ hdr = malloc(sizeof(struct andr_img_hdr));
583
+ if (!hdr)
584
+ return -ENOMEM;
585
+
586
+ ret = populate_boot_info(boot_hdr, vendor_boot_hdr,
587
+ init_boot_hdr, hdr, true);
588
+ if (ret < 0) {
589
+ printf("avb: populate boot info failed, ret=%d\n", ret);
590
+ return ret;
591
+ }
592
+ memcpy(boot_hdr, hdr, sizeof(*hdr));
593
+ }
594
+
595
+ /* distribute ! */
596
+ load_addr -= hdr->page_size;
597
+ if (android_image_memcpy_separate(boot_hdr, &load_addr)) {
598
+ printf("Failed to separate copy android image\n");
599
+ return AVB_SLOT_VERIFY_RESULT_ERROR_IO;
600
+ }
601
+
602
+ *load_address = load_addr;
603
+
604
+ return 0;
605
+}
606
+
607
+int android_image_verify_resource(const char *boot_part, ulong *resc_buf)
608
+{
609
+ const char *requested_partitions[] = {
610
+ NULL,
611
+ NULL,
612
+ };
613
+ struct AvbOpsData *data;
614
+ uint8_t unlocked = true;
615
+ AvbOps *ops;
616
+ AvbSlotVerifyFlags flags;
617
+ AvbSlotVerifyData *slot_data = {NULL};
618
+ AvbSlotVerifyResult verify_result;
619
+ char slot_suffix[3] = {0};
620
+ char *part_name;
621
+ void *image_buf = NULL;
622
+ int retry_no_vbmeta_partition = 1;
623
+ int i, ret;
624
+
625
+ ops = avb_ops_user_new();
626
+ if (ops == NULL) {
627
+ printf("avb_ops_user_new() failed!\n");
628
+ return -AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
629
+ }
630
+
631
+ if (ops->read_is_device_unlocked(ops, (bool *)&unlocked) != AVB_IO_RESULT_OK)
632
+ printf("Error determining whether device is unlocked.\n");
633
+
634
+ printf("Device is: %s\n", (unlocked & LOCK_MASK)? "UNLOCKED" : "LOCKED");
635
+
636
+ if (unlocked & LOCK_MASK) {
637
+ *resc_buf = 0;
638
+ return 0;
639
+ }
640
+
641
+ flags = AVB_SLOT_VERIFY_FLAGS_NONE;
642
+ if (strcmp(boot_part, ANDROID_PARTITION_RECOVERY) == 0)
643
+ flags |= AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION;
644
+
645
+#ifdef CONFIG_ANDROID_AB
646
+ part_name = strdup(boot_part);
647
+ *(part_name + strlen(boot_part) - 2) = '\0';
648
+ requested_partitions[0] = part_name;
649
+
650
+ ret = rk_avb_get_current_slot(slot_suffix);
651
+ if (ret) {
652
+ printf("Failed to get slot suffix, ret=%d\n", ret);
653
+ return ret;
654
+ }
655
+#else
656
+ requested_partitions[0] = boot_part;
657
+#endif
658
+ data = (struct AvbOpsData *)(ops->user_data);
659
+ ret = avb_image_distribute_prepare(slot_data, ops, slot_suffix);
660
+ if (ret) {
661
+ printf("avb image distribute prepare failed %d\n", ret);
662
+ return ret;
663
+ }
664
+
665
+retry_verify:
666
+ verify_result =
667
+ avb_slot_verify(ops,
668
+ requested_partitions,
669
+ slot_suffix,
670
+ flags,
671
+ AVB_HASHTREE_ERROR_MODE_RESTART,
672
+ &slot_data);
673
+ if (verify_result != AVB_SLOT_VERIFY_RESULT_OK &&
674
+ verify_result != AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED) {
675
+ if (retry_no_vbmeta_partition && strcmp(boot_part, ANDROID_PARTITION_RECOVERY) == 0) {
676
+ printf("Verify recovery with vbmeta.\n");
677
+ flags &= ~AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION;
678
+ retry_no_vbmeta_partition = 0;
679
+ goto retry_verify;
680
+ }
681
+ }
682
+
683
+ if (verify_result != AVB_SLOT_VERIFY_RESULT_OK || !slot_data) {
684
+ sysmem_free((ulong)data->boot.addr);
685
+ return verify_result;
686
+ }
687
+
688
+ for (i = 0; i < slot_data->num_loaded_partitions; i++) {
689
+ part_name = slot_data->loaded_partitions[i].partition_name;
690
+ if (!strncmp(ANDROID_PARTITION_RESOURCE, part_name, 8)) {
691
+ image_buf = slot_data->loaded_partitions[i].data;
692
+ break;
693
+ } else if (!strncmp(ANDROID_PARTITION_BOOT, part_name, 4) ||
694
+ !strncmp(ANDROID_PARTITION_RECOVERY, part_name, 8)) {
695
+ struct andr_img_hdr *hdr;
696
+
697
+ hdr = (void *)slot_data->loaded_partitions[i].data;
698
+ if (android_image_check_header(hdr))
699
+ continue;
700
+
701
+ if (hdr->header_version <= 2) {
702
+ image_buf = (void *)hdr + hdr->page_size +
703
+ ALIGN(hdr->kernel_size, hdr->page_size) +
704
+ ALIGN(hdr->ramdisk_size, hdr->page_size);
705
+ break;
706
+ }
707
+ }
708
+ }
709
+
710
+ if (image_buf) {
711
+ memcpy((char *)&preload_user_data, (char *)data, sizeof(*data));
712
+ *resc_buf = (ulong)image_buf;
713
+ }
714
+
715
+ return 0;
716
+}
717
+
718
+/*
719
+ * AVB Policy.
720
+ *
721
+ * == avb with unlock:
722
+ * Don't process hash verify.
723
+ * Go pre-loaded path: Loading vendor_boot and init_boot
724
+ * directly to where they should be, while loading the
725
+ * boot/recovery. The boot message tells like:
726
+ * ···
727
+ * preloaded: distribute image from 'boot_a'
728
+ * preloaded: distribute image from 'init_boot_a'
729
+ * preloaded: distribute image from 'vendor_boot_a'
730
+ * ···
731
+ *
732
+ * == avb with lock:
733
+ * Process hash verify.
734
+ * Go pre-loaded path: Loading full vendor_boot, init_boot and
735
+ * boot/recovery one by one to verify, and distributing them to
736
+ * where they should be by memcpy at last.
737
+ *
738
+ * The three images share a large memory buffer that allocated
739
+ * by sysmem_alloc(), it locate at high memory address that
740
+ * just lower than SP bottom. The boot message tells like:
741
+ * ···
742
+ * preloaded: full image from 'boot_a' at 0xe47f90c0 - 0xe7a4b0c0
743
+ * preloaded: full image from 'init_boot_a' at 0xeaff90c0 - 0xeb2950c0
744
+ * preloaded: full image from 'vendor_boot_a' at 0xe87f90c0 - 0xe9f6e0c0
745
+ * ···
746
+ */
465747 static AvbSlotVerifyResult android_slot_verify(char *boot_partname,
466748 unsigned long *android_load_address,
467749 char *slot_suffix)
468750 {
469
- const char *requested_partitions[1] = {NULL};
751
+ const char *requested_partitions[] = {
752
+ boot_partname,
753
+ NULL,
754
+ NULL,
755
+ NULL,
756
+ };
757
+ struct AvbOpsData *data;
758
+ struct blk_desc *dev_desc;
759
+ struct andr_img_hdr *hdr;
760
+ disk_partition_t part_info;
470761 uint8_t unlocked = true;
471762 AvbOps *ops;
472763 AvbSlotVerifyFlags flags;
473
- AvbSlotVerifyData *slot_data[1] = {NULL};
764
+ AvbSlotVerifyData *slot_data = {NULL};
474765 AvbSlotVerifyResult verify_result;
475766 AvbABData ab_data, ab_data_orig;
476767 size_t slot_index_to_boot = 0;
....@@ -478,9 +769,29 @@
478769 char can_boot = 1;
479770 char retry_no_vbmeta_partition = 1;
480771 unsigned long load_address = *android_load_address;
481
- struct andr_img_hdr *hdr;
772
+ int ret;
482773
483
- requested_partitions[0] = boot_partname;
774
+ dev_desc = rockchip_get_bootdev();
775
+ if (!dev_desc)
776
+ return AVB_IO_RESULT_ERROR_IO;
777
+
778
+ if (part_get_info_by_name(dev_desc, boot_partname, &part_info) < 0) {
779
+ printf("Could not find \"%s\" partition\n", boot_partname);
780
+ return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
781
+ }
782
+
783
+ hdr = populate_andr_img_hdr(dev_desc, &part_info);
784
+ if (!hdr) {
785
+ printf("No valid android hdr\n");
786
+ return AVB_IO_RESULT_ERROR_NO_SUCH_VALUE;
787
+ }
788
+
789
+ if (hdr->header_version >= 4) {
790
+ requested_partitions[1] = ANDROID_PARTITION_VENDOR_BOOT;
791
+ if (((hdr->os_version >> 25) & 0x7f) >= 13)
792
+ requested_partitions[2] = ANDROID_PARTITION_INIT_BOOT;
793
+ }
794
+
484795 ops = avb_ops_user_new();
485796 if (ops == NULL) {
486797 printf("avb_ops_user_new() failed!\n");
....@@ -497,7 +808,7 @@
497808 if (unlocked & LOCK_MASK)
498809 flags |= AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR;
499810
500
- if(load_metadata(ops->ab_ops, &ab_data, &ab_data_orig)) {
811
+ if (load_metadata(ops->ab_ops, &ab_data, &ab_data_orig)) {
501812 printf("Can not load metadata\n");
502813 return AVB_SLOT_VERIFY_RESULT_ERROR_IO;
503814 }
....@@ -509,8 +820,30 @@
509820 else
510821 slot_index_to_boot = 0;
511822
512
- if (strcmp(boot_partname, "recovery") == 0)
823
+ if (strcmp(boot_partname, ANDROID_PARTITION_RECOVERY) == 0)
513824 flags |= AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION;
825
+
826
+#ifdef CONFIG_MP_BOOT
827
+ preload_user_data.boot.addr = (void *)mpb_post(1);
828
+ preload_user_data.boot.size = (size_t)mpb_post(2);
829
+#endif
830
+
831
+ /* use preload one if available */
832
+ if (preload_user_data.boot.addr) {
833
+ data = (struct AvbOpsData *)(ops->user_data);
834
+
835
+ data->slot_suffix = slot_suffix;
836
+ data->boot = preload_user_data.boot;
837
+ data->vendor_boot = preload_user_data.vendor_boot;
838
+ data->init_boot = preload_user_data.init_boot;
839
+ data->resource = preload_user_data.resource;
840
+ } else {
841
+ ret = avb_image_distribute_prepare(slot_data, ops, slot_suffix);
842
+ if (ret < 0) {
843
+ printf("avb image distribute prepare failed %d\n", ret);
844
+ return AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
845
+ }
846
+ }
514847
515848 retry_verify:
516849 verify_result =
....@@ -519,10 +852,10 @@
519852 slot_suffix,
520853 flags,
521854 AVB_HASHTREE_ERROR_MODE_RESTART,
522
- &slot_data[0]);
855
+ &slot_data);
523856 if (verify_result != AVB_SLOT_VERIFY_RESULT_OK &&
524857 verify_result != AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED) {
525
- if (retry_no_vbmeta_partition && strcmp(boot_partname, "recovery") == 0) {
858
+ if (retry_no_vbmeta_partition && strcmp(boot_partname, ANDROID_PARTITION_RECOVERY) == 0) {
526859 printf("Verify recovery with vbmeta.\n");
527860 flags &= ~AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION;
528861 retry_no_vbmeta_partition = 0;
....@@ -558,7 +891,7 @@
558891 break;
559892 }
560893
561
- if (!slot_data[0]) {
894
+ if (!slot_data) {
562895 can_boot = 0;
563896 goto out;
564897 }
....@@ -569,12 +902,12 @@
569902 int len = 0;
570903 char *bootargs, *newbootargs;
571904 #ifdef CONFIG_ANDROID_AVB_ROLLBACK_INDEX
572
- if (rk_avb_update_stored_rollback_indexes_for_slot(ops, slot_data[0]))
905
+ if (rk_avb_update_stored_rollback_indexes_for_slot(ops, slot_data))
573906 printf("Fail to update the rollback indexes.\n");
574907 #endif
575
- if (*slot_data[0]->cmdline) {
576
- debug("Kernel command line: %s\n", slot_data[0]->cmdline);
577
- len += strlen(slot_data[0]->cmdline);
908
+ if (slot_data->cmdline) {
909
+ debug("Kernel command line: %s\n", slot_data->cmdline);
910
+ len += strlen(slot_data->cmdline);
578911 }
579912
580913 bootargs = env_get("bootargs");
....@@ -593,49 +926,15 @@
593926 strcpy(newbootargs, bootargs);
594927 strcat(newbootargs, " ");
595928 }
596
- if (*slot_data[0]->cmdline)
597
- strcat(newbootargs, slot_data[0]->cmdline);
929
+ if (slot_data->cmdline)
930
+ strcat(newbootargs, slot_data->cmdline);
598931 env_set("bootargs", newbootargs);
599932
600
- hdr = (void *)slot_data[0]->loaded_partitions->data;
601
-
602
- /*
603
- * populate boot_img_hdr_v34
604
- *
605
- * If allow verification error: the image is loaded by
606
- * ops->get_preloaded_partition() which auto populates
607
- * boot_img_hdr_v34.
608
- *
609
- * If not allow verification error: the image is full loaded
610
- * by ops->read_from_partition() which doesn't populate
611
- * boot_img_hdr_v34, we need to fix it here.
612
- */
613
- if (hdr->header_version >= 3 &&
614
- !(flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR)) {
615
- struct andr_img_hdr *v3hdr;
616
- struct blk_desc *dev_desc;
617
- disk_partition_t part;
618
-
619
- dev_desc = rockchip_get_bootdev();
620
- if (!dev_desc)
621
- return -1;
622
-
623
- if (part_get_info_by_name(dev_desc,
624
- boot_partname, &part) < 0)
625
- return -1;
626
-
627
- v3hdr = populate_andr_img_hdr(dev_desc, &part);
628
- if (v3hdr) {
629
- memcpy(hdr, v3hdr, sizeof(*v3hdr));
630
- free(v3hdr);
631
- }
632
- }
633
-
634
- /* Reserve page_size */
635
- load_address -= hdr->page_size;
636
- if (android_image_memcpy_separate(hdr, &load_address)) {
637
- printf("Failed to separate copy android image\n");
638
- return AVB_SLOT_VERIFY_RESULT_ERROR_IO;
933
+ /* if need, distribute full image to where they should be */
934
+ ret = avb_image_distribute_finish(slot_data, flags, &load_address);
935
+ if (ret) {
936
+ printf("avb image distribute finish failed %d\n", ret);
937
+ return ret;
639938 }
640939 *android_load_address = load_address;
641940 } else {
....@@ -649,8 +948,8 @@
649948 verify_result = AVB_SLOT_VERIFY_RESULT_ERROR_IO;
650949 }
651950
652
- if (slot_data[0] != NULL)
653
- avb_slot_verify_data_free(slot_data[0]);
951
+ if (slot_data != NULL)
952
+ avb_slot_verify_data_free(slot_data);
654953
655954 if ((unlocked & LOCK_MASK) && can_boot)
656955 return 0;
....@@ -1047,10 +1346,6 @@
10471346 printf("Android image load failed\n");
10481347 return -1;
10491348 }
1050
-#endif
1051
-
1052
-#ifdef CONFIG_ANDROID_AB
1053
- ab_update_root_uuid();
10541349 #endif
10551350
10561351 /* Set Android root variables. */
u-boot/common/board_f.c
....@@ -21,6 +21,7 @@
2121 #include <init_helpers.h>
2222 #include <malloc.h>
2323 #include <mapmem.h>
24
+#include <mp_boot.h>
2425 #include <os.h>
2526 #include <post.h>
2627 #include <relocate.h>
....@@ -254,6 +255,9 @@
254255 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
255256 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
256257 #endif
258
+#ifdef CONFIG_MP_BOOT
259
+ mpb_init_x(3);
260
+#endif
257261 return 0;
258262 }
259263
u-boot/common/board_info.c
....@@ -26,6 +26,7 @@
2626 if (model)
2727 printf("Model: %s\n", model);
2828 #endif
29
+ printf("MPIDR: 0x%lx\n", (ulong)read_mpidr());
2930
3031 #ifdef CONFIG_ARM64_BOOT_AARCH32
3132 if (!(gd->flags & GD_FLG_RELOC))
u-boot/common/board_r.c
....@@ -481,21 +481,6 @@
481481 }
482482 #endif
483483
484
-#ifdef CONFIG_MTD_BLK
485
-static int initr_mtd_blk(void)
486
-{
487
-#ifndef CONFIG_USING_KERNEL_DTB
488
- struct blk_desc *dev_desc;
489
-
490
- puts("mtd_blk: ");
491
- dev_desc = rockchip_get_bootdev();
492
- if (dev_desc)
493
- mtd_blk_map_partitions(dev_desc);
494
-#endif
495
- return 0;
496
-}
497
-#endif
498
-
499484 #if !defined(CONFIG_USING_KERNEL_DTB) || !defined(CONFIG_ENV_IS_NOWHERE)
500485 /*
501486 * Tell if it's OK to load the environment early in boot.
....@@ -966,9 +951,6 @@
966951 #endif
967952 #ifdef CONFIG_CMD_ONENAND
968953 initr_onenand,
969
-#endif
970
-#ifdef CONFIG_MTD_BLK
971
- initr_mtd_blk,
972954 #endif
973955 #ifdef CONFIG_MMC
974956 initr_mmc,
u-boot/common/bootm.c
....@@ -31,7 +31,7 @@
3131 #include <image.h>
3232
3333 #ifdef USE_HOSTCC
34
-#define CONFIG_SYS_BOOTM_LEN 0x4000000
34
+#define CONFIG_SYS_BOOTM_LEN 0x10000000
3535 #endif
3636
3737 #ifndef CONFIG_SYS_BOOTM_LEN
u-boot/common/fb_mmc.c
....@@ -31,6 +31,15 @@
3131 #define CONFIG_FASTBOOT_MBR_NAME "mbr"
3232 #endif
3333
34
+#ifndef CONFIG_FASTBOOT_IDBLOCK_NAME
35
+#define CONFIG_FASTBOOT_IDBLOCK_NAME "idblock"
36
+#endif
37
+
38
+#define CONFIG_FASTBOOT_MMC_BLOCK_SIZE 512
39
+#define CONFIG_FASTBOOT_IDBLOCK_SECTOR 64
40
+/* idblock sector:64 ~ 64 + 5 * 1024(512K for each MiniloadAll.bin) */
41
+#define CONFIG_FASTBOOT_IDBLOCK_SECTOR_SIZE 5184
42
+
3443 #define BOOT_PARTITION_NAME "boot"
3544 #define FASTBOOT_MAX_BLK_WRITE 16384
3645 static ulong timer;
....@@ -363,6 +372,14 @@
363372 }
364373 #endif
365374
375
+ if (strcmp(cmd, CONFIG_FASTBOOT_IDBLOCK_NAME) == 0) {
376
+ printf("%s: updating IDBLOCK\n", __func__);
377
+ info.blksz = CONFIG_FASTBOOT_MMC_BLOCK_SIZE;
378
+ info.start = CONFIG_FASTBOOT_IDBLOCK_SECTOR;
379
+ info.size = CONFIG_FASTBOOT_IDBLOCK_SECTOR_SIZE;
380
+ goto download;
381
+ }
382
+
366383 #ifdef CONFIG_ANDROID_BOOT_IMAGE
367384 if (strncasecmp(cmd, "zimage", 6) == 0) {
368385 fb_mmc_update_zimage(dev_desc, download_buffer, download_bytes, response);
....@@ -376,6 +393,7 @@
376393 return;
377394 }
378395
396
+download:
379397 if (is_sparse_image(download_buffer)) {
380398 struct fb_mmc_sparse sparse_priv;
381399 struct sparse_storage sparse;
u-boot/common/image-android.c
....@@ -6,14 +6,16 @@
66
77 #include <common.h>
88 #include <image.h>
9
-#include <android_image.h>
9
+#include <android_ab.h>
1010 #include <android_bootloader.h>
11
+#include <android_image.h>
1112 #include <malloc.h>
1213 #include <mapmem.h>
1314 #include <errno.h>
1415 #include <boot_rkimg.h>
1516 #include <crypto.h>
1617 #include <sysmem.h>
18
+#include <mp_boot.h>
1719 #include <u-boot/sha1.h>
1820 #ifdef CONFIG_RKIMG_BOOTLOADER
1921 #include <asm/arch/resource_img.h>
....@@ -28,8 +30,8 @@
2830 DECLARE_GLOBAL_DATA_PTR;
2931
3032 #define ANDROID_IMAGE_DEFAULT_KERNEL_ADDR 0x10008000
31
-#define ANDROID_Q_VER 10
3233 #define ANDROID_PARTITION_VENDOR_BOOT "vendor_boot"
34
+#define ANDROID_PARTITION_INIT_BOOT "init_boot"
3335
3436 #define BLK_CNT(_num_bytes, _block_size) \
3537 ((_num_bytes + _block_size - 1) / _block_size)
....@@ -37,27 +39,110 @@
3739 static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1];
3840 static u32 android_kernel_comp_type = IH_COMP_NONE;
3941
40
-u32 android_image_major_version(void)
42
+static int android_version_init(void)
4143 {
42
- /* MSB 7-bits */
43
- return gd->bd->bi_andr_version >> 25;
44
+ struct andr_img_hdr *hdr = NULL;
45
+ struct blk_desc *desc;
46
+ const char *part_name = PART_BOOT;
47
+ disk_partition_t part;
48
+ int os_version;
49
+
50
+ desc = rockchip_get_bootdev();
51
+ if (!desc) {
52
+ printf("No bootdev\n");
53
+ return -1;
54
+ }
55
+
56
+#ifdef CONFIG_ANDROID_AB
57
+ part_name = ab_can_find_recovery_part() ? PART_RECOVERY : PART_BOOT;
58
+#endif
59
+ if (part_get_info_by_name(desc, part_name, &part) < 0)
60
+ return -1;
61
+
62
+ hdr = populate_andr_img_hdr(desc, &part);
63
+ if (!hdr)
64
+ return -1;
65
+
66
+ os_version = hdr->os_version;
67
+ if (os_version)
68
+ printf("Android %u.%u, Build %u.%u, v%d\n",
69
+ (os_version >> 25) & 0x7f, (os_version >> 18) & 0x7F,
70
+ ((os_version >> 4) & 0x7f) + 2000, os_version & 0x0F,
71
+ hdr->header_version);
72
+ free(hdr);
73
+
74
+ return (os_version >> 25) & 0x7f;
4475 }
4576
4677 u32 android_bcb_msg_sector_offset(void)
4778 {
79
+ static int android_version = -1; /* static */
80
+
4881 /*
49
- * Rockchip platforms defines BCB message at the 16KB offset of
50
- * misc partition while the Google defines it at 0x00 offset.
82
+ * get android os version:
5183 *
52
- * From Android-Q, the 0x00 offset is mandary on Google VTS, so that
53
- * this is a compatibility according to android image 'os_version'.
84
+ * There are two types of misc.img:
85
+ * Rockchip platforms defines BCB message at the 16KB offset of
86
+ * misc.img except for the Android version >= 10. Because Google
87
+ * defines it at 0x00 offset, and from Android-10 it becoms mandary
88
+ * on Google VTS.
89
+ *
90
+ * So we must get android 'os_version' to identify which type we
91
+ * are using, then we could able to use rockchip_get_boot_mode()
92
+ * which reads BCB from misc.img.
5493 */
5594 #ifdef CONFIG_RKIMG_BOOTLOADER
56
- return (android_image_major_version() >= ANDROID_Q_VER) ? 0x00 : 0x20;
95
+ if (android_version < 0)
96
+ android_version = android_version_init();
97
+
98
+ return (android_version >= 10) ? 0x00 : 0x20;
5799 #else
58100 return 0x00;
59101 #endif
60102 }
103
+
104
+#ifdef CONFIG_ROCKCHIP_RESOURCE_IMAGE
105
+int android_image_init_resource(struct blk_desc *desc,
106
+ disk_partition_t *out_part,
107
+ ulong *out_blk_offset)
108
+{
109
+ struct andr_img_hdr *hdr = NULL;
110
+ const char *part_name = ANDROID_PARTITION_BOOT;
111
+ disk_partition_t part;
112
+ ulong offset;
113
+ int ret = 0;
114
+
115
+ if (!desc)
116
+ return -ENODEV;
117
+
118
+#ifndef CONFIG_ANDROID_AB
119
+ if (rockchip_get_boot_mode() == BOOT_MODE_RECOVERY)
120
+ part_name = ANDROID_PARTITION_RECOVERY;
121
+#endif
122
+ if (part_get_info_by_name(desc, part_name, &part) < 0)
123
+ return -ENOENT;
124
+
125
+ hdr = populate_andr_img_hdr(desc, &part);
126
+ if (!hdr)
127
+ return -EINVAL;
128
+
129
+ if (hdr->header_version >= 2 && hdr->dtb_size)
130
+ env_update("bootargs", "androidboot.dtb_idx=0");
131
+
132
+ if (hdr->header_version <= 2) {
133
+ offset = hdr->page_size +
134
+ ALIGN(hdr->kernel_size, hdr->page_size) +
135
+ ALIGN(hdr->ramdisk_size, hdr->page_size);
136
+ *out_part = part;
137
+ *out_blk_offset = DIV_ROUND_UP(offset, desc->blksz);
138
+ } else {
139
+ ret = -EINVAL;
140
+ }
141
+ free(hdr);
142
+
143
+ return ret;
144
+}
145
+#endif
61146
62147 static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr)
63148 {
....@@ -323,7 +408,7 @@
323408
324409 typedef enum {
325410 IMG_KERNEL,
326
- IMG_RAMDISK,
411
+ IMG_RAMDISK, /* within boot.img or init_boot.img(Android-13 or later) */
327412 IMG_SECOND,
328413 IMG_RECOVERY_DTBO,
329414 IMG_RK_DTB, /* within resource.img in second position */
....@@ -343,7 +428,9 @@
343428 {
344429 struct blk_desc *desc = rockchip_get_bootdev();
345430 disk_partition_t part_vendor_boot;
431
+ disk_partition_t part_init_boot;
346432 __maybe_unused u32 typesz;
433
+ u32 andr_version = (hdr->os_version >> 25) & 0x7f;
347434 ulong pgsz = hdr->page_size;
348435 ulong blksz = desc->blksz;
349436 ulong blkcnt, blkoff;
....@@ -352,6 +439,7 @@
352439 ulong extra = 0;
353440 ulong length;
354441 void *buffer;
442
+ void *tmp = NULL;
355443 int ret = 0;
356444
357445 switch (img) {
....@@ -366,17 +454,20 @@
366454 return -ENOMEM;
367455 break;
368456 case IMG_VENDOR_RAMDISK:
369
- if (part_get_info_by_name(desc,
370
- ANDROID_PARTITION_VENDOR_BOOT,
371
- &part_vendor_boot) < 0) {
372
- printf("No vendor boot partition\n");
373
- return -ENOENT;
457
+ if (hdr->vendor_boot_buf) {
458
+ ram_base = hdr->vendor_boot_buf;
459
+ } else {
460
+ if (part_get_info_by_name(desc,
461
+ ANDROID_PARTITION_VENDOR_BOOT,
462
+ &part_vendor_boot) < 0) {
463
+ printf("No vendor boot partition\n");
464
+ return -ENOENT;
465
+ }
466
+ ram_base = 0;
374467 }
375
- /* Always load vendor boot from storage: avb full load boot/recovery */
468
+
376469 blkstart = part_vendor_boot.start;
377470 pgsz = hdr->vendor_page_size;
378
- ram_base = 0;
379
-
380471 bsoffs = ALIGN(VENDOR_BOOT_HDRv3_SIZE, pgsz);
381472 length = hdr->vendor_ramdisk_size;
382473 buffer = (void *)env_get_ulong("ramdisk_addr_r", 16, 0);
....@@ -400,7 +491,25 @@
400491 return -ENOMEM;
401492 break;
402493 case IMG_RAMDISK:
403
- bsoffs = pgsz + ALIGN(hdr->kernel_size, pgsz);
494
+ /* get ramdisk from init_boot.img ? */
495
+ if (hdr->header_version >= 4 && andr_version >= 13) {
496
+ if (hdr->init_boot_buf) {
497
+ ram_base = hdr->init_boot_buf;
498
+ } else {
499
+ if (part_get_info_by_name(desc,
500
+ ANDROID_PARTITION_INIT_BOOT, &part_init_boot) < 0) {
501
+ printf("No init boot partition\n");
502
+ return -ENOENT;
503
+ }
504
+ blkstart = part_init_boot.start;
505
+ ram_base = 0;
506
+ }
507
+ bsoffs = pgsz;
508
+ } else {
509
+ /* get ramdisk from generic boot.img */
510
+ bsoffs = pgsz + ALIGN(hdr->kernel_size, pgsz);
511
+ }
512
+
404513 length = hdr->ramdisk_size;
405514 buffer = (void *)env_get_ulong("ramdisk_addr_r", 16, 0);
406515 blkcnt = DIV_ROUND_UP(hdr->ramdisk_size, blksz);
....@@ -412,15 +521,20 @@
412521 * | ramdisk |
413522 * |----------------|
414523 *
415
- * ramdisk_addr_r v3:
524
+ * ramdisk_addr_r v3 (Android-11 and later):
416525 * |----------------|---------|
417526 * | vendor-ramdisk | ramdisk |
418527 * |----------------|---------|
419528 *
420
- * ramdisk_addr_r v4:
529
+ * ramdisk_addr_r v4 (Android-12 and later):
421530 * |----------------|---------|------------|------------|
422531 * | vendor-ramdisk | ramdisk | bootconfig | bootparams |
423532 * |----------------|---------|------------|------------|
533
+ *
534
+ * ramdisk_addr_r v4 + init_boot(Android-13 and later):
535
+ * |----------------|----------------|------------|------------|
536
+ * | vendor-ramdisk | (init_)ramdisk | bootconfig | bootparams |
537
+ * |----------------|----------------|------------|------------|
424538 */
425539 if (hdr->header_version >= 3) {
426540 buffer += hdr->vendor_ramdisk_size;
....@@ -439,17 +553,20 @@
439553 case IMG_BOOTCONFIG:
440554 if (hdr->header_version < 4)
441555 return 0;
442
- if (part_get_info_by_name(desc,
443
- ANDROID_PARTITION_VENDOR_BOOT,
444
- &part_vendor_boot) < 0) {
445
- printf("No vendor boot partition\n");
446
- return -ENOENT;
447
- }
448556
557
+ if (hdr->vendor_boot_buf) {
558
+ ram_base = hdr->vendor_boot_buf;
559
+ } else {
560
+ if (part_get_info_by_name(desc,
561
+ ANDROID_PARTITION_VENDOR_BOOT,
562
+ &part_vendor_boot) < 0) {
563
+ printf("No vendor boot partition\n");
564
+ return -ENOENT;
565
+ }
566
+ ram_base = 0;
567
+ }
449568 blkstart = part_vendor_boot.start;
450569 pgsz = hdr->vendor_page_size;
451
- ram_base = 0;
452
-
453570 bsoffs = ALIGN(VENDOR_BOOT_HDRv4_SIZE, pgsz) +
454571 ALIGN(hdr->vendor_ramdisk_size, pgsz) +
455572 ALIGN(hdr->dtb_size, pgsz) +
....@@ -471,7 +588,7 @@
471588 ALIGN(hdr->ramdisk_size, pgsz);
472589 length = hdr->second_size;
473590 blkcnt = DIV_ROUND_UP(hdr->second_size, blksz);
474
- buffer = malloc(blkcnt * blksz);
591
+ buffer = tmp = malloc(blkcnt * blksz);
475592 typesz = sizeof(hdr->second_size);
476593 break;
477594 case IMG_RECOVERY_DTBO:
....@@ -481,7 +598,7 @@
481598 ALIGN(hdr->second_size, pgsz);
482599 length = hdr->recovery_dtbo_size;
483600 blkcnt = DIV_ROUND_UP(hdr->recovery_dtbo_size, blksz);
484
- buffer = malloc(blkcnt * blksz);
601
+ buffer = tmp = malloc(blkcnt * blksz);
485602 typesz = sizeof(hdr->recovery_dtbo_size);
486603 break;
487604 case IMG_DTB:
....@@ -492,7 +609,7 @@
492609 ALIGN(hdr->recovery_dtbo_size, pgsz);
493610 length = hdr->dtb_size;
494611 blkcnt = DIV_ROUND_UP(hdr->dtb_size, blksz);
495
- buffer = malloc(blkcnt * blksz);
612
+ buffer = tmp = malloc(blkcnt * blksz);
496613 typesz = sizeof(hdr->dtb_size);
497614 break;
498615 case IMG_RK_DTB:
....@@ -540,14 +657,19 @@
540657 if (hdr->header_version < 3) {
541658 #ifdef CONFIG_ANDROID_BOOT_IMAGE_HASH
542659 #ifdef CONFIG_DM_CRYPTO
543
- crypto_sha_update(crypto, (u32 *)buffer, length);
544
- crypto_sha_update(crypto, (u32 *)&length, typesz);
660
+ if (crypto) {
661
+ crypto_sha_update(crypto, (u32 *)buffer, length);
662
+ crypto_sha_update(crypto, (u32 *)&length, typesz);
663
+ }
545664 #else
546665 sha1_update(&sha1_ctx, (void *)buffer, length);
547666 sha1_update(&sha1_ctx, (void *)&length, typesz);
548667 #endif
549668 #endif
550669 }
670
+
671
+ if (tmp)
672
+ free(tmp);
551673
552674 return 0;
553675 }
....@@ -605,7 +727,12 @@
605727 return -1;
606728
607729 #ifdef CONFIG_ANDROID_BOOT_IMAGE_HASH
608
- if (hdr->header_version < 3) {
730
+ int verify = 1;
731
+
732
+#ifdef CONFIG_MP_BOOT
733
+ verify = mpb_post(3);
734
+#endif
735
+ if (hdr->header_version < 3 && verify) {
609736 struct udevice *dev = NULL;
610737 uchar hash[20];
611738 #ifdef CONFIG_DM_CRYPTO
....@@ -936,6 +1063,7 @@
9361063 const disk_partition_t *boot_img)
9371064 {
9381065 struct boot_img_hdr_v34 *boot_hdr;
1066
+ disk_partition_t part;
9391067 long blk_cnt, blks_read;
9401068
9411069 blk_cnt = BLK_CNT(sizeof(struct boot_img_hdr_v34), dev_desc->blksz);
....@@ -960,6 +1088,13 @@
9601088 printf("boot header %d, is not >= v3.\n",
9611089 boot_hdr->header_version);
9621090 return NULL;
1091
+ }
1092
+
1093
+ /* Start from android-13 GKI, it doesn't assign 'os_version' */
1094
+ if (boot_hdr->header_version >= 4 && boot_hdr->os_version == 0) {
1095
+ if (part_get_info_by_name(dev_desc,
1096
+ ANDROID_PARTITION_INIT_BOOT, &part) > 0)
1097
+ boot_hdr->os_version = 13 << 25;
9631098 }
9641099
9651100 return boot_hdr;
....@@ -1003,19 +1138,26 @@
10031138 return vboot_hdr;
10041139 }
10051140
1006
-static int populate_boot_info(const struct boot_img_hdr_v34 *boot_hdr,
1007
- const struct vendor_boot_img_hdr_v34 *vendor_hdr,
1008
- struct andr_img_hdr *hdr)
1141
+int populate_boot_info(const struct boot_img_hdr_v34 *boot_hdr,
1142
+ const struct vendor_boot_img_hdr_v34 *vendor_boot_hdr,
1143
+ const struct boot_img_hdr_v34 *init_boot_hdr,
1144
+ struct andr_img_hdr *hdr, bool save_hdr)
10091145 {
10101146 memset(hdr->magic, 0, ANDR_BOOT_MAGIC_SIZE);
10111147 memcpy(hdr->magic, boot_hdr->magic, ANDR_BOOT_MAGIC_SIZE);
10121148
10131149 hdr->kernel_size = boot_hdr->kernel_size;
1014
- /* don't use vendor_hdr->kernel_addr, we prefer "hdr + hdr->page_size" */
1150
+ /* don't use vendor_boot_hdr->kernel_addr, we prefer "hdr + hdr->page_size" */
10151151 hdr->kernel_addr = ANDROID_IMAGE_DEFAULT_KERNEL_ADDR;
1016
- /* generic ramdisk: immediately following the vendor ramdisk */
1017
- hdr->boot_ramdisk_size = boot_hdr->ramdisk_size;
1018
- hdr->ramdisk_size = boot_hdr->ramdisk_size;
1152
+
1153
+ /*
1154
+ * generic ramdisk: immediately following the vendor ramdisk.
1155
+ * It can be from init_boot.img or boot.img.
1156
+ */
1157
+ if (init_boot_hdr)
1158
+ hdr->ramdisk_size = init_boot_hdr->ramdisk_size;
1159
+ else
1160
+ hdr->ramdisk_size = boot_hdr->ramdisk_size;
10191161
10201162 /* actually, useless */
10211163 hdr->ramdisk_addr = env_get_ulong("ramdisk_addr_r", 16, 0);
....@@ -1024,7 +1166,7 @@
10241166 hdr->second_size = 0;
10251167 hdr->second_addr = 0;
10261168
1027
- hdr->tags_addr = vendor_hdr->tags_addr;
1169
+ hdr->tags_addr = vendor_boot_hdr->tags_addr;
10281170
10291171 /* fixed in v3 */
10301172 hdr->page_size = 4096;
....@@ -1032,7 +1174,7 @@
10321174 hdr->os_version = boot_hdr->os_version;
10331175
10341176 memset(hdr->name, 0, ANDR_BOOT_NAME_SIZE);
1035
- strncpy(hdr->name, (const char *)vendor_hdr->name, ANDR_BOOT_NAME_SIZE);
1177
+ strncpy(hdr->name, (const char *)vendor_boot_hdr->name, ANDR_BOOT_NAME_SIZE);
10361178
10371179 /* removed in v3 */
10381180 memset(hdr->cmdline, 0, ANDR_BOOT_ARGS_SIZE);
....@@ -1042,14 +1184,14 @@
10421184 hdr->recovery_dtbo_offset = 0;
10431185
10441186 hdr->header_size = boot_hdr->header_size;
1045
- hdr->dtb_size = vendor_hdr->dtb_size;
1046
- hdr->dtb_addr = vendor_hdr->dtb_addr;
1187
+ hdr->dtb_size = vendor_boot_hdr->dtb_size;
1188
+ hdr->dtb_addr = vendor_boot_hdr->dtb_addr;
10471189
10481190 /* boot_img_hdr_v34 fields */
1049
- hdr->vendor_ramdisk_size = vendor_hdr->vendor_ramdisk_size;
1050
- hdr->vendor_page_size = vendor_hdr->page_size;
1051
- hdr->vendor_header_version = vendor_hdr->header_version;
1052
- hdr->vendor_header_size = vendor_hdr->header_size;
1191
+ hdr->vendor_ramdisk_size = vendor_boot_hdr->vendor_ramdisk_size;
1192
+ hdr->vendor_page_size = vendor_boot_hdr->page_size;
1193
+ hdr->vendor_header_version = vendor_boot_hdr->header_version;
1194
+ hdr->vendor_header_size = vendor_boot_hdr->header_size;
10531195
10541196 hdr->total_cmdline = calloc(1, TOTAL_BOOT_ARGS_SIZE);
10551197 if (!hdr->total_cmdline)
....@@ -1057,30 +1199,33 @@
10571199 strncpy(hdr->total_cmdline, (const char *)boot_hdr->cmdline,
10581200 sizeof(boot_hdr->cmdline));
10591201 strncat(hdr->total_cmdline, " ", 1);
1060
- strncat(hdr->total_cmdline, (const char *)vendor_hdr->cmdline,
1061
- sizeof(vendor_hdr->cmdline));
1202
+ strncat(hdr->total_cmdline, (const char *)vendor_boot_hdr->cmdline,
1203
+ sizeof(vendor_boot_hdr->cmdline));
10621204
10631205 /* new for header v4 */
1064
- if (vendor_hdr->header_version > 3) {
1206
+ if (vendor_boot_hdr->header_version >= 4) {
10651207 hdr->vendor_ramdisk_table_size =
1066
- vendor_hdr->vendor_ramdisk_table_size;
1208
+ vendor_boot_hdr->vendor_ramdisk_table_size;
10671209 hdr->vendor_ramdisk_table_entry_num =
1068
- vendor_hdr->vendor_ramdisk_table_entry_num;
1210
+ vendor_boot_hdr->vendor_ramdisk_table_entry_num;
10691211 hdr->vendor_ramdisk_table_entry_size =
1070
- vendor_hdr->vendor_ramdisk_table_entry_size;
1212
+ vendor_boot_hdr->vendor_ramdisk_table_entry_size;
10711213 /*
10721214 * If we place additional "androidboot.xxx" parameters after
10731215 * bootconfig, this field value should be increased,
10741216 * but not over than ANDROID_ADDITION_BOOTCONFIG_PARAMS_MAX_SIZE.
10751217 */
10761218 hdr->vendor_bootconfig_size =
1077
- vendor_hdr->vendor_bootconfig_size;
1219
+ vendor_boot_hdr->vendor_bootconfig_size;
10781220 } else {
10791221 hdr->vendor_ramdisk_table_size = 0;
10801222 hdr->vendor_ramdisk_table_entry_num = 0;
10811223 hdr->vendor_ramdisk_table_entry_size = 0;
10821224 hdr->vendor_bootconfig_size = 0;
10831225 }
1226
+
1227
+ hdr->init_boot_buf = save_hdr ? (void *)init_boot_hdr : 0;
1228
+ hdr->vendor_boot_buf = save_hdr ? (void *)vendor_boot_hdr : 0;
10841229
10851230 if (hdr->page_size < sizeof(*hdr)) {
10861231 printf("android hdr is over size\n");
....@@ -1110,10 +1255,13 @@
11101255 disk_partition_t *part_boot)
11111256 {
11121257 disk_partition_t part_vendor_boot;
1113
- struct vendor_boot_img_hdr_v34 *vboot_hdr;
1114
- struct boot_img_hdr_v34 *boot_hdr;
1115
- struct andr_img_hdr *andr_hdr;
1258
+ disk_partition_t part_init_boot;
1259
+ struct vendor_boot_img_hdr_v34 *vboot_hdr = NULL;
1260
+ struct boot_img_hdr_v34 *iboot_hdr = NULL;
1261
+ struct boot_img_hdr_v34 *boot_hdr = NULL;
1262
+ struct andr_img_hdr *andr_hdr = NULL;
11161263 int header_version;
1264
+ int andr_version;
11171265
11181266 if (!dev_desc || !part_boot)
11191267 return NULL;
....@@ -1134,6 +1282,7 @@
11341282
11351283 header_version = andr_hdr->header_version;
11361284 free(andr_hdr);
1285
+ andr_hdr = NULL;
11371286
11381287 if (header_version < 3) {
11391288 return extract_boot_image_v012_header(dev_desc, part_boot);
....@@ -1150,6 +1299,23 @@
11501299 if (!boot_hdr || !vboot_hdr)
11511300 goto image_load_exit;
11521301
1302
+ andr_version = (boot_hdr->os_version >> 25) & 0x7f;
1303
+ if (header_version >= 4 && andr_version >= 13) {
1304
+ if (part_get_info_by_name(dev_desc,
1305
+ ANDROID_PARTITION_INIT_BOOT,
1306
+ &part_init_boot) < 0) {
1307
+ printf("No init boot partition\n");
1308
+ return NULL;
1309
+ }
1310
+ iboot_hdr = extract_boot_image_v34_header(dev_desc, &part_init_boot);
1311
+ if (!iboot_hdr)
1312
+ goto image_load_exit;
1313
+ if (!iboot_hdr->ramdisk_size) {
1314
+ printf("No ramdisk in init boot partition\n");
1315
+ goto image_load_exit;
1316
+ }
1317
+ }
1318
+
11531319 andr_hdr = (struct andr_img_hdr *)
11541320 malloc(sizeof(struct andr_img_hdr));
11551321 if (!andr_hdr) {
....@@ -1157,21 +1323,21 @@
11571323 goto image_load_exit;
11581324 }
11591325
1160
- if (populate_boot_info(boot_hdr, vboot_hdr, andr_hdr)) {
1326
+ if (populate_boot_info(boot_hdr, vboot_hdr,
1327
+ iboot_hdr, andr_hdr, false)) {
11611328 printf("populate boot info failed\n");
11621329 goto image_load_exit;
11631330 }
11641331
1165
- free(boot_hdr);
1166
- free(vboot_hdr);
1332
+image_load_exit:
1333
+ if (boot_hdr)
1334
+ free(boot_hdr);
1335
+ if (iboot_hdr)
1336
+ free(iboot_hdr);
1337
+ if (vboot_hdr)
1338
+ free(vboot_hdr);
11671339
11681340 return andr_hdr;
1169
-
1170
-image_load_exit:
1171
- free(boot_hdr);
1172
- free(vboot_hdr);
1173
-
1174
- return NULL;
11751341 }
11761342
11771343 return NULL;
u-boot/common/image-fdt.c
....@@ -78,39 +78,16 @@
7878 }
7979 #endif
8080
81
-/**
82
- * boot_fdt_add_mem_rsv_regions - Mark the memreserve sections as unusable
83
- * @lmb: pointer to lmb handle, will be used for memory mgmt
84
- * @fdt_blob: pointer to fdt blob base address
85
- *
86
- * Adds the memreserve regions in the dtb to the lmb block. Adding the
87
- * memreserve regions prevents u-boot from using them to store the initrd
88
- * or the fdt blob.
89
- */
90
-void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob)
81
+void boot_mem_rsv_regions(struct lmb *lmb, void *fdt_blob)
9182 {
92
- uint64_t addr, size;
93
- int i, total;
9483 int rsv_offset, offset;
9584 fdt_size_t rsv_size;
9685 fdt_addr_t rsv_addr;
97
- /* we needn't repeat do reserve, do_bootm_linux would call this again */
98
- static int rsv_done;
9986 const void *prop;
87
+ int i = 0;
10088
101
- if (fdt_check_header(fdt_blob) != 0 || rsv_done)
89
+ if (fdt_check_header(fdt_blob) != 0)
10290 return;
103
-
104
- rsv_done = 1;
105
-
106
- total = fdt_num_mem_rsv(fdt_blob);
107
- for (i = 0; i < total; i++) {
108
- if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0)
109
- continue;
110
- printf(" reserving fdt memory region: addr=%llx size=%llx\n",
111
- (unsigned long long)addr, (unsigned long long)size);
112
- lmb_reserve(lmb, addr, size);
113
- }
11491
11592 rsv_offset = fdt_subnode_offset(fdt_blob, 0, "reserved-memory");
11693 if (rsv_offset == -FDT_ERR_NOTFOUND)
....@@ -128,13 +105,56 @@
128105 &rsv_size, false);
129106 if (rsv_addr == FDT_ADDR_T_NONE || !rsv_size)
130107 continue;
131
- printf(" 'reserved-memory' %s: addr=%llx size=%llx\n",
132
- fdt_get_name(fdt_blob, offset, NULL),
133
- (unsigned long long)rsv_addr, (unsigned long long)rsv_size);
134
- lmb_reserve(lmb, rsv_addr, rsv_size);
108
+
109
+ i++;
110
+ /* be quiet while reserve */
111
+ if (lmb) {
112
+ lmb_reserve(lmb, rsv_addr, rsv_size);
113
+ } else {
114
+ if (i == 1)
115
+ printf("## reserved-memory:\n");
116
+
117
+ printf(" %s: addr=%llx size=%llx\n",
118
+ fdt_get_name(fdt_blob, offset, NULL),
119
+ (unsigned long long)rsv_addr, (unsigned long long)rsv_size);
120
+ }
135121 }
136122 }
137123
124
+/**
125
+ * boot_fdt_add_mem_rsv_regions - Mark the memreserve sections as unusable
126
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
127
+ * @fdt_blob: pointer to fdt blob base address
128
+ *
129
+ * Adds the memreserve regions in the dtb to the lmb block. Adding the
130
+ * memreserve regions prevents u-boot from using them to store the initrd
131
+ * or the fdt blob.
132
+ */
133
+void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob)
134
+{
135
+ uint64_t addr, size;
136
+ int i, total;
137
+ /* we needn't repeat do reserve, do_bootm_linux would call this again */
138
+ static int rsv_done;
139
+
140
+ if (fdt_check_header(fdt_blob) != 0 || rsv_done)
141
+ return;
142
+
143
+ rsv_done = 1;
144
+
145
+ total = fdt_num_mem_rsv(fdt_blob);
146
+ for (i = 0; i < total; i++) {
147
+ if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0)
148
+ continue;
149
+ printf(" reserving fdt memory region: addr=%llx size=%llx\n",
150
+ (unsigned long long)addr, (unsigned long long)size);
151
+ lmb_reserve(lmb, addr, size);
152
+ }
153
+
154
+ /* lmb_reserve() for "reserved-memory" */
155
+ boot_mem_rsv_regions(lmb, fdt_blob);
156
+}
157
+
138158 #ifdef CONFIG_SYSMEM
139159 /**
140160 * boot_fdt_add_mem_rsv_regions - Mark the memreserve sections as unusable
u-boot/common/image-fit.c
....@@ -2175,6 +2175,7 @@
21752175 fit_image_check_os(fit, noffset, IH_OS_ARM_TRUSTED_FIRMWARE) ||
21762176 fit_image_check_os(fit, noffset, IH_OS_OP_TEE) ||
21772177 fit_image_check_os(fit, noffset, IH_OS_U_BOOT) ||
2178
+ fit_image_check_os(fit, noffset, IH_OS_QNX) ||
21782179 fit_image_check_os(fit, noffset, IH_OS_OPENRTOS);
21792180
21802181 /*
u-boot/common/image-sparse.c
....@@ -56,10 +56,10 @@
5656 lbaint_t blk;
5757 lbaint_t blkcnt;
5858 lbaint_t blks;
59
- uint32_t bytes_written = 0;
59
+ uint64_t bytes_written = 0;
6060 unsigned int chunk;
6161 unsigned int offset;
62
- unsigned int chunk_data_sz;
62
+ uint64_t chunk_data_sz;
6363 uint32_t *fill_buf = NULL;
6464 uint32_t fill_val;
6565 sparse_header_t *sparse_header;
....@@ -130,8 +130,8 @@
130130 sizeof(chunk_header_t));
131131 }
132132
133
- chunk_data_sz = sparse_header->blk_sz * chunk_header->chunk_sz;
134
- blkcnt = chunk_data_sz / info->blksz;
133
+ chunk_data_sz = ((u64)sparse_header->blk_sz) * chunk_header->chunk_sz;
134
+ blkcnt = DIV_ROUND_UP_ULL(chunk_data_sz, info->blksz);
135135 switch (chunk_header->chunk_type) {
136136 case CHUNK_TYPE_RAW:
137137 if (chunk_header->total_sz !=
....@@ -161,7 +161,7 @@
161161 return;
162162 }
163163 blk += blks;
164
- bytes_written += blkcnt * info->blksz;
164
+ bytes_written += ((u64)blkcnt) * info->blksz;
165165 total_blocks += chunk_header->chunk_sz;
166166 data += chunk_data_sz;
167167 break;
....@@ -222,8 +222,9 @@
222222 blk += blks;
223223 i += j;
224224 }
225
- bytes_written += blkcnt * info->blksz;
226
- total_blocks += chunk_data_sz / sparse_header->blk_sz;
225
+ bytes_written += ((u64)blkcnt) * info->blksz;
226
+ total_blocks += DIV_ROUND_UP_ULL(chunk_data_sz,
227
+ sparse_header->blk_sz);
227228 free(fill_buf);
228229 break;
229230
....@@ -253,7 +254,7 @@
253254
254255 debug("Wrote %d blocks, expected to write %d blocks\n",
255256 total_blocks, sparse_header->total_blks);
256
- printf("........ wrote %u bytes to '%s'\n", bytes_written, part_name);
257
+ printf("........ wrote %llu bytes to '%s'\n", bytes_written, part_name);
257258
258259 if (total_blocks != sparse_header->total_blks)
259260 fastboot_fail("sparse image write failure", response);
u-boot/common/mp_boot_rk3528.S
....@@ -0,0 +1,9682 @@
1
+ .arch armv8-a+nosimd
2
+ .file "mp_boot.c"
3
+ .text
4
+.Ltext0:
5
+ .cfi_sections .debug_frame
6
+ .section .text.mpb_task_set_state,"ax",@progbits
7
+ .align 2
8
+ .type mpb_task_set_state, %function
9
+mpb_task_set_state:
10
+.LFB225:
11
+ .file 1 "common/mp_boot.c"
12
+ .loc 1 227 0
13
+ .cfi_startproc
14
+.LVL0:
15
+.LBB30:
16
+.LBB31:
17
+ .loc 1 146 0
18
+ mov x4, 136314880
19
+ mov w3, 1
20
+ lsl w3, w3, w1
21
+ ldr w5, [x4]
22
+.LBE31:
23
+.LBE30:
24
+ .loc 1 232 0
25
+ tst w3, w5
26
+ beq .L11
27
+.LBB32:
28
+.LBB33:
29
+ .loc 1 199 0
30
+ uxtw x5, w0
31
+ mov x3, 328
32
+ umull x0, w0, w3
33
+.LVL1:
34
+ madd x4, x5, x3, x4
35
+ mov w3, 0
36
+ ldrb w6, [x4, 328]
37
+ mov x4, 20
38
+ movk x4, 0x820, lsl 16
39
+ add x4, x0, x4
40
+.L3:
41
+.LVL2:
42
+ cmp w3, w6
43
+ blt .L5
44
+.LVL3:
45
+.L11:
46
+.LBE33:
47
+.LBE32:
48
+ .loc 1 252 0
49
+ mov w0, 0
50
+ ret
51
+.LVL4:
52
+.L5:
53
+.LBB35:
54
+.LBB34:
55
+ .loc 1 200 0
56
+ ldr w7, [x4], 40
57
+ cmp w1, w7
58
+ beq .L4
59
+ .loc 1 199 0
60
+ add w3, w3, 1
61
+.LVL5:
62
+ b .L3
63
+.L4:
64
+.LVL6:
65
+.LBE34:
66
+.LBE35:
67
+ .loc 1 239 0
68
+ mov x8, 328
69
+ sxtw x4, w3
70
+ mov x7, 40
71
+ .loc 1 240 0
72
+ add x0, x0, 16
73
+ .loc 1 239 0
74
+ mul x5, x5, x8
75
+ .loc 1 227 0
76
+ stp x29, x30, [sp, -16]!
77
+ .cfi_def_cfa_offset 16
78
+ .cfi_offset 29, -16
79
+ .cfi_offset 30, -8
80
+ .loc 1 239 0
81
+ nop // between mem op and mult-accumulate
82
+ madd x4, x4, x7, x5
83
+ mov x6, 136314880
84
+ .loc 1 240 0
85
+ smaddl x3, w3, w7, x0
86
+ .loc 1 227 0
87
+ add x29, sp, 0
88
+ .cfi_def_cfa_register 29
89
+ .loc 1 239 0
90
+ add x4, x6, x4
91
+ .loc 1 227 0
92
+ .loc 1 239 0
93
+ add w1, w1, w2
94
+.LVL7:
95
+ .loc 1 240 0
96
+ add x0, x3, x6
97
+ .loc 1 239 0
98
+ str w1, [x4, 16]
99
+ .loc 1 241 0
100
+ add x1, x0, 4
101
+ bl flush_dcache_range
102
+.LVL8:
103
+ .loc 1 252 0
104
+ mov w0, 0
105
+ ldp x29, x30, [sp], 16
106
+ .cfi_restore 30
107
+ .cfi_restore 29
108
+ .cfi_def_cfa 31, 0
109
+ ret
110
+ .cfi_endproc
111
+.LFE225:
112
+ .size mpb_task_set_state, .-mpb_task_set_state
113
+ .section .text.mpb_quit_load_image,"ax",@progbits
114
+ .align 2
115
+ .type mpb_quit_load_image, %function
116
+mpb_quit_load_image:
117
+.LFB238:
118
+ .loc 1 560 0
119
+ .cfi_startproc
120
+ stp x29, x30, [sp, -32]!
121
+ .cfi_def_cfa_offset 32
122
+ .cfi_offset 29, -32
123
+ .cfi_offset 30, -24
124
+ add x29, sp, 0
125
+ .cfi_def_cfa_register 29
126
+ str x19, [sp, 16]
127
+ .cfi_offset 19, -16
128
+ .loc 1 563 0
129
+ bl rockchip_get_boot_mode
130
+.LVL9:
131
+ cmp w0, 1
132
+ bne .L15
133
+ mov w19, w0
134
+.LBB38:
135
+.LBB39:
136
+ .loc 1 564 0
137
+ adrp x0, .LANCHOR0
138
+ ldr w1, [x0, #:lo12:.LANCHOR0]
139
+ cbnz w1, .L13
140
+ .loc 1 565 0
141
+ str w19, [x0, #:lo12:.LANCHOR0]
142
+ .loc 1 566 0
143
+ adrp x0, .LC1
144
+ add x0, x0, :lo12:.LC1
145
+ bl printf
146
+.LVL10:
147
+.L13:
148
+.LBE39:
149
+.LBE38:
150
+ .loc 1 573 0
151
+ mov w0, w19
152
+ ldr x19, [sp, 16]
153
+ ldp x29, x30, [sp], 32
154
+ .cfi_remember_state
155
+ .cfi_restore 30
156
+ .cfi_restore 29
157
+ .cfi_restore 19
158
+ .cfi_def_cfa 31, 0
159
+ ret
160
+.L15:
161
+ .cfi_restore_state
162
+ .loc 1 572 0
163
+ mov w19, 0
164
+ b .L13
165
+ .cfi_endproc
166
+.LFE238:
167
+ .size mpb_quit_load_image, .-mpb_quit_load_image
168
+ .section .text.spl_init_display,"ax",@progbits
169
+ .align 2
170
+ .weak spl_init_display
171
+ .type spl_init_display, %function
172
+spl_init_display:
173
+.LFB252:
174
+ .cfi_startproc
175
+ mov w0, 0
176
+ ret
177
+ .cfi_endproc
178
+.LFE252:
179
+ .size spl_init_display, .-spl_init_display
180
+ .section .text.spl_load_baseparamter,"ax",@progbits
181
+ .align 2
182
+ .weak spl_load_baseparamter
183
+ .type spl_load_baseparamter, %function
184
+spl_load_baseparamter:
185
+.LFB250:
186
+ .cfi_startproc
187
+ mov w0, 0
188
+ ret
189
+ .cfi_endproc
190
+.LFE250:
191
+ .size spl_load_baseparamter, .-spl_load_baseparamter
192
+ .section .text.spl_load_fit,"ax",@progbits
193
+ .align 2
194
+ .weak spl_load_fit
195
+ .type spl_load_fit, %function
196
+spl_load_fit:
197
+.LFB248:
198
+ .cfi_startproc
199
+ mov w0, 0
200
+ ret
201
+ .cfi_endproc
202
+.LFE248:
203
+ .size spl_load_fit, .-spl_load_fit
204
+ .section .text.spl_load_android,"ax",@progbits
205
+ .align 2
206
+ .weak spl_load_android
207
+ .type spl_load_android, %function
208
+spl_load_android:
209
+.LFB246:
210
+ .cfi_startproc
211
+ mov w0, 0
212
+ ret
213
+ .cfi_endproc
214
+.LFE246:
215
+ .size spl_load_android, .-spl_load_android
216
+ .section .text.spl_hash_android,"ax",@progbits
217
+ .align 2
218
+ .weak spl_hash_android
219
+ .type spl_hash_android, %function
220
+spl_hash_android:
221
+.LFB244:
222
+ .cfi_startproc
223
+ mov w0, 0
224
+ ret
225
+ .cfi_endproc
226
+.LFE244:
227
+ .size spl_hash_android, .-spl_hash_android
228
+ .section .text.spl_dummy,"ax",@progbits
229
+ .align 2
230
+ .weak spl_dummy
231
+ .type spl_dummy, %function
232
+spl_dummy:
233
+.LFB218:
234
+ .loc 1 52 0
235
+ .cfi_startproc
236
+.LVL11:
237
+ .loc 1 52 0
238
+ mov w0, 0
239
+.LVL12:
240
+ ret
241
+ .cfi_endproc
242
+.LFE218:
243
+ .size spl_dummy, .-spl_dummy
244
+ .section .text.mpb_task_is_done,"ax",@progbits
245
+ .align 2
246
+ .global mpb_task_is_done
247
+ .type mpb_task_is_done, %function
248
+mpb_task_is_done:
249
+.LFB226:
250
+ .loc 1 261 0
251
+ .cfi_startproc
252
+.LVL13:
253
+.LBB40:
254
+.LBB41:
255
+ .loc 1 146 0
256
+ mov x2, 136314880
257
+ mov w1, 1
258
+ lsl w1, w1, w0
259
+ ldr w2, [x2]
260
+.LBE41:
261
+.LBE40:
262
+ .loc 1 265 0
263
+ tst w1, w2
264
+ beq .L39
265
+ .loc 1 261 0
266
+ stp x29, x30, [sp, -96]!
267
+ .cfi_def_cfa_offset 96
268
+ .cfi_offset 29, -96
269
+ .cfi_offset 30, -88
270
+ add x29, sp, 0
271
+ .cfi_def_cfa_register 29
272
+ stp x19, x20, [sp, 16]
273
+ .cfi_offset 19, -80
274
+ .cfi_offset 20, -72
275
+ mov w19, w0
276
+ stp x23, x24, [sp, 48]
277
+ .cfi_offset 23, -48
278
+ .cfi_offset 24, -40
279
+ .loc 1 275 0
280
+ mov w24, -559087616
281
+ .loc 1 261 0
282
+ str x27, [sp, 80]
283
+ .loc 1 275 0
284
+ add w24, w0, w24
285
+ .cfi_offset 27, -16
286
+ .loc 1 277 0
287
+ sub w27, w0, #65536
288
+ .loc 1 261 0
289
+ stp x21, x22, [sp, 32]
290
+ stp x25, x26, [sp, 64]
291
+ .cfi_offset 21, -64
292
+ .cfi_offset 22, -56
293
+ .cfi_offset 25, -32
294
+ .cfi_offset 26, -24
295
+ mov x21, 0
296
+.LVL14:
297
+.L31:
298
+ mov x22, 16
299
+ mov x20, 20
300
+ .loc 1 269 0
301
+ mov x26, 328
302
+ movk x22, 0x820, lsl 16
303
+ movk x20, 0x820, lsl 16
304
+ add x22, x21, x22
305
+ add x20, x21, x20
306
+ .loc 1 261 0
307
+ mov w23, 0
308
+ .loc 1 269 0
309
+ movk x26, 0x820, lsl 16
310
+ .loc 1 279 0
311
+ mov w25, 1431655765
312
+ b .L27
313
+.LVL15:
314
+.L30:
315
+ .loc 1 270 0
316
+ ldr w0, [x20]
317
+ cmp w19, w0
318
+ beq .L26
319
+.L29:
320
+ .loc 1 269 0
321
+ add w23, w23, 1
322
+.LVL16:
323
+ add x22, x22, 40
324
+ add x20, x20, 40
325
+.LVL17:
326
+.L27:
327
+ .loc 1 269 0 is_stmt 0 discriminator 1
328
+ ldrb w0, [x21, x26]
329
+ cmp w23, w0
330
+ blt .L30
331
+.LVL18:
332
+ add x21, x21, 328
333
+ .loc 1 268 0 is_stmt 1 discriminator 2
334
+ cmp x21, 1312
335
+ bne .L31
336
+ .loc 1 286 0
337
+ mov w0, 0
338
+.L23:
339
+ .loc 1 287 0
340
+ ldp x19, x20, [sp, 16]
341
+.LVL19:
342
+ ldp x21, x22, [sp, 32]
343
+ ldp x23, x24, [sp, 48]
344
+.LVL20:
345
+ ldp x25, x26, [sp, 64]
346
+ ldr x27, [sp, 80]
347
+.LVL21:
348
+ ldp x29, x30, [sp], 96
349
+ .cfi_remember_state
350
+ .cfi_restore 30
351
+ .cfi_restore 29
352
+ .cfi_restore 27
353
+ .cfi_restore 25
354
+ .cfi_restore 26
355
+ .cfi_restore 23
356
+ .cfi_restore 24
357
+ .cfi_restore 21
358
+ .cfi_restore 22
359
+ .cfi_restore 19
360
+ .cfi_restore 20
361
+ .cfi_def_cfa 31, 0
362
+ ret
363
+.LVL22:
364
+.L26:
365
+ .cfi_restore_state
366
+ .loc 1 272 0
367
+ mov x0, x22
368
+ mov x1, x20
369
+ bl invalidate_dcache_range
370
+.LVL23:
371
+ .loc 1 275 0
372
+ ldr w0, [x22]
373
+ cmp w0, w24
374
+ beq .L32
375
+ .loc 1 277 0
376
+ cmp w0, w27
377
+ beq .L24
378
+ .loc 1 279 0
379
+ add w1, w19, w25
380
+ cmp w0, w1
381
+ bne .L29
382
+ .loc 1 280 0
383
+ mov w0, -2
384
+ b .L23
385
+.L24:
386
+ .loc 1 266 0
387
+ mov w0, -1
388
+ b .L23
389
+.L32:
390
+ .loc 1 276 0
391
+ mov w0, 1
392
+ b .L23
393
+.LVL24:
394
+.L39:
395
+ .cfi_def_cfa 31, 0
396
+ .cfi_restore 19
397
+ .cfi_restore 20
398
+ .cfi_restore 21
399
+ .cfi_restore 22
400
+ .cfi_restore 23
401
+ .cfi_restore 24
402
+ .cfi_restore 25
403
+ .cfi_restore 26
404
+ .cfi_restore 27
405
+ .cfi_restore 29
406
+ .cfi_restore 30
407
+ .loc 1 266 0
408
+ mov w0, -1
409
+.LVL25:
410
+ .loc 1 287 0
411
+ ret
412
+ .cfi_endproc
413
+.LFE226:
414
+ .size mpb_task_is_done, .-mpb_task_is_done
415
+ .section .text.mpb_task_dump,"ax",@progbits
416
+ .align 2
417
+ .global mpb_task_dump
418
+ .type mpb_task_dump, %function
419
+mpb_task_dump:
420
+.LFB227:
421
+ .loc 1 290 0
422
+ .cfi_startproc
423
+ stp x29, x30, [sp, -80]!
424
+ .cfi_def_cfa_offset 80
425
+ .cfi_offset 29, -80
426
+ .cfi_offset 30, -72
427
+ .loc 1 294 0
428
+ mov x0, 136314880
429
+ .loc 1 290 0
430
+ add x29, sp, 0
431
+ .cfi_def_cfa_register 29
432
+ .loc 1 294 0
433
+ ldr x1, [x0, 1360]
434
+ ldr x2, [x0, 1368]
435
+ adrp x0, .LC2
436
+ .loc 1 290 0
437
+ stp x19, x20, [sp, 16]
438
+ .cfi_offset 19, -64
439
+ .cfi_offset 20, -56
440
+ .loc 1 294 0
441
+ mov x20, 20
442
+ .loc 1 290 0
443
+ stp x23, x24, [sp, 48]
444
+ .loc 1 294 0
445
+ movk x20, 0x820, lsl 16
446
+ .loc 1 290 0
447
+ stp x21, x22, [sp, 32]
448
+ .cfi_offset 23, -32
449
+ .cfi_offset 24, -24
450
+ .cfi_offset 21, -48
451
+ .cfi_offset 22, -40
452
+ .loc 1 299 0
453
+ adrp x23, .LANCHOR1
454
+ adrp x24, .LC3
455
+ .loc 1 296 0
456
+ mov w21, 0
457
+ .loc 1 299 0
458
+ add x23, x23, :lo12:.LANCHOR1
459
+ add x24, x24, :lo12:.LC3
460
+ .loc 1 294 0
461
+ add x0, x0, :lo12:.LC2
462
+ .loc 1 290 0
463
+ str x25, [sp, 64]
464
+ .cfi_offset 25, -16
465
+ .loc 1 294 0
466
+ bl printf
467
+.LVL26:
468
+.L43:
469
+ .loc 1 290 0
470
+ mov x19, x20
471
+ mov w22, 0
472
+ .loc 1 300 0
473
+ adrp x25, .LC4
474
+ b .L46
475
+.LVL27:
476
+.L44:
477
+ .loc 1 299 0 discriminator 3
478
+ ldr w2, [x19]
479
+ mov w1, w21
480
+ mov x0, x24
481
+ .loc 1 297 0 discriminator 3
482
+ add w22, w22, 1
483
+.LVL28:
484
+ add x19, x19, 40
485
+ .loc 1 299 0 discriminator 3
486
+ ldr x3, [x23, w2, uxtw 3]
487
+ bl printf
488
+.LVL29:
489
+ .loc 1 300 0 discriminator 3
490
+ ldr w1, [x19, -40]
491
+ add x0, x25, :lo12:.LC4
492
+ bl printf
493
+.LVL30:
494
+ .loc 1 301 0 discriminator 3
495
+ ldr x1, [x19, -52]
496
+ adrp x0, .LC5
497
+ add x0, x0, :lo12:.LC5
498
+ bl printf
499
+.LVL31:
500
+ .loc 1 302 0 discriminator 3
501
+ ldr w1, [x19, -44]
502
+ adrp x0, .LC6
503
+ add x0, x0, :lo12:.LC6
504
+ bl printf
505
+.LVL32:
506
+ .loc 1 303 0 discriminator 3
507
+ ldr w1, [x19, -28]
508
+ adrp x0, .LC7
509
+ add x0, x0, :lo12:.LC7
510
+ bl printf
511
+.LVL33:
512
+ .loc 1 304 0 discriminator 3
513
+ ldr x1, [x19, -20]
514
+ adrp x0, .LC8
515
+ add x0, x0, :lo12:.LC8
516
+ bl printf
517
+.LVL34:
518
+ .loc 1 305 0 discriminator 3
519
+ ldr w1, [x19, -36]
520
+ adrp x0, .LC9
521
+ add x0, x0, :lo12:.LC9
522
+ bl printf
523
+.LVL35:
524
+ .loc 1 306 0 discriminator 3
525
+ ldr w1, [x19, -32]
526
+ adrp x0, .LC10
527
+ add x0, x0, :lo12:.LC10
528
+ bl printf
529
+.LVL36:
530
+.L46:
531
+ .loc 1 297 0 discriminator 1
532
+ ldrb w0, [x20, 308]
533
+ cmp w22, w0
534
+ blt .L44
535
+ .loc 1 296 0 discriminator 2
536
+ add w21, w21, 1
537
+.LVL37:
538
+ add x20, x20, 328
539
+ cmp w21, 4
540
+ bne .L43
541
+ .loc 1 310 0
542
+ ldp x19, x20, [sp, 16]
543
+ ldp x21, x22, [sp, 32]
544
+.LVL38:
545
+ ldp x23, x24, [sp, 48]
546
+ ldr x25, [sp, 64]
547
+ ldp x29, x30, [sp], 80
548
+ .cfi_restore 30
549
+ .cfi_restore 29
550
+ .cfi_restore 25
551
+ .cfi_restore 23
552
+ .cfi_restore 24
553
+ .cfi_restore 21
554
+ .cfi_restore 22
555
+ .cfi_restore 19
556
+ .cfi_restore 20
557
+ .cfi_def_cfa 31, 0
558
+ ret
559
+ .cfi_endproc
560
+.LFE227:
561
+ .size mpb_task_dump, .-mpb_task_dump
562
+ .section .text.core_task_run.part.2,"ax",@progbits
563
+ .align 2
564
+ .type core_task_run.part.2, %function
565
+core_task_run.part.2:
566
+.LFB242:
567
+ .loc 1 370 0
568
+ .cfi_startproc
569
+.LVL39:
570
+ stp x29, x30, [sp, -80]!
571
+ .cfi_def_cfa_offset 80
572
+ .cfi_offset 29, -80
573
+ .cfi_offset 30, -72
574
+ add x29, sp, 0
575
+ .cfi_def_cfa_register 29
576
+ stp x19, x20, [sp, 16]
577
+ .cfi_offset 19, -64
578
+ .cfi_offset 20, -56
579
+ mov w19, w0
580
+ stp x21, x22, [sp, 32]
581
+ mov w20, w2
582
+.LVL40:
583
+ stp x23, x24, [sp, 48]
584
+ .cfi_offset 21, -48
585
+ .cfi_offset 22, -40
586
+ .cfi_offset 23, -32
587
+ .cfi_offset 24, -24
588
+ and x22, x1, 255
589
+ stp x25, x26, [sp, 64]
590
+ .cfi_offset 25, -16
591
+ .cfi_offset 26, -8
592
+.LBB52:
593
+.LBB53:
594
+ .loc 1 319 0
595
+ cbz w3, .L49
596
+ mov w25, w3
597
+ mov w23, 0
598
+ mov w21, 0
599
+ .loc 1 324 0
600
+ mov w26, 1
601
+.LVL41:
602
+.L54:
603
+ lsl w0, w26, w21
604
+ tst w0, w25
605
+ beq .L50
606
+.L51:
607
+ .loc 1 319 0
608
+ mov w24, 20000
609
+.L52:
610
+.LVL42:
611
+ .loc 1 329 0
612
+ mov w0, w21
613
+ bl mpb_task_is_done
614
+.LVL43:
615
+ cbz w0, .L53
616
+ .loc 1 344 0
617
+ mov w0, w21
618
+ bl mpb_task_is_done
619
+.LVL44:
620
+ .loc 1 345 0
621
+ cmp w0, 0
622
+ cinc w23, w23, lt
623
+.LVL45:
624
+.L50:
625
+ .loc 1 323 0
626
+ add w21, w21, 1
627
+.LVL46:
628
+ cmp w21, 8
629
+ bne .L54
630
+.LVL47:
631
+.LBE53:
632
+.LBE52:
633
+ .loc 1 387 0
634
+ cbz w23, .L49
635
+.LVL48:
636
+ .loc 1 389 0
637
+ uxtw x1, w19
638
+ mov x2, 328
639
+ sxtw x0, w22
640
+ mul x1, x1, x2
641
+ mov x2, 40
642
+ madd x0, x0, x2, x1
643
+ mov x1, 136314880
644
+ add x0, x1, x0
645
+ ldr w0, [x0, 28]
646
+ cbnz w0, .L55
647
+.LVL49:
648
+.L56:
649
+ .loc 1 410 0
650
+ mov w2, w20
651
+ mov w1, w19
652
+ adrp x0, .LC12
653
+ add x0, x0, :lo12:.LC12
654
+ bl printf
655
+.LVL50:
656
+ .loc 1 374 0
657
+ mov w21, 0
658
+ .loc 1 411 0
659
+ mov w2, 1431655765
660
+ mov w1, w20
661
+ mov w0, w19
662
+ bl mpb_task_set_state
663
+.LVL51:
664
+ b .L62
665
+.LVL52:
666
+.L53:
667
+.LBB55:
668
+.LBB54:
669
+ .loc 1 330 0
670
+ mov x0, 100
671
+ bl udelay
672
+.LVL53:
673
+ .loc 1 333 0
674
+ subs w24, w24, #1
675
+.LVL54:
676
+ bne .L52
677
+.LVL55:
678
+ .loc 1 337 0
679
+ bl mpb_task_dump
680
+.LVL56:
681
+ b .L51
682
+.LVL57:
683
+.L49:
684
+.LBE54:
685
+.LBE55:
686
+ .loc 1 392 0
687
+ uxtw x1, w19
688
+ mov x2, 328
689
+ sxtw x0, w22
690
+ mul x1, x1, x2
691
+ mov x2, 40
692
+ madd x0, x0, x2, x1
693
+ mov x1, 136314880
694
+ add x0, x1, x0
695
+ ldr w0, [x0, 28]
696
+ cbnz w0, .L56
697
+.L55:
698
+.LVL58:
699
+ .loc 1 397 0
700
+ mov w2, w20
701
+ mov w1, w19
702
+ adrp x0, .LC13
703
+ add x0, x0, :lo12:.LC13
704
+ bl printf
705
+.LVL59:
706
+ .loc 1 401 0
707
+ uxtw x24, w19
708
+ .loc 1 398 0
709
+ bl get_ticks
710
+.LVL60:
711
+ mov x23, x0
712
+.LVL61:
713
+ .loc 1 400 0
714
+ mov w2, 286331153
715
+ mov w1, w20
716
+ mov w0, w19
717
+.LVL62:
718
+ bl mpb_task_set_state
719
+.LVL63:
720
+ .loc 1 401 0
721
+ mov x1, 328
722
+ mov x0, 40
723
+ mul x1, x24, x1
724
+ madd x1, x22, x0, x1
725
+ mov x0, 8
726
+ movk x0, 0x820, lsl 16
727
+ ldr x1, [x0, x1]
728
+ mov x0, 1320
729
+ movk x0, 0x820, lsl 16
730
+ blr x1
731
+.LVL64:
732
+ mov w21, w0
733
+.LVL65:
734
+ .loc 1 402 0
735
+ cbnz w0, .L63
736
+ .loc 1 405 0
737
+ mov w2, -559087616
738
+ b .L81
739
+.L63:
740
+ .loc 1 403 0
741
+ mov w2, -65536
742
+.L81:
743
+ .loc 1 405 0
744
+ mov w1, w20
745
+ mov w0, w19
746
+.LVL66:
747
+ bl mpb_task_set_state
748
+.LVL67:
749
+ .loc 1 407 0
750
+ bl get_ticks
751
+.LVL68:
752
+ sub x0, x0, x23
753
+ mov x4, 24000
754
+ .loc 1 408 0
755
+ mov w3, w21
756
+ mov w2, w20
757
+ mov w1, w19
758
+ .loc 1 407 0
759
+ udiv x4, x0, x4
760
+ mov x0, 328
761
+ mul x0, x24, x0
762
+ mov x24, 40
763
+ madd x24, x22, x24, x0
764
+ mov x22, 40
765
+.LVL69:
766
+ movk x22, 0x820, lsl 16
767
+ .loc 1 408 0
768
+ adrp x0, .LC11
769
+ add x0, x0, :lo12:.LC11
770
+ .loc 1 407 0
771
+ str x4, [x22, x24]
772
+ .loc 1 408 0
773
+ bl printf
774
+.LVL70:
775
+.L62:
776
+.LBB56:
777
+.LBB57:
778
+.LBB58:
779
+.LBB59:
780
+ .loc 1 146 0
781
+ mov x0, 136314880
782
+ mov w1, 1
783
+ lsl w1, w1, w20
784
+ ldr w2, [x0]
785
+.LBE59:
786
+.LBE58:
787
+ .loc 1 212 0
788
+ tst w1, w2
789
+ beq .L48
790
+.LBB60:
791
+.LBB61:
792
+ .loc 1 199 0
793
+ uxtw x3, w19
794
+ mov x1, 328
795
+ umull x19, w19, w1
796
+.LVL71:
797
+ madd x0, x3, x1, x0
798
+ mov w1, 0
799
+ ldrb w2, [x0, 328]
800
+ mov x0, 20
801
+ movk x0, 0x820, lsl 16
802
+ add x0, x19, x0
803
+.L59:
804
+.LVL72:
805
+ cmp w1, w2
806
+ blt .L61
807
+.LVL73:
808
+.L48:
809
+.LBE61:
810
+.LBE60:
811
+.LBE57:
812
+.LBE56:
813
+ .loc 1 417 0
814
+ ldp x19, x20, [sp, 16]
815
+.LVL74:
816
+ ldp x21, x22, [sp, 32]
817
+.LVL75:
818
+ ldp x23, x24, [sp, 48]
819
+ ldp x25, x26, [sp, 64]
820
+ ldp x29, x30, [sp], 80
821
+ .cfi_remember_state
822
+ .cfi_restore 30
823
+ .cfi_restore 29
824
+ .cfi_restore 25
825
+ .cfi_restore 26
826
+ .cfi_restore 23
827
+ .cfi_restore 24
828
+ .cfi_restore 21
829
+ .cfi_restore 22
830
+ .cfi_restore 19
831
+ .cfi_restore 20
832
+ .cfi_def_cfa 31, 0
833
+ ret
834
+.LVL76:
835
+.L61:
836
+ .cfi_restore_state
837
+.LBB69:
838
+.LBB64:
839
+.LBB63:
840
+.LBB62:
841
+ .loc 1 200 0
842
+ ldr w4, [x0], 40
843
+ cmp w20, w4
844
+ beq .L60
845
+ .loc 1 199 0
846
+ add w1, w1, 1
847
+.LVL77:
848
+ b .L59
849
+.L60:
850
+.LVL78:
851
+.LBE62:
852
+.LBE63:
853
+ .loc 1 219 0
854
+ sxtw x2, w1
855
+ mov x5, 328
856
+ mov x4, 40
857
+ .loc 1 220 0
858
+ add x19, x19, 32
859
+ .loc 1 219 0
860
+ mul x3, x3, x5
861
+ mov x0, 136314880
862
+ madd x2, x2, x4, x3
863
+ .loc 1 220 0
864
+ smaddl x19, w1, w4, x19
865
+ .loc 1 219 0
866
+ add x2, x0, x2
867
+.LBE64:
868
+.LBE69:
869
+ .loc 1 417 0
870
+ ldp x23, x24, [sp, 48]
871
+.LBB70:
872
+.LBB65:
873
+ .loc 1 220 0
874
+ add x0, x19, x0
875
+.LBE65:
876
+.LBE70:
877
+ .loc 1 417 0
878
+ ldp x25, x26, [sp, 64]
879
+.LBB71:
880
+.LBB66:
881
+ .loc 1 221 0
882
+ add x1, x0, 4
883
+.LBE66:
884
+.LBE71:
885
+ .loc 1 417 0
886
+ ldp x19, x20, [sp, 16]
887
+.LVL79:
888
+.LBB72:
889
+.LBB67:
890
+ .loc 1 219 0
891
+ str w21, [x2, 32]
892
+.LBE67:
893
+.LBE72:
894
+ .loc 1 417 0
895
+ ldp x21, x22, [sp, 32]
896
+.LVL80:
897
+ ldp x29, x30, [sp], 80
898
+ .cfi_restore 30
899
+ .cfi_restore 29
900
+ .cfi_restore 25
901
+ .cfi_restore 26
902
+ .cfi_restore 23
903
+ .cfi_restore 24
904
+ .cfi_restore 21
905
+ .cfi_restore 22
906
+ .cfi_restore 19
907
+ .cfi_restore 20
908
+ .cfi_def_cfa 31, 0
909
+.LBB73:
910
+.LBB68:
911
+ .loc 1 221 0
912
+ b flush_dcache_range
913
+.LVL81:
914
+.LBE68:
915
+.LBE73:
916
+ .cfi_endproc
917
+.LFE242:
918
+ .size core_task_run.part.2, .-core_task_run.part.2
919
+ .section .text.mpb_task_wait_done,"ax",@progbits
920
+ .align 2
921
+ .global mpb_task_wait_done
922
+ .type mpb_task_wait_done, %function
923
+mpb_task_wait_done:
924
+.LFB230:
925
+ .loc 1 366 0
926
+ .cfi_startproc
927
+.LVL82:
928
+ stp x29, x30, [sp, -32]!
929
+ .cfi_def_cfa_offset 32
930
+ .cfi_offset 29, -32
931
+ .cfi_offset 30, -24
932
+ add x29, sp, 0
933
+ .cfi_def_cfa_register 29
934
+ str x19, [sp, 16]
935
+ .cfi_offset 19, -16
936
+ mov w19, w0
937
+.LVL83:
938
+.L84:
939
+.LBB78:
940
+.LBB79:
941
+ .loc 1 355 0
942
+ mov w0, w19
943
+ bl mpb_task_is_done
944
+.LVL84:
945
+ cbnz w0, .L83
946
+.LVL85:
947
+.LBB80:
948
+.LBB81:
949
+ .file 2 "include/linux/delay.h"
950
+ .loc 2 16 0
951
+ mov x0, 1000
952
+ bl udelay
953
+.LVL86:
954
+ mov x0, 1000
955
+ bl udelay
956
+.LVL87:
957
+ b .L84
958
+.L83:
959
+.LBE81:
960
+.LBE80:
961
+ .loc 1 362 0
962
+ mov w0, w19
963
+.LBE79:
964
+.LBE78:
965
+ .loc 1 368 0
966
+ ldr x19, [sp, 16]
967
+.LVL88:
968
+ ldp x29, x30, [sp], 32
969
+ .cfi_restore 30
970
+ .cfi_restore 29
971
+ .cfi_restore 19
972
+ .cfi_def_cfa 31, 0
973
+.LBB83:
974
+.LBB82:
975
+ .loc 1 362 0
976
+ b mpb_task_is_done
977
+.LVL89:
978
+.LBE82:
979
+.LBE83:
980
+ .cfi_endproc
981
+.LFE230:
982
+ .size mpb_task_wait_done, .-mpb_task_wait_done
983
+ .section .text.mpb_task_run,"ax",@progbits
984
+ .align 2
985
+ .global mpb_task_run
986
+ .type mpb_task_run, %function
987
+mpb_task_run:
988
+.LFB232:
989
+ .loc 1 420 0
990
+ .cfi_startproc
991
+.LVL90:
992
+ stp x29, x30, [sp, -80]!
993
+ .cfi_def_cfa_offset 80
994
+ .cfi_offset 29, -80
995
+ .cfi_offset 30, -72
996
+.LBB90:
997
+.LBB91:
998
+ .loc 1 146 0
999
+ mov x3, 136314880
1000
+.LBE91:
1001
+.LBE90:
1002
+ .loc 1 420 0
1003
+ add x29, sp, 0
1004
+ .cfi_def_cfa_register 29
1005
+ stp x23, x24, [sp, 48]
1006
+ .cfi_offset 23, -32
1007
+ .cfi_offset 24, -24
1008
+.LBB93:
1009
+.LBB92:
1010
+ .loc 1 146 0
1011
+ mov w24, 1
1012
+ ldr w2, [x3]
1013
+ lsl w24, w24, w1
1014
+.LVL91:
1015
+.LBE92:
1016
+.LBE93:
1017
+ .loc 1 420 0
1018
+ stp x19, x20, [sp, 16]
1019
+ stp x21, x22, [sp, 32]
1020
+ .loc 1 424 0
1021
+ tst w24, w2
1022
+ .loc 1 420 0
1023
+ str x25, [sp, 64]
1024
+ .cfi_offset 19, -64
1025
+ .cfi_offset 20, -56
1026
+ .cfi_offset 21, -48
1027
+ .cfi_offset 22, -40
1028
+ .cfi_offset 25, -16
1029
+ .loc 1 424 0
1030
+ beq .L86
1031
+ .loc 1 424 0 is_stmt 0 discriminator 1
1032
+ cbz w1, .L86
1033
+ uxtw x25, w0
1034
+.LVL92:
1035
+ .loc 1 421 0 is_stmt 1
1036
+ mov w19, 328
1037
+ mov x0, 8
1038
+.LVL93:
1039
+ mov x22, x25
1040
+ mov w21, w1
1041
+ .loc 1 427 0
1042
+ mov x20, x3
1043
+ .loc 1 421 0
1044
+ umaddl x19, w25, w19, x0
1045
+ .loc 1 427 0
1046
+ mov x0, 328
1047
+ .loc 1 421 0
1048
+ mov w23, 0
1049
+ .loc 1 427 0
1050
+ madd x25, x25, x0, x3
1051
+.LVL94:
1052
+ .loc 1 421 0
1053
+ add x19, x19, x3
1054
+.LVL95:
1055
+.L89:
1056
+ .loc 1 427 0 discriminator 1
1057
+ ldrb w0, [x25, 328]
1058
+ cmp w23, w0
1059
+ blt .L91
1060
+.LVL96:
1061
+.L86:
1062
+ .loc 1 431 0
1063
+ ldp x19, x20, [sp, 16]
1064
+ ldp x21, x22, [sp, 32]
1065
+ ldp x23, x24, [sp, 48]
1066
+ ldr x25, [sp, 64]
1067
+ ldp x29, x30, [sp], 80
1068
+ .cfi_remember_state
1069
+ .cfi_restore 30
1070
+ .cfi_restore 29
1071
+ .cfi_restore 25
1072
+ .cfi_restore 23
1073
+ .cfi_restore 24
1074
+ .cfi_restore 21
1075
+ .cfi_restore 22
1076
+ .cfi_restore 19
1077
+ .cfi_restore 20
1078
+ .cfi_def_cfa 31, 0
1079
+ ret
1080
+.LVL97:
1081
+.L91:
1082
+ .cfi_restore_state
1083
+ .loc 1 428 0
1084
+ ldr w0, [x19, 12]
1085
+ cmp w21, w0
1086
+ bne .L90
1087
+ .loc 1 428 0 is_stmt 0 discriminator 1
1088
+ ldr x0, [x19]
1089
+ cbz x0, .L90
1090
+.LVL98:
1091
+.LBB94:
1092
+.LBB95:
1093
+.LBB96:
1094
+.LBB97:
1095
+ .loc 1 146 0 is_stmt 1
1096
+ ldr w0, [x20]
1097
+.LBE97:
1098
+.LBE96:
1099
+ .loc 1 377 0
1100
+ tst w24, w0
1101
+ beq .L90
1102
+ ldr w3, [x19, 16]
1103
+ mov w2, w21
1104
+ mov w1, w23
1105
+ mov w0, w22
1106
+ bl core_task_run.part.2
1107
+.LVL99:
1108
+.L90:
1109
+.LBE95:
1110
+.LBE94:
1111
+ .loc 1 427 0 discriminator 2
1112
+ add w23, w23, 1
1113
+.LVL100:
1114
+ add x19, x19, 40
1115
+ b .L89
1116
+ .cfi_endproc
1117
+.LFE232:
1118
+ .size mpb_task_run, .-mpb_task_run
1119
+ .section .text.core_main,"ax",@progbits
1120
+ .align 2
1121
+ .global core_main
1122
+ .type core_main, %function
1123
+core_main:
1124
+.LFB233:
1125
+ .loc 1 434 0
1126
+ .cfi_startproc
1127
+.LVL101:
1128
+ stp x29, x30, [sp, -64]!
1129
+ .cfi_def_cfa_offset 64
1130
+ .cfi_offset 29, -64
1131
+ .cfi_offset 30, -56
1132
+ add x29, sp, 0
1133
+ .cfi_def_cfa_register 29
1134
+ stp x21, x22, [sp, 32]
1135
+ .cfi_offset 21, -32
1136
+ .cfi_offset 22, -24
1137
+ uxtw x22, w0
1138
+ stp x19, x20, [sp, 16]
1139
+ .loc 1 435 0
1140
+ mov x0, 8
1141
+.LVL102:
1142
+ .cfi_offset 19, -48
1143
+ .cfi_offset 20, -40
1144
+ mov w19, 328
1145
+ mov x20, 136314880
1146
+ .loc 1 434 0
1147
+ stp x23, x24, [sp, 48]
1148
+ .cfi_offset 23, -16
1149
+ .cfi_offset 24, -8
1150
+ .loc 1 434 0
1151
+ mov x23, x22
1152
+.LVL103:
1153
+ .loc 1 435 0
1154
+ umaddl x19, w22, w19, x0
1155
+ .loc 1 438 0
1156
+ mov x0, 328
1157
+ mov w21, 0
1158
+.LBB102:
1159
+.LBB103:
1160
+.LBB104:
1161
+.LBB105:
1162
+ .loc 1 146 0
1163
+ mov w24, 1
1164
+.LBE105:
1165
+.LBE104:
1166
+.LBE103:
1167
+.LBE102:
1168
+ .loc 1 438 0
1169
+ madd x22, x22, x0, x20
1170
+.LVL104:
1171
+ .loc 1 435 0
1172
+ add x19, x19, x20
1173
+.LVL105:
1174
+.L103:
1175
+ .loc 1 438 0 discriminator 1
1176
+ ldrb w0, [x22, 328]
1177
+ cmp w21, w0
1178
+ blt .L105
1179
+ .loc 1 442 0
1180
+ ldp x19, x20, [sp, 16]
1181
+ ldp x21, x22, [sp, 32]
1182
+.LVL106:
1183
+ ldp x23, x24, [sp, 48]
1184
+.LVL107:
1185
+ ldp x29, x30, [sp], 64
1186
+ .cfi_remember_state
1187
+ .cfi_restore 30
1188
+ .cfi_restore 29
1189
+ .cfi_restore 23
1190
+ .cfi_restore 24
1191
+ .cfi_restore 21
1192
+ .cfi_restore 22
1193
+ .cfi_restore 19
1194
+ .cfi_restore 20
1195
+ .cfi_def_cfa 31, 0
1196
+ ret
1197
+.LVL108:
1198
+.L105:
1199
+ .cfi_restore_state
1200
+ .loc 1 439 0
1201
+ ldr x0, [x19]
1202
+ cbz x0, .L104
1203
+ .loc 1 440 0
1204
+ ldr w2, [x19, 12]
1205
+.LVL109:
1206
+.LBB109:
1207
+.LBB108:
1208
+.LBB107:
1209
+.LBB106:
1210
+ .loc 1 146 0
1211
+ ldr w0, [x20]
1212
+ lsl w1, w24, w2
1213
+.LBE106:
1214
+.LBE107:
1215
+ .loc 1 377 0
1216
+ tst w1, w0
1217
+ beq .L104
1218
+ ldr w3, [x19, 16]
1219
+ mov w1, w21
1220
+ mov w0, w23
1221
+ bl core_task_run.part.2
1222
+.LVL110:
1223
+.L104:
1224
+.LBE108:
1225
+.LBE109:
1226
+ .loc 1 438 0 discriminator 2
1227
+ add w21, w21, 1
1228
+.LVL111:
1229
+ add x19, x19, 40
1230
+ b .L103
1231
+ .cfi_endproc
1232
+.LFE233:
1233
+ .size core_main, .-core_main
1234
+ .section .text.smp_entry,"ax",@progbits
1235
+ .align 2
1236
+ .global smp_entry
1237
+ .type smp_entry, %function
1238
+smp_entry:
1239
+.LFB234:
1240
+ .loc 1 448 0
1241
+ .cfi_startproc
1242
+.LVL112:
1243
+ stp x29, x30, [sp, -32]!
1244
+ .cfi_def_cfa_offset 32
1245
+ .cfi_offset 29, -32
1246
+ .cfi_offset 30, -24
1247
+ add x29, sp, 0
1248
+ .cfi_def_cfa_register 29
1249
+ str x19, [sp, 16]
1250
+ .cfi_offset 19, -16
1251
+ .loc 1 448 0
1252
+ mov w19, w0
1253
+ .loc 1 450 0
1254
+ adrp x0, .LANCHOR2
1255
+.LVL113:
1256
+ ldr x0, [x0, #:lo12:.LANCHOR2]
1257
+.LVL114:
1258
+.LBB110:
1259
+.LBB111:
1260
+ .loc 1 131 0
1261
+#APP
1262
+// 131 "common/mp_boot.c" 1
1263
+ mov x18, x0
1264
+
1265
+// 0 "" 2
1266
+.LVL115:
1267
+#NO_APP
1268
+.LBE111:
1269
+.LBE110:
1270
+ .loc 1 451 0
1271
+ bl dcache_enable
1272
+.LVL116:
1273
+ .loc 1 455 0
1274
+ cmp w19, 1
1275
+ bne .L114
1276
+.L118:
1277
+ .loc 1 460 0
1278
+ mov w0, w19
1279
+ bl core_main
1280
+.LVL117:
1281
+ b .L115
1282
+.L114:
1283
+ .loc 1 459 0
1284
+ cmp w19, 2
1285
+ beq .L118
1286
+.L115:
1287
+ .loc 1 468 0
1288
+ bl flush_dcache_all
1289
+.LVL118:
1290
+ .loc 1 469 0
1291
+ bl disable_interrupts
1292
+.LVL119:
1293
+.LBB112:
1294
+.LBB113:
1295
+ .file 3 "./arch/arm/include/asm/system.h"
1296
+ .loc 3 193 0
1297
+#APP
1298
+// 193 "./arch/arm/include/asm/system.h" 1
1299
+ msr daifset, #0x04
1300
+// 0 "" 2
1301
+#NO_APP
1302
+.LBE113:
1303
+.LBE112:
1304
+ .loc 1 471 0
1305
+ bl icache_disable
1306
+.LVL120:
1307
+ .loc 1 472 0
1308
+ bl invalidate_icache_all
1309
+.LVL121:
1310
+ .loc 1 473 0
1311
+ bl dcache_disable
1312
+.LVL122:
1313
+.LBB114:
1314
+.LBB115:
1315
+ .loc 1 138 0
1316
+#APP
1317
+// 138 "common/mp_boot.c" 1
1318
+ mrs x0, S3_1_c15_c2_1
1319
+// 0 "" 2
1320
+ .loc 1 139 0
1321
+// 139 "common/mp_boot.c" 1
1322
+ bic x0, x0, #0x40
1323
+// 0 "" 2
1324
+ .loc 1 140 0
1325
+// 140 "common/mp_boot.c" 1
1326
+ msr S3_1_c15_c2_1, x0
1327
+// 0 "" 2
1328
+#NO_APP
1329
+.LBE115:
1330
+.LBE114:
1331
+ .loc 1 475 0
1332
+ bl invalidate_dcache_all
1333
+.LVL123:
1334
+ .loc 1 478 0
1335
+#APP
1336
+// 478 "common/mp_boot.c" 1
1337
+ dsb sy
1338
+// 0 "" 2
1339
+ .loc 1 479 0
1340
+// 479 "common/mp_boot.c" 1
1341
+ isb sy
1342
+// 0 "" 2
1343
+#NO_APP
1344
+.L116:
1345
+ .loc 1 481 0 discriminator 1
1346
+#APP
1347
+// 481 "common/mp_boot.c" 1
1348
+ wfe
1349
+// 0 "" 2
1350
+#NO_APP
1351
+ b .L116
1352
+ .cfi_endproc
1353
+.LFE234:
1354
+ .size smp_entry, .-smp_entry
1355
+ .section .text.mpb_init_1,"ax",@progbits
1356
+ .align 2
1357
+ .global mpb_init_1
1358
+ .type mpb_init_1, %function
1359
+mpb_init_1:
1360
+.LFB236:
1361
+ .loc 1 527 0
1362
+ .cfi_startproc
1363
+ stp x29, x30, [sp, -16]!
1364
+ .cfi_def_cfa_offset 16
1365
+ .cfi_offset 29, -16
1366
+ .cfi_offset 30, -8
1367
+ .loc 1 528 0
1368
+ mov x2, 40
1369
+ mov x1, x0
1370
+ mov x0, 1320
1371
+ .loc 1 527 0
1372
+ add x29, sp, 0
1373
+ .cfi_def_cfa_register 29
1374
+ .loc 1 528 0
1375
+ movk x0, 0x820, lsl 16
1376
+ .loc 1 527 0
1377
+ .loc 1 528 0
1378
+ bl memcpy
1379
+.LVL124:
1380
+ .loc 1 530 0
1381
+ mov w1, 2
1382
+ mov w0, 0
1383
+ bl mpb_task_run
1384
+.LVL125:
1385
+ .loc 1 531 0
1386
+ mov w2, 286331153
1387
+ mov w1, 3
1388
+ mov w0, 0
1389
+ bl mpb_task_set_state
1390
+.LVL126:
1391
+ .loc 1 532 0
1392
+ bl flush_dcache_all
1393
+.LVL127:
1394
+ .loc 1 533 0
1395
+#APP
1396
+// 533 "common/mp_boot.c" 1
1397
+ dsb sy
1398
+// 0 "" 2
1399
+ .loc 1 534 0
1400
+// 534 "common/mp_boot.c" 1
1401
+ isb sy
1402
+// 0 "" 2
1403
+ .loc 1 535 0
1404
+#NO_APP
1405
+ ldp x29, x30, [sp], 16
1406
+ .cfi_restore 30
1407
+ .cfi_restore 29
1408
+ .cfi_def_cfa 31, 0
1409
+ ret
1410
+ .cfi_endproc
1411
+.LFE236:
1412
+ .size mpb_init_1, .-mpb_init_1
1413
+ .section .text.mpb_init_x,"ax",@progbits
1414
+ .align 2
1415
+ .global mpb_init_x
1416
+ .type mpb_init_x, %function
1417
+mpb_init_x:
1418
+.LFB237:
1419
+ .loc 1 538 0
1420
+ .cfi_startproc
1421
+.LVL128:
1422
+ stp x29, x30, [sp, -64]!
1423
+ .cfi_def_cfa_offset 64
1424
+ .cfi_offset 29, -64
1425
+ .cfi_offset 30, -56
1426
+ .loc 1 539 0
1427
+ cmp w0, 2
1428
+ .loc 1 538 0
1429
+ add x29, sp, 0
1430
+ .cfi_def_cfa_register 29
1431
+ .loc 1 539 0
1432
+ beq .L123
1433
+ cmp w0, 3
1434
+ beq .L124
1435
+ cbnz w0, .L121
1436
+.LBB124:
1437
+.LBB125:
1438
+ .loc 1 494 0
1439
+ adrp x1, .LANCHOR3
1440
+ add x1, x1, :lo12:.LANCHOR3
1441
+ mov x2, 48
1442
+ add x0, x29, 16
1443
+.LVL129:
1444
+ bl memcpy
1445
+.LVL130:
1446
+ .loc 1 509 0
1447
+ adrp x0, .LC14
1448
+ add x0, x0, :lo12:.LC14
1449
+ bl printf
1450
+.LVL131:
1451
+ .loc 1 511 0
1452
+ mov x2, 1376
1453
+ mov w1, 0
1454
+ mov x0, 136314880
1455
+ bl memset
1456
+.LVL132:
1457
+ .loc 1 512 0
1458
+ adrp x0, .LANCHOR2
1459
+ add x6, x29, 64
1460
+.LBB126:
1461
+.LBB127:
1462
+ .loc 1 177 0
1463
+ mov x4, 136314880
1464
+ mov x7, 328
1465
+.LBE127:
1466
+.LBE126:
1467
+ .loc 1 512 0
1468
+ str x18, [x0, #:lo12:.LANCHOR2]
1469
+.LVL133:
1470
+ add x0, x29, 16
1471
+.LBB130:
1472
+.LBB128:
1473
+ .loc 1 179 0
1474
+ mov x8, 40
1475
+ .loc 1 185 0
1476
+ mov w10, 1
1477
+.LVL134:
1478
+.L126:
1479
+.LBE128:
1480
+.LBE130:
1481
+ .loc 1 514 0
1482
+ cmp x6, x0
1483
+ bne .L128
1484
+ .loc 1 517 0
1485
+ bl flush_dcache_all
1486
+.LVL135:
1487
+.LBB131:
1488
+ .loc 1 518 0
1489
+#APP
1490
+// 518 "common/mp_boot.c" 1
1491
+ dmb sy
1492
+// 0 "" 2
1493
+#NO_APP
1494
+ mov x1, 8
1495
+ adrp x0, save_boot_params_ret
1496
+ movk x1, 0xfe48, lsl 16
1497
+ add x0, x0, :lo12:save_boot_params_ret
1498
+ str w0, [x1]
1499
+.LVL136:
1500
+.LBE131:
1501
+.LBB132:
1502
+ .loc 1 519 0
1503
+#APP
1504
+// 519 "common/mp_boot.c" 1
1505
+ dmb sy
1506
+// 0 "" 2
1507
+#NO_APP
1508
+ mov x0, 4
1509
+ mov w1, 48815
1510
+ movk x0, 0xfe48, lsl 16
1511
+ movk w1, 0xdead, lsl 16
1512
+ str w1, [x0]
1513
+.LBE132:
1514
+ .loc 1 520 0
1515
+#APP
1516
+// 520 "common/mp_boot.c" 1
1517
+ dsb sy
1518
+// 0 "" 2
1519
+ .loc 1 522 0
1520
+// 522 "common/mp_boot.c" 1
1521
+ sev
1522
+// 0 "" 2
1523
+ .loc 1 523 0
1524
+// 523 "common/mp_boot.c" 1
1525
+ isb sy
1526
+// 0 "" 2
1527
+.LVL137:
1528
+#NO_APP
1529
+.L121:
1530
+.LBE125:
1531
+.LBE124:
1532
+ .loc 1 556 0
1533
+ ldp x29, x30, [sp], 64
1534
+ .cfi_remember_state
1535
+ .cfi_restore 30
1536
+ .cfi_restore 29
1537
+ .cfi_def_cfa 31, 0
1538
+ ret
1539
+.L128:
1540
+ .cfi_restore_state
1541
+ ldp w1, w3, [x0]
1542
+.LVL138:
1543
+ ldp w12, w11, [x0, 16]
1544
+.LBB135:
1545
+.LBB134:
1546
+.LBB133:
1547
+.LBB129:
1548
+ .loc 1 172 0
1549
+ cmp w1, 3
1550
+ ldr x13, [x0, 8]
1551
+.LVL139:
1552
+ beq .L127
1553
+ .loc 1 176 0
1554
+ sub w2, w3, #1
1555
+ cmp w2, 6
1556
+ bhi .L127
1557
+.LVL140:
1558
+ .loc 1 177 0
1559
+ uxtw x1, w1
1560
+ mul x2, x1, x7
1561
+ add x5, x4, x2
1562
+ .loc 1 179 0
1563
+ ldrb w1, [x5, 328]
1564
+.LVL141:
1565
+ madd x1, x1, x8, x2
1566
+ add x1, x4, x1
1567
+ .loc 1 181 0
1568
+ stp w3, w12, [x1, 20]
1569
+.LVL142:
1570
+ .loc 1 185 0
1571
+ lsl w3, w10, w3
1572
+.LVL143:
1573
+ .loc 1 183 0
1574
+ stp w11, wzr, [x1, 28]
1575
+ .loc 1 179 0
1576
+ str x13, [x1, 8]
1577
+ .loc 1 184 0
1578
+ str xzr, [x1, 40]
1579
+ .loc 1 185 0
1580
+ ldr w1, [x4]
1581
+.LVL144:
1582
+ orr w3, w1, w3
1583
+ str w3, [x4]
1584
+ .loc 1 186 0
1585
+ ldrb w1, [x5, 328]
1586
+ add w1, w1, 1
1587
+ strb w1, [x5, 328]
1588
+.L127:
1589
+ add x0, x0, 24
1590
+ b .L126
1591
+.LVL145:
1592
+.L123:
1593
+.LBE129:
1594
+.LBE133:
1595
+.LBE134:
1596
+.LBE135:
1597
+ .loc 1 544 0
1598
+ mov w2, -559087616
1599
+ mov w1, 3
1600
+ mov w0, 0
1601
+.LVL146:
1602
+ bl mpb_task_set_state
1603
+.LVL147:
1604
+ .loc 1 545 0
1605
+ bl flush_dcache_all
1606
+.LVL148:
1607
+ .loc 1 546 0
1608
+#APP
1609
+// 546 "common/mp_boot.c" 1
1610
+ dsb sy
1611
+// 0 "" 2
1612
+ .loc 1 547 0
1613
+// 547 "common/mp_boot.c" 1
1614
+ isb sy
1615
+// 0 "" 2
1616
+.LVL149:
1617
+ .loc 1 556 0
1618
+#NO_APP
1619
+ ldp x29, x30, [sp], 64
1620
+ .cfi_remember_state
1621
+ .cfi_restore 30
1622
+ .cfi_restore 29
1623
+ .cfi_def_cfa 31, 0
1624
+.LBB136:
1625
+.LBB137:
1626
+ .loc 2 16 0
1627
+ mov x0, 1000
1628
+ b udelay
1629
+.LVL150:
1630
+.L124:
1631
+ .cfi_restore_state
1632
+.LBE137:
1633
+.LBE136:
1634
+ .loc 1 556 0
1635
+ ldp x29, x30, [sp], 64
1636
+ .cfi_restore 30
1637
+ .cfi_restore 29
1638
+ .cfi_def_cfa 31, 0
1639
+ .loc 1 553 0
1640
+ mov w2, -559087616
1641
+ mov w1, 7
1642
+ mov w0, 0
1643
+.LVL151:
1644
+ b mpb_task_set_state
1645
+.LVL152:
1646
+ .cfi_endproc
1647
+.LFE237:
1648
+ .size mpb_init_x, .-mpb_init_x
1649
+ .section .text.mpb_post,"ax",@progbits
1650
+ .align 2
1651
+ .global mpb_post
1652
+ .type mpb_post, %function
1653
+mpb_post:
1654
+.LFB239:
1655
+ .loc 1 576 0
1656
+ .cfi_startproc
1657
+.LVL153:
1658
+ .loc 1 580 0
1659
+ cmp w0, 5
1660
+ bhi .L147
1661
+ .loc 1 576 0
1662
+ stp x29, x30, [sp, -48]!
1663
+ .cfi_def_cfa_offset 48
1664
+ .cfi_offset 29, -48
1665
+ .cfi_offset 30, -40
1666
+ .loc 1 580 0
1667
+ adrp x1, .L136
1668
+ add x1, x1, :lo12:.L136
1669
+ .loc 1 576 0
1670
+ add x29, sp, 0
1671
+ .cfi_def_cfa_register 29
1672
+ .loc 1 580 0
1673
+ ldrb w0, [x1,w0,uxtw]
1674
+ adr x1, .Lrtx136
1675
+ add x0, x1, w0, sxtb #2
1676
+ br x0
1677
+.Lrtx136:
1678
+.LVL154:
1679
+ .section .rodata.mpb_post,"a",@progbits
1680
+ .align 0
1681
+ .align 2
1682
+.L136:
1683
+ .byte (.L135 - .Lrtx136) / 4
1684
+ .byte (.L137 - .Lrtx136) / 4
1685
+ .byte (.L138 - .Lrtx136) / 4
1686
+ .byte (.L139 - .Lrtx136) / 4
1687
+ .byte (.L140 - .Lrtx136) / 4
1688
+ .byte (.L141 - .Lrtx136) / 4
1689
+ .section .text.mpb_post
1690
+.L135:
1691
+ .loc 1 582 0
1692
+ mov w0, 5
1693
+.L155:
1694
+ .loc 1 602 0
1695
+ bl mpb_task_wait_done
1696
+.LVL155:
1697
+ sxtw x0, w0
1698
+ b .L133
1699
+.L137:
1700
+.LVL156:
1701
+ .loc 1 586 0
1702
+ mov w0, 5
1703
+ bl mpb_task_wait_done
1704
+.LVL157:
1705
+ .loc 1 587 0
1706
+ bl mpb_quit_load_image
1707
+.LVL158:
1708
+ cbz w0, .L142
1709
+.LVL159:
1710
+.L156:
1711
+ .loc 1 621 0
1712
+ mov x0, 0
1713
+ .loc 1 617 0
1714
+ b .L133
1715
+.LVL160:
1716
+.L142:
1717
+ .loc 1 587 0 discriminator 1
1718
+ mov x0, 136314880
1719
+ ldr x0, [x0, 1360]
1720
+.LVL161:
1721
+.L133:
1722
+ .loc 1 622 0
1723
+ ldp x29, x30, [sp], 48
1724
+ .cfi_remember_state
1725
+ .cfi_restore 30
1726
+ .cfi_restore 29
1727
+ .cfi_def_cfa 31, 0
1728
+ ret
1729
+.L138:
1730
+ .cfi_restore_state
1731
+ .loc 1 590 0
1732
+ bl mpb_quit_load_image
1733
+.LVL162:
1734
+ cbnz w0, .L156
1735
+ .loc 1 590 0 is_stmt 0 discriminator 1
1736
+ mov x0, 136314880
1737
+ ldr x0, [x0, 1368]
1738
+ b .L133
1739
+.L139:
1740
+ .loc 1 594 0 is_stmt 1
1741
+ bl mpb_quit_load_image
1742
+.LVL163:
1743
+ cbz w0, .L156
1744
+ .loc 1 596 0
1745
+ mov w0, 6
1746
+ bl mpb_task_wait_done
1747
+.LVL164:
1748
+ .loc 1 597 0
1749
+ mov x0, 1
1750
+ b .L133
1751
+.L140:
1752
+ .loc 1 602 0
1753
+ mov w0, 6
1754
+ b .L155
1755
+.L141:
1756
+ .loc 1 605 0
1757
+ bl mpb_quit_load_image
1758
+.LVL165:
1759
+ cbnz w0, .L156
1760
+.LVL166:
1761
+ .loc 1 609 0
1762
+ mov w0, 5
1763
+ bl mpb_task_wait_done
1764
+.LVL167:
1765
+ cmp w0, 0
1766
+ ble .L144
1767
+.L146:
1768
+ .loc 1 611 0
1769
+ mov x0, 136314880
1770
+ adrp x2, .LC15
1771
+ add x2, x2, :lo12:.LC15
1772
+ mov x1, 32
1773
+ ldr x3, [x0, 1360]
1774
+ add x0, x29, 16
1775
+ bl snprintf
1776
+.LVL168:
1777
+ .loc 1 612 0
1778
+ mov w1, 0
1779
+ add x0, x29, 16
1780
+ bl run_command
1781
+.LVL169:
1782
+.L145:
1783
+ .loc 1 616 0
1784
+ bl mpb_task_dump
1785
+.LVL170:
1786
+ b .L156
1787
+.L144:
1788
+ .loc 1 610 0 discriminator 1
1789
+ mov w0, 4
1790
+ bl mpb_task_wait_done
1791
+.LVL171:
1792
+ .loc 1 609 0 discriminator 1
1793
+ cmp w0, 0
1794
+ bgt .L146
1795
+ b .L145
1796
+.LVL172:
1797
+.L147:
1798
+ .cfi_def_cfa 31, 0
1799
+ .cfi_restore 29
1800
+ .cfi_restore 30
1801
+ .loc 1 621 0
1802
+ mov x0, 0
1803
+.LVL173:
1804
+ ret
1805
+ .cfi_endproc
1806
+.LFE239:
1807
+ .size mpb_post, .-mpb_post
1808
+ .section .rodata
1809
+ .align 3
1810
+ .set .LANCHOR3,. + 0
1811
+.LC0:
1812
+ .word 0
1813
+ .word 2
1814
+ .xword spl_load_baseparamter
1815
+ .word 0
1816
+ .word 0
1817
+ .word 2
1818
+ .word 1
1819
+ .xword spl_init_display
1820
+ .word 0
1821
+ .word 0
1822
+ .section .bss.mpb_gd,"aw",@nobits
1823
+ .align 3
1824
+ .set .LANCHOR2,. + 0
1825
+ .type mpb_gd, %object
1826
+ .size mpb_gd, 8
1827
+mpb_gd:
1828
+ .zero 8
1829
+ .section .bss.once.6657,"aw",@nobits
1830
+ .align 2
1831
+ .set .LANCHOR0,. + 0
1832
+ .type once.6657, %object
1833
+ .size once.6657, 4
1834
+once.6657:
1835
+ .zero 4
1836
+ .section .rodata.core_task_run.part.2.str1.1,"aMS",@progbits,1
1837
+.LC11:
1838
+ .string "-- T%d.%d [%d, %ld]\n"
1839
+.LC12:
1840
+ .string "++ T%d.%d -\n"
1841
+.LC13:
1842
+ .string "++ T%d.%d\n"
1843
+ .section .rodata.mpb_init_x.str1.1,"aMS",@progbits,1
1844
+.LC14:
1845
+ .string "U-Boot SPL MP\n"
1846
+ .section .rodata.mpb_post.str1.1,"aMS",@progbits,1
1847
+.LC15:
1848
+ .string "bootm 0x%lx"
1849
+ .section .rodata.mpb_quit_load_image.str1.1,"aMS",@progbits,1
1850
+.LC1:
1851
+ .string "++ serial boot\n"
1852
+ .section .rodata.mpb_task_dump.str1.1,"aMS",@progbits,1
1853
+.LC2:
1854
+ .string "data: %08lx, %08lx\n"
1855
+.LC3:
1856
+ .string "T%d.%d:[%s]\n"
1857
+.LC4:
1858
+ .string " tid: %d\n"
1859
+.LC5:
1860
+ .string " fn: 0x%08lx\n"
1861
+.LC6:
1862
+ .string " state: 0x%08x\n"
1863
+.LC7:
1864
+ .string " ret: %d\n"
1865
+.LC8:
1866
+ .string " ms: %ld\n"
1867
+.LC9:
1868
+ .string " ptid_mask: 0x%08x\n"
1869
+.LC10:
1870
+ .string " rip_fail: %d\n\n"
1871
+ .section .rodata.str1.1,"aMS",@progbits,1
1872
+.LC16:
1873
+ .string "none"
1874
+.LC17:
1875
+ .string "init-display"
1876
+.LC18:
1877
+ .string "load-baseparameter"
1878
+.LC19:
1879
+ .string "load-uboot"
1880
+.LC20:
1881
+ .string "load-fit"
1882
+.LC21:
1883
+ .string "load-android"
1884
+.LC22:
1885
+ .string "hash-android"
1886
+.LC23:
1887
+ .string "run-uboot"
1888
+ .section .rodata.tid_name,"a",@progbits
1889
+ .align 3
1890
+ .set .LANCHOR1,. + 0
1891
+ .type tid_name, %object
1892
+ .size tid_name, 64
1893
+tid_name:
1894
+ .xword .LC16
1895
+ .xword .LC17
1896
+ .xword .LC18
1897
+ .xword .LC19
1898
+ .xword .LC20
1899
+ .xword .LC21
1900
+ .xword .LC22
1901
+ .xword .LC23
1902
+ .text
1903
+.Letext0:
1904
+ .file 4 "include/common.h"
1905
+ .file 5 "./arch/arm/include/asm/types.h"
1906
+ .file 6 "include/linux/types.h"
1907
+ .file 7 "include/errno.h"
1908
+ .file 8 "include/linux/string.h"
1909
+ .file 9 "include/efi.h"
1910
+ .file 10 "include/ide.h"
1911
+ .file 11 "include/linux/list.h"
1912
+ .file 12 "include/part.h"
1913
+ .file 13 "include/flash.h"
1914
+ .file 14 "include/lmb.h"
1915
+ .file 15 "include/asm-generic/u-boot.h"
1916
+ .file 16 "./arch/arm/include/asm/u-boot-arm.h"
1917
+ .file 17 "include/linux/libfdt_env.h"
1918
+ .file 18 "include/linux/../../scripts/dtc/libfdt/fdt.h"
1919
+ .file 19 "include/linux/libfdt.h"
1920
+ .file 20 "include/image.h"
1921
+ .file 21 "./arch/arm/include/asm/global_data.h"
1922
+ .file 22 "include/asm-generic/global_data.h"
1923
+ .file 23 "include/net.h"
1924
+ .file 24 "include/dm/uclass-id.h"
1925
+ .file 25 "./arch/arm/include/asm/spl.h"
1926
+ .file 26 "include/spl.h"
1927
+ .file 27 "include/mp_boot.h"
1928
+ .file 28 "include/boot_rkimg.h"
1929
+ .file 29 "include/log.h"
1930
+ .file 30 "include/vsprintf.h"
1931
+ .file 31 "include/stdio.h"
1932
+ .section .debug_info,"",@progbits
1933
+.Ldebug_info0:
1934
+ .4byte 0x2575
1935
+ .2byte 0x4
1936
+ .4byte .Ldebug_abbrev0
1937
+ .byte 0x8
1938
+ .uleb128 0x1
1939
+ .4byte .LASF447
1940
+ .byte 0xc
1941
+ .4byte .LASF448
1942
+ .4byte .LASF449
1943
+ .4byte .Ldebug_ranges0+0x230
1944
+ .8byte 0
1945
+ .4byte .Ldebug_line0
1946
+ .uleb128 0x2
1947
+ .4byte .LASF4
1948
+ .byte 0x4
1949
+ .byte 0xd
1950
+ .4byte 0x34
1951
+ .uleb128 0x3
1952
+ .byte 0x1
1953
+ .byte 0x8
1954
+ .4byte .LASF0
1955
+ .uleb128 0x3
1956
+ .byte 0x8
1957
+ .byte 0x7
1958
+ .4byte .LASF1
1959
+ .uleb128 0x3
1960
+ .byte 0x2
1961
+ .byte 0x7
1962
+ .4byte .LASF2
1963
+ .uleb128 0x4
1964
+ .4byte .LASF20
1965
+ .byte 0x7
1966
+ .byte 0xc
1967
+ .4byte 0x54
1968
+ .uleb128 0x5
1969
+ .byte 0x4
1970
+ .byte 0x5
1971
+ .string "int"
1972
+ .uleb128 0x3
1973
+ .byte 0x1
1974
+ .byte 0x6
1975
+ .4byte .LASF3
1976
+ .uleb128 0x2
1977
+ .4byte .LASF5
1978
+ .byte 0x5
1979
+ .byte 0xc
1980
+ .4byte 0x34
1981
+ .uleb128 0x3
1982
+ .byte 0x2
1983
+ .byte 0x5
1984
+ .4byte .LASF6
1985
+ .uleb128 0x2
1986
+ .4byte .LASF7
1987
+ .byte 0x5
1988
+ .byte 0x12
1989
+ .4byte 0x7f
1990
+ .uleb128 0x3
1991
+ .byte 0x4
1992
+ .byte 0x7
1993
+ .4byte .LASF8
1994
+ .uleb128 0x3
1995
+ .byte 0x8
1996
+ .byte 0x5
1997
+ .4byte .LASF9
1998
+ .uleb128 0x3
1999
+ .byte 0x8
2000
+ .byte 0x7
2001
+ .4byte .LASF10
2002
+ .uleb128 0x6
2003
+ .string "u8"
2004
+ .byte 0x5
2005
+ .byte 0x1f
2006
+ .4byte 0x34
2007
+ .uleb128 0x7
2008
+ .4byte 0x94
2009
+ .uleb128 0x6
2010
+ .string "u32"
2011
+ .byte 0x5
2012
+ .byte 0x25
2013
+ .4byte 0x7f
2014
+ .uleb128 0x6
2015
+ .string "u64"
2016
+ .byte 0x5
2017
+ .byte 0x28
2018
+ .4byte 0x8d
2019
+ .uleb128 0x2
2020
+ .4byte .LASF11
2021
+ .byte 0x5
2022
+ .byte 0x31
2023
+ .4byte 0x8d
2024
+ .uleb128 0x2
2025
+ .4byte .LASF12
2026
+ .byte 0x5
2027
+ .byte 0x32
2028
+ .4byte 0x8d
2029
+ .uleb128 0x3
2030
+ .byte 0x8
2031
+ .byte 0x7
2032
+ .4byte .LASF13
2033
+ .uleb128 0x8
2034
+ .byte 0x8
2035
+ .4byte 0xe3
2036
+ .uleb128 0x3
2037
+ .byte 0x1
2038
+ .byte 0x8
2039
+ .4byte .LASF14
2040
+ .uleb128 0x7
2041
+ .4byte 0xdc
2042
+ .uleb128 0x3
2043
+ .byte 0x8
2044
+ .byte 0x5
2045
+ .4byte .LASF15
2046
+ .uleb128 0x8
2047
+ .byte 0x8
2048
+ .4byte 0xdc
2049
+ .uleb128 0x2
2050
+ .4byte .LASF16
2051
+ .byte 0x6
2052
+ .byte 0x59
2053
+ .4byte 0x42
2054
+ .uleb128 0x2
2055
+ .4byte .LASF17
2056
+ .byte 0x6
2057
+ .byte 0x5b
2058
+ .4byte 0x3b
2059
+ .uleb128 0x9
2060
+ .4byte 0x100
2061
+ .uleb128 0x2
2062
+ .4byte .LASF18
2063
+ .byte 0x6
2064
+ .byte 0x69
2065
+ .4byte 0x62
2066
+ .uleb128 0x2
2067
+ .4byte .LASF19
2068
+ .byte 0x6
2069
+ .byte 0x97
2070
+ .4byte 0x74
2071
+ .uleb128 0xa
2072
+ .byte 0x8
2073
+ .uleb128 0x4
2074
+ .4byte .LASF21
2075
+ .byte 0x8
2076
+ .byte 0xb
2077
+ .4byte 0xef
2078
+ .uleb128 0x3
2079
+ .byte 0x1
2080
+ .byte 0x2
2081
+ .4byte .LASF22
2082
+ .uleb128 0xb
2083
+ .4byte 0xdc
2084
+ .4byte 0x145
2085
+ .uleb128 0xc
2086
+ .byte 0
2087
+ .uleb128 0xd
2088
+ .4byte .LASF23
2089
+ .byte 0x9
2090
+ .2byte 0x140
2091
+ .4byte 0x13a
2092
+ .uleb128 0xd
2093
+ .4byte .LASF24
2094
+ .byte 0x9
2095
+ .2byte 0x143
2096
+ .4byte 0x13a
2097
+ .uleb128 0xd
2098
+ .4byte .LASF25
2099
+ .byte 0x9
2100
+ .2byte 0x143
2101
+ .4byte 0x13a
2102
+ .uleb128 0xe
2103
+ .4byte .LASF38
2104
+ .uleb128 0x8
2105
+ .byte 0x8
2106
+ .4byte 0x169
2107
+ .uleb128 0x8
2108
+ .byte 0x8
2109
+ .4byte 0x17a
2110
+ .uleb128 0xf
2111
+ .uleb128 0xb
2112
+ .4byte 0x100
2113
+ .4byte 0x186
2114
+ .uleb128 0xc
2115
+ .byte 0
2116
+ .uleb128 0x4
2117
+ .4byte .LASF26
2118
+ .byte 0xa
2119
+ .byte 0x10
2120
+ .4byte 0x17b
2121
+ .uleb128 0xb
2122
+ .4byte 0x34
2123
+ .4byte 0x1a1
2124
+ .uleb128 0x10
2125
+ .4byte 0xcf
2126
+ .byte 0x5
2127
+ .byte 0
2128
+ .uleb128 0x11
2129
+ .4byte .LASF29
2130
+ .byte 0x10
2131
+ .byte 0xb
2132
+ .byte 0x16
2133
+ .4byte 0x1c6
2134
+ .uleb128 0x12
2135
+ .4byte .LASF27
2136
+ .byte 0xb
2137
+ .byte 0x17
2138
+ .4byte 0x1c6
2139
+ .byte 0
2140
+ .uleb128 0x12
2141
+ .4byte .LASF28
2142
+ .byte 0xb
2143
+ .byte 0x17
2144
+ .4byte 0x1c6
2145
+ .byte 0x8
2146
+ .byte 0
2147
+ .uleb128 0x8
2148
+ .byte 0x8
2149
+ .4byte 0x1a1
2150
+ .uleb128 0x11
2151
+ .4byte .LASF30
2152
+ .byte 0x10
2153
+ .byte 0xc
2154
+ .byte 0xf
2155
+ .4byte 0x1f1
2156
+ .uleb128 0x12
2157
+ .4byte .LASF31
2158
+ .byte 0xc
2159
+ .byte 0x10
2160
+ .4byte 0xef
2161
+ .byte 0
2162
+ .uleb128 0x12
2163
+ .4byte .LASF32
2164
+ .byte 0xc
2165
+ .byte 0x11
2166
+ .4byte 0x20a
2167
+ .byte 0x8
2168
+ .byte 0
2169
+ .uleb128 0x7
2170
+ .4byte 0x1cc
2171
+ .uleb128 0x13
2172
+ .4byte 0x54
2173
+ .4byte 0x20a
2174
+ .uleb128 0x14
2175
+ .4byte 0x54
2176
+ .uleb128 0x14
2177
+ .4byte 0x54
2178
+ .byte 0
2179
+ .uleb128 0x8
2180
+ .byte 0x8
2181
+ .4byte 0x1f6
2182
+ .uleb128 0xb
2183
+ .4byte 0x1f1
2184
+ .4byte 0x21b
2185
+ .uleb128 0xc
2186
+ .byte 0
2187
+ .uleb128 0x7
2188
+ .4byte 0x210
2189
+ .uleb128 0x4
2190
+ .4byte .LASF30
2191
+ .byte 0xc
2192
+ .byte 0xe1
2193
+ .4byte 0x21b
2194
+ .uleb128 0x15
2195
+ .2byte 0x1220
2196
+ .byte 0xd
2197
+ .byte 0x13
2198
+ .4byte 0x27f
2199
+ .uleb128 0x12
2200
+ .4byte .LASF33
2201
+ .byte 0xd
2202
+ .byte 0x14
2203
+ .4byte 0x100
2204
+ .byte 0
2205
+ .uleb128 0x12
2206
+ .4byte .LASF34
2207
+ .byte 0xd
2208
+ .byte 0x15
2209
+ .4byte 0xf5
2210
+ .byte 0x8
2211
+ .uleb128 0x12
2212
+ .4byte .LASF35
2213
+ .byte 0xd
2214
+ .byte 0x16
2215
+ .4byte 0x100
2216
+ .byte 0x10
2217
+ .uleb128 0x12
2218
+ .4byte .LASF36
2219
+ .byte 0xd
2220
+ .byte 0x17
2221
+ .4byte 0x27f
2222
+ .byte 0x18
2223
+ .uleb128 0x16
2224
+ .4byte .LASF37
2225
+ .byte 0xd
2226
+ .byte 0x18
2227
+ .4byte 0x290
2228
+ .2byte 0x1018
2229
+ .uleb128 0x17
2230
+ .string "mtd"
2231
+ .byte 0xd
2232
+ .byte 0x31
2233
+ .4byte 0x2a6
2234
+ .2byte 0x1218
2235
+ .byte 0
2236
+ .uleb128 0xb
2237
+ .4byte 0x100
2238
+ .4byte 0x290
2239
+ .uleb128 0x18
2240
+ .4byte 0xcf
2241
+ .2byte 0x1ff
2242
+ .byte 0
2243
+ .uleb128 0xb
2244
+ .4byte 0x29
2245
+ .4byte 0x2a1
2246
+ .uleb128 0x18
2247
+ .4byte 0xcf
2248
+ .2byte 0x1ff
2249
+ .byte 0
2250
+ .uleb128 0xe
2251
+ .4byte .LASF39
2252
+ .uleb128 0x8
2253
+ .byte 0x8
2254
+ .4byte 0x2a1
2255
+ .uleb128 0x2
2256
+ .4byte .LASF40
2257
+ .byte 0xd
2258
+ .byte 0x37
2259
+ .4byte 0x22b
2260
+ .uleb128 0xb
2261
+ .4byte 0x2ac
2262
+ .4byte 0x2c2
2263
+ .uleb128 0xc
2264
+ .byte 0
2265
+ .uleb128 0x4
2266
+ .4byte .LASF41
2267
+ .byte 0xd
2268
+ .byte 0x39
2269
+ .4byte 0x2b7
2270
+ .uleb128 0x3
2271
+ .byte 0x10
2272
+ .byte 0x4
2273
+ .4byte .LASF42
2274
+ .uleb128 0x11
2275
+ .4byte .LASF43
2276
+ .byte 0x10
2277
+ .byte 0xe
2278
+ .byte 0x10
2279
+ .4byte 0x2f9
2280
+ .uleb128 0x12
2281
+ .4byte .LASF44
2282
+ .byte 0xe
2283
+ .byte 0x11
2284
+ .4byte 0xb9
2285
+ .byte 0
2286
+ .uleb128 0x12
2287
+ .4byte .LASF33
2288
+ .byte 0xe
2289
+ .byte 0x12
2290
+ .4byte 0xc4
2291
+ .byte 0x8
2292
+ .byte 0
2293
+ .uleb128 0x19
2294
+ .4byte .LASF45
2295
+ .2byte 0x120
2296
+ .byte 0xe
2297
+ .byte 0x15
2298
+ .4byte 0x32b
2299
+ .uleb128 0x1a
2300
+ .string "cnt"
2301
+ .byte 0xe
2302
+ .byte 0x16
2303
+ .4byte 0x3b
2304
+ .byte 0
2305
+ .uleb128 0x12
2306
+ .4byte .LASF33
2307
+ .byte 0xe
2308
+ .byte 0x17
2309
+ .4byte 0xc4
2310
+ .byte 0x8
2311
+ .uleb128 0x12
2312
+ .4byte .LASF46
2313
+ .byte 0xe
2314
+ .byte 0x18
2315
+ .4byte 0x32b
2316
+ .byte 0x10
2317
+ .byte 0
2318
+ .uleb128 0xb
2319
+ .4byte 0x2d4
2320
+ .4byte 0x33b
2321
+ .uleb128 0x10
2322
+ .4byte 0xcf
2323
+ .byte 0x10
2324
+ .byte 0
2325
+ .uleb128 0x1b
2326
+ .string "lmb"
2327
+ .2byte 0x240
2328
+ .byte 0xe
2329
+ .byte 0x1b
2330
+ .4byte 0x362
2331
+ .uleb128 0x12
2332
+ .4byte .LASF47
2333
+ .byte 0xe
2334
+ .byte 0x1c
2335
+ .4byte 0x2f9
2336
+ .byte 0
2337
+ .uleb128 0x16
2338
+ .4byte .LASF48
2339
+ .byte 0xe
2340
+ .byte 0x1d
2341
+ .4byte 0x2f9
2342
+ .2byte 0x120
2343
+ .byte 0
2344
+ .uleb128 0x1c
2345
+ .string "lmb"
2346
+ .byte 0xe
2347
+ .byte 0x20
2348
+ .4byte 0x33b
2349
+ .uleb128 0x1d
2350
+ .byte 0x10
2351
+ .byte 0xf
2352
+ .byte 0x5b
2353
+ .4byte 0x38e
2354
+ .uleb128 0x12
2355
+ .4byte .LASF36
2356
+ .byte 0xf
2357
+ .byte 0x5c
2358
+ .4byte 0xae
2359
+ .byte 0
2360
+ .uleb128 0x12
2361
+ .4byte .LASF33
2362
+ .byte 0xf
2363
+ .byte 0x5d
2364
+ .4byte 0xae
2365
+ .byte 0x8
2366
+ .byte 0
2367
+ .uleb128 0x19
2368
+ .4byte .LASF49
2369
+ .2byte 0x148
2370
+ .byte 0xf
2371
+ .byte 0x1b
2372
+ .4byte 0x480
2373
+ .uleb128 0x12
2374
+ .4byte .LASF50
2375
+ .byte 0xf
2376
+ .byte 0x1c
2377
+ .4byte 0x3b
2378
+ .byte 0
2379
+ .uleb128 0x12
2380
+ .4byte .LASF51
2381
+ .byte 0xf
2382
+ .byte 0x1d
2383
+ .4byte 0xc4
2384
+ .byte 0x8
2385
+ .uleb128 0x12
2386
+ .4byte .LASF52
2387
+ .byte 0xf
2388
+ .byte 0x1e
2389
+ .4byte 0x3b
2390
+ .byte 0x10
2391
+ .uleb128 0x12
2392
+ .4byte .LASF53
2393
+ .byte 0xf
2394
+ .byte 0x1f
2395
+ .4byte 0x3b
2396
+ .byte 0x18
2397
+ .uleb128 0x12
2398
+ .4byte .LASF54
2399
+ .byte 0xf
2400
+ .byte 0x20
2401
+ .4byte 0x3b
2402
+ .byte 0x20
2403
+ .uleb128 0x12
2404
+ .4byte .LASF55
2405
+ .byte 0xf
2406
+ .byte 0x21
2407
+ .4byte 0x3b
2408
+ .byte 0x28
2409
+ .uleb128 0x12
2410
+ .4byte .LASF56
2411
+ .byte 0xf
2412
+ .byte 0x22
2413
+ .4byte 0x3b
2414
+ .byte 0x30
2415
+ .uleb128 0x12
2416
+ .4byte .LASF57
2417
+ .byte 0xf
2418
+ .byte 0x24
2419
+ .4byte 0x3b
2420
+ .byte 0x38
2421
+ .uleb128 0x12
2422
+ .4byte .LASF58
2423
+ .byte 0xf
2424
+ .byte 0x25
2425
+ .4byte 0x3b
2426
+ .byte 0x40
2427
+ .uleb128 0x12
2428
+ .4byte .LASF59
2429
+ .byte 0xf
2430
+ .byte 0x26
2431
+ .4byte 0x3b
2432
+ .byte 0x48
2433
+ .uleb128 0x12
2434
+ .4byte .LASF60
2435
+ .byte 0xf
2436
+ .byte 0x31
2437
+ .4byte 0x3b
2438
+ .byte 0x50
2439
+ .uleb128 0x12
2440
+ .4byte .LASF61
2441
+ .byte 0xf
2442
+ .byte 0x32
2443
+ .4byte 0x3b
2444
+ .byte 0x58
2445
+ .uleb128 0x12
2446
+ .4byte .LASF62
2447
+ .byte 0xf
2448
+ .byte 0x33
2449
+ .4byte 0x191
2450
+ .byte 0x60
2451
+ .uleb128 0x12
2452
+ .4byte .LASF63
2453
+ .byte 0xf
2454
+ .byte 0x34
2455
+ .4byte 0x42
2456
+ .byte 0x66
2457
+ .uleb128 0x12
2458
+ .4byte .LASF64
2459
+ .byte 0xf
2460
+ .byte 0x35
2461
+ .4byte 0x3b
2462
+ .byte 0x68
2463
+ .uleb128 0x12
2464
+ .4byte .LASF65
2465
+ .byte 0xf
2466
+ .byte 0x36
2467
+ .4byte 0x3b
2468
+ .byte 0x70
2469
+ .uleb128 0x12
2470
+ .4byte .LASF66
2471
+ .byte 0xf
2472
+ .byte 0x57
2473
+ .4byte 0x100
2474
+ .byte 0x78
2475
+ .uleb128 0x12
2476
+ .4byte .LASF67
2477
+ .byte 0xf
2478
+ .byte 0x58
2479
+ .4byte 0x100
2480
+ .byte 0x80
2481
+ .uleb128 0x12
2482
+ .4byte .LASF68
2483
+ .byte 0xf
2484
+ .byte 0x5e
2485
+ .4byte 0x480
2486
+ .byte 0x88
2487
+ .byte 0
2488
+ .uleb128 0xb
2489
+ .4byte 0x36d
2490
+ .4byte 0x490
2491
+ .uleb128 0x10
2492
+ .4byte 0xcf
2493
+ .byte 0xb
2494
+ .byte 0
2495
+ .uleb128 0x2
2496
+ .4byte .LASF69
2497
+ .byte 0xf
2498
+ .byte 0x60
2499
+ .4byte 0x38e
2500
+ .uleb128 0x4
2501
+ .4byte .LASF70
2502
+ .byte 0x10
2503
+ .byte 0x13
2504
+ .4byte 0x100
2505
+ .uleb128 0x4
2506
+ .4byte .LASF71
2507
+ .byte 0x10
2508
+ .byte 0x14
2509
+ .4byte 0x100
2510
+ .uleb128 0x4
2511
+ .4byte .LASF72
2512
+ .byte 0x10
2513
+ .byte 0x15
2514
+ .4byte 0x100
2515
+ .uleb128 0x4
2516
+ .4byte .LASF73
2517
+ .byte 0x10
2518
+ .byte 0x16
2519
+ .4byte 0x100
2520
+ .uleb128 0x4
2521
+ .4byte .LASF74
2522
+ .byte 0x10
2523
+ .byte 0x17
2524
+ .4byte 0x100
2525
+ .uleb128 0x4
2526
+ .4byte .LASF75
2527
+ .byte 0x10
2528
+ .byte 0x18
2529
+ .4byte 0x100
2530
+ .uleb128 0x4
2531
+ .4byte .LASF76
2532
+ .byte 0x10
2533
+ .byte 0x19
2534
+ .4byte 0x100
2535
+ .uleb128 0x2
2536
+ .4byte .LASF77
2537
+ .byte 0x11
2538
+ .byte 0x11
2539
+ .4byte 0x11b
2540
+ .uleb128 0x11
2541
+ .4byte .LASF78
2542
+ .byte 0x28
2543
+ .byte 0x12
2544
+ .byte 0x39
2545
+ .4byte 0x578
2546
+ .uleb128 0x12
2547
+ .4byte .LASF79
2548
+ .byte 0x12
2549
+ .byte 0x3a
2550
+ .4byte 0x4e8
2551
+ .byte 0
2552
+ .uleb128 0x12
2553
+ .4byte .LASF80
2554
+ .byte 0x12
2555
+ .byte 0x3b
2556
+ .4byte 0x4e8
2557
+ .byte 0x4
2558
+ .uleb128 0x12
2559
+ .4byte .LASF81
2560
+ .byte 0x12
2561
+ .byte 0x3c
2562
+ .4byte 0x4e8
2563
+ .byte 0x8
2564
+ .uleb128 0x12
2565
+ .4byte .LASF82
2566
+ .byte 0x12
2567
+ .byte 0x3d
2568
+ .4byte 0x4e8
2569
+ .byte 0xc
2570
+ .uleb128 0x12
2571
+ .4byte .LASF83
2572
+ .byte 0x12
2573
+ .byte 0x3e
2574
+ .4byte 0x4e8
2575
+ .byte 0x10
2576
+ .uleb128 0x12
2577
+ .4byte .LASF84
2578
+ .byte 0x12
2579
+ .byte 0x3f
2580
+ .4byte 0x4e8
2581
+ .byte 0x14
2582
+ .uleb128 0x12
2583
+ .4byte .LASF85
2584
+ .byte 0x12
2585
+ .byte 0x40
2586
+ .4byte 0x4e8
2587
+ .byte 0x18
2588
+ .uleb128 0x12
2589
+ .4byte .LASF86
2590
+ .byte 0x12
2591
+ .byte 0x43
2592
+ .4byte 0x4e8
2593
+ .byte 0x1c
2594
+ .uleb128 0x12
2595
+ .4byte .LASF87
2596
+ .byte 0x12
2597
+ .byte 0x46
2598
+ .4byte 0x4e8
2599
+ .byte 0x20
2600
+ .uleb128 0x12
2601
+ .4byte .LASF88
2602
+ .byte 0x12
2603
+ .byte 0x49
2604
+ .4byte 0x4e8
2605
+ .byte 0x24
2606
+ .byte 0
2607
+ .uleb128 0xd
2608
+ .4byte .LASF89
2609
+ .byte 0x13
2610
+ .2byte 0x136
2611
+ .4byte 0x584
2612
+ .uleb128 0x8
2613
+ .byte 0x8
2614
+ .4byte 0x4f3
2615
+ .uleb128 0x1e
2616
+ .4byte .LASF90
2617
+ .byte 0x40
2618
+ .byte 0x14
2619
+ .2byte 0x137
2620
+ .4byte 0x634
2621
+ .uleb128 0x1f
2622
+ .4byte .LASF91
2623
+ .byte 0x14
2624
+ .2byte 0x138
2625
+ .4byte 0x11b
2626
+ .byte 0
2627
+ .uleb128 0x1f
2628
+ .4byte .LASF92
2629
+ .byte 0x14
2630
+ .2byte 0x139
2631
+ .4byte 0x11b
2632
+ .byte 0x4
2633
+ .uleb128 0x1f
2634
+ .4byte .LASF93
2635
+ .byte 0x14
2636
+ .2byte 0x13a
2637
+ .4byte 0x11b
2638
+ .byte 0x8
2639
+ .uleb128 0x1f
2640
+ .4byte .LASF94
2641
+ .byte 0x14
2642
+ .2byte 0x13b
2643
+ .4byte 0x11b
2644
+ .byte 0xc
2645
+ .uleb128 0x1f
2646
+ .4byte .LASF95
2647
+ .byte 0x14
2648
+ .2byte 0x13c
2649
+ .4byte 0x11b
2650
+ .byte 0x10
2651
+ .uleb128 0x1f
2652
+ .4byte .LASF96
2653
+ .byte 0x14
2654
+ .2byte 0x13d
2655
+ .4byte 0x11b
2656
+ .byte 0x14
2657
+ .uleb128 0x1f
2658
+ .4byte .LASF97
2659
+ .byte 0x14
2660
+ .2byte 0x13e
2661
+ .4byte 0x11b
2662
+ .byte 0x18
2663
+ .uleb128 0x1f
2664
+ .4byte .LASF98
2665
+ .byte 0x14
2666
+ .2byte 0x13f
2667
+ .4byte 0x110
2668
+ .byte 0x1c
2669
+ .uleb128 0x1f
2670
+ .4byte .LASF99
2671
+ .byte 0x14
2672
+ .2byte 0x140
2673
+ .4byte 0x110
2674
+ .byte 0x1d
2675
+ .uleb128 0x1f
2676
+ .4byte .LASF100
2677
+ .byte 0x14
2678
+ .2byte 0x141
2679
+ .4byte 0x110
2680
+ .byte 0x1e
2681
+ .uleb128 0x1f
2682
+ .4byte .LASF101
2683
+ .byte 0x14
2684
+ .2byte 0x142
2685
+ .4byte 0x110
2686
+ .byte 0x1f
2687
+ .uleb128 0x1f
2688
+ .4byte .LASF102
2689
+ .byte 0x14
2690
+ .2byte 0x143
2691
+ .4byte 0x634
2692
+ .byte 0x20
2693
+ .byte 0
2694
+ .uleb128 0xb
2695
+ .4byte 0x110
2696
+ .4byte 0x644
2697
+ .uleb128 0x10
2698
+ .4byte 0xcf
2699
+ .byte 0x1f
2700
+ .byte 0
2701
+ .uleb128 0x20
2702
+ .4byte .LASF103
2703
+ .byte 0x14
2704
+ .2byte 0x144
2705
+ .4byte 0x58a
2706
+ .uleb128 0x1e
2707
+ .4byte .LASF104
2708
+ .byte 0x30
2709
+ .byte 0x14
2710
+ .2byte 0x146
2711
+ .4byte 0x6d2
2712
+ .uleb128 0x1f
2713
+ .4byte .LASF36
2714
+ .byte 0x14
2715
+ .2byte 0x147
2716
+ .4byte 0x100
2717
+ .byte 0
2718
+ .uleb128 0x21
2719
+ .string "end"
2720
+ .byte 0x14
2721
+ .2byte 0x147
2722
+ .4byte 0x100
2723
+ .byte 0x8
2724
+ .uleb128 0x1f
2725
+ .4byte .LASF105
2726
+ .byte 0x14
2727
+ .2byte 0x148
2728
+ .4byte 0x100
2729
+ .byte 0x10
2730
+ .uleb128 0x1f
2731
+ .4byte .LASF106
2732
+ .byte 0x14
2733
+ .2byte 0x148
2734
+ .4byte 0x100
2735
+ .byte 0x18
2736
+ .uleb128 0x1f
2737
+ .4byte .LASF107
2738
+ .byte 0x14
2739
+ .2byte 0x149
2740
+ .4byte 0x100
2741
+ .byte 0x20
2742
+ .uleb128 0x1f
2743
+ .4byte .LASF108
2744
+ .byte 0x14
2745
+ .2byte 0x14a
2746
+ .4byte 0x110
2747
+ .byte 0x28
2748
+ .uleb128 0x1f
2749
+ .4byte .LASF109
2750
+ .byte 0x14
2751
+ .2byte 0x14a
2752
+ .4byte 0x110
2753
+ .byte 0x29
2754
+ .uleb128 0x21
2755
+ .string "os"
2756
+ .byte 0x14
2757
+ .2byte 0x14a
2758
+ .4byte 0x110
2759
+ .byte 0x2a
2760
+ .uleb128 0x1f
2761
+ .4byte .LASF110
2762
+ .byte 0x14
2763
+ .2byte 0x14b
2764
+ .4byte 0x110
2765
+ .byte 0x2b
2766
+ .byte 0
2767
+ .uleb128 0x20
2768
+ .4byte .LASF111
2769
+ .byte 0x14
2770
+ .2byte 0x14c
2771
+ .4byte 0x650
2772
+ .uleb128 0x22
2773
+ .4byte .LASF112
2774
+ .2byte 0x380
2775
+ .byte 0x14
2776
+ .2byte 0x152
2777
+ .4byte 0x87b
2778
+ .uleb128 0x1f
2779
+ .4byte .LASF113
2780
+ .byte 0x14
2781
+ .2byte 0x158
2782
+ .4byte 0x87b
2783
+ .byte 0
2784
+ .uleb128 0x1f
2785
+ .4byte .LASF114
2786
+ .byte 0x14
2787
+ .2byte 0x159
2788
+ .4byte 0x644
2789
+ .byte 0x8
2790
+ .uleb128 0x1f
2791
+ .4byte .LASF115
2792
+ .byte 0x14
2793
+ .2byte 0x15a
2794
+ .4byte 0x100
2795
+ .byte 0x48
2796
+ .uleb128 0x1f
2797
+ .4byte .LASF116
2798
+ .byte 0x14
2799
+ .2byte 0x15d
2800
+ .4byte 0xd6
2801
+ .byte 0x50
2802
+ .uleb128 0x1f
2803
+ .4byte .LASF117
2804
+ .byte 0x14
2805
+ .2byte 0x15f
2806
+ .4byte 0x126
2807
+ .byte 0x58
2808
+ .uleb128 0x1f
2809
+ .4byte .LASF118
2810
+ .byte 0x14
2811
+ .2byte 0x160
2812
+ .4byte 0xd6
2813
+ .byte 0x60
2814
+ .uleb128 0x1f
2815
+ .4byte .LASF119
2816
+ .byte 0x14
2817
+ .2byte 0x161
2818
+ .4byte 0x54
2819
+ .byte 0x68
2820
+ .uleb128 0x1f
2821
+ .4byte .LASF120
2822
+ .byte 0x14
2823
+ .2byte 0x163
2824
+ .4byte 0x126
2825
+ .byte 0x70
2826
+ .uleb128 0x1f
2827
+ .4byte .LASF121
2828
+ .byte 0x14
2829
+ .2byte 0x164
2830
+ .4byte 0xd6
2831
+ .byte 0x78
2832
+ .uleb128 0x1f
2833
+ .4byte .LASF122
2834
+ .byte 0x14
2835
+ .2byte 0x165
2836
+ .4byte 0x54
2837
+ .byte 0x80
2838
+ .uleb128 0x1f
2839
+ .4byte .LASF123
2840
+ .byte 0x14
2841
+ .2byte 0x167
2842
+ .4byte 0x126
2843
+ .byte 0x88
2844
+ .uleb128 0x1f
2845
+ .4byte .LASF124
2846
+ .byte 0x14
2847
+ .2byte 0x168
2848
+ .4byte 0xd6
2849
+ .byte 0x90
2850
+ .uleb128 0x1f
2851
+ .4byte .LASF125
2852
+ .byte 0x14
2853
+ .2byte 0x169
2854
+ .4byte 0x54
2855
+ .byte 0x98
2856
+ .uleb128 0x1f
2857
+ .4byte .LASF126
2858
+ .byte 0x14
2859
+ .2byte 0x16b
2860
+ .4byte 0x126
2861
+ .byte 0xa0
2862
+ .uleb128 0x1f
2863
+ .4byte .LASF127
2864
+ .byte 0x14
2865
+ .2byte 0x16c
2866
+ .4byte 0xd6
2867
+ .byte 0xa8
2868
+ .uleb128 0x1f
2869
+ .4byte .LASF128
2870
+ .byte 0x14
2871
+ .2byte 0x16d
2872
+ .4byte 0x54
2873
+ .byte 0xb0
2874
+ .uleb128 0x21
2875
+ .string "os"
2876
+ .byte 0x14
2877
+ .2byte 0x171
2878
+ .4byte 0x6d2
2879
+ .byte 0xb8
2880
+ .uleb128 0x21
2881
+ .string "ep"
2882
+ .byte 0x14
2883
+ .2byte 0x172
2884
+ .4byte 0x100
2885
+ .byte 0xe8
2886
+ .uleb128 0x1f
2887
+ .4byte .LASF129
2888
+ .byte 0x14
2889
+ .2byte 0x174
2890
+ .4byte 0x100
2891
+ .byte 0xf0
2892
+ .uleb128 0x1f
2893
+ .4byte .LASF130
2894
+ .byte 0x14
2895
+ .2byte 0x174
2896
+ .4byte 0x100
2897
+ .byte 0xf8
2898
+ .uleb128 0x23
2899
+ .4byte .LASF131
2900
+ .byte 0x14
2901
+ .2byte 0x176
2902
+ .4byte 0xef
2903
+ .2byte 0x100
2904
+ .uleb128 0x23
2905
+ .4byte .LASF132
2906
+ .byte 0x14
2907
+ .2byte 0x177
2908
+ .4byte 0x100
2909
+ .2byte 0x108
2910
+ .uleb128 0x23
2911
+ .4byte .LASF133
2912
+ .byte 0x14
2913
+ .2byte 0x179
2914
+ .4byte 0x100
2915
+ .2byte 0x110
2916
+ .uleb128 0x23
2917
+ .4byte .LASF134
2918
+ .byte 0x14
2919
+ .2byte 0x17a
2920
+ .4byte 0x100
2921
+ .2byte 0x118
2922
+ .uleb128 0x23
2923
+ .4byte .LASF135
2924
+ .byte 0x14
2925
+ .2byte 0x17b
2926
+ .4byte 0x100
2927
+ .2byte 0x120
2928
+ .uleb128 0x23
2929
+ .4byte .LASF136
2930
+ .byte 0x14
2931
+ .2byte 0x17c
2932
+ .4byte 0x100
2933
+ .2byte 0x128
2934
+ .uleb128 0x24
2935
+ .string "kbd"
2936
+ .byte 0x14
2937
+ .2byte 0x17d
2938
+ .4byte 0x881
2939
+ .2byte 0x130
2940
+ .uleb128 0x23
2941
+ .4byte .LASF137
2942
+ .byte 0x14
2943
+ .2byte 0x180
2944
+ .4byte 0x54
2945
+ .2byte 0x138
2946
+ .uleb128 0x23
2947
+ .4byte .LASF138
2948
+ .byte 0x14
2949
+ .2byte 0x18d
2950
+ .4byte 0x54
2951
+ .2byte 0x13c
2952
+ .uleb128 0x24
2953
+ .string "lmb"
2954
+ .byte 0x14
2955
+ .2byte 0x190
2956
+ .4byte 0x33b
2957
+ .2byte 0x140
2958
+ .byte 0
2959
+ .uleb128 0x8
2960
+ .byte 0x8
2961
+ .4byte 0x644
2962
+ .uleb128 0x8
2963
+ .byte 0x8
2964
+ .4byte 0x490
2965
+ .uleb128 0x20
2966
+ .4byte .LASF139
2967
+ .byte 0x14
2968
+ .2byte 0x196
2969
+ .4byte 0x6de
2970
+ .uleb128 0xd
2971
+ .4byte .LASF140
2972
+ .byte 0x14
2973
+ .2byte 0x198
2974
+ .4byte 0x887
2975
+ .uleb128 0xb
2976
+ .4byte 0xdc
2977
+ .4byte 0x8b0
2978
+ .uleb128 0x18
2979
+ .4byte 0xcf
2980
+ .2byte 0x3ff
2981
+ .byte 0
2982
+ .uleb128 0x25
2983
+ .4byte .LASF331
2984
+ .byte 0x4
2985
+ .4byte 0x54
2986
+ .byte 0x18
2987
+ .byte 0xe
2988
+ .4byte 0xb19
2989
+ .uleb128 0x26
2990
+ .4byte .LASF141
2991
+ .byte 0
2992
+ .uleb128 0x26
2993
+ .4byte .LASF142
2994
+ .byte 0x1
2995
+ .uleb128 0x26
2996
+ .4byte .LASF143
2997
+ .byte 0x2
2998
+ .uleb128 0x26
2999
+ .4byte .LASF144
3000
+ .byte 0x3
3001
+ .uleb128 0x26
3002
+ .4byte .LASF145
3003
+ .byte 0x4
3004
+ .uleb128 0x26
3005
+ .4byte .LASF146
3006
+ .byte 0x5
3007
+ .uleb128 0x26
3008
+ .4byte .LASF147
3009
+ .byte 0x6
3010
+ .uleb128 0x26
3011
+ .4byte .LASF148
3012
+ .byte 0x7
3013
+ .uleb128 0x26
3014
+ .4byte .LASF149
3015
+ .byte 0x8
3016
+ .uleb128 0x26
3017
+ .4byte .LASF150
3018
+ .byte 0x9
3019
+ .uleb128 0x26
3020
+ .4byte .LASF151
3021
+ .byte 0xa
3022
+ .uleb128 0x26
3023
+ .4byte .LASF152
3024
+ .byte 0xb
3025
+ .uleb128 0x26
3026
+ .4byte .LASF153
3027
+ .byte 0xc
3028
+ .uleb128 0x26
3029
+ .4byte .LASF154
3030
+ .byte 0xd
3031
+ .uleb128 0x26
3032
+ .4byte .LASF155
3033
+ .byte 0xe
3034
+ .uleb128 0x26
3035
+ .4byte .LASF156
3036
+ .byte 0xf
3037
+ .uleb128 0x26
3038
+ .4byte .LASF157
3039
+ .byte 0x10
3040
+ .uleb128 0x26
3041
+ .4byte .LASF158
3042
+ .byte 0x11
3043
+ .uleb128 0x26
3044
+ .4byte .LASF159
3045
+ .byte 0x12
3046
+ .uleb128 0x26
3047
+ .4byte .LASF160
3048
+ .byte 0x13
3049
+ .uleb128 0x26
3050
+ .4byte .LASF161
3051
+ .byte 0x14
3052
+ .uleb128 0x26
3053
+ .4byte .LASF162
3054
+ .byte 0x15
3055
+ .uleb128 0x26
3056
+ .4byte .LASF163
3057
+ .byte 0x16
3058
+ .uleb128 0x26
3059
+ .4byte .LASF164
3060
+ .byte 0x17
3061
+ .uleb128 0x26
3062
+ .4byte .LASF165
3063
+ .byte 0x18
3064
+ .uleb128 0x26
3065
+ .4byte .LASF166
3066
+ .byte 0x19
3067
+ .uleb128 0x26
3068
+ .4byte .LASF167
3069
+ .byte 0x1a
3070
+ .uleb128 0x26
3071
+ .4byte .LASF168
3072
+ .byte 0x1b
3073
+ .uleb128 0x26
3074
+ .4byte .LASF169
3075
+ .byte 0x1c
3076
+ .uleb128 0x26
3077
+ .4byte .LASF170
3078
+ .byte 0x1d
3079
+ .uleb128 0x26
3080
+ .4byte .LASF171
3081
+ .byte 0x1e
3082
+ .uleb128 0x26
3083
+ .4byte .LASF172
3084
+ .byte 0x1f
3085
+ .uleb128 0x26
3086
+ .4byte .LASF173
3087
+ .byte 0x20
3088
+ .uleb128 0x26
3089
+ .4byte .LASF174
3090
+ .byte 0x21
3091
+ .uleb128 0x26
3092
+ .4byte .LASF175
3093
+ .byte 0x22
3094
+ .uleb128 0x26
3095
+ .4byte .LASF176
3096
+ .byte 0x23
3097
+ .uleb128 0x26
3098
+ .4byte .LASF177
3099
+ .byte 0x24
3100
+ .uleb128 0x26
3101
+ .4byte .LASF178
3102
+ .byte 0x25
3103
+ .uleb128 0x26
3104
+ .4byte .LASF179
3105
+ .byte 0x26
3106
+ .uleb128 0x26
3107
+ .4byte .LASF180
3108
+ .byte 0x27
3109
+ .uleb128 0x26
3110
+ .4byte .LASF181
3111
+ .byte 0x28
3112
+ .uleb128 0x26
3113
+ .4byte .LASF182
3114
+ .byte 0x29
3115
+ .uleb128 0x26
3116
+ .4byte .LASF183
3117
+ .byte 0x2a
3118
+ .uleb128 0x26
3119
+ .4byte .LASF184
3120
+ .byte 0x2b
3121
+ .uleb128 0x26
3122
+ .4byte .LASF185
3123
+ .byte 0x2c
3124
+ .uleb128 0x26
3125
+ .4byte .LASF186
3126
+ .byte 0x2d
3127
+ .uleb128 0x26
3128
+ .4byte .LASF187
3129
+ .byte 0x2e
3130
+ .uleb128 0x26
3131
+ .4byte .LASF188
3132
+ .byte 0x2f
3133
+ .uleb128 0x26
3134
+ .4byte .LASF189
3135
+ .byte 0x30
3136
+ .uleb128 0x26
3137
+ .4byte .LASF190
3138
+ .byte 0x31
3139
+ .uleb128 0x26
3140
+ .4byte .LASF191
3141
+ .byte 0x32
3142
+ .uleb128 0x26
3143
+ .4byte .LASF192
3144
+ .byte 0x33
3145
+ .uleb128 0x26
3146
+ .4byte .LASF193
3147
+ .byte 0x34
3148
+ .uleb128 0x26
3149
+ .4byte .LASF194
3150
+ .byte 0x35
3151
+ .uleb128 0x26
3152
+ .4byte .LASF195
3153
+ .byte 0x36
3154
+ .uleb128 0x26
3155
+ .4byte .LASF196
3156
+ .byte 0x37
3157
+ .uleb128 0x26
3158
+ .4byte .LASF197
3159
+ .byte 0x38
3160
+ .uleb128 0x26
3161
+ .4byte .LASF198
3162
+ .byte 0x39
3163
+ .uleb128 0x26
3164
+ .4byte .LASF199
3165
+ .byte 0x3a
3166
+ .uleb128 0x26
3167
+ .4byte .LASF200
3168
+ .byte 0x3b
3169
+ .uleb128 0x26
3170
+ .4byte .LASF201
3171
+ .byte 0x3c
3172
+ .uleb128 0x26
3173
+ .4byte .LASF202
3174
+ .byte 0x3d
3175
+ .uleb128 0x26
3176
+ .4byte .LASF203
3177
+ .byte 0x3e
3178
+ .uleb128 0x26
3179
+ .4byte .LASF204
3180
+ .byte 0x3f
3181
+ .uleb128 0x26
3182
+ .4byte .LASF205
3183
+ .byte 0x40
3184
+ .uleb128 0x26
3185
+ .4byte .LASF206
3186
+ .byte 0x41
3187
+ .uleb128 0x26
3188
+ .4byte .LASF207
3189
+ .byte 0x42
3190
+ .uleb128 0x26
3191
+ .4byte .LASF208
3192
+ .byte 0x43
3193
+ .uleb128 0x26
3194
+ .4byte .LASF209
3195
+ .byte 0x44
3196
+ .uleb128 0x26
3197
+ .4byte .LASF210
3198
+ .byte 0x45
3199
+ .uleb128 0x26
3200
+ .4byte .LASF211
3201
+ .byte 0x46
3202
+ .uleb128 0x26
3203
+ .4byte .LASF212
3204
+ .byte 0x47
3205
+ .uleb128 0x26
3206
+ .4byte .LASF213
3207
+ .byte 0x48
3208
+ .uleb128 0x26
3209
+ .4byte .LASF214
3210
+ .byte 0x49
3211
+ .uleb128 0x26
3212
+ .4byte .LASF215
3213
+ .byte 0x4a
3214
+ .uleb128 0x26
3215
+ .4byte .LASF216
3216
+ .byte 0x4b
3217
+ .uleb128 0x26
3218
+ .4byte .LASF217
3219
+ .byte 0x4c
3220
+ .uleb128 0x26
3221
+ .4byte .LASF218
3222
+ .byte 0x4d
3223
+ .uleb128 0x26
3224
+ .4byte .LASF219
3225
+ .byte 0x4e
3226
+ .uleb128 0x26
3227
+ .4byte .LASF220
3228
+ .byte 0x4f
3229
+ .uleb128 0x26
3230
+ .4byte .LASF221
3231
+ .byte 0x50
3232
+ .uleb128 0x26
3233
+ .4byte .LASF222
3234
+ .byte 0x51
3235
+ .uleb128 0x26
3236
+ .4byte .LASF223
3237
+ .byte 0x52
3238
+ .uleb128 0x26
3239
+ .4byte .LASF224
3240
+ .byte 0x53
3241
+ .uleb128 0x26
3242
+ .4byte .LASF225
3243
+ .byte 0x54
3244
+ .uleb128 0x26
3245
+ .4byte .LASF226
3246
+ .byte 0x55
3247
+ .uleb128 0x26
3248
+ .4byte .LASF227
3249
+ .byte 0x56
3250
+ .uleb128 0x26
3251
+ .4byte .LASF228
3252
+ .byte 0x57
3253
+ .uleb128 0x26
3254
+ .4byte .LASF229
3255
+ .byte 0x58
3256
+ .uleb128 0x26
3257
+ .4byte .LASF230
3258
+ .byte 0x59
3259
+ .uleb128 0x26
3260
+ .4byte .LASF231
3261
+ .byte 0x5a
3262
+ .uleb128 0x26
3263
+ .4byte .LASF232
3264
+ .byte 0x5b
3265
+ .uleb128 0x26
3266
+ .4byte .LASF233
3267
+ .byte 0x5c
3268
+ .uleb128 0x26
3269
+ .4byte .LASF234
3270
+ .byte 0x5d
3271
+ .uleb128 0x26
3272
+ .4byte .LASF235
3273
+ .byte 0x5e
3274
+ .uleb128 0x26
3275
+ .4byte .LASF236
3276
+ .byte 0x5f
3277
+ .uleb128 0x26
3278
+ .4byte .LASF237
3279
+ .byte 0x60
3280
+ .uleb128 0x26
3281
+ .4byte .LASF238
3282
+ .byte 0x61
3283
+ .uleb128 0x26
3284
+ .4byte .LASF239
3285
+ .byte 0x62
3286
+ .uleb128 0x27
3287
+ .4byte .LASF240
3288
+ .sleb128 -1
3289
+ .byte 0
3290
+ .uleb128 0x28
3291
+ .byte 0x4
3292
+ .4byte 0x7f
3293
+ .byte 0x1d
3294
+ .byte 0xf6
3295
+ .4byte 0xb2c
3296
+ .uleb128 0x26
3297
+ .4byte .LASF241
3298
+ .byte 0x5
3299
+ .byte 0
3300
+ .uleb128 0x11
3301
+ .4byte .LASF242
3302
+ .byte 0x40
3303
+ .byte 0x15
3304
+ .byte 0xc
3305
+ .4byte 0xba5
3306
+ .uleb128 0x12
3307
+ .4byte .LASF243
3308
+ .byte 0x15
3309
+ .byte 0x22
3310
+ .4byte 0x3b
3311
+ .byte 0
3312
+ .uleb128 0x1a
3313
+ .string "tbu"
3314
+ .byte 0x15
3315
+ .byte 0x23
3316
+ .4byte 0x7f
3317
+ .byte 0x8
3318
+ .uleb128 0x1a
3319
+ .string "tbl"
3320
+ .byte 0x15
3321
+ .byte 0x24
3322
+ .4byte 0x7f
3323
+ .byte 0xc
3324
+ .uleb128 0x12
3325
+ .4byte .LASF244
3326
+ .byte 0x15
3327
+ .byte 0x25
3328
+ .4byte 0x3b
3329
+ .byte 0x10
3330
+ .uleb128 0x12
3331
+ .4byte .LASF245
3332
+ .byte 0x15
3333
+ .byte 0x26
3334
+ .4byte 0x8d
3335
+ .byte 0x18
3336
+ .uleb128 0x12
3337
+ .4byte .LASF246
3338
+ .byte 0x15
3339
+ .byte 0x29
3340
+ .4byte 0x3b
3341
+ .byte 0x20
3342
+ .uleb128 0x12
3343
+ .4byte .LASF247
3344
+ .byte 0x15
3345
+ .byte 0x2a
3346
+ .4byte 0x3b
3347
+ .byte 0x28
3348
+ .uleb128 0x12
3349
+ .4byte .LASF248
3350
+ .byte 0x15
3351
+ .byte 0x2c
3352
+ .4byte 0x3b
3353
+ .byte 0x30
3354
+ .uleb128 0x12
3355
+ .4byte .LASF249
3356
+ .byte 0x15
3357
+ .byte 0x2d
3358
+ .4byte 0x3b
3359
+ .byte 0x38
3360
+ .byte 0
3361
+ .uleb128 0x11
3362
+ .4byte .LASF250
3363
+ .byte 0x18
3364
+ .byte 0x16
3365
+ .byte 0x22
3366
+ .4byte 0xbed
3367
+ .uleb128 0x12
3368
+ .4byte .LASF251
3369
+ .byte 0x16
3370
+ .byte 0x23
3371
+ .4byte 0xa3
3372
+ .byte 0
3373
+ .uleb128 0x12
3374
+ .4byte .LASF252
3375
+ .byte 0x16
3376
+ .byte 0x24
3377
+ .4byte 0xa3
3378
+ .byte 0x4
3379
+ .uleb128 0x1a
3380
+ .string "id"
3381
+ .byte 0x16
3382
+ .byte 0x25
3383
+ .4byte 0xa3
3384
+ .byte 0x8
3385
+ .uleb128 0x12
3386
+ .4byte .LASF253
3387
+ .byte 0x16
3388
+ .byte 0x26
3389
+ .4byte 0xa3
3390
+ .byte 0xc
3391
+ .uleb128 0x12
3392
+ .4byte .LASF254
3393
+ .byte 0x16
3394
+ .byte 0x27
3395
+ .4byte 0x100
3396
+ .byte 0x10
3397
+ .byte 0
3398
+ .uleb128 0x19
3399
+ .4byte .LASF255
3400
+ .2byte 0x1c8
3401
+ .byte 0x16
3402
+ .byte 0x2a
3403
+ .4byte 0xe23
3404
+ .uleb128 0x1a
3405
+ .string "bd"
3406
+ .byte 0x16
3407
+ .byte 0x2b
3408
+ .4byte 0x881
3409
+ .byte 0
3410
+ .uleb128 0x12
3411
+ .4byte .LASF256
3412
+ .byte 0x16
3413
+ .byte 0x2c
3414
+ .4byte 0x3b
3415
+ .byte 0x8
3416
+ .uleb128 0x12
3417
+ .4byte .LASF253
3418
+ .byte 0x16
3419
+ .byte 0x2d
3420
+ .4byte 0x7f
3421
+ .byte 0x10
3422
+ .uleb128 0x12
3423
+ .4byte .LASF257
3424
+ .byte 0x16
3425
+ .byte 0x2e
3426
+ .4byte 0x3b
3427
+ .byte 0x18
3428
+ .uleb128 0x12
3429
+ .4byte .LASF258
3430
+ .byte 0x16
3431
+ .byte 0x2f
3432
+ .4byte 0x3b
3433
+ .byte 0x20
3434
+ .uleb128 0x12
3435
+ .4byte .LASF259
3436
+ .byte 0x16
3437
+ .byte 0x31
3438
+ .4byte 0x3b
3439
+ .byte 0x28
3440
+ .uleb128 0x12
3441
+ .4byte .LASF260
3442
+ .byte 0x16
3443
+ .byte 0x32
3444
+ .4byte 0x3b
3445
+ .byte 0x30
3446
+ .uleb128 0x12
3447
+ .4byte .LASF261
3448
+ .byte 0x16
3449
+ .byte 0x3e
3450
+ .4byte 0x3b
3451
+ .byte 0x38
3452
+ .uleb128 0x12
3453
+ .4byte .LASF262
3454
+ .byte 0x16
3455
+ .byte 0x42
3456
+ .4byte 0x3b
3457
+ .byte 0x40
3458
+ .uleb128 0x12
3459
+ .4byte .LASF263
3460
+ .byte 0x16
3461
+ .byte 0x43
3462
+ .4byte 0x3b
3463
+ .byte 0x48
3464
+ .uleb128 0x12
3465
+ .4byte .LASF264
3466
+ .byte 0x16
3467
+ .byte 0x45
3468
+ .4byte 0x3b
3469
+ .byte 0x50
3470
+ .uleb128 0x12
3471
+ .4byte .LASF265
3472
+ .byte 0x16
3473
+ .byte 0x46
3474
+ .4byte 0x3b
3475
+ .byte 0x58
3476
+ .uleb128 0x12
3477
+ .4byte .LASF266
3478
+ .byte 0x16
3479
+ .byte 0x47
3480
+ .4byte 0x3b
3481
+ .byte 0x60
3482
+ .uleb128 0x12
3483
+ .4byte .LASF267
3484
+ .byte 0x16
3485
+ .byte 0x48
3486
+ .4byte 0xc4
3487
+ .byte 0x68
3488
+ .uleb128 0x12
3489
+ .4byte .LASF268
3490
+ .byte 0x16
3491
+ .byte 0x49
3492
+ .4byte 0x3b
3493
+ .byte 0x70
3494
+ .uleb128 0x12
3495
+ .4byte .LASF269
3496
+ .byte 0x16
3497
+ .byte 0x4a
3498
+ .4byte 0x3b
3499
+ .byte 0x78
3500
+ .uleb128 0x12
3501
+ .4byte .LASF270
3502
+ .byte 0x16
3503
+ .byte 0x4b
3504
+ .4byte 0x3b
3505
+ .byte 0x80
3506
+ .uleb128 0x12
3507
+ .4byte .LASF271
3508
+ .byte 0x16
3509
+ .byte 0x4c
3510
+ .4byte 0x3b
3511
+ .byte 0x88
3512
+ .uleb128 0x12
3513
+ .4byte .LASF272
3514
+ .byte 0x16
3515
+ .byte 0x4d
3516
+ .4byte 0xe23
3517
+ .byte 0x90
3518
+ .uleb128 0x12
3519
+ .4byte .LASF273
3520
+ .byte 0x16
3521
+ .byte 0x50
3522
+ .4byte 0x16e
3523
+ .byte 0x98
3524
+ .uleb128 0x12
3525
+ .4byte .LASF274
3526
+ .byte 0x16
3527
+ .byte 0x51
3528
+ .4byte 0x16e
3529
+ .byte 0xa0
3530
+ .uleb128 0x12
3531
+ .4byte .LASF275
3532
+ .byte 0x16
3533
+ .byte 0x52
3534
+ .4byte 0x1a1
3535
+ .byte 0xa8
3536
+ .uleb128 0x12
3537
+ .4byte .LASF276
3538
+ .byte 0x16
3539
+ .byte 0x57
3540
+ .4byte 0x174
3541
+ .byte 0xb8
3542
+ .uleb128 0x12
3543
+ .4byte .LASF277
3544
+ .byte 0x16
3545
+ .byte 0x58
3546
+ .4byte 0x126
3547
+ .byte 0xc0
3548
+ .uleb128 0x12
3549
+ .4byte .LASF278
3550
+ .byte 0x16
3551
+ .byte 0x59
3552
+ .4byte 0x3b
3553
+ .byte 0xc8
3554
+ .uleb128 0x12
3555
+ .4byte .LASF279
3556
+ .byte 0x16
3557
+ .byte 0x5b
3558
+ .4byte 0xe2e
3559
+ .byte 0xd0
3560
+ .uleb128 0x12
3561
+ .4byte .LASF280
3562
+ .byte 0x16
3563
+ .byte 0x5c
3564
+ .4byte 0xe2e
3565
+ .byte 0xd8
3566
+ .uleb128 0x12
3567
+ .4byte .LASF281
3568
+ .byte 0x16
3569
+ .byte 0x5e
3570
+ .4byte 0x174
3571
+ .byte 0xe0
3572
+ .uleb128 0x12
3573
+ .4byte .LASF282
3574
+ .byte 0x16
3575
+ .byte 0x5f
3576
+ .4byte 0x174
3577
+ .byte 0xe8
3578
+ .uleb128 0x1a
3579
+ .string "jt"
3580
+ .byte 0x16
3581
+ .byte 0x60
3582
+ .4byte 0xe39
3583
+ .byte 0xf0
3584
+ .uleb128 0x12
3585
+ .4byte .LASF283
3586
+ .byte 0x16
3587
+ .byte 0x61
3588
+ .4byte 0xe3f
3589
+ .byte 0xf8
3590
+ .uleb128 0x16
3591
+ .4byte .LASF284
3592
+ .byte 0x16
3593
+ .byte 0x6b
3594
+ .4byte 0x7f
3595
+ .2byte 0x118
3596
+ .uleb128 0x16
3597
+ .4byte .LASF285
3598
+ .byte 0x16
3599
+ .byte 0x6c
3600
+ .4byte 0x7f
3601
+ .2byte 0x11c
3602
+ .uleb128 0x16
3603
+ .4byte .LASF286
3604
+ .byte 0x16
3605
+ .byte 0x6e
3606
+ .4byte 0x3b
3607
+ .2byte 0x120
3608
+ .uleb128 0x16
3609
+ .4byte .LASF287
3610
+ .byte 0x16
3611
+ .byte 0x6f
3612
+ .4byte 0x3b
3613
+ .2byte 0x128
3614
+ .uleb128 0x16
3615
+ .4byte .LASF288
3616
+ .byte 0x16
3617
+ .byte 0x70
3618
+ .4byte 0x3b
3619
+ .2byte 0x130
3620
+ .uleb128 0x16
3621
+ .4byte .LASF289
3622
+ .byte 0x16
3623
+ .byte 0x79
3624
+ .4byte 0x16e
3625
+ .2byte 0x138
3626
+ .uleb128 0x16
3627
+ .4byte .LASF110
3628
+ .byte 0x16
3629
+ .byte 0x7a
3630
+ .4byte 0xb2c
3631
+ .2byte 0x140
3632
+ .uleb128 0x16
3633
+ .4byte .LASF290
3634
+ .byte 0x16
3635
+ .byte 0x80
3636
+ .4byte 0x100
3637
+ .2byte 0x180
3638
+ .uleb128 0x16
3639
+ .4byte .LASF291
3640
+ .byte 0x16
3641
+ .byte 0x81
3642
+ .4byte 0x100
3643
+ .2byte 0x188
3644
+ .uleb128 0x16
3645
+ .4byte .LASF292
3646
+ .byte 0x16
3647
+ .byte 0x87
3648
+ .4byte 0xb9
3649
+ .2byte 0x190
3650
+ .uleb128 0x16
3651
+ .4byte .LASF293
3652
+ .byte 0x16
3653
+ .byte 0x8a
3654
+ .4byte 0x54
3655
+ .2byte 0x198
3656
+ .uleb128 0x16
3657
+ .4byte .LASF294
3658
+ .byte 0x16
3659
+ .byte 0x8c
3660
+ .4byte 0xba5
3661
+ .2byte 0x1a0
3662
+ .uleb128 0x16
3663
+ .4byte .LASF295
3664
+ .byte 0x16
3665
+ .byte 0x8d
3666
+ .4byte 0x100
3667
+ .2byte 0x1b8
3668
+ .uleb128 0x16
3669
+ .4byte .LASF296
3670
+ .byte 0x16
3671
+ .byte 0x8e
3672
+ .4byte 0x54
3673
+ .2byte 0x1c0
3674
+ .byte 0
3675
+ .uleb128 0x8
3676
+ .byte 0x8
3677
+ .4byte 0xbed
3678
+ .uleb128 0xe
3679
+ .4byte .LASF297
3680
+ .uleb128 0x8
3681
+ .byte 0x8
3682
+ .4byte 0xe29
3683
+ .uleb128 0xe
3684
+ .4byte .LASF298
3685
+ .uleb128 0x8
3686
+ .byte 0x8
3687
+ .4byte 0xe34
3688
+ .uleb128 0xb
3689
+ .4byte 0xdc
3690
+ .4byte 0xe4f
3691
+ .uleb128 0x10
3692
+ .4byte 0xcf
3693
+ .byte 0x1f
3694
+ .byte 0
3695
+ .uleb128 0x2
3696
+ .4byte .LASF299
3697
+ .byte 0x16
3698
+ .byte 0x9b
3699
+ .4byte 0xbed
3700
+ .uleb128 0x9
3701
+ .4byte 0xe4f
3702
+ .uleb128 0x4
3703
+ .4byte .LASF300
3704
+ .byte 0x4
3705
+ .byte 0xad
3706
+ .4byte 0x100
3707
+ .uleb128 0xb
3708
+ .4byte 0x94
3709
+ .4byte 0xe75
3710
+ .uleb128 0xc
3711
+ .byte 0
3712
+ .uleb128 0x4
3713
+ .4byte .LASF301
3714
+ .byte 0x4
3715
+ .byte 0xaf
3716
+ .4byte 0xe6a
3717
+ .uleb128 0x4
3718
+ .4byte .LASF302
3719
+ .byte 0x4
3720
+ .byte 0xb0
3721
+ .4byte 0xe6a
3722
+ .uleb128 0x4
3723
+ .4byte .LASF303
3724
+ .byte 0x4
3725
+ .byte 0xfe
3726
+ .4byte 0x100
3727
+ .uleb128 0x4
3728
+ .4byte .LASF304
3729
+ .byte 0x4
3730
+ .byte 0xff
3731
+ .4byte 0x100
3732
+ .uleb128 0xd
3733
+ .4byte .LASF305
3734
+ .byte 0x4
3735
+ .2byte 0x100
3736
+ .4byte 0x100
3737
+ .uleb128 0x11
3738
+ .4byte .LASF306
3739
+ .byte 0x4
3740
+ .byte 0x17
3741
+ .byte 0x2e
3742
+ .4byte 0xec6
3743
+ .uleb128 0x12
3744
+ .4byte .LASF307
3745
+ .byte 0x17
3746
+ .byte 0x2f
3747
+ .4byte 0x11b
3748
+ .byte 0
3749
+ .byte 0
3750
+ .uleb128 0x8
3751
+ .byte 0x8
3752
+ .4byte 0x29
3753
+ .uleb128 0xb
3754
+ .4byte 0x94
3755
+ .4byte 0xedc
3756
+ .uleb128 0x10
3757
+ .4byte 0xcf
3758
+ .byte 0x5
3759
+ .byte 0
3760
+ .uleb128 0xd
3761
+ .4byte .LASF308
3762
+ .byte 0x17
3763
+ .2byte 0x1fd
3764
+ .4byte 0xead
3765
+ .uleb128 0xd
3766
+ .4byte .LASF309
3767
+ .byte 0x17
3768
+ .2byte 0x1fe
3769
+ .4byte 0xead
3770
+ .uleb128 0xd
3771
+ .4byte .LASF310
3772
+ .byte 0x17
3773
+ .2byte 0x200
3774
+ .4byte 0xead
3775
+ .uleb128 0xd
3776
+ .4byte .LASF311
3777
+ .byte 0x17
3778
+ .2byte 0x205
3779
+ .4byte 0xe3f
3780
+ .uleb128 0xd
3781
+ .4byte .LASF312
3782
+ .byte 0x17
3783
+ .2byte 0x206
3784
+ .4byte 0xe3f
3785
+ .uleb128 0xb
3786
+ .4byte 0xdc
3787
+ .4byte 0xf28
3788
+ .uleb128 0x10
3789
+ .4byte 0xcf
3790
+ .byte 0x3f
3791
+ .byte 0
3792
+ .uleb128 0xd
3793
+ .4byte .LASF313
3794
+ .byte 0x17
3795
+ .2byte 0x207
3796
+ .4byte 0xf18
3797
+ .uleb128 0xd
3798
+ .4byte .LASF314
3799
+ .byte 0x17
3800
+ .2byte 0x209
3801
+ .4byte 0xecc
3802
+ .uleb128 0xd
3803
+ .4byte .LASF315
3804
+ .byte 0x17
3805
+ .2byte 0x20a
3806
+ .4byte 0xecc
3807
+ .uleb128 0xd
3808
+ .4byte .LASF316
3809
+ .byte 0x17
3810
+ .2byte 0x20b
3811
+ .4byte 0xead
3812
+ .uleb128 0xd
3813
+ .4byte .LASF317
3814
+ .byte 0x17
3815
+ .2byte 0x20c
3816
+ .4byte 0xead
3817
+ .uleb128 0xd
3818
+ .4byte .LASF318
3819
+ .byte 0x17
3820
+ .2byte 0x20d
3821
+ .4byte 0xec6
3822
+ .uleb128 0xb
3823
+ .4byte 0xec6
3824
+ .4byte 0xf80
3825
+ .uleb128 0x10
3826
+ .4byte 0xcf
3827
+ .byte 0x3
3828
+ .byte 0
3829
+ .uleb128 0xd
3830
+ .4byte .LASF319
3831
+ .byte 0x17
3832
+ .2byte 0x20e
3833
+ .4byte 0xf70
3834
+ .uleb128 0xd
3835
+ .4byte .LASF320
3836
+ .byte 0x17
3837
+ .2byte 0x20f
3838
+ .4byte 0xec6
3839
+ .uleb128 0xd
3840
+ .4byte .LASF321
3841
+ .byte 0x17
3842
+ .2byte 0x210
3843
+ .4byte 0x54
3844
+ .uleb128 0xb
3845
+ .4byte 0x9e
3846
+ .4byte 0xfb4
3847
+ .uleb128 0x10
3848
+ .4byte 0xcf
3849
+ .byte 0x5
3850
+ .byte 0
3851
+ .uleb128 0x7
3852
+ .4byte 0xfa4
3853
+ .uleb128 0xd
3854
+ .4byte .LASF322
3855
+ .byte 0x17
3856
+ .2byte 0x211
3857
+ .4byte 0xfb4
3858
+ .uleb128 0xd
3859
+ .4byte .LASF323
3860
+ .byte 0x17
3861
+ .2byte 0x212
3862
+ .4byte 0xfb4
3863
+ .uleb128 0xd
3864
+ .4byte .LASF324
3865
+ .byte 0x17
3866
+ .2byte 0x216
3867
+ .4byte 0xf5
3868
+ .uleb128 0xd
3869
+ .4byte .LASF325
3870
+ .byte 0x17
3871
+ .2byte 0x217
3872
+ .4byte 0xf5
3873
+ .uleb128 0xd
3874
+ .4byte .LASF326
3875
+ .byte 0x17
3876
+ .2byte 0x219
3877
+ .4byte 0x54
3878
+ .uleb128 0xd
3879
+ .4byte .LASF327
3880
+ .byte 0x17
3881
+ .2byte 0x220
3882
+ .4byte 0x89f
3883
+ .uleb128 0xd
3884
+ .4byte .LASF328
3885
+ .byte 0x17
3886
+ .2byte 0x222
3887
+ .4byte 0xa3
3888
+ .uleb128 0xd
3889
+ .4byte .LASF329
3890
+ .byte 0x17
3891
+ .2byte 0x224
3892
+ .4byte 0xa3
3893
+ .uleb128 0xd
3894
+ .4byte .LASF330
3895
+ .byte 0x17
3896
+ .2byte 0x230
3897
+ .4byte 0xead
3898
+ .uleb128 0x29
3899
+ .4byte .LASF332
3900
+ .byte 0x4
3901
+ .4byte 0x7f
3902
+ .byte 0x17
3903
+ .2byte 0x286
3904
+ .4byte 0x104f
3905
+ .uleb128 0x26
3906
+ .4byte .LASF333
3907
+ .byte 0
3908
+ .uleb128 0x26
3909
+ .4byte .LASF334
3910
+ .byte 0x1
3911
+ .uleb128 0x26
3912
+ .4byte .LASF335
3913
+ .byte 0x2
3914
+ .uleb128 0x26
3915
+ .4byte .LASF336
3916
+ .byte 0x3
3917
+ .byte 0
3918
+ .uleb128 0xd
3919
+ .4byte .LASF337
3920
+ .byte 0x17
3921
+ .2byte 0x28c
3922
+ .4byte 0x1025
3923
+ .uleb128 0x4
3924
+ .4byte .LASF338
3925
+ .byte 0x19
3926
+ .byte 0x2b
3927
+ .4byte 0x13a
3928
+ .uleb128 0x4
3929
+ .4byte .LASF339
3930
+ .byte 0x19
3931
+ .byte 0x2b
3932
+ .4byte 0x13a
3933
+ .uleb128 0x11
3934
+ .4byte .LASF340
3935
+ .byte 0x28
3936
+ .byte 0x1a
3937
+ .byte 0x39
3938
+ .4byte 0x10ba
3939
+ .uleb128 0x1a
3940
+ .string "dev"
3941
+ .byte 0x1a
3942
+ .byte 0x3a
3943
+ .4byte 0x126
3944
+ .byte 0
3945
+ .uleb128 0x12
3946
+ .4byte .LASF341
3947
+ .byte 0x1a
3948
+ .byte 0x3b
3949
+ .4byte 0x126
3950
+ .byte 0x8
3951
+ .uleb128 0x12
3952
+ .4byte .LASF342
3953
+ .byte 0x1a
3954
+ .byte 0x3c
3955
+ .4byte 0x54
3956
+ .byte 0x10
3957
+ .uleb128 0x12
3958
+ .4byte .LASF343
3959
+ .byte 0x1a
3960
+ .byte 0x3d
3961
+ .4byte 0xd6
3962
+ .byte 0x18
3963
+ .uleb128 0x12
3964
+ .4byte .LASF344
3965
+ .byte 0x1a
3966
+ .byte 0x3e
3967
+ .4byte 0x10de
3968
+ .byte 0x20
3969
+ .byte 0
3970
+ .uleb128 0x13
3971
+ .4byte 0x100
3972
+ .4byte 0x10d8
3973
+ .uleb128 0x14
3974
+ .4byte 0x10d8
3975
+ .uleb128 0x14
3976
+ .4byte 0x100
3977
+ .uleb128 0x14
3978
+ .4byte 0x100
3979
+ .uleb128 0x14
3980
+ .4byte 0x126
3981
+ .byte 0
3982
+ .uleb128 0x8
3983
+ .byte 0x8
3984
+ .4byte 0x1071
3985
+ .uleb128 0x8
3986
+ .byte 0x8
3987
+ .4byte 0x10ba
3988
+ .uleb128 0x11
3989
+ .4byte .LASF345
3990
+ .byte 0x38
3991
+ .byte 0x1b
3992
+ .byte 0xc
3993
+ .4byte 0x1115
3994
+ .uleb128 0x12
3995
+ .4byte .LASF346
3996
+ .byte 0x1b
3997
+ .byte 0xd
3998
+ .4byte 0x1071
3999
+ .byte 0
4000
+ .uleb128 0x12
4001
+ .4byte .LASF347
4002
+ .byte 0x1b
4003
+ .byte 0x10
4004
+ .4byte 0x126
4005
+ .byte 0x28
4006
+ .uleb128 0x12
4007
+ .4byte .LASF348
4008
+ .byte 0x1b
4009
+ .byte 0x11
4010
+ .4byte 0x100
4011
+ .byte 0x30
4012
+ .byte 0
4013
+ .uleb128 0x25
4014
+ .4byte .LASF349
4015
+ .byte 0x4
4016
+ .4byte 0x7f
4017
+ .byte 0x1c
4018
+ .byte 0xb
4019
+ .4byte 0x116e
4020
+ .uleb128 0x26
4021
+ .4byte .LASF350
4022
+ .byte 0
4023
+ .uleb128 0x26
4024
+ .4byte .LASF351
4025
+ .byte 0x1
4026
+ .uleb128 0x26
4027
+ .4byte .LASF352
4028
+ .byte 0x2
4029
+ .uleb128 0x26
4030
+ .4byte .LASF353
4031
+ .byte 0x3
4032
+ .uleb128 0x26
4033
+ .4byte .LASF354
4034
+ .byte 0x4
4035
+ .uleb128 0x26
4036
+ .4byte .LASF355
4037
+ .byte 0x5
4038
+ .uleb128 0x26
4039
+ .4byte .LASF356
4040
+ .byte 0x6
4041
+ .uleb128 0x26
4042
+ .4byte .LASF357
4043
+ .byte 0x7
4044
+ .uleb128 0x26
4045
+ .4byte .LASF358
4046
+ .byte 0x8
4047
+ .uleb128 0x26
4048
+ .4byte .LASF359
4049
+ .byte 0x9
4050
+ .uleb128 0x26
4051
+ .4byte .LASF360
4052
+ .byte 0xa
4053
+ .uleb128 0x26
4054
+ .4byte .LASF361
4055
+ .byte 0xb
4056
+ .byte 0
4057
+ .uleb128 0x2a
4058
+ .string "gd"
4059
+ .byte 0x1
4060
+ .byte 0xf
4061
+ .4byte 0x1178
4062
+ .uleb128 0x8
4063
+ .byte 0x8
4064
+ .4byte 0xe5a
4065
+ .uleb128 0x28
4066
+ .byte 0x4
4067
+ .4byte 0x7f
4068
+ .byte 0x1
4069
+ .byte 0x40
4070
+ .4byte 0x11a3
4071
+ .uleb128 0x26
4072
+ .4byte .LASF362
4073
+ .byte 0
4074
+ .uleb128 0x26
4075
+ .4byte .LASF363
4076
+ .byte 0x1
4077
+ .uleb128 0x26
4078
+ .4byte .LASF364
4079
+ .byte 0x2
4080
+ .uleb128 0x26
4081
+ .4byte .LASF365
4082
+ .byte 0x3
4083
+ .byte 0
4084
+ .uleb128 0x28
4085
+ .byte 0x4
4086
+ .4byte 0x7f
4087
+ .byte 0x1
4088
+ .byte 0x47
4089
+ .4byte 0x11da
4090
+ .uleb128 0x26
4091
+ .4byte .LASF366
4092
+ .byte 0
4093
+ .uleb128 0x26
4094
+ .4byte .LASF367
4095
+ .byte 0x1
4096
+ .uleb128 0x26
4097
+ .4byte .LASF368
4098
+ .byte 0x2
4099
+ .uleb128 0x26
4100
+ .4byte .LASF369
4101
+ .byte 0x3
4102
+ .uleb128 0x26
4103
+ .4byte .LASF370
4104
+ .byte 0x4
4105
+ .uleb128 0x26
4106
+ .4byte .LASF371
4107
+ .byte 0x5
4108
+ .uleb128 0x26
4109
+ .4byte .LASF372
4110
+ .byte 0x6
4111
+ .byte 0
4112
+ .uleb128 0x28
4113
+ .byte 0x4
4114
+ .4byte 0x7f
4115
+ .byte 0x1
4116
+ .byte 0x51
4117
+ .4byte 0x121d
4118
+ .uleb128 0x26
4119
+ .4byte .LASF373
4120
+ .byte 0
4121
+ .uleb128 0x26
4122
+ .4byte .LASF374
4123
+ .byte 0x1
4124
+ .uleb128 0x26
4125
+ .4byte .LASF375
4126
+ .byte 0x2
4127
+ .uleb128 0x26
4128
+ .4byte .LASF376
4129
+ .byte 0x3
4130
+ .uleb128 0x26
4131
+ .4byte .LASF377
4132
+ .byte 0x4
4133
+ .uleb128 0x26
4134
+ .4byte .LASF378
4135
+ .byte 0x5
4136
+ .uleb128 0x26
4137
+ .4byte .LASF379
4138
+ .byte 0x6
4139
+ .uleb128 0x26
4140
+ .4byte .LASF380
4141
+ .byte 0x7
4142
+ .uleb128 0x26
4143
+ .4byte .LASF381
4144
+ .byte 0x8
4145
+ .byte 0
4146
+ .uleb128 0xb
4147
+ .4byte 0xd6
4148
+ .4byte 0x122d
4149
+ .uleb128 0x10
4150
+ .4byte 0xcf
4151
+ .byte 0x7
4152
+ .byte 0
4153
+ .uleb128 0x2b
4154
+ .4byte .LASF382
4155
+ .byte 0x1
4156
+ .byte 0x5d
4157
+ .4byte 0x121d
4158
+ .uleb128 0x9
4159
+ .byte 0x3
4160
+ .8byte tid_name
4161
+ .uleb128 0x2
4162
+ .4byte .LASF383
4163
+ .byte 0x1
4164
+ .byte 0x68
4165
+ .4byte 0x124d
4166
+ .uleb128 0x8
4167
+ .byte 0x8
4168
+ .4byte 0x1253
4169
+ .uleb128 0x13
4170
+ .4byte 0x54
4171
+ .4byte 0x1262
4172
+ .uleb128 0x14
4173
+ .4byte 0x1262
4174
+ .byte 0
4175
+ .uleb128 0x8
4176
+ .byte 0x8
4177
+ .4byte 0x10e4
4178
+ .uleb128 0x11
4179
+ .4byte .LASF384
4180
+ .byte 0x28
4181
+ .byte 0x1
4182
+ .byte 0x69
4183
+ .4byte 0x12c7
4184
+ .uleb128 0x1a
4185
+ .string "fn"
4186
+ .byte 0x1
4187
+ .byte 0x6a
4188
+ .4byte 0x1242
4189
+ .byte 0
4190
+ .uleb128 0x12
4191
+ .4byte .LASF138
4192
+ .byte 0x1
4193
+ .byte 0x6b
4194
+ .4byte 0xa3
4195
+ .byte 0x8
4196
+ .uleb128 0x1a
4197
+ .string "tid"
4198
+ .byte 0x1
4199
+ .byte 0x6c
4200
+ .4byte 0xa3
4201
+ .byte 0xc
4202
+ .uleb128 0x12
4203
+ .4byte .LASF385
4204
+ .byte 0x1
4205
+ .byte 0x6d
4206
+ .4byte 0xa3
4207
+ .byte 0x10
4208
+ .uleb128 0x12
4209
+ .4byte .LASF386
4210
+ .byte 0x1
4211
+ .byte 0x6e
4212
+ .4byte 0xa3
4213
+ .byte 0x14
4214
+ .uleb128 0x1a
4215
+ .string "ret"
4216
+ .byte 0x1
4217
+ .byte 0x6f
4218
+ .4byte 0x54
4219
+ .byte 0x18
4220
+ .uleb128 0x1a
4221
+ .string "ms"
4222
+ .byte 0x1
4223
+ .byte 0x70
4224
+ .4byte 0x100
4225
+ .byte 0x20
4226
+ .byte 0
4227
+ .uleb128 0x19
4228
+ .4byte .LASF387
4229
+ .2byte 0x148
4230
+ .byte 0x1
4231
+ .byte 0x73
4232
+ .4byte 0x12ee
4233
+ .uleb128 0x12
4234
+ .4byte .LASF388
4235
+ .byte 0x1
4236
+ .byte 0x74
4237
+ .4byte 0x12ee
4238
+ .byte 0
4239
+ .uleb128 0x17
4240
+ .string "num"
4241
+ .byte 0x1
4242
+ .byte 0x75
4243
+ .4byte 0x94
4244
+ .2byte 0x140
4245
+ .byte 0
4246
+ .uleb128 0xb
4247
+ .4byte 0x1268
4248
+ .4byte 0x12fe
4249
+ .uleb128 0x10
4250
+ .4byte 0xcf
4251
+ .byte 0x7
4252
+ .byte 0
4253
+ .uleb128 0x19
4254
+ .4byte .LASF389
4255
+ .2byte 0x560
4256
+ .byte 0x1
4257
+ .byte 0x78
4258
+ .4byte 0x1331
4259
+ .uleb128 0x12
4260
+ .4byte .LASF390
4261
+ .byte 0x1
4262
+ .byte 0x79
4263
+ .4byte 0xa3
4264
+ .byte 0
4265
+ .uleb128 0x1a
4266
+ .string "cpu"
4267
+ .byte 0x1
4268
+ .byte 0x7a
4269
+ .4byte 0x1331
4270
+ .byte 0x8
4271
+ .uleb128 0x16
4272
+ .4byte .LASF391
4273
+ .byte 0x1
4274
+ .byte 0x7b
4275
+ .4byte 0x10e4
4276
+ .2byte 0x528
4277
+ .byte 0
4278
+ .uleb128 0xb
4279
+ .4byte 0x12c7
4280
+ .4byte 0x1341
4281
+ .uleb128 0x10
4282
+ .4byte 0xcf
4283
+ .byte 0x3
4284
+ .byte 0
4285
+ .uleb128 0x2c
4286
+ .string "mpb"
4287
+ .byte 0x1
4288
+ .byte 0x7e
4289
+ .4byte 0x134c
4290
+ .uleb128 0x8
4291
+ .byte 0x8
4292
+ .4byte 0x12fe
4293
+ .uleb128 0x2b
4294
+ .4byte .LASF392
4295
+ .byte 0x1
4296
+ .byte 0x7f
4297
+ .4byte 0x100
4298
+ .uleb128 0x9
4299
+ .byte 0x3
4300
+ .8byte mpb_gd
4301
+ .uleb128 0x11
4302
+ .4byte .LASF393
4303
+ .byte 0x18
4304
+ .byte 0x1
4305
+ .byte 0x95
4306
+ .4byte 0x13af
4307
+ .uleb128 0x1a
4308
+ .string "cid"
4309
+ .byte 0x1
4310
+ .byte 0x96
4311
+ .4byte 0xa3
4312
+ .byte 0
4313
+ .uleb128 0x1a
4314
+ .string "tid"
4315
+ .byte 0x1
4316
+ .byte 0x97
4317
+ .4byte 0xa3
4318
+ .byte 0x4
4319
+ .uleb128 0x1a
4320
+ .string "fn"
4321
+ .byte 0x1
4322
+ .byte 0x98
4323
+ .4byte 0x1242
4324
+ .byte 0x8
4325
+ .uleb128 0x12
4326
+ .4byte .LASF385
4327
+ .byte 0x1
4328
+ .byte 0x99
4329
+ .4byte 0xa3
4330
+ .byte 0x10
4331
+ .uleb128 0x12
4332
+ .4byte .LASF386
4333
+ .byte 0x1
4334
+ .byte 0x9a
4335
+ .4byte 0xa3
4336
+ .byte 0x14
4337
+ .byte 0
4338
+ .uleb128 0x2d
4339
+ .4byte .LASF406
4340
+ .byte 0x1
4341
+ .2byte 0x23f
4342
+ .4byte 0x100
4343
+ .8byte .LFB239
4344
+ .8byte .LFE239-.LFB239
4345
+ .uleb128 0x1
4346
+ .byte 0x9c
4347
+ .4byte 0x14ef
4348
+ .uleb128 0x2e
4349
+ .string "evt"
4350
+ .byte 0x1
4351
+ .2byte 0x23f
4352
+ .4byte 0x54
4353
+ .4byte .LLST61
4354
+ .uleb128 0x2f
4355
+ .4byte .LASF394
4356
+ .byte 0x1
4357
+ .2byte 0x241
4358
+ .4byte 0x54
4359
+ .4byte .LLST62
4360
+ .uleb128 0x30
4361
+ .string "cmd"
4362
+ .byte 0x1
4363
+ .2byte 0x242
4364
+ .4byte 0xe3f
4365
+ .uleb128 0x2
4366
+ .byte 0x91
4367
+ .sleb128 -32
4368
+ .uleb128 0x31
4369
+ .8byte .LVL155
4370
+ .4byte 0x1b59
4371
+ .uleb128 0x32
4372
+ .8byte .LVL157
4373
+ .4byte 0x1b59
4374
+ .4byte 0x1424
4375
+ .uleb128 0x33
4376
+ .uleb128 0x1
4377
+ .byte 0x50
4378
+ .uleb128 0x1
4379
+ .byte 0x35
4380
+ .byte 0
4381
+ .uleb128 0x31
4382
+ .8byte .LVL158
4383
+ .4byte 0x14ef
4384
+ .uleb128 0x31
4385
+ .8byte .LVL162
4386
+ .4byte 0x14ef
4387
+ .uleb128 0x31
4388
+ .8byte .LVL163
4389
+ .4byte 0x14ef
4390
+ .uleb128 0x32
4391
+ .8byte .LVL164
4392
+ .4byte 0x1b59
4393
+ .4byte 0x1462
4394
+ .uleb128 0x33
4395
+ .uleb128 0x1
4396
+ .byte 0x50
4397
+ .uleb128 0x1
4398
+ .byte 0x36
4399
+ .byte 0
4400
+ .uleb128 0x31
4401
+ .8byte .LVL165
4402
+ .4byte 0x14ef
4403
+ .uleb128 0x32
4404
+ .8byte .LVL167
4405
+ .4byte 0x1b59
4406
+ .4byte 0x1486
4407
+ .uleb128 0x33
4408
+ .uleb128 0x1
4409
+ .byte 0x50
4410
+ .uleb128 0x1
4411
+ .byte 0x35
4412
+ .byte 0
4413
+ .uleb128 0x32
4414
+ .8byte .LVL168
4415
+ .4byte 0x24b5
4416
+ .4byte 0x14b1
4417
+ .uleb128 0x33
4418
+ .uleb128 0x1
4419
+ .byte 0x50
4420
+ .uleb128 0x2
4421
+ .byte 0x8f
4422
+ .sleb128 16
4423
+ .uleb128 0x33
4424
+ .uleb128 0x1
4425
+ .byte 0x51
4426
+ .uleb128 0x2
4427
+ .byte 0x8
4428
+ .byte 0x20
4429
+ .uleb128 0x33
4430
+ .uleb128 0x1
4431
+ .byte 0x52
4432
+ .uleb128 0x9
4433
+ .byte 0x3
4434
+ .8byte .LC15
4435
+ .byte 0
4436
+ .uleb128 0x32
4437
+ .8byte .LVL169
4438
+ .4byte 0x24c0
4439
+ .4byte 0x14ce
4440
+ .uleb128 0x33
4441
+ .uleb128 0x1
4442
+ .byte 0x50
4443
+ .uleb128 0x2
4444
+ .byte 0x8f
4445
+ .sleb128 16
4446
+ .uleb128 0x33
4447
+ .uleb128 0x1
4448
+ .byte 0x51
4449
+ .uleb128 0x1
4450
+ .byte 0x30
4451
+ .byte 0
4452
+ .uleb128 0x31
4453
+ .8byte .LVL170
4454
+ .4byte 0x1cdf
4455
+ .uleb128 0x34
4456
+ .8byte .LVL171
4457
+ .4byte 0x1b59
4458
+ .uleb128 0x33
4459
+ .uleb128 0x1
4460
+ .byte 0x50
4461
+ .uleb128 0x1
4462
+ .byte 0x34
4463
+ .byte 0
4464
+ .byte 0
4465
+ .uleb128 0x35
4466
+ .4byte .LASF402
4467
+ .byte 0x1
4468
+ .2byte 0x22f
4469
+ .4byte 0x54
4470
+ .byte 0x1
4471
+ .4byte 0x150d
4472
+ .uleb128 0x36
4473
+ .4byte .LASF395
4474
+ .byte 0x1
4475
+ .2byte 0x231
4476
+ .4byte 0x54
4477
+ .byte 0
4478
+ .uleb128 0x37
4479
+ .4byte .LASF396
4480
+ .byte 0x1
4481
+ .2byte 0x219
4482
+ .8byte .LFB237
4483
+ .8byte .LFE237-.LFB237
4484
+ .uleb128 0x1
4485
+ .byte 0x9c
4486
+ .4byte 0x16f6
4487
+ .uleb128 0x2e
4488
+ .string "evt"
4489
+ .byte 0x1
4490
+ .2byte 0x219
4491
+ .4byte 0x54
4492
+ .4byte .LLST53
4493
+ .uleb128 0x38
4494
+ .4byte 0x178a
4495
+ .8byte .LBB124
4496
+ .4byte .Ldebug_ranges0+0x1c0
4497
+ .byte 0x1
4498
+ .2byte 0x21d
4499
+ .4byte 0x1665
4500
+ .uleb128 0x39
4501
+ .4byte .Ldebug_ranges0+0x1c0
4502
+ .uleb128 0x3a
4503
+ .4byte 0x1797
4504
+ .uleb128 0x2
4505
+ .byte 0x91
4506
+ .sleb128 -48
4507
+ .uleb128 0x3b
4508
+ .4byte 0x17a3
4509
+ .4byte .LLST54
4510
+ .uleb128 0x38
4511
+ .4byte 0x2027
4512
+ .8byte .LBB126
4513
+ .4byte .Ldebug_ranges0+0x1f0
4514
+ .byte 0x1
4515
+ .2byte 0x203
4516
+ .4byte 0x15ac
4517
+ .uleb128 0x3c
4518
+ .4byte 0x2037
4519
+ .4byte .LLST55
4520
+ .uleb128 0x39
4521
+ .4byte .Ldebug_ranges0+0x1f0
4522
+ .uleb128 0x3b
4523
+ .4byte 0x2042
4524
+ .4byte .LLST56
4525
+ .uleb128 0x3b
4526
+ .4byte 0x204d
4527
+ .4byte .LLST57
4528
+ .uleb128 0x3b
4529
+ .4byte 0x2058
4530
+ .4byte .LLST58
4531
+ .byte 0
4532
+ .byte 0
4533
+ .uleb128 0x3d
4534
+ .8byte .LBB131
4535
+ .8byte .LBE131-.LBB131
4536
+ .4byte 0x15c7
4537
+ .uleb128 0x3e
4538
+ .4byte 0x17b2
4539
+ .byte 0
4540
+ .uleb128 0x3d
4541
+ .8byte .LBB132
4542
+ .8byte .LBE132-.LBB132
4543
+ .4byte 0x15e6
4544
+ .uleb128 0x3b
4545
+ .4byte 0x17c0
4546
+ .4byte .LLST59
4547
+ .byte 0
4548
+ .uleb128 0x32
4549
+ .8byte .LVL130
4550
+ .4byte 0x24cb
4551
+ .4byte 0x1611
4552
+ .uleb128 0x33
4553
+ .uleb128 0x1
4554
+ .byte 0x50
4555
+ .uleb128 0x2
4556
+ .byte 0x8f
4557
+ .sleb128 16
4558
+ .uleb128 0x33
4559
+ .uleb128 0x1
4560
+ .byte 0x51
4561
+ .uleb128 0x9
4562
+ .byte 0x3
4563
+ .8byte .LANCHOR3
4564
+ .uleb128 0x33
4565
+ .uleb128 0x1
4566
+ .byte 0x52
4567
+ .uleb128 0x2
4568
+ .byte 0x8
4569
+ .byte 0x30
4570
+ .byte 0
4571
+ .uleb128 0x32
4572
+ .8byte .LVL131
4573
+ .4byte 0x24d4
4574
+ .4byte 0x1630
4575
+ .uleb128 0x33
4576
+ .uleb128 0x1
4577
+ .byte 0x50
4578
+ .uleb128 0x9
4579
+ .byte 0x3
4580
+ .8byte .LC14
4581
+ .byte 0
4582
+ .uleb128 0x32
4583
+ .8byte .LVL132
4584
+ .4byte 0x24df
4585
+ .4byte 0x1656
4586
+ .uleb128 0x33
4587
+ .uleb128 0x1
4588
+ .byte 0x50
4589
+ .uleb128 0x4
4590
+ .byte 0x8
4591
+ .byte 0x82
4592
+ .byte 0x44
4593
+ .byte 0x24
4594
+ .uleb128 0x33
4595
+ .uleb128 0x1
4596
+ .byte 0x51
4597
+ .uleb128 0x1
4598
+ .byte 0x30
4599
+ .uleb128 0x33
4600
+ .uleb128 0x1
4601
+ .byte 0x52
4602
+ .uleb128 0x3
4603
+ .byte 0xa
4604
+ .2byte 0x560
4605
+ .byte 0
4606
+ .uleb128 0x31
4607
+ .8byte .LVL135
4608
+ .4byte 0x24ea
4609
+ .byte 0
4610
+ .byte 0
4611
+ .uleb128 0x3f
4612
+ .4byte 0x2149
4613
+ .8byte .LBB136
4614
+ .8byte .LBE136-.LBB136
4615
+ .byte 0x1
4616
+ .2byte 0x226
4617
+ .4byte 0x16a0
4618
+ .uleb128 0x3c
4619
+ .4byte 0x2155
4620
+ .4byte .LLST60
4621
+ .uleb128 0x40
4622
+ .8byte .LVL150
4623
+ .4byte 0x24f6
4624
+ .uleb128 0x33
4625
+ .uleb128 0x1
4626
+ .byte 0x50
4627
+ .uleb128 0x3
4628
+ .byte 0xa
4629
+ .2byte 0x3e8
4630
+ .byte 0
4631
+ .byte 0
4632
+ .uleb128 0x32
4633
+ .8byte .LVL147
4634
+ .4byte 0x1edd
4635
+ .4byte 0x16c6
4636
+ .uleb128 0x33
4637
+ .uleb128 0x1
4638
+ .byte 0x50
4639
+ .uleb128 0x1
4640
+ .byte 0x30
4641
+ .uleb128 0x33
4642
+ .uleb128 0x1
4643
+ .byte 0x51
4644
+ .uleb128 0x1
4645
+ .byte 0x33
4646
+ .uleb128 0x33
4647
+ .uleb128 0x1
4648
+ .byte 0x52
4649
+ .uleb128 0x6
4650
+ .byte 0x11
4651
+ .sleb128 -559087616
4652
+ .byte 0
4653
+ .uleb128 0x31
4654
+ .8byte .LVL148
4655
+ .4byte 0x24ea
4656
+ .uleb128 0x40
4657
+ .8byte .LVL152
4658
+ .4byte 0x1edd
4659
+ .uleb128 0x33
4660
+ .uleb128 0x1
4661
+ .byte 0x50
4662
+ .uleb128 0x1
4663
+ .byte 0x30
4664
+ .uleb128 0x33
4665
+ .uleb128 0x1
4666
+ .byte 0x51
4667
+ .uleb128 0x1
4668
+ .byte 0x37
4669
+ .uleb128 0x33
4670
+ .uleb128 0x1
4671
+ .byte 0x52
4672
+ .uleb128 0x6
4673
+ .byte 0x11
4674
+ .sleb128 -559087616
4675
+ .byte 0
4676
+ .byte 0
4677
+ .uleb128 0x37
4678
+ .4byte .LASF397
4679
+ .byte 0x1
4680
+ .2byte 0x20e
4681
+ .8byte .LFB236
4682
+ .8byte .LFE236-.LFB236
4683
+ .uleb128 0x1
4684
+ .byte 0x9c
4685
+ .4byte 0x178a
4686
+ .uleb128 0x41
4687
+ .4byte .LASF346
4688
+ .byte 0x1
4689
+ .2byte 0x20e
4690
+ .4byte 0x1071
4691
+ .uleb128 0x2
4692
+ .byte 0x70
4693
+ .sleb128 0
4694
+ .uleb128 0x32
4695
+ .8byte .LVL124
4696
+ .4byte 0x24cb
4697
+ .4byte 0x173b
4698
+ .uleb128 0x33
4699
+ .uleb128 0x1
4700
+ .byte 0x52
4701
+ .uleb128 0x2
4702
+ .byte 0x8
4703
+ .byte 0x28
4704
+ .byte 0
4705
+ .uleb128 0x32
4706
+ .8byte .LVL125
4707
+ .4byte 0x19bc
4708
+ .4byte 0x1757
4709
+ .uleb128 0x33
4710
+ .uleb128 0x1
4711
+ .byte 0x50
4712
+ .uleb128 0x1
4713
+ .byte 0x30
4714
+ .uleb128 0x33
4715
+ .uleb128 0x1
4716
+ .byte 0x51
4717
+ .uleb128 0x1
4718
+ .byte 0x32
4719
+ .byte 0
4720
+ .uleb128 0x32
4721
+ .8byte .LVL126
4722
+ .4byte 0x1edd
4723
+ .4byte 0x177c
4724
+ .uleb128 0x33
4725
+ .uleb128 0x1
4726
+ .byte 0x50
4727
+ .uleb128 0x1
4728
+ .byte 0x30
4729
+ .uleb128 0x33
4730
+ .uleb128 0x1
4731
+ .byte 0x51
4732
+ .uleb128 0x1
4733
+ .byte 0x33
4734
+ .uleb128 0x33
4735
+ .uleb128 0x1
4736
+ .byte 0x52
4737
+ .uleb128 0x5
4738
+ .byte 0xc
4739
+ .4byte 0x11111111
4740
+ .byte 0
4741
+ .uleb128 0x31
4742
+ .8byte .LVL127
4743
+ .4byte 0x24ea
4744
+ .byte 0
4745
+ .uleb128 0x42
4746
+ .4byte .LASF419
4747
+ .byte 0x1
4748
+ .2byte 0x1e9
4749
+ .byte 0x1
4750
+ .4byte 0x17ce
4751
+ .uleb128 0x36
4752
+ .4byte .LASF398
4753
+ .byte 0x1
4754
+ .2byte 0x1ee
4755
+ .4byte 0x17ce
4756
+ .uleb128 0x43
4757
+ .string "i"
4758
+ .byte 0x1
4759
+ .2byte 0x1fb
4760
+ .4byte 0x54
4761
+ .uleb128 0x44
4762
+ .4byte 0x17bf
4763
+ .uleb128 0x43
4764
+ .string "__v"
4765
+ .byte 0x1
4766
+ .2byte 0x206
4767
+ .4byte 0xa3
4768
+ .byte 0
4769
+ .uleb128 0x45
4770
+ .uleb128 0x43
4771
+ .string "__v"
4772
+ .byte 0x1
4773
+ .2byte 0x207
4774
+ .4byte 0xa3
4775
+ .byte 0
4776
+ .byte 0
4777
+ .uleb128 0xb
4778
+ .4byte 0x1367
4779
+ .4byte 0x17de
4780
+ .uleb128 0x10
4781
+ .4byte 0xcf
4782
+ .byte 0x1
4783
+ .byte 0
4784
+ .uleb128 0x37
4785
+ .4byte .LASF399
4786
+ .byte 0x1
4787
+ .2byte 0x1bf
4788
+ .8byte .LFB234
4789
+ .8byte .LFE234-.LFB234
4790
+ .uleb128 0x1
4791
+ .byte 0x9c
4792
+ .4byte 0x18d6
4793
+ .uleb128 0x2e
4794
+ .string "cpu"
4795
+ .byte 0x1
4796
+ .2byte 0x1bf
4797
+ .4byte 0xa3
4798
+ .4byte .LLST51
4799
+ .uleb128 0x3f
4800
+ .4byte 0x2086
4801
+ .8byte .LBB110
4802
+ .8byte .LBE110-.LBB110
4803
+ .byte 0x1
4804
+ .2byte 0x1c2
4805
+ .4byte 0x1832
4806
+ .uleb128 0x3c
4807
+ .4byte 0x2092
4808
+ .4byte .LLST52
4809
+ .byte 0
4810
+ .uleb128 0x46
4811
+ .4byte 0x2141
4812
+ .8byte .LBB112
4813
+ .8byte .LBE112-.LBB112
4814
+ .byte 0x1
4815
+ .2byte 0x1d6
4816
+ .uleb128 0x46
4817
+ .4byte 0x207e
4818
+ .8byte .LBB114
4819
+ .8byte .LBE114-.LBB114
4820
+ .byte 0x1
4821
+ .2byte 0x1da
4822
+ .uleb128 0x31
4823
+ .8byte .LVL116
4824
+ .4byte 0x2501
4825
+ .uleb128 0x32
4826
+ .8byte .LVL117
4827
+ .4byte 0x18d6
4828
+ .4byte 0x1887
4829
+ .uleb128 0x33
4830
+ .uleb128 0x1
4831
+ .byte 0x50
4832
+ .uleb128 0x2
4833
+ .byte 0x83
4834
+ .sleb128 0
4835
+ .byte 0
4836
+ .uleb128 0x31
4837
+ .8byte .LVL118
4838
+ .4byte 0x24ea
4839
+ .uleb128 0x31
4840
+ .8byte .LVL119
4841
+ .4byte 0x250d
4842
+ .uleb128 0x31
4843
+ .8byte .LVL120
4844
+ .4byte 0x2519
4845
+ .uleb128 0x31
4846
+ .8byte .LVL121
4847
+ .4byte 0x2525
4848
+ .uleb128 0x31
4849
+ .8byte .LVL122
4850
+ .4byte 0x2531
4851
+ .uleb128 0x31
4852
+ .8byte .LVL123
4853
+ .4byte 0x253d
4854
+ .byte 0
4855
+ .uleb128 0x37
4856
+ .4byte .LASF400
4857
+ .byte 0x1
4858
+ .2byte 0x1b1
4859
+ .8byte .LFB233
4860
+ .8byte .LFE233-.LFB233
4861
+ .uleb128 0x1
4862
+ .byte 0x9c
4863
+ .4byte 0x19b6
4864
+ .uleb128 0x2e
4865
+ .string "cpu"
4866
+ .byte 0x1
4867
+ .2byte 0x1b1
4868
+ .4byte 0xa3
4869
+ .4byte .LLST42
4870
+ .uleb128 0x2f
4871
+ .4byte .LASF388
4872
+ .byte 0x1
4873
+ .2byte 0x1b3
4874
+ .4byte 0x19b6
4875
+ .4byte .LLST43
4876
+ .uleb128 0x47
4877
+ .string "i"
4878
+ .byte 0x1
4879
+ .2byte 0x1b4
4880
+ .4byte 0x54
4881
+ .4byte .LLST44
4882
+ .uleb128 0x48
4883
+ .4byte 0x1ae8
4884
+ .8byte .LBB102
4885
+ .4byte .Ldebug_ranges0+0x160
4886
+ .byte 0x1
4887
+ .2byte 0x1b8
4888
+ .uleb128 0x3c
4889
+ .4byte 0x1b1c
4890
+ .4byte .LLST45
4891
+ .uleb128 0x3c
4892
+ .4byte 0x1b10
4893
+ .4byte .LLST46
4894
+ .uleb128 0x3c
4895
+ .4byte 0x1b05
4896
+ .4byte .LLST47
4897
+ .uleb128 0x3c
4898
+ .4byte 0x1af9
4899
+ .4byte .LLST48
4900
+ .uleb128 0x39
4901
+ .4byte .Ldebug_ranges0+0x160
4902
+ .uleb128 0x3e
4903
+ .4byte 0x1b28
4904
+ .uleb128 0x3e
4905
+ .4byte 0x1b34
4906
+ .uleb128 0x3b
4907
+ .4byte 0x1b40
4908
+ .4byte .LLST49
4909
+ .uleb128 0x3b
4910
+ .4byte 0x1b4c
4911
+ .4byte .LLST50
4912
+ .uleb128 0x38
4913
+ .4byte 0x2062
4914
+ .8byte .LBB104
4915
+ .4byte .Ldebug_ranges0+0x190
4916
+ .byte 0x1
4917
+ .2byte 0x179
4918
+ .4byte 0x1999
4919
+ .uleb128 0x49
4920
+ .4byte 0x2072
4921
+ .byte 0
4922
+ .uleb128 0x34
4923
+ .8byte .LVL110
4924
+ .4byte 0x21f4
4925
+ .uleb128 0x33
4926
+ .uleb128 0x1
4927
+ .byte 0x50
4928
+ .uleb128 0x2
4929
+ .byte 0x87
4930
+ .sleb128 0
4931
+ .uleb128 0x33
4932
+ .uleb128 0x1
4933
+ .byte 0x51
4934
+ .uleb128 0x2
4935
+ .byte 0x85
4936
+ .sleb128 0
4937
+ .byte 0
4938
+ .byte 0
4939
+ .byte 0
4940
+ .byte 0
4941
+ .uleb128 0x8
4942
+ .byte 0x8
4943
+ .4byte 0x1268
4944
+ .uleb128 0x37
4945
+ .4byte .LASF401
4946
+ .byte 0x1
4947
+ .2byte 0x1a3
4948
+ .8byte .LFB232
4949
+ .8byte .LFE232-.LFB232
4950
+ .uleb128 0x1
4951
+ .byte 0x9c
4952
+ .4byte 0x1ae8
4953
+ .uleb128 0x2e
4954
+ .string "cid"
4955
+ .byte 0x1
4956
+ .2byte 0x1a3
4957
+ .4byte 0xa3
4958
+ .4byte .LLST31
4959
+ .uleb128 0x2e
4960
+ .string "tid"
4961
+ .byte 0x1
4962
+ .2byte 0x1a3
4963
+ .4byte 0xa3
4964
+ .4byte .LLST32
4965
+ .uleb128 0x2f
4966
+ .4byte .LASF388
4967
+ .byte 0x1
4968
+ .2byte 0x1a5
4969
+ .4byte 0x19b6
4970
+ .4byte .LLST33
4971
+ .uleb128 0x47
4972
+ .string "i"
4973
+ .byte 0x1
4974
+ .2byte 0x1a6
4975
+ .4byte 0x54
4976
+ .4byte .LLST34
4977
+ .uleb128 0x38
4978
+ .4byte 0x2062
4979
+ .8byte .LBB90
4980
+ .4byte .Ldebug_ranges0+0x130
4981
+ .byte 0x1
4982
+ .2byte 0x1a8
4983
+ .4byte 0x1a3a
4984
+ .uleb128 0x3c
4985
+ .4byte 0x2072
4986
+ .4byte .LLST35
4987
+ .byte 0
4988
+ .uleb128 0x4a
4989
+ .4byte 0x1ae8
4990
+ .8byte .LBB94
4991
+ .8byte .LBE94-.LBB94
4992
+ .byte 0x1
4993
+ .2byte 0x1ad
4994
+ .uleb128 0x3c
4995
+ .4byte 0x1b1c
4996
+ .4byte .LLST36
4997
+ .uleb128 0x3c
4998
+ .4byte 0x1b10
4999
+ .4byte .LLST37
5000
+ .uleb128 0x3c
5001
+ .4byte 0x1b05
5002
+ .4byte .LLST38
5003
+ .uleb128 0x3c
5004
+ .4byte 0x1af9
5005
+ .4byte .LLST39
5006
+ .uleb128 0x4b
5007
+ .8byte .LBB95
5008
+ .8byte .LBE95-.LBB95
5009
+ .uleb128 0x3e
5010
+ .4byte 0x1b28
5011
+ .uleb128 0x3e
5012
+ .4byte 0x1b34
5013
+ .uleb128 0x3b
5014
+ .4byte 0x1b40
5015
+ .4byte .LLST40
5016
+ .uleb128 0x3b
5017
+ .4byte 0x1b4c
5018
+ .4byte .LLST41
5019
+ .uleb128 0x3f
5020
+ .4byte 0x2062
5021
+ .8byte .LBB96
5022
+ .8byte .LBE96-.LBB96
5023
+ .byte 0x1
5024
+ .2byte 0x179
5025
+ .4byte 0x1ac5
5026
+ .uleb128 0x49
5027
+ .4byte 0x2072
5028
+ .byte 0
5029
+ .uleb128 0x34
5030
+ .8byte .LVL99
5031
+ .4byte 0x21f4
5032
+ .uleb128 0x33
5033
+ .uleb128 0x1
5034
+ .byte 0x50
5035
+ .uleb128 0x2
5036
+ .byte 0x86
5037
+ .sleb128 0
5038
+ .uleb128 0x33
5039
+ .uleb128 0x1
5040
+ .byte 0x51
5041
+ .uleb128 0x2
5042
+ .byte 0x87
5043
+ .sleb128 0
5044
+ .uleb128 0x33
5045
+ .uleb128 0x1
5046
+ .byte 0x52
5047
+ .uleb128 0x2
5048
+ .byte 0x85
5049
+ .sleb128 0
5050
+ .byte 0
5051
+ .byte 0
5052
+ .byte 0
5053
+ .byte 0
5054
+ .uleb128 0x35
5055
+ .4byte .LASF403
5056
+ .byte 0x1
5057
+ .2byte 0x172
5058
+ .4byte 0x54
5059
+ .byte 0x1
5060
+ .4byte 0x1b59
5061
+ .uleb128 0x4c
5062
+ .string "cid"
5063
+ .byte 0x1
5064
+ .2byte 0x172
5065
+ .4byte 0xa3
5066
+ .uleb128 0x4c
5067
+ .string "id"
5068
+ .byte 0x1
5069
+ .2byte 0x172
5070
+ .4byte 0x94
5071
+ .uleb128 0x4c
5072
+ .string "tid"
5073
+ .byte 0x1
5074
+ .2byte 0x172
5075
+ .4byte 0xa3
5076
+ .uleb128 0x4d
5077
+ .4byte .LASF385
5078
+ .byte 0x1
5079
+ .2byte 0x172
5080
+ .4byte 0xa3
5081
+ .uleb128 0x36
5082
+ .4byte .LASF404
5083
+ .byte 0x1
5084
+ .2byte 0x174
5085
+ .4byte 0x8d
5086
+ .uleb128 0x36
5087
+ .4byte .LASF405
5088
+ .byte 0x1
5089
+ .2byte 0x175
5090
+ .4byte 0x54
5091
+ .uleb128 0x43
5092
+ .string "ret"
5093
+ .byte 0x1
5094
+ .2byte 0x176
5095
+ .4byte 0x54
5096
+ .uleb128 0x43
5097
+ .string "run"
5098
+ .byte 0x1
5099
+ .2byte 0x177
5100
+ .4byte 0x54
5101
+ .byte 0
5102
+ .uleb128 0x2d
5103
+ .4byte .LASF407
5104
+ .byte 0x1
5105
+ .2byte 0x16d
5106
+ .4byte 0x54
5107
+ .8byte .LFB230
5108
+ .8byte .LFE230-.LFB230
5109
+ .uleb128 0x1
5110
+ .byte 0x9c
5111
+ .4byte 0x1c3c
5112
+ .uleb128 0x2e
5113
+ .string "tid"
5114
+ .byte 0x1
5115
+ .2byte 0x16d
5116
+ .4byte 0xa3
5117
+ .4byte .LLST28
5118
+ .uleb128 0x48
5119
+ .4byte 0x1c3c
5120
+ .8byte .LBB78
5121
+ .4byte .Ldebug_ranges0+0x100
5122
+ .byte 0x1
5123
+ .2byte 0x16f
5124
+ .uleb128 0x4e
5125
+ .4byte 0x1c59
5126
+ .byte 0
5127
+ .uleb128 0x3c
5128
+ .4byte 0x1c4d
5129
+ .4byte .LLST29
5130
+ .uleb128 0x39
5131
+ .4byte .Ldebug_ranges0+0x100
5132
+ .uleb128 0x3e
5133
+ .4byte 0x1c65
5134
+ .uleb128 0x3f
5135
+ .4byte 0x2149
5136
+ .8byte .LBB80
5137
+ .8byte .LBE80-.LBB80
5138
+ .byte 0x1
5139
+ .2byte 0x164
5140
+ .4byte 0x1c0c
5141
+ .uleb128 0x3c
5142
+ .4byte 0x2155
5143
+ .4byte .LLST30
5144
+ .uleb128 0x32
5145
+ .8byte .LVL86
5146
+ .4byte 0x24f6
5147
+ .4byte 0x1bf6
5148
+ .uleb128 0x33
5149
+ .uleb128 0x1
5150
+ .byte 0x50
5151
+ .uleb128 0x3
5152
+ .byte 0xa
5153
+ .2byte 0x3e8
5154
+ .byte 0
5155
+ .uleb128 0x34
5156
+ .8byte .LVL87
5157
+ .4byte 0x24f6
5158
+ .uleb128 0x33
5159
+ .uleb128 0x1
5160
+ .byte 0x50
5161
+ .uleb128 0x3
5162
+ .byte 0xa
5163
+ .2byte 0x3e8
5164
+ .byte 0
5165
+ .byte 0
5166
+ .uleb128 0x32
5167
+ .8byte .LVL84
5168
+ .4byte 0x1e3e
5169
+ .4byte 0x1c24
5170
+ .uleb128 0x33
5171
+ .uleb128 0x1
5172
+ .byte 0x50
5173
+ .uleb128 0x2
5174
+ .byte 0x83
5175
+ .sleb128 0
5176
+ .byte 0
5177
+ .uleb128 0x40
5178
+ .8byte .LVL89
5179
+ .4byte 0x1e3e
5180
+ .uleb128 0x33
5181
+ .uleb128 0x1
5182
+ .byte 0x50
5183
+ .uleb128 0x3
5184
+ .byte 0xf3
5185
+ .uleb128 0x1
5186
+ .byte 0x50
5187
+ .byte 0
5188
+ .byte 0
5189
+ .byte 0
5190
+ .byte 0
5191
+ .uleb128 0x35
5192
+ .4byte .LASF408
5193
+ .byte 0x1
5194
+ .2byte 0x15f
5195
+ .4byte 0x54
5196
+ .byte 0x1
5197
+ .4byte 0x1c70
5198
+ .uleb128 0x4c
5199
+ .string "tid"
5200
+ .byte 0x1
5201
+ .2byte 0x15f
5202
+ .4byte 0xa3
5203
+ .uleb128 0x4d
5204
+ .4byte .LASF409
5205
+ .byte 0x1
5206
+ .2byte 0x15f
5207
+ .4byte 0xa3
5208
+ .uleb128 0x43
5209
+ .string "i"
5210
+ .byte 0x1
5211
+ .2byte 0x161
5212
+ .4byte 0xa3
5213
+ .byte 0
5214
+ .uleb128 0x35
5215
+ .4byte .LASF410
5216
+ .byte 0x1
5217
+ .2byte 0x138
5218
+ .4byte 0x54
5219
+ .byte 0x1
5220
+ .4byte 0x1cdf
5221
+ .uleb128 0x4c
5222
+ .string "cid"
5223
+ .byte 0x1
5224
+ .2byte 0x138
5225
+ .4byte 0xa3
5226
+ .uleb128 0x4c
5227
+ .string "tid"
5228
+ .byte 0x1
5229
+ .2byte 0x138
5230
+ .4byte 0xa3
5231
+ .uleb128 0x4d
5232
+ .4byte .LASF385
5233
+ .byte 0x1
5234
+ .2byte 0x138
5235
+ .4byte 0xa3
5236
+ .uleb128 0x36
5237
+ .4byte .LASF405
5238
+ .byte 0x1
5239
+ .2byte 0x13a
5240
+ .4byte 0x54
5241
+ .uleb128 0x43
5242
+ .string "us"
5243
+ .byte 0x1
5244
+ .2byte 0x13b
5245
+ .4byte 0x54
5246
+ .uleb128 0x43
5247
+ .string "i"
5248
+ .byte 0x1
5249
+ .2byte 0x13c
5250
+ .4byte 0x54
5251
+ .uleb128 0x36
5252
+ .4byte .LASF411
5253
+ .byte 0x1
5254
+ .2byte 0x13c
5255
+ .4byte 0x54
5256
+ .uleb128 0x36
5257
+ .4byte .LASF412
5258
+ .byte 0x1
5259
+ .2byte 0x13d
5260
+ .4byte 0x54
5261
+ .byte 0
5262
+ .uleb128 0x37
5263
+ .4byte .LASF413
5264
+ .byte 0x1
5265
+ .2byte 0x121
5266
+ .8byte .LFB227
5267
+ .8byte .LFE227-.LFB227
5268
+ .uleb128 0x1
5269
+ .byte 0x9c
5270
+ .4byte 0x1e3e
5271
+ .uleb128 0x2f
5272
+ .4byte .LASF388
5273
+ .byte 0x1
5274
+ .2byte 0x123
5275
+ .4byte 0x19b6
5276
+ .4byte .LLST8
5277
+ .uleb128 0x47
5278
+ .string "cid"
5279
+ .byte 0x1
5280
+ .2byte 0x124
5281
+ .4byte 0x54
5282
+ .4byte .LLST9
5283
+ .uleb128 0x47
5284
+ .string "i"
5285
+ .byte 0x1
5286
+ .2byte 0x124
5287
+ .4byte 0x54
5288
+ .4byte .LLST10
5289
+ .uleb128 0x32
5290
+ .8byte .LVL26
5291
+ .4byte 0x24d4
5292
+ .4byte 0x1d4a
5293
+ .uleb128 0x33
5294
+ .uleb128 0x1
5295
+ .byte 0x50
5296
+ .uleb128 0x9
5297
+ .byte 0x3
5298
+ .8byte .LC2
5299
+ .byte 0
5300
+ .uleb128 0x32
5301
+ .8byte .LVL29
5302
+ .4byte 0x24d4
5303
+ .4byte 0x1d68
5304
+ .uleb128 0x33
5305
+ .uleb128 0x1
5306
+ .byte 0x50
5307
+ .uleb128 0x2
5308
+ .byte 0x88
5309
+ .sleb128 0
5310
+ .uleb128 0x33
5311
+ .uleb128 0x1
5312
+ .byte 0x51
5313
+ .uleb128 0x2
5314
+ .byte 0x85
5315
+ .sleb128 0
5316
+ .byte 0
5317
+ .uleb128 0x32
5318
+ .8byte .LVL30
5319
+ .4byte 0x24d4
5320
+ .4byte 0x1d87
5321
+ .uleb128 0x33
5322
+ .uleb128 0x1
5323
+ .byte 0x50
5324
+ .uleb128 0x9
5325
+ .byte 0x3
5326
+ .8byte .LC4
5327
+ .byte 0
5328
+ .uleb128 0x32
5329
+ .8byte .LVL31
5330
+ .4byte 0x24d4
5331
+ .4byte 0x1da6
5332
+ .uleb128 0x33
5333
+ .uleb128 0x1
5334
+ .byte 0x50
5335
+ .uleb128 0x9
5336
+ .byte 0x3
5337
+ .8byte .LC5
5338
+ .byte 0
5339
+ .uleb128 0x32
5340
+ .8byte .LVL32
5341
+ .4byte 0x24d4
5342
+ .4byte 0x1dc5
5343
+ .uleb128 0x33
5344
+ .uleb128 0x1
5345
+ .byte 0x50
5346
+ .uleb128 0x9
5347
+ .byte 0x3
5348
+ .8byte .LC6
5349
+ .byte 0
5350
+ .uleb128 0x32
5351
+ .8byte .LVL33
5352
+ .4byte 0x24d4
5353
+ .4byte 0x1de4
5354
+ .uleb128 0x33
5355
+ .uleb128 0x1
5356
+ .byte 0x50
5357
+ .uleb128 0x9
5358
+ .byte 0x3
5359
+ .8byte .LC7
5360
+ .byte 0
5361
+ .uleb128 0x32
5362
+ .8byte .LVL34
5363
+ .4byte 0x24d4
5364
+ .4byte 0x1e03
5365
+ .uleb128 0x33
5366
+ .uleb128 0x1
5367
+ .byte 0x50
5368
+ .uleb128 0x9
5369
+ .byte 0x3
5370
+ .8byte .LC8
5371
+ .byte 0
5372
+ .uleb128 0x32
5373
+ .8byte .LVL35
5374
+ .4byte 0x24d4
5375
+ .4byte 0x1e22
5376
+ .uleb128 0x33
5377
+ .uleb128 0x1
5378
+ .byte 0x50
5379
+ .uleb128 0x9
5380
+ .byte 0x3
5381
+ .8byte .LC9
5382
+ .byte 0
5383
+ .uleb128 0x34
5384
+ .8byte .LVL36
5385
+ .4byte 0x24d4
5386
+ .uleb128 0x33
5387
+ .uleb128 0x1
5388
+ .byte 0x50
5389
+ .uleb128 0x9
5390
+ .byte 0x3
5391
+ .8byte .LC10
5392
+ .byte 0
5393
+ .byte 0
5394
+ .uleb128 0x2d
5395
+ .4byte .LASF414
5396
+ .byte 0x1
5397
+ .2byte 0x104
5398
+ .4byte 0x54
5399
+ .8byte .LFB226
5400
+ .8byte .LFE226-.LFB226
5401
+ .uleb128 0x1
5402
+ .byte 0x9c
5403
+ .4byte 0x1ed7
5404
+ .uleb128 0x2e
5405
+ .string "tid"
5406
+ .byte 0x1
5407
+ .2byte 0x104
5408
+ .4byte 0xa3
5409
+ .4byte .LLST5
5410
+ .uleb128 0x43
5411
+ .string "cid"
5412
+ .byte 0x1
5413
+ .2byte 0x106
5414
+ .4byte 0x54
5415
+ .uleb128 0x47
5416
+ .string "i"
5417
+ .byte 0x1
5418
+ .2byte 0x106
5419
+ .4byte 0x54
5420
+ .4byte .LLST6
5421
+ .uleb128 0x47
5422
+ .string "ptr"
5423
+ .byte 0x1
5424
+ .2byte 0x107
5425
+ .4byte 0x1ed7
5426
+ .4byte .LLST7
5427
+ .uleb128 0x3f
5428
+ .4byte 0x2062
5429
+ .8byte .LBB40
5430
+ .8byte .LBE40-.LBB40
5431
+ .byte 0x1
5432
+ .2byte 0x109
5433
+ .4byte 0x1ebc
5434
+ .uleb128 0x49
5435
+ .4byte 0x2072
5436
+ .byte 0
5437
+ .uleb128 0x34
5438
+ .8byte .LVL23
5439
+ .4byte 0x2549
5440
+ .uleb128 0x33
5441
+ .uleb128 0x1
5442
+ .byte 0x50
5443
+ .uleb128 0x2
5444
+ .byte 0x86
5445
+ .sleb128 0
5446
+ .uleb128 0x33
5447
+ .uleb128 0x1
5448
+ .byte 0x51
5449
+ .uleb128 0x2
5450
+ .byte 0x84
5451
+ .sleb128 0
5452
+ .byte 0
5453
+ .byte 0
5454
+ .uleb128 0x8
5455
+ .byte 0x8
5456
+ .4byte 0xa3
5457
+ .uleb128 0x4f
5458
+ .4byte .LASF450
5459
+ .byte 0x1
5460
+ .byte 0xe2
5461
+ .4byte 0x54
5462
+ .8byte .LFB225
5463
+ .8byte .LFE225-.LFB225
5464
+ .uleb128 0x1
5465
+ .byte 0x9c
5466
+ .4byte 0x1faa
5467
+ .uleb128 0x50
5468
+ .string "cid"
5469
+ .byte 0x1
5470
+ .byte 0xe2
5471
+ .4byte 0xa3
5472
+ .4byte .LLST0
5473
+ .uleb128 0x50
5474
+ .string "tid"
5475
+ .byte 0x1
5476
+ .byte 0xe2
5477
+ .4byte 0xa3
5478
+ .4byte .LLST1
5479
+ .uleb128 0x50
5480
+ .string "st"
5481
+ .byte 0x1
5482
+ .byte 0xe2
5483
+ .4byte 0xa3
5484
+ .4byte .LLST2
5485
+ .uleb128 0x51
5486
+ .4byte .LASF31
5487
+ .byte 0x1
5488
+ .byte 0xe4
5489
+ .4byte 0xef
5490
+ .uleb128 0x2c
5491
+ .string "ptr"
5492
+ .byte 0x1
5493
+ .byte 0xe5
5494
+ .4byte 0x1ed7
5495
+ .uleb128 0x2c
5496
+ .string "id"
5497
+ .byte 0x1
5498
+ .byte 0xe6
5499
+ .4byte 0x54
5500
+ .uleb128 0x52
5501
+ .4byte 0x2062
5502
+ .8byte .LBB30
5503
+ .8byte .LBE30-.LBB30
5504
+ .byte 0x1
5505
+ .byte 0xe8
5506
+ .4byte 0x1f6b
5507
+ .uleb128 0x49
5508
+ .4byte 0x2072
5509
+ .byte 0
5510
+ .uleb128 0x53
5511
+ .4byte 0x1ff7
5512
+ .8byte .LBB32
5513
+ .4byte .Ldebug_ranges0+0
5514
+ .byte 0x1
5515
+ .byte 0xeb
5516
+ .4byte 0x1f9c
5517
+ .uleb128 0x49
5518
+ .4byte 0x2012
5519
+ .uleb128 0x49
5520
+ .4byte 0x2007
5521
+ .uleb128 0x39
5522
+ .4byte .Ldebug_ranges0+0
5523
+ .uleb128 0x3b
5524
+ .4byte 0x201d
5525
+ .4byte .LLST3
5526
+ .byte 0
5527
+ .byte 0
5528
+ .uleb128 0x31
5529
+ .8byte .LVL8
5530
+ .4byte 0x2555
5531
+ .byte 0
5532
+ .uleb128 0x54
5533
+ .4byte .LASF415
5534
+ .byte 0x1
5535
+ .byte 0xcf
5536
+ .4byte 0x54
5537
+ .byte 0x1
5538
+ .4byte 0x1ff1
5539
+ .uleb128 0x55
5540
+ .string "cid"
5541
+ .byte 0x1
5542
+ .byte 0xcf
5543
+ .4byte 0xa3
5544
+ .uleb128 0x55
5545
+ .string "tid"
5546
+ .byte 0x1
5547
+ .byte 0xcf
5548
+ .4byte 0xa3
5549
+ .uleb128 0x55
5550
+ .string "ret"
5551
+ .byte 0x1
5552
+ .byte 0xcf
5553
+ .4byte 0xa3
5554
+ .uleb128 0x2c
5555
+ .string "ptr"
5556
+ .byte 0x1
5557
+ .byte 0xd1
5558
+ .4byte 0x1ff1
5559
+ .uleb128 0x2c
5560
+ .string "id"
5561
+ .byte 0x1
5562
+ .byte 0xd2
5563
+ .4byte 0x54
5564
+ .byte 0
5565
+ .uleb128 0x8
5566
+ .byte 0x8
5567
+ .4byte 0x54
5568
+ .uleb128 0x54
5569
+ .4byte .LASF416
5570
+ .byte 0x1
5571
+ .byte 0xc3
5572
+ .4byte 0x54
5573
+ .byte 0x1
5574
+ .4byte 0x2027
5575
+ .uleb128 0x55
5576
+ .string "cid"
5577
+ .byte 0x1
5578
+ .byte 0xc3
5579
+ .4byte 0xa3
5580
+ .uleb128 0x55
5581
+ .string "tid"
5582
+ .byte 0x1
5583
+ .byte 0xc3
5584
+ .4byte 0xa3
5585
+ .uleb128 0x2c
5586
+ .string "i"
5587
+ .byte 0x1
5588
+ .byte 0xc5
5589
+ .4byte 0x54
5590
+ .byte 0
5591
+ .uleb128 0x54
5592
+ .4byte .LASF417
5593
+ .byte 0x1
5594
+ .byte 0x9d
5595
+ .4byte 0x54
5596
+ .byte 0x1
5597
+ .4byte 0x2062
5598
+ .uleb128 0x56
5599
+ .4byte .LASF398
5600
+ .byte 0x1
5601
+ .byte 0x9d
5602
+ .4byte 0x1367
5603
+ .uleb128 0x2c
5604
+ .string "cid"
5605
+ .byte 0x1
5606
+ .byte 0x9f
5607
+ .4byte 0xa3
5608
+ .uleb128 0x2c
5609
+ .string "tid"
5610
+ .byte 0x1
5611
+ .byte 0xa0
5612
+ .4byte 0xa3
5613
+ .uleb128 0x2c
5614
+ .string "i"
5615
+ .byte 0x1
5616
+ .byte 0xa1
5617
+ .4byte 0x94
5618
+ .byte 0
5619
+ .uleb128 0x54
5620
+ .4byte .LASF418
5621
+ .byte 0x1
5622
+ .byte 0x90
5623
+ .4byte 0x54
5624
+ .byte 0x3
5625
+ .4byte 0x207e
5626
+ .uleb128 0x55
5627
+ .string "tid"
5628
+ .byte 0x1
5629
+ .byte 0x90
5630
+ .4byte 0xa3
5631
+ .byte 0
5632
+ .uleb128 0x57
5633
+ .4byte .LASF427
5634
+ .byte 0x1
5635
+ .byte 0x86
5636
+ .byte 0x3
5637
+ .uleb128 0x58
5638
+ .4byte .LASF420
5639
+ .byte 0x1
5640
+ .byte 0x81
5641
+ .byte 0x3
5642
+ .4byte 0x209e
5643
+ .uleb128 0x55
5644
+ .string "ptr"
5645
+ .byte 0x1
5646
+ .byte 0x81
5647
+ .4byte 0x10b
5648
+ .byte 0
5649
+ .uleb128 0x59
5650
+ .4byte .LASF451
5651
+ .byte 0x1
5652
+ .byte 0x34
5653
+ .4byte 0x54
5654
+ .byte 0x1
5655
+ .4byte 0x20ba
5656
+ .uleb128 0x56
5657
+ .4byte .LASF421
5658
+ .byte 0x1
5659
+ .byte 0x34
5660
+ .4byte 0x1262
5661
+ .byte 0
5662
+ .uleb128 0x5a
5663
+ .4byte .LASF422
5664
+ .byte 0x1
5665
+ .byte 0x33
5666
+ .4byte 0x54
5667
+ .4byte 0x20d5
5668
+ .uleb128 0x56
5669
+ .4byte .LASF421
5670
+ .byte 0x1
5671
+ .byte 0x33
5672
+ .4byte 0x1262
5673
+ .byte 0
5674
+ .uleb128 0x5a
5675
+ .4byte .LASF423
5676
+ .byte 0x1
5677
+ .byte 0x32
5678
+ .4byte 0x54
5679
+ .4byte 0x20f0
5680
+ .uleb128 0x56
5681
+ .4byte .LASF421
5682
+ .byte 0x1
5683
+ .byte 0x32
5684
+ .4byte 0x1262
5685
+ .byte 0
5686
+ .uleb128 0x5a
5687
+ .4byte .LASF424
5688
+ .byte 0x1
5689
+ .byte 0x31
5690
+ .4byte 0x54
5691
+ .4byte 0x210b
5692
+ .uleb128 0x56
5693
+ .4byte .LASF421
5694
+ .byte 0x1
5695
+ .byte 0x31
5696
+ .4byte 0x1262
5697
+ .byte 0
5698
+ .uleb128 0x5a
5699
+ .4byte .LASF425
5700
+ .byte 0x1
5701
+ .byte 0x30
5702
+ .4byte 0x54
5703
+ .4byte 0x2126
5704
+ .uleb128 0x56
5705
+ .4byte .LASF421
5706
+ .byte 0x1
5707
+ .byte 0x30
5708
+ .4byte 0x1262
5709
+ .byte 0
5710
+ .uleb128 0x5a
5711
+ .4byte .LASF426
5712
+ .byte 0x1
5713
+ .byte 0x2f
5714
+ .4byte 0x54
5715
+ .4byte 0x2141
5716
+ .uleb128 0x56
5717
+ .4byte .LASF421
5718
+ .byte 0x1
5719
+ .byte 0x2f
5720
+ .4byte 0x1262
5721
+ .byte 0
5722
+ .uleb128 0x57
5723
+ .4byte .LASF428
5724
+ .byte 0x3
5725
+ .byte 0xbf
5726
+ .byte 0x3
5727
+ .uleb128 0x58
5728
+ .4byte .LASF429
5729
+ .byte 0x2
5730
+ .byte 0xd
5731
+ .byte 0x3
5732
+ .4byte 0x2161
5733
+ .uleb128 0x56
5734
+ .4byte .LASF430
5735
+ .byte 0x2
5736
+ .byte 0xd
5737
+ .4byte 0x3b
5738
+ .byte 0
5739
+ .uleb128 0x5b
5740
+ .4byte 0x14ef
5741
+ .8byte .LFB238
5742
+ .8byte .LFE238-.LFB238
5743
+ .uleb128 0x1
5744
+ .byte 0x9c
5745
+ .4byte 0x21cf
5746
+ .uleb128 0x3a
5747
+ .4byte 0x1500
5748
+ .uleb128 0x9
5749
+ .byte 0x3
5750
+ .8byte once.6657
5751
+ .uleb128 0x3d
5752
+ .8byte .LBB39
5753
+ .8byte .LBE39-.LBB39
5754
+ .4byte 0x21c1
5755
+ .uleb128 0x3e
5756
+ .4byte 0x217c
5757
+ .uleb128 0x34
5758
+ .8byte .LVL10
5759
+ .4byte 0x24d4
5760
+ .uleb128 0x33
5761
+ .uleb128 0x1
5762
+ .byte 0x50
5763
+ .uleb128 0x9
5764
+ .byte 0x3
5765
+ .8byte .LC1
5766
+ .byte 0
5767
+ .byte 0
5768
+ .uleb128 0x31
5769
+ .8byte .LVL9
5770
+ .4byte 0x2561
5771
+ .byte 0
5772
+ .uleb128 0x5b
5773
+ .4byte 0x209e
5774
+ .8byte .LFB218
5775
+ .8byte .LFE218-.LFB218
5776
+ .uleb128 0x1
5777
+ .byte 0x9c
5778
+ .4byte 0x21f4
5779
+ .uleb128 0x3c
5780
+ .4byte 0x20ae
5781
+ .4byte .LLST4
5782
+ .byte 0
5783
+ .uleb128 0x5c
5784
+ .4byte 0x1ae8
5785
+ .8byte .LFB242
5786
+ .8byte .LFE242-.LFB242
5787
+ .uleb128 0x1
5788
+ .byte 0x9c
5789
+ .4byte 0x24b5
5790
+ .uleb128 0x3c
5791
+ .4byte 0x1af9
5792
+ .4byte .LLST11
5793
+ .uleb128 0x3c
5794
+ .4byte 0x1b05
5795
+ .4byte .LLST12
5796
+ .uleb128 0x3c
5797
+ .4byte 0x1b10
5798
+ .4byte .LLST13
5799
+ .uleb128 0x3c
5800
+ .4byte 0x1b1c
5801
+ .4byte .LLST14
5802
+ .uleb128 0x3b
5803
+ .4byte 0x1b28
5804
+ .4byte .LLST15
5805
+ .uleb128 0x3e
5806
+ .4byte 0x1b34
5807
+ .uleb128 0x3b
5808
+ .4byte 0x1b40
5809
+ .4byte .LLST16
5810
+ .uleb128 0x3b
5811
+ .4byte 0x1b4c
5812
+ .4byte .LLST17
5813
+ .uleb128 0x38
5814
+ .4byte 0x1c70
5815
+ .8byte .LBB52
5816
+ .4byte .Ldebug_ranges0+0x30
5817
+ .byte 0x1
5818
+ .2byte 0x17f
5819
+ .4byte 0x2308
5820
+ .uleb128 0x3c
5821
+ .4byte 0x1c81
5822
+ .4byte .LLST18
5823
+ .uleb128 0x3c
5824
+ .4byte 0x1c8d
5825
+ .4byte .LLST19
5826
+ .uleb128 0x3c
5827
+ .4byte 0x1c99
5828
+ .4byte .LLST20
5829
+ .uleb128 0x39
5830
+ .4byte .Ldebug_ranges0+0x30
5831
+ .uleb128 0x3b
5832
+ .4byte 0x1ca5
5833
+ .4byte .LLST21
5834
+ .uleb128 0x5d
5835
+ .4byte 0x1cb1
5836
+ .byte 0x64
5837
+ .uleb128 0x3e
5838
+ .4byte 0x1cbc
5839
+ .uleb128 0x3b
5840
+ .4byte 0x1cc6
5841
+ .4byte .LLST22
5842
+ .uleb128 0x3b
5843
+ .4byte 0x1cd2
5844
+ .4byte .LLST23
5845
+ .uleb128 0x32
5846
+ .8byte .LVL43
5847
+ .4byte 0x1e3e
5848
+ .4byte 0x22c9
5849
+ .uleb128 0x33
5850
+ .uleb128 0x1
5851
+ .byte 0x50
5852
+ .uleb128 0x2
5853
+ .byte 0x85
5854
+ .sleb128 0
5855
+ .byte 0
5856
+ .uleb128 0x32
5857
+ .8byte .LVL44
5858
+ .4byte 0x1e3e
5859
+ .4byte 0x22e1
5860
+ .uleb128 0x33
5861
+ .uleb128 0x1
5862
+ .byte 0x50
5863
+ .uleb128 0x2
5864
+ .byte 0x85
5865
+ .sleb128 0
5866
+ .byte 0
5867
+ .uleb128 0x32
5868
+ .8byte .LVL53
5869
+ .4byte 0x24f6
5870
+ .4byte 0x22f9
5871
+ .uleb128 0x33
5872
+ .uleb128 0x1
5873
+ .byte 0x50
5874
+ .uleb128 0x2
5875
+ .byte 0x8
5876
+ .byte 0x64
5877
+ .byte 0
5878
+ .uleb128 0x31
5879
+ .8byte .LVL56
5880
+ .4byte 0x1cdf
5881
+ .byte 0
5882
+ .byte 0
5883
+ .uleb128 0x38
5884
+ .4byte 0x1faa
5885
+ .8byte .LBB56
5886
+ .4byte .Ldebug_ranges0+0x60
5887
+ .byte 0x1
5888
+ .2byte 0x19e
5889
+ .4byte 0x23ab
5890
+ .uleb128 0x3c
5891
+ .4byte 0x1fd0
5892
+ .4byte .LLST24
5893
+ .uleb128 0x3c
5894
+ .4byte 0x1fc5
5895
+ .4byte .LLST25
5896
+ .uleb128 0x3c
5897
+ .4byte 0x1fba
5898
+ .4byte .LLST26
5899
+ .uleb128 0x39
5900
+ .4byte .Ldebug_ranges0+0x60
5901
+ .uleb128 0x3e
5902
+ .4byte 0x1fdb
5903
+ .uleb128 0x3e
5904
+ .4byte 0x1fe6
5905
+ .uleb128 0x52
5906
+ .4byte 0x2062
5907
+ .8byte .LBB58
5908
+ .8byte .LBE58-.LBB58
5909
+ .byte 0x1
5910
+ .byte 0xd4
5911
+ .4byte 0x236b
5912
+ .uleb128 0x49
5913
+ .4byte 0x2072
5914
+ .byte 0
5915
+ .uleb128 0x53
5916
+ .4byte 0x1ff7
5917
+ .8byte .LBB60
5918
+ .4byte .Ldebug_ranges0+0xd0
5919
+ .byte 0x1
5920
+ .byte 0xd7
5921
+ .4byte 0x239c
5922
+ .uleb128 0x49
5923
+ .4byte 0x2012
5924
+ .uleb128 0x49
5925
+ .4byte 0x2007
5926
+ .uleb128 0x39
5927
+ .4byte .Ldebug_ranges0+0xd0
5928
+ .uleb128 0x3b
5929
+ .4byte 0x201d
5930
+ .4byte .LLST27
5931
+ .byte 0
5932
+ .byte 0
5933
+ .uleb128 0x5e
5934
+ .8byte .LVL81
5935
+ .4byte 0x2555
5936
+ .byte 0
5937
+ .byte 0
5938
+ .uleb128 0x32
5939
+ .8byte .LVL50
5940
+ .4byte 0x24d4
5941
+ .4byte 0x23d6
5942
+ .uleb128 0x33
5943
+ .uleb128 0x1
5944
+ .byte 0x50
5945
+ .uleb128 0x9
5946
+ .byte 0x3
5947
+ .8byte .LC12
5948
+ .uleb128 0x33
5949
+ .uleb128 0x1
5950
+ .byte 0x51
5951
+ .uleb128 0x2
5952
+ .byte 0x83
5953
+ .sleb128 0
5954
+ .uleb128 0x33
5955
+ .uleb128 0x1
5956
+ .byte 0x52
5957
+ .uleb128 0x2
5958
+ .byte 0x84
5959
+ .sleb128 0
5960
+ .byte 0
5961
+ .uleb128 0x32
5962
+ .8byte .LVL51
5963
+ .4byte 0x1edd
5964
+ .4byte 0x23fd
5965
+ .uleb128 0x33
5966
+ .uleb128 0x1
5967
+ .byte 0x50
5968
+ .uleb128 0x2
5969
+ .byte 0x83
5970
+ .sleb128 0
5971
+ .uleb128 0x33
5972
+ .uleb128 0x1
5973
+ .byte 0x51
5974
+ .uleb128 0x2
5975
+ .byte 0x84
5976
+ .sleb128 0
5977
+ .uleb128 0x33
5978
+ .uleb128 0x1
5979
+ .byte 0x52
5980
+ .uleb128 0x5
5981
+ .byte 0xc
5982
+ .4byte 0x55555555
5983
+ .byte 0
5984
+ .uleb128 0x32
5985
+ .8byte .LVL59
5986
+ .4byte 0x24d4
5987
+ .4byte 0x2428
5988
+ .uleb128 0x33
5989
+ .uleb128 0x1
5990
+ .byte 0x50
5991
+ .uleb128 0x9
5992
+ .byte 0x3
5993
+ .8byte .LC13
5994
+ .uleb128 0x33
5995
+ .uleb128 0x1
5996
+ .byte 0x51
5997
+ .uleb128 0x2
5998
+ .byte 0x83
5999
+ .sleb128 0
6000
+ .uleb128 0x33
6001
+ .uleb128 0x1
6002
+ .byte 0x52
6003
+ .uleb128 0x2
6004
+ .byte 0x84
6005
+ .sleb128 0
6006
+ .byte 0
6007
+ .uleb128 0x31
6008
+ .8byte .LVL60
6009
+ .4byte 0x256c
6010
+ .uleb128 0x32
6011
+ .8byte .LVL63
6012
+ .4byte 0x1edd
6013
+ .4byte 0x245c
6014
+ .uleb128 0x33
6015
+ .uleb128 0x1
6016
+ .byte 0x50
6017
+ .uleb128 0x2
6018
+ .byte 0x83
6019
+ .sleb128 0
6020
+ .uleb128 0x33
6021
+ .uleb128 0x1
6022
+ .byte 0x51
6023
+ .uleb128 0x2
6024
+ .byte 0x84
6025
+ .sleb128 0
6026
+ .uleb128 0x33
6027
+ .uleb128 0x1
6028
+ .byte 0x52
6029
+ .uleb128 0x5
6030
+ .byte 0xc
6031
+ .4byte 0x11111111
6032
+ .byte 0
6033
+ .uleb128 0x32
6034
+ .8byte .LVL67
6035
+ .4byte 0x1edd
6036
+ .4byte 0x247a
6037
+ .uleb128 0x33
6038
+ .uleb128 0x1
6039
+ .byte 0x50
6040
+ .uleb128 0x2
6041
+ .byte 0x83
6042
+ .sleb128 0
6043
+ .uleb128 0x33
6044
+ .uleb128 0x1
6045
+ .byte 0x51
6046
+ .uleb128 0x2
6047
+ .byte 0x84
6048
+ .sleb128 0
6049
+ .byte 0
6050
+ .uleb128 0x31
6051
+ .8byte .LVL68
6052
+ .4byte 0x256c
6053
+ .uleb128 0x34
6054
+ .8byte .LVL70
6055
+ .4byte 0x24d4
6056
+ .uleb128 0x33
6057
+ .uleb128 0x1
6058
+ .byte 0x50
6059
+ .uleb128 0x9
6060
+ .byte 0x3
6061
+ .8byte .LC11
6062
+ .uleb128 0x33
6063
+ .uleb128 0x1
6064
+ .byte 0x51
6065
+ .uleb128 0x2
6066
+ .byte 0x83
6067
+ .sleb128 0
6068
+ .uleb128 0x33
6069
+ .uleb128 0x1
6070
+ .byte 0x52
6071
+ .uleb128 0x2
6072
+ .byte 0x84
6073
+ .sleb128 0
6074
+ .uleb128 0x33
6075
+ .uleb128 0x1
6076
+ .byte 0x53
6077
+ .uleb128 0x2
6078
+ .byte 0x85
6079
+ .sleb128 0
6080
+ .byte 0
6081
+ .byte 0
6082
+ .uleb128 0x5f
6083
+ .4byte .LASF431
6084
+ .4byte .LASF431
6085
+ .byte 0x1e
6086
+ .byte 0x8e
6087
+ .uleb128 0x5f
6088
+ .4byte .LASF432
6089
+ .4byte .LASF432
6090
+ .byte 0x4
6091
+ .byte 0x6b
6092
+ .uleb128 0x60
6093
+ .4byte .LASF452
6094
+ .4byte .LASF452
6095
+ .uleb128 0x5f
6096
+ .4byte .LASF433
6097
+ .4byte .LASF433
6098
+ .byte 0x1f
6099
+ .byte 0x13
6100
+ .uleb128 0x5f
6101
+ .4byte .LASF434
6102
+ .4byte .LASF434
6103
+ .byte 0x8
6104
+ .byte 0x66
6105
+ .uleb128 0x61
6106
+ .4byte .LASF435
6107
+ .4byte .LASF435
6108
+ .byte 0x4
6109
+ .2byte 0x260
6110
+ .uleb128 0x5f
6111
+ .4byte .LASF436
6112
+ .4byte .LASF436
6113
+ .byte 0x2
6114
+ .byte 0xb
6115
+ .uleb128 0x61
6116
+ .4byte .LASF437
6117
+ .4byte .LASF437
6118
+ .byte 0x4
6119
+ .2byte 0x1f3
6120
+ .uleb128 0x61
6121
+ .4byte .LASF438
6122
+ .4byte .LASF438
6123
+ .byte 0x4
6124
+ .2byte 0x248
6125
+ .uleb128 0x61
6126
+ .4byte .LASF439
6127
+ .4byte .LASF439
6128
+ .byte 0x4
6129
+ .2byte 0x1f1
6130
+ .uleb128 0x61
6131
+ .4byte .LASF440
6132
+ .4byte .LASF440
6133
+ .byte 0x4
6134
+ .2byte 0x264
6135
+ .uleb128 0x61
6136
+ .4byte .LASF441
6137
+ .4byte .LASF441
6138
+ .byte 0x4
6139
+ .2byte 0x1f4
6140
+ .uleb128 0x61
6141
+ .4byte .LASF442
6142
+ .4byte .LASF442
6143
+ .byte 0x4
6144
+ .2byte 0x263
6145
+ .uleb128 0x61
6146
+ .4byte .LASF443
6147
+ .4byte .LASF443
6148
+ .byte 0x4
6149
+ .2byte 0x262
6150
+ .uleb128 0x61
6151
+ .4byte .LASF444
6152
+ .4byte .LASF444
6153
+ .byte 0x4
6154
+ .2byte 0x261
6155
+ .uleb128 0x5f
6156
+ .4byte .LASF445
6157
+ .4byte .LASF445
6158
+ .byte 0x1c
6159
+ .byte 0x50
6160
+ .uleb128 0x61
6161
+ .4byte .LASF446
6162
+ .4byte .LASF446
6163
+ .byte 0x4
6164
+ .2byte 0x276
6165
+ .byte 0
6166
+ .section .debug_abbrev,"",@progbits
6167
+.Ldebug_abbrev0:
6168
+ .uleb128 0x1
6169
+ .uleb128 0x11
6170
+ .byte 0x1
6171
+ .uleb128 0x25
6172
+ .uleb128 0xe
6173
+ .uleb128 0x13
6174
+ .uleb128 0xb
6175
+ .uleb128 0x3
6176
+ .uleb128 0xe
6177
+ .uleb128 0x1b
6178
+ .uleb128 0xe
6179
+ .uleb128 0x55
6180
+ .uleb128 0x17
6181
+ .uleb128 0x11
6182
+ .uleb128 0x1
6183
+ .uleb128 0x10
6184
+ .uleb128 0x17
6185
+ .byte 0
6186
+ .byte 0
6187
+ .uleb128 0x2
6188
+ .uleb128 0x16
6189
+ .byte 0
6190
+ .uleb128 0x3
6191
+ .uleb128 0xe
6192
+ .uleb128 0x3a
6193
+ .uleb128 0xb
6194
+ .uleb128 0x3b
6195
+ .uleb128 0xb
6196
+ .uleb128 0x49
6197
+ .uleb128 0x13
6198
+ .byte 0
6199
+ .byte 0
6200
+ .uleb128 0x3
6201
+ .uleb128 0x24
6202
+ .byte 0
6203
+ .uleb128 0xb
6204
+ .uleb128 0xb
6205
+ .uleb128 0x3e
6206
+ .uleb128 0xb
6207
+ .uleb128 0x3
6208
+ .uleb128 0xe
6209
+ .byte 0
6210
+ .byte 0
6211
+ .uleb128 0x4
6212
+ .uleb128 0x34
6213
+ .byte 0
6214
+ .uleb128 0x3
6215
+ .uleb128 0xe
6216
+ .uleb128 0x3a
6217
+ .uleb128 0xb
6218
+ .uleb128 0x3b
6219
+ .uleb128 0xb
6220
+ .uleb128 0x49
6221
+ .uleb128 0x13
6222
+ .uleb128 0x3f
6223
+ .uleb128 0x19
6224
+ .uleb128 0x3c
6225
+ .uleb128 0x19
6226
+ .byte 0
6227
+ .byte 0
6228
+ .uleb128 0x5
6229
+ .uleb128 0x24
6230
+ .byte 0
6231
+ .uleb128 0xb
6232
+ .uleb128 0xb
6233
+ .uleb128 0x3e
6234
+ .uleb128 0xb
6235
+ .uleb128 0x3
6236
+ .uleb128 0x8
6237
+ .byte 0
6238
+ .byte 0
6239
+ .uleb128 0x6
6240
+ .uleb128 0x16
6241
+ .byte 0
6242
+ .uleb128 0x3
6243
+ .uleb128 0x8
6244
+ .uleb128 0x3a
6245
+ .uleb128 0xb
6246
+ .uleb128 0x3b
6247
+ .uleb128 0xb
6248
+ .uleb128 0x49
6249
+ .uleb128 0x13
6250
+ .byte 0
6251
+ .byte 0
6252
+ .uleb128 0x7
6253
+ .uleb128 0x26
6254
+ .byte 0
6255
+ .uleb128 0x49
6256
+ .uleb128 0x13
6257
+ .byte 0
6258
+ .byte 0
6259
+ .uleb128 0x8
6260
+ .uleb128 0xf
6261
+ .byte 0
6262
+ .uleb128 0xb
6263
+ .uleb128 0xb
6264
+ .uleb128 0x49
6265
+ .uleb128 0x13
6266
+ .byte 0
6267
+ .byte 0
6268
+ .uleb128 0x9
6269
+ .uleb128 0x35
6270
+ .byte 0
6271
+ .uleb128 0x49
6272
+ .uleb128 0x13
6273
+ .byte 0
6274
+ .byte 0
6275
+ .uleb128 0xa
6276
+ .uleb128 0xf
6277
+ .byte 0
6278
+ .uleb128 0xb
6279
+ .uleb128 0xb
6280
+ .byte 0
6281
+ .byte 0
6282
+ .uleb128 0xb
6283
+ .uleb128 0x1
6284
+ .byte 0x1
6285
+ .uleb128 0x49
6286
+ .uleb128 0x13
6287
+ .uleb128 0x1
6288
+ .uleb128 0x13
6289
+ .byte 0
6290
+ .byte 0
6291
+ .uleb128 0xc
6292
+ .uleb128 0x21
6293
+ .byte 0
6294
+ .byte 0
6295
+ .byte 0
6296
+ .uleb128 0xd
6297
+ .uleb128 0x34
6298
+ .byte 0
6299
+ .uleb128 0x3
6300
+ .uleb128 0xe
6301
+ .uleb128 0x3a
6302
+ .uleb128 0xb
6303
+ .uleb128 0x3b
6304
+ .uleb128 0x5
6305
+ .uleb128 0x49
6306
+ .uleb128 0x13
6307
+ .uleb128 0x3f
6308
+ .uleb128 0x19
6309
+ .uleb128 0x3c
6310
+ .uleb128 0x19
6311
+ .byte 0
6312
+ .byte 0
6313
+ .uleb128 0xe
6314
+ .uleb128 0x13
6315
+ .byte 0
6316
+ .uleb128 0x3
6317
+ .uleb128 0xe
6318
+ .uleb128 0x3c
6319
+ .uleb128 0x19
6320
+ .byte 0
6321
+ .byte 0
6322
+ .uleb128 0xf
6323
+ .uleb128 0x26
6324
+ .byte 0
6325
+ .byte 0
6326
+ .byte 0
6327
+ .uleb128 0x10
6328
+ .uleb128 0x21
6329
+ .byte 0
6330
+ .uleb128 0x49
6331
+ .uleb128 0x13
6332
+ .uleb128 0x2f
6333
+ .uleb128 0xb
6334
+ .byte 0
6335
+ .byte 0
6336
+ .uleb128 0x11
6337
+ .uleb128 0x13
6338
+ .byte 0x1
6339
+ .uleb128 0x3
6340
+ .uleb128 0xe
6341
+ .uleb128 0xb
6342
+ .uleb128 0xb
6343
+ .uleb128 0x3a
6344
+ .uleb128 0xb
6345
+ .uleb128 0x3b
6346
+ .uleb128 0xb
6347
+ .uleb128 0x1
6348
+ .uleb128 0x13
6349
+ .byte 0
6350
+ .byte 0
6351
+ .uleb128 0x12
6352
+ .uleb128 0xd
6353
+ .byte 0
6354
+ .uleb128 0x3
6355
+ .uleb128 0xe
6356
+ .uleb128 0x3a
6357
+ .uleb128 0xb
6358
+ .uleb128 0x3b
6359
+ .uleb128 0xb
6360
+ .uleb128 0x49
6361
+ .uleb128 0x13
6362
+ .uleb128 0x38
6363
+ .uleb128 0xb
6364
+ .byte 0
6365
+ .byte 0
6366
+ .uleb128 0x13
6367
+ .uleb128 0x15
6368
+ .byte 0x1
6369
+ .uleb128 0x27
6370
+ .uleb128 0x19
6371
+ .uleb128 0x49
6372
+ .uleb128 0x13
6373
+ .uleb128 0x1
6374
+ .uleb128 0x13
6375
+ .byte 0
6376
+ .byte 0
6377
+ .uleb128 0x14
6378
+ .uleb128 0x5
6379
+ .byte 0
6380
+ .uleb128 0x49
6381
+ .uleb128 0x13
6382
+ .byte 0
6383
+ .byte 0
6384
+ .uleb128 0x15
6385
+ .uleb128 0x13
6386
+ .byte 0x1
6387
+ .uleb128 0xb
6388
+ .uleb128 0x5
6389
+ .uleb128 0x3a
6390
+ .uleb128 0xb
6391
+ .uleb128 0x3b
6392
+ .uleb128 0xb
6393
+ .uleb128 0x1
6394
+ .uleb128 0x13
6395
+ .byte 0
6396
+ .byte 0
6397
+ .uleb128 0x16
6398
+ .uleb128 0xd
6399
+ .byte 0
6400
+ .uleb128 0x3
6401
+ .uleb128 0xe
6402
+ .uleb128 0x3a
6403
+ .uleb128 0xb
6404
+ .uleb128 0x3b
6405
+ .uleb128 0xb
6406
+ .uleb128 0x49
6407
+ .uleb128 0x13
6408
+ .uleb128 0x38
6409
+ .uleb128 0x5
6410
+ .byte 0
6411
+ .byte 0
6412
+ .uleb128 0x17
6413
+ .uleb128 0xd
6414
+ .byte 0
6415
+ .uleb128 0x3
6416
+ .uleb128 0x8
6417
+ .uleb128 0x3a
6418
+ .uleb128 0xb
6419
+ .uleb128 0x3b
6420
+ .uleb128 0xb
6421
+ .uleb128 0x49
6422
+ .uleb128 0x13
6423
+ .uleb128 0x38
6424
+ .uleb128 0x5
6425
+ .byte 0
6426
+ .byte 0
6427
+ .uleb128 0x18
6428
+ .uleb128 0x21
6429
+ .byte 0
6430
+ .uleb128 0x49
6431
+ .uleb128 0x13
6432
+ .uleb128 0x2f
6433
+ .uleb128 0x5
6434
+ .byte 0
6435
+ .byte 0
6436
+ .uleb128 0x19
6437
+ .uleb128 0x13
6438
+ .byte 0x1
6439
+ .uleb128 0x3
6440
+ .uleb128 0xe
6441
+ .uleb128 0xb
6442
+ .uleb128 0x5
6443
+ .uleb128 0x3a
6444
+ .uleb128 0xb
6445
+ .uleb128 0x3b
6446
+ .uleb128 0xb
6447
+ .uleb128 0x1
6448
+ .uleb128 0x13
6449
+ .byte 0
6450
+ .byte 0
6451
+ .uleb128 0x1a
6452
+ .uleb128 0xd
6453
+ .byte 0
6454
+ .uleb128 0x3
6455
+ .uleb128 0x8
6456
+ .uleb128 0x3a
6457
+ .uleb128 0xb
6458
+ .uleb128 0x3b
6459
+ .uleb128 0xb
6460
+ .uleb128 0x49
6461
+ .uleb128 0x13
6462
+ .uleb128 0x38
6463
+ .uleb128 0xb
6464
+ .byte 0
6465
+ .byte 0
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7085
+ .uleb128 0xb
7086
+ .uleb128 0x59
7087
+ .uleb128 0x5
7088
+ .byte 0
7089
+ .byte 0
7090
+ .uleb128 0x49
7091
+ .uleb128 0x5
7092
+ .byte 0
7093
+ .uleb128 0x31
7094
+ .uleb128 0x13
7095
+ .byte 0
7096
+ .byte 0
7097
+ .uleb128 0x4a
7098
+ .uleb128 0x1d
7099
+ .byte 0x1
7100
+ .uleb128 0x31
7101
+ .uleb128 0x13
7102
+ .uleb128 0x11
7103
+ .uleb128 0x1
7104
+ .uleb128 0x12
7105
+ .uleb128 0x7
7106
+ .uleb128 0x58
7107
+ .uleb128 0xb
7108
+ .uleb128 0x59
7109
+ .uleb128 0x5
7110
+ .byte 0
7111
+ .byte 0
7112
+ .uleb128 0x4b
7113
+ .uleb128 0xb
7114
+ .byte 0x1
7115
+ .uleb128 0x11
7116
+ .uleb128 0x1
7117
+ .uleb128 0x12
7118
+ .uleb128 0x7
7119
+ .byte 0
7120
+ .byte 0
7121
+ .uleb128 0x4c
7122
+ .uleb128 0x5
7123
+ .byte 0
7124
+ .uleb128 0x3
7125
+ .uleb128 0x8
7126
+ .uleb128 0x3a
7127
+ .uleb128 0xb
7128
+ .uleb128 0x3b
7129
+ .uleb128 0x5
7130
+ .uleb128 0x49
7131
+ .uleb128 0x13
7132
+ .byte 0
7133
+ .byte 0
7134
+ .uleb128 0x4d
7135
+ .uleb128 0x5
7136
+ .byte 0
7137
+ .uleb128 0x3
7138
+ .uleb128 0xe
7139
+ .uleb128 0x3a
7140
+ .uleb128 0xb
7141
+ .uleb128 0x3b
7142
+ .uleb128 0x5
7143
+ .uleb128 0x49
7144
+ .uleb128 0x13
7145
+ .byte 0
7146
+ .byte 0
7147
+ .uleb128 0x4e
7148
+ .uleb128 0x5
7149
+ .byte 0
7150
+ .uleb128 0x31
7151
+ .uleb128 0x13
7152
+ .uleb128 0x1c
7153
+ .uleb128 0xb
7154
+ .byte 0
7155
+ .byte 0
7156
+ .uleb128 0x4f
7157
+ .uleb128 0x2e
7158
+ .byte 0x1
7159
+ .uleb128 0x3
7160
+ .uleb128 0xe
7161
+ .uleb128 0x3a
7162
+ .uleb128 0xb
7163
+ .uleb128 0x3b
7164
+ .uleb128 0xb
7165
+ .uleb128 0x27
7166
+ .uleb128 0x19
7167
+ .uleb128 0x49
7168
+ .uleb128 0x13
7169
+ .uleb128 0x11
7170
+ .uleb128 0x1
7171
+ .uleb128 0x12
7172
+ .uleb128 0x7
7173
+ .uleb128 0x40
7174
+ .uleb128 0x18
7175
+ .uleb128 0x2117
7176
+ .uleb128 0x19
7177
+ .uleb128 0x1
7178
+ .uleb128 0x13
7179
+ .byte 0
7180
+ .byte 0
7181
+ .uleb128 0x50
7182
+ .uleb128 0x5
7183
+ .byte 0
7184
+ .uleb128 0x3
7185
+ .uleb128 0x8
7186
+ .uleb128 0x3a
7187
+ .uleb128 0xb
7188
+ .uleb128 0x3b
7189
+ .uleb128 0xb
7190
+ .uleb128 0x49
7191
+ .uleb128 0x13
7192
+ .uleb128 0x2
7193
+ .uleb128 0x17
7194
+ .byte 0
7195
+ .byte 0
7196
+ .uleb128 0x51
7197
+ .uleb128 0x34
7198
+ .byte 0
7199
+ .uleb128 0x3
7200
+ .uleb128 0xe
7201
+ .uleb128 0x3a
7202
+ .uleb128 0xb
7203
+ .uleb128 0x3b
7204
+ .uleb128 0xb
7205
+ .uleb128 0x49
7206
+ .uleb128 0x13
7207
+ .byte 0
7208
+ .byte 0
7209
+ .uleb128 0x52
7210
+ .uleb128 0x1d
7211
+ .byte 0x1
7212
+ .uleb128 0x31
7213
+ .uleb128 0x13
7214
+ .uleb128 0x11
7215
+ .uleb128 0x1
7216
+ .uleb128 0x12
7217
+ .uleb128 0x7
7218
+ .uleb128 0x58
7219
+ .uleb128 0xb
7220
+ .uleb128 0x59
7221
+ .uleb128 0xb
7222
+ .uleb128 0x1
7223
+ .uleb128 0x13
7224
+ .byte 0
7225
+ .byte 0
7226
+ .uleb128 0x53
7227
+ .uleb128 0x1d
7228
+ .byte 0x1
7229
+ .uleb128 0x31
7230
+ .uleb128 0x13
7231
+ .uleb128 0x52
7232
+ .uleb128 0x1
7233
+ .uleb128 0x55
7234
+ .uleb128 0x17
7235
+ .uleb128 0x58
7236
+ .uleb128 0xb
7237
+ .uleb128 0x59
7238
+ .uleb128 0xb
7239
+ .uleb128 0x1
7240
+ .uleb128 0x13
7241
+ .byte 0
7242
+ .byte 0
7243
+ .uleb128 0x54
7244
+ .uleb128 0x2e
7245
+ .byte 0x1
7246
+ .uleb128 0x3
7247
+ .uleb128 0xe
7248
+ .uleb128 0x3a
7249
+ .uleb128 0xb
7250
+ .uleb128 0x3b
7251
+ .uleb128 0xb
7252
+ .uleb128 0x27
7253
+ .uleb128 0x19
7254
+ .uleb128 0x49
7255
+ .uleb128 0x13
7256
+ .uleb128 0x20
7257
+ .uleb128 0xb
7258
+ .uleb128 0x1
7259
+ .uleb128 0x13
7260
+ .byte 0
7261
+ .byte 0
7262
+ .uleb128 0x55
7263
+ .uleb128 0x5
7264
+ .byte 0
7265
+ .uleb128 0x3
7266
+ .uleb128 0x8
7267
+ .uleb128 0x3a
7268
+ .uleb128 0xb
7269
+ .uleb128 0x3b
7270
+ .uleb128 0xb
7271
+ .uleb128 0x49
7272
+ .uleb128 0x13
7273
+ .byte 0
7274
+ .byte 0
7275
+ .uleb128 0x56
7276
+ .uleb128 0x5
7277
+ .byte 0
7278
+ .uleb128 0x3
7279
+ .uleb128 0xe
7280
+ .uleb128 0x3a
7281
+ .uleb128 0xb
7282
+ .uleb128 0x3b
7283
+ .uleb128 0xb
7284
+ .uleb128 0x49
7285
+ .uleb128 0x13
7286
+ .byte 0
7287
+ .byte 0
7288
+ .uleb128 0x57
7289
+ .uleb128 0x2e
7290
+ .byte 0
7291
+ .uleb128 0x3
7292
+ .uleb128 0xe
7293
+ .uleb128 0x3a
7294
+ .uleb128 0xb
7295
+ .uleb128 0x3b
7296
+ .uleb128 0xb
7297
+ .uleb128 0x27
7298
+ .uleb128 0x19
7299
+ .uleb128 0x20
7300
+ .uleb128 0xb
7301
+ .byte 0
7302
+ .byte 0
7303
+ .uleb128 0x58
7304
+ .uleb128 0x2e
7305
+ .byte 0x1
7306
+ .uleb128 0x3
7307
+ .uleb128 0xe
7308
+ .uleb128 0x3a
7309
+ .uleb128 0xb
7310
+ .uleb128 0x3b
7311
+ .uleb128 0xb
7312
+ .uleb128 0x27
7313
+ .uleb128 0x19
7314
+ .uleb128 0x20
7315
+ .uleb128 0xb
7316
+ .uleb128 0x1
7317
+ .uleb128 0x13
7318
+ .byte 0
7319
+ .byte 0
7320
+ .uleb128 0x59
7321
+ .uleb128 0x2e
7322
+ .byte 0x1
7323
+ .uleb128 0x3f
7324
+ .uleb128 0x19
7325
+ .uleb128 0x3
7326
+ .uleb128 0xe
7327
+ .uleb128 0x3a
7328
+ .uleb128 0xb
7329
+ .uleb128 0x3b
7330
+ .uleb128 0xb
7331
+ .uleb128 0x27
7332
+ .uleb128 0x19
7333
+ .uleb128 0x49
7334
+ .uleb128 0x13
7335
+ .uleb128 0x20
7336
+ .uleb128 0xb
7337
+ .uleb128 0x1
7338
+ .uleb128 0x13
7339
+ .byte 0
7340
+ .byte 0
7341
+ .uleb128 0x5a
7342
+ .uleb128 0x2e
7343
+ .byte 0x1
7344
+ .uleb128 0x3f
7345
+ .uleb128 0x19
7346
+ .uleb128 0x3
7347
+ .uleb128 0xe
7348
+ .uleb128 0x3a
7349
+ .uleb128 0xb
7350
+ .uleb128 0x3b
7351
+ .uleb128 0xb
7352
+ .uleb128 0x27
7353
+ .uleb128 0x19
7354
+ .uleb128 0x49
7355
+ .uleb128 0x13
7356
+ .uleb128 0x1
7357
+ .uleb128 0x13
7358
+ .byte 0
7359
+ .byte 0
7360
+ .uleb128 0x5b
7361
+ .uleb128 0x2e
7362
+ .byte 0x1
7363
+ .uleb128 0x31
7364
+ .uleb128 0x13
7365
+ .uleb128 0x11
7366
+ .uleb128 0x1
7367
+ .uleb128 0x12
7368
+ .uleb128 0x7
7369
+ .uleb128 0x40
7370
+ .uleb128 0x18
7371
+ .uleb128 0x2117
7372
+ .uleb128 0x19
7373
+ .uleb128 0x1
7374
+ .uleb128 0x13
7375
+ .byte 0
7376
+ .byte 0
7377
+ .uleb128 0x5c
7378
+ .uleb128 0x2e
7379
+ .byte 0x1
7380
+ .uleb128 0x31
7381
+ .uleb128 0x13
7382
+ .uleb128 0x11
7383
+ .uleb128 0x1
7384
+ .uleb128 0x12
7385
+ .uleb128 0x7
7386
+ .uleb128 0x40
7387
+ .uleb128 0x18
7388
+ .uleb128 0x2116
7389
+ .uleb128 0x19
7390
+ .uleb128 0x1
7391
+ .uleb128 0x13
7392
+ .byte 0
7393
+ .byte 0
7394
+ .uleb128 0x5d
7395
+ .uleb128 0x34
7396
+ .byte 0
7397
+ .uleb128 0x31
7398
+ .uleb128 0x13
7399
+ .uleb128 0x1c
7400
+ .uleb128 0xb
7401
+ .byte 0
7402
+ .byte 0
7403
+ .uleb128 0x5e
7404
+ .uleb128 0x4109
7405
+ .byte 0
7406
+ .uleb128 0x11
7407
+ .uleb128 0x1
7408
+ .uleb128 0x2115
7409
+ .uleb128 0x19
7410
+ .uleb128 0x31
7411
+ .uleb128 0x13
7412
+ .byte 0
7413
+ .byte 0
7414
+ .uleb128 0x5f
7415
+ .uleb128 0x2e
7416
+ .byte 0
7417
+ .uleb128 0x3f
7418
+ .uleb128 0x19
7419
+ .uleb128 0x3c
7420
+ .uleb128 0x19
7421
+ .uleb128 0x6e
7422
+ .uleb128 0xe
7423
+ .uleb128 0x3
7424
+ .uleb128 0xe
7425
+ .uleb128 0x3a
7426
+ .uleb128 0xb
7427
+ .uleb128 0x3b
7428
+ .uleb128 0xb
7429
+ .byte 0
7430
+ .byte 0
7431
+ .uleb128 0x60
7432
+ .uleb128 0x2e
7433
+ .byte 0
7434
+ .uleb128 0x3f
7435
+ .uleb128 0x19
7436
+ .uleb128 0x3c
7437
+ .uleb128 0x19
7438
+ .uleb128 0x6e
7439
+ .uleb128 0xe
7440
+ .uleb128 0x3
7441
+ .uleb128 0xe
7442
+ .byte 0
7443
+ .byte 0
7444
+ .uleb128 0x61
7445
+ .uleb128 0x2e
7446
+ .byte 0
7447
+ .uleb128 0x3f
7448
+ .uleb128 0x19
7449
+ .uleb128 0x3c
7450
+ .uleb128 0x19
7451
+ .uleb128 0x6e
7452
+ .uleb128 0xe
7453
+ .uleb128 0x3
7454
+ .uleb128 0xe
7455
+ .uleb128 0x3a
7456
+ .uleb128 0xb
7457
+ .uleb128 0x3b
7458
+ .uleb128 0x5
7459
+ .byte 0
7460
+ .byte 0
7461
+ .byte 0
7462
+ .section .debug_loc,"",@progbits
7463
+.Ldebug_loc0:
7464
+.LLST61:
7465
+ .8byte .LVL153
7466
+ .8byte .LVL154
7467
+ .2byte 0x1
7468
+ .byte 0x50
7469
+ .8byte .LVL154
7470
+ .8byte .LVL172
7471
+ .2byte 0x4
7472
+ .byte 0xf3
7473
+ .uleb128 0x1
7474
+ .byte 0x50
7475
+ .byte 0x9f
7476
+ .8byte .LVL172
7477
+ .8byte .LVL173
7478
+ .2byte 0x1
7479
+ .byte 0x50
7480
+ .8byte .LVL173
7481
+ .8byte .LFE239
7482
+ .2byte 0x4
7483
+ .byte 0xf3
7484
+ .uleb128 0x1
7485
+ .byte 0x50
7486
+ .byte 0x9f
7487
+ .8byte 0
7488
+ .8byte 0
7489
+.LLST62:
7490
+ .8byte .LVL156
7491
+ .8byte .LVL159
7492
+ .2byte 0x2
7493
+ .byte 0x35
7494
+ .byte 0x9f
7495
+ .8byte .LVL160
7496
+ .8byte .LVL161
7497
+ .2byte 0x2
7498
+ .byte 0x35
7499
+ .byte 0x9f
7500
+ .8byte .LVL166
7501
+ .8byte .LVL172
7502
+ .2byte 0x2
7503
+ .byte 0x35
7504
+ .byte 0x9f
7505
+ .8byte 0
7506
+ .8byte 0
7507
+.LLST53:
7508
+ .8byte .LVL128
7509
+ .8byte .LVL129
7510
+ .2byte 0x1
7511
+ .byte 0x50
7512
+ .8byte .LVL129
7513
+ .8byte .LVL145
7514
+ .2byte 0x4
7515
+ .byte 0xf3
7516
+ .uleb128 0x1
7517
+ .byte 0x50
7518
+ .byte 0x9f
7519
+ .8byte .LVL145
7520
+ .8byte .LVL146
7521
+ .2byte 0x1
7522
+ .byte 0x50
7523
+ .8byte .LVL146
7524
+ .8byte .LVL150
7525
+ .2byte 0x4
7526
+ .byte 0xf3
7527
+ .uleb128 0x1
7528
+ .byte 0x50
7529
+ .byte 0x9f
7530
+ .8byte .LVL150
7531
+ .8byte .LVL151
7532
+ .2byte 0x1
7533
+ .byte 0x50
7534
+ .8byte .LVL151
7535
+ .8byte .LFE237
7536
+ .2byte 0x4
7537
+ .byte 0xf3
7538
+ .uleb128 0x1
7539
+ .byte 0x50
7540
+ .byte 0x9f
7541
+ .8byte 0
7542
+ .8byte 0
7543
+.LLST54:
7544
+ .8byte .LVL133
7545
+ .8byte .LVL134
7546
+ .2byte 0x2
7547
+ .byte 0x30
7548
+ .byte 0x9f
7549
+ .8byte 0
7550
+ .8byte 0
7551
+.LLST55:
7552
+ .8byte .LVL138
7553
+ .8byte .LVL139
7554
+ .2byte 0x7
7555
+ .byte 0x93
7556
+ .uleb128 0x4
7557
+ .byte 0x53
7558
+ .byte 0x93
7559
+ .uleb128 0x4
7560
+ .byte 0x93
7561
+ .uleb128 0x10
7562
+ .8byte .LVL139
7563
+ .8byte .LVL143
7564
+ .2byte 0xe
7565
+ .byte 0x93
7566
+ .uleb128 0x4
7567
+ .byte 0x53
7568
+ .byte 0x93
7569
+ .uleb128 0x4
7570
+ .byte 0x5d
7571
+ .byte 0x93
7572
+ .uleb128 0x8
7573
+ .byte 0x5c
7574
+ .byte 0x93
7575
+ .uleb128 0x4
7576
+ .byte 0x5b
7577
+ .byte 0x93
7578
+ .uleb128 0x4
7579
+ .8byte .LVL143
7580
+ .8byte .LVL144
7581
+ .2byte 0xf
7582
+ .byte 0x93
7583
+ .uleb128 0x4
7584
+ .byte 0x71
7585
+ .sleb128 20
7586
+ .byte 0x93
7587
+ .uleb128 0x4
7588
+ .byte 0x5d
7589
+ .byte 0x93
7590
+ .uleb128 0x8
7591
+ .byte 0x5c
7592
+ .byte 0x93
7593
+ .uleb128 0x4
7594
+ .byte 0x5b
7595
+ .byte 0x93
7596
+ .uleb128 0x4
7597
+ .8byte .LVL144
7598
+ .8byte .LVL145
7599
+ .2byte 0xb
7600
+ .byte 0x93
7601
+ .uleb128 0x8
7602
+ .byte 0x5d
7603
+ .byte 0x93
7604
+ .uleb128 0x8
7605
+ .byte 0x5c
7606
+ .byte 0x93
7607
+ .uleb128 0x4
7608
+ .byte 0x5b
7609
+ .byte 0x93
7610
+ .uleb128 0x4
7611
+ .8byte 0
7612
+ .8byte 0
7613
+.LLST56:
7614
+ .8byte .LVL139
7615
+ .8byte .LVL141
7616
+ .2byte 0x1
7617
+ .byte 0x51
7618
+ .8byte .LVL141
7619
+ .8byte .LVL142
7620
+ .2byte 0x2
7621
+ .byte 0x70
7622
+ .sleb128 0
7623
+ .8byte 0
7624
+ .8byte 0
7625
+.LLST57:
7626
+ .8byte .LVL139
7627
+ .8byte .LVL143
7628
+ .2byte 0x1
7629
+ .byte 0x53
7630
+ .8byte .LVL143
7631
+ .8byte .LVL144
7632
+ .2byte 0x2
7633
+ .byte 0x71
7634
+ .sleb128 20
7635
+ .8byte 0
7636
+ .8byte 0
7637
+.LLST58:
7638
+ .8byte .LVL140
7639
+ .8byte .LVL141
7640
+ .2byte 0x11
7641
+ .byte 0x71
7642
+ .sleb128 0
7643
+ .byte 0xc
7644
+ .4byte 0xffffffff
7645
+ .byte 0x1a
7646
+ .byte 0xa
7647
+ .2byte 0x148
7648
+ .byte 0x1e
7649
+ .byte 0x23
7650
+ .uleb128 0x8200148
7651
+ .8byte .LVL141
7652
+ .8byte .LVL142
7653
+ .2byte 0x13
7654
+ .byte 0x70
7655
+ .sleb128 0
7656
+ .byte 0x94
7657
+ .byte 0x4
7658
+ .byte 0xc
7659
+ .4byte 0xffffffff
7660
+ .byte 0x1a
7661
+ .byte 0xa
7662
+ .2byte 0x148
7663
+ .byte 0x1e
7664
+ .byte 0x23
7665
+ .uleb128 0x8200148
7666
+ .8byte 0
7667
+ .8byte 0
7668
+.LLST59:
7669
+ .8byte .LVL136
7670
+ .8byte .LVL137
7671
+ .2byte 0x6
7672
+ .byte 0x9e
7673
+ .uleb128 0x4
7674
+ .4byte 0xdeadbeaf
7675
+ .8byte 0
7676
+ .8byte 0
7677
+.LLST60:
7678
+ .8byte .LVL149
7679
+ .8byte .LVL150
7680
+ .2byte 0x2
7681
+ .byte 0x30
7682
+ .byte 0x9f
7683
+ .8byte 0
7684
+ .8byte 0
7685
+.LLST51:
7686
+ .8byte .LVL112
7687
+ .8byte .LVL113
7688
+ .2byte 0x1
7689
+ .byte 0x50
7690
+ .8byte .LVL113
7691
+ .8byte .LFE234
7692
+ .2byte 0x1
7693
+ .byte 0x63
7694
+ .8byte 0
7695
+ .8byte 0
7696
+.LLST52:
7697
+ .8byte .LVL114
7698
+ .8byte .LVL115
7699
+ .2byte 0x1
7700
+ .byte 0x50
7701
+ .8byte 0
7702
+ .8byte 0
7703
+.LLST42:
7704
+ .8byte .LVL101
7705
+ .8byte .LVL102
7706
+ .2byte 0x1
7707
+ .byte 0x50
7708
+ .8byte .LVL102
7709
+ .8byte .LVL104
7710
+ .2byte 0x1
7711
+ .byte 0x66
7712
+ .8byte .LVL104
7713
+ .8byte .LVL107
7714
+ .2byte 0x1
7715
+ .byte 0x67
7716
+ .8byte .LVL107
7717
+ .8byte .LFE233
7718
+ .2byte 0x4
7719
+ .byte 0xf3
7720
+ .uleb128 0x1
7721
+ .byte 0x50
7722
+ .byte 0x9f
7723
+ .8byte 0
7724
+ .8byte 0
7725
+.LLST43:
7726
+ .8byte .LVL103
7727
+ .8byte .LVL104
7728
+ .2byte 0x12
7729
+ .byte 0x86
7730
+ .sleb128 0
7731
+ .byte 0xc
7732
+ .4byte 0xffffffff
7733
+ .byte 0x1a
7734
+ .byte 0xa
7735
+ .2byte 0x148
7736
+ .byte 0x1e
7737
+ .byte 0x23
7738
+ .uleb128 0x8200008
7739
+ .byte 0x9f
7740
+ .8byte .LVL104
7741
+ .8byte .LVL107
7742
+ .2byte 0x12
7743
+ .byte 0x87
7744
+ .sleb128 0
7745
+ .byte 0xc
7746
+ .4byte 0xffffffff
7747
+ .byte 0x1a
7748
+ .byte 0xa
7749
+ .2byte 0x148
7750
+ .byte 0x1e
7751
+ .byte 0x23
7752
+ .uleb128 0x8200008
7753
+ .byte 0x9f
7754
+ .8byte .LVL107
7755
+ .8byte .LVL108
7756
+ .2byte 0x13
7757
+ .byte 0xf3
7758
+ .uleb128 0x1
7759
+ .byte 0x50
7760
+ .byte 0xc
7761
+ .4byte 0xffffffff
7762
+ .byte 0x1a
7763
+ .byte 0xa
7764
+ .2byte 0x148
7765
+ .byte 0x1e
7766
+ .byte 0x23
7767
+ .uleb128 0x8200008
7768
+ .byte 0x9f
7769
+ .8byte .LVL108
7770
+ .8byte .LFE233
7771
+ .2byte 0x12
7772
+ .byte 0x87
7773
+ .sleb128 0
7774
+ .byte 0xc
7775
+ .4byte 0xffffffff
7776
+ .byte 0x1a
7777
+ .byte 0xa
7778
+ .2byte 0x148
7779
+ .byte 0x1e
7780
+ .byte 0x23
7781
+ .uleb128 0x8200008
7782
+ .byte 0x9f
7783
+ .8byte 0
7784
+ .8byte 0
7785
+.LLST44:
7786
+ .8byte .LVL103
7787
+ .8byte .LVL105
7788
+ .2byte 0x2
7789
+ .byte 0x30
7790
+ .byte 0x9f
7791
+ .8byte .LVL105
7792
+ .8byte .LVL106
7793
+ .2byte 0x1
7794
+ .byte 0x65
7795
+ .8byte .LVL108
7796
+ .8byte .LFE233
7797
+ .2byte 0x1
7798
+ .byte 0x65
7799
+ .8byte 0
7800
+ .8byte 0
7801
+.LLST45:
7802
+ .8byte .LVL109
7803
+ .8byte .LVL110-1
7804
+ .2byte 0x2
7805
+ .byte 0x83
7806
+ .sleb128 16
7807
+ .8byte 0
7808
+ .8byte 0
7809
+.LLST46:
7810
+ .8byte .LVL109
7811
+ .8byte .LVL110-1
7812
+ .2byte 0x1
7813
+ .byte 0x52
7814
+ .8byte 0
7815
+ .8byte 0
7816
+.LLST47:
7817
+ .8byte .LVL109
7818
+ .8byte .LVL110
7819
+ .2byte 0x1
7820
+ .byte 0x65
7821
+ .8byte 0
7822
+ .8byte 0
7823
+.LLST48:
7824
+ .8byte .LVL109
7825
+ .8byte .LVL110
7826
+ .2byte 0x1
7827
+ .byte 0x67
7828
+ .8byte 0
7829
+ .8byte 0
7830
+.LLST49:
7831
+ .8byte .LVL109
7832
+ .8byte .LVL110
7833
+ .2byte 0x2
7834
+ .byte 0x30
7835
+ .byte 0x9f
7836
+ .8byte 0
7837
+ .8byte 0
7838
+.LLST50:
7839
+ .8byte .LVL109
7840
+ .8byte .LVL110
7841
+ .2byte 0x2
7842
+ .byte 0x31
7843
+ .byte 0x9f
7844
+ .8byte 0
7845
+ .8byte 0
7846
+.LLST31:
7847
+ .8byte .LVL90
7848
+ .8byte .LVL93
7849
+ .2byte 0x1
7850
+ .byte 0x50
7851
+ .8byte .LVL93
7852
+ .8byte .LVL94
7853
+ .2byte 0x1
7854
+ .byte 0x69
7855
+ .8byte .LVL94
7856
+ .8byte .LVL96
7857
+ .2byte 0x1
7858
+ .byte 0x66
7859
+ .8byte .LVL96
7860
+ .8byte .LFE232
7861
+ .2byte 0x4
7862
+ .byte 0xf3
7863
+ .uleb128 0x1
7864
+ .byte 0x50
7865
+ .byte 0x9f
7866
+ .8byte 0
7867
+ .8byte 0
7868
+.LLST32:
7869
+ .8byte .LVL90
7870
+ .8byte .LVL95
7871
+ .2byte 0x1
7872
+ .byte 0x51
7873
+ .8byte .LVL95
7874
+ .8byte .LVL96
7875
+ .2byte 0x1
7876
+ .byte 0x65
7877
+ .8byte .LVL96
7878
+ .8byte .LVL97
7879
+ .2byte 0x4
7880
+ .byte 0xf3
7881
+ .uleb128 0x1
7882
+ .byte 0x51
7883
+ .byte 0x9f
7884
+ .8byte .LVL97
7885
+ .8byte .LFE232
7886
+ .2byte 0x1
7887
+ .byte 0x65
7888
+ .8byte 0
7889
+ .8byte 0
7890
+.LLST33:
7891
+ .8byte .LVL90
7892
+ .8byte .LVL92
7893
+ .2byte 0x12
7894
+ .byte 0x70
7895
+ .sleb128 0
7896
+ .byte 0xc
7897
+ .4byte 0xffffffff
7898
+ .byte 0x1a
7899
+ .byte 0xa
7900
+ .2byte 0x148
7901
+ .byte 0x1e
7902
+ .byte 0x23
7903
+ .uleb128 0x8200008
7904
+ .byte 0x9f
7905
+ .8byte .LVL92
7906
+ .8byte .LVL94
7907
+ .2byte 0xc
7908
+ .byte 0x89
7909
+ .sleb128 0
7910
+ .byte 0xa
7911
+ .2byte 0x148
7912
+ .byte 0x1e
7913
+ .byte 0x23
7914
+ .uleb128 0x8200008
7915
+ .byte 0x9f
7916
+ .8byte .LVL94
7917
+ .8byte .LVL96
7918
+ .2byte 0xc
7919
+ .byte 0x86
7920
+ .sleb128 0
7921
+ .byte 0xa
7922
+ .2byte 0x148
7923
+ .byte 0x1e
7924
+ .byte 0x23
7925
+ .uleb128 0x8200008
7926
+ .byte 0x9f
7927
+ .8byte .LVL96
7928
+ .8byte .LVL97
7929
+ .2byte 0x13
7930
+ .byte 0xf3
7931
+ .uleb128 0x1
7932
+ .byte 0x50
7933
+ .byte 0xc
7934
+ .4byte 0xffffffff
7935
+ .byte 0x1a
7936
+ .byte 0xa
7937
+ .2byte 0x148
7938
+ .byte 0x1e
7939
+ .byte 0x23
7940
+ .uleb128 0x8200008
7941
+ .byte 0x9f
7942
+ .8byte .LVL97
7943
+ .8byte .LFE232
7944
+ .2byte 0xc
7945
+ .byte 0x86
7946
+ .sleb128 0
7947
+ .byte 0xa
7948
+ .2byte 0x148
7949
+ .byte 0x1e
7950
+ .byte 0x23
7951
+ .uleb128 0x8200008
7952
+ .byte 0x9f
7953
+ .8byte 0
7954
+ .8byte 0
7955
+.LLST34:
7956
+ .8byte .LVL95
7957
+ .8byte .LVL96
7958
+ .2byte 0x1
7959
+ .byte 0x67
7960
+ .8byte .LVL97
7961
+ .8byte .LFE232
7962
+ .2byte 0x1
7963
+ .byte 0x67
7964
+ .8byte 0
7965
+ .8byte 0
7966
+.LLST35:
7967
+ .8byte .LVL90
7968
+ .8byte .LVL91
7969
+ .2byte 0x1
7970
+ .byte 0x51
7971
+ .8byte 0
7972
+ .8byte 0
7973
+.LLST36:
7974
+ .8byte .LVL98
7975
+ .8byte .LVL99-1
7976
+ .2byte 0x2
7977
+ .byte 0x83
7978
+ .sleb128 16
7979
+ .8byte 0
7980
+ .8byte 0
7981
+.LLST37:
7982
+ .8byte .LVL98
7983
+ .8byte .LVL99
7984
+ .2byte 0x1
7985
+ .byte 0x65
7986
+ .8byte 0
7987
+ .8byte 0
7988
+.LLST38:
7989
+ .8byte .LVL98
7990
+ .8byte .LVL99
7991
+ .2byte 0x1
7992
+ .byte 0x67
7993
+ .8byte 0
7994
+ .8byte 0
7995
+.LLST39:
7996
+ .8byte .LVL98
7997
+ .8byte .LVL99
7998
+ .2byte 0x1
7999
+ .byte 0x66
8000
+ .8byte 0
8001
+ .8byte 0
8002
+.LLST40:
8003
+ .8byte .LVL98
8004
+ .8byte .LVL99
8005
+ .2byte 0x2
8006
+ .byte 0x30
8007
+ .byte 0x9f
8008
+ .8byte 0
8009
+ .8byte 0
8010
+.LLST41:
8011
+ .8byte .LVL98
8012
+ .8byte .LVL99
8013
+ .2byte 0x2
8014
+ .byte 0x31
8015
+ .byte 0x9f
8016
+ .8byte 0
8017
+ .8byte 0
8018
+.LLST28:
8019
+ .8byte .LVL82
8020
+ .8byte .LVL83
8021
+ .2byte 0x1
8022
+ .byte 0x50
8023
+ .8byte .LVL83
8024
+ .8byte .LVL88
8025
+ .2byte 0x1
8026
+ .byte 0x63
8027
+ .8byte .LVL88
8028
+ .8byte .LVL89-1
8029
+ .2byte 0x1
8030
+ .byte 0x50
8031
+ .8byte .LVL89-1
8032
+ .8byte .LFE230
8033
+ .2byte 0x4
8034
+ .byte 0xf3
8035
+ .uleb128 0x1
8036
+ .byte 0x50
8037
+ .byte 0x9f
8038
+ .8byte 0
8039
+ .8byte 0
8040
+.LLST29:
8041
+ .8byte .LVL83
8042
+ .8byte .LVL88
8043
+ .2byte 0x1
8044
+ .byte 0x63
8045
+ .8byte .LVL88
8046
+ .8byte .LVL89-1
8047
+ .2byte 0x1
8048
+ .byte 0x50
8049
+ .8byte .LVL89-1
8050
+ .8byte .LFE230
8051
+ .2byte 0x4
8052
+ .byte 0xf3
8053
+ .uleb128 0x1
8054
+ .byte 0x50
8055
+ .byte 0x9f
8056
+ .8byte 0
8057
+ .8byte 0
8058
+.LLST30:
8059
+ .8byte .LVL85
8060
+ .8byte .LVL86
8061
+ .2byte 0x2
8062
+ .byte 0x31
8063
+ .byte 0x9f
8064
+ .8byte .LVL86
8065
+ .8byte .LVL87
8066
+ .2byte 0x2
8067
+ .byte 0x30
8068
+ .byte 0x9f
8069
+ .8byte 0
8070
+ .8byte 0
8071
+.LLST8:
8072
+ .8byte .LVL27
8073
+ .8byte .LVL28
8074
+ .2byte 0x1e
8075
+ .byte 0x86
8076
+ .sleb128 0
8077
+ .byte 0x8
8078
+ .byte 0x20
8079
+ .byte 0x24
8080
+ .byte 0x8
8081
+ .byte 0x20
8082
+ .byte 0x26
8083
+ .byte 0x8
8084
+ .byte 0x28
8085
+ .byte 0x1e
8086
+ .byte 0x85
8087
+ .sleb128 0
8088
+ .byte 0x8
8089
+ .byte 0x20
8090
+ .byte 0x24
8091
+ .byte 0x8
8092
+ .byte 0x20
8093
+ .byte 0x26
8094
+ .byte 0xa
8095
+ .2byte 0x148
8096
+ .byte 0x1e
8097
+ .byte 0x22
8098
+ .byte 0x23
8099
+ .uleb128 0x8200008
8100
+ .byte 0x9f
8101
+ .8byte .LVL28
8102
+ .8byte .LVL36
8103
+ .2byte 0x1e
8104
+ .byte 0x86
8105
+ .sleb128 -1
8106
+ .byte 0x8
8107
+ .byte 0x20
8108
+ .byte 0x24
8109
+ .byte 0x8
8110
+ .byte 0x20
8111
+ .byte 0x26
8112
+ .byte 0x8
8113
+ .byte 0x28
8114
+ .byte 0x1e
8115
+ .byte 0x85
8116
+ .sleb128 0
8117
+ .byte 0x8
8118
+ .byte 0x20
8119
+ .byte 0x24
8120
+ .byte 0x8
8121
+ .byte 0x20
8122
+ .byte 0x26
8123
+ .byte 0xa
8124
+ .2byte 0x148
8125
+ .byte 0x1e
8126
+ .byte 0x22
8127
+ .byte 0x23
8128
+ .uleb128 0x8200008
8129
+ .byte 0x9f
8130
+ .8byte 0
8131
+ .8byte 0
8132
+.LLST9:
8133
+ .8byte .LVL26
8134
+ .8byte .LVL38
8135
+ .2byte 0x1
8136
+ .byte 0x65
8137
+ .8byte 0
8138
+ .8byte 0
8139
+.LLST10:
8140
+ .8byte .LVL27
8141
+ .8byte .LVL28
8142
+ .2byte 0x1
8143
+ .byte 0x66
8144
+ .8byte .LVL28
8145
+ .8byte .LVL36
8146
+ .2byte 0x3
8147
+ .byte 0x86
8148
+ .sleb128 -1
8149
+ .byte 0x9f
8150
+ .8byte .LVL36
8151
+ .8byte .LVL38
8152
+ .2byte 0x1
8153
+ .byte 0x66
8154
+ .8byte 0
8155
+ .8byte 0
8156
+.LLST5:
8157
+ .8byte .LVL13
8158
+ .8byte .LVL14
8159
+ .2byte 0x1
8160
+ .byte 0x50
8161
+ .8byte .LVL14
8162
+ .8byte .LVL19
8163
+ .2byte 0x1
8164
+ .byte 0x63
8165
+ .8byte .LVL19
8166
+ .8byte .LVL21
8167
+ .2byte 0x5
8168
+ .byte 0x8b
8169
+ .sleb128 65536
8170
+ .byte 0x9f
8171
+ .8byte .LVL21
8172
+ .8byte .LVL22
8173
+ .2byte 0x4
8174
+ .byte 0xf3
8175
+ .uleb128 0x1
8176
+ .byte 0x50
8177
+ .byte 0x9f
8178
+ .8byte .LVL22
8179
+ .8byte .LVL24
8180
+ .2byte 0x1
8181
+ .byte 0x63
8182
+ .8byte .LVL24
8183
+ .8byte .LVL25
8184
+ .2byte 0x1
8185
+ .byte 0x50
8186
+ .8byte .LVL25
8187
+ .8byte .LFE226
8188
+ .2byte 0x4
8189
+ .byte 0xf3
8190
+ .uleb128 0x1
8191
+ .byte 0x50
8192
+ .byte 0x9f
8193
+ .8byte 0
8194
+ .8byte 0
8195
+.LLST6:
8196
+ .8byte .LVL15
8197
+ .8byte .LVL20
8198
+ .2byte 0x1
8199
+ .byte 0x67
8200
+ .8byte .LVL22
8201
+ .8byte .LVL24
8202
+ .2byte 0x1
8203
+ .byte 0x67
8204
+ .8byte 0
8205
+ .8byte 0
8206
+.LLST7:
8207
+ .8byte .LVL22
8208
+ .8byte .LVL24
8209
+ .2byte 0x3
8210
+ .byte 0x84
8211
+ .sleb128 -4
8212
+ .byte 0x9f
8213
+ .8byte 0
8214
+ .8byte 0
8215
+.LLST0:
8216
+ .8byte .LVL0
8217
+ .8byte .LVL1
8218
+ .2byte 0x1
8219
+ .byte 0x50
8220
+ .8byte .LVL1
8221
+ .8byte .LVL3
8222
+ .2byte 0x1
8223
+ .byte 0x55
8224
+ .8byte .LVL3
8225
+ .8byte .LFE225
8226
+ .2byte 0x4
8227
+ .byte 0xf3
8228
+ .uleb128 0x1
8229
+ .byte 0x50
8230
+ .byte 0x9f
8231
+ .8byte 0
8232
+ .8byte 0
8233
+.LLST1:
8234
+ .8byte .LVL0
8235
+ .8byte .LVL7
8236
+ .2byte 0x1
8237
+ .byte 0x51
8238
+ .8byte .LVL7
8239
+ .8byte .LFE225
8240
+ .2byte 0x4
8241
+ .byte 0xf3
8242
+ .uleb128 0x1
8243
+ .byte 0x51
8244
+ .byte 0x9f
8245
+ .8byte 0
8246
+ .8byte 0
8247
+.LLST2:
8248
+ .8byte .LVL0
8249
+ .8byte .LVL8-1
8250
+ .2byte 0x1
8251
+ .byte 0x52
8252
+ .8byte .LVL8-1
8253
+ .8byte .LFE225
8254
+ .2byte 0x4
8255
+ .byte 0xf3
8256
+ .uleb128 0x1
8257
+ .byte 0x52
8258
+ .byte 0x9f
8259
+ .8byte 0
8260
+ .8byte 0
8261
+.LLST3:
8262
+ .8byte .LVL2
8263
+ .8byte .LVL3
8264
+ .2byte 0x1
8265
+ .byte 0x53
8266
+ .8byte .LVL4
8267
+ .8byte .LVL6
8268
+ .2byte 0x1
8269
+ .byte 0x53
8270
+ .8byte 0
8271
+ .8byte 0
8272
+.LLST4:
8273
+ .8byte .LVL11
8274
+ .8byte .LVL12
8275
+ .2byte 0x1
8276
+ .byte 0x50
8277
+ .8byte .LVL12
8278
+ .8byte .LFE218
8279
+ .2byte 0x4
8280
+ .byte 0xf3
8281
+ .uleb128 0x1
8282
+ .byte 0x50
8283
+ .byte 0x9f
8284
+ .8byte 0
8285
+ .8byte 0
8286
+.LLST11:
8287
+ .8byte .LVL39
8288
+ .8byte .LVL41
8289
+ .2byte 0x1
8290
+ .byte 0x50
8291
+ .8byte .LVL41
8292
+ .8byte .LVL71
8293
+ .2byte 0x1
8294
+ .byte 0x63
8295
+ .8byte .LVL71
8296
+ .8byte .LVL73
8297
+ .2byte 0x1
8298
+ .byte 0x53
8299
+ .8byte .LVL73
8300
+ .8byte .LFE242
8301
+ .2byte 0x4
8302
+ .byte 0xf3
8303
+ .uleb128 0x1
8304
+ .byte 0x50
8305
+ .byte 0x9f
8306
+ .8byte 0
8307
+ .8byte 0
8308
+.LLST12:
8309
+ .8byte .LVL39
8310
+ .8byte .LVL41
8311
+ .2byte 0x1
8312
+ .byte 0x51
8313
+ .8byte .LVL41
8314
+ .8byte .LVL69
8315
+ .2byte 0x1
8316
+ .byte 0x66
8317
+ .8byte .LVL69
8318
+ .8byte .LFE242
8319
+ .2byte 0x4
8320
+ .byte 0xf3
8321
+ .uleb128 0x1
8322
+ .byte 0x51
8323
+ .byte 0x9f
8324
+ .8byte 0
8325
+ .8byte 0
8326
+.LLST13:
8327
+ .8byte .LVL39
8328
+ .8byte .LVL41
8329
+ .2byte 0x1
8330
+ .byte 0x52
8331
+ .8byte .LVL41
8332
+ .8byte .LVL74
8333
+ .2byte 0x1
8334
+ .byte 0x64
8335
+ .8byte .LVL74
8336
+ .8byte .LVL76
8337
+ .2byte 0x4
8338
+ .byte 0xf3
8339
+ .uleb128 0x1
8340
+ .byte 0x52
8341
+ .byte 0x9f
8342
+ .8byte .LVL76
8343
+ .8byte .LVL79
8344
+ .2byte 0x1
8345
+ .byte 0x64
8346
+ .8byte .LVL79
8347
+ .8byte .LFE242
8348
+ .2byte 0x4
8349
+ .byte 0xf3
8350
+ .uleb128 0x1
8351
+ .byte 0x52
8352
+ .byte 0x9f
8353
+ .8byte 0
8354
+ .8byte 0
8355
+.LLST14:
8356
+ .8byte .LVL39
8357
+ .8byte .LVL41
8358
+ .2byte 0x1
8359
+ .byte 0x53
8360
+ .8byte .LVL41
8361
+ .8byte .LVL49
8362
+ .2byte 0x1
8363
+ .byte 0x69
8364
+ .8byte .LVL49
8365
+ .8byte .LVL52
8366
+ .2byte 0x4
8367
+ .byte 0xf3
8368
+ .uleb128 0x1
8369
+ .byte 0x53
8370
+ .byte 0x9f
8371
+ .8byte .LVL52
8372
+ .8byte .LVL57
8373
+ .2byte 0x1
8374
+ .byte 0x69
8375
+ .8byte .LVL57
8376
+ .8byte .LFE242
8377
+ .2byte 0x4
8378
+ .byte 0xf3
8379
+ .uleb128 0x1
8380
+ .byte 0x53
8381
+ .byte 0x9f
8382
+ .8byte 0
8383
+ .8byte 0
8384
+.LLST15:
8385
+ .8byte .LVL61
8386
+ .8byte .LVL62
8387
+ .2byte 0x1
8388
+ .byte 0x50
8389
+ .8byte .LVL62
8390
+ .8byte .LVL70
8391
+ .2byte 0x1
8392
+ .byte 0x67
8393
+ .8byte 0
8394
+ .8byte 0
8395
+.LLST16:
8396
+ .8byte .LVL65
8397
+ .8byte .LVL66
8398
+ .2byte 0x1
8399
+ .byte 0x50
8400
+ .8byte .LVL66
8401
+ .8byte .LVL75
8402
+ .2byte 0x1
8403
+ .byte 0x65
8404
+ .8byte .LVL76
8405
+ .8byte .LVL80
8406
+ .2byte 0x1
8407
+ .byte 0x65
8408
+ .8byte .LVL80
8409
+ .8byte .LVL81-1
8410
+ .2byte 0x2
8411
+ .byte 0x72
8412
+ .sleb128 32
8413
+ .8byte 0
8414
+ .8byte 0
8415
+.LLST17:
8416
+ .8byte .LVL48
8417
+ .8byte .LVL52
8418
+ .2byte 0x2
8419
+ .byte 0x30
8420
+ .byte 0x9f
8421
+ .8byte .LVL58
8422
+ .8byte .LVL70
8423
+ .2byte 0x2
8424
+ .byte 0x31
8425
+ .byte 0x9f
8426
+ .8byte 0
8427
+ .8byte 0
8428
+.LLST18:
8429
+ .8byte .LVL40
8430
+ .8byte .LVL41
8431
+ .2byte 0x1
8432
+ .byte 0x50
8433
+ .8byte .LVL41
8434
+ .8byte .LVL71
8435
+ .2byte 0x1
8436
+ .byte 0x63
8437
+ .8byte .LVL71
8438
+ .8byte .LVL73
8439
+ .2byte 0x1
8440
+ .byte 0x53
8441
+ .8byte .LVL73
8442
+ .8byte .LFE242
8443
+ .2byte 0x4
8444
+ .byte 0xf3
8445
+ .uleb128 0x1
8446
+ .byte 0x50
8447
+ .byte 0x9f
8448
+ .8byte 0
8449
+ .8byte 0
8450
+.LLST19:
8451
+ .8byte .LVL40
8452
+ .8byte .LVL41
8453
+ .2byte 0x1
8454
+ .byte 0x52
8455
+ .8byte .LVL41
8456
+ .8byte .LVL74
8457
+ .2byte 0x1
8458
+ .byte 0x64
8459
+ .8byte .LVL74
8460
+ .8byte .LVL76
8461
+ .2byte 0x4
8462
+ .byte 0xf3
8463
+ .uleb128 0x1
8464
+ .byte 0x52
8465
+ .byte 0x9f
8466
+ .8byte .LVL76
8467
+ .8byte .LVL79
8468
+ .2byte 0x1
8469
+ .byte 0x64
8470
+ .8byte .LVL79
8471
+ .8byte .LFE242
8472
+ .2byte 0x4
8473
+ .byte 0xf3
8474
+ .uleb128 0x1
8475
+ .byte 0x52
8476
+ .byte 0x9f
8477
+ .8byte 0
8478
+ .8byte 0
8479
+.LLST20:
8480
+ .8byte .LVL40
8481
+ .8byte .LVL41
8482
+ .2byte 0x1
8483
+ .byte 0x53
8484
+ .8byte .LVL41
8485
+ .8byte .LVL47
8486
+ .2byte 0x1
8487
+ .byte 0x69
8488
+ .8byte .LVL52
8489
+ .8byte .LVL57
8490
+ .2byte 0x1
8491
+ .byte 0x69
8492
+ .8byte 0
8493
+ .8byte 0
8494
+.LLST21:
8495
+ .8byte .LVL40
8496
+ .8byte .LVL41
8497
+ .2byte 0x2
8498
+ .byte 0x30
8499
+ .byte 0x9f
8500
+ .8byte .LVL41
8501
+ .8byte .LVL47
8502
+ .2byte 0x1
8503
+ .byte 0x67
8504
+ .8byte .LVL52
8505
+ .8byte .LVL57
8506
+ .2byte 0x1
8507
+ .byte 0x67
8508
+ .8byte 0
8509
+ .8byte 0
8510
+.LLST22:
8511
+ .8byte .LVL41
8512
+ .8byte .LVL47
8513
+ .2byte 0x1
8514
+ .byte 0x65
8515
+ .8byte .LVL52
8516
+ .8byte .LVL57
8517
+ .2byte 0x1
8518
+ .byte 0x65
8519
+ .8byte 0
8520
+ .8byte 0
8521
+.LLST23:
8522
+ .8byte .LVL42
8523
+ .8byte .LVL45
8524
+ .2byte 0x7
8525
+ .byte 0xa
8526
+ .2byte 0x4e20
8527
+ .byte 0x88
8528
+ .sleb128 0
8529
+ .byte 0x1c
8530
+ .byte 0x9f
8531
+ .8byte .LVL52
8532
+ .8byte .LVL53
8533
+ .2byte 0x7
8534
+ .byte 0xa
8535
+ .2byte 0x4e20
8536
+ .byte 0x88
8537
+ .sleb128 0
8538
+ .byte 0x1c
8539
+ .byte 0x9f
8540
+ .8byte .LVL53
8541
+ .8byte .LVL54
8542
+ .2byte 0x7
8543
+ .byte 0xa
8544
+ .2byte 0x4e21
8545
+ .byte 0x88
8546
+ .sleb128 0
8547
+ .byte 0x1c
8548
+ .byte 0x9f
8549
+ .8byte .LVL54
8550
+ .8byte .LVL55
8551
+ .2byte 0x7
8552
+ .byte 0xa
8553
+ .2byte 0x4e20
8554
+ .byte 0x88
8555
+ .sleb128 0
8556
+ .byte 0x1c
8557
+ .byte 0x9f
8558
+ .8byte .LVL55
8559
+ .8byte .LVL57
8560
+ .2byte 0x2
8561
+ .byte 0x30
8562
+ .byte 0x9f
8563
+ .8byte 0
8564
+ .8byte 0
8565
+.LLST24:
8566
+ .8byte .LVL70
8567
+ .8byte .LVL75
8568
+ .2byte 0x1
8569
+ .byte 0x65
8570
+ .8byte .LVL76
8571
+ .8byte .LVL80
8572
+ .2byte 0x1
8573
+ .byte 0x65
8574
+ .8byte .LVL80
8575
+ .8byte .LVL81-1
8576
+ .2byte 0x2
8577
+ .byte 0x72
8578
+ .sleb128 32
8579
+ .8byte 0
8580
+ .8byte 0
8581
+.LLST25:
8582
+ .8byte .LVL70
8583
+ .8byte .LVL74
8584
+ .2byte 0x1
8585
+ .byte 0x64
8586
+ .8byte .LVL74
8587
+ .8byte .LVL76
8588
+ .2byte 0x4
8589
+ .byte 0xf3
8590
+ .uleb128 0x1
8591
+ .byte 0x52
8592
+ .byte 0x9f
8593
+ .8byte .LVL76
8594
+ .8byte .LVL79
8595
+ .2byte 0x1
8596
+ .byte 0x64
8597
+ .8byte .LVL79
8598
+ .8byte .LFE242
8599
+ .2byte 0x4
8600
+ .byte 0xf3
8601
+ .uleb128 0x1
8602
+ .byte 0x52
8603
+ .byte 0x9f
8604
+ .8byte 0
8605
+ .8byte 0
8606
+.LLST26:
8607
+ .8byte .LVL70
8608
+ .8byte .LVL71
8609
+ .2byte 0x1
8610
+ .byte 0x63
8611
+ .8byte .LVL71
8612
+ .8byte .LVL73
8613
+ .2byte 0x1
8614
+ .byte 0x53
8615
+ .8byte .LVL73
8616
+ .8byte .LFE242
8617
+ .2byte 0x4
8618
+ .byte 0xf3
8619
+ .uleb128 0x1
8620
+ .byte 0x50
8621
+ .byte 0x9f
8622
+ .8byte 0
8623
+ .8byte 0
8624
+.LLST27:
8625
+ .8byte .LVL72
8626
+ .8byte .LVL73
8627
+ .2byte 0x1
8628
+ .byte 0x51
8629
+ .8byte .LVL76
8630
+ .8byte .LVL78
8631
+ .2byte 0x1
8632
+ .byte 0x51
8633
+ .8byte 0
8634
+ .8byte 0
8635
+ .section .debug_aranges,"",@progbits
8636
+ .4byte 0xec
8637
+ .2byte 0x2
8638
+ .4byte .Ldebug_info0
8639
+ .byte 0x8
8640
+ .byte 0
8641
+ .2byte 0
8642
+ .2byte 0
8643
+ .8byte .LFB225
8644
+ .8byte .LFE225-.LFB225
8645
+ .8byte .LFB238
8646
+ .8byte .LFE238-.LFB238
8647
+ .8byte .LFB218
8648
+ .8byte .LFE218-.LFB218
8649
+ .8byte .LFB226
8650
+ .8byte .LFE226-.LFB226
8651
+ .8byte .LFB227
8652
+ .8byte .LFE227-.LFB227
8653
+ .8byte .LFB242
8654
+ .8byte .LFE242-.LFB242
8655
+ .8byte .LFB230
8656
+ .8byte .LFE230-.LFB230
8657
+ .8byte .LFB232
8658
+ .8byte .LFE232-.LFB232
8659
+ .8byte .LFB233
8660
+ .8byte .LFE233-.LFB233
8661
+ .8byte .LFB234
8662
+ .8byte .LFE234-.LFB234
8663
+ .8byte .LFB236
8664
+ .8byte .LFE236-.LFB236
8665
+ .8byte .LFB237
8666
+ .8byte .LFE237-.LFB237
8667
+ .8byte .LFB239
8668
+ .8byte .LFE239-.LFB239
8669
+ .8byte 0
8670
+ .8byte 0
8671
+ .section .debug_ranges,"",@progbits
8672
+.Ldebug_ranges0:
8673
+ .8byte .LBB32
8674
+ .8byte .LBE32
8675
+ .8byte .LBB35
8676
+ .8byte .LBE35
8677
+ .8byte 0
8678
+ .8byte 0
8679
+ .8byte .LBB52
8680
+ .8byte .LBE52
8681
+ .8byte .LBB55
8682
+ .8byte .LBE55
8683
+ .8byte 0
8684
+ .8byte 0
8685
+ .8byte .LBB56
8686
+ .8byte .LBE56
8687
+ .8byte .LBB69
8688
+ .8byte .LBE69
8689
+ .8byte .LBB70
8690
+ .8byte .LBE70
8691
+ .8byte .LBB71
8692
+ .8byte .LBE71
8693
+ .8byte .LBB72
8694
+ .8byte .LBE72
8695
+ .8byte .LBB73
8696
+ .8byte .LBE73
8697
+ .8byte 0
8698
+ .8byte 0
8699
+ .8byte .LBB60
8700
+ .8byte .LBE60
8701
+ .8byte .LBB63
8702
+ .8byte .LBE63
8703
+ .8byte 0
8704
+ .8byte 0
8705
+ .8byte .LBB78
8706
+ .8byte .LBE78
8707
+ .8byte .LBB83
8708
+ .8byte .LBE83
8709
+ .8byte 0
8710
+ .8byte 0
8711
+ .8byte .LBB90
8712
+ .8byte .LBE90
8713
+ .8byte .LBB93
8714
+ .8byte .LBE93
8715
+ .8byte 0
8716
+ .8byte 0
8717
+ .8byte .LBB102
8718
+ .8byte .LBE102
8719
+ .8byte .LBB109
8720
+ .8byte .LBE109
8721
+ .8byte 0
8722
+ .8byte 0
8723
+ .8byte .LBB104
8724
+ .8byte .LBE104
8725
+ .8byte .LBB107
8726
+ .8byte .LBE107
8727
+ .8byte 0
8728
+ .8byte 0
8729
+ .8byte .LBB124
8730
+ .8byte .LBE124
8731
+ .8byte .LBB135
8732
+ .8byte .LBE135
8733
+ .8byte 0
8734
+ .8byte 0
8735
+ .8byte .LBB126
8736
+ .8byte .LBE126
8737
+ .8byte .LBB130
8738
+ .8byte .LBE130
8739
+ .8byte .LBB133
8740
+ .8byte .LBE133
8741
+ .8byte 0
8742
+ .8byte 0
8743
+ .8byte .LFB225
8744
+ .8byte .LFE225
8745
+ .8byte .LFB238
8746
+ .8byte .LFE238
8747
+ .8byte .LFB218
8748
+ .8byte .LFE218
8749
+ .8byte .LFB226
8750
+ .8byte .LFE226
8751
+ .8byte .LFB227
8752
+ .8byte .LFE227
8753
+ .8byte .LFB242
8754
+ .8byte .LFE242
8755
+ .8byte .LFB230
8756
+ .8byte .LFE230
8757
+ .8byte .LFB232
8758
+ .8byte .LFE232
8759
+ .8byte .LFB233
8760
+ .8byte .LFE233
8761
+ .8byte .LFB234
8762
+ .8byte .LFE234
8763
+ .8byte .LFB236
8764
+ .8byte .LFE236
8765
+ .8byte .LFB237
8766
+ .8byte .LFE237
8767
+ .8byte .LFB239
8768
+ .8byte .LFE239
8769
+ .8byte 0
8770
+ .8byte 0
8771
+ .section .debug_line,"",@progbits
8772
+.Ldebug_line0:
8773
+ .section .debug_str,"MS",@progbits,1
8774
+.LASF83:
8775
+ .string "off_mem_rsvmap"
8776
+.LASF166:
8777
+ .string "UCLASS_I2C_EEPROM"
8778
+.LASF298:
8779
+ .string "jt_funcs"
8780
+.LASF171:
8781
+ .string "UCLASS_IRQ"
8782
+.LASF133:
8783
+ .string "initrd_start"
8784
+.LASF165:
8785
+ .string "UCLASS_I2C"
8786
+.LASF13:
8787
+ .string "sizetype"
8788
+.LASF312:
8789
+ .string "net_hostname"
8790
+.LASF36:
8791
+ .string "start"
8792
+.LASF206:
8793
+ .string "UCLASS_SPI"
8794
+.LASF169:
8795
+ .string "UCLASS_I2S"
8796
+.LASF334:
8797
+ .string "NETLOOP_RESTART"
8798
+.LASF167:
8799
+ .string "UCLASS_I2C_GENERIC"
8800
+.LASF179:
8801
+ .string "UCLASS_MOD_EXP"
8802
+.LASF230:
8803
+ .string "UCLASS_IO_DOMAIN"
8804
+.LASF251:
8805
+ .string "using_pre_serial"
8806
+.LASF200:
8807
+ .string "UCLASS_RKNAND"
8808
+.LASF142:
8809
+ .string "UCLASS_DEMO"
8810
+.LASF386:
8811
+ .string "rip_fail"
8812
+.LASF91:
8813
+ .string "ih_magic"
8814
+.LASF29:
8815
+ .string "list_head"
8816
+.LASF292:
8817
+ .string "pm_ctx_phys"
8818
+.LASF146:
8819
+ .string "UCLASS_TEST_PROBE"
8820
+.LASF226:
8821
+ .string "UCLASS_KEY"
8822
+.LASF64:
8823
+ .string "bi_intfreq"
8824
+.LASF11:
8825
+ .string "phys_addr_t"
8826
+.LASF221:
8827
+ .string "UCLASS_VIDEO_BRIDGE"
8828
+.LASF291:
8829
+ .string "video_bottom"
8830
+.LASF5:
8831
+ .string "__u8"
8832
+.LASF390:
8833
+ .string "task_list"
8834
+.LASF333:
8835
+ .string "NETLOOP_CONTINUE"
8836
+.LASF209:
8837
+ .string "UCLASS_SPI_GENERIC"
8838
+.LASF286:
8839
+ .string "malloc_base"
8840
+.LASF382:
8841
+ .string "tid_name"
8842
+.LASF40:
8843
+ .string "flash_info_t"
8844
+.LASF184:
8845
+ .string "UCLASS_PANEL"
8846
+.LASF108:
8847
+ .string "comp"
8848
+.LASF103:
8849
+ .string "image_header_t"
8850
+.LASF138:
8851
+ .string "state"
8852
+.LASF428:
8853
+ .string "disable_serror"
8854
+.LASF159:
8855
+ .string "UCLASS_CROS_EC"
8856
+.LASF360:
8857
+ .string "BOOT_MODE_QUIESCENT"
8858
+.LASF58:
8859
+ .string "bi_dsp_freq"
8860
+.LASF105:
8861
+ .string "image_start"
8862
+.LASF350:
8863
+ .string "BOOT_MODE_NORMAL"
8864
+.LASF440:
8865
+ .string "invalidate_icache_all"
8866
+.LASF438:
8867
+ .string "disable_interrupts"
8868
+.LASF144:
8869
+ .string "UCLASS_TEST_FDT"
8870
+.LASF49:
8871
+ .string "bd_info"
8872
+.LASF331:
8873
+ .string "uclass_id"
8874
+.LASF95:
8875
+ .string "ih_load"
8876
+.LASF215:
8877
+ .string "UCLASS_UFS"
8878
+.LASF302:
8879
+ .string "__dtb_dt_spl_begin"
8880
+.LASF376:
8881
+ .string "TASK_LOAD_UBOOT"
8882
+.LASF7:
8883
+ .string "__u32"
8884
+.LASF149:
8885
+ .string "UCLASS_PCI_EMUL"
8886
+.LASF449:
8887
+ .string "/home4/cjh/uboot-nextdev-v3"
8888
+.LASF289:
8889
+ .string "cur_serial_dev"
8890
+.LASF351:
8891
+ .string "BOOT_MODE_RECOVERY"
8892
+.LASF318:
8893
+ .string "net_tx_packet"
8894
+.LASF225:
8895
+ .string "UCLASS_FG"
8896
+.LASF317:
8897
+ .string "net_server_ip"
8898
+.LASF325:
8899
+ .string "net_native_vlan"
8900
+.LASF265:
8901
+ .string "ram_top_ext_size"
8902
+.LASF223:
8903
+ .string "UCLASS_VIDEO_CRTC"
8904
+.LASF158:
8905
+ .string "UCLASS_CODEC"
8906
+.LASF447:
8907
+ .ascii "GNU C11 6.3.1 20170404 -ms"
8908
+ .string "trict-align -march=armv8-a+nosimd -mlittle-endian -mabi=lp64 -g -Os -fno-builtin -ffreestanding -fshort-wchar -fno-stack-protector -fno-delete-null-pointer-checks -fstack-usage -fno-pic -ffunction-sections -fdata-sections -ffixed-r9 -fno-common -ffixed-x18"
8909
+.LASF283:
8910
+ .string "env_buf"
8911
+.LASF20:
8912
+ .string "errno"
8913
+.LASF15:
8914
+ .string "long int"
8915
+.LASF53:
8916
+ .string "bi_flashsize"
8917
+.LASF339:
8918
+ .string "__bss_end"
8919
+.LASF189:
8920
+ .string "UCLASS_PHY"
8921
+.LASF76:
8922
+ .string "IRQ_STACK_START_IN"
8923
+.LASF87:
8924
+ .string "size_dt_strings"
8925
+.LASF220:
8926
+ .string "UCLASS_VIDEO"
8927
+.LASF369:
8928
+ .string "EVT_CRYPTO"
8929
+.LASF266:
8930
+ .string "relocaddr"
8931
+.LASF406:
8932
+ .string "mpb_post"
8933
+.LASF448:
8934
+ .string "common/mp_boot.c"
8935
+.LASF328:
8936
+ .string "net_boot_file_size"
8937
+.LASF387:
8938
+ .string "cpu_core"
8939
+.LASF432:
8940
+ .string "run_command"
8941
+.LASF97:
8942
+ .string "ih_dcrc"
8943
+.LASF63:
8944
+ .string "bi_ethspeed"
8945
+.LASF141:
8946
+ .string "UCLASS_ROOT"
8947
+.LASF26:
8948
+ .string "ide_bus_offset"
8949
+.LASF374:
8950
+ .string "TASK_INIT_DISPLAY"
8951
+.LASF315:
8952
+ .string "net_server_ethaddr"
8953
+.LASF66:
8954
+ .string "bi_arch_number"
8955
+.LASF3:
8956
+ .string "signed char"
8957
+.LASF172:
8958
+ .string "UCLASS_KEYBOARD"
8959
+.LASF18:
8960
+ .string "uint8_t"
8961
+.LASF38:
8962
+ .string "udevice"
8963
+.LASF436:
8964
+ .string "udelay"
8965
+.LASF99:
8966
+ .string "ih_arch"
8967
+.LASF80:
8968
+ .string "totalsize"
8969
+.LASF92:
8970
+ .string "ih_hcrc"
8971
+.LASF268:
8972
+ .string "mon_len"
8973
+.LASF107:
8974
+ .string "load"
8975
+.LASF214:
8976
+ .string "UCLASS_TPM"
8977
+.LASF43:
8978
+ .string "lmb_property"
8979
+.LASF85:
8980
+ .string "last_comp_version"
8981
+.LASF0:
8982
+ .string "unsigned char"
8983
+.LASF140:
8984
+ .string "images"
8985
+.LASF341:
8986
+ .string "priv"
8987
+.LASF229:
8988
+ .string "UCLASS_DVFS"
8989
+.LASF59:
8990
+ .string "bi_ddr_freq"
8991
+.LASF419:
8992
+ .string "mpb_initial"
8993
+.LASF173:
8994
+ .string "UCLASS_LED"
8995
+.LASF94:
8996
+ .string "ih_size"
8997
+.LASF445:
8998
+ .string "rockchip_get_boot_mode"
8999
+.LASF437:
9000
+ .string "dcache_enable"
9001
+.LASF203:
9002
+ .string "UCLASS_SCMI_AGENT"
9003
+.LASF233:
9004
+ .string "UCLASS_MDIO"
9005
+.LASF22:
9006
+ .string "_Bool"
9007
+.LASF337:
9008
+ .string "net_state"
9009
+.LASF168:
9010
+ .string "UCLASS_I2C_MUX"
9011
+.LASF14:
9012
+ .string "char"
9013
+.LASF24:
9014
+ .string "_binary_u_boot_bin_start"
9015
+.LASF219:
9016
+ .string "UCLASS_USB_GADGET_GENERIC"
9017
+.LASF335:
9018
+ .string "NETLOOP_SUCCESS"
9019
+.LASF433:
9020
+ .string "printf"
9021
+.LASF385:
9022
+ .string "ptid_mask"
9023
+.LASF332:
9024
+ .string "net_loop_state"
9025
+.LASF247:
9026
+ .string "tlb_size"
9027
+.LASF274:
9028
+ .string "dm_root_f"
9029
+.LASF157:
9030
+ .string "UCLASS_AMP"
9031
+.LASF195:
9032
+ .string "UCLASS_PWRSEQ"
9033
+.LASF123:
9034
+ .string "fit_hdr_fdt"
9035
+.LASF326:
9036
+ .string "net_restart_wrap"
9037
+.LASF314:
9038
+ .string "net_ethaddr"
9039
+.LASF256:
9040
+ .string "flags"
9041
+.LASF100:
9042
+ .string "ih_type"
9043
+.LASF368:
9044
+ .string "EVT_BOOT_SIZE"
9045
+.LASF81:
9046
+ .string "off_dt_struct"
9047
+.LASF429:
9048
+ .string "mdelay"
9049
+.LASF54:
9050
+ .string "bi_flashoffset"
9051
+.LASF327:
9052
+ .string "net_boot_file_name"
9053
+.LASF143:
9054
+ .string "UCLASS_TEST"
9055
+.LASF413:
9056
+ .string "mpb_task_dump"
9057
+.LASF93:
9058
+ .string "ih_time"
9059
+.LASF258:
9060
+ .string "bus_clk"
9061
+.LASF196:
9062
+ .string "UCLASS_RAM"
9063
+.LASF162:
9064
+ .string "UCLASS_ETH"
9065
+.LASF377:
9066
+ .string "TASK_LOAD_FIT"
9067
+.LASF104:
9068
+ .string "image_info"
9069
+.LASF110:
9070
+ .string "arch"
9071
+.LASF260:
9072
+ .string "mem_clk"
9073
+.LASF257:
9074
+ .string "cpu_clk"
9075
+.LASF32:
9076
+ .string "select_hwpart"
9077
+.LASF319:
9078
+ .string "net_rx_packets"
9079
+.LASF75:
9080
+ .string "_datarelro_start_ofs"
9081
+.LASF17:
9082
+ .string "ulong"
9083
+.LASF384:
9084
+ .string "task_fn"
9085
+.LASF96:
9086
+ .string "ih_ep"
9087
+.LASF45:
9088
+ .string "lmb_region"
9089
+.LASF388:
9090
+ .string "task"
9091
+.LASF408:
9092
+ .string "mpb_task_wait_timeout_done"
9093
+.LASF416:
9094
+ .string "tid_to_task_index"
9095
+.LASF118:
9096
+ .string "fit_uname_os"
9097
+.LASF60:
9098
+ .string "bi_bootflags"
9099
+.LASF316:
9100
+ .string "net_ip"
9101
+.LASF278:
9102
+ .string "fdt_size"
9103
+.LASF310:
9104
+ .string "net_dns_server"
9105
+.LASF338:
9106
+ .string "__bss_start"
9107
+.LASF330:
9108
+ .string "net_ping_ip"
9109
+.LASF47:
9110
+ .string "memory"
9111
+.LASF78:
9112
+ .string "fdt_header"
9113
+.LASF175:
9114
+ .string "UCLASS_MAILBOX"
9115
+.LASF343:
9116
+ .string "filename"
9117
+.LASF130:
9118
+ .string "rd_end"
9119
+.LASF269:
9120
+ .string "irq_sp"
9121
+.LASF135:
9122
+ .string "cmdline_start"
9123
+.LASF255:
9124
+ .string "global_data"
9125
+.LASF371:
9126
+ .string "EVT_SIMPLE_BOOTM"
9127
+.LASF379:
9128
+ .string "TASK_HASH_ANDROID"
9129
+.LASF204:
9130
+ .string "UCLASS_SCSI"
9131
+.LASF217:
9132
+ .string "UCLASS_USB_DEV_GENERIC"
9133
+.LASF176:
9134
+ .string "UCLASS_MASS_STORAGE"
9135
+.LASF1:
9136
+ .string "long unsigned int"
9137
+.LASF151:
9138
+ .string "UCLASS_SIMPLE_BUS"
9139
+.LASF299:
9140
+ .string "gd_t"
9141
+.LASF311:
9142
+ .string "net_nis_domain"
9143
+.LASF125:
9144
+ .string "fit_noffset_fdt"
9145
+.LASF370:
9146
+ .string "EVT_LINUX"
9147
+.LASF342:
9148
+ .string "bl_len"
9149
+.LASF446:
9150
+ .string "get_ticks"
9151
+.LASF336:
9152
+ .string "NETLOOP_FAIL"
9153
+.LASF224:
9154
+ .string "UCLASS_WDT"
9155
+.LASF245:
9156
+ .string "timer_reset_value"
9157
+.LASF270:
9158
+ .string "start_addr_sp"
9159
+.LASF55:
9160
+ .string "bi_sramstart"
9161
+.LASF25:
9162
+ .string "_binary_u_boot_bin_end"
9163
+.LASF271:
9164
+ .string "reloc_off"
9165
+.LASF86:
9166
+ .string "boot_cpuid_phys"
9167
+.LASF244:
9168
+ .string "lastinc"
9169
+.LASF248:
9170
+ .string "tlb_fillptr"
9171
+.LASF121:
9172
+ .string "fit_uname_rd"
9173
+.LASF210:
9174
+ .string "UCLASS_SYSCON"
9175
+.LASF116:
9176
+ .string "fit_uname_cfg"
9177
+.LASF205:
9178
+ .string "UCLASS_SERIAL"
9179
+.LASF324:
9180
+ .string "net_our_vlan"
9181
+.LASF294:
9182
+ .string "serial"
9183
+.LASF154:
9184
+ .string "UCLASS_BLK"
9185
+.LASF111:
9186
+ .string "image_info_t"
9187
+.LASF150:
9188
+ .string "UCLASS_USB_EMUL"
9189
+.LASF439:
9190
+ .string "icache_disable"
9191
+.LASF246:
9192
+ .string "tlb_addr"
9193
+.LASF354:
9194
+ .string "BOOT_MODE_CHARGING"
9195
+.LASF188:
9196
+ .string "UCLASS_PCI_GENERIC"
9197
+.LASF383:
9198
+ .string "task_t"
9199
+.LASF423:
9200
+ .string "spl_load_android"
9201
+.LASF404:
9202
+ .string "ticks"
9203
+.LASF106:
9204
+ .string "image_len"
9205
+.LASF375:
9206
+ .string "TASK_LOAD_BASEPARAMETER"
9207
+.LASF394:
9208
+ .string "wait_evt"
9209
+.LASF61:
9210
+ .string "bi_ip_addr"
9211
+.LASF409:
9212
+ .string "timeout_ms"
9213
+.LASF190:
9214
+ .string "UCLASS_PINCONFIG"
9215
+.LASF399:
9216
+ .string "smp_entry"
9217
+.LASF212:
9218
+ .string "UCLASS_THERMAL"
9219
+.LASF114:
9220
+ .string "legacy_hdr_os_copy"
9221
+.LASF367:
9222
+ .string "EVT_BOOT_ADDR"
9223
+.LASF9:
9224
+ .string "long long int"
9225
+.LASF277:
9226
+ .string "new_fdt"
9227
+.LASF21:
9228
+ .string "___strtok"
9229
+.LASF329:
9230
+ .string "net_boot_file_expected_size_in_blocks"
9231
+.LASF252:
9232
+ .string "enable"
9233
+.LASF411:
9234
+ .string "ptid"
9235
+.LASF183:
9236
+ .string "UCLASS_NVME"
9237
+.LASF249:
9238
+ .string "tlb_emerg"
9239
+.LASF112:
9240
+ .string "bootm_headers"
9241
+.LASF37:
9242
+ .string "protect"
9243
+.LASF216:
9244
+ .string "UCLASS_USB"
9245
+.LASF227:
9246
+ .string "UCLASS_RC"
9247
+.LASF414:
9248
+ .string "mpb_task_is_done"
9249
+.LASF284:
9250
+ .string "timebase_h"
9251
+.LASF285:
9252
+ .string "timebase_l"
9253
+.LASF160:
9254
+ .string "UCLASS_DISPLAY"
9255
+.LASF323:
9256
+ .string "net_null_ethaddr"
9257
+.LASF263:
9258
+ .string "env_valid"
9259
+.LASF228:
9260
+ .string "UCLASS_CHARGE_DISPLAY"
9261
+.LASF303:
9262
+ .string "load_addr"
9263
+.LASF117:
9264
+ .string "fit_hdr_os"
9265
+.LASF73:
9266
+ .string "_datarelrolocal_start_ofs"
9267
+.LASF412:
9268
+ .string "timeout"
9269
+.LASF361:
9270
+ .string "BOOT_MODE_UNDEFINE"
9271
+.LASF254:
9272
+ .string "addr"
9273
+.LASF344:
9274
+ .string "read"
9275
+.LASF355:
9276
+ .string "BOOT_MODE_UMS"
9277
+.LASF8:
9278
+ .string "unsigned int"
9279
+.LASF16:
9280
+ .string "ushort"
9281
+.LASF418:
9282
+ .string "task_is_registered"
9283
+.LASF281:
9284
+ .string "ufdt_blob"
9285
+.LASF426:
9286
+ .string "spl_init_display"
9287
+.LASF287:
9288
+ .string "malloc_limit"
9289
+.LASF417:
9290
+ .string "mpb_task_register"
9291
+.LASF192:
9292
+ .string "UCLASS_PMIC"
9293
+.LASF113:
9294
+ .string "legacy_hdr_os"
9295
+.LASF82:
9296
+ .string "off_dt_strings"
9297
+.LASF397:
9298
+ .string "mpb_init_1"
9299
+.LASF300:
9300
+ .string "monitor_flash_len"
9301
+.LASF177:
9302
+ .string "UCLASS_MISC"
9303
+.LASF51:
9304
+ .string "bi_memsize"
9305
+.LASF410:
9306
+ .string "mpb_task_wait_parent"
9307
+.LASF23:
9308
+ .string "image_base"
9309
+.LASF395:
9310
+ .string "once"
9311
+.LASF211:
9312
+ .string "UCLASS_SYSRESET"
9313
+.LASF164:
9314
+ .string "UCLASS_FIRMWARE"
9315
+.LASF443:
9316
+ .string "invalidate_dcache_range"
9317
+.LASF174:
9318
+ .string "UCLASS_LPC"
9319
+.LASF170:
9320
+ .string "UCLASS_IDE"
9321
+.LASF290:
9322
+ .string "video_top"
9323
+.LASF431:
9324
+ .string "snprintf"
9325
+.LASF280:
9326
+ .string "of_root_f"
9327
+.LASF139:
9328
+ .string "bootm_headers_t"
9329
+.LASF57:
9330
+ .string "bi_arm_freq"
9331
+.LASF198:
9332
+ .string "UCLASS_REMOTEPROC"
9333
+.LASF109:
9334
+ .string "type"
9335
+.LASF120:
9336
+ .string "fit_hdr_rd"
9337
+.LASF405:
9338
+ .string "fail"
9339
+.LASF262:
9340
+ .string "env_addr"
9341
+.LASF56:
9342
+ .string "bi_sramsize"
9343
+.LASF348:
9344
+ .string "boot_size"
9345
+.LASF407:
9346
+ .string "mpb_task_wait_done"
9347
+.LASF422:
9348
+ .string "spl_hash_android"
9349
+.LASF275:
9350
+ .string "uclass_root"
9351
+.LASF163:
9352
+ .string "UCLASS_GPIO"
9353
+.LASF193:
9354
+ .string "UCLASS_PWM"
9355
+.LASF420:
9356
+ .string "set_gd"
9357
+.LASF42:
9358
+ .string "long double"
9359
+.LASF264:
9360
+ .string "ram_top"
9361
+.LASF296:
9362
+ .string "console_evt"
9363
+.LASF396:
9364
+ .string "mpb_init_x"
9365
+.LASF450:
9366
+ .string "mpb_task_set_state"
9367
+.LASF129:
9368
+ .string "rd_start"
9369
+.LASF194:
9370
+ .string "UCLASS_POWER_DOMAIN"
9371
+.LASF197:
9372
+ .string "UCLASS_REGULATOR"
9373
+.LASF305:
9374
+ .string "save_size"
9375
+.LASF430:
9376
+ .string "msec"
9377
+.LASF155:
9378
+ .string "UCLASS_CLK"
9379
+.LASF403:
9380
+ .string "core_task_run"
9381
+.LASF346:
9382
+ .string "info"
9383
+.LASF72:
9384
+ .string "_datarel_start_ofs"
9385
+.LASF250:
9386
+ .string "pre_serial"
9387
+.LASF102:
9388
+ .string "ih_name"
9389
+.LASF98:
9390
+ .string "ih_os"
9391
+.LASF345:
9392
+ .string "task_data"
9393
+.LASF136:
9394
+ .string "cmdline_end"
9395
+.LASF320:
9396
+ .string "net_rx_packet"
9397
+.LASF241:
9398
+ .string "LOGF_MAX_CATEGORIES"
9399
+.LASF276:
9400
+ .string "fdt_blob"
9401
+.LASF33:
9402
+ .string "size"
9403
+.LASF357:
9404
+ .string "BOOT_MODE_PANIC"
9405
+.LASF10:
9406
+ .string "long long unsigned int"
9407
+.LASF90:
9408
+ .string "image_header"
9409
+.LASF363:
9410
+ .string "CPU_1"
9411
+.LASF19:
9412
+ .string "__be32"
9413
+.LASF402:
9414
+ .string "mpb_quit_load_image"
9415
+.LASF52:
9416
+ .string "bi_flashstart"
9417
+.LASF119:
9418
+ .string "fit_noffset_os"
9419
+.LASF415:
9420
+ .string "mpb_task_set_result"
9421
+.LASF178:
9422
+ .string "UCLASS_MMC"
9423
+.LASF240:
9424
+ .string "UCLASS_INVALID"
9425
+.LASF389:
9426
+ .string "mpb_core"
9427
+.LASF218:
9428
+ .string "UCLASS_USB_HUB"
9429
+.LASF279:
9430
+ .string "of_root"
9431
+.LASF234:
9432
+ .string "UCLASS_EBC"
9433
+.LASF340:
9434
+ .string "spl_load_info"
9435
+.LASF293:
9436
+ .string "new_line"
9437
+.LASF434:
9438
+ .string "memset"
9439
+.LASF41:
9440
+ .string "flash_info"
9441
+.LASF84:
9442
+ .string "version"
9443
+.LASF46:
9444
+ .string "region"
9445
+.LASF88:
9446
+ .string "size_dt_struct"
9447
+.LASF273:
9448
+ .string "dm_root"
9449
+.LASF236:
9450
+ .string "UCLASS_RNG"
9451
+.LASF295:
9452
+ .string "sys_start_tick"
9453
+.LASF180:
9454
+ .string "UCLASS_MTD"
9455
+.LASF352:
9456
+ .string "BOOT_MODE_BOOTLOADER"
9457
+.LASF77:
9458
+ .string "fdt32_t"
9459
+.LASF272:
9460
+ .string "new_gd"
9461
+.LASF182:
9462
+ .string "UCLASS_NORTHBRIDGE"
9463
+.LASF62:
9464
+ .string "bi_enetaddr"
9465
+.LASF39:
9466
+ .string "mtd_info"
9467
+.LASF306:
9468
+ .string "in_addr"
9469
+.LASF353:
9470
+ .string "BOOT_MODE_LOADER"
9471
+.LASF321:
9472
+ .string "net_rx_packet_len"
9473
+.LASF398:
9474
+ .string "init"
9475
+.LASF301:
9476
+ .string "__dtb_dt_begin"
9477
+.LASF199:
9478
+ .string "UCLASS_RESET"
9479
+.LASF122:
9480
+ .string "fit_noffset_rd"
9481
+.LASF153:
9482
+ .string "UCLASS_AHCI"
9483
+.LASF12:
9484
+ .string "phys_size_t"
9485
+.LASF156:
9486
+ .string "UCLASS_CPU"
9487
+.LASF71:
9488
+ .string "FIQ_STACK_START"
9489
+.LASF137:
9490
+ .string "verify"
9491
+.LASF31:
9492
+ .string "name"
9493
+.LASF235:
9494
+ .string "UCLASS_EINK_DISPLAY"
9495
+.LASF185:
9496
+ .string "UCLASS_PANEL_BACKLIGHT"
9497
+.LASF213:
9498
+ .string "UCLASS_TIMER"
9499
+.LASF208:
9500
+ .string "UCLASS_SPI_FLASH"
9501
+.LASF261:
9502
+ .string "have_console"
9503
+.LASF65:
9504
+ .string "bi_busfreq"
9505
+.LASF6:
9506
+ .string "short int"
9507
+.LASF347:
9508
+ .string "boot_addr"
9509
+.LASF191:
9510
+ .string "UCLASS_PINCTRL"
9511
+.LASF201:
9512
+ .string "UCLASS_RAMDISK"
9513
+.LASF148:
9514
+ .string "UCLASS_I2C_EMUL"
9515
+.LASF378:
9516
+ .string "TASK_LOAD_ANDROID"
9517
+.LASF207:
9518
+ .string "UCLASS_SPMI"
9519
+.LASF391:
9520
+ .string "tdata"
9521
+.LASF145:
9522
+ .string "UCLASS_TEST_BUS"
9523
+.LASF435:
9524
+ .string "flush_dcache_all"
9525
+.LASF304:
9526
+ .string "save_addr"
9527
+.LASF444:
9528
+ .string "flush_dcache_range"
9529
+.LASF288:
9530
+ .string "malloc_ptr"
9531
+.LASF427:
9532
+ .string "cpuectlr_disable"
9533
+.LASF401:
9534
+ .string "mpb_task_run"
9535
+.LASF424:
9536
+ .string "spl_load_fit"
9537
+.LASF134:
9538
+ .string "initrd_end"
9539
+.LASF372:
9540
+ .string "EVT_VIDEO_BP"
9541
+.LASF253:
9542
+ .string "baudrate"
9543
+.LASF74:
9544
+ .string "_datarellocal_start_ofs"
9545
+.LASF242:
9546
+ .string "arch_global_data"
9547
+.LASF239:
9548
+ .string "UCLASS_COUNT"
9549
+.LASF362:
9550
+ .string "CPU_0"
9551
+.LASF259:
9552
+ .string "pci_clk"
9553
+.LASF364:
9554
+ .string "CPU_2"
9555
+.LASF365:
9556
+ .string "CPU_3"
9557
+.LASF30:
9558
+ .string "block_drvr"
9559
+.LASF452:
9560
+ .string "memcpy"
9561
+.LASF35:
9562
+ .string "flash_id"
9563
+.LASF231:
9564
+ .string "UCLASS_CRYPTO"
9565
+.LASF297:
9566
+ .string "device_node"
9567
+.LASF267:
9568
+ .string "ram_size"
9569
+.LASF128:
9570
+ .string "fit_noffset_setup"
9571
+.LASF89:
9572
+ .string "working_fdt"
9573
+.LASF282:
9574
+ .string "fdt_blob_kern"
9575
+.LASF313:
9576
+ .string "net_root_path"
9577
+.LASF161:
9578
+ .string "UCLASS_DMA"
9579
+.LASF69:
9580
+ .string "bd_t"
9581
+.LASF237:
9582
+ .string "UCLASS_DMC"
9583
+.LASF307:
9584
+ .string "s_addr"
9585
+.LASF322:
9586
+ .string "net_bcast_ethaddr"
9587
+.LASF392:
9588
+ .string "mpb_gd"
9589
+.LASF67:
9590
+ .string "bi_boot_params"
9591
+.LASF359:
9592
+ .string "BOOT_MODE_DFU"
9593
+.LASF308:
9594
+ .string "net_gateway"
9595
+.LASF50:
9596
+ .string "bi_memstart"
9597
+.LASF222:
9598
+ .string "UCLASS_VIDEO_CONSOLE"
9599
+.LASF48:
9600
+ .string "reserved"
9601
+.LASF373:
9602
+ .string "TASK_NONE"
9603
+.LASF238:
9604
+ .string "UCLASS_PD"
9605
+.LASF441:
9606
+ .string "dcache_disable"
9607
+.LASF68:
9608
+ .string "bi_dram"
9609
+.LASF2:
9610
+ .string "short unsigned int"
9611
+.LASF79:
9612
+ .string "magic"
9613
+.LASF126:
9614
+ .string "fit_hdr_setup"
9615
+.LASF115:
9616
+ .string "legacy_hdr_valid"
9617
+.LASF381:
9618
+ .string "TASK_MAX"
9619
+.LASF44:
9620
+ .string "base"
9621
+.LASF451:
9622
+ .string "spl_dummy"
9623
+.LASF202:
9624
+ .string "UCLASS_RTC"
9625
+.LASF366:
9626
+ .string "EVT_BOOT_DEV"
9627
+.LASF243:
9628
+ .string "timer_rate_hz"
9629
+.LASF34:
9630
+ .string "sector_count"
9631
+.LASF101:
9632
+ .string "ih_comp"
9633
+.LASF400:
9634
+ .string "core_main"
9635
+.LASF131:
9636
+ .string "ft_addr"
9637
+.LASF232:
9638
+ .string "UCLASS_ETH_PHY"
9639
+.LASF393:
9640
+ .string "task_init"
9641
+.LASF4:
9642
+ .string "uchar"
9643
+.LASF132:
9644
+ .string "ft_len"
9645
+.LASF27:
9646
+ .string "next"
9647
+.LASF421:
9648
+ .string "data"
9649
+.LASF181:
9650
+ .string "UCLASS_NOP"
9651
+.LASF380:
9652
+ .string "TASK_RUN_UBOOT"
9653
+.LASF349:
9654
+ .string "_boot_mode"
9655
+.LASF127:
9656
+ .string "fit_uname_setup"
9657
+.LASF28:
9658
+ .string "prev"
9659
+.LASF442:
9660
+ .string "invalidate_dcache_all"
9661
+.LASF186:
9662
+ .string "UCLASS_PCH"
9663
+.LASF187:
9664
+ .string "UCLASS_PCI"
9665
+.LASF309:
9666
+ .string "net_netmask"
9667
+.LASF358:
9668
+ .string "BOOT_MODE_WATCHDOG"
9669
+.LASF70:
9670
+ .string "IRQ_STACK_START"
9671
+.LASF152:
9672
+ .string "UCLASS_ADC"
9673
+.LASF356:
9674
+ .string "BOOT_MODE_BROM_DOWNLOAD"
9675
+.LASF147:
9676
+ .string "UCLASS_SPI_EMUL"
9677
+.LASF425:
9678
+ .string "spl_load_baseparamter"
9679
+.LASF124:
9680
+ .string "fit_uname_fdt"
9681
+ .ident "GCC: (Linaro GCC 6.3-2017.05) 6.3.1 20170404"
9682
+ .section .note.GNU-stack,"",@progbits
u-boot/common/spl/Kconfig
....@@ -144,6 +144,17 @@
144144 The SPL code will be relocated to a high memory if you say no here.
145145 Only ARM64 and PowerPC SPL support relocate now.
146146
147
+config SPL_BOOT_IMAGE
148
+ bool "SPL boot image load support"
149
+ default n
150
+ help
151
+ This enable SPL boot image load support
152
+
153
+config SPL_BOOT_IMAGE_BUF
154
+ hex "SPL boot image memory buffer"
155
+ depends on SPL_BOOT_IMAGE
156
+ default 0x10000000
157
+
147158 config SPL_RELOC_TEXT_BASE
148159 hex "Address the SPL relocate to"
149160 depends on !SPL_SKIP_RELOCATE
....@@ -598,6 +609,12 @@
598609 boot. This enables the drivers in drivers/pch as part of an SPL
599610 build.
600611
612
+config SPL_PCIE_EP_SUPPORT
613
+ bool "Support loading from PCIE EP"
614
+ help
615
+ Enable support for PCIE EP driver in SPL. The RC will download the
616
+ image as a RAM partition for firmware.
617
+
601618 config SPL_POST_MEM_SUPPORT
602619 bool "Support POST drivers"
603620 help
....@@ -900,6 +917,13 @@
900917 help
901918 Enable boot kernel in SPL.
902919
920
+config SPL_KERNEL_BOOT_PREBUILT
921
+ bool "Enable boot kernel in SPL with prebuilt program"
922
+ depends on SPL_KERNEL_BOOT
923
+ default y
924
+ help
925
+ Enable boot kernel in SPL with prebuilt program.
926
+
903927 config SPL_KERNEL_BOOT_SECTOR
904928 hex "Sector address to load kernel in SPL"
905929 depends on SPL_KERNEL_BOOT
u-boot/common/spl/Makefile
....@@ -24,7 +24,7 @@
2424
2525 ifdef CONFIG_SPL_BUILD
2626 obj-$(CONFIG_$(SPL_TPL_)BOOTROM_SUPPORT) += spl_bootrom.o
27
-ifdef CONFIG_SPL_KERNEL_BOOT
27
+ifdef CONFIG_SPL_KERNEL_BOOT_PREBUILT
2828 ifdef CONFIG_ARM64
2929 obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += spl_fit_tb_arm64.o
3030 else
....@@ -57,4 +57,5 @@
5757 obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o
5858 obj-$(CONFIG_$(SPL_TPL_)RAM_SUPPORT) += spl_ram.o
5959 obj-$(CONFIG_$(SPL_TPL_)USB_SDP_SUPPORT) += spl_sdp.o
60
+obj-$(CONFIG_$(SPL_TPL_)BOOT_IMAGE) += spl_boot_image.o
6061 endif
u-boot/common/spl/spl.c
....@@ -17,6 +17,7 @@
1717 #include <version.h>
1818 #include <image.h>
1919 #include <malloc.h>
20
+#include <mp_boot.h>
2021 #include <dm/root.h>
2122 #include <linux/compiler.h>
2223 #include <fdt_support.h>
....@@ -547,6 +548,10 @@
547548
548549 memset(&spl_image, '\0', sizeof(spl_image));
549550
551
+#ifdef CONFIG_MP_BOOT
552
+ mpb_init_x(0);
553
+#endif
554
+
550555 #if CONFIG_IS_ENABLED(ATF)
551556 /*
552557 * Bl32 ep is optional, initial it as an invalid value.
....@@ -574,6 +579,10 @@
574579 }
575580
576581 spl_perform_fixups(&spl_image);
582
+
583
+#ifdef CONFIG_MP_BOOT
584
+ mpb_init_x(2);
585
+#endif
577586
578587 #ifdef CONFIG_CPU_V7M
579588 spl_image.entry_point |= 0x1;
....@@ -710,7 +719,7 @@
710719 /* cleanup before jump to next stage */
711720 void spl_cleanup_before_jump(struct spl_image_info *spl_image)
712721 {
713
- ulong us;
722
+ ulong us, tt_us;
714723
715724 spl_board_prepare_for_jump(spl_image);
716725
....@@ -738,5 +747,6 @@
738747 isb();
739748
740749 us = (get_ticks() - gd->sys_start_tick) / 24UL;
741
- printf("Total: %ld.%ld ms\n\n", us / 1000, us % 1000);
750
+ tt_us = get_ticks() / (COUNTER_FREQUENCY / 1000000);
751
+ printf("Total: %ld.%ld/%ld.%ld ms\n\n", us / 1000, us % 1000, tt_us / 1000, tt_us % 1000);
742752 }
u-boot/common/spl/spl_ab.c
....@@ -319,3 +319,38 @@
319319 out:
320320 return ret;
321321 }
322
+
323
+/*
324
+ * If boot A/B system fail, tries-remaining decrease 1
325
+ * and do reset automatically if still bootable.
326
+ */
327
+int spl_ab_decrease_reset(struct blk_desc *dev_desc)
328
+{
329
+ AvbABData ab_data;
330
+ int ret;
331
+
332
+ ret = spl_ab_data_read(dev_desc, &ab_data, "misc");
333
+ if (ret)
334
+ return ret;
335
+
336
+ /* If current device cannot boot, return and try other devices. */
337
+ if (!spl_slot_is_bootable(&ab_data.slots[0]) &&
338
+ !spl_slot_is_bootable(&ab_data.slots[1])) {
339
+ printf("A/B: no bootable slot\n");
340
+ return -ENODEV;
341
+ }
342
+
343
+ /* If current device still can boot, decrease and do reset. */
344
+ ret = spl_ab_decrease_tries(dev_desc);
345
+ if (ret)
346
+ return ret;
347
+
348
+ printf("A/B: slot boot fail, do reset\n");
349
+ do_reset(NULL, 0, 0, NULL);
350
+
351
+ /*
352
+ * Only do_reset() fail will arrive here, return a
353
+ * negative number, then enter maskrom in the caller.
354
+ */
355
+ return -EINVAL;
356
+}
u-boot/common/spl/spl_boot_image.c
....@@ -0,0 +1,305 @@
1
+/*
2
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+
7
+#include <common.h>
8
+#include <android_image.h>
9
+#include <crypto.h>
10
+#include <image.h>
11
+#include <mp_boot.h>
12
+#include <part.h>
13
+#include <spl.h>
14
+#include <asm/io.h>
15
+
16
+#define BLK_CNT(_num_bytes, _block_size) \
17
+ ((_num_bytes + _block_size - 1) / _block_size)
18
+
19
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
20
+static int android_check_header(const struct andr_img_hdr *hdr)
21
+{
22
+ return memcmp(ANDR_BOOT_MAGIC, hdr->magic, ANDR_BOOT_MAGIC_SIZE);
23
+}
24
+
25
+static void print_hash(const char *label, u8 *hash, int len)
26
+{
27
+ int i;
28
+
29
+ printf("%s:\n 0x", label ? : "Hash");
30
+ for (i = 0; i < len; i++)
31
+ printf("%02x", hash[i]);
32
+ printf("\n");
33
+}
34
+
35
+#if 0
36
+static void spl_android_print_contents(const struct andr_img_hdr *hdr)
37
+{
38
+ const char * const p = IMAGE_INDENT_STRING;
39
+ /* os_version = ver << 11 | lvl */
40
+ u32 os_ver = hdr->os_version >> 11;
41
+ u32 os_lvl = hdr->os_version & ((1U << 11) - 1);
42
+ u32 header_version = hdr->header_version;
43
+
44
+ printf("%skernel size: %x\n", p, hdr->kernel_size);
45
+ printf("%skernel address: %x\n", p, hdr->kernel_addr);
46
+ printf("%sramdisk size: %x\n", p, hdr->ramdisk_size);
47
+ printf("%sramdisk address: %x\n", p, hdr->ramdisk_addr);
48
+ printf("%ssecond size: %x\n", p, hdr->second_size);
49
+ printf("%ssecond address: %x\n", p, hdr->second_addr);
50
+ printf("%stags address: %x\n", p, hdr->tags_addr);
51
+ printf("%spage size: %x\n", p, hdr->page_size);
52
+ printf("%sheader_version: %x\n", p, header_version);
53
+ /* ver = A << 14 | B << 7 | C (7 bits for each of A, B, C)
54
+ * lvl = ((Y - 2000) & 127) << 4 | M (7 bits for Y, 4 bits for M) */
55
+ printf("%sos_version: %x (ver: %u.%u.%u, level: %u.%u)\n",
56
+ p, hdr->os_version,
57
+ (os_ver >> 7) & 0x7F, (os_ver >> 14) & 0x7F, os_ver & 0x7F,
58
+ (os_lvl >> 4) + 2000, os_lvl & 0x0F);
59
+ printf("%sname: %s\n", p, hdr->name);
60
+ printf("%scmdline: %s\n", p, hdr->cmdline);
61
+
62
+ if (header_version == 1 || header_version == 2) {
63
+ printf("%srecovery dtbo size: %x\n", p, hdr->recovery_dtbo_size);
64
+ printf("%srecovery dtbo offset: %llx\n", p, hdr->recovery_dtbo_offset);
65
+ printf("%sheader size: %x\n", p, hdr->header_size);
66
+ }
67
+
68
+ if (header_version == 2 || header_version == 3) {
69
+ printf("%sdtb size: %x\n", p, hdr->dtb_size);
70
+ printf("%sdtb addr: %llx\n", p, hdr->dtb_addr);
71
+ }
72
+
73
+ if (header_version >= 3) {
74
+ printf("%scmdline: %s\n", p, hdr->total_cmdline);
75
+ printf("%svendor ramdisk size: %x\n", p, hdr->vendor_ramdisk_size);
76
+ printf("%svendor page size: %x\n", p, hdr->vendor_page_size);
77
+ printf("%svendor header version: %d\n", p, hdr->vendor_header_version);
78
+ printf("%svendor header size: %x\n", p, hdr->vendor_header_size);
79
+ }
80
+
81
+ if (header_version >= 4) {
82
+ printf("%svendor ramdisk table size: %x\n",
83
+ p, hdr->vendor_ramdisk_table_size);
84
+ printf("%svendor ramdisk table entry num: %x\n",
85
+ p, hdr->vendor_ramdisk_table_entry_num);
86
+ printf("%svendor ramdisk table entry size: %x\n",
87
+ p, hdr->vendor_ramdisk_table_entry_size);
88
+ printf("%svendor bootconfig size: %d\n",
89
+ p, hdr->vendor_bootconfig_size);
90
+ }
91
+}
92
+#endif
93
+
94
+static ulong android_size(struct andr_img_hdr *hdr)
95
+{
96
+ ulong len;
97
+
98
+ len = hdr->page_size +
99
+ ALIGN(hdr->kernel_size, hdr->page_size) +
100
+ ALIGN(hdr->ramdisk_size, hdr->page_size) +
101
+ ALIGN(hdr->second_size, hdr->page_size);
102
+ if (hdr->header_version > 0)
103
+ len += ALIGN(hdr->recovery_dtbo_size, hdr->page_size);
104
+ if (hdr->header_version > 1)
105
+ len += ALIGN(hdr->dtb_size, hdr->page_size);
106
+#if 0
107
+ spl_android_print_contents(hdr);
108
+#endif
109
+
110
+ return len;
111
+}
112
+
113
+int spl_load_android(struct task_data *data)
114
+{
115
+ struct spl_load_info *info = &data->info;
116
+ void *buf = (void *)CONFIG_SPL_BOOT_IMAGE_BUF;
117
+ disk_partition_t part;
118
+ ulong blkcnt;
119
+
120
+ debug("== Android: load start\n");
121
+
122
+ if (part_get_info_by_name(info->dev, "boot", &part) < 0) {
123
+ printf("No boot partition\n");
124
+ return -ENOENT;
125
+ }
126
+
127
+ blkcnt = BLK_CNT(sizeof(struct andr_img_hdr), info->bl_len);
128
+ if (info->read(info, part.start, blkcnt, buf) != blkcnt)
129
+ return -EIO;
130
+
131
+ if (android_check_header(buf))
132
+ return -EINVAL;
133
+
134
+ blkcnt = BLK_CNT(android_size(buf), info->bl_len);
135
+ if (info->read(info, part.start, blkcnt, buf) != blkcnt)
136
+ return -EIO;
137
+
138
+ data->boot_addr = (void *)CONFIG_SPL_BOOT_IMAGE_BUF;
139
+ data->boot_size = blkcnt * info->bl_len;
140
+
141
+ flush_dcache_range((ulong)data, (ulong)data + sizeof(*data));
142
+ flush_dcache_range((ulong)buf, (ulong)buf + blkcnt);
143
+
144
+ debug("== Android: load 0x%08lx size OK\n", blkcnt * info->bl_len);
145
+
146
+ return 0;
147
+}
148
+
149
+#ifdef CONFIG_ARMV8_CE_SHA1
150
+int spl_hash_android(struct task_data *data)
151
+{
152
+ struct andr_img_hdr *hdr = (void *)CONFIG_SPL_BOOT_IMAGE_BUF;
153
+ sha1_context ctx;
154
+ uchar hash[32];
155
+ void *buf;
156
+
157
+ printf("== Android: hash start\n");
158
+
159
+ if (hdr->header_version >= 3)
160
+ return -EINVAL;
161
+
162
+ sha1_starts(&ctx);
163
+
164
+ buf = (void *)hdr + hdr->page_size;
165
+ sha1_update(&ctx, (const uchar *)buf, hdr->kernel_size);
166
+ sha1_update(&ctx, (const uchar *)&hdr->kernel_size, sizeof(hdr->kernel_size));
167
+
168
+ buf += ALIGN(hdr->kernel_size, hdr->page_size);
169
+ sha1_update(&ctx, (const uchar *)buf, hdr->ramdisk_size);
170
+ sha1_update(&ctx, (const uchar *)&hdr->ramdisk_size, sizeof(hdr->ramdisk_size));
171
+
172
+ buf += ALIGN(hdr->ramdisk_size, hdr->page_size);
173
+ sha1_update(&ctx, (const uchar *)buf, hdr->second_size);
174
+ sha1_update(&ctx, (const uchar *)&hdr->second_size, sizeof(hdr->second_size));
175
+
176
+ if (hdr->header_version > 0) {
177
+ buf += ALIGN(hdr->second_size, hdr->page_size);
178
+ sha1_update(&ctx, (const uchar *)buf, hdr->recovery_dtbo_size);
179
+ sha1_update(&ctx, (const uchar *)&hdr->recovery_dtbo_size, sizeof(hdr->recovery_dtbo_size));
180
+ }
181
+ if (hdr->header_version > 1) {
182
+ buf += ALIGN(hdr->recovery_dtbo_size, hdr->page_size);
183
+ sha1_update(&ctx, (const uchar *)buf, hdr->dtb_size);
184
+ sha1_update(&ctx, (const uchar *)&hdr->dtb_size, sizeof(hdr->dtb_size));
185
+ }
186
+
187
+ sha1_finish(&ctx, hash);
188
+
189
+ if (memcmp(hash, hdr->id, 20)) {
190
+ print_hash("Hash from header", (u8 *)hdr->id, 20);
191
+ print_hash("Hash real", (u8 *)hash, 20);
192
+ return -EBADFD;
193
+ }
194
+
195
+ printf("== Android: hash OK, 0x%08lx\n", (ulong)data->boot_addr);
196
+
197
+ return 0;
198
+}
199
+
200
+#else
201
+int spl_hash_android(struct task_data *data)
202
+{
203
+ struct andr_img_hdr *hdr = (void *)CONFIG_SPL_BOOT_IMAGE_BUF;
204
+ struct udevice *dev;
205
+ sha_context ctx;
206
+ uchar hash[32];
207
+ void *buf;
208
+
209
+ debug("== Android: hash start\n");
210
+
211
+ if (hdr->header_version >= 3)
212
+ return -EINVAL;
213
+
214
+ ctx.algo = CRYPTO_SHA1;
215
+ dev = crypto_get_device(ctx.algo);
216
+ if (!dev) {
217
+ printf("No crypto device for sha1\n");
218
+ return -ENODEV;
219
+ }
220
+
221
+ ctx.length = hdr->kernel_size + sizeof(hdr->kernel_size) +
222
+ hdr->ramdisk_size + sizeof(hdr->ramdisk_size) +
223
+ hdr->second_size + sizeof(hdr->second_size);
224
+ if (hdr->header_version > 0)
225
+ ctx.length += hdr->recovery_dtbo_size + sizeof(hdr->recovery_dtbo_size);
226
+ if (hdr->header_version > 1)
227
+ ctx.length += hdr->dtb_size + sizeof(hdr->dtb_size);
228
+
229
+ crypto_sha_init(dev, &ctx);
230
+
231
+ buf = (void *)hdr + hdr->page_size;
232
+ crypto_sha_update(dev, buf, hdr->kernel_size);
233
+ crypto_sha_update(dev, &hdr->kernel_size, sizeof(hdr->kernel_size));
234
+
235
+ buf += ALIGN(hdr->kernel_size, hdr->page_size);
236
+ crypto_sha_update(dev, buf, hdr->ramdisk_size);
237
+ crypto_sha_update(dev, &hdr->ramdisk_size, sizeof(hdr->ramdisk_size));
238
+
239
+ buf += ALIGN(hdr->ramdisk_size, hdr->page_size);
240
+ crypto_sha_update(dev, buf, hdr->second_size);
241
+ crypto_sha_update(dev, &hdr->second_size, sizeof(hdr->second_size));
242
+
243
+ if (hdr->header_version > 0) {
244
+ buf += ALIGN(hdr->second_size, hdr->page_size);
245
+ crypto_sha_update(dev, buf, hdr->recovery_dtbo_size);
246
+ crypto_sha_update(dev, &hdr->recovery_dtbo_size, sizeof(hdr->recovery_dtbo_size));
247
+ }
248
+ if (hdr->header_version > 1) {
249
+ buf += ALIGN(hdr->recovery_dtbo_size, hdr->page_size);
250
+ crypto_sha_update(dev, buf, hdr->dtb_size);
251
+ crypto_sha_update(dev, &hdr->dtb_size, sizeof(hdr->dtb_size));
252
+ }
253
+
254
+ crypto_sha_final(dev, &ctx, hash);
255
+
256
+ if (memcmp(hash, hdr->id, 20)) {
257
+ print_hash("Hash from header", (u8 *)hdr->id, 20);
258
+ print_hash("Hash real", (u8 *)hash, 20);
259
+ return -EBADFD;
260
+ }
261
+
262
+ debug("== Android: hash OK, 0x%08lx\n", (ulong)data->boot_addr);
263
+
264
+ return 0;
265
+}
266
+
267
+#endif
268
+#endif
269
+
270
+#ifdef CONFIG_ROCKCHIP_FIT_IMAGE
271
+int spl_load_fit(struct task_data *data)
272
+{
273
+ struct spl_load_info *info = &data->info;
274
+ void *buf = (void *)CONFIG_SPL_BOOT_IMAGE_BUF;
275
+ disk_partition_t part;
276
+ ulong blkcnt;
277
+ int size;
278
+
279
+ debug("== FIT: load start\n");
280
+
281
+ if (part_get_info_by_name(info->dev, "boot", &part) < 0) {
282
+ printf("No boot partition\n");
283
+ return -ENOENT;
284
+ }
285
+
286
+ blkcnt = BLK_CNT(sizeof(struct fdt_header), info->bl_len);
287
+ if (info->read(info, part.start, blkcnt, buf) != blkcnt)
288
+ return -EIO;
289
+
290
+ if (fdt_check_header(buf))
291
+ return -EINVAL;
292
+
293
+ size = fit_get_totalsize(buf, &size);
294
+ blkcnt = BLK_CNT(size, info->bl_len);
295
+ if (info->read(info, part.start, blkcnt, buf) != blkcnt)
296
+ return -EIO;
297
+
298
+ flush_dcache_range((ulong)buf, (ulong)buf + blkcnt);
299
+
300
+ debug("== FIT: load 0x%08x size OK\n", size);
301
+
302
+ return 0;
303
+}
304
+#endif
305
+
u-boot/common/spl/spl_fit.c
....@@ -12,6 +12,7 @@
1212 #include <image.h>
1313 #include <malloc.h>
1414 #include <mtd_blk.h>
15
+#include <mp_boot.h>
1516 #include <spl.h>
1617 #include <spl_ab.h>
1718 #include <linux/libfdt.h>
....@@ -481,6 +482,8 @@
481482 #else
482483 sector = CONFIG_SPL_KERNEL_BOOT_SECTOR;
483484 #endif
485
+ printf("Trying kernel at 0x%x sector from '%s' part\n", sector, part_name);
486
+
484487 if (info->read(info, sector, 1, &fit_header) != 1) {
485488 debug("%s: Failed to read header\n", __func__);
486489 return -EIO;
....@@ -793,6 +796,10 @@
793796 int ret = -EINVAL;
794797 int i;
795798
799
+#ifdef CONFIG_MP_BOOT
800
+ mpb_init_1(*info);
801
+#endif
802
+
796803 printf("Trying fit image at 0x%lx sector\n", sector_offs);
797804 for (i = 0; i < CONFIG_SPL_FIT_IMAGE_MULTIPLE; i++) {
798805 if (i > 0) {
....@@ -820,15 +827,18 @@
820827 }
821828 }
822829 #ifdef CONFIG_SPL_AB
830
+ /* If boot fail in spl, spl must decrease 1 and do_reset. */
831
+ if (ret)
832
+ return spl_ab_decrease_reset(info->dev);
823833 /*
824
- * If boot fail in spl, spl must decrease 1. If boot
825
- * successfully, it is no need to do that and U-boot will
826
- * always to decrease 1. If in thunderboot process,
827
- * always need to decrease 1.
834
+ * If boot successfully, it is no need to do decrease
835
+ * and U-boot will always decrease 1.
836
+ * If in thunderboot process, always need to decrease 1.
828837 */
829
- if (IS_ENABLED(CONFIG_SPL_KERNEL_BOOT) || ret)
838
+ if (spl_image->next_stage == SPL_NEXT_STAGE_KERNEL)
830839 spl_ab_decrease_tries(info->dev);
831840 #endif
841
+
832842 return ret;
833843 }
834844
u-boot/common/spl_mp_boot_rk3528.S
....@@ -0,0 +1,9214 @@
1
+ .arch armv8-a+nosimd
2
+ .file "mp_boot.c"
3
+ .text
4
+.Ltext0:
5
+ .cfi_sections .debug_frame
6
+ .section .text.mpb_task_set_state,"ax",@progbits
7
+ .align 2
8
+ .type mpb_task_set_state, %function
9
+mpb_task_set_state:
10
+.LFB227:
11
+ .file 1 "common/mp_boot.c"
12
+ .loc 1 227 0
13
+ .cfi_startproc
14
+.LVL0:
15
+.LBB30:
16
+.LBB31:
17
+ .loc 1 146 0
18
+ mov x4, 136314880
19
+ mov w3, 1
20
+ lsl w3, w3, w1
21
+ ldr w5, [x4]
22
+.LBE31:
23
+.LBE30:
24
+ .loc 1 232 0
25
+ tst w3, w5
26
+ beq .L11
27
+.LBB32:
28
+.LBB33:
29
+ .loc 1 199 0
30
+ uxtw x5, w0
31
+ mov x3, 328
32
+ umull x0, w0, w3
33
+.LVL1:
34
+ madd x4, x5, x3, x4
35
+ mov w3, 0
36
+ ldrb w6, [x4, 328]
37
+ mov x4, 20
38
+ movk x4, 0x820, lsl 16
39
+ add x4, x0, x4
40
+.L3:
41
+.LVL2:
42
+ cmp w3, w6
43
+ blt .L5
44
+.LVL3:
45
+.L11:
46
+.LBE33:
47
+.LBE32:
48
+ .loc 1 252 0
49
+ mov w0, 0
50
+ ret
51
+.LVL4:
52
+.L5:
53
+.LBB35:
54
+.LBB34:
55
+ .loc 1 200 0
56
+ ldr w7, [x4], 40
57
+ cmp w1, w7
58
+ beq .L4
59
+ .loc 1 199 0
60
+ add w3, w3, 1
61
+.LVL5:
62
+ b .L3
63
+.L4:
64
+.LVL6:
65
+.LBE34:
66
+.LBE35:
67
+ .loc 1 239 0
68
+ mov x8, 328
69
+ sxtw x4, w3
70
+ mov x7, 40
71
+ .loc 1 240 0
72
+ add x0, x0, 16
73
+ .loc 1 239 0
74
+ mul x5, x5, x8
75
+ .loc 1 227 0
76
+ stp x29, x30, [sp, -16]!
77
+ .cfi_def_cfa_offset 16
78
+ .cfi_offset 29, -16
79
+ .cfi_offset 30, -8
80
+ .loc 1 239 0
81
+ nop // between mem op and mult-accumulate
82
+ madd x4, x4, x7, x5
83
+ mov x6, 136314880
84
+ .loc 1 240 0
85
+ smaddl x3, w3, w7, x0
86
+ .loc 1 227 0
87
+ add x29, sp, 0
88
+ .cfi_def_cfa_register 29
89
+ .loc 1 239 0
90
+ add x4, x6, x4
91
+ .loc 1 227 0
92
+ .loc 1 239 0
93
+ add w1, w1, w2
94
+.LVL7:
95
+ .loc 1 240 0
96
+ add x0, x3, x6
97
+ .loc 1 239 0
98
+ str w1, [x4, 16]
99
+ .loc 1 241 0
100
+ add x1, x0, 4
101
+ bl flush_dcache_range
102
+.LVL8:
103
+ .loc 1 252 0
104
+ mov w0, 0
105
+ ldp x29, x30, [sp], 16
106
+ .cfi_restore 30
107
+ .cfi_restore 29
108
+ .cfi_def_cfa 31, 0
109
+ ret
110
+ .cfi_endproc
111
+.LFE227:
112
+ .size mpb_task_set_state, .-mpb_task_set_state
113
+ .section .text.spl_init_display,"ax",@progbits
114
+ .align 2
115
+ .weak spl_init_display
116
+ .type spl_init_display, %function
117
+spl_init_display:
118
+.LFB252:
119
+ .cfi_startproc
120
+ mov w0, 0
121
+ ret
122
+ .cfi_endproc
123
+.LFE252:
124
+ .size spl_init_display, .-spl_init_display
125
+ .section .text.spl_load_baseparamter,"ax",@progbits
126
+ .align 2
127
+ .weak spl_load_baseparamter
128
+ .type spl_load_baseparamter, %function
129
+spl_load_baseparamter:
130
+.LFB250:
131
+ .cfi_startproc
132
+ mov w0, 0
133
+ ret
134
+ .cfi_endproc
135
+.LFE250:
136
+ .size spl_load_baseparamter, .-spl_load_baseparamter
137
+ .section .text.spl_load_fit,"ax",@progbits
138
+ .align 2
139
+ .weak spl_load_fit
140
+ .type spl_load_fit, %function
141
+spl_load_fit:
142
+.LFB248:
143
+ .cfi_startproc
144
+ mov w0, 0
145
+ ret
146
+ .cfi_endproc
147
+.LFE248:
148
+ .size spl_load_fit, .-spl_load_fit
149
+ .section .text.spl_load_android,"ax",@progbits
150
+ .align 2
151
+ .weak spl_load_android
152
+ .type spl_load_android, %function
153
+spl_load_android:
154
+.LFB246:
155
+ .cfi_startproc
156
+ mov w0, 0
157
+ ret
158
+ .cfi_endproc
159
+.LFE246:
160
+ .size spl_load_android, .-spl_load_android
161
+ .section .text.spl_hash_android,"ax",@progbits
162
+ .align 2
163
+ .weak spl_hash_android
164
+ .type spl_hash_android, %function
165
+spl_hash_android:
166
+.LFB244:
167
+ .cfi_startproc
168
+ mov w0, 0
169
+ ret
170
+ .cfi_endproc
171
+.LFE244:
172
+ .size spl_hash_android, .-spl_hash_android
173
+ .section .text.spl_dummy,"ax",@progbits
174
+ .align 2
175
+ .weak spl_dummy
176
+ .type spl_dummy, %function
177
+spl_dummy:
178
+.LFB220:
179
+ .loc 1 52 0
180
+ .cfi_startproc
181
+.LVL9:
182
+ .loc 1 52 0
183
+ mov w0, 0
184
+.LVL10:
185
+ ret
186
+ .cfi_endproc
187
+.LFE220:
188
+ .size spl_dummy, .-spl_dummy
189
+ .section .text.mpb_task_is_done,"ax",@progbits
190
+ .align 2
191
+ .global mpb_task_is_done
192
+ .type mpb_task_is_done, %function
193
+mpb_task_is_done:
194
+.LFB228:
195
+ .loc 1 261 0
196
+ .cfi_startproc
197
+.LVL11:
198
+.LBB36:
199
+.LBB37:
200
+ .loc 1 146 0
201
+ mov x2, 136314880
202
+ mov w1, 1
203
+ lsl w1, w1, w0
204
+ ldr w2, [x2]
205
+.LBE37:
206
+.LBE36:
207
+ .loc 1 265 0
208
+ tst w1, w2
209
+ beq .L35
210
+ .loc 1 261 0
211
+ stp x29, x30, [sp, -96]!
212
+ .cfi_def_cfa_offset 96
213
+ .cfi_offset 29, -96
214
+ .cfi_offset 30, -88
215
+ add x29, sp, 0
216
+ .cfi_def_cfa_register 29
217
+ stp x19, x20, [sp, 16]
218
+ .cfi_offset 19, -80
219
+ .cfi_offset 20, -72
220
+ mov w19, w0
221
+ stp x23, x24, [sp, 48]
222
+ .cfi_offset 23, -48
223
+ .cfi_offset 24, -40
224
+ .loc 1 275 0
225
+ mov w24, -559087616
226
+ .loc 1 261 0
227
+ str x27, [sp, 80]
228
+ .loc 1 275 0
229
+ add w24, w0, w24
230
+ .cfi_offset 27, -16
231
+ .loc 1 277 0
232
+ sub w27, w0, #65536
233
+ .loc 1 261 0
234
+ stp x21, x22, [sp, 32]
235
+ stp x25, x26, [sp, 64]
236
+ .cfi_offset 21, -64
237
+ .cfi_offset 22, -56
238
+ .cfi_offset 25, -32
239
+ .cfi_offset 26, -24
240
+ mov x21, 0
241
+.LVL12:
242
+.L27:
243
+ mov x22, 16
244
+ mov x20, 20
245
+ .loc 1 269 0
246
+ mov x26, 328
247
+ movk x22, 0x820, lsl 16
248
+ movk x20, 0x820, lsl 16
249
+ add x22, x21, x22
250
+ add x20, x21, x20
251
+ .loc 1 261 0
252
+ mov w23, 0
253
+ .loc 1 269 0
254
+ movk x26, 0x820, lsl 16
255
+ .loc 1 279 0
256
+ mov w25, 1431655765
257
+ b .L23
258
+.LVL13:
259
+.L26:
260
+ .loc 1 270 0
261
+ ldr w0, [x20]
262
+ cmp w19, w0
263
+ beq .L22
264
+.L25:
265
+ .loc 1 269 0
266
+ add w23, w23, 1
267
+.LVL14:
268
+ add x22, x22, 40
269
+ add x20, x20, 40
270
+.LVL15:
271
+.L23:
272
+ .loc 1 269 0 is_stmt 0 discriminator 1
273
+ ldrb w0, [x21, x26]
274
+ cmp w23, w0
275
+ blt .L26
276
+.LVL16:
277
+ add x21, x21, 328
278
+ .loc 1 268 0 is_stmt 1 discriminator 2
279
+ cmp x21, 1312
280
+ bne .L27
281
+ .loc 1 286 0
282
+ mov w0, 0
283
+.L19:
284
+ .loc 1 287 0
285
+ ldp x19, x20, [sp, 16]
286
+.LVL17:
287
+ ldp x21, x22, [sp, 32]
288
+ ldp x23, x24, [sp, 48]
289
+.LVL18:
290
+ ldp x25, x26, [sp, 64]
291
+ ldr x27, [sp, 80]
292
+.LVL19:
293
+ ldp x29, x30, [sp], 96
294
+ .cfi_remember_state
295
+ .cfi_restore 30
296
+ .cfi_restore 29
297
+ .cfi_restore 27
298
+ .cfi_restore 25
299
+ .cfi_restore 26
300
+ .cfi_restore 23
301
+ .cfi_restore 24
302
+ .cfi_restore 21
303
+ .cfi_restore 22
304
+ .cfi_restore 19
305
+ .cfi_restore 20
306
+ .cfi_def_cfa 31, 0
307
+ ret
308
+.LVL20:
309
+.L22:
310
+ .cfi_restore_state
311
+ .loc 1 272 0
312
+ mov x0, x22
313
+ mov x1, x20
314
+ bl invalidate_dcache_range
315
+.LVL21:
316
+ .loc 1 275 0
317
+ ldr w0, [x22]
318
+ cmp w0, w24
319
+ beq .L28
320
+ .loc 1 277 0
321
+ cmp w0, w27
322
+ beq .L20
323
+ .loc 1 279 0
324
+ add w1, w19, w25
325
+ cmp w0, w1
326
+ bne .L25
327
+ .loc 1 280 0
328
+ mov w0, -2
329
+ b .L19
330
+.L20:
331
+ .loc 1 266 0
332
+ mov w0, -1
333
+ b .L19
334
+.L28:
335
+ .loc 1 276 0
336
+ mov w0, 1
337
+ b .L19
338
+.LVL22:
339
+.L35:
340
+ .cfi_def_cfa 31, 0
341
+ .cfi_restore 19
342
+ .cfi_restore 20
343
+ .cfi_restore 21
344
+ .cfi_restore 22
345
+ .cfi_restore 23
346
+ .cfi_restore 24
347
+ .cfi_restore 25
348
+ .cfi_restore 26
349
+ .cfi_restore 27
350
+ .cfi_restore 29
351
+ .cfi_restore 30
352
+ .loc 1 266 0
353
+ mov w0, -1
354
+.LVL23:
355
+ .loc 1 287 0
356
+ ret
357
+ .cfi_endproc
358
+.LFE228:
359
+ .size mpb_task_is_done, .-mpb_task_is_done
360
+ .section .text.mpb_task_dump,"ax",@progbits
361
+ .align 2
362
+ .global mpb_task_dump
363
+ .type mpb_task_dump, %function
364
+mpb_task_dump:
365
+.LFB229:
366
+ .loc 1 290 0
367
+ .cfi_startproc
368
+ stp x29, x30, [sp, -80]!
369
+ .cfi_def_cfa_offset 80
370
+ .cfi_offset 29, -80
371
+ .cfi_offset 30, -72
372
+ .loc 1 294 0
373
+ mov x0, 136314880
374
+ .loc 1 290 0
375
+ add x29, sp, 0
376
+ .cfi_def_cfa_register 29
377
+ .loc 1 294 0
378
+ ldr x1, [x0, 1360]
379
+ ldr x2, [x0, 1368]
380
+ adrp x0, .LC1
381
+ .loc 1 290 0
382
+ stp x19, x20, [sp, 16]
383
+ .cfi_offset 19, -64
384
+ .cfi_offset 20, -56
385
+ .loc 1 294 0
386
+ mov x20, 20
387
+ .loc 1 290 0
388
+ stp x23, x24, [sp, 48]
389
+ .loc 1 294 0
390
+ movk x20, 0x820, lsl 16
391
+ .loc 1 290 0
392
+ stp x21, x22, [sp, 32]
393
+ .cfi_offset 23, -32
394
+ .cfi_offset 24, -24
395
+ .cfi_offset 21, -48
396
+ .cfi_offset 22, -40
397
+ .loc 1 299 0
398
+ adrp x23, .LANCHOR0
399
+ adrp x24, .LC2
400
+ .loc 1 296 0
401
+ mov w21, 0
402
+ .loc 1 299 0
403
+ add x23, x23, :lo12:.LANCHOR0
404
+ add x24, x24, :lo12:.LC2
405
+ .loc 1 294 0
406
+ add x0, x0, :lo12:.LC1
407
+ .loc 1 290 0
408
+ str x25, [sp, 64]
409
+ .cfi_offset 25, -16
410
+ .loc 1 294 0
411
+ bl printf
412
+.LVL24:
413
+.L39:
414
+ .loc 1 290 0
415
+ mov x19, x20
416
+ mov w22, 0
417
+ .loc 1 300 0
418
+ adrp x25, .LC3
419
+ b .L42
420
+.LVL25:
421
+.L40:
422
+ .loc 1 299 0 discriminator 3
423
+ ldr w2, [x19]
424
+ mov w1, w21
425
+ mov x0, x24
426
+ .loc 1 297 0 discriminator 3
427
+ add w22, w22, 1
428
+.LVL26:
429
+ add x19, x19, 40
430
+ .loc 1 299 0 discriminator 3
431
+ ldr x3, [x23, w2, uxtw 3]
432
+ bl printf
433
+.LVL27:
434
+ .loc 1 300 0 discriminator 3
435
+ ldr w1, [x19, -40]
436
+ add x0, x25, :lo12:.LC3
437
+ bl printf
438
+.LVL28:
439
+ .loc 1 301 0 discriminator 3
440
+ ldr x1, [x19, -52]
441
+ adrp x0, .LC4
442
+ add x0, x0, :lo12:.LC4
443
+ bl printf
444
+.LVL29:
445
+ .loc 1 302 0 discriminator 3
446
+ ldr w1, [x19, -44]
447
+ adrp x0, .LC5
448
+ add x0, x0, :lo12:.LC5
449
+ bl printf
450
+.LVL30:
451
+ .loc 1 303 0 discriminator 3
452
+ ldr w1, [x19, -28]
453
+ adrp x0, .LC6
454
+ add x0, x0, :lo12:.LC6
455
+ bl printf
456
+.LVL31:
457
+ .loc 1 304 0 discriminator 3
458
+ ldr x1, [x19, -20]
459
+ adrp x0, .LC7
460
+ add x0, x0, :lo12:.LC7
461
+ bl printf
462
+.LVL32:
463
+ .loc 1 305 0 discriminator 3
464
+ ldr w1, [x19, -36]
465
+ adrp x0, .LC8
466
+ add x0, x0, :lo12:.LC8
467
+ bl printf
468
+.LVL33:
469
+ .loc 1 306 0 discriminator 3
470
+ ldr w1, [x19, -32]
471
+ adrp x0, .LC9
472
+ add x0, x0, :lo12:.LC9
473
+ bl printf
474
+.LVL34:
475
+.L42:
476
+ .loc 1 297 0 discriminator 1
477
+ ldrb w0, [x20, 308]
478
+ cmp w22, w0
479
+ blt .L40
480
+ .loc 1 296 0 discriminator 2
481
+ add w21, w21, 1
482
+.LVL35:
483
+ add x20, x20, 328
484
+ cmp w21, 4
485
+ bne .L39
486
+ .loc 1 310 0
487
+ ldp x19, x20, [sp, 16]
488
+ ldp x21, x22, [sp, 32]
489
+.LVL36:
490
+ ldp x23, x24, [sp, 48]
491
+ ldr x25, [sp, 64]
492
+ ldp x29, x30, [sp], 80
493
+ .cfi_restore 30
494
+ .cfi_restore 29
495
+ .cfi_restore 25
496
+ .cfi_restore 23
497
+ .cfi_restore 24
498
+ .cfi_restore 21
499
+ .cfi_restore 22
500
+ .cfi_restore 19
501
+ .cfi_restore 20
502
+ .cfi_def_cfa 31, 0
503
+ ret
504
+ .cfi_endproc
505
+.LFE229:
506
+ .size mpb_task_dump, .-mpb_task_dump
507
+ .section .text.core_task_run.part.1,"ax",@progbits
508
+ .align 2
509
+ .type core_task_run.part.1, %function
510
+core_task_run.part.1:
511
+.LFB242:
512
+ .loc 1 370 0
513
+ .cfi_startproc
514
+.LVL37:
515
+ stp x29, x30, [sp, -80]!
516
+ .cfi_def_cfa_offset 80
517
+ .cfi_offset 29, -80
518
+ .cfi_offset 30, -72
519
+ add x29, sp, 0
520
+ .cfi_def_cfa_register 29
521
+ stp x19, x20, [sp, 16]
522
+ .cfi_offset 19, -64
523
+ .cfi_offset 20, -56
524
+ mov w19, w0
525
+ stp x21, x22, [sp, 32]
526
+ mov w20, w2
527
+.LVL38:
528
+ stp x23, x24, [sp, 48]
529
+ .cfi_offset 21, -48
530
+ .cfi_offset 22, -40
531
+ .cfi_offset 23, -32
532
+ .cfi_offset 24, -24
533
+ and x22, x1, 255
534
+ stp x25, x26, [sp, 64]
535
+ .cfi_offset 25, -16
536
+ .cfi_offset 26, -8
537
+.LBB48:
538
+.LBB49:
539
+ .loc 1 319 0
540
+ cbz w3, .L45
541
+ mov w25, w3
542
+ mov w23, 0
543
+ mov w21, 0
544
+ .loc 1 324 0
545
+ mov w26, 1
546
+.LVL39:
547
+.L50:
548
+ lsl w0, w26, w21
549
+ tst w0, w25
550
+ beq .L46
551
+.L47:
552
+ .loc 1 319 0
553
+ mov w24, 20000
554
+.L48:
555
+.LVL40:
556
+ .loc 1 329 0
557
+ mov w0, w21
558
+ bl mpb_task_is_done
559
+.LVL41:
560
+ cbz w0, .L49
561
+ .loc 1 344 0
562
+ mov w0, w21
563
+ bl mpb_task_is_done
564
+.LVL42:
565
+ .loc 1 345 0
566
+ cmp w0, 0
567
+ cinc w23, w23, lt
568
+.LVL43:
569
+.L46:
570
+ .loc 1 323 0
571
+ add w21, w21, 1
572
+.LVL44:
573
+ cmp w21, 8
574
+ bne .L50
575
+.LVL45:
576
+.LBE49:
577
+.LBE48:
578
+ .loc 1 387 0
579
+ cbz w23, .L45
580
+.LVL46:
581
+ .loc 1 389 0
582
+ uxtw x1, w19
583
+ mov x2, 328
584
+ sxtw x0, w22
585
+ mul x1, x1, x2
586
+ mov x2, 40
587
+ madd x0, x0, x2, x1
588
+ mov x1, 136314880
589
+ add x0, x1, x0
590
+ ldr w0, [x0, 28]
591
+ cbnz w0, .L51
592
+.LVL47:
593
+.L52:
594
+ .loc 1 410 0
595
+ mov w2, w20
596
+ mov w1, w19
597
+ adrp x0, .LC11
598
+ add x0, x0, :lo12:.LC11
599
+ bl printf
600
+.LVL48:
601
+ .loc 1 374 0
602
+ mov w21, 0
603
+ .loc 1 411 0
604
+ mov w2, 1431655765
605
+ mov w1, w20
606
+ mov w0, w19
607
+ bl mpb_task_set_state
608
+.LVL49:
609
+ b .L58
610
+.LVL50:
611
+.L49:
612
+.LBB51:
613
+.LBB50:
614
+ .loc 1 330 0
615
+ mov x0, 100
616
+ bl udelay
617
+.LVL51:
618
+ .loc 1 333 0
619
+ subs w24, w24, #1
620
+.LVL52:
621
+ bne .L48
622
+.LVL53:
623
+ .loc 1 337 0
624
+ bl mpb_task_dump
625
+.LVL54:
626
+ b .L47
627
+.LVL55:
628
+.L45:
629
+.LBE50:
630
+.LBE51:
631
+ .loc 1 392 0
632
+ uxtw x1, w19
633
+ mov x2, 328
634
+ sxtw x0, w22
635
+ mul x1, x1, x2
636
+ mov x2, 40
637
+ madd x0, x0, x2, x1
638
+ mov x1, 136314880
639
+ add x0, x1, x0
640
+ ldr w0, [x0, 28]
641
+ cbnz w0, .L52
642
+.L51:
643
+.LVL56:
644
+ .loc 1 397 0
645
+ mov w2, w20
646
+ mov w1, w19
647
+ adrp x0, .LC12
648
+ add x0, x0, :lo12:.LC12
649
+ bl printf
650
+.LVL57:
651
+ .loc 1 401 0
652
+ uxtw x24, w19
653
+ .loc 1 398 0
654
+ bl get_ticks
655
+.LVL58:
656
+ mov x23, x0
657
+.LVL59:
658
+ .loc 1 400 0
659
+ mov w2, 286331153
660
+ mov w1, w20
661
+ mov w0, w19
662
+.LVL60:
663
+ bl mpb_task_set_state
664
+.LVL61:
665
+ .loc 1 401 0
666
+ mov x1, 328
667
+ mov x0, 40
668
+ mul x1, x24, x1
669
+ madd x1, x22, x0, x1
670
+ mov x0, 8
671
+ movk x0, 0x820, lsl 16
672
+ ldr x1, [x0, x1]
673
+ mov x0, 1320
674
+ movk x0, 0x820, lsl 16
675
+ blr x1
676
+.LVL62:
677
+ mov w21, w0
678
+.LVL63:
679
+ .loc 1 402 0
680
+ cbnz w0, .L59
681
+ .loc 1 405 0
682
+ mov w2, -559087616
683
+ b .L77
684
+.L59:
685
+ .loc 1 403 0
686
+ mov w2, -65536
687
+.L77:
688
+ .loc 1 405 0
689
+ mov w1, w20
690
+ mov w0, w19
691
+.LVL64:
692
+ bl mpb_task_set_state
693
+.LVL65:
694
+ .loc 1 407 0
695
+ bl get_ticks
696
+.LVL66:
697
+ sub x0, x0, x23
698
+ mov x4, 24000
699
+ .loc 1 408 0
700
+ mov w3, w21
701
+ mov w2, w20
702
+ mov w1, w19
703
+ .loc 1 407 0
704
+ udiv x4, x0, x4
705
+ mov x0, 328
706
+ mul x0, x24, x0
707
+ mov x24, 40
708
+ madd x24, x22, x24, x0
709
+ mov x22, 40
710
+.LVL67:
711
+ movk x22, 0x820, lsl 16
712
+ .loc 1 408 0
713
+ adrp x0, .LC10
714
+ add x0, x0, :lo12:.LC10
715
+ .loc 1 407 0
716
+ str x4, [x22, x24]
717
+ .loc 1 408 0
718
+ bl printf
719
+.LVL68:
720
+.L58:
721
+.LBB52:
722
+.LBB53:
723
+.LBB54:
724
+.LBB55:
725
+ .loc 1 146 0
726
+ mov x0, 136314880
727
+ mov w1, 1
728
+ lsl w1, w1, w20
729
+ ldr w2, [x0]
730
+.LBE55:
731
+.LBE54:
732
+ .loc 1 212 0
733
+ tst w1, w2
734
+ beq .L44
735
+.LBB56:
736
+.LBB57:
737
+ .loc 1 199 0
738
+ uxtw x3, w19
739
+ mov x1, 328
740
+ umull x19, w19, w1
741
+.LVL69:
742
+ madd x0, x3, x1, x0
743
+ mov w1, 0
744
+ ldrb w2, [x0, 328]
745
+ mov x0, 20
746
+ movk x0, 0x820, lsl 16
747
+ add x0, x19, x0
748
+.L55:
749
+.LVL70:
750
+ cmp w1, w2
751
+ blt .L57
752
+.LVL71:
753
+.L44:
754
+.LBE57:
755
+.LBE56:
756
+.LBE53:
757
+.LBE52:
758
+ .loc 1 417 0
759
+ ldp x19, x20, [sp, 16]
760
+.LVL72:
761
+ ldp x21, x22, [sp, 32]
762
+.LVL73:
763
+ ldp x23, x24, [sp, 48]
764
+ ldp x25, x26, [sp, 64]
765
+ ldp x29, x30, [sp], 80
766
+ .cfi_remember_state
767
+ .cfi_restore 30
768
+ .cfi_restore 29
769
+ .cfi_restore 25
770
+ .cfi_restore 26
771
+ .cfi_restore 23
772
+ .cfi_restore 24
773
+ .cfi_restore 21
774
+ .cfi_restore 22
775
+ .cfi_restore 19
776
+ .cfi_restore 20
777
+ .cfi_def_cfa 31, 0
778
+ ret
779
+.LVL74:
780
+.L57:
781
+ .cfi_restore_state
782
+.LBB65:
783
+.LBB60:
784
+.LBB59:
785
+.LBB58:
786
+ .loc 1 200 0
787
+ ldr w4, [x0], 40
788
+ cmp w20, w4
789
+ beq .L56
790
+ .loc 1 199 0
791
+ add w1, w1, 1
792
+.LVL75:
793
+ b .L55
794
+.L56:
795
+.LVL76:
796
+.LBE58:
797
+.LBE59:
798
+ .loc 1 219 0
799
+ sxtw x2, w1
800
+ mov x5, 328
801
+ mov x4, 40
802
+ .loc 1 220 0
803
+ add x19, x19, 32
804
+ .loc 1 219 0
805
+ mul x3, x3, x5
806
+ mov x0, 136314880
807
+ madd x2, x2, x4, x3
808
+ .loc 1 220 0
809
+ smaddl x19, w1, w4, x19
810
+ .loc 1 219 0
811
+ add x2, x0, x2
812
+.LBE60:
813
+.LBE65:
814
+ .loc 1 417 0
815
+ ldp x23, x24, [sp, 48]
816
+.LBB66:
817
+.LBB61:
818
+ .loc 1 220 0
819
+ add x0, x19, x0
820
+.LBE61:
821
+.LBE66:
822
+ .loc 1 417 0
823
+ ldp x25, x26, [sp, 64]
824
+.LBB67:
825
+.LBB62:
826
+ .loc 1 221 0
827
+ add x1, x0, 4
828
+.LBE62:
829
+.LBE67:
830
+ .loc 1 417 0
831
+ ldp x19, x20, [sp, 16]
832
+.LVL77:
833
+.LBB68:
834
+.LBB63:
835
+ .loc 1 219 0
836
+ str w21, [x2, 32]
837
+.LBE63:
838
+.LBE68:
839
+ .loc 1 417 0
840
+ ldp x21, x22, [sp, 32]
841
+.LVL78:
842
+ ldp x29, x30, [sp], 80
843
+ .cfi_restore 30
844
+ .cfi_restore 29
845
+ .cfi_restore 25
846
+ .cfi_restore 26
847
+ .cfi_restore 23
848
+ .cfi_restore 24
849
+ .cfi_restore 21
850
+ .cfi_restore 22
851
+ .cfi_restore 19
852
+ .cfi_restore 20
853
+ .cfi_def_cfa 31, 0
854
+.LBB69:
855
+.LBB64:
856
+ .loc 1 221 0
857
+ b flush_dcache_range
858
+.LVL79:
859
+.LBE64:
860
+.LBE69:
861
+ .cfi_endproc
862
+.LFE242:
863
+ .size core_task_run.part.1, .-core_task_run.part.1
864
+ .section .text.mpb_task_wait_done,"ax",@progbits
865
+ .align 2
866
+ .global mpb_task_wait_done
867
+ .type mpb_task_wait_done, %function
868
+mpb_task_wait_done:
869
+.LFB232:
870
+ .loc 1 366 0
871
+ .cfi_startproc
872
+.LVL80:
873
+ stp x29, x30, [sp, -32]!
874
+ .cfi_def_cfa_offset 32
875
+ .cfi_offset 29, -32
876
+ .cfi_offset 30, -24
877
+ add x29, sp, 0
878
+ .cfi_def_cfa_register 29
879
+ str x19, [sp, 16]
880
+ .cfi_offset 19, -16
881
+ mov w19, w0
882
+.LVL81:
883
+.L80:
884
+.LBB74:
885
+.LBB75:
886
+ .loc 1 355 0
887
+ mov w0, w19
888
+ bl mpb_task_is_done
889
+.LVL82:
890
+ cbnz w0, .L79
891
+.LVL83:
892
+.LBB76:
893
+.LBB77:
894
+ .file 2 "include/linux/delay.h"
895
+ .loc 2 16 0
896
+ mov x0, 1000
897
+ bl udelay
898
+.LVL84:
899
+ mov x0, 1000
900
+ bl udelay
901
+.LVL85:
902
+ b .L80
903
+.L79:
904
+.LBE77:
905
+.LBE76:
906
+ .loc 1 362 0
907
+ mov w0, w19
908
+.LBE75:
909
+.LBE74:
910
+ .loc 1 368 0
911
+ ldr x19, [sp, 16]
912
+.LVL86:
913
+ ldp x29, x30, [sp], 32
914
+ .cfi_restore 30
915
+ .cfi_restore 29
916
+ .cfi_restore 19
917
+ .cfi_def_cfa 31, 0
918
+.LBB79:
919
+.LBB78:
920
+ .loc 1 362 0
921
+ b mpb_task_is_done
922
+.LVL87:
923
+.LBE78:
924
+.LBE79:
925
+ .cfi_endproc
926
+.LFE232:
927
+ .size mpb_task_wait_done, .-mpb_task_wait_done
928
+ .section .text.mpb_task_run,"ax",@progbits
929
+ .align 2
930
+ .global mpb_task_run
931
+ .type mpb_task_run, %function
932
+mpb_task_run:
933
+.LFB234:
934
+ .loc 1 420 0
935
+ .cfi_startproc
936
+.LVL88:
937
+ stp x29, x30, [sp, -80]!
938
+ .cfi_def_cfa_offset 80
939
+ .cfi_offset 29, -80
940
+ .cfi_offset 30, -72
941
+.LBB86:
942
+.LBB87:
943
+ .loc 1 146 0
944
+ mov x3, 136314880
945
+.LBE87:
946
+.LBE86:
947
+ .loc 1 420 0
948
+ add x29, sp, 0
949
+ .cfi_def_cfa_register 29
950
+ stp x23, x24, [sp, 48]
951
+ .cfi_offset 23, -32
952
+ .cfi_offset 24, -24
953
+.LBB89:
954
+.LBB88:
955
+ .loc 1 146 0
956
+ mov w24, 1
957
+ ldr w2, [x3]
958
+ lsl w24, w24, w1
959
+.LVL89:
960
+.LBE88:
961
+.LBE89:
962
+ .loc 1 420 0
963
+ stp x19, x20, [sp, 16]
964
+ stp x21, x22, [sp, 32]
965
+ .loc 1 424 0
966
+ tst w24, w2
967
+ .loc 1 420 0
968
+ str x25, [sp, 64]
969
+ .cfi_offset 19, -64
970
+ .cfi_offset 20, -56
971
+ .cfi_offset 21, -48
972
+ .cfi_offset 22, -40
973
+ .cfi_offset 25, -16
974
+ .loc 1 424 0
975
+ beq .L82
976
+ .loc 1 424 0 is_stmt 0 discriminator 1
977
+ cbz w1, .L82
978
+ uxtw x25, w0
979
+.LVL90:
980
+ .loc 1 421 0 is_stmt 1
981
+ mov w19, 328
982
+ mov x0, 8
983
+.LVL91:
984
+ mov x22, x25
985
+ mov w21, w1
986
+ .loc 1 427 0
987
+ mov x20, x3
988
+ .loc 1 421 0
989
+ umaddl x19, w25, w19, x0
990
+ .loc 1 427 0
991
+ mov x0, 328
992
+ .loc 1 421 0
993
+ mov w23, 0
994
+ .loc 1 427 0
995
+ madd x25, x25, x0, x3
996
+.LVL92:
997
+ .loc 1 421 0
998
+ add x19, x19, x3
999
+.LVL93:
1000
+.L85:
1001
+ .loc 1 427 0 discriminator 1
1002
+ ldrb w0, [x25, 328]
1003
+ cmp w23, w0
1004
+ blt .L87
1005
+.LVL94:
1006
+.L82:
1007
+ .loc 1 431 0
1008
+ ldp x19, x20, [sp, 16]
1009
+ ldp x21, x22, [sp, 32]
1010
+ ldp x23, x24, [sp, 48]
1011
+ ldr x25, [sp, 64]
1012
+ ldp x29, x30, [sp], 80
1013
+ .cfi_remember_state
1014
+ .cfi_restore 30
1015
+ .cfi_restore 29
1016
+ .cfi_restore 25
1017
+ .cfi_restore 23
1018
+ .cfi_restore 24
1019
+ .cfi_restore 21
1020
+ .cfi_restore 22
1021
+ .cfi_restore 19
1022
+ .cfi_restore 20
1023
+ .cfi_def_cfa 31, 0
1024
+ ret
1025
+.LVL95:
1026
+.L87:
1027
+ .cfi_restore_state
1028
+ .loc 1 428 0
1029
+ ldr w0, [x19, 12]
1030
+ cmp w21, w0
1031
+ bne .L86
1032
+ .loc 1 428 0 is_stmt 0 discriminator 1
1033
+ ldr x0, [x19]
1034
+ cbz x0, .L86
1035
+.LVL96:
1036
+.LBB90:
1037
+.LBB91:
1038
+.LBB92:
1039
+.LBB93:
1040
+ .loc 1 146 0 is_stmt 1
1041
+ ldr w0, [x20]
1042
+.LBE93:
1043
+.LBE92:
1044
+ .loc 1 377 0
1045
+ tst w24, w0
1046
+ beq .L86
1047
+ ldr w3, [x19, 16]
1048
+ mov w2, w21
1049
+ mov w1, w23
1050
+ mov w0, w22
1051
+ bl core_task_run.part.1
1052
+.LVL97:
1053
+.L86:
1054
+.LBE91:
1055
+.LBE90:
1056
+ .loc 1 427 0 discriminator 2
1057
+ add w23, w23, 1
1058
+.LVL98:
1059
+ add x19, x19, 40
1060
+ b .L85
1061
+ .cfi_endproc
1062
+.LFE234:
1063
+ .size mpb_task_run, .-mpb_task_run
1064
+ .section .text.core_main,"ax",@progbits
1065
+ .align 2
1066
+ .global core_main
1067
+ .type core_main, %function
1068
+core_main:
1069
+.LFB235:
1070
+ .loc 1 434 0
1071
+ .cfi_startproc
1072
+.LVL99:
1073
+ stp x29, x30, [sp, -64]!
1074
+ .cfi_def_cfa_offset 64
1075
+ .cfi_offset 29, -64
1076
+ .cfi_offset 30, -56
1077
+ add x29, sp, 0
1078
+ .cfi_def_cfa_register 29
1079
+ stp x21, x22, [sp, 32]
1080
+ .cfi_offset 21, -32
1081
+ .cfi_offset 22, -24
1082
+ uxtw x22, w0
1083
+ stp x19, x20, [sp, 16]
1084
+ .loc 1 435 0
1085
+ mov x0, 8
1086
+.LVL100:
1087
+ .cfi_offset 19, -48
1088
+ .cfi_offset 20, -40
1089
+ mov w19, 328
1090
+ mov x20, 136314880
1091
+ .loc 1 434 0
1092
+ stp x23, x24, [sp, 48]
1093
+ .cfi_offset 23, -16
1094
+ .cfi_offset 24, -8
1095
+ .loc 1 434 0
1096
+ mov x23, x22
1097
+.LVL101:
1098
+ .loc 1 435 0
1099
+ umaddl x19, w22, w19, x0
1100
+ .loc 1 438 0
1101
+ mov x0, 328
1102
+ mov w21, 0
1103
+.LBB98:
1104
+.LBB99:
1105
+.LBB100:
1106
+.LBB101:
1107
+ .loc 1 146 0
1108
+ mov w24, 1
1109
+.LBE101:
1110
+.LBE100:
1111
+.LBE99:
1112
+.LBE98:
1113
+ .loc 1 438 0
1114
+ madd x22, x22, x0, x20
1115
+.LVL102:
1116
+ .loc 1 435 0
1117
+ add x19, x19, x20
1118
+.LVL103:
1119
+.L99:
1120
+ .loc 1 438 0 discriminator 1
1121
+ ldrb w0, [x22, 328]
1122
+ cmp w21, w0
1123
+ blt .L101
1124
+ .loc 1 442 0
1125
+ ldp x19, x20, [sp, 16]
1126
+ ldp x21, x22, [sp, 32]
1127
+.LVL104:
1128
+ ldp x23, x24, [sp, 48]
1129
+.LVL105:
1130
+ ldp x29, x30, [sp], 64
1131
+ .cfi_remember_state
1132
+ .cfi_restore 30
1133
+ .cfi_restore 29
1134
+ .cfi_restore 23
1135
+ .cfi_restore 24
1136
+ .cfi_restore 21
1137
+ .cfi_restore 22
1138
+ .cfi_restore 19
1139
+ .cfi_restore 20
1140
+ .cfi_def_cfa 31, 0
1141
+ ret
1142
+.LVL106:
1143
+.L101:
1144
+ .cfi_restore_state
1145
+ .loc 1 439 0
1146
+ ldr x0, [x19]
1147
+ cbz x0, .L100
1148
+ .loc 1 440 0
1149
+ ldr w2, [x19, 12]
1150
+.LVL107:
1151
+.LBB105:
1152
+.LBB104:
1153
+.LBB103:
1154
+.LBB102:
1155
+ .loc 1 146 0
1156
+ ldr w0, [x20]
1157
+ lsl w1, w24, w2
1158
+.LBE102:
1159
+.LBE103:
1160
+ .loc 1 377 0
1161
+ tst w1, w0
1162
+ beq .L100
1163
+ ldr w3, [x19, 16]
1164
+ mov w1, w21
1165
+ mov w0, w23
1166
+ bl core_task_run.part.1
1167
+.LVL108:
1168
+.L100:
1169
+.LBE104:
1170
+.LBE105:
1171
+ .loc 1 438 0 discriminator 2
1172
+ add w21, w21, 1
1173
+.LVL109:
1174
+ add x19, x19, 40
1175
+ b .L99
1176
+ .cfi_endproc
1177
+.LFE235:
1178
+ .size core_main, .-core_main
1179
+ .section .text.smp_entry,"ax",@progbits
1180
+ .align 2
1181
+ .global smp_entry
1182
+ .type smp_entry, %function
1183
+smp_entry:
1184
+.LFB236:
1185
+ .loc 1 448 0
1186
+ .cfi_startproc
1187
+.LVL110:
1188
+ stp x29, x30, [sp, -32]!
1189
+ .cfi_def_cfa_offset 32
1190
+ .cfi_offset 29, -32
1191
+ .cfi_offset 30, -24
1192
+ add x29, sp, 0
1193
+ .cfi_def_cfa_register 29
1194
+ str x19, [sp, 16]
1195
+ .cfi_offset 19, -16
1196
+ .loc 1 448 0
1197
+ mov w19, w0
1198
+ .loc 1 450 0
1199
+ adrp x0, .LANCHOR1
1200
+.LVL111:
1201
+ ldr x0, [x0, #:lo12:.LANCHOR1]
1202
+.LVL112:
1203
+.LBB106:
1204
+.LBB107:
1205
+ .loc 1 131 0
1206
+#APP
1207
+// 131 "common/mp_boot.c" 1
1208
+ mov x18, x0
1209
+
1210
+// 0 "" 2
1211
+.LVL113:
1212
+#NO_APP
1213
+.LBE107:
1214
+.LBE106:
1215
+ .loc 1 451 0
1216
+ bl dcache_enable
1217
+.LVL114:
1218
+ .loc 1 455 0
1219
+ cmp w19, 1
1220
+ bne .L110
1221
+.L114:
1222
+ .loc 1 460 0
1223
+ mov w0, w19
1224
+ bl core_main
1225
+.LVL115:
1226
+ b .L111
1227
+.L110:
1228
+ .loc 1 459 0
1229
+ cmp w19, 2
1230
+ beq .L114
1231
+.L111:
1232
+ .loc 1 468 0
1233
+ bl flush_dcache_all
1234
+.LVL116:
1235
+ .loc 1 469 0
1236
+ bl disable_interrupts
1237
+.LVL117:
1238
+.LBB108:
1239
+.LBB109:
1240
+ .file 3 "./arch/arm/include/asm/system.h"
1241
+ .loc 3 193 0
1242
+#APP
1243
+// 193 "./arch/arm/include/asm/system.h" 1
1244
+ msr daifset, #0x04
1245
+// 0 "" 2
1246
+#NO_APP
1247
+.LBE109:
1248
+.LBE108:
1249
+ .loc 1 471 0
1250
+ bl icache_disable
1251
+.LVL118:
1252
+ .loc 1 472 0
1253
+ bl invalidate_icache_all
1254
+.LVL119:
1255
+ .loc 1 473 0
1256
+ bl dcache_disable
1257
+.LVL120:
1258
+.LBB110:
1259
+.LBB111:
1260
+ .loc 1 138 0
1261
+#APP
1262
+// 138 "common/mp_boot.c" 1
1263
+ mrs x0, S3_1_c15_c2_1
1264
+// 0 "" 2
1265
+ .loc 1 139 0
1266
+// 139 "common/mp_boot.c" 1
1267
+ bic x0, x0, #0x40
1268
+// 0 "" 2
1269
+ .loc 1 140 0
1270
+// 140 "common/mp_boot.c" 1
1271
+ msr S3_1_c15_c2_1, x0
1272
+// 0 "" 2
1273
+#NO_APP
1274
+.LBE111:
1275
+.LBE110:
1276
+ .loc 1 475 0
1277
+ bl invalidate_dcache_all
1278
+.LVL121:
1279
+ .loc 1 478 0
1280
+#APP
1281
+// 478 "common/mp_boot.c" 1
1282
+ dsb sy
1283
+// 0 "" 2
1284
+ .loc 1 479 0
1285
+// 479 "common/mp_boot.c" 1
1286
+ isb sy
1287
+// 0 "" 2
1288
+#NO_APP
1289
+.L112:
1290
+ .loc 1 481 0 discriminator 1
1291
+#APP
1292
+// 481 "common/mp_boot.c" 1
1293
+ wfe
1294
+// 0 "" 2
1295
+#NO_APP
1296
+ b .L112
1297
+ .cfi_endproc
1298
+.LFE236:
1299
+ .size smp_entry, .-smp_entry
1300
+ .section .text.mpb_init_1,"ax",@progbits
1301
+ .align 2
1302
+ .global mpb_init_1
1303
+ .type mpb_init_1, %function
1304
+mpb_init_1:
1305
+.LFB238:
1306
+ .loc 1 527 0
1307
+ .cfi_startproc
1308
+ stp x29, x30, [sp, -16]!
1309
+ .cfi_def_cfa_offset 16
1310
+ .cfi_offset 29, -16
1311
+ .cfi_offset 30, -8
1312
+ .loc 1 528 0
1313
+ mov x2, 40
1314
+ mov x1, x0
1315
+ mov x0, 1320
1316
+ .loc 1 527 0
1317
+ add x29, sp, 0
1318
+ .cfi_def_cfa_register 29
1319
+ .loc 1 528 0
1320
+ movk x0, 0x820, lsl 16
1321
+ .loc 1 527 0
1322
+ .loc 1 528 0
1323
+ bl memcpy
1324
+.LVL122:
1325
+ .loc 1 530 0
1326
+ mov w1, 2
1327
+ mov w0, 0
1328
+ bl mpb_task_run
1329
+.LVL123:
1330
+ .loc 1 531 0
1331
+ mov w2, 286331153
1332
+ mov w1, 3
1333
+ mov w0, 0
1334
+ bl mpb_task_set_state
1335
+.LVL124:
1336
+ .loc 1 532 0
1337
+ bl flush_dcache_all
1338
+.LVL125:
1339
+ .loc 1 533 0
1340
+#APP
1341
+// 533 "common/mp_boot.c" 1
1342
+ dsb sy
1343
+// 0 "" 2
1344
+ .loc 1 534 0
1345
+// 534 "common/mp_boot.c" 1
1346
+ isb sy
1347
+// 0 "" 2
1348
+ .loc 1 535 0
1349
+#NO_APP
1350
+ ldp x29, x30, [sp], 16
1351
+ .cfi_restore 30
1352
+ .cfi_restore 29
1353
+ .cfi_def_cfa 31, 0
1354
+ ret
1355
+ .cfi_endproc
1356
+.LFE238:
1357
+ .size mpb_init_1, .-mpb_init_1
1358
+ .section .text.mpb_init_x,"ax",@progbits
1359
+ .align 2
1360
+ .global mpb_init_x
1361
+ .type mpb_init_x, %function
1362
+mpb_init_x:
1363
+.LFB239:
1364
+ .loc 1 538 0
1365
+ .cfi_startproc
1366
+.LVL126:
1367
+ stp x29, x30, [sp, -64]!
1368
+ .cfi_def_cfa_offset 64
1369
+ .cfi_offset 29, -64
1370
+ .cfi_offset 30, -56
1371
+ .loc 1 539 0
1372
+ cmp w0, 2
1373
+ .loc 1 538 0
1374
+ add x29, sp, 0
1375
+ .cfi_def_cfa_register 29
1376
+ .loc 1 539 0
1377
+ beq .L119
1378
+ cmp w0, 3
1379
+ beq .L120
1380
+ cbnz w0, .L117
1381
+.LBB120:
1382
+.LBB121:
1383
+ .loc 1 494 0
1384
+ adrp x1, .LANCHOR2
1385
+ add x1, x1, :lo12:.LANCHOR2
1386
+ mov x2, 48
1387
+ add x0, x29, 16
1388
+.LVL127:
1389
+ bl memcpy
1390
+.LVL128:
1391
+ .loc 1 509 0
1392
+ adrp x0, .LC13
1393
+ add x0, x0, :lo12:.LC13
1394
+ bl printf
1395
+.LVL129:
1396
+ .loc 1 511 0
1397
+ mov x2, 1376
1398
+ mov w1, 0
1399
+ mov x0, 136314880
1400
+ bl memset
1401
+.LVL130:
1402
+ .loc 1 512 0
1403
+ adrp x0, .LANCHOR1
1404
+ add x6, x29, 64
1405
+.LBB122:
1406
+.LBB123:
1407
+ .loc 1 177 0
1408
+ mov x4, 136314880
1409
+ mov x7, 328
1410
+.LBE123:
1411
+.LBE122:
1412
+ .loc 1 512 0
1413
+ str x18, [x0, #:lo12:.LANCHOR1]
1414
+.LVL131:
1415
+ add x0, x29, 16
1416
+.LBB126:
1417
+.LBB124:
1418
+ .loc 1 179 0
1419
+ mov x8, 40
1420
+ .loc 1 185 0
1421
+ mov w10, 1
1422
+.LVL132:
1423
+.L122:
1424
+.LBE124:
1425
+.LBE126:
1426
+ .loc 1 514 0
1427
+ cmp x6, x0
1428
+ bne .L124
1429
+ .loc 1 517 0
1430
+ bl flush_dcache_all
1431
+.LVL133:
1432
+.LBB127:
1433
+ .loc 1 518 0
1434
+#APP
1435
+// 518 "common/mp_boot.c" 1
1436
+ dmb sy
1437
+// 0 "" 2
1438
+#NO_APP
1439
+ mov x1, 8
1440
+ adrp x0, save_boot_params_ret
1441
+ movk x1, 0xfe48, lsl 16
1442
+ add x0, x0, :lo12:save_boot_params_ret
1443
+ str w0, [x1]
1444
+.LVL134:
1445
+.LBE127:
1446
+.LBB128:
1447
+ .loc 1 519 0
1448
+#APP
1449
+// 519 "common/mp_boot.c" 1
1450
+ dmb sy
1451
+// 0 "" 2
1452
+#NO_APP
1453
+ mov x0, 4
1454
+ mov w1, 48815
1455
+ movk x0, 0xfe48, lsl 16
1456
+ movk w1, 0xdead, lsl 16
1457
+ str w1, [x0]
1458
+.LBE128:
1459
+ .loc 1 520 0
1460
+#APP
1461
+// 520 "common/mp_boot.c" 1
1462
+ dsb sy
1463
+// 0 "" 2
1464
+ .loc 1 522 0
1465
+// 522 "common/mp_boot.c" 1
1466
+ sev
1467
+// 0 "" 2
1468
+ .loc 1 523 0
1469
+// 523 "common/mp_boot.c" 1
1470
+ isb sy
1471
+// 0 "" 2
1472
+.LVL135:
1473
+#NO_APP
1474
+.L117:
1475
+.LBE121:
1476
+.LBE120:
1477
+ .loc 1 556 0
1478
+ ldp x29, x30, [sp], 64
1479
+ .cfi_remember_state
1480
+ .cfi_restore 30
1481
+ .cfi_restore 29
1482
+ .cfi_def_cfa 31, 0
1483
+ ret
1484
+.L124:
1485
+ .cfi_restore_state
1486
+ ldp w1, w3, [x0]
1487
+.LVL136:
1488
+ ldp w12, w11, [x0, 16]
1489
+.LBB131:
1490
+.LBB130:
1491
+.LBB129:
1492
+.LBB125:
1493
+ .loc 1 172 0
1494
+ cmp w1, 3
1495
+ ldr x13, [x0, 8]
1496
+.LVL137:
1497
+ beq .L123
1498
+ .loc 1 176 0
1499
+ sub w2, w3, #1
1500
+ cmp w2, 6
1501
+ bhi .L123
1502
+.LVL138:
1503
+ .loc 1 177 0
1504
+ uxtw x1, w1
1505
+ mul x2, x1, x7
1506
+ add x5, x4, x2
1507
+ .loc 1 179 0
1508
+ ldrb w1, [x5, 328]
1509
+.LVL139:
1510
+ madd x1, x1, x8, x2
1511
+ add x1, x4, x1
1512
+ .loc 1 181 0
1513
+ stp w3, w12, [x1, 20]
1514
+.LVL140:
1515
+ .loc 1 185 0
1516
+ lsl w3, w10, w3
1517
+.LVL141:
1518
+ .loc 1 183 0
1519
+ stp w11, wzr, [x1, 28]
1520
+ .loc 1 179 0
1521
+ str x13, [x1, 8]
1522
+ .loc 1 184 0
1523
+ str xzr, [x1, 40]
1524
+ .loc 1 185 0
1525
+ ldr w1, [x4]
1526
+.LVL142:
1527
+ orr w3, w1, w3
1528
+ str w3, [x4]
1529
+ .loc 1 186 0
1530
+ ldrb w1, [x5, 328]
1531
+ add w1, w1, 1
1532
+ strb w1, [x5, 328]
1533
+.L123:
1534
+ add x0, x0, 24
1535
+ b .L122
1536
+.LVL143:
1537
+.L119:
1538
+.LBE125:
1539
+.LBE129:
1540
+.LBE130:
1541
+.LBE131:
1542
+ .loc 1 544 0
1543
+ mov w2, -559087616
1544
+ mov w1, 3
1545
+ mov w0, 0
1546
+.LVL144:
1547
+ bl mpb_task_set_state
1548
+.LVL145:
1549
+ .loc 1 545 0
1550
+ bl flush_dcache_all
1551
+.LVL146:
1552
+ .loc 1 546 0
1553
+#APP
1554
+// 546 "common/mp_boot.c" 1
1555
+ dsb sy
1556
+// 0 "" 2
1557
+ .loc 1 547 0
1558
+// 547 "common/mp_boot.c" 1
1559
+ isb sy
1560
+// 0 "" 2
1561
+.LVL147:
1562
+ .loc 1 556 0
1563
+#NO_APP
1564
+ ldp x29, x30, [sp], 64
1565
+ .cfi_remember_state
1566
+ .cfi_restore 30
1567
+ .cfi_restore 29
1568
+ .cfi_def_cfa 31, 0
1569
+.LBB132:
1570
+.LBB133:
1571
+ .loc 2 16 0
1572
+ mov x0, 1000
1573
+ b udelay
1574
+.LVL148:
1575
+.L120:
1576
+ .cfi_restore_state
1577
+.LBE133:
1578
+.LBE132:
1579
+ .loc 1 556 0
1580
+ ldp x29, x30, [sp], 64
1581
+ .cfi_restore 30
1582
+ .cfi_restore 29
1583
+ .cfi_def_cfa 31, 0
1584
+ .loc 1 553 0
1585
+ mov w2, -559087616
1586
+ mov w1, 7
1587
+ mov w0, 0
1588
+.LVL149:
1589
+ b mpb_task_set_state
1590
+.LVL150:
1591
+ .cfi_endproc
1592
+.LFE239:
1593
+ .size mpb_init_x, .-mpb_init_x
1594
+ .section .text.mpb_post,"ax",@progbits
1595
+ .align 2
1596
+ .global mpb_post
1597
+ .type mpb_post, %function
1598
+mpb_post:
1599
+.LFB240:
1600
+ .loc 1 626 0
1601
+ .cfi_startproc
1602
+.LVL151:
1603
+ .loc 1 627 0
1604
+ cmp w0, 6
1605
+ bne .L133
1606
+ .loc 1 626 0
1607
+ stp x29, x30, [sp, -16]!
1608
+ .cfi_def_cfa_offset 16
1609
+ .cfi_offset 29, -16
1610
+ .cfi_offset 30, -8
1611
+ .loc 1 629 0
1612
+ mov w0, 2
1613
+.LVL152:
1614
+ .loc 1 626 0
1615
+ add x29, sp, 0
1616
+ .cfi_def_cfa_register 29
1617
+ .loc 1 629 0
1618
+ bl mpb_task_wait_done
1619
+.LVL153:
1620
+ sxtw x0, w0
1621
+ .loc 1 633 0
1622
+ ldp x29, x30, [sp], 16
1623
+ .cfi_restore 30
1624
+ .cfi_restore 29
1625
+ .cfi_def_cfa 31, 0
1626
+ ret
1627
+.LVL154:
1628
+.L133:
1629
+ .loc 1 632 0
1630
+ mov x0, 0
1631
+.LVL155:
1632
+ ret
1633
+ .cfi_endproc
1634
+.LFE240:
1635
+ .size mpb_post, .-mpb_post
1636
+ .section .rodata
1637
+ .align 3
1638
+ .set .LANCHOR2,. + 0
1639
+.LC0:
1640
+ .word 0
1641
+ .word 2
1642
+ .xword spl_load_baseparamter
1643
+ .word 0
1644
+ .word 0
1645
+ .word 2
1646
+ .word 1
1647
+ .xword spl_init_display
1648
+ .word 0
1649
+ .word 0
1650
+ .section .bss.mpb_gd,"aw",@nobits
1651
+ .align 3
1652
+ .set .LANCHOR1,. + 0
1653
+ .type mpb_gd, %object
1654
+ .size mpb_gd, 8
1655
+mpb_gd:
1656
+ .zero 8
1657
+ .section .rodata.core_task_run.part.1.str1.1,"aMS",@progbits,1
1658
+.LC10:
1659
+ .string "-- T%d.%d [%d, %ld]\n"
1660
+.LC11:
1661
+ .string "++ T%d.%d -\n"
1662
+.LC12:
1663
+ .string "++ T%d.%d\n"
1664
+ .section .rodata.mpb_init_x.str1.1,"aMS",@progbits,1
1665
+.LC13:
1666
+ .string "U-Boot SPL MP\n"
1667
+ .section .rodata.mpb_task_dump.str1.1,"aMS",@progbits,1
1668
+.LC1:
1669
+ .string "data: %08lx, %08lx\n"
1670
+.LC2:
1671
+ .string "T%d.%d:[%s]\n"
1672
+.LC3:
1673
+ .string " tid: %d\n"
1674
+.LC4:
1675
+ .string " fn: 0x%08lx\n"
1676
+.LC5:
1677
+ .string " state: 0x%08x\n"
1678
+.LC6:
1679
+ .string " ret: %d\n"
1680
+.LC7:
1681
+ .string " ms: %ld\n"
1682
+.LC8:
1683
+ .string " ptid_mask: 0x%08x\n"
1684
+.LC9:
1685
+ .string " rip_fail: %d\n\n"
1686
+ .section .rodata.str1.1,"aMS",@progbits,1
1687
+.LC14:
1688
+ .string "none"
1689
+.LC15:
1690
+ .string "init-display"
1691
+.LC16:
1692
+ .string "load-baseparameter"
1693
+.LC17:
1694
+ .string "load-uboot"
1695
+.LC18:
1696
+ .string "load-fit"
1697
+.LC19:
1698
+ .string "load-android"
1699
+.LC20:
1700
+ .string "hash-android"
1701
+.LC21:
1702
+ .string "run-uboot"
1703
+ .section .rodata.tid_name,"a",@progbits
1704
+ .align 3
1705
+ .set .LANCHOR0,. + 0
1706
+ .type tid_name, %object
1707
+ .size tid_name, 64
1708
+tid_name:
1709
+ .xword .LC14
1710
+ .xword .LC15
1711
+ .xword .LC16
1712
+ .xword .LC17
1713
+ .xword .LC18
1714
+ .xword .LC19
1715
+ .xword .LC20
1716
+ .xword .LC21
1717
+ .text
1718
+.Letext0:
1719
+ .file 4 "include/common.h"
1720
+ .file 5 "./arch/arm/include/asm/types.h"
1721
+ .file 6 "include/linux/types.h"
1722
+ .file 7 "include/errno.h"
1723
+ .file 8 "include/linux/string.h"
1724
+ .file 9 "include/efi.h"
1725
+ .file 10 "include/ide.h"
1726
+ .file 11 "include/linux/list.h"
1727
+ .file 12 "include/part.h"
1728
+ .file 13 "include/flash.h"
1729
+ .file 14 "include/lmb.h"
1730
+ .file 15 "include/asm-generic/u-boot.h"
1731
+ .file 16 "./arch/arm/include/asm/u-boot-arm.h"
1732
+ .file 17 "include/linux/libfdt_env.h"
1733
+ .file 18 "include/linux/../../scripts/dtc/libfdt/fdt.h"
1734
+ .file 19 "include/linux/libfdt.h"
1735
+ .file 20 "include/image.h"
1736
+ .file 21 "./arch/arm/include/asm/global_data.h"
1737
+ .file 22 "include/asm-generic/global_data.h"
1738
+ .file 23 "include/net.h"
1739
+ .file 24 "include/dm/uclass-id.h"
1740
+ .file 25 "./arch/arm/include/asm/spl.h"
1741
+ .file 26 "include/spl.h"
1742
+ .file 27 "include/mp_boot.h"
1743
+ .file 28 "include/log.h"
1744
+ .file 29 "include/stdio.h"
1745
+ .section .debug_info,"",@progbits
1746
+.Ldebug_info0:
1747
+ .4byte 0x2374
1748
+ .2byte 0x4
1749
+ .4byte .Ldebug_abbrev0
1750
+ .byte 0x8
1751
+ .uleb128 0x1
1752
+ .4byte .LASF428
1753
+ .byte 0xc
1754
+ .4byte .LASF429
1755
+ .4byte .LASF430
1756
+ .4byte .Ldebug_ranges0+0x230
1757
+ .8byte 0
1758
+ .4byte .Ldebug_line0
1759
+ .uleb128 0x2
1760
+ .4byte .LASF4
1761
+ .byte 0x4
1762
+ .byte 0xd
1763
+ .4byte 0x34
1764
+ .uleb128 0x3
1765
+ .byte 0x1
1766
+ .byte 0x8
1767
+ .4byte .LASF0
1768
+ .uleb128 0x3
1769
+ .byte 0x8
1770
+ .byte 0x7
1771
+ .4byte .LASF1
1772
+ .uleb128 0x3
1773
+ .byte 0x2
1774
+ .byte 0x7
1775
+ .4byte .LASF2
1776
+ .uleb128 0x4
1777
+ .4byte .LASF20
1778
+ .byte 0x7
1779
+ .byte 0xc
1780
+ .4byte 0x54
1781
+ .uleb128 0x5
1782
+ .byte 0x4
1783
+ .byte 0x5
1784
+ .string "int"
1785
+ .uleb128 0x3
1786
+ .byte 0x1
1787
+ .byte 0x6
1788
+ .4byte .LASF3
1789
+ .uleb128 0x2
1790
+ .4byte .LASF5
1791
+ .byte 0x5
1792
+ .byte 0xc
1793
+ .4byte 0x34
1794
+ .uleb128 0x3
1795
+ .byte 0x2
1796
+ .byte 0x5
1797
+ .4byte .LASF6
1798
+ .uleb128 0x2
1799
+ .4byte .LASF7
1800
+ .byte 0x5
1801
+ .byte 0x12
1802
+ .4byte 0x7f
1803
+ .uleb128 0x3
1804
+ .byte 0x4
1805
+ .byte 0x7
1806
+ .4byte .LASF8
1807
+ .uleb128 0x3
1808
+ .byte 0x8
1809
+ .byte 0x5
1810
+ .4byte .LASF9
1811
+ .uleb128 0x3
1812
+ .byte 0x8
1813
+ .byte 0x7
1814
+ .4byte .LASF10
1815
+ .uleb128 0x6
1816
+ .string "u8"
1817
+ .byte 0x5
1818
+ .byte 0x1f
1819
+ .4byte 0x34
1820
+ .uleb128 0x7
1821
+ .4byte 0x94
1822
+ .uleb128 0x6
1823
+ .string "u32"
1824
+ .byte 0x5
1825
+ .byte 0x25
1826
+ .4byte 0x7f
1827
+ .uleb128 0x6
1828
+ .string "u64"
1829
+ .byte 0x5
1830
+ .byte 0x28
1831
+ .4byte 0x8d
1832
+ .uleb128 0x2
1833
+ .4byte .LASF11
1834
+ .byte 0x5
1835
+ .byte 0x31
1836
+ .4byte 0x8d
1837
+ .uleb128 0x2
1838
+ .4byte .LASF12
1839
+ .byte 0x5
1840
+ .byte 0x32
1841
+ .4byte 0x8d
1842
+ .uleb128 0x3
1843
+ .byte 0x8
1844
+ .byte 0x7
1845
+ .4byte .LASF13
1846
+ .uleb128 0x8
1847
+ .byte 0x8
1848
+ .4byte 0xe3
1849
+ .uleb128 0x3
1850
+ .byte 0x1
1851
+ .byte 0x8
1852
+ .4byte .LASF14
1853
+ .uleb128 0x7
1854
+ .4byte 0xdc
1855
+ .uleb128 0x3
1856
+ .byte 0x8
1857
+ .byte 0x5
1858
+ .4byte .LASF15
1859
+ .uleb128 0x8
1860
+ .byte 0x8
1861
+ .4byte 0xdc
1862
+ .uleb128 0x2
1863
+ .4byte .LASF16
1864
+ .byte 0x6
1865
+ .byte 0x59
1866
+ .4byte 0x42
1867
+ .uleb128 0x2
1868
+ .4byte .LASF17
1869
+ .byte 0x6
1870
+ .byte 0x5b
1871
+ .4byte 0x3b
1872
+ .uleb128 0x9
1873
+ .4byte 0x100
1874
+ .uleb128 0x2
1875
+ .4byte .LASF18
1876
+ .byte 0x6
1877
+ .byte 0x69
1878
+ .4byte 0x62
1879
+ .uleb128 0x2
1880
+ .4byte .LASF19
1881
+ .byte 0x6
1882
+ .byte 0x97
1883
+ .4byte 0x74
1884
+ .uleb128 0xa
1885
+ .byte 0x8
1886
+ .uleb128 0x4
1887
+ .4byte .LASF21
1888
+ .byte 0x8
1889
+ .byte 0xb
1890
+ .4byte 0xef
1891
+ .uleb128 0x3
1892
+ .byte 0x1
1893
+ .byte 0x2
1894
+ .4byte .LASF22
1895
+ .uleb128 0xb
1896
+ .4byte 0xdc
1897
+ .4byte 0x145
1898
+ .uleb128 0xc
1899
+ .byte 0
1900
+ .uleb128 0xd
1901
+ .4byte .LASF23
1902
+ .byte 0x9
1903
+ .2byte 0x140
1904
+ .4byte 0x13a
1905
+ .uleb128 0xd
1906
+ .4byte .LASF24
1907
+ .byte 0x9
1908
+ .2byte 0x143
1909
+ .4byte 0x13a
1910
+ .uleb128 0xd
1911
+ .4byte .LASF25
1912
+ .byte 0x9
1913
+ .2byte 0x143
1914
+ .4byte 0x13a
1915
+ .uleb128 0xe
1916
+ .4byte .LASF38
1917
+ .uleb128 0x8
1918
+ .byte 0x8
1919
+ .4byte 0x169
1920
+ .uleb128 0x8
1921
+ .byte 0x8
1922
+ .4byte 0x17a
1923
+ .uleb128 0xf
1924
+ .uleb128 0xb
1925
+ .4byte 0x100
1926
+ .4byte 0x186
1927
+ .uleb128 0xc
1928
+ .byte 0
1929
+ .uleb128 0x4
1930
+ .4byte .LASF26
1931
+ .byte 0xa
1932
+ .byte 0x10
1933
+ .4byte 0x17b
1934
+ .uleb128 0xb
1935
+ .4byte 0x34
1936
+ .4byte 0x1a1
1937
+ .uleb128 0x10
1938
+ .4byte 0xcf
1939
+ .byte 0x5
1940
+ .byte 0
1941
+ .uleb128 0x11
1942
+ .4byte .LASF29
1943
+ .byte 0x10
1944
+ .byte 0xb
1945
+ .byte 0x16
1946
+ .4byte 0x1c6
1947
+ .uleb128 0x12
1948
+ .4byte .LASF27
1949
+ .byte 0xb
1950
+ .byte 0x17
1951
+ .4byte 0x1c6
1952
+ .byte 0
1953
+ .uleb128 0x12
1954
+ .4byte .LASF28
1955
+ .byte 0xb
1956
+ .byte 0x17
1957
+ .4byte 0x1c6
1958
+ .byte 0x8
1959
+ .byte 0
1960
+ .uleb128 0x8
1961
+ .byte 0x8
1962
+ .4byte 0x1a1
1963
+ .uleb128 0x11
1964
+ .4byte .LASF30
1965
+ .byte 0x10
1966
+ .byte 0xc
1967
+ .byte 0xf
1968
+ .4byte 0x1f1
1969
+ .uleb128 0x12
1970
+ .4byte .LASF31
1971
+ .byte 0xc
1972
+ .byte 0x10
1973
+ .4byte 0xef
1974
+ .byte 0
1975
+ .uleb128 0x12
1976
+ .4byte .LASF32
1977
+ .byte 0xc
1978
+ .byte 0x11
1979
+ .4byte 0x20a
1980
+ .byte 0x8
1981
+ .byte 0
1982
+ .uleb128 0x7
1983
+ .4byte 0x1cc
1984
+ .uleb128 0x13
1985
+ .4byte 0x54
1986
+ .4byte 0x20a
1987
+ .uleb128 0x14
1988
+ .4byte 0x54
1989
+ .uleb128 0x14
1990
+ .4byte 0x54
1991
+ .byte 0
1992
+ .uleb128 0x8
1993
+ .byte 0x8
1994
+ .4byte 0x1f6
1995
+ .uleb128 0xb
1996
+ .4byte 0x1f1
1997
+ .4byte 0x21b
1998
+ .uleb128 0xc
1999
+ .byte 0
2000
+ .uleb128 0x7
2001
+ .4byte 0x210
2002
+ .uleb128 0x4
2003
+ .4byte .LASF30
2004
+ .byte 0xc
2005
+ .byte 0xe1
2006
+ .4byte 0x21b
2007
+ .uleb128 0x15
2008
+ .2byte 0x1220
2009
+ .byte 0xd
2010
+ .byte 0x13
2011
+ .4byte 0x27f
2012
+ .uleb128 0x12
2013
+ .4byte .LASF33
2014
+ .byte 0xd
2015
+ .byte 0x14
2016
+ .4byte 0x100
2017
+ .byte 0
2018
+ .uleb128 0x12
2019
+ .4byte .LASF34
2020
+ .byte 0xd
2021
+ .byte 0x15
2022
+ .4byte 0xf5
2023
+ .byte 0x8
2024
+ .uleb128 0x12
2025
+ .4byte .LASF35
2026
+ .byte 0xd
2027
+ .byte 0x16
2028
+ .4byte 0x100
2029
+ .byte 0x10
2030
+ .uleb128 0x12
2031
+ .4byte .LASF36
2032
+ .byte 0xd
2033
+ .byte 0x17
2034
+ .4byte 0x27f
2035
+ .byte 0x18
2036
+ .uleb128 0x16
2037
+ .4byte .LASF37
2038
+ .byte 0xd
2039
+ .byte 0x18
2040
+ .4byte 0x290
2041
+ .2byte 0x1018
2042
+ .uleb128 0x17
2043
+ .string "mtd"
2044
+ .byte 0xd
2045
+ .byte 0x31
2046
+ .4byte 0x2a6
2047
+ .2byte 0x1218
2048
+ .byte 0
2049
+ .uleb128 0xb
2050
+ .4byte 0x100
2051
+ .4byte 0x290
2052
+ .uleb128 0x18
2053
+ .4byte 0xcf
2054
+ .2byte 0x1ff
2055
+ .byte 0
2056
+ .uleb128 0xb
2057
+ .4byte 0x29
2058
+ .4byte 0x2a1
2059
+ .uleb128 0x18
2060
+ .4byte 0xcf
2061
+ .2byte 0x1ff
2062
+ .byte 0
2063
+ .uleb128 0xe
2064
+ .4byte .LASF39
2065
+ .uleb128 0x8
2066
+ .byte 0x8
2067
+ .4byte 0x2a1
2068
+ .uleb128 0x2
2069
+ .4byte .LASF40
2070
+ .byte 0xd
2071
+ .byte 0x37
2072
+ .4byte 0x22b
2073
+ .uleb128 0xb
2074
+ .4byte 0x2ac
2075
+ .4byte 0x2c2
2076
+ .uleb128 0xc
2077
+ .byte 0
2078
+ .uleb128 0x4
2079
+ .4byte .LASF41
2080
+ .byte 0xd
2081
+ .byte 0x39
2082
+ .4byte 0x2b7
2083
+ .uleb128 0x3
2084
+ .byte 0x10
2085
+ .byte 0x4
2086
+ .4byte .LASF42
2087
+ .uleb128 0x11
2088
+ .4byte .LASF43
2089
+ .byte 0x10
2090
+ .byte 0xe
2091
+ .byte 0x10
2092
+ .4byte 0x2f9
2093
+ .uleb128 0x12
2094
+ .4byte .LASF44
2095
+ .byte 0xe
2096
+ .byte 0x11
2097
+ .4byte 0xb9
2098
+ .byte 0
2099
+ .uleb128 0x12
2100
+ .4byte .LASF33
2101
+ .byte 0xe
2102
+ .byte 0x12
2103
+ .4byte 0xc4
2104
+ .byte 0x8
2105
+ .byte 0
2106
+ .uleb128 0x19
2107
+ .4byte .LASF45
2108
+ .2byte 0x120
2109
+ .byte 0xe
2110
+ .byte 0x15
2111
+ .4byte 0x32b
2112
+ .uleb128 0x1a
2113
+ .string "cnt"
2114
+ .byte 0xe
2115
+ .byte 0x16
2116
+ .4byte 0x3b
2117
+ .byte 0
2118
+ .uleb128 0x12
2119
+ .4byte .LASF33
2120
+ .byte 0xe
2121
+ .byte 0x17
2122
+ .4byte 0xc4
2123
+ .byte 0x8
2124
+ .uleb128 0x12
2125
+ .4byte .LASF46
2126
+ .byte 0xe
2127
+ .byte 0x18
2128
+ .4byte 0x32b
2129
+ .byte 0x10
2130
+ .byte 0
2131
+ .uleb128 0xb
2132
+ .4byte 0x2d4
2133
+ .4byte 0x33b
2134
+ .uleb128 0x10
2135
+ .4byte 0xcf
2136
+ .byte 0x10
2137
+ .byte 0
2138
+ .uleb128 0x1b
2139
+ .string "lmb"
2140
+ .2byte 0x240
2141
+ .byte 0xe
2142
+ .byte 0x1b
2143
+ .4byte 0x362
2144
+ .uleb128 0x12
2145
+ .4byte .LASF47
2146
+ .byte 0xe
2147
+ .byte 0x1c
2148
+ .4byte 0x2f9
2149
+ .byte 0
2150
+ .uleb128 0x16
2151
+ .4byte .LASF48
2152
+ .byte 0xe
2153
+ .byte 0x1d
2154
+ .4byte 0x2f9
2155
+ .2byte 0x120
2156
+ .byte 0
2157
+ .uleb128 0x1c
2158
+ .string "lmb"
2159
+ .byte 0xe
2160
+ .byte 0x20
2161
+ .4byte 0x33b
2162
+ .uleb128 0x1d
2163
+ .byte 0x10
2164
+ .byte 0xf
2165
+ .byte 0x5b
2166
+ .4byte 0x38e
2167
+ .uleb128 0x12
2168
+ .4byte .LASF36
2169
+ .byte 0xf
2170
+ .byte 0x5c
2171
+ .4byte 0xae
2172
+ .byte 0
2173
+ .uleb128 0x12
2174
+ .4byte .LASF33
2175
+ .byte 0xf
2176
+ .byte 0x5d
2177
+ .4byte 0xae
2178
+ .byte 0x8
2179
+ .byte 0
2180
+ .uleb128 0x11
2181
+ .4byte .LASF49
2182
+ .byte 0xa8
2183
+ .byte 0xf
2184
+ .byte 0x1b
2185
+ .4byte 0x47f
2186
+ .uleb128 0x12
2187
+ .4byte .LASF50
2188
+ .byte 0xf
2189
+ .byte 0x1c
2190
+ .4byte 0x3b
2191
+ .byte 0
2192
+ .uleb128 0x12
2193
+ .4byte .LASF51
2194
+ .byte 0xf
2195
+ .byte 0x1d
2196
+ .4byte 0xc4
2197
+ .byte 0x8
2198
+ .uleb128 0x12
2199
+ .4byte .LASF52
2200
+ .byte 0xf
2201
+ .byte 0x1e
2202
+ .4byte 0x3b
2203
+ .byte 0x10
2204
+ .uleb128 0x12
2205
+ .4byte .LASF53
2206
+ .byte 0xf
2207
+ .byte 0x1f
2208
+ .4byte 0x3b
2209
+ .byte 0x18
2210
+ .uleb128 0x12
2211
+ .4byte .LASF54
2212
+ .byte 0xf
2213
+ .byte 0x20
2214
+ .4byte 0x3b
2215
+ .byte 0x20
2216
+ .uleb128 0x12
2217
+ .4byte .LASF55
2218
+ .byte 0xf
2219
+ .byte 0x21
2220
+ .4byte 0x3b
2221
+ .byte 0x28
2222
+ .uleb128 0x12
2223
+ .4byte .LASF56
2224
+ .byte 0xf
2225
+ .byte 0x22
2226
+ .4byte 0x3b
2227
+ .byte 0x30
2228
+ .uleb128 0x12
2229
+ .4byte .LASF57
2230
+ .byte 0xf
2231
+ .byte 0x24
2232
+ .4byte 0x3b
2233
+ .byte 0x38
2234
+ .uleb128 0x12
2235
+ .4byte .LASF58
2236
+ .byte 0xf
2237
+ .byte 0x25
2238
+ .4byte 0x3b
2239
+ .byte 0x40
2240
+ .uleb128 0x12
2241
+ .4byte .LASF59
2242
+ .byte 0xf
2243
+ .byte 0x26
2244
+ .4byte 0x3b
2245
+ .byte 0x48
2246
+ .uleb128 0x12
2247
+ .4byte .LASF60
2248
+ .byte 0xf
2249
+ .byte 0x31
2250
+ .4byte 0x3b
2251
+ .byte 0x50
2252
+ .uleb128 0x12
2253
+ .4byte .LASF61
2254
+ .byte 0xf
2255
+ .byte 0x32
2256
+ .4byte 0x3b
2257
+ .byte 0x58
2258
+ .uleb128 0x12
2259
+ .4byte .LASF62
2260
+ .byte 0xf
2261
+ .byte 0x33
2262
+ .4byte 0x191
2263
+ .byte 0x60
2264
+ .uleb128 0x12
2265
+ .4byte .LASF63
2266
+ .byte 0xf
2267
+ .byte 0x34
2268
+ .4byte 0x42
2269
+ .byte 0x66
2270
+ .uleb128 0x12
2271
+ .4byte .LASF64
2272
+ .byte 0xf
2273
+ .byte 0x35
2274
+ .4byte 0x3b
2275
+ .byte 0x68
2276
+ .uleb128 0x12
2277
+ .4byte .LASF65
2278
+ .byte 0xf
2279
+ .byte 0x36
2280
+ .4byte 0x3b
2281
+ .byte 0x70
2282
+ .uleb128 0x12
2283
+ .4byte .LASF66
2284
+ .byte 0xf
2285
+ .byte 0x57
2286
+ .4byte 0x100
2287
+ .byte 0x78
2288
+ .uleb128 0x12
2289
+ .4byte .LASF67
2290
+ .byte 0xf
2291
+ .byte 0x58
2292
+ .4byte 0x100
2293
+ .byte 0x80
2294
+ .uleb128 0x12
2295
+ .4byte .LASF68
2296
+ .byte 0xf
2297
+ .byte 0x5e
2298
+ .4byte 0x47f
2299
+ .byte 0x88
2300
+ .byte 0
2301
+ .uleb128 0xb
2302
+ .4byte 0x36d
2303
+ .4byte 0x48f
2304
+ .uleb128 0x10
2305
+ .4byte 0xcf
2306
+ .byte 0x1
2307
+ .byte 0
2308
+ .uleb128 0x2
2309
+ .4byte .LASF69
2310
+ .byte 0xf
2311
+ .byte 0x60
2312
+ .4byte 0x38e
2313
+ .uleb128 0x4
2314
+ .4byte .LASF70
2315
+ .byte 0x10
2316
+ .byte 0x13
2317
+ .4byte 0x100
2318
+ .uleb128 0x4
2319
+ .4byte .LASF71
2320
+ .byte 0x10
2321
+ .byte 0x14
2322
+ .4byte 0x100
2323
+ .uleb128 0x4
2324
+ .4byte .LASF72
2325
+ .byte 0x10
2326
+ .byte 0x15
2327
+ .4byte 0x100
2328
+ .uleb128 0x4
2329
+ .4byte .LASF73
2330
+ .byte 0x10
2331
+ .byte 0x16
2332
+ .4byte 0x100
2333
+ .uleb128 0x4
2334
+ .4byte .LASF74
2335
+ .byte 0x10
2336
+ .byte 0x17
2337
+ .4byte 0x100
2338
+ .uleb128 0x4
2339
+ .4byte .LASF75
2340
+ .byte 0x10
2341
+ .byte 0x18
2342
+ .4byte 0x100
2343
+ .uleb128 0x4
2344
+ .4byte .LASF76
2345
+ .byte 0x10
2346
+ .byte 0x19
2347
+ .4byte 0x100
2348
+ .uleb128 0x2
2349
+ .4byte .LASF77
2350
+ .byte 0x11
2351
+ .byte 0x11
2352
+ .4byte 0x11b
2353
+ .uleb128 0x11
2354
+ .4byte .LASF78
2355
+ .byte 0x28
2356
+ .byte 0x12
2357
+ .byte 0x39
2358
+ .4byte 0x577
2359
+ .uleb128 0x12
2360
+ .4byte .LASF79
2361
+ .byte 0x12
2362
+ .byte 0x3a
2363
+ .4byte 0x4e7
2364
+ .byte 0
2365
+ .uleb128 0x12
2366
+ .4byte .LASF80
2367
+ .byte 0x12
2368
+ .byte 0x3b
2369
+ .4byte 0x4e7
2370
+ .byte 0x4
2371
+ .uleb128 0x12
2372
+ .4byte .LASF81
2373
+ .byte 0x12
2374
+ .byte 0x3c
2375
+ .4byte 0x4e7
2376
+ .byte 0x8
2377
+ .uleb128 0x12
2378
+ .4byte .LASF82
2379
+ .byte 0x12
2380
+ .byte 0x3d
2381
+ .4byte 0x4e7
2382
+ .byte 0xc
2383
+ .uleb128 0x12
2384
+ .4byte .LASF83
2385
+ .byte 0x12
2386
+ .byte 0x3e
2387
+ .4byte 0x4e7
2388
+ .byte 0x10
2389
+ .uleb128 0x12
2390
+ .4byte .LASF84
2391
+ .byte 0x12
2392
+ .byte 0x3f
2393
+ .4byte 0x4e7
2394
+ .byte 0x14
2395
+ .uleb128 0x12
2396
+ .4byte .LASF85
2397
+ .byte 0x12
2398
+ .byte 0x40
2399
+ .4byte 0x4e7
2400
+ .byte 0x18
2401
+ .uleb128 0x12
2402
+ .4byte .LASF86
2403
+ .byte 0x12
2404
+ .byte 0x43
2405
+ .4byte 0x4e7
2406
+ .byte 0x1c
2407
+ .uleb128 0x12
2408
+ .4byte .LASF87
2409
+ .byte 0x12
2410
+ .byte 0x46
2411
+ .4byte 0x4e7
2412
+ .byte 0x20
2413
+ .uleb128 0x12
2414
+ .4byte .LASF88
2415
+ .byte 0x12
2416
+ .byte 0x49
2417
+ .4byte 0x4e7
2418
+ .byte 0x24
2419
+ .byte 0
2420
+ .uleb128 0xd
2421
+ .4byte .LASF89
2422
+ .byte 0x13
2423
+ .2byte 0x136
2424
+ .4byte 0x583
2425
+ .uleb128 0x8
2426
+ .byte 0x8
2427
+ .4byte 0x4f2
2428
+ .uleb128 0x1e
2429
+ .4byte .LASF90
2430
+ .byte 0x40
2431
+ .byte 0x14
2432
+ .2byte 0x137
2433
+ .4byte 0x633
2434
+ .uleb128 0x1f
2435
+ .4byte .LASF91
2436
+ .byte 0x14
2437
+ .2byte 0x138
2438
+ .4byte 0x11b
2439
+ .byte 0
2440
+ .uleb128 0x1f
2441
+ .4byte .LASF92
2442
+ .byte 0x14
2443
+ .2byte 0x139
2444
+ .4byte 0x11b
2445
+ .byte 0x4
2446
+ .uleb128 0x1f
2447
+ .4byte .LASF93
2448
+ .byte 0x14
2449
+ .2byte 0x13a
2450
+ .4byte 0x11b
2451
+ .byte 0x8
2452
+ .uleb128 0x1f
2453
+ .4byte .LASF94
2454
+ .byte 0x14
2455
+ .2byte 0x13b
2456
+ .4byte 0x11b
2457
+ .byte 0xc
2458
+ .uleb128 0x1f
2459
+ .4byte .LASF95
2460
+ .byte 0x14
2461
+ .2byte 0x13c
2462
+ .4byte 0x11b
2463
+ .byte 0x10
2464
+ .uleb128 0x1f
2465
+ .4byte .LASF96
2466
+ .byte 0x14
2467
+ .2byte 0x13d
2468
+ .4byte 0x11b
2469
+ .byte 0x14
2470
+ .uleb128 0x1f
2471
+ .4byte .LASF97
2472
+ .byte 0x14
2473
+ .2byte 0x13e
2474
+ .4byte 0x11b
2475
+ .byte 0x18
2476
+ .uleb128 0x1f
2477
+ .4byte .LASF98
2478
+ .byte 0x14
2479
+ .2byte 0x13f
2480
+ .4byte 0x110
2481
+ .byte 0x1c
2482
+ .uleb128 0x1f
2483
+ .4byte .LASF99
2484
+ .byte 0x14
2485
+ .2byte 0x140
2486
+ .4byte 0x110
2487
+ .byte 0x1d
2488
+ .uleb128 0x1f
2489
+ .4byte .LASF100
2490
+ .byte 0x14
2491
+ .2byte 0x141
2492
+ .4byte 0x110
2493
+ .byte 0x1e
2494
+ .uleb128 0x1f
2495
+ .4byte .LASF101
2496
+ .byte 0x14
2497
+ .2byte 0x142
2498
+ .4byte 0x110
2499
+ .byte 0x1f
2500
+ .uleb128 0x1f
2501
+ .4byte .LASF102
2502
+ .byte 0x14
2503
+ .2byte 0x143
2504
+ .4byte 0x633
2505
+ .byte 0x20
2506
+ .byte 0
2507
+ .uleb128 0xb
2508
+ .4byte 0x110
2509
+ .4byte 0x643
2510
+ .uleb128 0x10
2511
+ .4byte 0xcf
2512
+ .byte 0x1f
2513
+ .byte 0
2514
+ .uleb128 0x20
2515
+ .4byte .LASF103
2516
+ .byte 0x14
2517
+ .2byte 0x144
2518
+ .4byte 0x589
2519
+ .uleb128 0x1e
2520
+ .4byte .LASF104
2521
+ .byte 0x30
2522
+ .byte 0x14
2523
+ .2byte 0x146
2524
+ .4byte 0x6d1
2525
+ .uleb128 0x1f
2526
+ .4byte .LASF36
2527
+ .byte 0x14
2528
+ .2byte 0x147
2529
+ .4byte 0x100
2530
+ .byte 0
2531
+ .uleb128 0x21
2532
+ .string "end"
2533
+ .byte 0x14
2534
+ .2byte 0x147
2535
+ .4byte 0x100
2536
+ .byte 0x8
2537
+ .uleb128 0x1f
2538
+ .4byte .LASF105
2539
+ .byte 0x14
2540
+ .2byte 0x148
2541
+ .4byte 0x100
2542
+ .byte 0x10
2543
+ .uleb128 0x1f
2544
+ .4byte .LASF106
2545
+ .byte 0x14
2546
+ .2byte 0x148
2547
+ .4byte 0x100
2548
+ .byte 0x18
2549
+ .uleb128 0x1f
2550
+ .4byte .LASF107
2551
+ .byte 0x14
2552
+ .2byte 0x149
2553
+ .4byte 0x100
2554
+ .byte 0x20
2555
+ .uleb128 0x1f
2556
+ .4byte .LASF108
2557
+ .byte 0x14
2558
+ .2byte 0x14a
2559
+ .4byte 0x110
2560
+ .byte 0x28
2561
+ .uleb128 0x1f
2562
+ .4byte .LASF109
2563
+ .byte 0x14
2564
+ .2byte 0x14a
2565
+ .4byte 0x110
2566
+ .byte 0x29
2567
+ .uleb128 0x21
2568
+ .string "os"
2569
+ .byte 0x14
2570
+ .2byte 0x14a
2571
+ .4byte 0x110
2572
+ .byte 0x2a
2573
+ .uleb128 0x1f
2574
+ .4byte .LASF110
2575
+ .byte 0x14
2576
+ .2byte 0x14b
2577
+ .4byte 0x110
2578
+ .byte 0x2b
2579
+ .byte 0
2580
+ .uleb128 0x20
2581
+ .4byte .LASF111
2582
+ .byte 0x14
2583
+ .2byte 0x14c
2584
+ .4byte 0x64f
2585
+ .uleb128 0x22
2586
+ .4byte .LASF112
2587
+ .2byte 0x380
2588
+ .byte 0x14
2589
+ .2byte 0x152
2590
+ .4byte 0x87a
2591
+ .uleb128 0x1f
2592
+ .4byte .LASF113
2593
+ .byte 0x14
2594
+ .2byte 0x158
2595
+ .4byte 0x87a
2596
+ .byte 0
2597
+ .uleb128 0x1f
2598
+ .4byte .LASF114
2599
+ .byte 0x14
2600
+ .2byte 0x159
2601
+ .4byte 0x643
2602
+ .byte 0x8
2603
+ .uleb128 0x1f
2604
+ .4byte .LASF115
2605
+ .byte 0x14
2606
+ .2byte 0x15a
2607
+ .4byte 0x100
2608
+ .byte 0x48
2609
+ .uleb128 0x1f
2610
+ .4byte .LASF116
2611
+ .byte 0x14
2612
+ .2byte 0x15d
2613
+ .4byte 0xd6
2614
+ .byte 0x50
2615
+ .uleb128 0x1f
2616
+ .4byte .LASF117
2617
+ .byte 0x14
2618
+ .2byte 0x15f
2619
+ .4byte 0x126
2620
+ .byte 0x58
2621
+ .uleb128 0x1f
2622
+ .4byte .LASF118
2623
+ .byte 0x14
2624
+ .2byte 0x160
2625
+ .4byte 0xd6
2626
+ .byte 0x60
2627
+ .uleb128 0x1f
2628
+ .4byte .LASF119
2629
+ .byte 0x14
2630
+ .2byte 0x161
2631
+ .4byte 0x54
2632
+ .byte 0x68
2633
+ .uleb128 0x1f
2634
+ .4byte .LASF120
2635
+ .byte 0x14
2636
+ .2byte 0x163
2637
+ .4byte 0x126
2638
+ .byte 0x70
2639
+ .uleb128 0x1f
2640
+ .4byte .LASF121
2641
+ .byte 0x14
2642
+ .2byte 0x164
2643
+ .4byte 0xd6
2644
+ .byte 0x78
2645
+ .uleb128 0x1f
2646
+ .4byte .LASF122
2647
+ .byte 0x14
2648
+ .2byte 0x165
2649
+ .4byte 0x54
2650
+ .byte 0x80
2651
+ .uleb128 0x1f
2652
+ .4byte .LASF123
2653
+ .byte 0x14
2654
+ .2byte 0x167
2655
+ .4byte 0x126
2656
+ .byte 0x88
2657
+ .uleb128 0x1f
2658
+ .4byte .LASF124
2659
+ .byte 0x14
2660
+ .2byte 0x168
2661
+ .4byte 0xd6
2662
+ .byte 0x90
2663
+ .uleb128 0x1f
2664
+ .4byte .LASF125
2665
+ .byte 0x14
2666
+ .2byte 0x169
2667
+ .4byte 0x54
2668
+ .byte 0x98
2669
+ .uleb128 0x1f
2670
+ .4byte .LASF126
2671
+ .byte 0x14
2672
+ .2byte 0x16b
2673
+ .4byte 0x126
2674
+ .byte 0xa0
2675
+ .uleb128 0x1f
2676
+ .4byte .LASF127
2677
+ .byte 0x14
2678
+ .2byte 0x16c
2679
+ .4byte 0xd6
2680
+ .byte 0xa8
2681
+ .uleb128 0x1f
2682
+ .4byte .LASF128
2683
+ .byte 0x14
2684
+ .2byte 0x16d
2685
+ .4byte 0x54
2686
+ .byte 0xb0
2687
+ .uleb128 0x21
2688
+ .string "os"
2689
+ .byte 0x14
2690
+ .2byte 0x171
2691
+ .4byte 0x6d1
2692
+ .byte 0xb8
2693
+ .uleb128 0x21
2694
+ .string "ep"
2695
+ .byte 0x14
2696
+ .2byte 0x172
2697
+ .4byte 0x100
2698
+ .byte 0xe8
2699
+ .uleb128 0x1f
2700
+ .4byte .LASF129
2701
+ .byte 0x14
2702
+ .2byte 0x174
2703
+ .4byte 0x100
2704
+ .byte 0xf0
2705
+ .uleb128 0x1f
2706
+ .4byte .LASF130
2707
+ .byte 0x14
2708
+ .2byte 0x174
2709
+ .4byte 0x100
2710
+ .byte 0xf8
2711
+ .uleb128 0x23
2712
+ .4byte .LASF131
2713
+ .byte 0x14
2714
+ .2byte 0x176
2715
+ .4byte 0xef
2716
+ .2byte 0x100
2717
+ .uleb128 0x23
2718
+ .4byte .LASF132
2719
+ .byte 0x14
2720
+ .2byte 0x177
2721
+ .4byte 0x100
2722
+ .2byte 0x108
2723
+ .uleb128 0x23
2724
+ .4byte .LASF133
2725
+ .byte 0x14
2726
+ .2byte 0x179
2727
+ .4byte 0x100
2728
+ .2byte 0x110
2729
+ .uleb128 0x23
2730
+ .4byte .LASF134
2731
+ .byte 0x14
2732
+ .2byte 0x17a
2733
+ .4byte 0x100
2734
+ .2byte 0x118
2735
+ .uleb128 0x23
2736
+ .4byte .LASF135
2737
+ .byte 0x14
2738
+ .2byte 0x17b
2739
+ .4byte 0x100
2740
+ .2byte 0x120
2741
+ .uleb128 0x23
2742
+ .4byte .LASF136
2743
+ .byte 0x14
2744
+ .2byte 0x17c
2745
+ .4byte 0x100
2746
+ .2byte 0x128
2747
+ .uleb128 0x24
2748
+ .string "kbd"
2749
+ .byte 0x14
2750
+ .2byte 0x17d
2751
+ .4byte 0x880
2752
+ .2byte 0x130
2753
+ .uleb128 0x23
2754
+ .4byte .LASF137
2755
+ .byte 0x14
2756
+ .2byte 0x180
2757
+ .4byte 0x54
2758
+ .2byte 0x138
2759
+ .uleb128 0x23
2760
+ .4byte .LASF138
2761
+ .byte 0x14
2762
+ .2byte 0x18d
2763
+ .4byte 0x54
2764
+ .2byte 0x13c
2765
+ .uleb128 0x24
2766
+ .string "lmb"
2767
+ .byte 0x14
2768
+ .2byte 0x190
2769
+ .4byte 0x33b
2770
+ .2byte 0x140
2771
+ .byte 0
2772
+ .uleb128 0x8
2773
+ .byte 0x8
2774
+ .4byte 0x643
2775
+ .uleb128 0x8
2776
+ .byte 0x8
2777
+ .4byte 0x48f
2778
+ .uleb128 0x20
2779
+ .4byte .LASF139
2780
+ .byte 0x14
2781
+ .2byte 0x196
2782
+ .4byte 0x6dd
2783
+ .uleb128 0xd
2784
+ .4byte .LASF140
2785
+ .byte 0x14
2786
+ .2byte 0x198
2787
+ .4byte 0x886
2788
+ .uleb128 0xb
2789
+ .4byte 0xdc
2790
+ .4byte 0x8af
2791
+ .uleb128 0x18
2792
+ .4byte 0xcf
2793
+ .2byte 0x3ff
2794
+ .byte 0
2795
+ .uleb128 0x25
2796
+ .4byte .LASF331
2797
+ .byte 0x4
2798
+ .4byte 0x54
2799
+ .byte 0x18
2800
+ .byte 0xe
2801
+ .4byte 0xb18
2802
+ .uleb128 0x26
2803
+ .4byte .LASF141
2804
+ .byte 0
2805
+ .uleb128 0x26
2806
+ .4byte .LASF142
2807
+ .byte 0x1
2808
+ .uleb128 0x26
2809
+ .4byte .LASF143
2810
+ .byte 0x2
2811
+ .uleb128 0x26
2812
+ .4byte .LASF144
2813
+ .byte 0x3
2814
+ .uleb128 0x26
2815
+ .4byte .LASF145
2816
+ .byte 0x4
2817
+ .uleb128 0x26
2818
+ .4byte .LASF146
2819
+ .byte 0x5
2820
+ .uleb128 0x26
2821
+ .4byte .LASF147
2822
+ .byte 0x6
2823
+ .uleb128 0x26
2824
+ .4byte .LASF148
2825
+ .byte 0x7
2826
+ .uleb128 0x26
2827
+ .4byte .LASF149
2828
+ .byte 0x8
2829
+ .uleb128 0x26
2830
+ .4byte .LASF150
2831
+ .byte 0x9
2832
+ .uleb128 0x26
2833
+ .4byte .LASF151
2834
+ .byte 0xa
2835
+ .uleb128 0x26
2836
+ .4byte .LASF152
2837
+ .byte 0xb
2838
+ .uleb128 0x26
2839
+ .4byte .LASF153
2840
+ .byte 0xc
2841
+ .uleb128 0x26
2842
+ .4byte .LASF154
2843
+ .byte 0xd
2844
+ .uleb128 0x26
2845
+ .4byte .LASF155
2846
+ .byte 0xe
2847
+ .uleb128 0x26
2848
+ .4byte .LASF156
2849
+ .byte 0xf
2850
+ .uleb128 0x26
2851
+ .4byte .LASF157
2852
+ .byte 0x10
2853
+ .uleb128 0x26
2854
+ .4byte .LASF158
2855
+ .byte 0x11
2856
+ .uleb128 0x26
2857
+ .4byte .LASF159
2858
+ .byte 0x12
2859
+ .uleb128 0x26
2860
+ .4byte .LASF160
2861
+ .byte 0x13
2862
+ .uleb128 0x26
2863
+ .4byte .LASF161
2864
+ .byte 0x14
2865
+ .uleb128 0x26
2866
+ .4byte .LASF162
2867
+ .byte 0x15
2868
+ .uleb128 0x26
2869
+ .4byte .LASF163
2870
+ .byte 0x16
2871
+ .uleb128 0x26
2872
+ .4byte .LASF164
2873
+ .byte 0x17
2874
+ .uleb128 0x26
2875
+ .4byte .LASF165
2876
+ .byte 0x18
2877
+ .uleb128 0x26
2878
+ .4byte .LASF166
2879
+ .byte 0x19
2880
+ .uleb128 0x26
2881
+ .4byte .LASF167
2882
+ .byte 0x1a
2883
+ .uleb128 0x26
2884
+ .4byte .LASF168
2885
+ .byte 0x1b
2886
+ .uleb128 0x26
2887
+ .4byte .LASF169
2888
+ .byte 0x1c
2889
+ .uleb128 0x26
2890
+ .4byte .LASF170
2891
+ .byte 0x1d
2892
+ .uleb128 0x26
2893
+ .4byte .LASF171
2894
+ .byte 0x1e
2895
+ .uleb128 0x26
2896
+ .4byte .LASF172
2897
+ .byte 0x1f
2898
+ .uleb128 0x26
2899
+ .4byte .LASF173
2900
+ .byte 0x20
2901
+ .uleb128 0x26
2902
+ .4byte .LASF174
2903
+ .byte 0x21
2904
+ .uleb128 0x26
2905
+ .4byte .LASF175
2906
+ .byte 0x22
2907
+ .uleb128 0x26
2908
+ .4byte .LASF176
2909
+ .byte 0x23
2910
+ .uleb128 0x26
2911
+ .4byte .LASF177
2912
+ .byte 0x24
2913
+ .uleb128 0x26
2914
+ .4byte .LASF178
2915
+ .byte 0x25
2916
+ .uleb128 0x26
2917
+ .4byte .LASF179
2918
+ .byte 0x26
2919
+ .uleb128 0x26
2920
+ .4byte .LASF180
2921
+ .byte 0x27
2922
+ .uleb128 0x26
2923
+ .4byte .LASF181
2924
+ .byte 0x28
2925
+ .uleb128 0x26
2926
+ .4byte .LASF182
2927
+ .byte 0x29
2928
+ .uleb128 0x26
2929
+ .4byte .LASF183
2930
+ .byte 0x2a
2931
+ .uleb128 0x26
2932
+ .4byte .LASF184
2933
+ .byte 0x2b
2934
+ .uleb128 0x26
2935
+ .4byte .LASF185
2936
+ .byte 0x2c
2937
+ .uleb128 0x26
2938
+ .4byte .LASF186
2939
+ .byte 0x2d
2940
+ .uleb128 0x26
2941
+ .4byte .LASF187
2942
+ .byte 0x2e
2943
+ .uleb128 0x26
2944
+ .4byte .LASF188
2945
+ .byte 0x2f
2946
+ .uleb128 0x26
2947
+ .4byte .LASF189
2948
+ .byte 0x30
2949
+ .uleb128 0x26
2950
+ .4byte .LASF190
2951
+ .byte 0x31
2952
+ .uleb128 0x26
2953
+ .4byte .LASF191
2954
+ .byte 0x32
2955
+ .uleb128 0x26
2956
+ .4byte .LASF192
2957
+ .byte 0x33
2958
+ .uleb128 0x26
2959
+ .4byte .LASF193
2960
+ .byte 0x34
2961
+ .uleb128 0x26
2962
+ .4byte .LASF194
2963
+ .byte 0x35
2964
+ .uleb128 0x26
2965
+ .4byte .LASF195
2966
+ .byte 0x36
2967
+ .uleb128 0x26
2968
+ .4byte .LASF196
2969
+ .byte 0x37
2970
+ .uleb128 0x26
2971
+ .4byte .LASF197
2972
+ .byte 0x38
2973
+ .uleb128 0x26
2974
+ .4byte .LASF198
2975
+ .byte 0x39
2976
+ .uleb128 0x26
2977
+ .4byte .LASF199
2978
+ .byte 0x3a
2979
+ .uleb128 0x26
2980
+ .4byte .LASF200
2981
+ .byte 0x3b
2982
+ .uleb128 0x26
2983
+ .4byte .LASF201
2984
+ .byte 0x3c
2985
+ .uleb128 0x26
2986
+ .4byte .LASF202
2987
+ .byte 0x3d
2988
+ .uleb128 0x26
2989
+ .4byte .LASF203
2990
+ .byte 0x3e
2991
+ .uleb128 0x26
2992
+ .4byte .LASF204
2993
+ .byte 0x3f
2994
+ .uleb128 0x26
2995
+ .4byte .LASF205
2996
+ .byte 0x40
2997
+ .uleb128 0x26
2998
+ .4byte .LASF206
2999
+ .byte 0x41
3000
+ .uleb128 0x26
3001
+ .4byte .LASF207
3002
+ .byte 0x42
3003
+ .uleb128 0x26
3004
+ .4byte .LASF208
3005
+ .byte 0x43
3006
+ .uleb128 0x26
3007
+ .4byte .LASF209
3008
+ .byte 0x44
3009
+ .uleb128 0x26
3010
+ .4byte .LASF210
3011
+ .byte 0x45
3012
+ .uleb128 0x26
3013
+ .4byte .LASF211
3014
+ .byte 0x46
3015
+ .uleb128 0x26
3016
+ .4byte .LASF212
3017
+ .byte 0x47
3018
+ .uleb128 0x26
3019
+ .4byte .LASF213
3020
+ .byte 0x48
3021
+ .uleb128 0x26
3022
+ .4byte .LASF214
3023
+ .byte 0x49
3024
+ .uleb128 0x26
3025
+ .4byte .LASF215
3026
+ .byte 0x4a
3027
+ .uleb128 0x26
3028
+ .4byte .LASF216
3029
+ .byte 0x4b
3030
+ .uleb128 0x26
3031
+ .4byte .LASF217
3032
+ .byte 0x4c
3033
+ .uleb128 0x26
3034
+ .4byte .LASF218
3035
+ .byte 0x4d
3036
+ .uleb128 0x26
3037
+ .4byte .LASF219
3038
+ .byte 0x4e
3039
+ .uleb128 0x26
3040
+ .4byte .LASF220
3041
+ .byte 0x4f
3042
+ .uleb128 0x26
3043
+ .4byte .LASF221
3044
+ .byte 0x50
3045
+ .uleb128 0x26
3046
+ .4byte .LASF222
3047
+ .byte 0x51
3048
+ .uleb128 0x26
3049
+ .4byte .LASF223
3050
+ .byte 0x52
3051
+ .uleb128 0x26
3052
+ .4byte .LASF224
3053
+ .byte 0x53
3054
+ .uleb128 0x26
3055
+ .4byte .LASF225
3056
+ .byte 0x54
3057
+ .uleb128 0x26
3058
+ .4byte .LASF226
3059
+ .byte 0x55
3060
+ .uleb128 0x26
3061
+ .4byte .LASF227
3062
+ .byte 0x56
3063
+ .uleb128 0x26
3064
+ .4byte .LASF228
3065
+ .byte 0x57
3066
+ .uleb128 0x26
3067
+ .4byte .LASF229
3068
+ .byte 0x58
3069
+ .uleb128 0x26
3070
+ .4byte .LASF230
3071
+ .byte 0x59
3072
+ .uleb128 0x26
3073
+ .4byte .LASF231
3074
+ .byte 0x5a
3075
+ .uleb128 0x26
3076
+ .4byte .LASF232
3077
+ .byte 0x5b
3078
+ .uleb128 0x26
3079
+ .4byte .LASF233
3080
+ .byte 0x5c
3081
+ .uleb128 0x26
3082
+ .4byte .LASF234
3083
+ .byte 0x5d
3084
+ .uleb128 0x26
3085
+ .4byte .LASF235
3086
+ .byte 0x5e
3087
+ .uleb128 0x26
3088
+ .4byte .LASF236
3089
+ .byte 0x5f
3090
+ .uleb128 0x26
3091
+ .4byte .LASF237
3092
+ .byte 0x60
3093
+ .uleb128 0x26
3094
+ .4byte .LASF238
3095
+ .byte 0x61
3096
+ .uleb128 0x26
3097
+ .4byte .LASF239
3098
+ .byte 0x62
3099
+ .uleb128 0x27
3100
+ .4byte .LASF240
3101
+ .sleb128 -1
3102
+ .byte 0
3103
+ .uleb128 0x28
3104
+ .byte 0x4
3105
+ .4byte 0x7f
3106
+ .byte 0x1c
3107
+ .byte 0xf6
3108
+ .4byte 0xb2b
3109
+ .uleb128 0x26
3110
+ .4byte .LASF241
3111
+ .byte 0x5
3112
+ .byte 0
3113
+ .uleb128 0x11
3114
+ .4byte .LASF242
3115
+ .byte 0x40
3116
+ .byte 0x15
3117
+ .byte 0xc
3118
+ .4byte 0xba4
3119
+ .uleb128 0x12
3120
+ .4byte .LASF243
3121
+ .byte 0x15
3122
+ .byte 0x22
3123
+ .4byte 0x3b
3124
+ .byte 0
3125
+ .uleb128 0x1a
3126
+ .string "tbu"
3127
+ .byte 0x15
3128
+ .byte 0x23
3129
+ .4byte 0x7f
3130
+ .byte 0x8
3131
+ .uleb128 0x1a
3132
+ .string "tbl"
3133
+ .byte 0x15
3134
+ .byte 0x24
3135
+ .4byte 0x7f
3136
+ .byte 0xc
3137
+ .uleb128 0x12
3138
+ .4byte .LASF244
3139
+ .byte 0x15
3140
+ .byte 0x25
3141
+ .4byte 0x3b
3142
+ .byte 0x10
3143
+ .uleb128 0x12
3144
+ .4byte .LASF245
3145
+ .byte 0x15
3146
+ .byte 0x26
3147
+ .4byte 0x8d
3148
+ .byte 0x18
3149
+ .uleb128 0x12
3150
+ .4byte .LASF246
3151
+ .byte 0x15
3152
+ .byte 0x29
3153
+ .4byte 0x3b
3154
+ .byte 0x20
3155
+ .uleb128 0x12
3156
+ .4byte .LASF247
3157
+ .byte 0x15
3158
+ .byte 0x2a
3159
+ .4byte 0x3b
3160
+ .byte 0x28
3161
+ .uleb128 0x12
3162
+ .4byte .LASF248
3163
+ .byte 0x15
3164
+ .byte 0x2c
3165
+ .4byte 0x3b
3166
+ .byte 0x30
3167
+ .uleb128 0x12
3168
+ .4byte .LASF249
3169
+ .byte 0x15
3170
+ .byte 0x2d
3171
+ .4byte 0x3b
3172
+ .byte 0x38
3173
+ .byte 0
3174
+ .uleb128 0x11
3175
+ .4byte .LASF250
3176
+ .byte 0x18
3177
+ .byte 0x16
3178
+ .byte 0x22
3179
+ .4byte 0xbec
3180
+ .uleb128 0x12
3181
+ .4byte .LASF251
3182
+ .byte 0x16
3183
+ .byte 0x23
3184
+ .4byte 0xa3
3185
+ .byte 0
3186
+ .uleb128 0x12
3187
+ .4byte .LASF252
3188
+ .byte 0x16
3189
+ .byte 0x24
3190
+ .4byte 0xa3
3191
+ .byte 0x4
3192
+ .uleb128 0x1a
3193
+ .string "id"
3194
+ .byte 0x16
3195
+ .byte 0x25
3196
+ .4byte 0xa3
3197
+ .byte 0x8
3198
+ .uleb128 0x12
3199
+ .4byte .LASF253
3200
+ .byte 0x16
3201
+ .byte 0x26
3202
+ .4byte 0xa3
3203
+ .byte 0xc
3204
+ .uleb128 0x12
3205
+ .4byte .LASF254
3206
+ .byte 0x16
3207
+ .byte 0x27
3208
+ .4byte 0x100
3209
+ .byte 0x10
3210
+ .byte 0
3211
+ .uleb128 0x19
3212
+ .4byte .LASF255
3213
+ .2byte 0x1c8
3214
+ .byte 0x16
3215
+ .byte 0x2a
3216
+ .4byte 0xe22
3217
+ .uleb128 0x1a
3218
+ .string "bd"
3219
+ .byte 0x16
3220
+ .byte 0x2b
3221
+ .4byte 0x880
3222
+ .byte 0
3223
+ .uleb128 0x12
3224
+ .4byte .LASF256
3225
+ .byte 0x16
3226
+ .byte 0x2c
3227
+ .4byte 0x3b
3228
+ .byte 0x8
3229
+ .uleb128 0x12
3230
+ .4byte .LASF253
3231
+ .byte 0x16
3232
+ .byte 0x2d
3233
+ .4byte 0x7f
3234
+ .byte 0x10
3235
+ .uleb128 0x12
3236
+ .4byte .LASF257
3237
+ .byte 0x16
3238
+ .byte 0x2e
3239
+ .4byte 0x3b
3240
+ .byte 0x18
3241
+ .uleb128 0x12
3242
+ .4byte .LASF258
3243
+ .byte 0x16
3244
+ .byte 0x2f
3245
+ .4byte 0x3b
3246
+ .byte 0x20
3247
+ .uleb128 0x12
3248
+ .4byte .LASF259
3249
+ .byte 0x16
3250
+ .byte 0x31
3251
+ .4byte 0x3b
3252
+ .byte 0x28
3253
+ .uleb128 0x12
3254
+ .4byte .LASF260
3255
+ .byte 0x16
3256
+ .byte 0x32
3257
+ .4byte 0x3b
3258
+ .byte 0x30
3259
+ .uleb128 0x12
3260
+ .4byte .LASF261
3261
+ .byte 0x16
3262
+ .byte 0x3e
3263
+ .4byte 0x3b
3264
+ .byte 0x38
3265
+ .uleb128 0x12
3266
+ .4byte .LASF262
3267
+ .byte 0x16
3268
+ .byte 0x42
3269
+ .4byte 0x3b
3270
+ .byte 0x40
3271
+ .uleb128 0x12
3272
+ .4byte .LASF263
3273
+ .byte 0x16
3274
+ .byte 0x43
3275
+ .4byte 0x3b
3276
+ .byte 0x48
3277
+ .uleb128 0x12
3278
+ .4byte .LASF264
3279
+ .byte 0x16
3280
+ .byte 0x45
3281
+ .4byte 0x3b
3282
+ .byte 0x50
3283
+ .uleb128 0x12
3284
+ .4byte .LASF265
3285
+ .byte 0x16
3286
+ .byte 0x46
3287
+ .4byte 0x3b
3288
+ .byte 0x58
3289
+ .uleb128 0x12
3290
+ .4byte .LASF266
3291
+ .byte 0x16
3292
+ .byte 0x47
3293
+ .4byte 0x3b
3294
+ .byte 0x60
3295
+ .uleb128 0x12
3296
+ .4byte .LASF267
3297
+ .byte 0x16
3298
+ .byte 0x48
3299
+ .4byte 0xc4
3300
+ .byte 0x68
3301
+ .uleb128 0x12
3302
+ .4byte .LASF268
3303
+ .byte 0x16
3304
+ .byte 0x49
3305
+ .4byte 0x3b
3306
+ .byte 0x70
3307
+ .uleb128 0x12
3308
+ .4byte .LASF269
3309
+ .byte 0x16
3310
+ .byte 0x4a
3311
+ .4byte 0x3b
3312
+ .byte 0x78
3313
+ .uleb128 0x12
3314
+ .4byte .LASF270
3315
+ .byte 0x16
3316
+ .byte 0x4b
3317
+ .4byte 0x3b
3318
+ .byte 0x80
3319
+ .uleb128 0x12
3320
+ .4byte .LASF271
3321
+ .byte 0x16
3322
+ .byte 0x4c
3323
+ .4byte 0x3b
3324
+ .byte 0x88
3325
+ .uleb128 0x12
3326
+ .4byte .LASF272
3327
+ .byte 0x16
3328
+ .byte 0x4d
3329
+ .4byte 0xe22
3330
+ .byte 0x90
3331
+ .uleb128 0x12
3332
+ .4byte .LASF273
3333
+ .byte 0x16
3334
+ .byte 0x50
3335
+ .4byte 0x16e
3336
+ .byte 0x98
3337
+ .uleb128 0x12
3338
+ .4byte .LASF274
3339
+ .byte 0x16
3340
+ .byte 0x51
3341
+ .4byte 0x16e
3342
+ .byte 0xa0
3343
+ .uleb128 0x12
3344
+ .4byte .LASF275
3345
+ .byte 0x16
3346
+ .byte 0x52
3347
+ .4byte 0x1a1
3348
+ .byte 0xa8
3349
+ .uleb128 0x12
3350
+ .4byte .LASF276
3351
+ .byte 0x16
3352
+ .byte 0x57
3353
+ .4byte 0x174
3354
+ .byte 0xb8
3355
+ .uleb128 0x12
3356
+ .4byte .LASF277
3357
+ .byte 0x16
3358
+ .byte 0x58
3359
+ .4byte 0x126
3360
+ .byte 0xc0
3361
+ .uleb128 0x12
3362
+ .4byte .LASF278
3363
+ .byte 0x16
3364
+ .byte 0x59
3365
+ .4byte 0x3b
3366
+ .byte 0xc8
3367
+ .uleb128 0x12
3368
+ .4byte .LASF279
3369
+ .byte 0x16
3370
+ .byte 0x5b
3371
+ .4byte 0xe2d
3372
+ .byte 0xd0
3373
+ .uleb128 0x12
3374
+ .4byte .LASF280
3375
+ .byte 0x16
3376
+ .byte 0x5c
3377
+ .4byte 0xe2d
3378
+ .byte 0xd8
3379
+ .uleb128 0x12
3380
+ .4byte .LASF281
3381
+ .byte 0x16
3382
+ .byte 0x5e
3383
+ .4byte 0x174
3384
+ .byte 0xe0
3385
+ .uleb128 0x12
3386
+ .4byte .LASF282
3387
+ .byte 0x16
3388
+ .byte 0x5f
3389
+ .4byte 0x174
3390
+ .byte 0xe8
3391
+ .uleb128 0x1a
3392
+ .string "jt"
3393
+ .byte 0x16
3394
+ .byte 0x60
3395
+ .4byte 0xe38
3396
+ .byte 0xf0
3397
+ .uleb128 0x12
3398
+ .4byte .LASF283
3399
+ .byte 0x16
3400
+ .byte 0x61
3401
+ .4byte 0xe3e
3402
+ .byte 0xf8
3403
+ .uleb128 0x16
3404
+ .4byte .LASF284
3405
+ .byte 0x16
3406
+ .byte 0x6b
3407
+ .4byte 0x7f
3408
+ .2byte 0x118
3409
+ .uleb128 0x16
3410
+ .4byte .LASF285
3411
+ .byte 0x16
3412
+ .byte 0x6c
3413
+ .4byte 0x7f
3414
+ .2byte 0x11c
3415
+ .uleb128 0x16
3416
+ .4byte .LASF286
3417
+ .byte 0x16
3418
+ .byte 0x6e
3419
+ .4byte 0x3b
3420
+ .2byte 0x120
3421
+ .uleb128 0x16
3422
+ .4byte .LASF287
3423
+ .byte 0x16
3424
+ .byte 0x6f
3425
+ .4byte 0x3b
3426
+ .2byte 0x128
3427
+ .uleb128 0x16
3428
+ .4byte .LASF288
3429
+ .byte 0x16
3430
+ .byte 0x70
3431
+ .4byte 0x3b
3432
+ .2byte 0x130
3433
+ .uleb128 0x16
3434
+ .4byte .LASF289
3435
+ .byte 0x16
3436
+ .byte 0x79
3437
+ .4byte 0x16e
3438
+ .2byte 0x138
3439
+ .uleb128 0x16
3440
+ .4byte .LASF110
3441
+ .byte 0x16
3442
+ .byte 0x7a
3443
+ .4byte 0xb2b
3444
+ .2byte 0x140
3445
+ .uleb128 0x16
3446
+ .4byte .LASF290
3447
+ .byte 0x16
3448
+ .byte 0x80
3449
+ .4byte 0x100
3450
+ .2byte 0x180
3451
+ .uleb128 0x16
3452
+ .4byte .LASF291
3453
+ .byte 0x16
3454
+ .byte 0x81
3455
+ .4byte 0x100
3456
+ .2byte 0x188
3457
+ .uleb128 0x16
3458
+ .4byte .LASF292
3459
+ .byte 0x16
3460
+ .byte 0x87
3461
+ .4byte 0xb9
3462
+ .2byte 0x190
3463
+ .uleb128 0x16
3464
+ .4byte .LASF293
3465
+ .byte 0x16
3466
+ .byte 0x8a
3467
+ .4byte 0x54
3468
+ .2byte 0x198
3469
+ .uleb128 0x16
3470
+ .4byte .LASF294
3471
+ .byte 0x16
3472
+ .byte 0x8c
3473
+ .4byte 0xba4
3474
+ .2byte 0x1a0
3475
+ .uleb128 0x16
3476
+ .4byte .LASF295
3477
+ .byte 0x16
3478
+ .byte 0x8d
3479
+ .4byte 0x100
3480
+ .2byte 0x1b8
3481
+ .uleb128 0x16
3482
+ .4byte .LASF296
3483
+ .byte 0x16
3484
+ .byte 0x8e
3485
+ .4byte 0x54
3486
+ .2byte 0x1c0
3487
+ .byte 0
3488
+ .uleb128 0x8
3489
+ .byte 0x8
3490
+ .4byte 0xbec
3491
+ .uleb128 0xe
3492
+ .4byte .LASF297
3493
+ .uleb128 0x8
3494
+ .byte 0x8
3495
+ .4byte 0xe28
3496
+ .uleb128 0xe
3497
+ .4byte .LASF298
3498
+ .uleb128 0x8
3499
+ .byte 0x8
3500
+ .4byte 0xe33
3501
+ .uleb128 0xb
3502
+ .4byte 0xdc
3503
+ .4byte 0xe4e
3504
+ .uleb128 0x10
3505
+ .4byte 0xcf
3506
+ .byte 0x1f
3507
+ .byte 0
3508
+ .uleb128 0x2
3509
+ .4byte .LASF299
3510
+ .byte 0x16
3511
+ .byte 0x9b
3512
+ .4byte 0xbec
3513
+ .uleb128 0x9
3514
+ .4byte 0xe4e
3515
+ .uleb128 0x4
3516
+ .4byte .LASF300
3517
+ .byte 0x4
3518
+ .byte 0xad
3519
+ .4byte 0x100
3520
+ .uleb128 0xb
3521
+ .4byte 0x94
3522
+ .4byte 0xe74
3523
+ .uleb128 0xc
3524
+ .byte 0
3525
+ .uleb128 0x4
3526
+ .4byte .LASF301
3527
+ .byte 0x4
3528
+ .byte 0xaf
3529
+ .4byte 0xe69
3530
+ .uleb128 0x4
3531
+ .4byte .LASF302
3532
+ .byte 0x4
3533
+ .byte 0xb0
3534
+ .4byte 0xe69
3535
+ .uleb128 0x4
3536
+ .4byte .LASF303
3537
+ .byte 0x4
3538
+ .byte 0xfe
3539
+ .4byte 0x100
3540
+ .uleb128 0x4
3541
+ .4byte .LASF304
3542
+ .byte 0x4
3543
+ .byte 0xff
3544
+ .4byte 0x100
3545
+ .uleb128 0xd
3546
+ .4byte .LASF305
3547
+ .byte 0x4
3548
+ .2byte 0x100
3549
+ .4byte 0x100
3550
+ .uleb128 0x11
3551
+ .4byte .LASF306
3552
+ .byte 0x4
3553
+ .byte 0x17
3554
+ .byte 0x2e
3555
+ .4byte 0xec5
3556
+ .uleb128 0x12
3557
+ .4byte .LASF307
3558
+ .byte 0x17
3559
+ .byte 0x2f
3560
+ .4byte 0x11b
3561
+ .byte 0
3562
+ .byte 0
3563
+ .uleb128 0x8
3564
+ .byte 0x8
3565
+ .4byte 0x29
3566
+ .uleb128 0xb
3567
+ .4byte 0x94
3568
+ .4byte 0xedb
3569
+ .uleb128 0x10
3570
+ .4byte 0xcf
3571
+ .byte 0x5
3572
+ .byte 0
3573
+ .uleb128 0xd
3574
+ .4byte .LASF308
3575
+ .byte 0x17
3576
+ .2byte 0x1fd
3577
+ .4byte 0xeac
3578
+ .uleb128 0xd
3579
+ .4byte .LASF309
3580
+ .byte 0x17
3581
+ .2byte 0x1fe
3582
+ .4byte 0xeac
3583
+ .uleb128 0xd
3584
+ .4byte .LASF310
3585
+ .byte 0x17
3586
+ .2byte 0x200
3587
+ .4byte 0xeac
3588
+ .uleb128 0xd
3589
+ .4byte .LASF311
3590
+ .byte 0x17
3591
+ .2byte 0x205
3592
+ .4byte 0xe3e
3593
+ .uleb128 0xd
3594
+ .4byte .LASF312
3595
+ .byte 0x17
3596
+ .2byte 0x206
3597
+ .4byte 0xe3e
3598
+ .uleb128 0xb
3599
+ .4byte 0xdc
3600
+ .4byte 0xf27
3601
+ .uleb128 0x10
3602
+ .4byte 0xcf
3603
+ .byte 0x3f
3604
+ .byte 0
3605
+ .uleb128 0xd
3606
+ .4byte .LASF313
3607
+ .byte 0x17
3608
+ .2byte 0x207
3609
+ .4byte 0xf17
3610
+ .uleb128 0xd
3611
+ .4byte .LASF314
3612
+ .byte 0x17
3613
+ .2byte 0x209
3614
+ .4byte 0xecb
3615
+ .uleb128 0xd
3616
+ .4byte .LASF315
3617
+ .byte 0x17
3618
+ .2byte 0x20a
3619
+ .4byte 0xecb
3620
+ .uleb128 0xd
3621
+ .4byte .LASF316
3622
+ .byte 0x17
3623
+ .2byte 0x20b
3624
+ .4byte 0xeac
3625
+ .uleb128 0xd
3626
+ .4byte .LASF317
3627
+ .byte 0x17
3628
+ .2byte 0x20c
3629
+ .4byte 0xeac
3630
+ .uleb128 0xd
3631
+ .4byte .LASF318
3632
+ .byte 0x17
3633
+ .2byte 0x20d
3634
+ .4byte 0xec5
3635
+ .uleb128 0xb
3636
+ .4byte 0xec5
3637
+ .4byte 0xf7f
3638
+ .uleb128 0x10
3639
+ .4byte 0xcf
3640
+ .byte 0x3
3641
+ .byte 0
3642
+ .uleb128 0xd
3643
+ .4byte .LASF319
3644
+ .byte 0x17
3645
+ .2byte 0x20e
3646
+ .4byte 0xf6f
3647
+ .uleb128 0xd
3648
+ .4byte .LASF320
3649
+ .byte 0x17
3650
+ .2byte 0x20f
3651
+ .4byte 0xec5
3652
+ .uleb128 0xd
3653
+ .4byte .LASF321
3654
+ .byte 0x17
3655
+ .2byte 0x210
3656
+ .4byte 0x54
3657
+ .uleb128 0xb
3658
+ .4byte 0x9e
3659
+ .4byte 0xfb3
3660
+ .uleb128 0x10
3661
+ .4byte 0xcf
3662
+ .byte 0x5
3663
+ .byte 0
3664
+ .uleb128 0x7
3665
+ .4byte 0xfa3
3666
+ .uleb128 0xd
3667
+ .4byte .LASF322
3668
+ .byte 0x17
3669
+ .2byte 0x211
3670
+ .4byte 0xfb3
3671
+ .uleb128 0xd
3672
+ .4byte .LASF323
3673
+ .byte 0x17
3674
+ .2byte 0x212
3675
+ .4byte 0xfb3
3676
+ .uleb128 0xd
3677
+ .4byte .LASF324
3678
+ .byte 0x17
3679
+ .2byte 0x216
3680
+ .4byte 0xf5
3681
+ .uleb128 0xd
3682
+ .4byte .LASF325
3683
+ .byte 0x17
3684
+ .2byte 0x217
3685
+ .4byte 0xf5
3686
+ .uleb128 0xd
3687
+ .4byte .LASF326
3688
+ .byte 0x17
3689
+ .2byte 0x219
3690
+ .4byte 0x54
3691
+ .uleb128 0xd
3692
+ .4byte .LASF327
3693
+ .byte 0x17
3694
+ .2byte 0x220
3695
+ .4byte 0x89e
3696
+ .uleb128 0xd
3697
+ .4byte .LASF328
3698
+ .byte 0x17
3699
+ .2byte 0x222
3700
+ .4byte 0xa3
3701
+ .uleb128 0xd
3702
+ .4byte .LASF329
3703
+ .byte 0x17
3704
+ .2byte 0x224
3705
+ .4byte 0xa3
3706
+ .uleb128 0xd
3707
+ .4byte .LASF330
3708
+ .byte 0x17
3709
+ .2byte 0x230
3710
+ .4byte 0xeac
3711
+ .uleb128 0x29
3712
+ .4byte .LASF332
3713
+ .byte 0x4
3714
+ .4byte 0x7f
3715
+ .byte 0x17
3716
+ .2byte 0x286
3717
+ .4byte 0x104e
3718
+ .uleb128 0x26
3719
+ .4byte .LASF333
3720
+ .byte 0
3721
+ .uleb128 0x26
3722
+ .4byte .LASF334
3723
+ .byte 0x1
3724
+ .uleb128 0x26
3725
+ .4byte .LASF335
3726
+ .byte 0x2
3727
+ .uleb128 0x26
3728
+ .4byte .LASF336
3729
+ .byte 0x3
3730
+ .byte 0
3731
+ .uleb128 0xd
3732
+ .4byte .LASF337
3733
+ .byte 0x17
3734
+ .2byte 0x28c
3735
+ .4byte 0x1024
3736
+ .uleb128 0x4
3737
+ .4byte .LASF338
3738
+ .byte 0x19
3739
+ .byte 0x2b
3740
+ .4byte 0x13a
3741
+ .uleb128 0x4
3742
+ .4byte .LASF339
3743
+ .byte 0x19
3744
+ .byte 0x2b
3745
+ .4byte 0x13a
3746
+ .uleb128 0x11
3747
+ .4byte .LASF340
3748
+ .byte 0x28
3749
+ .byte 0x1a
3750
+ .byte 0x39
3751
+ .4byte 0x10b9
3752
+ .uleb128 0x1a
3753
+ .string "dev"
3754
+ .byte 0x1a
3755
+ .byte 0x3a
3756
+ .4byte 0x126
3757
+ .byte 0
3758
+ .uleb128 0x12
3759
+ .4byte .LASF341
3760
+ .byte 0x1a
3761
+ .byte 0x3b
3762
+ .4byte 0x126
3763
+ .byte 0x8
3764
+ .uleb128 0x12
3765
+ .4byte .LASF342
3766
+ .byte 0x1a
3767
+ .byte 0x3c
3768
+ .4byte 0x54
3769
+ .byte 0x10
3770
+ .uleb128 0x12
3771
+ .4byte .LASF343
3772
+ .byte 0x1a
3773
+ .byte 0x3d
3774
+ .4byte 0xd6
3775
+ .byte 0x18
3776
+ .uleb128 0x12
3777
+ .4byte .LASF344
3778
+ .byte 0x1a
3779
+ .byte 0x3e
3780
+ .4byte 0x10dd
3781
+ .byte 0x20
3782
+ .byte 0
3783
+ .uleb128 0x13
3784
+ .4byte 0x100
3785
+ .4byte 0x10d7
3786
+ .uleb128 0x14
3787
+ .4byte 0x10d7
3788
+ .uleb128 0x14
3789
+ .4byte 0x100
3790
+ .uleb128 0x14
3791
+ .4byte 0x100
3792
+ .uleb128 0x14
3793
+ .4byte 0x126
3794
+ .byte 0
3795
+ .uleb128 0x8
3796
+ .byte 0x8
3797
+ .4byte 0x1070
3798
+ .uleb128 0x8
3799
+ .byte 0x8
3800
+ .4byte 0x10b9
3801
+ .uleb128 0x11
3802
+ .4byte .LASF345
3803
+ .byte 0x38
3804
+ .byte 0x1b
3805
+ .byte 0xc
3806
+ .4byte 0x1114
3807
+ .uleb128 0x12
3808
+ .4byte .LASF346
3809
+ .byte 0x1b
3810
+ .byte 0xd
3811
+ .4byte 0x1070
3812
+ .byte 0
3813
+ .uleb128 0x12
3814
+ .4byte .LASF347
3815
+ .byte 0x1b
3816
+ .byte 0x10
3817
+ .4byte 0x126
3818
+ .byte 0x28
3819
+ .uleb128 0x12
3820
+ .4byte .LASF348
3821
+ .byte 0x1b
3822
+ .byte 0x11
3823
+ .4byte 0x100
3824
+ .byte 0x30
3825
+ .byte 0
3826
+ .uleb128 0x2a
3827
+ .string "gd"
3828
+ .byte 0x1
3829
+ .byte 0xf
3830
+ .4byte 0x111e
3831
+ .uleb128 0x8
3832
+ .byte 0x8
3833
+ .4byte 0xe59
3834
+ .uleb128 0x28
3835
+ .byte 0x4
3836
+ .4byte 0x7f
3837
+ .byte 0x1
3838
+ .byte 0x40
3839
+ .4byte 0x1149
3840
+ .uleb128 0x26
3841
+ .4byte .LASF349
3842
+ .byte 0
3843
+ .uleb128 0x26
3844
+ .4byte .LASF350
3845
+ .byte 0x1
3846
+ .uleb128 0x26
3847
+ .4byte .LASF351
3848
+ .byte 0x2
3849
+ .uleb128 0x26
3850
+ .4byte .LASF352
3851
+ .byte 0x3
3852
+ .byte 0
3853
+ .uleb128 0x28
3854
+ .byte 0x4
3855
+ .4byte 0x7f
3856
+ .byte 0x1
3857
+ .byte 0x47
3858
+ .4byte 0x1180
3859
+ .uleb128 0x26
3860
+ .4byte .LASF353
3861
+ .byte 0
3862
+ .uleb128 0x26
3863
+ .4byte .LASF354
3864
+ .byte 0x1
3865
+ .uleb128 0x26
3866
+ .4byte .LASF355
3867
+ .byte 0x2
3868
+ .uleb128 0x26
3869
+ .4byte .LASF356
3870
+ .byte 0x3
3871
+ .uleb128 0x26
3872
+ .4byte .LASF357
3873
+ .byte 0x4
3874
+ .uleb128 0x26
3875
+ .4byte .LASF358
3876
+ .byte 0x5
3877
+ .uleb128 0x26
3878
+ .4byte .LASF359
3879
+ .byte 0x6
3880
+ .byte 0
3881
+ .uleb128 0x28
3882
+ .byte 0x4
3883
+ .4byte 0x7f
3884
+ .byte 0x1
3885
+ .byte 0x51
3886
+ .4byte 0x11c3
3887
+ .uleb128 0x26
3888
+ .4byte .LASF360
3889
+ .byte 0
3890
+ .uleb128 0x26
3891
+ .4byte .LASF361
3892
+ .byte 0x1
3893
+ .uleb128 0x26
3894
+ .4byte .LASF362
3895
+ .byte 0x2
3896
+ .uleb128 0x26
3897
+ .4byte .LASF363
3898
+ .byte 0x3
3899
+ .uleb128 0x26
3900
+ .4byte .LASF364
3901
+ .byte 0x4
3902
+ .uleb128 0x26
3903
+ .4byte .LASF365
3904
+ .byte 0x5
3905
+ .uleb128 0x26
3906
+ .4byte .LASF366
3907
+ .byte 0x6
3908
+ .uleb128 0x26
3909
+ .4byte .LASF367
3910
+ .byte 0x7
3911
+ .uleb128 0x26
3912
+ .4byte .LASF368
3913
+ .byte 0x8
3914
+ .byte 0
3915
+ .uleb128 0xb
3916
+ .4byte 0xd6
3917
+ .4byte 0x11d3
3918
+ .uleb128 0x10
3919
+ .4byte 0xcf
3920
+ .byte 0x7
3921
+ .byte 0
3922
+ .uleb128 0x2b
3923
+ .4byte .LASF369
3924
+ .byte 0x1
3925
+ .byte 0x5d
3926
+ .4byte 0x11c3
3927
+ .uleb128 0x9
3928
+ .byte 0x3
3929
+ .8byte tid_name
3930
+ .uleb128 0x2
3931
+ .4byte .LASF370
3932
+ .byte 0x1
3933
+ .byte 0x68
3934
+ .4byte 0x11f3
3935
+ .uleb128 0x8
3936
+ .byte 0x8
3937
+ .4byte 0x11f9
3938
+ .uleb128 0x13
3939
+ .4byte 0x54
3940
+ .4byte 0x1208
3941
+ .uleb128 0x14
3942
+ .4byte 0x1208
3943
+ .byte 0
3944
+ .uleb128 0x8
3945
+ .byte 0x8
3946
+ .4byte 0x10e3
3947
+ .uleb128 0x11
3948
+ .4byte .LASF371
3949
+ .byte 0x28
3950
+ .byte 0x1
3951
+ .byte 0x69
3952
+ .4byte 0x126d
3953
+ .uleb128 0x1a
3954
+ .string "fn"
3955
+ .byte 0x1
3956
+ .byte 0x6a
3957
+ .4byte 0x11e8
3958
+ .byte 0
3959
+ .uleb128 0x12
3960
+ .4byte .LASF138
3961
+ .byte 0x1
3962
+ .byte 0x6b
3963
+ .4byte 0xa3
3964
+ .byte 0x8
3965
+ .uleb128 0x1a
3966
+ .string "tid"
3967
+ .byte 0x1
3968
+ .byte 0x6c
3969
+ .4byte 0xa3
3970
+ .byte 0xc
3971
+ .uleb128 0x12
3972
+ .4byte .LASF372
3973
+ .byte 0x1
3974
+ .byte 0x6d
3975
+ .4byte 0xa3
3976
+ .byte 0x10
3977
+ .uleb128 0x12
3978
+ .4byte .LASF373
3979
+ .byte 0x1
3980
+ .byte 0x6e
3981
+ .4byte 0xa3
3982
+ .byte 0x14
3983
+ .uleb128 0x1a
3984
+ .string "ret"
3985
+ .byte 0x1
3986
+ .byte 0x6f
3987
+ .4byte 0x54
3988
+ .byte 0x18
3989
+ .uleb128 0x1a
3990
+ .string "ms"
3991
+ .byte 0x1
3992
+ .byte 0x70
3993
+ .4byte 0x100
3994
+ .byte 0x20
3995
+ .byte 0
3996
+ .uleb128 0x19
3997
+ .4byte .LASF374
3998
+ .2byte 0x148
3999
+ .byte 0x1
4000
+ .byte 0x73
4001
+ .4byte 0x1294
4002
+ .uleb128 0x12
4003
+ .4byte .LASF375
4004
+ .byte 0x1
4005
+ .byte 0x74
4006
+ .4byte 0x1294
4007
+ .byte 0
4008
+ .uleb128 0x17
4009
+ .string "num"
4010
+ .byte 0x1
4011
+ .byte 0x75
4012
+ .4byte 0x94
4013
+ .2byte 0x140
4014
+ .byte 0
4015
+ .uleb128 0xb
4016
+ .4byte 0x120e
4017
+ .4byte 0x12a4
4018
+ .uleb128 0x10
4019
+ .4byte 0xcf
4020
+ .byte 0x7
4021
+ .byte 0
4022
+ .uleb128 0x19
4023
+ .4byte .LASF376
4024
+ .2byte 0x560
4025
+ .byte 0x1
4026
+ .byte 0x78
4027
+ .4byte 0x12d7
4028
+ .uleb128 0x12
4029
+ .4byte .LASF377
4030
+ .byte 0x1
4031
+ .byte 0x79
4032
+ .4byte 0xa3
4033
+ .byte 0
4034
+ .uleb128 0x1a
4035
+ .string "cpu"
4036
+ .byte 0x1
4037
+ .byte 0x7a
4038
+ .4byte 0x12d7
4039
+ .byte 0x8
4040
+ .uleb128 0x16
4041
+ .4byte .LASF378
4042
+ .byte 0x1
4043
+ .byte 0x7b
4044
+ .4byte 0x10e3
4045
+ .2byte 0x528
4046
+ .byte 0
4047
+ .uleb128 0xb
4048
+ .4byte 0x126d
4049
+ .4byte 0x12e7
4050
+ .uleb128 0x10
4051
+ .4byte 0xcf
4052
+ .byte 0x3
4053
+ .byte 0
4054
+ .uleb128 0x2c
4055
+ .string "mpb"
4056
+ .byte 0x1
4057
+ .byte 0x7e
4058
+ .4byte 0x12f2
4059
+ .uleb128 0x8
4060
+ .byte 0x8
4061
+ .4byte 0x12a4
4062
+ .uleb128 0x2b
4063
+ .4byte .LASF379
4064
+ .byte 0x1
4065
+ .byte 0x7f
4066
+ .4byte 0x100
4067
+ .uleb128 0x9
4068
+ .byte 0x3
4069
+ .8byte mpb_gd
4070
+ .uleb128 0x11
4071
+ .4byte .LASF380
4072
+ .byte 0x18
4073
+ .byte 0x1
4074
+ .byte 0x95
4075
+ .4byte 0x1355
4076
+ .uleb128 0x1a
4077
+ .string "cid"
4078
+ .byte 0x1
4079
+ .byte 0x96
4080
+ .4byte 0xa3
4081
+ .byte 0
4082
+ .uleb128 0x1a
4083
+ .string "tid"
4084
+ .byte 0x1
4085
+ .byte 0x97
4086
+ .4byte 0xa3
4087
+ .byte 0x4
4088
+ .uleb128 0x1a
4089
+ .string "fn"
4090
+ .byte 0x1
4091
+ .byte 0x98
4092
+ .4byte 0x11e8
4093
+ .byte 0x8
4094
+ .uleb128 0x12
4095
+ .4byte .LASF372
4096
+ .byte 0x1
4097
+ .byte 0x99
4098
+ .4byte 0xa3
4099
+ .byte 0x10
4100
+ .uleb128 0x12
4101
+ .4byte .LASF373
4102
+ .byte 0x1
4103
+ .byte 0x9a
4104
+ .4byte 0xa3
4105
+ .byte 0x14
4106
+ .byte 0
4107
+ .uleb128 0x2d
4108
+ .4byte .LASF389
4109
+ .byte 0x1
4110
+ .2byte 0x271
4111
+ .4byte 0x100
4112
+ .8byte .LFB240
4113
+ .8byte .LFE240-.LFB240
4114
+ .uleb128 0x1
4115
+ .byte 0x9c
4116
+ .4byte 0x139b
4117
+ .uleb128 0x2e
4118
+ .string "evt"
4119
+ .byte 0x1
4120
+ .2byte 0x271
4121
+ .4byte 0x54
4122
+ .4byte .LLST61
4123
+ .uleb128 0x2f
4124
+ .8byte .LVL153
4125
+ .4byte 0x19e7
4126
+ .uleb128 0x30
4127
+ .uleb128 0x1
4128
+ .byte 0x50
4129
+ .uleb128 0x1
4130
+ .byte 0x32
4131
+ .byte 0
4132
+ .byte 0
4133
+ .uleb128 0x31
4134
+ .4byte .LASF381
4135
+ .byte 0x1
4136
+ .2byte 0x219
4137
+ .8byte .LFB239
4138
+ .8byte .LFE239-.LFB239
4139
+ .uleb128 0x1
4140
+ .byte 0x9c
4141
+ .4byte 0x1584
4142
+ .uleb128 0x2e
4143
+ .string "evt"
4144
+ .byte 0x1
4145
+ .2byte 0x219
4146
+ .4byte 0x54
4147
+ .4byte .LLST53
4148
+ .uleb128 0x32
4149
+ .4byte 0x1618
4150
+ .8byte .LBB120
4151
+ .4byte .Ldebug_ranges0+0x1c0
4152
+ .byte 0x1
4153
+ .2byte 0x21d
4154
+ .4byte 0x14f3
4155
+ .uleb128 0x33
4156
+ .4byte .Ldebug_ranges0+0x1c0
4157
+ .uleb128 0x34
4158
+ .4byte 0x1625
4159
+ .uleb128 0x2
4160
+ .byte 0x91
4161
+ .sleb128 -48
4162
+ .uleb128 0x35
4163
+ .4byte 0x1631
4164
+ .4byte .LLST54
4165
+ .uleb128 0x32
4166
+ .4byte 0x1eb5
4167
+ .8byte .LBB122
4168
+ .4byte .Ldebug_ranges0+0x1f0
4169
+ .byte 0x1
4170
+ .2byte 0x203
4171
+ .4byte 0x143a
4172
+ .uleb128 0x36
4173
+ .4byte 0x1ec5
4174
+ .4byte .LLST55
4175
+ .uleb128 0x33
4176
+ .4byte .Ldebug_ranges0+0x1f0
4177
+ .uleb128 0x35
4178
+ .4byte 0x1ed0
4179
+ .4byte .LLST56
4180
+ .uleb128 0x35
4181
+ .4byte 0x1edb
4182
+ .4byte .LLST57
4183
+ .uleb128 0x35
4184
+ .4byte 0x1ee6
4185
+ .4byte .LLST58
4186
+ .byte 0
4187
+ .byte 0
4188
+ .uleb128 0x37
4189
+ .8byte .LBB127
4190
+ .8byte .LBE127-.LBB127
4191
+ .4byte 0x1455
4192
+ .uleb128 0x38
4193
+ .4byte 0x1640
4194
+ .byte 0
4195
+ .uleb128 0x37
4196
+ .8byte .LBB128
4197
+ .8byte .LBE128-.LBB128
4198
+ .4byte 0x1474
4199
+ .uleb128 0x35
4200
+ .4byte 0x164e
4201
+ .4byte .LLST59
4202
+ .byte 0
4203
+ .uleb128 0x39
4204
+ .8byte .LVL128
4205
+ .4byte 0x22d5
4206
+ .4byte 0x149f
4207
+ .uleb128 0x30
4208
+ .uleb128 0x1
4209
+ .byte 0x50
4210
+ .uleb128 0x2
4211
+ .byte 0x8f
4212
+ .sleb128 16
4213
+ .uleb128 0x30
4214
+ .uleb128 0x1
4215
+ .byte 0x51
4216
+ .uleb128 0x9
4217
+ .byte 0x3
4218
+ .8byte .LANCHOR2
4219
+ .uleb128 0x30
4220
+ .uleb128 0x1
4221
+ .byte 0x52
4222
+ .uleb128 0x2
4223
+ .byte 0x8
4224
+ .byte 0x30
4225
+ .byte 0
4226
+ .uleb128 0x39
4227
+ .8byte .LVL129
4228
+ .4byte 0x22de
4229
+ .4byte 0x14be
4230
+ .uleb128 0x30
4231
+ .uleb128 0x1
4232
+ .byte 0x50
4233
+ .uleb128 0x9
4234
+ .byte 0x3
4235
+ .8byte .LC13
4236
+ .byte 0
4237
+ .uleb128 0x39
4238
+ .8byte .LVL130
4239
+ .4byte 0x22e9
4240
+ .4byte 0x14e4
4241
+ .uleb128 0x30
4242
+ .uleb128 0x1
4243
+ .byte 0x50
4244
+ .uleb128 0x4
4245
+ .byte 0x8
4246
+ .byte 0x82
4247
+ .byte 0x44
4248
+ .byte 0x24
4249
+ .uleb128 0x30
4250
+ .uleb128 0x1
4251
+ .byte 0x51
4252
+ .uleb128 0x1
4253
+ .byte 0x30
4254
+ .uleb128 0x30
4255
+ .uleb128 0x1
4256
+ .byte 0x52
4257
+ .uleb128 0x3
4258
+ .byte 0xa
4259
+ .2byte 0x560
4260
+ .byte 0
4261
+ .uleb128 0x3a
4262
+ .8byte .LVL133
4263
+ .4byte 0x22f4
4264
+ .byte 0
4265
+ .byte 0
4266
+ .uleb128 0x3b
4267
+ .4byte 0x1fd7
4268
+ .8byte .LBB132
4269
+ .8byte .LBE132-.LBB132
4270
+ .byte 0x1
4271
+ .2byte 0x226
4272
+ .4byte 0x152e
4273
+ .uleb128 0x36
4274
+ .4byte 0x1fe3
4275
+ .4byte .LLST60
4276
+ .uleb128 0x3c
4277
+ .8byte .LVL148
4278
+ .4byte 0x2300
4279
+ .uleb128 0x30
4280
+ .uleb128 0x1
4281
+ .byte 0x50
4282
+ .uleb128 0x3
4283
+ .byte 0xa
4284
+ .2byte 0x3e8
4285
+ .byte 0
4286
+ .byte 0
4287
+ .uleb128 0x39
4288
+ .8byte .LVL145
4289
+ .4byte 0x1d6b
4290
+ .4byte 0x1554
4291
+ .uleb128 0x30
4292
+ .uleb128 0x1
4293
+ .byte 0x50
4294
+ .uleb128 0x1
4295
+ .byte 0x30
4296
+ .uleb128 0x30
4297
+ .uleb128 0x1
4298
+ .byte 0x51
4299
+ .uleb128 0x1
4300
+ .byte 0x33
4301
+ .uleb128 0x30
4302
+ .uleb128 0x1
4303
+ .byte 0x52
4304
+ .uleb128 0x6
4305
+ .byte 0x11
4306
+ .sleb128 -559087616
4307
+ .byte 0
4308
+ .uleb128 0x3a
4309
+ .8byte .LVL146
4310
+ .4byte 0x22f4
4311
+ .uleb128 0x3c
4312
+ .8byte .LVL150
4313
+ .4byte 0x1d6b
4314
+ .uleb128 0x30
4315
+ .uleb128 0x1
4316
+ .byte 0x50
4317
+ .uleb128 0x1
4318
+ .byte 0x30
4319
+ .uleb128 0x30
4320
+ .uleb128 0x1
4321
+ .byte 0x51
4322
+ .uleb128 0x1
4323
+ .byte 0x37
4324
+ .uleb128 0x30
4325
+ .uleb128 0x1
4326
+ .byte 0x52
4327
+ .uleb128 0x6
4328
+ .byte 0x11
4329
+ .sleb128 -559087616
4330
+ .byte 0
4331
+ .byte 0
4332
+ .uleb128 0x31
4333
+ .4byte .LASF382
4334
+ .byte 0x1
4335
+ .2byte 0x20e
4336
+ .8byte .LFB238
4337
+ .8byte .LFE238-.LFB238
4338
+ .uleb128 0x1
4339
+ .byte 0x9c
4340
+ .4byte 0x1618
4341
+ .uleb128 0x3d
4342
+ .4byte .LASF346
4343
+ .byte 0x1
4344
+ .2byte 0x20e
4345
+ .4byte 0x1070
4346
+ .uleb128 0x2
4347
+ .byte 0x70
4348
+ .sleb128 0
4349
+ .uleb128 0x39
4350
+ .8byte .LVL122
4351
+ .4byte 0x22d5
4352
+ .4byte 0x15c9
4353
+ .uleb128 0x30
4354
+ .uleb128 0x1
4355
+ .byte 0x52
4356
+ .uleb128 0x2
4357
+ .byte 0x8
4358
+ .byte 0x28
4359
+ .byte 0
4360
+ .uleb128 0x39
4361
+ .8byte .LVL123
4362
+ .4byte 0x184a
4363
+ .4byte 0x15e5
4364
+ .uleb128 0x30
4365
+ .uleb128 0x1
4366
+ .byte 0x50
4367
+ .uleb128 0x1
4368
+ .byte 0x30
4369
+ .uleb128 0x30
4370
+ .uleb128 0x1
4371
+ .byte 0x51
4372
+ .uleb128 0x1
4373
+ .byte 0x32
4374
+ .byte 0
4375
+ .uleb128 0x39
4376
+ .8byte .LVL124
4377
+ .4byte 0x1d6b
4378
+ .4byte 0x160a
4379
+ .uleb128 0x30
4380
+ .uleb128 0x1
4381
+ .byte 0x50
4382
+ .uleb128 0x1
4383
+ .byte 0x30
4384
+ .uleb128 0x30
4385
+ .uleb128 0x1
4386
+ .byte 0x51
4387
+ .uleb128 0x1
4388
+ .byte 0x33
4389
+ .uleb128 0x30
4390
+ .uleb128 0x1
4391
+ .byte 0x52
4392
+ .uleb128 0x5
4393
+ .byte 0xc
4394
+ .4byte 0x11111111
4395
+ .byte 0
4396
+ .uleb128 0x3a
4397
+ .8byte .LVL125
4398
+ .4byte 0x22f4
4399
+ .byte 0
4400
+ .uleb128 0x3e
4401
+ .4byte .LASF403
4402
+ .byte 0x1
4403
+ .2byte 0x1e9
4404
+ .byte 0x1
4405
+ .4byte 0x165c
4406
+ .uleb128 0x3f
4407
+ .4byte .LASF383
4408
+ .byte 0x1
4409
+ .2byte 0x1ee
4410
+ .4byte 0x165c
4411
+ .uleb128 0x40
4412
+ .string "i"
4413
+ .byte 0x1
4414
+ .2byte 0x1fb
4415
+ .4byte 0x54
4416
+ .uleb128 0x41
4417
+ .4byte 0x164d
4418
+ .uleb128 0x40
4419
+ .string "__v"
4420
+ .byte 0x1
4421
+ .2byte 0x206
4422
+ .4byte 0xa3
4423
+ .byte 0
4424
+ .uleb128 0x42
4425
+ .uleb128 0x40
4426
+ .string "__v"
4427
+ .byte 0x1
4428
+ .2byte 0x207
4429
+ .4byte 0xa3
4430
+ .byte 0
4431
+ .byte 0
4432
+ .uleb128 0xb
4433
+ .4byte 0x130d
4434
+ .4byte 0x166c
4435
+ .uleb128 0x10
4436
+ .4byte 0xcf
4437
+ .byte 0x1
4438
+ .byte 0
4439
+ .uleb128 0x31
4440
+ .4byte .LASF384
4441
+ .byte 0x1
4442
+ .2byte 0x1bf
4443
+ .8byte .LFB236
4444
+ .8byte .LFE236-.LFB236
4445
+ .uleb128 0x1
4446
+ .byte 0x9c
4447
+ .4byte 0x1764
4448
+ .uleb128 0x2e
4449
+ .string "cpu"
4450
+ .byte 0x1
4451
+ .2byte 0x1bf
4452
+ .4byte 0xa3
4453
+ .4byte .LLST51
4454
+ .uleb128 0x3b
4455
+ .4byte 0x1f14
4456
+ .8byte .LBB106
4457
+ .8byte .LBE106-.LBB106
4458
+ .byte 0x1
4459
+ .2byte 0x1c2
4460
+ .4byte 0x16c0
4461
+ .uleb128 0x36
4462
+ .4byte 0x1f20
4463
+ .4byte .LLST52
4464
+ .byte 0
4465
+ .uleb128 0x43
4466
+ .4byte 0x1fcf
4467
+ .8byte .LBB108
4468
+ .8byte .LBE108-.LBB108
4469
+ .byte 0x1
4470
+ .2byte 0x1d6
4471
+ .uleb128 0x43
4472
+ .4byte 0x1f0c
4473
+ .8byte .LBB110
4474
+ .8byte .LBE110-.LBB110
4475
+ .byte 0x1
4476
+ .2byte 0x1da
4477
+ .uleb128 0x3a
4478
+ .8byte .LVL114
4479
+ .4byte 0x230b
4480
+ .uleb128 0x39
4481
+ .8byte .LVL115
4482
+ .4byte 0x1764
4483
+ .4byte 0x1715
4484
+ .uleb128 0x30
4485
+ .uleb128 0x1
4486
+ .byte 0x50
4487
+ .uleb128 0x2
4488
+ .byte 0x83
4489
+ .sleb128 0
4490
+ .byte 0
4491
+ .uleb128 0x3a
4492
+ .8byte .LVL116
4493
+ .4byte 0x22f4
4494
+ .uleb128 0x3a
4495
+ .8byte .LVL117
4496
+ .4byte 0x2317
4497
+ .uleb128 0x3a
4498
+ .8byte .LVL118
4499
+ .4byte 0x2323
4500
+ .uleb128 0x3a
4501
+ .8byte .LVL119
4502
+ .4byte 0x232f
4503
+ .uleb128 0x3a
4504
+ .8byte .LVL120
4505
+ .4byte 0x233b
4506
+ .uleb128 0x3a
4507
+ .8byte .LVL121
4508
+ .4byte 0x2347
4509
+ .byte 0
4510
+ .uleb128 0x31
4511
+ .4byte .LASF385
4512
+ .byte 0x1
4513
+ .2byte 0x1b1
4514
+ .8byte .LFB235
4515
+ .8byte .LFE235-.LFB235
4516
+ .uleb128 0x1
4517
+ .byte 0x9c
4518
+ .4byte 0x1844
4519
+ .uleb128 0x2e
4520
+ .string "cpu"
4521
+ .byte 0x1
4522
+ .2byte 0x1b1
4523
+ .4byte 0xa3
4524
+ .4byte .LLST42
4525
+ .uleb128 0x44
4526
+ .4byte .LASF375
4527
+ .byte 0x1
4528
+ .2byte 0x1b3
4529
+ .4byte 0x1844
4530
+ .4byte .LLST43
4531
+ .uleb128 0x45
4532
+ .string "i"
4533
+ .byte 0x1
4534
+ .2byte 0x1b4
4535
+ .4byte 0x54
4536
+ .4byte .LLST44
4537
+ .uleb128 0x46
4538
+ .4byte 0x1976
4539
+ .8byte .LBB98
4540
+ .4byte .Ldebug_ranges0+0x160
4541
+ .byte 0x1
4542
+ .2byte 0x1b8
4543
+ .uleb128 0x36
4544
+ .4byte 0x19aa
4545
+ .4byte .LLST45
4546
+ .uleb128 0x36
4547
+ .4byte 0x199e
4548
+ .4byte .LLST46
4549
+ .uleb128 0x36
4550
+ .4byte 0x1993
4551
+ .4byte .LLST47
4552
+ .uleb128 0x36
4553
+ .4byte 0x1987
4554
+ .4byte .LLST48
4555
+ .uleb128 0x33
4556
+ .4byte .Ldebug_ranges0+0x160
4557
+ .uleb128 0x38
4558
+ .4byte 0x19b6
4559
+ .uleb128 0x38
4560
+ .4byte 0x19c2
4561
+ .uleb128 0x35
4562
+ .4byte 0x19ce
4563
+ .4byte .LLST49
4564
+ .uleb128 0x35
4565
+ .4byte 0x19da
4566
+ .4byte .LLST50
4567
+ .uleb128 0x32
4568
+ .4byte 0x1ef0
4569
+ .8byte .LBB100
4570
+ .4byte .Ldebug_ranges0+0x190
4571
+ .byte 0x1
4572
+ .2byte 0x179
4573
+ .4byte 0x1827
4574
+ .uleb128 0x47
4575
+ .4byte 0x1f00
4576
+ .byte 0
4577
+ .uleb128 0x2f
4578
+ .8byte .LVL108
4579
+ .4byte 0x2014
4580
+ .uleb128 0x30
4581
+ .uleb128 0x1
4582
+ .byte 0x50
4583
+ .uleb128 0x2
4584
+ .byte 0x87
4585
+ .sleb128 0
4586
+ .uleb128 0x30
4587
+ .uleb128 0x1
4588
+ .byte 0x51
4589
+ .uleb128 0x2
4590
+ .byte 0x85
4591
+ .sleb128 0
4592
+ .byte 0
4593
+ .byte 0
4594
+ .byte 0
4595
+ .byte 0
4596
+ .uleb128 0x8
4597
+ .byte 0x8
4598
+ .4byte 0x120e
4599
+ .uleb128 0x31
4600
+ .4byte .LASF386
4601
+ .byte 0x1
4602
+ .2byte 0x1a3
4603
+ .8byte .LFB234
4604
+ .8byte .LFE234-.LFB234
4605
+ .uleb128 0x1
4606
+ .byte 0x9c
4607
+ .4byte 0x1976
4608
+ .uleb128 0x2e
4609
+ .string "cid"
4610
+ .byte 0x1
4611
+ .2byte 0x1a3
4612
+ .4byte 0xa3
4613
+ .4byte .LLST31
4614
+ .uleb128 0x2e
4615
+ .string "tid"
4616
+ .byte 0x1
4617
+ .2byte 0x1a3
4618
+ .4byte 0xa3
4619
+ .4byte .LLST32
4620
+ .uleb128 0x44
4621
+ .4byte .LASF375
4622
+ .byte 0x1
4623
+ .2byte 0x1a5
4624
+ .4byte 0x1844
4625
+ .4byte .LLST33
4626
+ .uleb128 0x45
4627
+ .string "i"
4628
+ .byte 0x1
4629
+ .2byte 0x1a6
4630
+ .4byte 0x54
4631
+ .4byte .LLST34
4632
+ .uleb128 0x32
4633
+ .4byte 0x1ef0
4634
+ .8byte .LBB86
4635
+ .4byte .Ldebug_ranges0+0x130
4636
+ .byte 0x1
4637
+ .2byte 0x1a8
4638
+ .4byte 0x18c8
4639
+ .uleb128 0x36
4640
+ .4byte 0x1f00
4641
+ .4byte .LLST35
4642
+ .byte 0
4643
+ .uleb128 0x48
4644
+ .4byte 0x1976
4645
+ .8byte .LBB90
4646
+ .8byte .LBE90-.LBB90
4647
+ .byte 0x1
4648
+ .2byte 0x1ad
4649
+ .uleb128 0x36
4650
+ .4byte 0x19aa
4651
+ .4byte .LLST36
4652
+ .uleb128 0x36
4653
+ .4byte 0x199e
4654
+ .4byte .LLST37
4655
+ .uleb128 0x36
4656
+ .4byte 0x1993
4657
+ .4byte .LLST38
4658
+ .uleb128 0x36
4659
+ .4byte 0x1987
4660
+ .4byte .LLST39
4661
+ .uleb128 0x49
4662
+ .8byte .LBB91
4663
+ .8byte .LBE91-.LBB91
4664
+ .uleb128 0x38
4665
+ .4byte 0x19b6
4666
+ .uleb128 0x38
4667
+ .4byte 0x19c2
4668
+ .uleb128 0x35
4669
+ .4byte 0x19ce
4670
+ .4byte .LLST40
4671
+ .uleb128 0x35
4672
+ .4byte 0x19da
4673
+ .4byte .LLST41
4674
+ .uleb128 0x3b
4675
+ .4byte 0x1ef0
4676
+ .8byte .LBB92
4677
+ .8byte .LBE92-.LBB92
4678
+ .byte 0x1
4679
+ .2byte 0x179
4680
+ .4byte 0x1953
4681
+ .uleb128 0x47
4682
+ .4byte 0x1f00
4683
+ .byte 0
4684
+ .uleb128 0x2f
4685
+ .8byte .LVL97
4686
+ .4byte 0x2014
4687
+ .uleb128 0x30
4688
+ .uleb128 0x1
4689
+ .byte 0x50
4690
+ .uleb128 0x2
4691
+ .byte 0x86
4692
+ .sleb128 0
4693
+ .uleb128 0x30
4694
+ .uleb128 0x1
4695
+ .byte 0x51
4696
+ .uleb128 0x2
4697
+ .byte 0x87
4698
+ .sleb128 0
4699
+ .uleb128 0x30
4700
+ .uleb128 0x1
4701
+ .byte 0x52
4702
+ .uleb128 0x2
4703
+ .byte 0x85
4704
+ .sleb128 0
4705
+ .byte 0
4706
+ .byte 0
4707
+ .byte 0
4708
+ .byte 0
4709
+ .uleb128 0x4a
4710
+ .4byte .LASF391
4711
+ .byte 0x1
4712
+ .2byte 0x172
4713
+ .4byte 0x54
4714
+ .byte 0x1
4715
+ .4byte 0x19e7
4716
+ .uleb128 0x4b
4717
+ .string "cid"
4718
+ .byte 0x1
4719
+ .2byte 0x172
4720
+ .4byte 0xa3
4721
+ .uleb128 0x4b
4722
+ .string "id"
4723
+ .byte 0x1
4724
+ .2byte 0x172
4725
+ .4byte 0x94
4726
+ .uleb128 0x4b
4727
+ .string "tid"
4728
+ .byte 0x1
4729
+ .2byte 0x172
4730
+ .4byte 0xa3
4731
+ .uleb128 0x4c
4732
+ .4byte .LASF372
4733
+ .byte 0x1
4734
+ .2byte 0x172
4735
+ .4byte 0xa3
4736
+ .uleb128 0x3f
4737
+ .4byte .LASF387
4738
+ .byte 0x1
4739
+ .2byte 0x174
4740
+ .4byte 0x8d
4741
+ .uleb128 0x3f
4742
+ .4byte .LASF388
4743
+ .byte 0x1
4744
+ .2byte 0x175
4745
+ .4byte 0x54
4746
+ .uleb128 0x40
4747
+ .string "ret"
4748
+ .byte 0x1
4749
+ .2byte 0x176
4750
+ .4byte 0x54
4751
+ .uleb128 0x40
4752
+ .string "run"
4753
+ .byte 0x1
4754
+ .2byte 0x177
4755
+ .4byte 0x54
4756
+ .byte 0
4757
+ .uleb128 0x2d
4758
+ .4byte .LASF390
4759
+ .byte 0x1
4760
+ .2byte 0x16d
4761
+ .4byte 0x54
4762
+ .8byte .LFB232
4763
+ .8byte .LFE232-.LFB232
4764
+ .uleb128 0x1
4765
+ .byte 0x9c
4766
+ .4byte 0x1aca
4767
+ .uleb128 0x2e
4768
+ .string "tid"
4769
+ .byte 0x1
4770
+ .2byte 0x16d
4771
+ .4byte 0xa3
4772
+ .4byte .LLST28
4773
+ .uleb128 0x46
4774
+ .4byte 0x1aca
4775
+ .8byte .LBB74
4776
+ .4byte .Ldebug_ranges0+0x100
4777
+ .byte 0x1
4778
+ .2byte 0x16f
4779
+ .uleb128 0x4d
4780
+ .4byte 0x1ae7
4781
+ .byte 0
4782
+ .uleb128 0x36
4783
+ .4byte 0x1adb
4784
+ .4byte .LLST29
4785
+ .uleb128 0x33
4786
+ .4byte .Ldebug_ranges0+0x100
4787
+ .uleb128 0x38
4788
+ .4byte 0x1af3
4789
+ .uleb128 0x3b
4790
+ .4byte 0x1fd7
4791
+ .8byte .LBB76
4792
+ .8byte .LBE76-.LBB76
4793
+ .byte 0x1
4794
+ .2byte 0x164
4795
+ .4byte 0x1a9a
4796
+ .uleb128 0x36
4797
+ .4byte 0x1fe3
4798
+ .4byte .LLST30
4799
+ .uleb128 0x39
4800
+ .8byte .LVL84
4801
+ .4byte 0x2300
4802
+ .4byte 0x1a84
4803
+ .uleb128 0x30
4804
+ .uleb128 0x1
4805
+ .byte 0x50
4806
+ .uleb128 0x3
4807
+ .byte 0xa
4808
+ .2byte 0x3e8
4809
+ .byte 0
4810
+ .uleb128 0x2f
4811
+ .8byte .LVL85
4812
+ .4byte 0x2300
4813
+ .uleb128 0x30
4814
+ .uleb128 0x1
4815
+ .byte 0x50
4816
+ .uleb128 0x3
4817
+ .byte 0xa
4818
+ .2byte 0x3e8
4819
+ .byte 0
4820
+ .byte 0
4821
+ .uleb128 0x39
4822
+ .8byte .LVL82
4823
+ .4byte 0x1ccc
4824
+ .4byte 0x1ab2
4825
+ .uleb128 0x30
4826
+ .uleb128 0x1
4827
+ .byte 0x50
4828
+ .uleb128 0x2
4829
+ .byte 0x83
4830
+ .sleb128 0
4831
+ .byte 0
4832
+ .uleb128 0x3c
4833
+ .8byte .LVL87
4834
+ .4byte 0x1ccc
4835
+ .uleb128 0x30
4836
+ .uleb128 0x1
4837
+ .byte 0x50
4838
+ .uleb128 0x3
4839
+ .byte 0xf3
4840
+ .uleb128 0x1
4841
+ .byte 0x50
4842
+ .byte 0
4843
+ .byte 0
4844
+ .byte 0
4845
+ .byte 0
4846
+ .uleb128 0x4a
4847
+ .4byte .LASF392
4848
+ .byte 0x1
4849
+ .2byte 0x15f
4850
+ .4byte 0x54
4851
+ .byte 0x1
4852
+ .4byte 0x1afe
4853
+ .uleb128 0x4b
4854
+ .string "tid"
4855
+ .byte 0x1
4856
+ .2byte 0x15f
4857
+ .4byte 0xa3
4858
+ .uleb128 0x4c
4859
+ .4byte .LASF393
4860
+ .byte 0x1
4861
+ .2byte 0x15f
4862
+ .4byte 0xa3
4863
+ .uleb128 0x40
4864
+ .string "i"
4865
+ .byte 0x1
4866
+ .2byte 0x161
4867
+ .4byte 0xa3
4868
+ .byte 0
4869
+ .uleb128 0x4a
4870
+ .4byte .LASF394
4871
+ .byte 0x1
4872
+ .2byte 0x138
4873
+ .4byte 0x54
4874
+ .byte 0x1
4875
+ .4byte 0x1b6d
4876
+ .uleb128 0x4b
4877
+ .string "cid"
4878
+ .byte 0x1
4879
+ .2byte 0x138
4880
+ .4byte 0xa3
4881
+ .uleb128 0x4b
4882
+ .string "tid"
4883
+ .byte 0x1
4884
+ .2byte 0x138
4885
+ .4byte 0xa3
4886
+ .uleb128 0x4c
4887
+ .4byte .LASF372
4888
+ .byte 0x1
4889
+ .2byte 0x138
4890
+ .4byte 0xa3
4891
+ .uleb128 0x3f
4892
+ .4byte .LASF388
4893
+ .byte 0x1
4894
+ .2byte 0x13a
4895
+ .4byte 0x54
4896
+ .uleb128 0x40
4897
+ .string "us"
4898
+ .byte 0x1
4899
+ .2byte 0x13b
4900
+ .4byte 0x54
4901
+ .uleb128 0x40
4902
+ .string "i"
4903
+ .byte 0x1
4904
+ .2byte 0x13c
4905
+ .4byte 0x54
4906
+ .uleb128 0x3f
4907
+ .4byte .LASF395
4908
+ .byte 0x1
4909
+ .2byte 0x13c
4910
+ .4byte 0x54
4911
+ .uleb128 0x3f
4912
+ .4byte .LASF396
4913
+ .byte 0x1
4914
+ .2byte 0x13d
4915
+ .4byte 0x54
4916
+ .byte 0
4917
+ .uleb128 0x31
4918
+ .4byte .LASF397
4919
+ .byte 0x1
4920
+ .2byte 0x121
4921
+ .8byte .LFB229
4922
+ .8byte .LFE229-.LFB229
4923
+ .uleb128 0x1
4924
+ .byte 0x9c
4925
+ .4byte 0x1ccc
4926
+ .uleb128 0x44
4927
+ .4byte .LASF375
4928
+ .byte 0x1
4929
+ .2byte 0x123
4930
+ .4byte 0x1844
4931
+ .4byte .LLST8
4932
+ .uleb128 0x45
4933
+ .string "cid"
4934
+ .byte 0x1
4935
+ .2byte 0x124
4936
+ .4byte 0x54
4937
+ .4byte .LLST9
4938
+ .uleb128 0x45
4939
+ .string "i"
4940
+ .byte 0x1
4941
+ .2byte 0x124
4942
+ .4byte 0x54
4943
+ .4byte .LLST10
4944
+ .uleb128 0x39
4945
+ .8byte .LVL24
4946
+ .4byte 0x22de
4947
+ .4byte 0x1bd8
4948
+ .uleb128 0x30
4949
+ .uleb128 0x1
4950
+ .byte 0x50
4951
+ .uleb128 0x9
4952
+ .byte 0x3
4953
+ .8byte .LC1
4954
+ .byte 0
4955
+ .uleb128 0x39
4956
+ .8byte .LVL27
4957
+ .4byte 0x22de
4958
+ .4byte 0x1bf6
4959
+ .uleb128 0x30
4960
+ .uleb128 0x1
4961
+ .byte 0x50
4962
+ .uleb128 0x2
4963
+ .byte 0x88
4964
+ .sleb128 0
4965
+ .uleb128 0x30
4966
+ .uleb128 0x1
4967
+ .byte 0x51
4968
+ .uleb128 0x2
4969
+ .byte 0x85
4970
+ .sleb128 0
4971
+ .byte 0
4972
+ .uleb128 0x39
4973
+ .8byte .LVL28
4974
+ .4byte 0x22de
4975
+ .4byte 0x1c15
4976
+ .uleb128 0x30
4977
+ .uleb128 0x1
4978
+ .byte 0x50
4979
+ .uleb128 0x9
4980
+ .byte 0x3
4981
+ .8byte .LC3
4982
+ .byte 0
4983
+ .uleb128 0x39
4984
+ .8byte .LVL29
4985
+ .4byte 0x22de
4986
+ .4byte 0x1c34
4987
+ .uleb128 0x30
4988
+ .uleb128 0x1
4989
+ .byte 0x50
4990
+ .uleb128 0x9
4991
+ .byte 0x3
4992
+ .8byte .LC4
4993
+ .byte 0
4994
+ .uleb128 0x39
4995
+ .8byte .LVL30
4996
+ .4byte 0x22de
4997
+ .4byte 0x1c53
4998
+ .uleb128 0x30
4999
+ .uleb128 0x1
5000
+ .byte 0x50
5001
+ .uleb128 0x9
5002
+ .byte 0x3
5003
+ .8byte .LC5
5004
+ .byte 0
5005
+ .uleb128 0x39
5006
+ .8byte .LVL31
5007
+ .4byte 0x22de
5008
+ .4byte 0x1c72
5009
+ .uleb128 0x30
5010
+ .uleb128 0x1
5011
+ .byte 0x50
5012
+ .uleb128 0x9
5013
+ .byte 0x3
5014
+ .8byte .LC6
5015
+ .byte 0
5016
+ .uleb128 0x39
5017
+ .8byte .LVL32
5018
+ .4byte 0x22de
5019
+ .4byte 0x1c91
5020
+ .uleb128 0x30
5021
+ .uleb128 0x1
5022
+ .byte 0x50
5023
+ .uleb128 0x9
5024
+ .byte 0x3
5025
+ .8byte .LC7
5026
+ .byte 0
5027
+ .uleb128 0x39
5028
+ .8byte .LVL33
5029
+ .4byte 0x22de
5030
+ .4byte 0x1cb0
5031
+ .uleb128 0x30
5032
+ .uleb128 0x1
5033
+ .byte 0x50
5034
+ .uleb128 0x9
5035
+ .byte 0x3
5036
+ .8byte .LC8
5037
+ .byte 0
5038
+ .uleb128 0x2f
5039
+ .8byte .LVL34
5040
+ .4byte 0x22de
5041
+ .uleb128 0x30
5042
+ .uleb128 0x1
5043
+ .byte 0x50
5044
+ .uleb128 0x9
5045
+ .byte 0x3
5046
+ .8byte .LC9
5047
+ .byte 0
5048
+ .byte 0
5049
+ .uleb128 0x2d
5050
+ .4byte .LASF398
5051
+ .byte 0x1
5052
+ .2byte 0x104
5053
+ .4byte 0x54
5054
+ .8byte .LFB228
5055
+ .8byte .LFE228-.LFB228
5056
+ .uleb128 0x1
5057
+ .byte 0x9c
5058
+ .4byte 0x1d65
5059
+ .uleb128 0x2e
5060
+ .string "tid"
5061
+ .byte 0x1
5062
+ .2byte 0x104
5063
+ .4byte 0xa3
5064
+ .4byte .LLST5
5065
+ .uleb128 0x40
5066
+ .string "cid"
5067
+ .byte 0x1
5068
+ .2byte 0x106
5069
+ .4byte 0x54
5070
+ .uleb128 0x45
5071
+ .string "i"
5072
+ .byte 0x1
5073
+ .2byte 0x106
5074
+ .4byte 0x54
5075
+ .4byte .LLST6
5076
+ .uleb128 0x45
5077
+ .string "ptr"
5078
+ .byte 0x1
5079
+ .2byte 0x107
5080
+ .4byte 0x1d65
5081
+ .4byte .LLST7
5082
+ .uleb128 0x3b
5083
+ .4byte 0x1ef0
5084
+ .8byte .LBB36
5085
+ .8byte .LBE36-.LBB36
5086
+ .byte 0x1
5087
+ .2byte 0x109
5088
+ .4byte 0x1d4a
5089
+ .uleb128 0x47
5090
+ .4byte 0x1f00
5091
+ .byte 0
5092
+ .uleb128 0x2f
5093
+ .8byte .LVL21
5094
+ .4byte 0x2353
5095
+ .uleb128 0x30
5096
+ .uleb128 0x1
5097
+ .byte 0x50
5098
+ .uleb128 0x2
5099
+ .byte 0x86
5100
+ .sleb128 0
5101
+ .uleb128 0x30
5102
+ .uleb128 0x1
5103
+ .byte 0x51
5104
+ .uleb128 0x2
5105
+ .byte 0x84
5106
+ .sleb128 0
5107
+ .byte 0
5108
+ .byte 0
5109
+ .uleb128 0x8
5110
+ .byte 0x8
5111
+ .4byte 0xa3
5112
+ .uleb128 0x4e
5113
+ .4byte .LASF431
5114
+ .byte 0x1
5115
+ .byte 0xe2
5116
+ .4byte 0x54
5117
+ .8byte .LFB227
5118
+ .8byte .LFE227-.LFB227
5119
+ .uleb128 0x1
5120
+ .byte 0x9c
5121
+ .4byte 0x1e38
5122
+ .uleb128 0x4f
5123
+ .string "cid"
5124
+ .byte 0x1
5125
+ .byte 0xe2
5126
+ .4byte 0xa3
5127
+ .4byte .LLST0
5128
+ .uleb128 0x4f
5129
+ .string "tid"
5130
+ .byte 0x1
5131
+ .byte 0xe2
5132
+ .4byte 0xa3
5133
+ .4byte .LLST1
5134
+ .uleb128 0x4f
5135
+ .string "st"
5136
+ .byte 0x1
5137
+ .byte 0xe2
5138
+ .4byte 0xa3
5139
+ .4byte .LLST2
5140
+ .uleb128 0x50
5141
+ .4byte .LASF31
5142
+ .byte 0x1
5143
+ .byte 0xe4
5144
+ .4byte 0xef
5145
+ .uleb128 0x2c
5146
+ .string "ptr"
5147
+ .byte 0x1
5148
+ .byte 0xe5
5149
+ .4byte 0x1d65
5150
+ .uleb128 0x2c
5151
+ .string "id"
5152
+ .byte 0x1
5153
+ .byte 0xe6
5154
+ .4byte 0x54
5155
+ .uleb128 0x51
5156
+ .4byte 0x1ef0
5157
+ .8byte .LBB30
5158
+ .8byte .LBE30-.LBB30
5159
+ .byte 0x1
5160
+ .byte 0xe8
5161
+ .4byte 0x1df9
5162
+ .uleb128 0x47
5163
+ .4byte 0x1f00
5164
+ .byte 0
5165
+ .uleb128 0x52
5166
+ .4byte 0x1e85
5167
+ .8byte .LBB32
5168
+ .4byte .Ldebug_ranges0+0
5169
+ .byte 0x1
5170
+ .byte 0xeb
5171
+ .4byte 0x1e2a
5172
+ .uleb128 0x47
5173
+ .4byte 0x1ea0
5174
+ .uleb128 0x47
5175
+ .4byte 0x1e95
5176
+ .uleb128 0x33
5177
+ .4byte .Ldebug_ranges0+0
5178
+ .uleb128 0x35
5179
+ .4byte 0x1eab
5180
+ .4byte .LLST3
5181
+ .byte 0
5182
+ .byte 0
5183
+ .uleb128 0x3a
5184
+ .8byte .LVL8
5185
+ .4byte 0x235f
5186
+ .byte 0
5187
+ .uleb128 0x53
5188
+ .4byte .LASF399
5189
+ .byte 0x1
5190
+ .byte 0xcf
5191
+ .4byte 0x54
5192
+ .byte 0x1
5193
+ .4byte 0x1e7f
5194
+ .uleb128 0x54
5195
+ .string "cid"
5196
+ .byte 0x1
5197
+ .byte 0xcf
5198
+ .4byte 0xa3
5199
+ .uleb128 0x54
5200
+ .string "tid"
5201
+ .byte 0x1
5202
+ .byte 0xcf
5203
+ .4byte 0xa3
5204
+ .uleb128 0x54
5205
+ .string "ret"
5206
+ .byte 0x1
5207
+ .byte 0xcf
5208
+ .4byte 0xa3
5209
+ .uleb128 0x2c
5210
+ .string "ptr"
5211
+ .byte 0x1
5212
+ .byte 0xd1
5213
+ .4byte 0x1e7f
5214
+ .uleb128 0x2c
5215
+ .string "id"
5216
+ .byte 0x1
5217
+ .byte 0xd2
5218
+ .4byte 0x54
5219
+ .byte 0
5220
+ .uleb128 0x8
5221
+ .byte 0x8
5222
+ .4byte 0x54
5223
+ .uleb128 0x53
5224
+ .4byte .LASF400
5225
+ .byte 0x1
5226
+ .byte 0xc3
5227
+ .4byte 0x54
5228
+ .byte 0x1
5229
+ .4byte 0x1eb5
5230
+ .uleb128 0x54
5231
+ .string "cid"
5232
+ .byte 0x1
5233
+ .byte 0xc3
5234
+ .4byte 0xa3
5235
+ .uleb128 0x54
5236
+ .string "tid"
5237
+ .byte 0x1
5238
+ .byte 0xc3
5239
+ .4byte 0xa3
5240
+ .uleb128 0x2c
5241
+ .string "i"
5242
+ .byte 0x1
5243
+ .byte 0xc5
5244
+ .4byte 0x54
5245
+ .byte 0
5246
+ .uleb128 0x53
5247
+ .4byte .LASF401
5248
+ .byte 0x1
5249
+ .byte 0x9d
5250
+ .4byte 0x54
5251
+ .byte 0x1
5252
+ .4byte 0x1ef0
5253
+ .uleb128 0x55
5254
+ .4byte .LASF383
5255
+ .byte 0x1
5256
+ .byte 0x9d
5257
+ .4byte 0x130d
5258
+ .uleb128 0x2c
5259
+ .string "cid"
5260
+ .byte 0x1
5261
+ .byte 0x9f
5262
+ .4byte 0xa3
5263
+ .uleb128 0x2c
5264
+ .string "tid"
5265
+ .byte 0x1
5266
+ .byte 0xa0
5267
+ .4byte 0xa3
5268
+ .uleb128 0x2c
5269
+ .string "i"
5270
+ .byte 0x1
5271
+ .byte 0xa1
5272
+ .4byte 0x94
5273
+ .byte 0
5274
+ .uleb128 0x53
5275
+ .4byte .LASF402
5276
+ .byte 0x1
5277
+ .byte 0x90
5278
+ .4byte 0x54
5279
+ .byte 0x3
5280
+ .4byte 0x1f0c
5281
+ .uleb128 0x54
5282
+ .string "tid"
5283
+ .byte 0x1
5284
+ .byte 0x90
5285
+ .4byte 0xa3
5286
+ .byte 0
5287
+ .uleb128 0x56
5288
+ .4byte .LASF411
5289
+ .byte 0x1
5290
+ .byte 0x86
5291
+ .byte 0x3
5292
+ .uleb128 0x57
5293
+ .4byte .LASF404
5294
+ .byte 0x1
5295
+ .byte 0x81
5296
+ .byte 0x3
5297
+ .4byte 0x1f2c
5298
+ .uleb128 0x54
5299
+ .string "ptr"
5300
+ .byte 0x1
5301
+ .byte 0x81
5302
+ .4byte 0x10b
5303
+ .byte 0
5304
+ .uleb128 0x58
5305
+ .4byte .LASF432
5306
+ .byte 0x1
5307
+ .byte 0x34
5308
+ .4byte 0x54
5309
+ .byte 0x1
5310
+ .4byte 0x1f48
5311
+ .uleb128 0x55
5312
+ .4byte .LASF405
5313
+ .byte 0x1
5314
+ .byte 0x34
5315
+ .4byte 0x1208
5316
+ .byte 0
5317
+ .uleb128 0x59
5318
+ .4byte .LASF406
5319
+ .byte 0x1
5320
+ .byte 0x33
5321
+ .4byte 0x54
5322
+ .4byte 0x1f63
5323
+ .uleb128 0x55
5324
+ .4byte .LASF405
5325
+ .byte 0x1
5326
+ .byte 0x33
5327
+ .4byte 0x1208
5328
+ .byte 0
5329
+ .uleb128 0x59
5330
+ .4byte .LASF407
5331
+ .byte 0x1
5332
+ .byte 0x32
5333
+ .4byte 0x54
5334
+ .4byte 0x1f7e
5335
+ .uleb128 0x55
5336
+ .4byte .LASF405
5337
+ .byte 0x1
5338
+ .byte 0x32
5339
+ .4byte 0x1208
5340
+ .byte 0
5341
+ .uleb128 0x59
5342
+ .4byte .LASF408
5343
+ .byte 0x1
5344
+ .byte 0x31
5345
+ .4byte 0x54
5346
+ .4byte 0x1f99
5347
+ .uleb128 0x55
5348
+ .4byte .LASF405
5349
+ .byte 0x1
5350
+ .byte 0x31
5351
+ .4byte 0x1208
5352
+ .byte 0
5353
+ .uleb128 0x59
5354
+ .4byte .LASF409
5355
+ .byte 0x1
5356
+ .byte 0x30
5357
+ .4byte 0x54
5358
+ .4byte 0x1fb4
5359
+ .uleb128 0x55
5360
+ .4byte .LASF405
5361
+ .byte 0x1
5362
+ .byte 0x30
5363
+ .4byte 0x1208
5364
+ .byte 0
5365
+ .uleb128 0x59
5366
+ .4byte .LASF410
5367
+ .byte 0x1
5368
+ .byte 0x2f
5369
+ .4byte 0x54
5370
+ .4byte 0x1fcf
5371
+ .uleb128 0x55
5372
+ .4byte .LASF405
5373
+ .byte 0x1
5374
+ .byte 0x2f
5375
+ .4byte 0x1208
5376
+ .byte 0
5377
+ .uleb128 0x56
5378
+ .4byte .LASF412
5379
+ .byte 0x3
5380
+ .byte 0xbf
5381
+ .byte 0x3
5382
+ .uleb128 0x57
5383
+ .4byte .LASF413
5384
+ .byte 0x2
5385
+ .byte 0xd
5386
+ .byte 0x3
5387
+ .4byte 0x1fef
5388
+ .uleb128 0x55
5389
+ .4byte .LASF414
5390
+ .byte 0x2
5391
+ .byte 0xd
5392
+ .4byte 0x3b
5393
+ .byte 0
5394
+ .uleb128 0x5a
5395
+ .4byte 0x1f2c
5396
+ .8byte .LFB220
5397
+ .8byte .LFE220-.LFB220
5398
+ .uleb128 0x1
5399
+ .byte 0x9c
5400
+ .4byte 0x2014
5401
+ .uleb128 0x36
5402
+ .4byte 0x1f3c
5403
+ .4byte .LLST4
5404
+ .byte 0
5405
+ .uleb128 0x5b
5406
+ .4byte 0x1976
5407
+ .8byte .LFB242
5408
+ .8byte .LFE242-.LFB242
5409
+ .uleb128 0x1
5410
+ .byte 0x9c
5411
+ .4byte 0x22d5
5412
+ .uleb128 0x36
5413
+ .4byte 0x1987
5414
+ .4byte .LLST11
5415
+ .uleb128 0x36
5416
+ .4byte 0x1993
5417
+ .4byte .LLST12
5418
+ .uleb128 0x36
5419
+ .4byte 0x199e
5420
+ .4byte .LLST13
5421
+ .uleb128 0x36
5422
+ .4byte 0x19aa
5423
+ .4byte .LLST14
5424
+ .uleb128 0x35
5425
+ .4byte 0x19b6
5426
+ .4byte .LLST15
5427
+ .uleb128 0x38
5428
+ .4byte 0x19c2
5429
+ .uleb128 0x35
5430
+ .4byte 0x19ce
5431
+ .4byte .LLST16
5432
+ .uleb128 0x35
5433
+ .4byte 0x19da
5434
+ .4byte .LLST17
5435
+ .uleb128 0x32
5436
+ .4byte 0x1afe
5437
+ .8byte .LBB48
5438
+ .4byte .Ldebug_ranges0+0x30
5439
+ .byte 0x1
5440
+ .2byte 0x17f
5441
+ .4byte 0x2128
5442
+ .uleb128 0x36
5443
+ .4byte 0x1b0f
5444
+ .4byte .LLST18
5445
+ .uleb128 0x36
5446
+ .4byte 0x1b1b
5447
+ .4byte .LLST19
5448
+ .uleb128 0x36
5449
+ .4byte 0x1b27
5450
+ .4byte .LLST20
5451
+ .uleb128 0x33
5452
+ .4byte .Ldebug_ranges0+0x30
5453
+ .uleb128 0x35
5454
+ .4byte 0x1b33
5455
+ .4byte .LLST21
5456
+ .uleb128 0x5c
5457
+ .4byte 0x1b3f
5458
+ .byte 0x64
5459
+ .uleb128 0x38
5460
+ .4byte 0x1b4a
5461
+ .uleb128 0x35
5462
+ .4byte 0x1b54
5463
+ .4byte .LLST22
5464
+ .uleb128 0x35
5465
+ .4byte 0x1b60
5466
+ .4byte .LLST23
5467
+ .uleb128 0x39
5468
+ .8byte .LVL41
5469
+ .4byte 0x1ccc
5470
+ .4byte 0x20e9
5471
+ .uleb128 0x30
5472
+ .uleb128 0x1
5473
+ .byte 0x50
5474
+ .uleb128 0x2
5475
+ .byte 0x85
5476
+ .sleb128 0
5477
+ .byte 0
5478
+ .uleb128 0x39
5479
+ .8byte .LVL42
5480
+ .4byte 0x1ccc
5481
+ .4byte 0x2101
5482
+ .uleb128 0x30
5483
+ .uleb128 0x1
5484
+ .byte 0x50
5485
+ .uleb128 0x2
5486
+ .byte 0x85
5487
+ .sleb128 0
5488
+ .byte 0
5489
+ .uleb128 0x39
5490
+ .8byte .LVL51
5491
+ .4byte 0x2300
5492
+ .4byte 0x2119
5493
+ .uleb128 0x30
5494
+ .uleb128 0x1
5495
+ .byte 0x50
5496
+ .uleb128 0x2
5497
+ .byte 0x8
5498
+ .byte 0x64
5499
+ .byte 0
5500
+ .uleb128 0x3a
5501
+ .8byte .LVL54
5502
+ .4byte 0x1b6d
5503
+ .byte 0
5504
+ .byte 0
5505
+ .uleb128 0x32
5506
+ .4byte 0x1e38
5507
+ .8byte .LBB52
5508
+ .4byte .Ldebug_ranges0+0x60
5509
+ .byte 0x1
5510
+ .2byte 0x19e
5511
+ .4byte 0x21cb
5512
+ .uleb128 0x36
5513
+ .4byte 0x1e5e
5514
+ .4byte .LLST24
5515
+ .uleb128 0x36
5516
+ .4byte 0x1e53
5517
+ .4byte .LLST25
5518
+ .uleb128 0x36
5519
+ .4byte 0x1e48
5520
+ .4byte .LLST26
5521
+ .uleb128 0x33
5522
+ .4byte .Ldebug_ranges0+0x60
5523
+ .uleb128 0x38
5524
+ .4byte 0x1e69
5525
+ .uleb128 0x38
5526
+ .4byte 0x1e74
5527
+ .uleb128 0x51
5528
+ .4byte 0x1ef0
5529
+ .8byte .LBB54
5530
+ .8byte .LBE54-.LBB54
5531
+ .byte 0x1
5532
+ .byte 0xd4
5533
+ .4byte 0x218b
5534
+ .uleb128 0x47
5535
+ .4byte 0x1f00
5536
+ .byte 0
5537
+ .uleb128 0x52
5538
+ .4byte 0x1e85
5539
+ .8byte .LBB56
5540
+ .4byte .Ldebug_ranges0+0xd0
5541
+ .byte 0x1
5542
+ .byte 0xd7
5543
+ .4byte 0x21bc
5544
+ .uleb128 0x47
5545
+ .4byte 0x1ea0
5546
+ .uleb128 0x47
5547
+ .4byte 0x1e95
5548
+ .uleb128 0x33
5549
+ .4byte .Ldebug_ranges0+0xd0
5550
+ .uleb128 0x35
5551
+ .4byte 0x1eab
5552
+ .4byte .LLST27
5553
+ .byte 0
5554
+ .byte 0
5555
+ .uleb128 0x5d
5556
+ .8byte .LVL79
5557
+ .4byte 0x235f
5558
+ .byte 0
5559
+ .byte 0
5560
+ .uleb128 0x39
5561
+ .8byte .LVL48
5562
+ .4byte 0x22de
5563
+ .4byte 0x21f6
5564
+ .uleb128 0x30
5565
+ .uleb128 0x1
5566
+ .byte 0x50
5567
+ .uleb128 0x9
5568
+ .byte 0x3
5569
+ .8byte .LC11
5570
+ .uleb128 0x30
5571
+ .uleb128 0x1
5572
+ .byte 0x51
5573
+ .uleb128 0x2
5574
+ .byte 0x83
5575
+ .sleb128 0
5576
+ .uleb128 0x30
5577
+ .uleb128 0x1
5578
+ .byte 0x52
5579
+ .uleb128 0x2
5580
+ .byte 0x84
5581
+ .sleb128 0
5582
+ .byte 0
5583
+ .uleb128 0x39
5584
+ .8byte .LVL49
5585
+ .4byte 0x1d6b
5586
+ .4byte 0x221d
5587
+ .uleb128 0x30
5588
+ .uleb128 0x1
5589
+ .byte 0x50
5590
+ .uleb128 0x2
5591
+ .byte 0x83
5592
+ .sleb128 0
5593
+ .uleb128 0x30
5594
+ .uleb128 0x1
5595
+ .byte 0x51
5596
+ .uleb128 0x2
5597
+ .byte 0x84
5598
+ .sleb128 0
5599
+ .uleb128 0x30
5600
+ .uleb128 0x1
5601
+ .byte 0x52
5602
+ .uleb128 0x5
5603
+ .byte 0xc
5604
+ .4byte 0x55555555
5605
+ .byte 0
5606
+ .uleb128 0x39
5607
+ .8byte .LVL57
5608
+ .4byte 0x22de
5609
+ .4byte 0x2248
5610
+ .uleb128 0x30
5611
+ .uleb128 0x1
5612
+ .byte 0x50
5613
+ .uleb128 0x9
5614
+ .byte 0x3
5615
+ .8byte .LC12
5616
+ .uleb128 0x30
5617
+ .uleb128 0x1
5618
+ .byte 0x51
5619
+ .uleb128 0x2
5620
+ .byte 0x83
5621
+ .sleb128 0
5622
+ .uleb128 0x30
5623
+ .uleb128 0x1
5624
+ .byte 0x52
5625
+ .uleb128 0x2
5626
+ .byte 0x84
5627
+ .sleb128 0
5628
+ .byte 0
5629
+ .uleb128 0x3a
5630
+ .8byte .LVL58
5631
+ .4byte 0x236b
5632
+ .uleb128 0x39
5633
+ .8byte .LVL61
5634
+ .4byte 0x1d6b
5635
+ .4byte 0x227c
5636
+ .uleb128 0x30
5637
+ .uleb128 0x1
5638
+ .byte 0x50
5639
+ .uleb128 0x2
5640
+ .byte 0x83
5641
+ .sleb128 0
5642
+ .uleb128 0x30
5643
+ .uleb128 0x1
5644
+ .byte 0x51
5645
+ .uleb128 0x2
5646
+ .byte 0x84
5647
+ .sleb128 0
5648
+ .uleb128 0x30
5649
+ .uleb128 0x1
5650
+ .byte 0x52
5651
+ .uleb128 0x5
5652
+ .byte 0xc
5653
+ .4byte 0x11111111
5654
+ .byte 0
5655
+ .uleb128 0x39
5656
+ .8byte .LVL65
5657
+ .4byte 0x1d6b
5658
+ .4byte 0x229a
5659
+ .uleb128 0x30
5660
+ .uleb128 0x1
5661
+ .byte 0x50
5662
+ .uleb128 0x2
5663
+ .byte 0x83
5664
+ .sleb128 0
5665
+ .uleb128 0x30
5666
+ .uleb128 0x1
5667
+ .byte 0x51
5668
+ .uleb128 0x2
5669
+ .byte 0x84
5670
+ .sleb128 0
5671
+ .byte 0
5672
+ .uleb128 0x3a
5673
+ .8byte .LVL66
5674
+ .4byte 0x236b
5675
+ .uleb128 0x2f
5676
+ .8byte .LVL68
5677
+ .4byte 0x22de
5678
+ .uleb128 0x30
5679
+ .uleb128 0x1
5680
+ .byte 0x50
5681
+ .uleb128 0x9
5682
+ .byte 0x3
5683
+ .8byte .LC10
5684
+ .uleb128 0x30
5685
+ .uleb128 0x1
5686
+ .byte 0x51
5687
+ .uleb128 0x2
5688
+ .byte 0x83
5689
+ .sleb128 0
5690
+ .uleb128 0x30
5691
+ .uleb128 0x1
5692
+ .byte 0x52
5693
+ .uleb128 0x2
5694
+ .byte 0x84
5695
+ .sleb128 0
5696
+ .uleb128 0x30
5697
+ .uleb128 0x1
5698
+ .byte 0x53
5699
+ .uleb128 0x2
5700
+ .byte 0x85
5701
+ .sleb128 0
5702
+ .byte 0
5703
+ .byte 0
5704
+ .uleb128 0x5e
5705
+ .4byte .LASF433
5706
+ .4byte .LASF433
5707
+ .uleb128 0x5f
5708
+ .4byte .LASF415
5709
+ .4byte .LASF415
5710
+ .byte 0x1d
5711
+ .byte 0x13
5712
+ .uleb128 0x5f
5713
+ .4byte .LASF416
5714
+ .4byte .LASF416
5715
+ .byte 0x8
5716
+ .byte 0x66
5717
+ .uleb128 0x60
5718
+ .4byte .LASF417
5719
+ .4byte .LASF417
5720
+ .byte 0x4
5721
+ .2byte 0x260
5722
+ .uleb128 0x5f
5723
+ .4byte .LASF418
5724
+ .4byte .LASF418
5725
+ .byte 0x2
5726
+ .byte 0xb
5727
+ .uleb128 0x60
5728
+ .4byte .LASF419
5729
+ .4byte .LASF419
5730
+ .byte 0x4
5731
+ .2byte 0x1f3
5732
+ .uleb128 0x60
5733
+ .4byte .LASF420
5734
+ .4byte .LASF420
5735
+ .byte 0x4
5736
+ .2byte 0x248
5737
+ .uleb128 0x60
5738
+ .4byte .LASF421
5739
+ .4byte .LASF421
5740
+ .byte 0x4
5741
+ .2byte 0x1f1
5742
+ .uleb128 0x60
5743
+ .4byte .LASF422
5744
+ .4byte .LASF422
5745
+ .byte 0x4
5746
+ .2byte 0x264
5747
+ .uleb128 0x60
5748
+ .4byte .LASF423
5749
+ .4byte .LASF423
5750
+ .byte 0x4
5751
+ .2byte 0x1f4
5752
+ .uleb128 0x60
5753
+ .4byte .LASF424
5754
+ .4byte .LASF424
5755
+ .byte 0x4
5756
+ .2byte 0x263
5757
+ .uleb128 0x60
5758
+ .4byte .LASF425
5759
+ .4byte .LASF425
5760
+ .byte 0x4
5761
+ .2byte 0x262
5762
+ .uleb128 0x60
5763
+ .4byte .LASF426
5764
+ .4byte .LASF426
5765
+ .byte 0x4
5766
+ .2byte 0x261
5767
+ .uleb128 0x60
5768
+ .4byte .LASF427
5769
+ .4byte .LASF427
5770
+ .byte 0x4
5771
+ .2byte 0x276
5772
+ .byte 0
5773
+ .section .debug_abbrev,"",@progbits
5774
+.Ldebug_abbrev0:
5775
+ .uleb128 0x1
5776
+ .uleb128 0x11
5777
+ .byte 0x1
5778
+ .uleb128 0x25
5779
+ .uleb128 0xe
5780
+ .uleb128 0x13
5781
+ .uleb128 0xb
5782
+ .uleb128 0x3
5783
+ .uleb128 0xe
5784
+ .uleb128 0x1b
5785
+ .uleb128 0xe
5786
+ .uleb128 0x55
5787
+ .uleb128 0x17
5788
+ .uleb128 0x11
5789
+ .uleb128 0x1
5790
+ .uleb128 0x10
5791
+ .uleb128 0x17
5792
+ .byte 0
5793
+ .byte 0
5794
+ .uleb128 0x2
5795
+ .uleb128 0x16
5796
+ .byte 0
5797
+ .uleb128 0x3
5798
+ .uleb128 0xe
5799
+ .uleb128 0x3a
5800
+ .uleb128 0xb
5801
+ .uleb128 0x3b
5802
+ .uleb128 0xb
5803
+ .uleb128 0x49
5804
+ .uleb128 0x13
5805
+ .byte 0
5806
+ .byte 0
5807
+ .uleb128 0x3
5808
+ .uleb128 0x24
5809
+ .byte 0
5810
+ .uleb128 0xb
5811
+ .uleb128 0xb
5812
+ .uleb128 0x3e
5813
+ .uleb128 0xb
5814
+ .uleb128 0x3
5815
+ .uleb128 0xe
5816
+ .byte 0
5817
+ .byte 0
5818
+ .uleb128 0x4
5819
+ .uleb128 0x34
5820
+ .byte 0
5821
+ .uleb128 0x3
5822
+ .uleb128 0xe
5823
+ .uleb128 0x3a
5824
+ .uleb128 0xb
5825
+ .uleb128 0x3b
5826
+ .uleb128 0xb
5827
+ .uleb128 0x49
5828
+ .uleb128 0x13
5829
+ .uleb128 0x3f
5830
+ .uleb128 0x19
5831
+ .uleb128 0x3c
5832
+ .uleb128 0x19
5833
+ .byte 0
5834
+ .byte 0
5835
+ .uleb128 0x5
5836
+ .uleb128 0x24
5837
+ .byte 0
5838
+ .uleb128 0xb
5839
+ .uleb128 0xb
5840
+ .uleb128 0x3e
5841
+ .uleb128 0xb
5842
+ .uleb128 0x3
5843
+ .uleb128 0x8
5844
+ .byte 0
5845
+ .byte 0
5846
+ .uleb128 0x6
5847
+ .uleb128 0x16
5848
+ .byte 0
5849
+ .uleb128 0x3
5850
+ .uleb128 0x8
5851
+ .uleb128 0x3a
5852
+ .uleb128 0xb
5853
+ .uleb128 0x3b
5854
+ .uleb128 0xb
5855
+ .uleb128 0x49
5856
+ .uleb128 0x13
5857
+ .byte 0
5858
+ .byte 0
5859
+ .uleb128 0x7
5860
+ .uleb128 0x26
5861
+ .byte 0
5862
+ .uleb128 0x49
5863
+ .uleb128 0x13
5864
+ .byte 0
5865
+ .byte 0
5866
+ .uleb128 0x8
5867
+ .uleb128 0xf
5868
+ .byte 0
5869
+ .uleb128 0xb
5870
+ .uleb128 0xb
5871
+ .uleb128 0x49
5872
+ .uleb128 0x13
5873
+ .byte 0
5874
+ .byte 0
5875
+ .uleb128 0x9
5876
+ .uleb128 0x35
5877
+ .byte 0
5878
+ .uleb128 0x49
5879
+ .uleb128 0x13
5880
+ .byte 0
5881
+ .byte 0
5882
+ .uleb128 0xa
5883
+ .uleb128 0xf
5884
+ .byte 0
5885
+ .uleb128 0xb
5886
+ .uleb128 0xb
5887
+ .byte 0
5888
+ .byte 0
5889
+ .uleb128 0xb
5890
+ .uleb128 0x1
5891
+ .byte 0x1
5892
+ .uleb128 0x49
5893
+ .uleb128 0x13
5894
+ .uleb128 0x1
5895
+ .uleb128 0x13
5896
+ .byte 0
5897
+ .byte 0
5898
+ .uleb128 0xc
5899
+ .uleb128 0x21
5900
+ .byte 0
5901
+ .byte 0
5902
+ .byte 0
5903
+ .uleb128 0xd
5904
+ .uleb128 0x34
5905
+ .byte 0
5906
+ .uleb128 0x3
5907
+ .uleb128 0xe
5908
+ .uleb128 0x3a
5909
+ .uleb128 0xb
5910
+ .uleb128 0x3b
5911
+ .uleb128 0x5
5912
+ .uleb128 0x49
5913
+ .uleb128 0x13
5914
+ .uleb128 0x3f
5915
+ .uleb128 0x19
5916
+ .uleb128 0x3c
5917
+ .uleb128 0x19
5918
+ .byte 0
5919
+ .byte 0
5920
+ .uleb128 0xe
5921
+ .uleb128 0x13
5922
+ .byte 0
5923
+ .uleb128 0x3
5924
+ .uleb128 0xe
5925
+ .uleb128 0x3c
5926
+ .uleb128 0x19
5927
+ .byte 0
5928
+ .byte 0
5929
+ .uleb128 0xf
5930
+ .uleb128 0x26
5931
+ .byte 0
5932
+ .byte 0
5933
+ .byte 0
5934
+ .uleb128 0x10
5935
+ .uleb128 0x21
5936
+ .byte 0
5937
+ .uleb128 0x49
5938
+ .uleb128 0x13
5939
+ .uleb128 0x2f
5940
+ .uleb128 0xb
5941
+ .byte 0
5942
+ .byte 0
5943
+ .uleb128 0x11
5944
+ .uleb128 0x13
5945
+ .byte 0x1
5946
+ .uleb128 0x3
5947
+ .uleb128 0xe
5948
+ .uleb128 0xb
5949
+ .uleb128 0xb
5950
+ .uleb128 0x3a
5951
+ .uleb128 0xb
5952
+ .uleb128 0x3b
5953
+ .uleb128 0xb
5954
+ .uleb128 0x1
5955
+ .uleb128 0x13
5956
+ .byte 0
5957
+ .byte 0
5958
+ .uleb128 0x12
5959
+ .uleb128 0xd
5960
+ .byte 0
5961
+ .uleb128 0x3
5962
+ .uleb128 0xe
5963
+ .uleb128 0x3a
5964
+ .uleb128 0xb
5965
+ .uleb128 0x3b
5966
+ .uleb128 0xb
5967
+ .uleb128 0x49
5968
+ .uleb128 0x13
5969
+ .uleb128 0x38
5970
+ .uleb128 0xb
5971
+ .byte 0
5972
+ .byte 0
5973
+ .uleb128 0x13
5974
+ .uleb128 0x15
5975
+ .byte 0x1
5976
+ .uleb128 0x27
5977
+ .uleb128 0x19
5978
+ .uleb128 0x49
5979
+ .uleb128 0x13
5980
+ .uleb128 0x1
5981
+ .uleb128 0x13
5982
+ .byte 0
5983
+ .byte 0
5984
+ .uleb128 0x14
5985
+ .uleb128 0x5
5986
+ .byte 0
5987
+ .uleb128 0x49
5988
+ .uleb128 0x13
5989
+ .byte 0
5990
+ .byte 0
5991
+ .uleb128 0x15
5992
+ .uleb128 0x13
5993
+ .byte 0x1
5994
+ .uleb128 0xb
5995
+ .uleb128 0x5
5996
+ .uleb128 0x3a
5997
+ .uleb128 0xb
5998
+ .uleb128 0x3b
5999
+ .uleb128 0xb
6000
+ .uleb128 0x1
6001
+ .uleb128 0x13
6002
+ .byte 0
6003
+ .byte 0
6004
+ .uleb128 0x16
6005
+ .uleb128 0xd
6006
+ .byte 0
6007
+ .uleb128 0x3
6008
+ .uleb128 0xe
6009
+ .uleb128 0x3a
6010
+ .uleb128 0xb
6011
+ .uleb128 0x3b
6012
+ .uleb128 0xb
6013
+ .uleb128 0x49
6014
+ .uleb128 0x13
6015
+ .uleb128 0x38
6016
+ .uleb128 0x5
6017
+ .byte 0
6018
+ .byte 0
6019
+ .uleb128 0x17
6020
+ .uleb128 0xd
6021
+ .byte 0
6022
+ .uleb128 0x3
6023
+ .uleb128 0x8
6024
+ .uleb128 0x3a
6025
+ .uleb128 0xb
6026
+ .uleb128 0x3b
6027
+ .uleb128 0xb
6028
+ .uleb128 0x49
6029
+ .uleb128 0x13
6030
+ .uleb128 0x38
6031
+ .uleb128 0x5
6032
+ .byte 0
6033
+ .byte 0
6034
+ .uleb128 0x18
6035
+ .uleb128 0x21
6036
+ .byte 0
6037
+ .uleb128 0x49
6038
+ .uleb128 0x13
6039
+ .uleb128 0x2f
6040
+ .uleb128 0x5
6041
+ .byte 0
6042
+ .byte 0
6043
+ .uleb128 0x19
6044
+ .uleb128 0x13
6045
+ .byte 0x1
6046
+ .uleb128 0x3
6047
+ .uleb128 0xe
6048
+ .uleb128 0xb
6049
+ .uleb128 0x5
6050
+ .uleb128 0x3a
6051
+ .uleb128 0xb
6052
+ .uleb128 0x3b
6053
+ .uleb128 0xb
6054
+ .uleb128 0x1
6055
+ .uleb128 0x13
6056
+ .byte 0
6057
+ .byte 0
6058
+ .uleb128 0x1a
6059
+ .uleb128 0xd
6060
+ .byte 0
6061
+ .uleb128 0x3
6062
+ .uleb128 0x8
6063
+ .uleb128 0x3a
6064
+ .uleb128 0xb
6065
+ .uleb128 0x3b
6066
+ .uleb128 0xb
6067
+ .uleb128 0x49
6068
+ .uleb128 0x13
6069
+ .uleb128 0x38
6070
+ .uleb128 0xb
6071
+ .byte 0
6072
+ .byte 0
6073
+ .uleb128 0x1b
6074
+ .uleb128 0x13
6075
+ .byte 0x1
6076
+ .uleb128 0x3
6077
+ .uleb128 0x8
6078
+ .uleb128 0xb
6079
+ .uleb128 0x5
6080
+ .uleb128 0x3a
6081
+ .uleb128 0xb
6082
+ .uleb128 0x3b
6083
+ .uleb128 0xb
6084
+ .uleb128 0x1
6085
+ .uleb128 0x13
6086
+ .byte 0
6087
+ .byte 0
6088
+ .uleb128 0x1c
6089
+ .uleb128 0x34
6090
+ .byte 0
6091
+ .uleb128 0x3
6092
+ .uleb128 0x8
6093
+ .uleb128 0x3a
6094
+ .uleb128 0xb
6095
+ .uleb128 0x3b
6096
+ .uleb128 0xb
6097
+ .uleb128 0x49
6098
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+ .uleb128 0x8
6718
+ .uleb128 0x3a
6719
+ .uleb128 0xb
6720
+ .uleb128 0x3b
6721
+ .uleb128 0x5
6722
+ .uleb128 0x49
6723
+ .uleb128 0x13
6724
+ .byte 0
6725
+ .byte 0
6726
+ .uleb128 0x4c
6727
+ .uleb128 0x5
6728
+ .byte 0
6729
+ .uleb128 0x3
6730
+ .uleb128 0xe
6731
+ .uleb128 0x3a
6732
+ .uleb128 0xb
6733
+ .uleb128 0x3b
6734
+ .uleb128 0x5
6735
+ .uleb128 0x49
6736
+ .uleb128 0x13
6737
+ .byte 0
6738
+ .byte 0
6739
+ .uleb128 0x4d
6740
+ .uleb128 0x5
6741
+ .byte 0
6742
+ .uleb128 0x31
6743
+ .uleb128 0x13
6744
+ .uleb128 0x1c
6745
+ .uleb128 0xb
6746
+ .byte 0
6747
+ .byte 0
6748
+ .uleb128 0x4e
6749
+ .uleb128 0x2e
6750
+ .byte 0x1
6751
+ .uleb128 0x3
6752
+ .uleb128 0xe
6753
+ .uleb128 0x3a
6754
+ .uleb128 0xb
6755
+ .uleb128 0x3b
6756
+ .uleb128 0xb
6757
+ .uleb128 0x27
6758
+ .uleb128 0x19
6759
+ .uleb128 0x49
6760
+ .uleb128 0x13
6761
+ .uleb128 0x11
6762
+ .uleb128 0x1
6763
+ .uleb128 0x12
6764
+ .uleb128 0x7
6765
+ .uleb128 0x40
6766
+ .uleb128 0x18
6767
+ .uleb128 0x2117
6768
+ .uleb128 0x19
6769
+ .uleb128 0x1
6770
+ .uleb128 0x13
6771
+ .byte 0
6772
+ .byte 0
6773
+ .uleb128 0x4f
6774
+ .uleb128 0x5
6775
+ .byte 0
6776
+ .uleb128 0x3
6777
+ .uleb128 0x8
6778
+ .uleb128 0x3a
6779
+ .uleb128 0xb
6780
+ .uleb128 0x3b
6781
+ .uleb128 0xb
6782
+ .uleb128 0x49
6783
+ .uleb128 0x13
6784
+ .uleb128 0x2
6785
+ .uleb128 0x17
6786
+ .byte 0
6787
+ .byte 0
6788
+ .uleb128 0x50
6789
+ .uleb128 0x34
6790
+ .byte 0
6791
+ .uleb128 0x3
6792
+ .uleb128 0xe
6793
+ .uleb128 0x3a
6794
+ .uleb128 0xb
6795
+ .uleb128 0x3b
6796
+ .uleb128 0xb
6797
+ .uleb128 0x49
6798
+ .uleb128 0x13
6799
+ .byte 0
6800
+ .byte 0
6801
+ .uleb128 0x51
6802
+ .uleb128 0x1d
6803
+ .byte 0x1
6804
+ .uleb128 0x31
6805
+ .uleb128 0x13
6806
+ .uleb128 0x11
6807
+ .uleb128 0x1
6808
+ .uleb128 0x12
6809
+ .uleb128 0x7
6810
+ .uleb128 0x58
6811
+ .uleb128 0xb
6812
+ .uleb128 0x59
6813
+ .uleb128 0xb
6814
+ .uleb128 0x1
6815
+ .uleb128 0x13
6816
+ .byte 0
6817
+ .byte 0
6818
+ .uleb128 0x52
6819
+ .uleb128 0x1d
6820
+ .byte 0x1
6821
+ .uleb128 0x31
6822
+ .uleb128 0x13
6823
+ .uleb128 0x52
6824
+ .uleb128 0x1
6825
+ .uleb128 0x55
6826
+ .uleb128 0x17
6827
+ .uleb128 0x58
6828
+ .uleb128 0xb
6829
+ .uleb128 0x59
6830
+ .uleb128 0xb
6831
+ .uleb128 0x1
6832
+ .uleb128 0x13
6833
+ .byte 0
6834
+ .byte 0
6835
+ .uleb128 0x53
6836
+ .uleb128 0x2e
6837
+ .byte 0x1
6838
+ .uleb128 0x3
6839
+ .uleb128 0xe
6840
+ .uleb128 0x3a
6841
+ .uleb128 0xb
6842
+ .uleb128 0x3b
6843
+ .uleb128 0xb
6844
+ .uleb128 0x27
6845
+ .uleb128 0x19
6846
+ .uleb128 0x49
6847
+ .uleb128 0x13
6848
+ .uleb128 0x20
6849
+ .uleb128 0xb
6850
+ .uleb128 0x1
6851
+ .uleb128 0x13
6852
+ .byte 0
6853
+ .byte 0
6854
+ .uleb128 0x54
6855
+ .uleb128 0x5
6856
+ .byte 0
6857
+ .uleb128 0x3
6858
+ .uleb128 0x8
6859
+ .uleb128 0x3a
6860
+ .uleb128 0xb
6861
+ .uleb128 0x3b
6862
+ .uleb128 0xb
6863
+ .uleb128 0x49
6864
+ .uleb128 0x13
6865
+ .byte 0
6866
+ .byte 0
6867
+ .uleb128 0x55
6868
+ .uleb128 0x5
6869
+ .byte 0
6870
+ .uleb128 0x3
6871
+ .uleb128 0xe
6872
+ .uleb128 0x3a
6873
+ .uleb128 0xb
6874
+ .uleb128 0x3b
6875
+ .uleb128 0xb
6876
+ .uleb128 0x49
6877
+ .uleb128 0x13
6878
+ .byte 0
6879
+ .byte 0
6880
+ .uleb128 0x56
6881
+ .uleb128 0x2e
6882
+ .byte 0
6883
+ .uleb128 0x3
6884
+ .uleb128 0xe
6885
+ .uleb128 0x3a
6886
+ .uleb128 0xb
6887
+ .uleb128 0x3b
6888
+ .uleb128 0xb
6889
+ .uleb128 0x27
6890
+ .uleb128 0x19
6891
+ .uleb128 0x20
6892
+ .uleb128 0xb
6893
+ .byte 0
6894
+ .byte 0
6895
+ .uleb128 0x57
6896
+ .uleb128 0x2e
6897
+ .byte 0x1
6898
+ .uleb128 0x3
6899
+ .uleb128 0xe
6900
+ .uleb128 0x3a
6901
+ .uleb128 0xb
6902
+ .uleb128 0x3b
6903
+ .uleb128 0xb
6904
+ .uleb128 0x27
6905
+ .uleb128 0x19
6906
+ .uleb128 0x20
6907
+ .uleb128 0xb
6908
+ .uleb128 0x1
6909
+ .uleb128 0x13
6910
+ .byte 0
6911
+ .byte 0
6912
+ .uleb128 0x58
6913
+ .uleb128 0x2e
6914
+ .byte 0x1
6915
+ .uleb128 0x3f
6916
+ .uleb128 0x19
6917
+ .uleb128 0x3
6918
+ .uleb128 0xe
6919
+ .uleb128 0x3a
6920
+ .uleb128 0xb
6921
+ .uleb128 0x3b
6922
+ .uleb128 0xb
6923
+ .uleb128 0x27
6924
+ .uleb128 0x19
6925
+ .uleb128 0x49
6926
+ .uleb128 0x13
6927
+ .uleb128 0x20
6928
+ .uleb128 0xb
6929
+ .uleb128 0x1
6930
+ .uleb128 0x13
6931
+ .byte 0
6932
+ .byte 0
6933
+ .uleb128 0x59
6934
+ .uleb128 0x2e
6935
+ .byte 0x1
6936
+ .uleb128 0x3f
6937
+ .uleb128 0x19
6938
+ .uleb128 0x3
6939
+ .uleb128 0xe
6940
+ .uleb128 0x3a
6941
+ .uleb128 0xb
6942
+ .uleb128 0x3b
6943
+ .uleb128 0xb
6944
+ .uleb128 0x27
6945
+ .uleb128 0x19
6946
+ .uleb128 0x49
6947
+ .uleb128 0x13
6948
+ .uleb128 0x1
6949
+ .uleb128 0x13
6950
+ .byte 0
6951
+ .byte 0
6952
+ .uleb128 0x5a
6953
+ .uleb128 0x2e
6954
+ .byte 0x1
6955
+ .uleb128 0x31
6956
+ .uleb128 0x13
6957
+ .uleb128 0x11
6958
+ .uleb128 0x1
6959
+ .uleb128 0x12
6960
+ .uleb128 0x7
6961
+ .uleb128 0x40
6962
+ .uleb128 0x18
6963
+ .uleb128 0x2117
6964
+ .uleb128 0x19
6965
+ .uleb128 0x1
6966
+ .uleb128 0x13
6967
+ .byte 0
6968
+ .byte 0
6969
+ .uleb128 0x5b
6970
+ .uleb128 0x2e
6971
+ .byte 0x1
6972
+ .uleb128 0x31
6973
+ .uleb128 0x13
6974
+ .uleb128 0x11
6975
+ .uleb128 0x1
6976
+ .uleb128 0x12
6977
+ .uleb128 0x7
6978
+ .uleb128 0x40
6979
+ .uleb128 0x18
6980
+ .uleb128 0x2116
6981
+ .uleb128 0x19
6982
+ .uleb128 0x1
6983
+ .uleb128 0x13
6984
+ .byte 0
6985
+ .byte 0
6986
+ .uleb128 0x5c
6987
+ .uleb128 0x34
6988
+ .byte 0
6989
+ .uleb128 0x31
6990
+ .uleb128 0x13
6991
+ .uleb128 0x1c
6992
+ .uleb128 0xb
6993
+ .byte 0
6994
+ .byte 0
6995
+ .uleb128 0x5d
6996
+ .uleb128 0x4109
6997
+ .byte 0
6998
+ .uleb128 0x11
6999
+ .uleb128 0x1
7000
+ .uleb128 0x2115
7001
+ .uleb128 0x19
7002
+ .uleb128 0x31
7003
+ .uleb128 0x13
7004
+ .byte 0
7005
+ .byte 0
7006
+ .uleb128 0x5e
7007
+ .uleb128 0x2e
7008
+ .byte 0
7009
+ .uleb128 0x3f
7010
+ .uleb128 0x19
7011
+ .uleb128 0x3c
7012
+ .uleb128 0x19
7013
+ .uleb128 0x6e
7014
+ .uleb128 0xe
7015
+ .uleb128 0x3
7016
+ .uleb128 0xe
7017
+ .byte 0
7018
+ .byte 0
7019
+ .uleb128 0x5f
7020
+ .uleb128 0x2e
7021
+ .byte 0
7022
+ .uleb128 0x3f
7023
+ .uleb128 0x19
7024
+ .uleb128 0x3c
7025
+ .uleb128 0x19
7026
+ .uleb128 0x6e
7027
+ .uleb128 0xe
7028
+ .uleb128 0x3
7029
+ .uleb128 0xe
7030
+ .uleb128 0x3a
7031
+ .uleb128 0xb
7032
+ .uleb128 0x3b
7033
+ .uleb128 0xb
7034
+ .byte 0
7035
+ .byte 0
7036
+ .uleb128 0x60
7037
+ .uleb128 0x2e
7038
+ .byte 0
7039
+ .uleb128 0x3f
7040
+ .uleb128 0x19
7041
+ .uleb128 0x3c
7042
+ .uleb128 0x19
7043
+ .uleb128 0x6e
7044
+ .uleb128 0xe
7045
+ .uleb128 0x3
7046
+ .uleb128 0xe
7047
+ .uleb128 0x3a
7048
+ .uleb128 0xb
7049
+ .uleb128 0x3b
7050
+ .uleb128 0x5
7051
+ .byte 0
7052
+ .byte 0
7053
+ .byte 0
7054
+ .section .debug_loc,"",@progbits
7055
+.Ldebug_loc0:
7056
+.LLST61:
7057
+ .8byte .LVL151
7058
+ .8byte .LVL152
7059
+ .2byte 0x1
7060
+ .byte 0x50
7061
+ .8byte .LVL152
7062
+ .8byte .LVL154
7063
+ .2byte 0x4
7064
+ .byte 0xf3
7065
+ .uleb128 0x1
7066
+ .byte 0x50
7067
+ .byte 0x9f
7068
+ .8byte .LVL154
7069
+ .8byte .LVL155
7070
+ .2byte 0x1
7071
+ .byte 0x50
7072
+ .8byte .LVL155
7073
+ .8byte .LFE240
7074
+ .2byte 0x4
7075
+ .byte 0xf3
7076
+ .uleb128 0x1
7077
+ .byte 0x50
7078
+ .byte 0x9f
7079
+ .8byte 0
7080
+ .8byte 0
7081
+.LLST53:
7082
+ .8byte .LVL126
7083
+ .8byte .LVL127
7084
+ .2byte 0x1
7085
+ .byte 0x50
7086
+ .8byte .LVL127
7087
+ .8byte .LVL143
7088
+ .2byte 0x4
7089
+ .byte 0xf3
7090
+ .uleb128 0x1
7091
+ .byte 0x50
7092
+ .byte 0x9f
7093
+ .8byte .LVL143
7094
+ .8byte .LVL144
7095
+ .2byte 0x1
7096
+ .byte 0x50
7097
+ .8byte .LVL144
7098
+ .8byte .LVL148
7099
+ .2byte 0x4
7100
+ .byte 0xf3
7101
+ .uleb128 0x1
7102
+ .byte 0x50
7103
+ .byte 0x9f
7104
+ .8byte .LVL148
7105
+ .8byte .LVL149
7106
+ .2byte 0x1
7107
+ .byte 0x50
7108
+ .8byte .LVL149
7109
+ .8byte .LFE239
7110
+ .2byte 0x4
7111
+ .byte 0xf3
7112
+ .uleb128 0x1
7113
+ .byte 0x50
7114
+ .byte 0x9f
7115
+ .8byte 0
7116
+ .8byte 0
7117
+.LLST54:
7118
+ .8byte .LVL131
7119
+ .8byte .LVL132
7120
+ .2byte 0x2
7121
+ .byte 0x30
7122
+ .byte 0x9f
7123
+ .8byte 0
7124
+ .8byte 0
7125
+.LLST55:
7126
+ .8byte .LVL136
7127
+ .8byte .LVL137
7128
+ .2byte 0x7
7129
+ .byte 0x93
7130
+ .uleb128 0x4
7131
+ .byte 0x53
7132
+ .byte 0x93
7133
+ .uleb128 0x4
7134
+ .byte 0x93
7135
+ .uleb128 0x10
7136
+ .8byte .LVL137
7137
+ .8byte .LVL141
7138
+ .2byte 0xe
7139
+ .byte 0x93
7140
+ .uleb128 0x4
7141
+ .byte 0x53
7142
+ .byte 0x93
7143
+ .uleb128 0x4
7144
+ .byte 0x5d
7145
+ .byte 0x93
7146
+ .uleb128 0x8
7147
+ .byte 0x5c
7148
+ .byte 0x93
7149
+ .uleb128 0x4
7150
+ .byte 0x5b
7151
+ .byte 0x93
7152
+ .uleb128 0x4
7153
+ .8byte .LVL141
7154
+ .8byte .LVL142
7155
+ .2byte 0xf
7156
+ .byte 0x93
7157
+ .uleb128 0x4
7158
+ .byte 0x71
7159
+ .sleb128 20
7160
+ .byte 0x93
7161
+ .uleb128 0x4
7162
+ .byte 0x5d
7163
+ .byte 0x93
7164
+ .uleb128 0x8
7165
+ .byte 0x5c
7166
+ .byte 0x93
7167
+ .uleb128 0x4
7168
+ .byte 0x5b
7169
+ .byte 0x93
7170
+ .uleb128 0x4
7171
+ .8byte .LVL142
7172
+ .8byte .LVL143
7173
+ .2byte 0xb
7174
+ .byte 0x93
7175
+ .uleb128 0x8
7176
+ .byte 0x5d
7177
+ .byte 0x93
7178
+ .uleb128 0x8
7179
+ .byte 0x5c
7180
+ .byte 0x93
7181
+ .uleb128 0x4
7182
+ .byte 0x5b
7183
+ .byte 0x93
7184
+ .uleb128 0x4
7185
+ .8byte 0
7186
+ .8byte 0
7187
+.LLST56:
7188
+ .8byte .LVL137
7189
+ .8byte .LVL139
7190
+ .2byte 0x1
7191
+ .byte 0x51
7192
+ .8byte .LVL139
7193
+ .8byte .LVL140
7194
+ .2byte 0x2
7195
+ .byte 0x70
7196
+ .sleb128 0
7197
+ .8byte 0
7198
+ .8byte 0
7199
+.LLST57:
7200
+ .8byte .LVL137
7201
+ .8byte .LVL141
7202
+ .2byte 0x1
7203
+ .byte 0x53
7204
+ .8byte .LVL141
7205
+ .8byte .LVL142
7206
+ .2byte 0x2
7207
+ .byte 0x71
7208
+ .sleb128 20
7209
+ .8byte 0
7210
+ .8byte 0
7211
+.LLST58:
7212
+ .8byte .LVL138
7213
+ .8byte .LVL139
7214
+ .2byte 0x11
7215
+ .byte 0x71
7216
+ .sleb128 0
7217
+ .byte 0xc
7218
+ .4byte 0xffffffff
7219
+ .byte 0x1a
7220
+ .byte 0xa
7221
+ .2byte 0x148
7222
+ .byte 0x1e
7223
+ .byte 0x23
7224
+ .uleb128 0x8200148
7225
+ .8byte .LVL139
7226
+ .8byte .LVL140
7227
+ .2byte 0x13
7228
+ .byte 0x70
7229
+ .sleb128 0
7230
+ .byte 0x94
7231
+ .byte 0x4
7232
+ .byte 0xc
7233
+ .4byte 0xffffffff
7234
+ .byte 0x1a
7235
+ .byte 0xa
7236
+ .2byte 0x148
7237
+ .byte 0x1e
7238
+ .byte 0x23
7239
+ .uleb128 0x8200148
7240
+ .8byte 0
7241
+ .8byte 0
7242
+.LLST59:
7243
+ .8byte .LVL134
7244
+ .8byte .LVL135
7245
+ .2byte 0x6
7246
+ .byte 0x9e
7247
+ .uleb128 0x4
7248
+ .4byte 0xdeadbeaf
7249
+ .8byte 0
7250
+ .8byte 0
7251
+.LLST60:
7252
+ .8byte .LVL147
7253
+ .8byte .LVL148
7254
+ .2byte 0x2
7255
+ .byte 0x30
7256
+ .byte 0x9f
7257
+ .8byte 0
7258
+ .8byte 0
7259
+.LLST51:
7260
+ .8byte .LVL110
7261
+ .8byte .LVL111
7262
+ .2byte 0x1
7263
+ .byte 0x50
7264
+ .8byte .LVL111
7265
+ .8byte .LFE236
7266
+ .2byte 0x1
7267
+ .byte 0x63
7268
+ .8byte 0
7269
+ .8byte 0
7270
+.LLST52:
7271
+ .8byte .LVL112
7272
+ .8byte .LVL113
7273
+ .2byte 0x1
7274
+ .byte 0x50
7275
+ .8byte 0
7276
+ .8byte 0
7277
+.LLST42:
7278
+ .8byte .LVL99
7279
+ .8byte .LVL100
7280
+ .2byte 0x1
7281
+ .byte 0x50
7282
+ .8byte .LVL100
7283
+ .8byte .LVL102
7284
+ .2byte 0x1
7285
+ .byte 0x66
7286
+ .8byte .LVL102
7287
+ .8byte .LVL105
7288
+ .2byte 0x1
7289
+ .byte 0x67
7290
+ .8byte .LVL105
7291
+ .8byte .LFE235
7292
+ .2byte 0x4
7293
+ .byte 0xf3
7294
+ .uleb128 0x1
7295
+ .byte 0x50
7296
+ .byte 0x9f
7297
+ .8byte 0
7298
+ .8byte 0
7299
+.LLST43:
7300
+ .8byte .LVL101
7301
+ .8byte .LVL102
7302
+ .2byte 0x12
7303
+ .byte 0x86
7304
+ .sleb128 0
7305
+ .byte 0xc
7306
+ .4byte 0xffffffff
7307
+ .byte 0x1a
7308
+ .byte 0xa
7309
+ .2byte 0x148
7310
+ .byte 0x1e
7311
+ .byte 0x23
7312
+ .uleb128 0x8200008
7313
+ .byte 0x9f
7314
+ .8byte .LVL102
7315
+ .8byte .LVL105
7316
+ .2byte 0x12
7317
+ .byte 0x87
7318
+ .sleb128 0
7319
+ .byte 0xc
7320
+ .4byte 0xffffffff
7321
+ .byte 0x1a
7322
+ .byte 0xa
7323
+ .2byte 0x148
7324
+ .byte 0x1e
7325
+ .byte 0x23
7326
+ .uleb128 0x8200008
7327
+ .byte 0x9f
7328
+ .8byte .LVL105
7329
+ .8byte .LVL106
7330
+ .2byte 0x13
7331
+ .byte 0xf3
7332
+ .uleb128 0x1
7333
+ .byte 0x50
7334
+ .byte 0xc
7335
+ .4byte 0xffffffff
7336
+ .byte 0x1a
7337
+ .byte 0xa
7338
+ .2byte 0x148
7339
+ .byte 0x1e
7340
+ .byte 0x23
7341
+ .uleb128 0x8200008
7342
+ .byte 0x9f
7343
+ .8byte .LVL106
7344
+ .8byte .LFE235
7345
+ .2byte 0x12
7346
+ .byte 0x87
7347
+ .sleb128 0
7348
+ .byte 0xc
7349
+ .4byte 0xffffffff
7350
+ .byte 0x1a
7351
+ .byte 0xa
7352
+ .2byte 0x148
7353
+ .byte 0x1e
7354
+ .byte 0x23
7355
+ .uleb128 0x8200008
7356
+ .byte 0x9f
7357
+ .8byte 0
7358
+ .8byte 0
7359
+.LLST44:
7360
+ .8byte .LVL101
7361
+ .8byte .LVL103
7362
+ .2byte 0x2
7363
+ .byte 0x30
7364
+ .byte 0x9f
7365
+ .8byte .LVL103
7366
+ .8byte .LVL104
7367
+ .2byte 0x1
7368
+ .byte 0x65
7369
+ .8byte .LVL106
7370
+ .8byte .LFE235
7371
+ .2byte 0x1
7372
+ .byte 0x65
7373
+ .8byte 0
7374
+ .8byte 0
7375
+.LLST45:
7376
+ .8byte .LVL107
7377
+ .8byte .LVL108-1
7378
+ .2byte 0x2
7379
+ .byte 0x83
7380
+ .sleb128 16
7381
+ .8byte 0
7382
+ .8byte 0
7383
+.LLST46:
7384
+ .8byte .LVL107
7385
+ .8byte .LVL108-1
7386
+ .2byte 0x1
7387
+ .byte 0x52
7388
+ .8byte 0
7389
+ .8byte 0
7390
+.LLST47:
7391
+ .8byte .LVL107
7392
+ .8byte .LVL108
7393
+ .2byte 0x1
7394
+ .byte 0x65
7395
+ .8byte 0
7396
+ .8byte 0
7397
+.LLST48:
7398
+ .8byte .LVL107
7399
+ .8byte .LVL108
7400
+ .2byte 0x1
7401
+ .byte 0x67
7402
+ .8byte 0
7403
+ .8byte 0
7404
+.LLST49:
7405
+ .8byte .LVL107
7406
+ .8byte .LVL108
7407
+ .2byte 0x2
7408
+ .byte 0x30
7409
+ .byte 0x9f
7410
+ .8byte 0
7411
+ .8byte 0
7412
+.LLST50:
7413
+ .8byte .LVL107
7414
+ .8byte .LVL108
7415
+ .2byte 0x2
7416
+ .byte 0x31
7417
+ .byte 0x9f
7418
+ .8byte 0
7419
+ .8byte 0
7420
+.LLST31:
7421
+ .8byte .LVL88
7422
+ .8byte .LVL91
7423
+ .2byte 0x1
7424
+ .byte 0x50
7425
+ .8byte .LVL91
7426
+ .8byte .LVL92
7427
+ .2byte 0x1
7428
+ .byte 0x69
7429
+ .8byte .LVL92
7430
+ .8byte .LVL94
7431
+ .2byte 0x1
7432
+ .byte 0x66
7433
+ .8byte .LVL94
7434
+ .8byte .LFE234
7435
+ .2byte 0x4
7436
+ .byte 0xf3
7437
+ .uleb128 0x1
7438
+ .byte 0x50
7439
+ .byte 0x9f
7440
+ .8byte 0
7441
+ .8byte 0
7442
+.LLST32:
7443
+ .8byte .LVL88
7444
+ .8byte .LVL93
7445
+ .2byte 0x1
7446
+ .byte 0x51
7447
+ .8byte .LVL93
7448
+ .8byte .LVL94
7449
+ .2byte 0x1
7450
+ .byte 0x65
7451
+ .8byte .LVL94
7452
+ .8byte .LVL95
7453
+ .2byte 0x4
7454
+ .byte 0xf3
7455
+ .uleb128 0x1
7456
+ .byte 0x51
7457
+ .byte 0x9f
7458
+ .8byte .LVL95
7459
+ .8byte .LFE234
7460
+ .2byte 0x1
7461
+ .byte 0x65
7462
+ .8byte 0
7463
+ .8byte 0
7464
+.LLST33:
7465
+ .8byte .LVL88
7466
+ .8byte .LVL90
7467
+ .2byte 0x12
7468
+ .byte 0x70
7469
+ .sleb128 0
7470
+ .byte 0xc
7471
+ .4byte 0xffffffff
7472
+ .byte 0x1a
7473
+ .byte 0xa
7474
+ .2byte 0x148
7475
+ .byte 0x1e
7476
+ .byte 0x23
7477
+ .uleb128 0x8200008
7478
+ .byte 0x9f
7479
+ .8byte .LVL90
7480
+ .8byte .LVL92
7481
+ .2byte 0xc
7482
+ .byte 0x89
7483
+ .sleb128 0
7484
+ .byte 0xa
7485
+ .2byte 0x148
7486
+ .byte 0x1e
7487
+ .byte 0x23
7488
+ .uleb128 0x8200008
7489
+ .byte 0x9f
7490
+ .8byte .LVL92
7491
+ .8byte .LVL94
7492
+ .2byte 0xc
7493
+ .byte 0x86
7494
+ .sleb128 0
7495
+ .byte 0xa
7496
+ .2byte 0x148
7497
+ .byte 0x1e
7498
+ .byte 0x23
7499
+ .uleb128 0x8200008
7500
+ .byte 0x9f
7501
+ .8byte .LVL94
7502
+ .8byte .LVL95
7503
+ .2byte 0x13
7504
+ .byte 0xf3
7505
+ .uleb128 0x1
7506
+ .byte 0x50
7507
+ .byte 0xc
7508
+ .4byte 0xffffffff
7509
+ .byte 0x1a
7510
+ .byte 0xa
7511
+ .2byte 0x148
7512
+ .byte 0x1e
7513
+ .byte 0x23
7514
+ .uleb128 0x8200008
7515
+ .byte 0x9f
7516
+ .8byte .LVL95
7517
+ .8byte .LFE234
7518
+ .2byte 0xc
7519
+ .byte 0x86
7520
+ .sleb128 0
7521
+ .byte 0xa
7522
+ .2byte 0x148
7523
+ .byte 0x1e
7524
+ .byte 0x23
7525
+ .uleb128 0x8200008
7526
+ .byte 0x9f
7527
+ .8byte 0
7528
+ .8byte 0
7529
+.LLST34:
7530
+ .8byte .LVL93
7531
+ .8byte .LVL94
7532
+ .2byte 0x1
7533
+ .byte 0x67
7534
+ .8byte .LVL95
7535
+ .8byte .LFE234
7536
+ .2byte 0x1
7537
+ .byte 0x67
7538
+ .8byte 0
7539
+ .8byte 0
7540
+.LLST35:
7541
+ .8byte .LVL88
7542
+ .8byte .LVL89
7543
+ .2byte 0x1
7544
+ .byte 0x51
7545
+ .8byte 0
7546
+ .8byte 0
7547
+.LLST36:
7548
+ .8byte .LVL96
7549
+ .8byte .LVL97-1
7550
+ .2byte 0x2
7551
+ .byte 0x83
7552
+ .sleb128 16
7553
+ .8byte 0
7554
+ .8byte 0
7555
+.LLST37:
7556
+ .8byte .LVL96
7557
+ .8byte .LVL97
7558
+ .2byte 0x1
7559
+ .byte 0x65
7560
+ .8byte 0
7561
+ .8byte 0
7562
+.LLST38:
7563
+ .8byte .LVL96
7564
+ .8byte .LVL97
7565
+ .2byte 0x1
7566
+ .byte 0x67
7567
+ .8byte 0
7568
+ .8byte 0
7569
+.LLST39:
7570
+ .8byte .LVL96
7571
+ .8byte .LVL97
7572
+ .2byte 0x1
7573
+ .byte 0x66
7574
+ .8byte 0
7575
+ .8byte 0
7576
+.LLST40:
7577
+ .8byte .LVL96
7578
+ .8byte .LVL97
7579
+ .2byte 0x2
7580
+ .byte 0x30
7581
+ .byte 0x9f
7582
+ .8byte 0
7583
+ .8byte 0
7584
+.LLST41:
7585
+ .8byte .LVL96
7586
+ .8byte .LVL97
7587
+ .2byte 0x2
7588
+ .byte 0x31
7589
+ .byte 0x9f
7590
+ .8byte 0
7591
+ .8byte 0
7592
+.LLST28:
7593
+ .8byte .LVL80
7594
+ .8byte .LVL81
7595
+ .2byte 0x1
7596
+ .byte 0x50
7597
+ .8byte .LVL81
7598
+ .8byte .LVL86
7599
+ .2byte 0x1
7600
+ .byte 0x63
7601
+ .8byte .LVL86
7602
+ .8byte .LVL87-1
7603
+ .2byte 0x1
7604
+ .byte 0x50
7605
+ .8byte .LVL87-1
7606
+ .8byte .LFE232
7607
+ .2byte 0x4
7608
+ .byte 0xf3
7609
+ .uleb128 0x1
7610
+ .byte 0x50
7611
+ .byte 0x9f
7612
+ .8byte 0
7613
+ .8byte 0
7614
+.LLST29:
7615
+ .8byte .LVL81
7616
+ .8byte .LVL86
7617
+ .2byte 0x1
7618
+ .byte 0x63
7619
+ .8byte .LVL86
7620
+ .8byte .LVL87-1
7621
+ .2byte 0x1
7622
+ .byte 0x50
7623
+ .8byte .LVL87-1
7624
+ .8byte .LFE232
7625
+ .2byte 0x4
7626
+ .byte 0xf3
7627
+ .uleb128 0x1
7628
+ .byte 0x50
7629
+ .byte 0x9f
7630
+ .8byte 0
7631
+ .8byte 0
7632
+.LLST30:
7633
+ .8byte .LVL83
7634
+ .8byte .LVL84
7635
+ .2byte 0x2
7636
+ .byte 0x31
7637
+ .byte 0x9f
7638
+ .8byte .LVL84
7639
+ .8byte .LVL85
7640
+ .2byte 0x2
7641
+ .byte 0x30
7642
+ .byte 0x9f
7643
+ .8byte 0
7644
+ .8byte 0
7645
+.LLST8:
7646
+ .8byte .LVL25
7647
+ .8byte .LVL26
7648
+ .2byte 0x1e
7649
+ .byte 0x86
7650
+ .sleb128 0
7651
+ .byte 0x8
7652
+ .byte 0x20
7653
+ .byte 0x24
7654
+ .byte 0x8
7655
+ .byte 0x20
7656
+ .byte 0x26
7657
+ .byte 0x8
7658
+ .byte 0x28
7659
+ .byte 0x1e
7660
+ .byte 0x85
7661
+ .sleb128 0
7662
+ .byte 0x8
7663
+ .byte 0x20
7664
+ .byte 0x24
7665
+ .byte 0x8
7666
+ .byte 0x20
7667
+ .byte 0x26
7668
+ .byte 0xa
7669
+ .2byte 0x148
7670
+ .byte 0x1e
7671
+ .byte 0x22
7672
+ .byte 0x23
7673
+ .uleb128 0x8200008
7674
+ .byte 0x9f
7675
+ .8byte .LVL26
7676
+ .8byte .LVL34
7677
+ .2byte 0x1e
7678
+ .byte 0x86
7679
+ .sleb128 -1
7680
+ .byte 0x8
7681
+ .byte 0x20
7682
+ .byte 0x24
7683
+ .byte 0x8
7684
+ .byte 0x20
7685
+ .byte 0x26
7686
+ .byte 0x8
7687
+ .byte 0x28
7688
+ .byte 0x1e
7689
+ .byte 0x85
7690
+ .sleb128 0
7691
+ .byte 0x8
7692
+ .byte 0x20
7693
+ .byte 0x24
7694
+ .byte 0x8
7695
+ .byte 0x20
7696
+ .byte 0x26
7697
+ .byte 0xa
7698
+ .2byte 0x148
7699
+ .byte 0x1e
7700
+ .byte 0x22
7701
+ .byte 0x23
7702
+ .uleb128 0x8200008
7703
+ .byte 0x9f
7704
+ .8byte 0
7705
+ .8byte 0
7706
+.LLST9:
7707
+ .8byte .LVL24
7708
+ .8byte .LVL36
7709
+ .2byte 0x1
7710
+ .byte 0x65
7711
+ .8byte 0
7712
+ .8byte 0
7713
+.LLST10:
7714
+ .8byte .LVL25
7715
+ .8byte .LVL26
7716
+ .2byte 0x1
7717
+ .byte 0x66
7718
+ .8byte .LVL26
7719
+ .8byte .LVL34
7720
+ .2byte 0x3
7721
+ .byte 0x86
7722
+ .sleb128 -1
7723
+ .byte 0x9f
7724
+ .8byte .LVL34
7725
+ .8byte .LVL36
7726
+ .2byte 0x1
7727
+ .byte 0x66
7728
+ .8byte 0
7729
+ .8byte 0
7730
+.LLST5:
7731
+ .8byte .LVL11
7732
+ .8byte .LVL12
7733
+ .2byte 0x1
7734
+ .byte 0x50
7735
+ .8byte .LVL12
7736
+ .8byte .LVL17
7737
+ .2byte 0x1
7738
+ .byte 0x63
7739
+ .8byte .LVL17
7740
+ .8byte .LVL19
7741
+ .2byte 0x5
7742
+ .byte 0x8b
7743
+ .sleb128 65536
7744
+ .byte 0x9f
7745
+ .8byte .LVL19
7746
+ .8byte .LVL20
7747
+ .2byte 0x4
7748
+ .byte 0xf3
7749
+ .uleb128 0x1
7750
+ .byte 0x50
7751
+ .byte 0x9f
7752
+ .8byte .LVL20
7753
+ .8byte .LVL22
7754
+ .2byte 0x1
7755
+ .byte 0x63
7756
+ .8byte .LVL22
7757
+ .8byte .LVL23
7758
+ .2byte 0x1
7759
+ .byte 0x50
7760
+ .8byte .LVL23
7761
+ .8byte .LFE228
7762
+ .2byte 0x4
7763
+ .byte 0xf3
7764
+ .uleb128 0x1
7765
+ .byte 0x50
7766
+ .byte 0x9f
7767
+ .8byte 0
7768
+ .8byte 0
7769
+.LLST6:
7770
+ .8byte .LVL13
7771
+ .8byte .LVL18
7772
+ .2byte 0x1
7773
+ .byte 0x67
7774
+ .8byte .LVL20
7775
+ .8byte .LVL22
7776
+ .2byte 0x1
7777
+ .byte 0x67
7778
+ .8byte 0
7779
+ .8byte 0
7780
+.LLST7:
7781
+ .8byte .LVL20
7782
+ .8byte .LVL22
7783
+ .2byte 0x3
7784
+ .byte 0x84
7785
+ .sleb128 -4
7786
+ .byte 0x9f
7787
+ .8byte 0
7788
+ .8byte 0
7789
+.LLST0:
7790
+ .8byte .LVL0
7791
+ .8byte .LVL1
7792
+ .2byte 0x1
7793
+ .byte 0x50
7794
+ .8byte .LVL1
7795
+ .8byte .LVL3
7796
+ .2byte 0x1
7797
+ .byte 0x55
7798
+ .8byte .LVL3
7799
+ .8byte .LFE227
7800
+ .2byte 0x4
7801
+ .byte 0xf3
7802
+ .uleb128 0x1
7803
+ .byte 0x50
7804
+ .byte 0x9f
7805
+ .8byte 0
7806
+ .8byte 0
7807
+.LLST1:
7808
+ .8byte .LVL0
7809
+ .8byte .LVL7
7810
+ .2byte 0x1
7811
+ .byte 0x51
7812
+ .8byte .LVL7
7813
+ .8byte .LFE227
7814
+ .2byte 0x4
7815
+ .byte 0xf3
7816
+ .uleb128 0x1
7817
+ .byte 0x51
7818
+ .byte 0x9f
7819
+ .8byte 0
7820
+ .8byte 0
7821
+.LLST2:
7822
+ .8byte .LVL0
7823
+ .8byte .LVL8-1
7824
+ .2byte 0x1
7825
+ .byte 0x52
7826
+ .8byte .LVL8-1
7827
+ .8byte .LFE227
7828
+ .2byte 0x4
7829
+ .byte 0xf3
7830
+ .uleb128 0x1
7831
+ .byte 0x52
7832
+ .byte 0x9f
7833
+ .8byte 0
7834
+ .8byte 0
7835
+.LLST3:
7836
+ .8byte .LVL2
7837
+ .8byte .LVL3
7838
+ .2byte 0x1
7839
+ .byte 0x53
7840
+ .8byte .LVL4
7841
+ .8byte .LVL6
7842
+ .2byte 0x1
7843
+ .byte 0x53
7844
+ .8byte 0
7845
+ .8byte 0
7846
+.LLST4:
7847
+ .8byte .LVL9
7848
+ .8byte .LVL10
7849
+ .2byte 0x1
7850
+ .byte 0x50
7851
+ .8byte .LVL10
7852
+ .8byte .LFE220
7853
+ .2byte 0x4
7854
+ .byte 0xf3
7855
+ .uleb128 0x1
7856
+ .byte 0x50
7857
+ .byte 0x9f
7858
+ .8byte 0
7859
+ .8byte 0
7860
+.LLST11:
7861
+ .8byte .LVL37
7862
+ .8byte .LVL39
7863
+ .2byte 0x1
7864
+ .byte 0x50
7865
+ .8byte .LVL39
7866
+ .8byte .LVL69
7867
+ .2byte 0x1
7868
+ .byte 0x63
7869
+ .8byte .LVL69
7870
+ .8byte .LVL71
7871
+ .2byte 0x1
7872
+ .byte 0x53
7873
+ .8byte .LVL71
7874
+ .8byte .LFE242
7875
+ .2byte 0x4
7876
+ .byte 0xf3
7877
+ .uleb128 0x1
7878
+ .byte 0x50
7879
+ .byte 0x9f
7880
+ .8byte 0
7881
+ .8byte 0
7882
+.LLST12:
7883
+ .8byte .LVL37
7884
+ .8byte .LVL39
7885
+ .2byte 0x1
7886
+ .byte 0x51
7887
+ .8byte .LVL39
7888
+ .8byte .LVL67
7889
+ .2byte 0x1
7890
+ .byte 0x66
7891
+ .8byte .LVL67
7892
+ .8byte .LFE242
7893
+ .2byte 0x4
7894
+ .byte 0xf3
7895
+ .uleb128 0x1
7896
+ .byte 0x51
7897
+ .byte 0x9f
7898
+ .8byte 0
7899
+ .8byte 0
7900
+.LLST13:
7901
+ .8byte .LVL37
7902
+ .8byte .LVL39
7903
+ .2byte 0x1
7904
+ .byte 0x52
7905
+ .8byte .LVL39
7906
+ .8byte .LVL72
7907
+ .2byte 0x1
7908
+ .byte 0x64
7909
+ .8byte .LVL72
7910
+ .8byte .LVL74
7911
+ .2byte 0x4
7912
+ .byte 0xf3
7913
+ .uleb128 0x1
7914
+ .byte 0x52
7915
+ .byte 0x9f
7916
+ .8byte .LVL74
7917
+ .8byte .LVL77
7918
+ .2byte 0x1
7919
+ .byte 0x64
7920
+ .8byte .LVL77
7921
+ .8byte .LFE242
7922
+ .2byte 0x4
7923
+ .byte 0xf3
7924
+ .uleb128 0x1
7925
+ .byte 0x52
7926
+ .byte 0x9f
7927
+ .8byte 0
7928
+ .8byte 0
7929
+.LLST14:
7930
+ .8byte .LVL37
7931
+ .8byte .LVL39
7932
+ .2byte 0x1
7933
+ .byte 0x53
7934
+ .8byte .LVL39
7935
+ .8byte .LVL47
7936
+ .2byte 0x1
7937
+ .byte 0x69
7938
+ .8byte .LVL47
7939
+ .8byte .LVL50
7940
+ .2byte 0x4
7941
+ .byte 0xf3
7942
+ .uleb128 0x1
7943
+ .byte 0x53
7944
+ .byte 0x9f
7945
+ .8byte .LVL50
7946
+ .8byte .LVL55
7947
+ .2byte 0x1
7948
+ .byte 0x69
7949
+ .8byte .LVL55
7950
+ .8byte .LFE242
7951
+ .2byte 0x4
7952
+ .byte 0xf3
7953
+ .uleb128 0x1
7954
+ .byte 0x53
7955
+ .byte 0x9f
7956
+ .8byte 0
7957
+ .8byte 0
7958
+.LLST15:
7959
+ .8byte .LVL59
7960
+ .8byte .LVL60
7961
+ .2byte 0x1
7962
+ .byte 0x50
7963
+ .8byte .LVL60
7964
+ .8byte .LVL68
7965
+ .2byte 0x1
7966
+ .byte 0x67
7967
+ .8byte 0
7968
+ .8byte 0
7969
+.LLST16:
7970
+ .8byte .LVL63
7971
+ .8byte .LVL64
7972
+ .2byte 0x1
7973
+ .byte 0x50
7974
+ .8byte .LVL64
7975
+ .8byte .LVL73
7976
+ .2byte 0x1
7977
+ .byte 0x65
7978
+ .8byte .LVL74
7979
+ .8byte .LVL78
7980
+ .2byte 0x1
7981
+ .byte 0x65
7982
+ .8byte .LVL78
7983
+ .8byte .LVL79-1
7984
+ .2byte 0x2
7985
+ .byte 0x72
7986
+ .sleb128 32
7987
+ .8byte 0
7988
+ .8byte 0
7989
+.LLST17:
7990
+ .8byte .LVL46
7991
+ .8byte .LVL50
7992
+ .2byte 0x2
7993
+ .byte 0x30
7994
+ .byte 0x9f
7995
+ .8byte .LVL56
7996
+ .8byte .LVL68
7997
+ .2byte 0x2
7998
+ .byte 0x31
7999
+ .byte 0x9f
8000
+ .8byte 0
8001
+ .8byte 0
8002
+.LLST18:
8003
+ .8byte .LVL38
8004
+ .8byte .LVL39
8005
+ .2byte 0x1
8006
+ .byte 0x50
8007
+ .8byte .LVL39
8008
+ .8byte .LVL69
8009
+ .2byte 0x1
8010
+ .byte 0x63
8011
+ .8byte .LVL69
8012
+ .8byte .LVL71
8013
+ .2byte 0x1
8014
+ .byte 0x53
8015
+ .8byte .LVL71
8016
+ .8byte .LFE242
8017
+ .2byte 0x4
8018
+ .byte 0xf3
8019
+ .uleb128 0x1
8020
+ .byte 0x50
8021
+ .byte 0x9f
8022
+ .8byte 0
8023
+ .8byte 0
8024
+.LLST19:
8025
+ .8byte .LVL38
8026
+ .8byte .LVL39
8027
+ .2byte 0x1
8028
+ .byte 0x52
8029
+ .8byte .LVL39
8030
+ .8byte .LVL72
8031
+ .2byte 0x1
8032
+ .byte 0x64
8033
+ .8byte .LVL72
8034
+ .8byte .LVL74
8035
+ .2byte 0x4
8036
+ .byte 0xf3
8037
+ .uleb128 0x1
8038
+ .byte 0x52
8039
+ .byte 0x9f
8040
+ .8byte .LVL74
8041
+ .8byte .LVL77
8042
+ .2byte 0x1
8043
+ .byte 0x64
8044
+ .8byte .LVL77
8045
+ .8byte .LFE242
8046
+ .2byte 0x4
8047
+ .byte 0xf3
8048
+ .uleb128 0x1
8049
+ .byte 0x52
8050
+ .byte 0x9f
8051
+ .8byte 0
8052
+ .8byte 0
8053
+.LLST20:
8054
+ .8byte .LVL38
8055
+ .8byte .LVL39
8056
+ .2byte 0x1
8057
+ .byte 0x53
8058
+ .8byte .LVL39
8059
+ .8byte .LVL45
8060
+ .2byte 0x1
8061
+ .byte 0x69
8062
+ .8byte .LVL50
8063
+ .8byte .LVL55
8064
+ .2byte 0x1
8065
+ .byte 0x69
8066
+ .8byte 0
8067
+ .8byte 0
8068
+.LLST21:
8069
+ .8byte .LVL38
8070
+ .8byte .LVL39
8071
+ .2byte 0x2
8072
+ .byte 0x30
8073
+ .byte 0x9f
8074
+ .8byte .LVL39
8075
+ .8byte .LVL45
8076
+ .2byte 0x1
8077
+ .byte 0x67
8078
+ .8byte .LVL50
8079
+ .8byte .LVL55
8080
+ .2byte 0x1
8081
+ .byte 0x67
8082
+ .8byte 0
8083
+ .8byte 0
8084
+.LLST22:
8085
+ .8byte .LVL39
8086
+ .8byte .LVL45
8087
+ .2byte 0x1
8088
+ .byte 0x65
8089
+ .8byte .LVL50
8090
+ .8byte .LVL55
8091
+ .2byte 0x1
8092
+ .byte 0x65
8093
+ .8byte 0
8094
+ .8byte 0
8095
+.LLST23:
8096
+ .8byte .LVL40
8097
+ .8byte .LVL43
8098
+ .2byte 0x7
8099
+ .byte 0xa
8100
+ .2byte 0x4e20
8101
+ .byte 0x88
8102
+ .sleb128 0
8103
+ .byte 0x1c
8104
+ .byte 0x9f
8105
+ .8byte .LVL50
8106
+ .8byte .LVL51
8107
+ .2byte 0x7
8108
+ .byte 0xa
8109
+ .2byte 0x4e20
8110
+ .byte 0x88
8111
+ .sleb128 0
8112
+ .byte 0x1c
8113
+ .byte 0x9f
8114
+ .8byte .LVL51
8115
+ .8byte .LVL52
8116
+ .2byte 0x7
8117
+ .byte 0xa
8118
+ .2byte 0x4e21
8119
+ .byte 0x88
8120
+ .sleb128 0
8121
+ .byte 0x1c
8122
+ .byte 0x9f
8123
+ .8byte .LVL52
8124
+ .8byte .LVL53
8125
+ .2byte 0x7
8126
+ .byte 0xa
8127
+ .2byte 0x4e20
8128
+ .byte 0x88
8129
+ .sleb128 0
8130
+ .byte 0x1c
8131
+ .byte 0x9f
8132
+ .8byte .LVL53
8133
+ .8byte .LVL55
8134
+ .2byte 0x2
8135
+ .byte 0x30
8136
+ .byte 0x9f
8137
+ .8byte 0
8138
+ .8byte 0
8139
+.LLST24:
8140
+ .8byte .LVL68
8141
+ .8byte .LVL73
8142
+ .2byte 0x1
8143
+ .byte 0x65
8144
+ .8byte .LVL74
8145
+ .8byte .LVL78
8146
+ .2byte 0x1
8147
+ .byte 0x65
8148
+ .8byte .LVL78
8149
+ .8byte .LVL79-1
8150
+ .2byte 0x2
8151
+ .byte 0x72
8152
+ .sleb128 32
8153
+ .8byte 0
8154
+ .8byte 0
8155
+.LLST25:
8156
+ .8byte .LVL68
8157
+ .8byte .LVL72
8158
+ .2byte 0x1
8159
+ .byte 0x64
8160
+ .8byte .LVL72
8161
+ .8byte .LVL74
8162
+ .2byte 0x4
8163
+ .byte 0xf3
8164
+ .uleb128 0x1
8165
+ .byte 0x52
8166
+ .byte 0x9f
8167
+ .8byte .LVL74
8168
+ .8byte .LVL77
8169
+ .2byte 0x1
8170
+ .byte 0x64
8171
+ .8byte .LVL77
8172
+ .8byte .LFE242
8173
+ .2byte 0x4
8174
+ .byte 0xf3
8175
+ .uleb128 0x1
8176
+ .byte 0x52
8177
+ .byte 0x9f
8178
+ .8byte 0
8179
+ .8byte 0
8180
+.LLST26:
8181
+ .8byte .LVL68
8182
+ .8byte .LVL69
8183
+ .2byte 0x1
8184
+ .byte 0x63
8185
+ .8byte .LVL69
8186
+ .8byte .LVL71
8187
+ .2byte 0x1
8188
+ .byte 0x53
8189
+ .8byte .LVL71
8190
+ .8byte .LFE242
8191
+ .2byte 0x4
8192
+ .byte 0xf3
8193
+ .uleb128 0x1
8194
+ .byte 0x50
8195
+ .byte 0x9f
8196
+ .8byte 0
8197
+ .8byte 0
8198
+.LLST27:
8199
+ .8byte .LVL70
8200
+ .8byte .LVL71
8201
+ .2byte 0x1
8202
+ .byte 0x51
8203
+ .8byte .LVL74
8204
+ .8byte .LVL76
8205
+ .2byte 0x1
8206
+ .byte 0x51
8207
+ .8byte 0
8208
+ .8byte 0
8209
+ .section .debug_aranges,"",@progbits
8210
+ .4byte 0xdc
8211
+ .2byte 0x2
8212
+ .4byte .Ldebug_info0
8213
+ .byte 0x8
8214
+ .byte 0
8215
+ .2byte 0
8216
+ .2byte 0
8217
+ .8byte .LFB227
8218
+ .8byte .LFE227-.LFB227
8219
+ .8byte .LFB220
8220
+ .8byte .LFE220-.LFB220
8221
+ .8byte .LFB228
8222
+ .8byte .LFE228-.LFB228
8223
+ .8byte .LFB229
8224
+ .8byte .LFE229-.LFB229
8225
+ .8byte .LFB242
8226
+ .8byte .LFE242-.LFB242
8227
+ .8byte .LFB232
8228
+ .8byte .LFE232-.LFB232
8229
+ .8byte .LFB234
8230
+ .8byte .LFE234-.LFB234
8231
+ .8byte .LFB235
8232
+ .8byte .LFE235-.LFB235
8233
+ .8byte .LFB236
8234
+ .8byte .LFE236-.LFB236
8235
+ .8byte .LFB238
8236
+ .8byte .LFE238-.LFB238
8237
+ .8byte .LFB239
8238
+ .8byte .LFE239-.LFB239
8239
+ .8byte .LFB240
8240
+ .8byte .LFE240-.LFB240
8241
+ .8byte 0
8242
+ .8byte 0
8243
+ .section .debug_ranges,"",@progbits
8244
+.Ldebug_ranges0:
8245
+ .8byte .LBB32
8246
+ .8byte .LBE32
8247
+ .8byte .LBB35
8248
+ .8byte .LBE35
8249
+ .8byte 0
8250
+ .8byte 0
8251
+ .8byte .LBB48
8252
+ .8byte .LBE48
8253
+ .8byte .LBB51
8254
+ .8byte .LBE51
8255
+ .8byte 0
8256
+ .8byte 0
8257
+ .8byte .LBB52
8258
+ .8byte .LBE52
8259
+ .8byte .LBB65
8260
+ .8byte .LBE65
8261
+ .8byte .LBB66
8262
+ .8byte .LBE66
8263
+ .8byte .LBB67
8264
+ .8byte .LBE67
8265
+ .8byte .LBB68
8266
+ .8byte .LBE68
8267
+ .8byte .LBB69
8268
+ .8byte .LBE69
8269
+ .8byte 0
8270
+ .8byte 0
8271
+ .8byte .LBB56
8272
+ .8byte .LBE56
8273
+ .8byte .LBB59
8274
+ .8byte .LBE59
8275
+ .8byte 0
8276
+ .8byte 0
8277
+ .8byte .LBB74
8278
+ .8byte .LBE74
8279
+ .8byte .LBB79
8280
+ .8byte .LBE79
8281
+ .8byte 0
8282
+ .8byte 0
8283
+ .8byte .LBB86
8284
+ .8byte .LBE86
8285
+ .8byte .LBB89
8286
+ .8byte .LBE89
8287
+ .8byte 0
8288
+ .8byte 0
8289
+ .8byte .LBB98
8290
+ .8byte .LBE98
8291
+ .8byte .LBB105
8292
+ .8byte .LBE105
8293
+ .8byte 0
8294
+ .8byte 0
8295
+ .8byte .LBB100
8296
+ .8byte .LBE100
8297
+ .8byte .LBB103
8298
+ .8byte .LBE103
8299
+ .8byte 0
8300
+ .8byte 0
8301
+ .8byte .LBB120
8302
+ .8byte .LBE120
8303
+ .8byte .LBB131
8304
+ .8byte .LBE131
8305
+ .8byte 0
8306
+ .8byte 0
8307
+ .8byte .LBB122
8308
+ .8byte .LBE122
8309
+ .8byte .LBB126
8310
+ .8byte .LBE126
8311
+ .8byte .LBB129
8312
+ .8byte .LBE129
8313
+ .8byte 0
8314
+ .8byte 0
8315
+ .8byte .LFB227
8316
+ .8byte .LFE227
8317
+ .8byte .LFB220
8318
+ .8byte .LFE220
8319
+ .8byte .LFB228
8320
+ .8byte .LFE228
8321
+ .8byte .LFB229
8322
+ .8byte .LFE229
8323
+ .8byte .LFB242
8324
+ .8byte .LFE242
8325
+ .8byte .LFB232
8326
+ .8byte .LFE232
8327
+ .8byte .LFB234
8328
+ .8byte .LFE234
8329
+ .8byte .LFB235
8330
+ .8byte .LFE235
8331
+ .8byte .LFB236
8332
+ .8byte .LFE236
8333
+ .8byte .LFB238
8334
+ .8byte .LFE238
8335
+ .8byte .LFB239
8336
+ .8byte .LFE239
8337
+ .8byte .LFB240
8338
+ .8byte .LFE240
8339
+ .8byte 0
8340
+ .8byte 0
8341
+ .section .debug_line,"",@progbits
8342
+.Ldebug_line0:
8343
+ .section .debug_str,"MS",@progbits,1
8344
+.LASF83:
8345
+ .string "off_mem_rsvmap"
8346
+.LASF166:
8347
+ .string "UCLASS_I2C_EEPROM"
8348
+.LASF298:
8349
+ .string "jt_funcs"
8350
+.LASF171:
8351
+ .string "UCLASS_IRQ"
8352
+.LASF133:
8353
+ .string "initrd_start"
8354
+.LASF165:
8355
+ .string "UCLASS_I2C"
8356
+.LASF13:
8357
+ .string "sizetype"
8358
+.LASF312:
8359
+ .string "net_hostname"
8360
+.LASF36:
8361
+ .string "start"
8362
+.LASF206:
8363
+ .string "UCLASS_SPI"
8364
+.LASF169:
8365
+ .string "UCLASS_I2S"
8366
+.LASF334:
8367
+ .string "NETLOOP_RESTART"
8368
+.LASF167:
8369
+ .string "UCLASS_I2C_GENERIC"
8370
+.LASF179:
8371
+ .string "UCLASS_MOD_EXP"
8372
+.LASF230:
8373
+ .string "UCLASS_IO_DOMAIN"
8374
+.LASF251:
8375
+ .string "using_pre_serial"
8376
+.LASF200:
8377
+ .string "UCLASS_RKNAND"
8378
+.LASF142:
8379
+ .string "UCLASS_DEMO"
8380
+.LASF373:
8381
+ .string "rip_fail"
8382
+.LASF91:
8383
+ .string "ih_magic"
8384
+.LASF29:
8385
+ .string "list_head"
8386
+.LASF292:
8387
+ .string "pm_ctx_phys"
8388
+.LASF146:
8389
+ .string "UCLASS_TEST_PROBE"
8390
+.LASF226:
8391
+ .string "UCLASS_KEY"
8392
+.LASF64:
8393
+ .string "bi_intfreq"
8394
+.LASF11:
8395
+ .string "phys_addr_t"
8396
+.LASF221:
8397
+ .string "UCLASS_VIDEO_BRIDGE"
8398
+.LASF291:
8399
+ .string "video_bottom"
8400
+.LASF5:
8401
+ .string "__u8"
8402
+.LASF377:
8403
+ .string "task_list"
8404
+.LASF333:
8405
+ .string "NETLOOP_CONTINUE"
8406
+.LASF209:
8407
+ .string "UCLASS_SPI_GENERIC"
8408
+.LASF286:
8409
+ .string "malloc_base"
8410
+.LASF369:
8411
+ .string "tid_name"
8412
+.LASF40:
8413
+ .string "flash_info_t"
8414
+.LASF184:
8415
+ .string "UCLASS_PANEL"
8416
+.LASF108:
8417
+ .string "comp"
8418
+.LASF103:
8419
+ .string "image_header_t"
8420
+.LASF138:
8421
+ .string "state"
8422
+.LASF412:
8423
+ .string "disable_serror"
8424
+.LASF159:
8425
+ .string "UCLASS_CROS_EC"
8426
+.LASF58:
8427
+ .string "bi_dsp_freq"
8428
+.LASF105:
8429
+ .string "image_start"
8430
+.LASF422:
8431
+ .string "invalidate_icache_all"
8432
+.LASF420:
8433
+ .string "disable_interrupts"
8434
+.LASF144:
8435
+ .string "UCLASS_TEST_FDT"
8436
+.LASF49:
8437
+ .string "bd_info"
8438
+.LASF331:
8439
+ .string "uclass_id"
8440
+.LASF95:
8441
+ .string "ih_load"
8442
+.LASF215:
8443
+ .string "UCLASS_UFS"
8444
+.LASF302:
8445
+ .string "__dtb_dt_spl_begin"
8446
+.LASF363:
8447
+ .string "TASK_LOAD_UBOOT"
8448
+.LASF7:
8449
+ .string "__u32"
8450
+.LASF149:
8451
+ .string "UCLASS_PCI_EMUL"
8452
+.LASF430:
8453
+ .string "/home4/cjh/uboot-nextdev-v3"
8454
+.LASF289:
8455
+ .string "cur_serial_dev"
8456
+.LASF318:
8457
+ .string "net_tx_packet"
8458
+.LASF225:
8459
+ .string "UCLASS_FG"
8460
+.LASF317:
8461
+ .string "net_server_ip"
8462
+.LASF325:
8463
+ .string "net_native_vlan"
8464
+.LASF265:
8465
+ .string "ram_top_ext_size"
8466
+.LASF223:
8467
+ .string "UCLASS_VIDEO_CRTC"
8468
+.LASF158:
8469
+ .string "UCLASS_CODEC"
8470
+.LASF283:
8471
+ .string "env_buf"
8472
+.LASF20:
8473
+ .string "errno"
8474
+.LASF15:
8475
+ .string "long int"
8476
+.LASF53:
8477
+ .string "bi_flashsize"
8478
+.LASF339:
8479
+ .string "__bss_end"
8480
+.LASF189:
8481
+ .string "UCLASS_PHY"
8482
+.LASF76:
8483
+ .string "IRQ_STACK_START_IN"
8484
+.LASF87:
8485
+ .string "size_dt_strings"
8486
+.LASF220:
8487
+ .string "UCLASS_VIDEO"
8488
+.LASF356:
8489
+ .string "EVT_CRYPTO"
8490
+.LASF266:
8491
+ .string "relocaddr"
8492
+.LASF389:
8493
+ .string "mpb_post"
8494
+.LASF429:
8495
+ .string "common/mp_boot.c"
8496
+.LASF328:
8497
+ .string "net_boot_file_size"
8498
+.LASF374:
8499
+ .string "cpu_core"
8500
+.LASF97:
8501
+ .string "ih_dcrc"
8502
+.LASF63:
8503
+ .string "bi_ethspeed"
8504
+.LASF141:
8505
+ .string "UCLASS_ROOT"
8506
+.LASF26:
8507
+ .string "ide_bus_offset"
8508
+.LASF361:
8509
+ .string "TASK_INIT_DISPLAY"
8510
+.LASF315:
8511
+ .string "net_server_ethaddr"
8512
+.LASF66:
8513
+ .string "bi_arch_number"
8514
+.LASF3:
8515
+ .string "signed char"
8516
+.LASF172:
8517
+ .string "UCLASS_KEYBOARD"
8518
+.LASF18:
8519
+ .string "uint8_t"
8520
+.LASF38:
8521
+ .string "udevice"
8522
+.LASF418:
8523
+ .string "udelay"
8524
+.LASF99:
8525
+ .string "ih_arch"
8526
+.LASF80:
8527
+ .string "totalsize"
8528
+.LASF92:
8529
+ .string "ih_hcrc"
8530
+.LASF268:
8531
+ .string "mon_len"
8532
+.LASF107:
8533
+ .string "load"
8534
+.LASF214:
8535
+ .string "UCLASS_TPM"
8536
+.LASF43:
8537
+ .string "lmb_property"
8538
+.LASF85:
8539
+ .string "last_comp_version"
8540
+.LASF0:
8541
+ .string "unsigned char"
8542
+.LASF140:
8543
+ .string "images"
8544
+.LASF341:
8545
+ .string "priv"
8546
+.LASF229:
8547
+ .string "UCLASS_DVFS"
8548
+.LASF59:
8549
+ .string "bi_ddr_freq"
8550
+.LASF403:
8551
+ .string "mpb_initial"
8552
+.LASF173:
8553
+ .string "UCLASS_LED"
8554
+.LASF94:
8555
+ .string "ih_size"
8556
+.LASF419:
8557
+ .string "dcache_enable"
8558
+.LASF203:
8559
+ .string "UCLASS_SCMI_AGENT"
8560
+.LASF233:
8561
+ .string "UCLASS_MDIO"
8562
+.LASF22:
8563
+ .string "_Bool"
8564
+.LASF337:
8565
+ .string "net_state"
8566
+.LASF168:
8567
+ .string "UCLASS_I2C_MUX"
8568
+.LASF14:
8569
+ .string "char"
8570
+.LASF24:
8571
+ .string "_binary_u_boot_bin_start"
8572
+.LASF219:
8573
+ .string "UCLASS_USB_GADGET_GENERIC"
8574
+.LASF335:
8575
+ .string "NETLOOP_SUCCESS"
8576
+.LASF415:
8577
+ .string "printf"
8578
+.LASF372:
8579
+ .string "ptid_mask"
8580
+.LASF332:
8581
+ .string "net_loop_state"
8582
+.LASF247:
8583
+ .string "tlb_size"
8584
+.LASF274:
8585
+ .string "dm_root_f"
8586
+.LASF157:
8587
+ .string "UCLASS_AMP"
8588
+.LASF195:
8589
+ .string "UCLASS_PWRSEQ"
8590
+.LASF123:
8591
+ .string "fit_hdr_fdt"
8592
+.LASF326:
8593
+ .string "net_restart_wrap"
8594
+.LASF314:
8595
+ .string "net_ethaddr"
8596
+.LASF256:
8597
+ .string "flags"
8598
+.LASF100:
8599
+ .string "ih_type"
8600
+.LASF355:
8601
+ .string "EVT_BOOT_SIZE"
8602
+.LASF81:
8603
+ .string "off_dt_struct"
8604
+.LASF413:
8605
+ .string "mdelay"
8606
+.LASF54:
8607
+ .string "bi_flashoffset"
8608
+.LASF327:
8609
+ .string "net_boot_file_name"
8610
+.LASF143:
8611
+ .string "UCLASS_TEST"
8612
+.LASF397:
8613
+ .string "mpb_task_dump"
8614
+.LASF93:
8615
+ .string "ih_time"
8616
+.LASF258:
8617
+ .string "bus_clk"
8618
+.LASF196:
8619
+ .string "UCLASS_RAM"
8620
+.LASF162:
8621
+ .string "UCLASS_ETH"
8622
+.LASF364:
8623
+ .string "TASK_LOAD_FIT"
8624
+.LASF104:
8625
+ .string "image_info"
8626
+.LASF110:
8627
+ .string "arch"
8628
+.LASF260:
8629
+ .string "mem_clk"
8630
+.LASF257:
8631
+ .string "cpu_clk"
8632
+.LASF32:
8633
+ .string "select_hwpart"
8634
+.LASF319:
8635
+ .string "net_rx_packets"
8636
+.LASF75:
8637
+ .string "_datarelro_start_ofs"
8638
+.LASF17:
8639
+ .string "ulong"
8640
+.LASF371:
8641
+ .string "task_fn"
8642
+.LASF96:
8643
+ .string "ih_ep"
8644
+.LASF45:
8645
+ .string "lmb_region"
8646
+.LASF375:
8647
+ .string "task"
8648
+.LASF392:
8649
+ .string "mpb_task_wait_timeout_done"
8650
+.LASF400:
8651
+ .string "tid_to_task_index"
8652
+.LASF118:
8653
+ .string "fit_uname_os"
8654
+.LASF60:
8655
+ .string "bi_bootflags"
8656
+.LASF316:
8657
+ .string "net_ip"
8658
+.LASF278:
8659
+ .string "fdt_size"
8660
+.LASF310:
8661
+ .string "net_dns_server"
8662
+.LASF338:
8663
+ .string "__bss_start"
8664
+.LASF330:
8665
+ .string "net_ping_ip"
8666
+.LASF47:
8667
+ .string "memory"
8668
+.LASF78:
8669
+ .string "fdt_header"
8670
+.LASF175:
8671
+ .string "UCLASS_MAILBOX"
8672
+.LASF343:
8673
+ .string "filename"
8674
+.LASF130:
8675
+ .string "rd_end"
8676
+.LASF269:
8677
+ .string "irq_sp"
8678
+.LASF135:
8679
+ .string "cmdline_start"
8680
+.LASF255:
8681
+ .string "global_data"
8682
+.LASF358:
8683
+ .string "EVT_SIMPLE_BOOTM"
8684
+.LASF366:
8685
+ .string "TASK_HASH_ANDROID"
8686
+.LASF204:
8687
+ .string "UCLASS_SCSI"
8688
+.LASF217:
8689
+ .string "UCLASS_USB_DEV_GENERIC"
8690
+.LASF176:
8691
+ .string "UCLASS_MASS_STORAGE"
8692
+.LASF1:
8693
+ .string "long unsigned int"
8694
+.LASF151:
8695
+ .string "UCLASS_SIMPLE_BUS"
8696
+.LASF299:
8697
+ .string "gd_t"
8698
+.LASF311:
8699
+ .string "net_nis_domain"
8700
+.LASF125:
8701
+ .string "fit_noffset_fdt"
8702
+.LASF342:
8703
+ .string "bl_len"
8704
+.LASF427:
8705
+ .string "get_ticks"
8706
+.LASF336:
8707
+ .string "NETLOOP_FAIL"
8708
+.LASF224:
8709
+ .string "UCLASS_WDT"
8710
+.LASF245:
8711
+ .string "timer_reset_value"
8712
+.LASF270:
8713
+ .string "start_addr_sp"
8714
+.LASF55:
8715
+ .string "bi_sramstart"
8716
+.LASF25:
8717
+ .string "_binary_u_boot_bin_end"
8718
+.LASF271:
8719
+ .string "reloc_off"
8720
+.LASF86:
8721
+ .string "boot_cpuid_phys"
8722
+.LASF244:
8723
+ .string "lastinc"
8724
+.LASF248:
8725
+ .string "tlb_fillptr"
8726
+.LASF121:
8727
+ .string "fit_uname_rd"
8728
+.LASF210:
8729
+ .string "UCLASS_SYSCON"
8730
+.LASF116:
8731
+ .string "fit_uname_cfg"
8732
+.LASF205:
8733
+ .string "UCLASS_SERIAL"
8734
+.LASF324:
8735
+ .string "net_our_vlan"
8736
+.LASF294:
8737
+ .string "serial"
8738
+.LASF154:
8739
+ .string "UCLASS_BLK"
8740
+.LASF111:
8741
+ .string "image_info_t"
8742
+.LASF150:
8743
+ .string "UCLASS_USB_EMUL"
8744
+.LASF421:
8745
+ .string "icache_disable"
8746
+.LASF246:
8747
+ .string "tlb_addr"
8748
+.LASF188:
8749
+ .string "UCLASS_PCI_GENERIC"
8750
+.LASF370:
8751
+ .string "task_t"
8752
+.LASF407:
8753
+ .string "spl_load_android"
8754
+.LASF387:
8755
+ .string "ticks"
8756
+.LASF106:
8757
+ .string "image_len"
8758
+.LASF362:
8759
+ .string "TASK_LOAD_BASEPARAMETER"
8760
+.LASF61:
8761
+ .string "bi_ip_addr"
8762
+.LASF393:
8763
+ .string "timeout_ms"
8764
+.LASF190:
8765
+ .string "UCLASS_PINCONFIG"
8766
+.LASF384:
8767
+ .string "smp_entry"
8768
+.LASF212:
8769
+ .string "UCLASS_THERMAL"
8770
+.LASF114:
8771
+ .string "legacy_hdr_os_copy"
8772
+.LASF354:
8773
+ .string "EVT_BOOT_ADDR"
8774
+.LASF9:
8775
+ .string "long long int"
8776
+.LASF277:
8777
+ .string "new_fdt"
8778
+.LASF21:
8779
+ .string "___strtok"
8780
+.LASF329:
8781
+ .string "net_boot_file_expected_size_in_blocks"
8782
+.LASF252:
8783
+ .string "enable"
8784
+.LASF395:
8785
+ .string "ptid"
8786
+.LASF183:
8787
+ .string "UCLASS_NVME"
8788
+.LASF249:
8789
+ .string "tlb_emerg"
8790
+.LASF112:
8791
+ .string "bootm_headers"
8792
+.LASF37:
8793
+ .string "protect"
8794
+.LASF216:
8795
+ .string "UCLASS_USB"
8796
+.LASF227:
8797
+ .string "UCLASS_RC"
8798
+.LASF398:
8799
+ .string "mpb_task_is_done"
8800
+.LASF284:
8801
+ .string "timebase_h"
8802
+.LASF285:
8803
+ .string "timebase_l"
8804
+.LASF160:
8805
+ .string "UCLASS_DISPLAY"
8806
+.LASF323:
8807
+ .string "net_null_ethaddr"
8808
+.LASF263:
8809
+ .string "env_valid"
8810
+.LASF228:
8811
+ .string "UCLASS_CHARGE_DISPLAY"
8812
+.LASF303:
8813
+ .string "load_addr"
8814
+.LASF117:
8815
+ .string "fit_hdr_os"
8816
+.LASF73:
8817
+ .string "_datarelrolocal_start_ofs"
8818
+.LASF396:
8819
+ .string "timeout"
8820
+.LASF254:
8821
+ .string "addr"
8822
+.LASF344:
8823
+ .string "read"
8824
+.LASF8:
8825
+ .string "unsigned int"
8826
+.LASF16:
8827
+ .string "ushort"
8828
+.LASF402:
8829
+ .string "task_is_registered"
8830
+.LASF281:
8831
+ .string "ufdt_blob"
8832
+.LASF410:
8833
+ .string "spl_init_display"
8834
+.LASF287:
8835
+ .string "malloc_limit"
8836
+.LASF401:
8837
+ .string "mpb_task_register"
8838
+.LASF192:
8839
+ .string "UCLASS_PMIC"
8840
+.LASF113:
8841
+ .string "legacy_hdr_os"
8842
+.LASF82:
8843
+ .string "off_dt_strings"
8844
+.LASF300:
8845
+ .string "monitor_flash_len"
8846
+.LASF177:
8847
+ .string "UCLASS_MISC"
8848
+.LASF51:
8849
+ .string "bi_memsize"
8850
+.LASF394:
8851
+ .string "mpb_task_wait_parent"
8852
+.LASF23:
8853
+ .string "image_base"
8854
+.LASF382:
8855
+ .string "mpb_init_1"
8856
+.LASF211:
8857
+ .string "UCLASS_SYSRESET"
8858
+.LASF164:
8859
+ .string "UCLASS_FIRMWARE"
8860
+.LASF425:
8861
+ .string "invalidate_dcache_range"
8862
+.LASF174:
8863
+ .string "UCLASS_LPC"
8864
+.LASF170:
8865
+ .string "UCLASS_IDE"
8866
+.LASF290:
8867
+ .string "video_top"
8868
+.LASF280:
8869
+ .string "of_root_f"
8870
+.LASF139:
8871
+ .string "bootm_headers_t"
8872
+.LASF57:
8873
+ .string "bi_arm_freq"
8874
+.LASF198:
8875
+ .string "UCLASS_REMOTEPROC"
8876
+.LASF109:
8877
+ .string "type"
8878
+.LASF120:
8879
+ .string "fit_hdr_rd"
8880
+.LASF388:
8881
+ .string "fail"
8882
+.LASF262:
8883
+ .string "env_addr"
8884
+.LASF56:
8885
+ .string "bi_sramsize"
8886
+.LASF348:
8887
+ .string "boot_size"
8888
+.LASF390:
8889
+ .string "mpb_task_wait_done"
8890
+.LASF406:
8891
+ .string "spl_hash_android"
8892
+.LASF275:
8893
+ .string "uclass_root"
8894
+.LASF163:
8895
+ .string "UCLASS_GPIO"
8896
+.LASF193:
8897
+ .string "UCLASS_PWM"
8898
+.LASF404:
8899
+ .string "set_gd"
8900
+.LASF42:
8901
+ .string "long double"
8902
+.LASF264:
8903
+ .string "ram_top"
8904
+.LASF296:
8905
+ .string "console_evt"
8906
+.LASF381:
8907
+ .string "mpb_init_x"
8908
+.LASF431:
8909
+ .string "mpb_task_set_state"
8910
+.LASF129:
8911
+ .string "rd_start"
8912
+.LASF194:
8913
+ .string "UCLASS_POWER_DOMAIN"
8914
+.LASF197:
8915
+ .string "UCLASS_REGULATOR"
8916
+.LASF305:
8917
+ .string "save_size"
8918
+.LASF414:
8919
+ .string "msec"
8920
+.LASF155:
8921
+ .string "UCLASS_CLK"
8922
+.LASF391:
8923
+ .string "core_task_run"
8924
+.LASF346:
8925
+ .string "info"
8926
+.LASF72:
8927
+ .string "_datarel_start_ofs"
8928
+.LASF250:
8929
+ .string "pre_serial"
8930
+.LASF428:
8931
+ .ascii "GNU C11 6.3.1 201"
8932
+ .string "70404 -mstrict-align -march=armv8-a+nosimd -mlittle-endian -mabi=lp64 -g -Os -fno-builtin -ffreestanding -fshort-wchar -fno-stack-protector -fno-delete-null-pointer-checks -fstack-usage -ffunction-sections -fdata-sections -ffixed-r9 -fno-common -ffixed-x18"
8933
+.LASF102:
8934
+ .string "ih_name"
8935
+.LASF98:
8936
+ .string "ih_os"
8937
+.LASF345:
8938
+ .string "task_data"
8939
+.LASF136:
8940
+ .string "cmdline_end"
8941
+.LASF320:
8942
+ .string "net_rx_packet"
8943
+.LASF241:
8944
+ .string "LOGF_MAX_CATEGORIES"
8945
+.LASF276:
8946
+ .string "fdt_blob"
8947
+.LASF33:
8948
+ .string "size"
8949
+.LASF10:
8950
+ .string "long long unsigned int"
8951
+.LASF90:
8952
+ .string "image_header"
8953
+.LASF350:
8954
+ .string "CPU_1"
8955
+.LASF19:
8956
+ .string "__be32"
8957
+.LASF52:
8958
+ .string "bi_flashstart"
8959
+.LASF119:
8960
+ .string "fit_noffset_os"
8961
+.LASF399:
8962
+ .string "mpb_task_set_result"
8963
+.LASF178:
8964
+ .string "UCLASS_MMC"
8965
+.LASF240:
8966
+ .string "UCLASS_INVALID"
8967
+.LASF376:
8968
+ .string "mpb_core"
8969
+.LASF218:
8970
+ .string "UCLASS_USB_HUB"
8971
+.LASF279:
8972
+ .string "of_root"
8973
+.LASF234:
8974
+ .string "UCLASS_EBC"
8975
+.LASF340:
8976
+ .string "spl_load_info"
8977
+.LASF293:
8978
+ .string "new_line"
8979
+.LASF416:
8980
+ .string "memset"
8981
+.LASF41:
8982
+ .string "flash_info"
8983
+.LASF84:
8984
+ .string "version"
8985
+.LASF46:
8986
+ .string "region"
8987
+.LASF88:
8988
+ .string "size_dt_struct"
8989
+.LASF273:
8990
+ .string "dm_root"
8991
+.LASF236:
8992
+ .string "UCLASS_RNG"
8993
+.LASF295:
8994
+ .string "sys_start_tick"
8995
+.LASF180:
8996
+ .string "UCLASS_MTD"
8997
+.LASF77:
8998
+ .string "fdt32_t"
8999
+.LASF272:
9000
+ .string "new_gd"
9001
+.LASF182:
9002
+ .string "UCLASS_NORTHBRIDGE"
9003
+.LASF62:
9004
+ .string "bi_enetaddr"
9005
+.LASF39:
9006
+ .string "mtd_info"
9007
+.LASF306:
9008
+ .string "in_addr"
9009
+.LASF321:
9010
+ .string "net_rx_packet_len"
9011
+.LASF383:
9012
+ .string "init"
9013
+.LASF301:
9014
+ .string "__dtb_dt_begin"
9015
+.LASF199:
9016
+ .string "UCLASS_RESET"
9017
+.LASF122:
9018
+ .string "fit_noffset_rd"
9019
+.LASF153:
9020
+ .string "UCLASS_AHCI"
9021
+.LASF12:
9022
+ .string "phys_size_t"
9023
+.LASF156:
9024
+ .string "UCLASS_CPU"
9025
+.LASF71:
9026
+ .string "FIQ_STACK_START"
9027
+.LASF137:
9028
+ .string "verify"
9029
+.LASF31:
9030
+ .string "name"
9031
+.LASF235:
9032
+ .string "UCLASS_EINK_DISPLAY"
9033
+.LASF185:
9034
+ .string "UCLASS_PANEL_BACKLIGHT"
9035
+.LASF213:
9036
+ .string "UCLASS_TIMER"
9037
+.LASF208:
9038
+ .string "UCLASS_SPI_FLASH"
9039
+.LASF261:
9040
+ .string "have_console"
9041
+.LASF65:
9042
+ .string "bi_busfreq"
9043
+.LASF6:
9044
+ .string "short int"
9045
+.LASF347:
9046
+ .string "boot_addr"
9047
+.LASF191:
9048
+ .string "UCLASS_PINCTRL"
9049
+.LASF201:
9050
+ .string "UCLASS_RAMDISK"
9051
+.LASF148:
9052
+ .string "UCLASS_I2C_EMUL"
9053
+.LASF365:
9054
+ .string "TASK_LOAD_ANDROID"
9055
+.LASF207:
9056
+ .string "UCLASS_SPMI"
9057
+.LASF378:
9058
+ .string "tdata"
9059
+.LASF145:
9060
+ .string "UCLASS_TEST_BUS"
9061
+.LASF417:
9062
+ .string "flush_dcache_all"
9063
+.LASF304:
9064
+ .string "save_addr"
9065
+.LASF426:
9066
+ .string "flush_dcache_range"
9067
+.LASF288:
9068
+ .string "malloc_ptr"
9069
+.LASF411:
9070
+ .string "cpuectlr_disable"
9071
+.LASF386:
9072
+ .string "mpb_task_run"
9073
+.LASF408:
9074
+ .string "spl_load_fit"
9075
+.LASF134:
9076
+ .string "initrd_end"
9077
+.LASF359:
9078
+ .string "EVT_VIDEO_BP"
9079
+.LASF253:
9080
+ .string "baudrate"
9081
+.LASF74:
9082
+ .string "_datarellocal_start_ofs"
9083
+.LASF242:
9084
+ .string "arch_global_data"
9085
+.LASF239:
9086
+ .string "UCLASS_COUNT"
9087
+.LASF349:
9088
+ .string "CPU_0"
9089
+.LASF259:
9090
+ .string "pci_clk"
9091
+.LASF351:
9092
+ .string "CPU_2"
9093
+.LASF352:
9094
+ .string "CPU_3"
9095
+.LASF30:
9096
+ .string "block_drvr"
9097
+.LASF433:
9098
+ .string "memcpy"
9099
+.LASF35:
9100
+ .string "flash_id"
9101
+.LASF231:
9102
+ .string "UCLASS_CRYPTO"
9103
+.LASF297:
9104
+ .string "device_node"
9105
+.LASF267:
9106
+ .string "ram_size"
9107
+.LASF128:
9108
+ .string "fit_noffset_setup"
9109
+.LASF89:
9110
+ .string "working_fdt"
9111
+.LASF282:
9112
+ .string "fdt_blob_kern"
9113
+.LASF313:
9114
+ .string "net_root_path"
9115
+.LASF161:
9116
+ .string "UCLASS_DMA"
9117
+.LASF69:
9118
+ .string "bd_t"
9119
+.LASF237:
9120
+ .string "UCLASS_DMC"
9121
+.LASF307:
9122
+ .string "s_addr"
9123
+.LASF322:
9124
+ .string "net_bcast_ethaddr"
9125
+.LASF379:
9126
+ .string "mpb_gd"
9127
+.LASF67:
9128
+ .string "bi_boot_params"
9129
+.LASF308:
9130
+ .string "net_gateway"
9131
+.LASF50:
9132
+ .string "bi_memstart"
9133
+.LASF222:
9134
+ .string "UCLASS_VIDEO_CONSOLE"
9135
+.LASF48:
9136
+ .string "reserved"
9137
+.LASF360:
9138
+ .string "TASK_NONE"
9139
+.LASF238:
9140
+ .string "UCLASS_PD"
9141
+.LASF423:
9142
+ .string "dcache_disable"
9143
+.LASF68:
9144
+ .string "bi_dram"
9145
+.LASF2:
9146
+ .string "short unsigned int"
9147
+.LASF79:
9148
+ .string "magic"
9149
+.LASF126:
9150
+ .string "fit_hdr_setup"
9151
+.LASF115:
9152
+ .string "legacy_hdr_valid"
9153
+.LASF368:
9154
+ .string "TASK_MAX"
9155
+.LASF44:
9156
+ .string "base"
9157
+.LASF432:
9158
+ .string "spl_dummy"
9159
+.LASF202:
9160
+ .string "UCLASS_RTC"
9161
+.LASF353:
9162
+ .string "EVT_BOOT_DEV"
9163
+.LASF243:
9164
+ .string "timer_rate_hz"
9165
+.LASF34:
9166
+ .string "sector_count"
9167
+.LASF101:
9168
+ .string "ih_comp"
9169
+.LASF385:
9170
+ .string "core_main"
9171
+.LASF131:
9172
+ .string "ft_addr"
9173
+.LASF232:
9174
+ .string "UCLASS_ETH_PHY"
9175
+.LASF380:
9176
+ .string "task_init"
9177
+.LASF4:
9178
+ .string "uchar"
9179
+.LASF132:
9180
+ .string "ft_len"
9181
+.LASF27:
9182
+ .string "next"
9183
+.LASF405:
9184
+ .string "data"
9185
+.LASF181:
9186
+ .string "UCLASS_NOP"
9187
+.LASF367:
9188
+ .string "TASK_RUN_UBOOT"
9189
+.LASF357:
9190
+ .string "EVT_LINUX"
9191
+.LASF127:
9192
+ .string "fit_uname_setup"
9193
+.LASF28:
9194
+ .string "prev"
9195
+.LASF424:
9196
+ .string "invalidate_dcache_all"
9197
+.LASF186:
9198
+ .string "UCLASS_PCH"
9199
+.LASF187:
9200
+ .string "UCLASS_PCI"
9201
+.LASF309:
9202
+ .string "net_netmask"
9203
+.LASF70:
9204
+ .string "IRQ_STACK_START"
9205
+.LASF152:
9206
+ .string "UCLASS_ADC"
9207
+.LASF147:
9208
+ .string "UCLASS_SPI_EMUL"
9209
+.LASF409:
9210
+ .string "spl_load_baseparamter"
9211
+.LASF124:
9212
+ .string "fit_uname_fdt"
9213
+ .ident "GCC: (Linaro GCC 6.3-2017.05) 6.3.1 20170404"
9214
+ .section .note.GNU-stack,"",@progbits
u-boot/configs/px30-tb_defconfig
....@@ -4,7 +4,7 @@
44 CONFIG_SPL_LIBGENERIC_SUPPORT=y
55 CONFIG_SYS_MALLOC_F_LEN=0x80000
66 CONFIG_ROCKCHIP_PX30=y
7
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
7
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
88 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
99 CONFIG_ROCKCHIP_FIT_IMAGE=y
1010 CONFIG_ROCKCHIP_VENDOR_PARTITION=y
u-boot/configs/px30_defconfig
....@@ -135,6 +135,7 @@
135135 CONFIG_LCD=y
136136 CONFIG_USE_TINY_PRINTF=y
137137 CONFIG_SPL_TINY_MEMSET=y
138
+CONFIG_XBC=y
138139 CONFIG_LZ4=y
139140 CONFIG_LZO=y
140141 CONFIG_ERRNO_STR=y
u-boot/configs/rk-amp.config
....@@ -0,0 +1,3 @@
1
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
2
+CONFIG_AMP=y
3
+CONFIG_ROCKCHIP_AMP=y
u-boot/configs/rk3036_defconfig
....@@ -73,11 +73,13 @@
7373 CONFIG_SYS_I2C_ROCKCHIP=y
7474 CONFIG_DM_KEY=y
7575 CONFIG_ADC_KEY=y
76
+CONFIG_GPIO_KEY=y
7677 CONFIG_LED=y
7778 CONFIG_MMC_DW=y
7879 CONFIG_MMC_DW_ROCKCHIP=y
7980 CONFIG_SPI_FLASH=y
8081 CONFIG_SF_DEFAULT_SPEED=20000000
82
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
8183 CONFIG_PINCTRL=y
8284 CONFIG_SPL_PINCTRL=y
8385 CONFIG_REGULATOR_PWM=y
u-boot/configs/rk3126_defconfig
....@@ -15,6 +15,7 @@
1515 # CONFIG_DISPLAY_CPUINFO is not set
1616 CONFIG_ANDROID_BOOTLOADER=y
1717 CONFIG_ANDROID_AVB=y
18
+# CONFIG_SKIP_RELOCATE_UBOOT is not set
1819 CONFIG_FASTBOOT_BUF_ADDR=0x60800800
1920 CONFIG_FASTBOOT_BUF_SIZE=0x04000000
2021 CONFIG_FASTBOOT_FLASH=y
u-boot/configs/rk3128_defconfig
....@@ -2,7 +2,6 @@
22 CONFIG_ARCH_ROCKCHIP=y
33 CONFIG_SYS_MALLOC_F_LEN=0x38000
44 CONFIG_ROCKCHIP_RK3128=y
5
-CONFIG_RKIMG_BOOTLOADER=y
65 CONFIG_ROCKCHIP_VENDOR_PARTITION=y
76 CONFIG_DEFAULT_DEVICE_TREE="rk3126-evb"
87 CONFIG_DEBUG_UART=y
....@@ -13,6 +12,7 @@
1312 # CONFIG_DISPLAY_CPUINFO is not set
1413 CONFIG_ANDROID_BOOTLOADER=y
1514 CONFIG_ANDROID_AVB=y
15
+# CONFIG_SKIP_RELOCATE_UBOOT is not set
1616 CONFIG_FASTBOOT_BUF_ADDR=0x60800800
1717 CONFIG_FASTBOOT_BUF_SIZE=0x04000000
1818 CONFIG_FASTBOOT_FLASH=y
....@@ -82,9 +82,6 @@
8282 CONFIG_USB_GADGET=y
8383 CONFIG_USB_GADGET_DWC2_OTG=y
8484 CONFIG_USB_GADGET_DOWNLOAD=y
85
-CONFIG_G_DNL_MANUFACTURER="Rockchip"
86
-CONFIG_G_DNL_VENDOR_NUM=0x2207
87
-CONFIG_G_DNL_PRODUCT_NUM=0x310c
8885 CONFIG_DM_VIDEO=y
8986 CONFIG_DISPLAY=y
9087 CONFIG_VIDEO_ROCKCHIP=y
u-boot/configs/rk3128x_defconfig
....@@ -120,7 +120,7 @@
120120 CONFIG_DRM_ROCKCHIP=y
121121 CONFIG_DRM_ROCKCHIP_DW_HDMI=y
122122 CONFIG_ROCKCHIP_INNO_HDMI_PHY=y
123
-CONFIG_ROCKCHIP_DRM_TVE=y
123
+CONFIG_DRM_ROCKCHIP_TVE=y
124124 CONFIG_LCD=y
125125 CONFIG_USE_TINY_PRINTF=y
126126 CONFIG_SPL_TINY_MEMSET=y
u-boot/configs/rk312x-rkflash.config
....@@ -0,0 +1,6 @@
1
+CONFIG_RKFLASH=y
2
+# CONFIG_RKNAND is not set
3
+CONFIG_CMD_RKSFC=y
4
+CONFIG_RKNANDC_NAND=y
5
+CONFIG_RKSFC_NAND=y
6
+CONFIG_RKSFC_NOR=y
u-boot/configs/rk322x_defconfig
....@@ -115,7 +115,7 @@
115115 CONFIG_DRM_ROCKCHIP=y
116116 CONFIG_DRM_ROCKCHIP_DW_HDMI=y
117117 CONFIG_ROCKCHIP_INNO_HDMI_PHY=y
118
-CONFIG_ROCKCHIP_DRM_TVE=y
118
+CONFIG_DRM_ROCKCHIP_TVE=y
119119 CONFIG_LCD=y
120120 CONFIG_USE_TINY_PRINTF=y
121121 CONFIG_SPL_TINY_MEMSET=y
u-boot/configs/rk3308-amp.config
....@@ -0,0 +1,3 @@
1
+CONFIG_AMP=y
2
+CONFIG_BASE_DEFCONFIG="rk3308_defconfig"
3
+CONFIG_ROCKCHIP_AMP=y
u-boot/configs/rk3326_defconfig
....@@ -69,6 +69,8 @@
6969 CONFIG_SPL_SYSCON=y
7070 CONFIG_CLK=y
7171 CONFIG_SPL_CLK=y
72
+CONFIG_AMP=y
73
+CONFIG_ROCKCHIP_AMP=y
7274 CONFIG_DM_CRYPTO=y
7375 CONFIG_ROCKCHIP_CRYPTO_V2=y
7476 CONFIG_ROCKCHIP_GPIO=y
....@@ -128,6 +130,8 @@
128130 CONFIG_LCD=y
129131 CONFIG_USE_TINY_PRINTF=y
130132 CONFIG_SPL_TINY_MEMSET=y
133
+CONFIG_XBC=y
134
+CONFIG_SHA256=y
131135 CONFIG_LZ4=y
132136 CONFIG_LZO=y
133137 CONFIG_ERRNO_STR=y
u-boot/configs/rk3328_defconfig
....@@ -129,7 +129,7 @@
129129 CONFIG_DRM_ROCKCHIP_PANEL=y
130130 CONFIG_DRM_ROCKCHIP_DW_HDMI=y
131131 CONFIG_ROCKCHIP_INNO_HDMI_PHY=y
132
-CONFIG_ROCKCHIP_DRM_TVE=y
132
+CONFIG_DRM_ROCKCHIP_TVE=y
133133 CONFIG_LCD=y
134134 # CONFIG_IRQ is not set
135135 CONFIG_USE_TINY_PRINTF=y
u-boot/configs/rk3399_defconfig
....@@ -90,8 +90,8 @@
9090 CONFIG_PINCTRL=y
9191 CONFIG_SPL_PINCTRL=y
9292 CONFIG_DM_FUEL_GAUGE=y
93
-CONFIG_POWER_FG_RK817=y
9493 CONFIG_POWER_FG_RK818=y
94
+CONFIG_POWER_FG_RK817=y
9595 CONFIG_IO_DOMAIN=y
9696 CONFIG_ROCKCHIP_IO_DOMAIN=y
9797 CONFIG_DM_PMIC=y
....@@ -137,6 +137,7 @@
137137 CONFIG_USE_TINY_PRINTF=y
138138 CONFIG_LIB_RAND=y
139139 CONFIG_SPL_TINY_MEMSET=y
140
+CONFIG_XBC=y
140141 CONFIG_ERRNO_STR=y
141142 CONFIG_AVB_LIBAVB=y
142143 CONFIG_AVB_LIBAVB_AB=y
u-boot/configs/rk3528-aarch32.config
....@@ -0,0 +1,24 @@
1
+CONFIG_ARM64_BOOT_AARCH32=y
2
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
3
+# CONFIG_ARMV7_LPAE is not set
4
+CONFIG_BASE_DEFCONFIG="rk3528_defconfig"
5
+CONFIG_BOOTP_PXE_CLIENTARCH=0x15
6
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7"
7
+CONFIG_CPU_V7=y
8
+# CONFIG_DEBUG_LL is not set
9
+CONFIG_HAS_THUMB2=y
10
+CONFIG_HAS_VBAR=y
11
+CONFIG_HAVE_PRIVATE_LIBGCC=y
12
+# CONFIG_PHYS_64BIT is not set
13
+# CONFIG_SPL_OF_LIBFDT is not set
14
+CONFIG_SPL_SYS_THUMB_BUILD=y
15
+CONFIG_SPL_USE_ARCH_MEMCPY=y
16
+CONFIG_SPL_USE_ARCH_MEMSET=y
17
+CONFIG_SYS_ARM_ARCH=7
18
+CONFIG_SYS_CPU="armv7"
19
+CONFIG_SYS_THUMB_BUILD=y
20
+CONFIG_TPL_USE_ARCH_MEMCPY=y
21
+CONFIG_TPL_USE_ARCH_MEMSET=y
22
+CONFIG_USE_ARCH_MEMCPY=y
23
+CONFIG_USE_ARCH_MEMSET=y
24
+CONFIG_USE_PRIVATE_LIBGCC=y
u-boot/configs/rk3528_defconfig
....@@ -0,0 +1,201 @@
1
+CONFIG_ARM=y
2
+CONFIG_ARM_SMCCC=y
3
+CONFIG_ARCH_ROCKCHIP=y
4
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
5
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
6
+CONFIG_SYS_MALLOC_F_LEN=0x80000
7
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
8
+CONFIG_ROCKCHIP_RK3528=y
9
+CONFIG_ROCKCHIP_FIT_IMAGE=y
10
+CONFIG_ROCKCHIP_VENDOR_PARTITION=y
11
+CONFIG_USING_KERNEL_DTB_V2=y
12
+CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
13
+CONFIG_ROCKCHIP_NEW_IDB=y
14
+CONFIG_SPL_SERIAL_SUPPORT=y
15
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
16
+CONFIG_TARGET_EVB_RK3528=y
17
+CONFIG_SPL_LIBDISK_SUPPORT=y
18
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
19
+CONFIG_SPL_SPI_SUPPORT=y
20
+CONFIG_DEFAULT_DEVICE_TREE="rk3528-evb"
21
+CONFIG_DEBUG_UART=y
22
+CONFIG_FIT=y
23
+CONFIG_FIT_IMAGE_POST_PROCESS=y
24
+CONFIG_FIT_HW_CRYPTO=y
25
+CONFIG_SPL_LOAD_FIT=y
26
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
27
+CONFIG_SPL_FIT_HW_CRYPTO=y
28
+# CONFIG_SPL_SYS_DCACHE_OFF is not set
29
+CONFIG_BOOTDELAY=0
30
+# CONFIG_CONSOLE_MUX is not set
31
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
32
+# CONFIG_DISPLAY_CPUINFO is not set
33
+CONFIG_ANDROID_BOOTLOADER=y
34
+CONFIG_ANDROID_AVB=y
35
+CONFIG_ANDROID_BOOT_IMAGE_HASH=y
36
+CONFIG_SPL_BOARD_INIT=y
37
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
38
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
39
+CONFIG_SPL_SEPARATE_BSS=y
40
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
41
+CONFIG_SPL_CRYPTO_SUPPORT=y
42
+CONFIG_SPL_MMC_WRITE=y
43
+CONFIG_SPL_MTD_SUPPORT=y
44
+CONFIG_SPL_MTD_WRITE=y
45
+CONFIG_SPL_ATF=y
46
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
47
+CONFIG_SPL_AB=y
48
+CONFIG_FASTBOOT_BUF_ADDR=0xc00800
49
+CONFIG_FASTBOOT_BUF_SIZE=0x04000000
50
+CONFIG_FASTBOOT_FLASH=y
51
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
52
+CONFIG_CMD_BOOTZ=y
53
+CONFIG_CMD_DTIMG=y
54
+# CONFIG_CMD_ELF is not set
55
+# CONFIG_CMD_IMI is not set
56
+# CONFIG_CMD_IMLS is not set
57
+# CONFIG_CMD_XIMG is not set
58
+# CONFIG_CMD_LZMADEC is not set
59
+# CONFIG_CMD_UNZIP is not set
60
+# CONFIG_CMD_FLASH is not set
61
+# CONFIG_CMD_FPGA is not set
62
+CONFIG_CMD_GPT=y
63
+# CONFIG_CMD_LOADB is not set
64
+# CONFIG_CMD_LOADS is not set
65
+CONFIG_CMD_BOOT_ANDROID=y
66
+CONFIG_CMD_MMC=y
67
+CONFIG_CMD_MTD=y
68
+CONFIG_CMD_USB=y
69
+CONFIG_CMD_USB_MASS_STORAGE=y
70
+# CONFIG_CMD_ITEST is not set
71
+# CONFIG_CMD_SETEXPR is not set
72
+CONFIG_CMD_TFTPPUT=y
73
+CONFIG_CMD_TFTP_BOOTM=y
74
+CONFIG_CMD_TFTP_FLASH=y
75
+# CONFIG_CMD_MISC is not set
76
+CONFIG_CMD_MTD_BLK=y
77
+# CONFIG_SPL_DOS_PARTITION is not set
78
+# CONFIG_ISO_PARTITION is not set
79
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
80
+CONFIG_SPL_OF_CONTROL=y
81
+CONFIG_SPL_DTB_MINIMUM=y
82
+CONFIG_OF_LIVE=y
83
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clock-parents"
84
+# CONFIG_NET_TFTP_VARS is not set
85
+CONFIG_REGMAP=y
86
+CONFIG_SPL_REGMAP=y
87
+CONFIG_SYSCON=y
88
+CONFIG_SPL_SYSCON=y
89
+# CONFIG_SARADC_ROCKCHIP is not set
90
+CONFIG_SARADC_ROCKCHIP_V2=y
91
+CONFIG_CLK=y
92
+CONFIG_SPL_CLK=y
93
+CONFIG_CLK_SCMI=y
94
+CONFIG_SPL_CLK_SCMI=y
95
+CONFIG_DM_CRYPTO=y
96
+CONFIG_SPL_DM_CRYPTO=y
97
+CONFIG_ROCKCHIP_CRYPTO_V2=y
98
+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
99
+CONFIG_DM_RNG=y
100
+CONFIG_RNG_ROCKCHIP=y
101
+CONFIG_SCMI_FIRMWARE=y
102
+CONFIG_SPL_SCMI_FIRMWARE=y
103
+CONFIG_ROCKCHIP_GPIO=y
104
+CONFIG_ROCKCHIP_GPIO_V2=y
105
+CONFIG_SYS_I2C_ROCKCHIP=y
106
+CONFIG_DM_KEY=y
107
+CONFIG_ADC_KEY=y
108
+CONFIG_MISC=y
109
+CONFIG_SPL_MISC=y
110
+CONFIG_ROCKCHIP_OTP=y
111
+CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
112
+CONFIG_MMC_DW=y
113
+CONFIG_MMC_DW_ROCKCHIP=y
114
+CONFIG_MMC_SDHCI=y
115
+CONFIG_MMC_SDHCI_SDMA=y
116
+CONFIG_MMC_SDHCI_ROCKCHIP=y
117
+CONFIG_MTD=y
118
+CONFIG_MTD_BLK=y
119
+CONFIG_MTD_DEVICE=y
120
+CONFIG_MTD_SPI_NAND=y
121
+CONFIG_SPI_FLASH=y
122
+CONFIG_SPI_FLASH_EON=y
123
+CONFIG_SPI_FLASH_GIGADEVICE=y
124
+CONFIG_SPI_FLASH_ISSI=y
125
+CONFIG_SPI_FLASH_MACRONIX=y
126
+CONFIG_SPI_FLASH_WINBOND=y
127
+CONFIG_SPI_FLASH_XMC=y
128
+CONFIG_SPI_FLASH_XTX=y
129
+CONFIG_SPI_FLASH_PUYA=y
130
+CONFIG_SPI_FLASH_FMSH=y
131
+CONFIG_SPI_FLASH_DOSILICON=y
132
+CONFIG_SPI_FLASH_BOYA=y
133
+CONFIG_SPI_FLASH_MTD=y
134
+CONFIG_SPL_SPI_FLASH_MTD=y
135
+CONFIG_PHY_RK630=y
136
+CONFIG_DM_ETH=y
137
+CONFIG_DM_ETH_PHY=y
138
+CONFIG_DWC_ETH_QOS=y
139
+CONFIG_GMAC_ROCKCHIP=y
140
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
141
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
142
+CONFIG_PINCTRL=y
143
+CONFIG_SPL_PINCTRL=y
144
+CONFIG_REGULATOR_PWM=y
145
+CONFIG_DM_REGULATOR_FIXED=y
146
+CONFIG_DM_REGULATOR_GPIO=y
147
+CONFIG_PWM_ROCKCHIP=y
148
+CONFIG_RAM=y
149
+CONFIG_SPL_RAM=y
150
+CONFIG_TPL_RAM=y
151
+CONFIG_DM_RESET=y
152
+CONFIG_SPL_DM_RESET=y
153
+CONFIG_SPL_RESET_ROCKCHIP=y
154
+CONFIG_BAUDRATE=1500000
155
+CONFIG_DEBUG_UART_BASE=0xff9f0000
156
+CONFIG_DEBUG_UART_CLOCK=24000000
157
+CONFIG_DEBUG_UART_SHIFT=2
158
+CONFIG_ROCKCHIP_SFC=y
159
+CONFIG_SYSRESET=y
160
+CONFIG_USB=y
161
+CONFIG_USB_XHCI_HCD=y
162
+CONFIG_USB_XHCI_DWC3=y
163
+CONFIG_USB_EHCI_HCD=y
164
+CONFIG_USB_EHCI_GENERIC=y
165
+CONFIG_USB_OHCI_HCD=y
166
+CONFIG_USB_OHCI_GENERIC=y
167
+CONFIG_USB_DWC3=y
168
+CONFIG_USB_DWC3_GADGET=y
169
+CONFIG_USB_DWC3_GENERIC=y
170
+CONFIG_USB_STORAGE=y
171
+CONFIG_USB_GADGET=y
172
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
173
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207
174
+CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
175
+CONFIG_USB_GADGET_DOWNLOAD=y
176
+CONFIG_DM_VIDEO=y
177
+CONFIG_DISPLAY=y
178
+CONFIG_VIDEO_ROCKCHIP=y
179
+CONFIG_DRM_ROCKCHIP=y
180
+CONFIG_DRM_ROCKCHIP_DW_HDMI=y
181
+CONFIG_ROCKCHIP_INNO_HDMI_PHY=y
182
+CONFIG_DRM_ROCKCHIP_TVE=y
183
+CONFIG_USE_TINY_PRINTF=y
184
+CONFIG_SPL_TINY_MEMSET=y
185
+CONFIG_RSA=y
186
+CONFIG_SPL_RSA=y
187
+CONFIG_RSA_N_SIZE=0x200
188
+CONFIG_RSA_E_SIZE=0x10
189
+CONFIG_RSA_C_SIZE=0x20
190
+CONFIG_LZ4=y
191
+CONFIG_LZMA=y
192
+CONFIG_SPL_GZIP=y
193
+CONFIG_ERRNO_STR=y
194
+# CONFIG_EFI_LOADER is not set
195
+CONFIG_AVB_LIBAVB=y
196
+CONFIG_AVB_LIBAVB_AB=y
197
+CONFIG_AVB_LIBAVB_ATX=y
198
+CONFIG_AVB_LIBAVB_USER=y
199
+CONFIG_RK_AVB_LIBAVB_USER=y
200
+CONFIG_OPTEE_CLIENT=y
201
+CONFIG_OPTEE_V2=y
u-boot/configs/rk3562_defconfig
....@@ -0,0 +1,211 @@
1
+CONFIG_ARM=y
2
+CONFIG_ARCH_ROCKCHIP=y
3
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
4
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
5
+CONFIG_SYS_MALLOC_F_LEN=0x80000
6
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
7
+CONFIG_ROCKCHIP_RK3562=y
8
+CONFIG_ROCKCHIP_FIT_IMAGE=y
9
+CONFIG_ROCKCHIP_VENDOR_PARTITION=y
10
+CONFIG_USING_KERNEL_DTB_V2=y
11
+CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
12
+CONFIG_ROCKCHIP_NEW_IDB=y
13
+CONFIG_SPL_SERIAL_SUPPORT=y
14
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
15
+CONFIG_TARGET_EVB_RK3562=y
16
+CONFIG_SPL_LIBDISK_SUPPORT=y
17
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
18
+CONFIG_SPL_SPI_SUPPORT=y
19
+CONFIG_DEFAULT_DEVICE_TREE="rk3562-evb"
20
+CONFIG_DEBUG_UART=y
21
+CONFIG_FIT=y
22
+CONFIG_FIT_IMAGE_POST_PROCESS=y
23
+CONFIG_FIT_HW_CRYPTO=y
24
+CONFIG_SPL_LOAD_FIT=y
25
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
26
+CONFIG_SPL_FIT_HW_CRYPTO=y
27
+# CONFIG_SPL_SYS_DCACHE_OFF is not set
28
+CONFIG_BOOTDELAY=0
29
+# CONFIG_CONSOLE_MUX is not set
30
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
31
+# CONFIG_DISPLAY_CPUINFO is not set
32
+CONFIG_ANDROID_BOOTLOADER=y
33
+CONFIG_ANDROID_AVB=y
34
+CONFIG_ANDROID_BOOT_IMAGE_HASH=y
35
+CONFIG_SPL_BOARD_INIT=y
36
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
37
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
38
+CONFIG_SPL_SEPARATE_BSS=y
39
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
40
+CONFIG_SPL_MMC_WRITE=y
41
+CONFIG_SPL_MTD_SUPPORT=y
42
+CONFIG_SPL_MTD_WRITE=y
43
+CONFIG_SPL_ATF=y
44
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
45
+CONFIG_SPL_AB=y
46
+CONFIG_FASTBOOT_BUF_ADDR=0xc00800
47
+CONFIG_FASTBOOT_BUF_SIZE=0x04000000
48
+CONFIG_FASTBOOT_FLASH=y
49
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
50
+# CONFIG_CMD_BDI is not set
51
+CONFIG_CMD_BOOTZ=y
52
+CONFIG_CMD_DTIMG=y
53
+# CONFIG_CMD_ELF is not set
54
+# CONFIG_CMD_IMI is not set
55
+# CONFIG_CMD_IMLS is not set
56
+# CONFIG_CMD_XIMG is not set
57
+# CONFIG_CMD_LZMADEC is not set
58
+# CONFIG_CMD_UNZIP is not set
59
+# CONFIG_CMD_FLASH is not set
60
+# CONFIG_CMD_FPGA is not set
61
+CONFIG_CMD_GPT=y
62
+# CONFIG_CMD_LOADB is not set
63
+# CONFIG_CMD_LOADS is not set
64
+CONFIG_CMD_BOOT_ANDROID=y
65
+CONFIG_CMD_MMC=y
66
+CONFIG_CMD_MTD=y
67
+CONFIG_CMD_SF=y
68
+CONFIG_CMD_SPI=y
69
+CONFIG_CMD_USB=y
70
+CONFIG_CMD_USB_MASS_STORAGE=y
71
+# CONFIG_CMD_ITEST is not set
72
+# CONFIG_CMD_SETEXPR is not set
73
+# CONFIG_CMD_MISC is not set
74
+CONFIG_CMD_MTD_BLK=y
75
+# CONFIG_ISO_PARTITION is not set
76
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
77
+CONFIG_SPL_OF_CONTROL=y
78
+CONFIG_SPL_DTB_MINIMUM=y
79
+CONFIG_OF_LIVE=y
80
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
81
+# CONFIG_NET_TFTP_VARS is not set
82
+CONFIG_REGMAP=y
83
+CONFIG_SPL_REGMAP=y
84
+CONFIG_SYSCON=y
85
+CONFIG_SPL_SYSCON=y
86
+# CONFIG_SARADC_ROCKCHIP is not set
87
+CONFIG_SARADC_ROCKCHIP_V2=y
88
+CONFIG_CLK=y
89
+CONFIG_SPL_CLK=y
90
+CONFIG_CLK_SCMI=y
91
+CONFIG_SPL_CLK_SCMI=y
92
+CONFIG_DM_CRYPTO=y
93
+CONFIG_SPL_DM_CRYPTO=y
94
+CONFIG_ROCKCHIP_CRYPTO_V2=y
95
+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
96
+CONFIG_DM_RNG=y
97
+CONFIG_RNG_ROCKCHIP=y
98
+CONFIG_SCMI_FIRMWARE=y
99
+CONFIG_SPL_SCMI_FIRMWARE=y
100
+CONFIG_ROCKCHIP_GPIO=y
101
+CONFIG_ROCKCHIP_GPIO_V2=y
102
+CONFIG_SYS_I2C_ROCKCHIP=y
103
+CONFIG_DM_KEY=y
104
+CONFIG_RK8XX_PWRKEY=y
105
+CONFIG_ADC_KEY=y
106
+CONFIG_MISC=y
107
+CONFIG_SPL_MISC=y
108
+CONFIG_ROCKCHIP_OTP=y
109
+CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
110
+CONFIG_MMC_DW=y
111
+CONFIG_MMC_DW_ROCKCHIP=y
112
+CONFIG_MMC_SDHCI=y
113
+CONFIG_MMC_SDHCI_SDMA=y
114
+CONFIG_MMC_SDHCI_ROCKCHIP=y
115
+CONFIG_MTD=y
116
+CONFIG_MTD_BLK=y
117
+CONFIG_MTD_DEVICE=y
118
+CONFIG_MTD_SPI_NAND=y
119
+CONFIG_SPI_FLASH=y
120
+CONFIG_SF_DEFAULT_MODE=0x3
121
+CONFIG_SPI_FLASH_GIGADEVICE=y
122
+CONFIG_SPI_FLASH_MACRONIX=y
123
+CONFIG_SPI_FLASH_SST=y
124
+CONFIG_SPI_FLASH_WINBOND=y
125
+CONFIG_SPI_FLASH_XMC=y
126
+CONFIG_SPI_FLASH_XTX=y
127
+CONFIG_SPI_FLASH_PUYA=y
128
+CONFIG_SPI_FLASH_FMSH=y
129
+CONFIG_SPI_FLASH_DOSILICON=y
130
+CONFIG_SPI_FLASH_BOYA=y
131
+CONFIG_SPI_FLASH_NORMEM=y
132
+CONFIG_SPI_FLASH_MTD=y
133
+CONFIG_SPL_SPI_FLASH_MTD=y
134
+CONFIG_DM_ETH=y
135
+CONFIG_DM_ETH_PHY=y
136
+CONFIG_DWC_ETH_QOS=y
137
+CONFIG_GMAC_ROCKCHIP=y
138
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
139
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
140
+CONFIG_PINCTRL=y
141
+CONFIG_SPL_PINCTRL=y
142
+CONFIG_DM_FUEL_GAUGE=y
143
+CONFIG_POWER_FG_RK817=y
144
+CONFIG_DM_PMIC=y
145
+CONFIG_PMIC_RK8XX=y
146
+CONFIG_REGULATOR_FAN53555=y
147
+CONFIG_REGULATOR_PWM=y
148
+CONFIG_DM_REGULATOR_FIXED=y
149
+CONFIG_DM_REGULATOR_GPIO=y
150
+CONFIG_REGULATOR_RK8XX=y
151
+CONFIG_DM_CHARGE_DISPLAY=y
152
+CONFIG_CHARGE_ANIMATION=y
153
+CONFIG_PWM_ROCKCHIP=y
154
+CONFIG_RAM=y
155
+CONFIG_SPL_RAM=y
156
+CONFIG_TPL_RAM=y
157
+CONFIG_DM_DMC=y
158
+CONFIG_DM_RESET=y
159
+CONFIG_SPL_DM_RESET=y
160
+CONFIG_SPL_RESET_ROCKCHIP=y
161
+CONFIG_BAUDRATE=1500000
162
+CONFIG_DEBUG_UART_BASE=0xff210000
163
+CONFIG_DEBUG_UART_CLOCK=24000000
164
+CONFIG_DEBUG_UART_SHIFT=2
165
+CONFIG_ROCKCHIP_SFC=y
166
+CONFIG_SYSRESET=y
167
+CONFIG_USB=y
168
+CONFIG_USB_XHCI_HCD=y
169
+CONFIG_USB_XHCI_DWC3=y
170
+CONFIG_USB_EHCI_HCD=y
171
+CONFIG_USB_EHCI_GENERIC=y
172
+CONFIG_USB_OHCI_HCD=y
173
+CONFIG_USB_OHCI_GENERIC=y
174
+CONFIG_USB_DWC3=y
175
+CONFIG_USB_DWC3_GADGET=y
176
+CONFIG_USB_DWC3_GENERIC=y
177
+CONFIG_USB_STORAGE=y
178
+CONFIG_USB_GADGET=y
179
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
180
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207
181
+CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
182
+CONFIG_USB_GADGET_DOWNLOAD=y
183
+CONFIG_DM_VIDEO=y
184
+CONFIG_DISPLAY=y
185
+CONFIG_DRM_ROCKCHIP=y
186
+CONFIG_DRM_ROCKCHIP_INNO_VIDEO_COMBO_PHY=y
187
+CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI=y
188
+CONFIG_DRM_ROCKCHIP_LVDS=y
189
+CONFIG_DRM_ROCKCHIP_RGB=y
190
+CONFIG_USE_TINY_PRINTF=y
191
+CONFIG_SPL_TINY_MEMSET=y
192
+CONFIG_RSA=y
193
+CONFIG_SPL_RSA=y
194
+CONFIG_RSA_N_SIZE=0x200
195
+CONFIG_RSA_E_SIZE=0x10
196
+CONFIG_RSA_C_SIZE=0x20
197
+CONFIG_XBC=y
198
+CONFIG_SHA1=y
199
+CONFIG_SHA256=y
200
+CONFIG_LZ4=y
201
+CONFIG_SPL_GZIP=y
202
+CONFIG_ERRNO_STR=y
203
+# CONFIG_EFI_LOADER is not set
204
+CONFIG_AVB_LIBAVB=y
205
+CONFIG_AVB_LIBAVB_AB=y
206
+CONFIG_AVB_LIBAVB_ATX=y
207
+CONFIG_AVB_LIBAVB_USER=y
208
+CONFIG_RK_AVB_LIBAVB_USER=y
209
+CONFIG_OPTEE_CLIENT=y
210
+CONFIG_OPTEE_V2=y
211
+CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y
u-boot/configs/rk3568-rt.config
....@@ -0,0 +1,2 @@
1
+CONFIG_BASE_DEFCONFIG="rk3568_defconfig"
2
+CONFIG_TRUST_INI="RK3568TRUST_RT.ini"
u-boot/configs/rk3568-spl-spi-nand_defconfig
....@@ -26,9 +26,6 @@
2626 CONFIG_BOOTDELAY=0
2727 CONFIG_SYS_CONSOLE_INFO_QUIET=y
2828 # CONFIG_DISPLAY_CPUINFO is not set
29
-# CONFIG_ANDROID_WRITE_KEYBOX is not set
30
-CONFIG_ANDROID_AVB=y
31
-# CONFIG_ANDROID_KEYMASTER_CA is not set
3229 CONFIG_SPL_BOARD_INIT=y
3330 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
3431 # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
....@@ -183,12 +180,4 @@
183180 CONFIG_RSA_E_SIZE=0x10
184181 CONFIG_RSA_C_SIZE=0x20
185182 CONFIG_SHA512=y
186
-CONFIG_LZ4=y
187183 CONFIG_ERRNO_STR=y
188
-CONFIG_AVB_LIBAVB=y
189
-CONFIG_AVB_LIBAVB_AB=y
190
-CONFIG_AVB_LIBAVB_ATX=y
191
-CONFIG_AVB_LIBAVB_USER=y
192
-CONFIG_RK_AVB_LIBAVB_USER=y
193
-CONFIG_OPTEE_CLIENT=y
194
-CONFIG_OPTEE_V2=y
u-boot/configs/rk3568_defconfig
....@@ -83,6 +83,7 @@
8383 # CONFIG_ISO_PARTITION is not set
8484 CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
8585 CONFIG_SPL_OF_CONTROL=y
86
+CONFIG_SPL_DTB_MINIMUM=y
8687 CONFIG_OF_LIVE=y
8788 CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
8889 # CONFIG_NET_TFTP_VARS is not set
....@@ -206,6 +207,7 @@
206207 CONFIG_RSA_N_SIZE=0x200
207208 CONFIG_RSA_E_SIZE=0x10
208209 CONFIG_RSA_C_SIZE=0x20
210
+CONFIG_XBC=y
209211 CONFIG_SHA512=y
210212 CONFIG_LZ4=y
211213 CONFIG_LZMA=y
u-boot/configs/rk3588-ab.config
....@@ -0,0 +1,3 @@
1
+CONFIG_ANDROID_AB=y
2
+CONFIG_BASE_DEFCONFIG="rk3588_defconfig"
3
+# CONFIG_CMD_ANDROID_AB_SELECT is not set
u-boot/configs/rk3588-qnx_defconfig
....@@ -0,0 +1,212 @@
1
+CONFIG_ARM=y
2
+CONFIG_ARCH_ROCKCHIP=y
3
+CONFIG_SPL_GPIO_SUPPORT=y
4
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
5
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
6
+CONFIG_SYS_MALLOC_F_LEN=0x80000
7
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
8
+CONFIG_ROCKCHIP_RK3588=y
9
+CONFIG_ROCKCHIP_FIT_IMAGE=y
10
+CONFIG_ROCKCHIP_HWID_DTB=y
11
+CONFIG_ROCKCHIP_VENDOR_PARTITION=y
12
+CONFIG_USING_KERNEL_DTB_V2=y
13
+CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
14
+CONFIG_ROCKCHIP_NEW_IDB=y
15
+CONFIG_PSTORE=y
16
+CONFIG_SPL_SERIAL_SUPPORT=y
17
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
18
+CONFIG_TARGET_EVB_RK3588=y
19
+CONFIG_SPL_LIBDISK_SUPPORT=y
20
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb"
21
+CONFIG_DEBUG_UART=y
22
+CONFIG_FIT=y
23
+CONFIG_FIT_IMAGE_POST_PROCESS=y
24
+CONFIG_FIT_HW_CRYPTO=y
25
+CONFIG_FIT_OMIT_UBOOT=y
26
+CONFIG_SPL_LOAD_FIT=y
27
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
28
+CONFIG_SPL_FIT_HW_CRYPTO=y
29
+# CONFIG_SPL_SYS_DCACHE_OFF is not set
30
+CONFIG_BOOTDELAY=0
31
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
32
+# CONFIG_DISPLAY_CPUINFO is not set
33
+CONFIG_ANDROID_BOOTLOADER=y
34
+CONFIG_ANDROID_AVB=y
35
+CONFIG_ANDROID_BOOT_IMAGE_HASH=y
36
+CONFIG_SPL_BOARD_INIT=y
37
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
38
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
39
+CONFIG_SPL_SEPARATE_BSS=y
40
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
41
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
42
+CONFIG_SPL_MMC_WRITE=y
43
+CONFIG_SPL_ATF=y
44
+CONFIG_SPL_KERNEL_BOOT=y
45
+# CONFIG_SPL_KERNEL_BOOT_PREBUILT is not set
46
+CONFIG_FASTBOOT_BUF_ADDR=0xc00800
47
+CONFIG_FASTBOOT_BUF_SIZE=0x07000000
48
+CONFIG_FASTBOOT_FLASH=y
49
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
50
+CONFIG_CMD_BOOTZ=y
51
+CONFIG_CMD_DTIMG=y
52
+# CONFIG_CMD_ELF is not set
53
+# CONFIG_CMD_IMI is not set
54
+# CONFIG_CMD_IMLS is not set
55
+# CONFIG_CMD_XIMG is not set
56
+# CONFIG_CMD_LZMADEC is not set
57
+# CONFIG_CMD_UNZIP is not set
58
+# CONFIG_CMD_FLASH is not set
59
+# CONFIG_CMD_FPGA is not set
60
+CONFIG_CMD_GPT=y
61
+# CONFIG_CMD_LOADB is not set
62
+# CONFIG_CMD_LOADS is not set
63
+CONFIG_CMD_BOOT_ANDROID=y
64
+CONFIG_CMD_MMC=y
65
+CONFIG_CMD_USB=y
66
+CONFIG_CMD_USB_MASS_STORAGE=y
67
+# CONFIG_CMD_ITEST is not set
68
+# CONFIG_CMD_SETEXPR is not set
69
+CONFIG_CMD_TFTPPUT=y
70
+CONFIG_CMD_TFTP_BOOTM=y
71
+CONFIG_CMD_TFTP_FLASH=y
72
+# CONFIG_CMD_MISC is not set
73
+# CONFIG_SPL_DOS_PARTITION is not set
74
+# CONFIG_ISO_PARTITION is not set
75
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
76
+CONFIG_SPL_OF_CONTROL=y
77
+CONFIG_SPL_DTB_MINIMUM=y
78
+CONFIG_OF_LIVE=y
79
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
80
+CONFIG_OF_U_BOOT_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
81
+# CONFIG_NET_TFTP_VARS is not set
82
+CONFIG_REGMAP=y
83
+CONFIG_SPL_REGMAP=y
84
+CONFIG_SYSCON=y
85
+CONFIG_SPL_SYSCON=y
86
+# CONFIG_SARADC_ROCKCHIP is not set
87
+CONFIG_SARADC_ROCKCHIP_V2=y
88
+CONFIG_CLK=y
89
+CONFIG_SPL_CLK=y
90
+CONFIG_CLK_SCMI=y
91
+CONFIG_SPL_CLK_SCMI=y
92
+CONFIG_DM_CRYPTO=y
93
+CONFIG_SPL_DM_CRYPTO=y
94
+CONFIG_ROCKCHIP_CRYPTO_V2=y
95
+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
96
+CONFIG_DM_RNG=y
97
+CONFIG_RNG_ROCKCHIP=y
98
+CONFIG_SCMI_FIRMWARE=y
99
+CONFIG_SPL_SCMI_FIRMWARE=y
100
+CONFIG_GPIO_HOG=y
101
+CONFIG_ROCKCHIP_GPIO=y
102
+CONFIG_ROCKCHIP_GPIO_V2=y
103
+CONFIG_SYS_I2C_ROCKCHIP=y
104
+CONFIG_I2C_MUX=y
105
+CONFIG_DM_KEY=y
106
+CONFIG_RK8XX_PWRKEY=y
107
+CONFIG_ADC_KEY=y
108
+CONFIG_MISC=y
109
+CONFIG_SPL_MISC=y
110
+CONFIG_MISC_DECOMPRESS=y
111
+CONFIG_SPL_MISC_DECOMPRESS=y
112
+CONFIG_ROCKCHIP_OTP=y
113
+CONFIG_ROCKCHIP_HW_DECOMPRESS=y
114
+CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
115
+CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
116
+CONFIG_MMC_SDHCI=y
117
+CONFIG_MMC_SDHCI_SDMA=y
118
+CONFIG_MMC_SDHCI_ROCKCHIP=y
119
+CONFIG_DM_ETH=y
120
+CONFIG_DM_ETH_PHY=y
121
+CONFIG_DWC_ETH_QOS=y
122
+CONFIG_GMAC_ROCKCHIP=y
123
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
124
+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
125
+CONFIG_PHY_ROCKCHIP_USBDP=y
126
+CONFIG_PINCTRL=y
127
+CONFIG_SPL_PINCTRL=y
128
+CONFIG_DM_FUEL_GAUGE=y
129
+CONFIG_POWER_FG_CW201X=y
130
+CONFIG_POWER_FG_CW221X=y
131
+CONFIG_DM_PMIC=y
132
+CONFIG_PMIC_SPI_RK8XX=y
133
+CONFIG_DM_POWER_DELIVERY=y
134
+CONFIG_TYPEC_TCPM=y
135
+CONFIG_TYPEC_TCPCI=y
136
+CONFIG_TYPEC_HUSB311=y
137
+CONFIG_TYPEC_FUSB302=y
138
+CONFIG_REGULATOR_PWM=y
139
+CONFIG_DM_REGULATOR_FIXED=y
140
+CONFIG_DM_REGULATOR_GPIO=y
141
+CONFIG_REGULATOR_RK860X=y
142
+CONFIG_REGULATOR_RK806=y
143
+CONFIG_CHARGER_BQ25700=y
144
+CONFIG_CHARGER_BQ25890=y
145
+CONFIG_CHARGER_SC8551=y
146
+CONFIG_CHARGER_SGM41542=y
147
+CONFIG_DM_CHARGE_DISPLAY=y
148
+CONFIG_CHARGE_ANIMATION=y
149
+CONFIG_PWM_ROCKCHIP=y
150
+CONFIG_RAM=y
151
+CONFIG_SPL_RAM=y
152
+CONFIG_TPL_RAM=y
153
+CONFIG_DM_RAMDISK=y
154
+CONFIG_RAMDISK_RO=y
155
+CONFIG_DM_RESET=y
156
+CONFIG_SPL_DM_RESET=y
157
+CONFIG_SPL_RESET_ROCKCHIP=y
158
+CONFIG_BAUDRATE=1500000
159
+CONFIG_DEBUG_UART_BASE=0xFEB50000
160
+CONFIG_DEBUG_UART_CLOCK=24000000
161
+CONFIG_DEBUG_UART_SHIFT=2
162
+CONFIG_SYSRESET=y
163
+CONFIG_USB=y
164
+CONFIG_USB_XHCI_HCD=y
165
+CONFIG_USB_XHCI_DWC3=y
166
+CONFIG_USB_EHCI_HCD=y
167
+CONFIG_USB_EHCI_GENERIC=y
168
+CONFIG_USB_OHCI_HCD=y
169
+CONFIG_USB_OHCI_GENERIC=y
170
+CONFIG_USB_DWC3=y
171
+CONFIG_USB_DWC3_GADGET=y
172
+CONFIG_USB_DWC3_GENERIC=y
173
+CONFIG_USB_STORAGE=y
174
+CONFIG_USB_GADGET=y
175
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
176
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207
177
+CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
178
+CONFIG_USB_GADGET_DOWNLOAD=y
179
+CONFIG_DM_VIDEO=y
180
+CONFIG_DISPLAY=y
181
+CONFIG_DRM_ROCKCHIP=y
182
+CONFIG_DRM_MAXIM_MAX96745=y
183
+CONFIG_DRM_MAXIM_MAX96755F=y
184
+CONFIG_DRM_PANEL_MAXIM_DESERIALIZER=y
185
+CONFIG_DRM_ROHM_BU18XL82=y
186
+CONFIG_DRM_ROCKCHIP_DW_HDMI_QP=y
187
+CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y
188
+CONFIG_DRM_ROCKCHIP_DW_DP=y
189
+CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
190
+CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y
191
+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=y
192
+CONFIG_USE_TINY_PRINTF=y
193
+CONFIG_LIB_RAND=y
194
+CONFIG_SPL_TINY_MEMSET=y
195
+CONFIG_RSA=y
196
+CONFIG_SPL_RSA=y
197
+CONFIG_RSA_N_SIZE=0x200
198
+CONFIG_RSA_E_SIZE=0x10
199
+CONFIG_RSA_C_SIZE=0x20
200
+CONFIG_XBC=y
201
+CONFIG_LZ4=y
202
+CONFIG_LZMA=y
203
+CONFIG_ERRNO_STR=y
204
+# CONFIG_EFI_LOADER is not set
205
+CONFIG_AVB_LIBAVB=y
206
+CONFIG_AVB_LIBAVB_AB=y
207
+CONFIG_AVB_LIBAVB_ATX=y
208
+CONFIG_AVB_LIBAVB_USER=y
209
+CONFIG_RK_AVB_LIBAVB_USER=y
210
+CONFIG_OPTEE_CLIENT=y
211
+CONFIG_OPTEE_V2=y
212
+CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y
u-boot/configs/rk3588_defconfig
....@@ -12,8 +12,6 @@
1212 CONFIG_USING_KERNEL_DTB_V2=y
1313 CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
1414 CONFIG_ROCKCHIP_NEW_IDB=y
15
-CONFIG_LOADER_INI="RK3588MINIALL.ini"
16
-CONFIG_TRUST_INI="RK3588TRUST.ini"
1715 CONFIG_PSTORE=y
1816 CONFIG_SPL_SERIAL_SUPPORT=y
1917 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
....@@ -45,6 +43,7 @@
4543 CONFIG_SPL_MMC_WRITE=y
4644 CONFIG_SPL_MTD_SUPPORT=y
4745 CONFIG_SPL_ATF=y
46
+CONFIG_SPL_AB=y
4847 CONFIG_FASTBOOT_BUF_ADDR=0xc00800
4948 CONFIG_FASTBOOT_BUF_SIZE=0x07000000
5049 CONFIG_FASTBOOT_FLASH=y
....@@ -204,14 +203,14 @@
204203 CONFIG_DISPLAY=y
205204 CONFIG_DRM_ROCKCHIP=y
206205 CONFIG_DRM_MAXIM_MAX96745=y
207
-CONFIG_DRM_MAXIM_MAX96752F=y
208206 CONFIG_DRM_MAXIM_MAX96755F=y
209
-CONFIG_DRM_PANEL_MAXIM_DESERIALIZER=y
207
+CONFIG_DRM_PANEL_ROHM_BU18RL82=y
208
+CONFIG_DRM_PANEL_MAXIM_MAX96752F=y
210209 CONFIG_DRM_ROHM_BU18XL82=y
211210 CONFIG_DRM_ROCKCHIP_DW_HDMI_QP=y
212211 CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y
213
-CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
214212 CONFIG_DRM_ROCKCHIP_DW_DP=y
213
+CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
215214 CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y
216215 CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=y
217216 CONFIG_USE_TINY_PRINTF=y
u-boot/configs/rv1106-display.config
....@@ -48,7 +48,7 @@
4848 # CONFIG_REGULATOR_PWM is not set
4949 # CONFIG_REGULATOR_RK860X is not set
5050 CONFIG_ROCKCHIP_CUBIC_LUT_SIZE=0
51
-# CONFIG_ROCKCHIP_DRM_TVE is not set
51
+# CONFIG_DRM_ROCKCHIP_TVE is not set
5252 # CONFIG_ROCKCHIP_INNO_HDMI_PHY is not set
5353 # CONFIG_SPL_DM_REGULATOR is not set
5454 # CONFIG_VIDCONSOLE_AS_LCD is not set
u-boot/configs/rv1106-emmc-tb_defconfig
....@@ -3,7 +3,7 @@
33 CONFIG_SPL_LIBCOMMON_SUPPORT=y
44 CONFIG_SPL_LIBGENERIC_SUPPORT=y
55 CONFIG_SYS_MALLOC_F_LEN=0x100000
6
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_uboot.sh"
6
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_optee.sh"
77 CONFIG_ROCKCHIP_RV1106=y
88 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
99 CONFIG_ROCKCHIP_FIT_IMAGE=y
....@@ -38,12 +38,12 @@
3838 CONFIG_ANDROID_BOOTLOADER=y
3939 CONFIG_ANDROID_BOOT_IMAGE_HASH=y
4040 # CONFIG_SKIP_RELOCATE_UBOOT is not set
41
+CONFIG_SPL_ADC_SUPPORT=y
4142 CONFIG_SPL_BOARD_INIT=y
4243 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
4344 # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
4445 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
4546 CONFIG_SPL_MMC_WRITE=y
46
-CONFIG_SPL_OPTEE=y
4747 CONFIG_SPL_KERNEL_BOOT=y
4848 CONFIG_HUSH_PARSER=y
4949 # CONFIG_CMD_BDI is not set
....@@ -78,14 +78,19 @@
7878 CONFIG_SPL_REGMAP=y
7979 CONFIG_SYSCON=y
8080 CONFIG_SPL_SYSCON=y
81
-# CONFIG_ADC is not set
8281 # CONFIG_SARADC_ROCKCHIP is not set
82
+CONFIG_SARADC_ROCKCHIP_V2=y
8383 CONFIG_SPL_BLK_READ_PREPARE=y
8484 CONFIG_CLK=y
8585 CONFIG_SPL_CLK=y
8686 CONFIG_SPL_DM_CRYPTO=y
87
+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
8788 CONFIG_ROCKCHIP_GPIO=y
8889 # CONFIG_DM_I2C is not set
90
+CONFIG_SPL_INPUT=y
91
+CONFIG_DM_KEY=y
92
+CONFIG_ADC_KEY=y
93
+CONFIG_SPL_ADC_KEY=y
8994 CONFIG_SPL_MISC=y
9095 CONFIG_SPL_MISC_DECOMPRESS=y
9196 CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
u-boot/configs/rv1106-optee.config
....@@ -0,0 +1,5 @@
1
+CONFIG_BASE_DEFCONFIG="rv1106_defconfig"
2
+CONFIG_OPTEE_CLIENT=y
3
+CONFIG_OPTEE_V2=y
4
+CONFIG_SPL_FIT_IMAGE_KB=512
5
+CONFIG_SPL_OPTEE=y
u-boot/configs/rv1106-spi-nor-tb_defconfig
....@@ -3,7 +3,7 @@
33 CONFIG_SPL_LIBCOMMON_SUPPORT=y
44 CONFIG_SPL_LIBGENERIC_SUPPORT=y
55 CONFIG_SYS_MALLOC_F_LEN=0x80000
6
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_uboot.sh"
6
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_optee.sh"
77 CONFIG_ROCKCHIP_RV1106=y
88 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
99 CONFIG_ROCKCHIP_FIT_IMAGE=y
....@@ -38,13 +38,13 @@
3838 CONFIG_ANDROID_BOOTLOADER=y
3939 CONFIG_ANDROID_BOOT_IMAGE_HASH=y
4040 # CONFIG_SKIP_RELOCATE_UBOOT is not set
41
+CONFIG_SPL_ADC_SUPPORT=y
4142 CONFIG_SPL_BOARD_INIT=y
4243 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
4344 # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
4445 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
4546 CONFIG_SPL_MTD_SUPPORT=y
4647 CONFIG_MTD_BLK_U_BOOT_OFFS=0x200
47
-CONFIG_SPL_OPTEE=y
4848 CONFIG_SPL_KERNEL_BOOT=y
4949 CONFIG_HUSH_PARSER=y
5050 # CONFIG_CMD_BDI is not set
....@@ -81,8 +81,8 @@
8181 CONFIG_SPL_REGMAP=y
8282 CONFIG_SYSCON=y
8383 CONFIG_SPL_SYSCON=y
84
-# CONFIG_ADC is not set
8584 # CONFIG_SARADC_ROCKCHIP is not set
85
+CONFIG_SARADC_ROCKCHIP_V2=y
8686 CONFIG_SPL_BLK_READ_PREPARE=y
8787 CONFIG_CLK=y
8888 CONFIG_SPL_CLK=y
....@@ -90,6 +90,10 @@
9090 CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
9191 CONFIG_ROCKCHIP_GPIO=y
9292 # CONFIG_DM_I2C is not set
93
+CONFIG_SPL_INPUT=y
94
+CONFIG_DM_KEY=y
95
+CONFIG_ADC_KEY=y
96
+CONFIG_SPL_ADC_KEY=y
9397 CONFIG_SPL_MISC=y
9498 CONFIG_SPL_MISC_DECOMPRESS=y
9599 CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
....@@ -104,6 +108,7 @@
104108 CONFIG_SPI_FLASH_GIGADEVICE=y
105109 CONFIG_SPI_FLASH_MACRONIX=y
106110 CONFIG_SPI_FLASH_WINBOND=y
111
+CONFIG_SPI_FLASH_XMC=y
107112 CONFIG_SPI_FLASH_MTD=y
108113 CONFIG_PINCTRL=y
109114 # CONFIG_DM_REGULATOR is not set
u-boot/configs/rv1106-spi-nor_defconfig
....@@ -3,7 +3,7 @@
33 CONFIG_SPL_LIBCOMMON_SUPPORT=y
44 CONFIG_SPL_LIBGENERIC_SUPPORT=y
55 CONFIG_SYS_MALLOC_F_LEN=0x80000
6
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_uboot.sh"
6
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_optee.sh"
77 CONFIG_ROCKCHIP_RV1106=y
88 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
99 # CONFIG_ROCKCHIP_RESOURCE_IMAGE is not set
....@@ -30,7 +30,7 @@
3030 CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
3131 CONFIG_SPL_FIT_HW_CRYPTO=y
3232 # CONFIG_SPL_SYS_DCACHE_OFF is not set
33
-CONFIG_SPL_FIT_IMAGE_KB=128
33
+CONFIG_SPL_FIT_IMAGE_KB=192
3434 CONFIG_SPL_FIT_IMAGE_MULTIPLE=1
3535 CONFIG_BOOTDELAY=0
3636 CONFIG_SYS_CONSOLE_INFO_QUIET=y
....@@ -40,9 +40,7 @@
4040 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
4141 # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
4242 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
43
-CONFIG_SPL_MMC_WRITE=y
4443 CONFIG_SPL_MTD_SUPPORT=y
45
-CONFIG_SPL_OPTEE=y
4644 # CONFIG_CMD_BDI is not set
4745 # CONFIG_CMD_CONSOLE is not set
4846 CONFIG_CMD_BOOTZ=y
....@@ -63,12 +61,11 @@
6361 CONFIG_RANDOM_UUID=y
6462 # CONFIG_CMD_LOADB is not set
6563 # CONFIG_CMD_LOADS is not set
66
-CONFIG_CMD_PART=y
64
+CONFIG_CMD_MTD=y
6765 # CONFIG_CMD_ITEST is not set
6866 CONFIG_CMD_SCRIPT_UPDATE=y
6967 # CONFIG_CMD_SOURCE is not set
7068 # CONFIG_CMD_SETEXPR is not set
71
-CONFIG_CMD_TFTP_BOOTM=y
7269 CONFIG_CMD_TFTP_FLASH=y
7370 CONFIG_CMD_DHCP=y
7471 # CONFIG_CMD_NFS is not set
....@@ -154,5 +151,4 @@
154151 CONFIG_RSA_E_SIZE=0x10
155152 CONFIG_RSA_C_SIZE=0x20
156153 CONFIG_SPL_LZMA=y
157
-CONFIG_SPL_GZIP=y
158154 # CONFIG_EFI_LOADER is not set
u-boot/configs/rv1106-usb.config
....@@ -0,0 +1,17 @@
1
+CONFIG_DM_REGULATOR=y
2
+CONFIG_DM_REGULATOR_FIXED=y
3
+CONFIG_DM_REGULATOR_GPIO=y
4
+CONFIG_CMD_USB=y
5
+CONFIG_USB=y
6
+CONFIG_USB_XHCI_HCD=y
7
+CONFIG_USB_DWC3=y
8
+CONFIG_USB_DWC3_GENERIC=y
9
+CONFIG_USB_STORAGE=y
10
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
11
+# CONFIG_FASTBOOT is not set
12
+CONFIG_USB_DWC3_GADGET=y
13
+CONFIG_USB_GADGET=y
14
+CONFIG_USB_GADGET_DOWNLOAD=y
15
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
16
+CONFIG_USB_GADGET_PRODUCT_NUM=0x110c
17
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207
u-boot/configs/rv1106_defconfig
....@@ -4,7 +4,7 @@
44 CONFIG_SPL_LIBCOMMON_SUPPORT=y
55 CONFIG_SPL_LIBGENERIC_SUPPORT=y
66 CONFIG_SYS_MALLOC_F_LEN=0x80000
7
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_uboot.sh"
7
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_optee.sh"
88 CONFIG_ROCKCHIP_RV1106=y
99 CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
1010 CONFIG_ROCKCHIP_FIT_IMAGE=y
....@@ -41,7 +41,6 @@
4141 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
4242 CONFIG_SPL_MMC_WRITE=y
4343 CONFIG_SPL_MTD_SUPPORT=y
44
-CONFIG_SPL_OPTEE=y
4544 CONFIG_HUSH_PARSER=y
4645 # CONFIG_CMD_BDI is not set
4746 # CONFIG_CMD_CONSOLE is not set
u-boot/configs/rv1126-bat-spi-nor-tb.config
....@@ -2,6 +2,6 @@
22 # CONFIG_MMC is not set
33 CONFIG_BASE_DEFCONFIG="rv1126-spi-nor-tb.config"
44 CONFIG_DEFAULT_DEVICE_TREE="rv1126-bat-evb"
5
-CONFIG_LOADER_INI="RV1126MINIALL_LP4_EMMC_TB.ini"
5
+CONFIG_LOADER_INI="RV1126MINIALL_SPI_NOR_TB.ini"
66 CONFIG_OF_LIST="rv1126-bat-evb"
77 CONFIG_SPL_FIT_IMAGE_KB=320
u-boot/configs/rv1126-ipc.config
....@@ -4,9 +4,11 @@
44 # CONFIG_EFI_PARTITION is not set
55 CONFIG_ENVF_LIST="blkdevparts mtdparts sys_bootargs app reserved ipaddr serverip netmask gatewayip ethaddr"
66 CONFIG_ENVF=y
7
+CONFIG_ENV_PARTITION=y
78 CONFIG_LOADER_INI="RV1126MINIALL_IPC.ini"
89 # CONFIG_SPL_EFI_PARTITION is not set
910 CONFIG_SPL_ENVF=y
11
+CONFIG_SPL_ENV_PARTITION=y
1012 CONFIG_NETDEVICES=y
1113 CONFIG_GMAC_ROCKCHIP=y
1214 CONFIG_DWC_ETH_QOS=y
u-boot/configs/rv1126-spi-nor-tiny_defconfig
....@@ -126,6 +126,7 @@
126126 CONFIG_ROCKCHIP_SFC=y
127127 CONFIG_SYSRESET=y
128128 CONFIG_USE_TINY_PRINTF=y
129
+CONFIG_LIB_RAND=y
129130 CONFIG_SPL_TINY_MEMSET=y
130131 CONFIG_ERRNO_STR=y
131132 # CONFIG_EFI_LOADER is not set
u-boot/disk/Kconfig
....@@ -137,15 +137,15 @@
137137
138138 config ENV_PARTITION
139139 bool "Enable ENV partition table support"
140
- depends on PARTITIONS && ENVF
141
- default y
140
+ depends on PARTITIONS
141
+ default y if ENVF
142142 help
143143 Say Y here if you would like to use ENV partition table.
144144
145145 config SPL_ENV_PARTITION
146146 bool "Enable ENV partition table support in SPL"
147
- depends on SPL && PARTITIONS && SPL_ENVF
148
- default y
147
+ depends on SPL && PARTITIONS
148
+ default y if SPL_ENVF
149149 help
150150 Say Y here if you would like to use ENV partition table in SPL.
151151
u-boot/disk/part.c
....@@ -684,8 +684,9 @@
684684 disk_partition_t *info,
685685 bool strict)
686686 {
687
+ __maybe_unused char name_slot[32] = {0};
687688 struct part_driver *part_drv;
688
- char name_slot[32] = {0};
689
+ const char *full_name = name;
689690 int none_slot_try = 1;
690691 int ret, i;
691692
....@@ -695,37 +696,35 @@
695696
696697 if (strict) {
697698 none_slot_try = 0;
698
- strcpy(name_slot, name);
699699 goto lookup;
700700 }
701701
702
+ /* 1. Query partition with A/B slot suffix */
702703 #if defined(CONFIG_ANDROID_AB) || defined(CONFIG_SPL_AB)
703
- char *name_suffix = (char *)name + strlen(name) - 2;
704
+ char *slot = (char *)name + strlen(name) - 2;
704705
705
- /* Fix can not find partition with suffix "_a" & "_b". If with them, clear */
706
- if (!memcmp(name_suffix, "_a", strlen("_a")) ||
707
- !memcmp(name_suffix, "_b", strlen("_b")))
708
- memset(name_suffix, 0, 2);
706
+ if (!strcmp(slot, "_a") || !strcmp(slot, "_b"))
707
+ goto lookup;
709708 #endif
710709 #if defined(CONFIG_ANDROID_AB) && !defined(CONFIG_SPL_BUILD)
711
- /* 1. Query partition with A/B slot suffix */
712710 if (rk_avb_append_part_slot(name, name_slot))
713711 return -1;
712
+ full_name = name_slot;
714713 #elif defined(CONFIG_SPL_AB) && defined(CONFIG_SPL_BUILD)
715714 if (spl_ab_append_part_slot(dev_desc, name, name_slot))
716715 return -1;
717
-#else
718
- strcpy(name_slot, name);
716
+ full_name = name_slot;
719717 #endif
718
+
720719 lookup:
721
- debug("## Query partition(%d): %s\n", none_slot_try, name_slot);
720
+ debug("## Query partition(%d): %s\n", none_slot_try, full_name);
722721 for (i = 1; i < part_drv->max_entries; i++) {
723722 ret = part_drv->get_info(dev_desc, i, info);
724723 if (ret != 0) {
725724 /* no more entries in table */
726725 break;
727726 }
728
- if (strcmp(name_slot, (const char *)info->name) == 0) {
727
+ if (strcmp(full_name, (const char *)info->name) == 0) {
729728 /* matched */
730729 return i;
731730 }
....@@ -734,7 +733,7 @@
734733 /* 2. Query partition without A/B slot suffix if above failed */
735734 if (none_slot_try) {
736735 none_slot_try = 0;
737
- strcpy(name_slot, name);
736
+ full_name = name;
738737 goto lookup;
739738 }
740739
u-boot/disk/part_efi.c
....@@ -368,7 +368,7 @@
368368 if (gpt_pte[i - 1].ending_lba <= (dev_desc->lba - 0x22))
369369 return;
370370 /* The last partition size need align to 4KB, here align to 32KB. */
371
- gpt_pte[i - 1].ending_lba = dev_desc->lba - 0x40;
371
+ gpt_pte[i - 1].ending_lba = dev_desc->lba - 0x41;
372372 calc_crc32 = efi_crc32((const unsigned char *)gpt_pte,
373373 le32_to_cpu(gpt_head->num_partition_entries) *
374374 le32_to_cpu(gpt_head->sizeof_partition_entry));
....@@ -963,7 +963,8 @@
963963 dev_desc->blksz);
964964
965965 if ((le64_to_cpu(gpt_h->alternate_lba) + 1)
966
- != cpu_to_le64(dev_desc->lba)) {
966
+ != cpu_to_le64(dev_desc->lba) &&
967
+ le64_to_cpu(gpt_h->last_usable_lba) != FACTORY_UNKNOWN_LBA) {
967968 printf("%s: failed checking '%s'\n", __func__,
968969 "invalid GPT Disk Size");
969970 return -1;
u-boot/disk/part_env.c
....@@ -82,14 +82,7 @@
8282 #if CONFIG_IS_ENABLED(ENVF)
8383 parts_list = envf_get_part_table(dev_desc);
8484 #else
85
- const char *parts_prefix[] = { "mtdparts", "blkdevparts", };
86
- int i;
87
-
88
- for (i = 0; i < ARRAY_SIZE(parts_prefix); i++) {
89
- parts_list = env_get(parts_prefix[i]);
90
- if (parts_list)
91
- break;
92
- }
85
+ parts_list = ENV_PARTITIONS;
9386 #endif
9487 if (!parts_list)
9588 return -EINVAL;
u-boot/drivers/Kconfig
....@@ -102,6 +102,8 @@
102102
103103 source "drivers/usb/Kconfig"
104104
105
+source "drivers/ufs/Kconfig"
106
+
105107 source "drivers/video/Kconfig"
106108
107109 source "drivers/watchdog/Kconfig"
u-boot/drivers/Makefile
....@@ -20,6 +20,7 @@
2020 obj-$(CONFIG_$(SPL_TPL_)SPI_SUPPORT) += spi/
2121 obj-$(CONFIG_$(SPL_TPL_)TIMER) += timer/
2222 obj-$(CONFIG_$(SPL_TPL_)IRQ) += irq/
23
+obj-$(CONFIG_$(SPL_TPL_)DM_VIDEO) += video/
2324
2425 ifndef CONFIG_TPL_BUILD
2526 ifdef CONFIG_SPL_BUILD
....@@ -101,7 +102,6 @@
101102 obj-y += spmi/
102103 obj-y += sysreset/
103104 obj-y += tpm/
104
-obj-y += video/
105105 obj-y += watchdog/
106106 obj-$(CONFIG_QE) += qe/
107107 obj-$(CONFIG_U_QE) += qe/
....@@ -113,6 +113,7 @@
113113 obj-y += soc/
114114 obj-$(CONFIG_REMOTEPROC) += remoteproc/
115115 obj-y += thermal/
116
+obj-y += ufs/
116117
117118 obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
118119 endif
u-boot/drivers/adc/rockchip-saradc-v2.c
....@@ -181,6 +181,9 @@
181181 if (IS_ERR_VALUE(ret))
182182 return ret;
183183
184
+ /* Wait until pll stable */
185
+ mdelay(5);
186
+
184187 priv->active_channel = -1;
185188
186189 return 0;
....@@ -220,9 +223,35 @@
220223 .clk_rate = 1000000,
221224 };
222225
226
+static const struct rockchip_saradc_data rk3562_saradc_data = {
227
+ .num_bits = 10,
228
+ .num_channels = 8,
229
+ .clk_rate = 1000000,
230
+};
231
+
232
+static const struct rockchip_saradc_data rk1106_saradc_data = {
233
+ .num_bits = 10,
234
+ .num_channels = 2,
235
+ .clk_rate = 1000000,
236
+};
237
+
223238 static const struct udevice_id rockchip_saradc_ids[] = {
224
- { .compatible = "rockchip,rk3588-saradc",
225
- .data = (ulong)&rk3588_saradc_data },
239
+ {
240
+ .compatible = "rockchip,rk3588-saradc",
241
+ .data = (ulong)&rk3588_saradc_data
242
+ },
243
+ {
244
+ .compatible = "rockchip,rk3528-saradc",
245
+ .data = (ulong)&rk3588_saradc_data
246
+ },
247
+ {
248
+ .compatible = "rockchip,rk3562-saradc",
249
+ .data = (ulong)&rk3562_saradc_data
250
+ },
251
+ {
252
+ .compatible = "rockchip,rv1106-saradc",
253
+ .data = (ulong)&rk1106_saradc_data
254
+ },
226255 { }
227256 };
228257
u-boot/drivers/clk/clk-uclass.c
....@@ -237,10 +237,11 @@
237237 {
238238 int ret;
239239
240
+#ifndef CONFIG_SPL_BUILD
240241 /* If this is running pre-reloc state, don't take any action. */
241242 if (!(gd->flags & GD_FLG_RELOC))
242243 return 0;
243
-
244
+#endif
244245 debug("%s(%s)\n", __func__, dev_read_name(dev));
245246
246247 ret = clk_set_default_parents(dev);
u-boot/drivers/clk/rockchip/Makefile
....@@ -17,6 +17,8 @@
1717 obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
1818 obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
1919 obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
20
+obj-$(CONFIG_ROCKCHIP_RK3528) += clk_rk3528.o
21
+obj-$(CONFIG_ROCKCHIP_RK3562) += clk_rk3562.o
2022 obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
2123 obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o
2224 obj-$(CONFIG_ROCKCHIP_RV1106) += clk_rv1106.o
u-boot/drivers/clk/rockchip/clk_pll.c
....@@ -267,9 +267,11 @@
267267 * When power on or changing PLL setting,
268268 * we must force PLL into slow mode to ensure output stable clock.
269269 */
270
- rk_clrsetreg(base + pll->mode_offset,
271
- pll->mode_mask << pll->mode_shift,
272
- RKCLK_PLL_MODE_SLOW << pll->mode_shift);
270
+ if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
271
+ rk_clrsetreg(base + pll->mode_offset,
272
+ pll->mode_mask << pll->mode_shift,
273
+ RKCLK_PLL_MODE_SLOW << pll->mode_shift);
274
+ }
273275
274276 /* Power down */
275277 rk_setreg(base + pll->con_offset + 0x4,
....@@ -308,8 +310,11 @@
308310 if (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift)))
309311 printf("%s: wait pll lock timeout! pll_id=%ld\n", __func__, pll_id);
310312
311
- rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
312
- RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
313
+ if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
314
+ rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
315
+ RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
316
+ }
317
+
313318 debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",
314319 pll, readl(base + pll->con_offset),
315320 readl(base + pll->con_offset + 0x4),
....@@ -325,12 +330,18 @@
325330 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac;
326331 u32 con = 0, shift, mask;
327332 ulong rate;
333
+ int mode;
328334
329335 con = readl(base + pll->mode_offset);
330336 shift = pll->mode_shift;
331337 mask = pll->mode_mask << shift;
332338
333
- switch ((con & mask) >> shift) {
339
+ if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE))
340
+ mode = (con & mask) >> shift;
341
+ else
342
+ mode = RKCLK_PLL_MODE_NORMAL;
343
+
344
+ switch (mode) {
334345 case RKCLK_PLL_MODE_SLOW:
335346 return OSC_HZ;
336347 case RKCLK_PLL_MODE_NORMAL:
u-boot/drivers/clk/rockchip/clk_rk3399.c
....@@ -773,6 +773,10 @@
773773 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
774774 ACLK_VOP_PLL_SEL_GPLL << ACLK_VOP_PLL_SEL_SHIFT |
775775 (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
776
+ rk_clrsetreg(&cru->clksel_con[42],
777
+ ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
778
+ ACLK_VOP_PLL_SEL_GPLL << ACLK_VOP_PLL_SEL_SHIFT |
779
+ (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
776780
777781 if (readl(dclkreg_addr) & DCLK_VOP_PLL_SEL_MASK) {
778782 if (pll_para_config(hz, &cpll_config))
u-boot/drivers/clk/rockchip/clk_rk3528.c
....@@ -0,0 +1,2145 @@
1
+// SPDX-License-Identifier: GPL-2.0
2
+/*
3
+ * Copyright (c) 2022 Fuzhou Rockchip Electronics Co., Ltd
4
+ * Author: Joseph Chen <chenjh@rock-chips.com>
5
+ */
6
+
7
+#include <common.h>
8
+#include <clk-uclass.h>
9
+#include <dm.h>
10
+#include <syscon.h>
11
+#include <asm/arch/clock.h>
12
+#include <asm/arch/cru_rk3528.h>
13
+#include <asm/arch/grf_rk3528.h>
14
+#include <asm/arch/hardware.h>
15
+#include <asm/io.h>
16
+#include <dm/lists.h>
17
+#include <dt-bindings/clock/rk3528-cru.h>
18
+
19
+DECLARE_GLOBAL_DATA_PTR;
20
+
21
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
22
+
23
+/*
24
+ * PLL attention.
25
+ *
26
+ * [FRAC PLL]: GPLL, PPLL, DPLL
27
+ * - frac mode: refdiv can be 1 or 2 only
28
+ * - int mode: refdiv has no special limit
29
+ * - VCO range: [950, 3800] MHZ
30
+ *
31
+ * [INT PLL]: CPLL, APLL
32
+ * - int mode: refdiv can be 1 or 2 only
33
+ * - VCO range: [475, 1900] MHZ
34
+ *
35
+ * [PPLL]: normal mode only.
36
+ *
37
+ */
38
+static struct rockchip_pll_rate_table rk3528_pll_rates[] = {
39
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
40
+ RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
41
+ RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
42
+ RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
43
+ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
44
+ RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
45
+ RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
46
+ RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
47
+ RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
48
+ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */
49
+ RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0),
50
+ RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0),
51
+ RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */
52
+ RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */
53
+ RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0),
54
+ RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
55
+ RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
56
+ RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
57
+ RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
58
+ RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
59
+ RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
60
+ RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
61
+ RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0),
62
+ { /* sentinel */ },
63
+};
64
+
65
+static struct rockchip_pll_clock rk3528_pll_clks[] = {
66
+ [APLL] = PLL(pll_rk3328, PLL_APLL, RK3528_PLL_CON(0),
67
+ RK3528_MODE_CON, 0, 10, 0, rk3528_pll_rates),
68
+
69
+ [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3528_PLL_CON(8),
70
+ RK3528_MODE_CON, 2, 10, 0, rk3528_pll_rates),
71
+
72
+ [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3528_PLL_CON(24),
73
+ RK3528_MODE_CON, 4, 10, 0, rk3528_pll_rates),
74
+
75
+ [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3528_PCIE_PLL_CON(32),
76
+ RK3528_MODE_CON, 6, 10, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates),
77
+
78
+ [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3528_DDRPHY_PLL_CON(16),
79
+ RK3528_DDRPHY_MODE_CON, 0, 10, 0, rk3528_pll_rates),
80
+};
81
+
82
+#define RK3528_CPUCLK_RATE(_rate, _aclk_m_core, _pclk_dbg) \
83
+{ \
84
+ .rate = _rate##U, \
85
+ .aclk_div = (_aclk_m_core), \
86
+ .pclk_div = (_pclk_dbg), \
87
+}
88
+
89
+/* sign-off: _aclk_m_core: 550M, _pclk_dbg: 137.5M, */
90
+static struct rockchip_cpu_rate_table rk3528_cpu_rates[] = {
91
+ RK3528_CPUCLK_RATE(1896000000, 1, 13),
92
+ RK3528_CPUCLK_RATE(1800000000, 1, 12),
93
+ RK3528_CPUCLK_RATE(1704000000, 1, 11),
94
+ RK3528_CPUCLK_RATE(1608000000, 1, 11),
95
+ RK3528_CPUCLK_RATE(1512000000, 1, 11),
96
+ RK3528_CPUCLK_RATE(1416000000, 1, 9),
97
+ RK3528_CPUCLK_RATE(1296000000, 1, 8),
98
+ RK3528_CPUCLK_RATE(1200000000, 1, 8),
99
+ RK3528_CPUCLK_RATE(1188000000, 1, 8),
100
+ RK3528_CPUCLK_RATE(1092000000, 1, 7),
101
+ RK3528_CPUCLK_RATE(1008000000, 1, 6),
102
+ RK3528_CPUCLK_RATE(1000000000, 1, 6),
103
+ RK3528_CPUCLK_RATE(996000000, 1, 6),
104
+ RK3528_CPUCLK_RATE(960000000, 1, 6),
105
+ RK3528_CPUCLK_RATE(912000000, 1, 6),
106
+ RK3528_CPUCLK_RATE(816000000, 1, 5),
107
+ RK3528_CPUCLK_RATE(600000000, 1, 3),
108
+ RK3528_CPUCLK_RATE(594000000, 1, 3),
109
+ RK3528_CPUCLK_RATE(408000000, 1, 2),
110
+ RK3528_CPUCLK_RATE(312000000, 1, 2),
111
+ RK3528_CPUCLK_RATE(216000000, 1, 1),
112
+ RK3528_CPUCLK_RATE(96000000, 1, 0),
113
+};
114
+
115
+#ifndef CONFIG_SPL_BUILD
116
+#define RK3528_CLK_DUMP(_id, _name) \
117
+{ \
118
+ .id = _id, \
119
+ .name = _name, \
120
+}
121
+
122
+static const struct rk3528_clk_info clks_dump[] = {
123
+ RK3528_CLK_DUMP(PLL_APLL, "apll"),
124
+ RK3528_CLK_DUMP(PLL_GPLL, "gpll"),
125
+ RK3528_CLK_DUMP(PLL_CPLL, "cpll"),
126
+ RK3528_CLK_DUMP(PLL_DPLL, "dpll"),
127
+ RK3528_CLK_DUMP(PLL_PPLL, "ppll"),
128
+ RK3528_CLK_DUMP(CLK_MATRIX_50M_SRC, "clk_50m"),
129
+ RK3528_CLK_DUMP(CLK_MATRIX_100M_SRC, "clk_100m"),
130
+ RK3528_CLK_DUMP(CLK_MATRIX_150M_SRC, "clk_150m"),
131
+ RK3528_CLK_DUMP(CLK_MATRIX_200M_SRC, "clk_200m"),
132
+ RK3528_CLK_DUMP(CLK_MATRIX_250M_SRC, "clk_250m"),
133
+ RK3528_CLK_DUMP(CLK_MATRIX_300M_SRC, "clk_300m"),
134
+ RK3528_CLK_DUMP(CLK_MATRIX_339M_SRC, "clk_339m"),
135
+ RK3528_CLK_DUMP(CLK_MATRIX_400M_SRC, "clk_400m"),
136
+ RK3528_CLK_DUMP(CLK_MATRIX_500M_SRC, "clk_500m"),
137
+ RK3528_CLK_DUMP(CLK_MATRIX_600M_SRC, "clk_600m"),
138
+ RK3528_CLK_DUMP(CLK_PPLL_50M_MATRIX, "clk_ppll_50m"),
139
+ RK3528_CLK_DUMP(CLK_PPLL_100M_MATRIX, "clk_ppll_100m"),
140
+ RK3528_CLK_DUMP(CLK_PPLL_125M_MATRIX, "clk_ppll_125m"),
141
+};
142
+#endif
143
+
144
+/*
145
+ *
146
+ * rational_best_approximation(31415, 10000,
147
+ * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
148
+ *
149
+ * you may look at given_numerator as a fixed point number,
150
+ * with the fractional part size described in given_denominator.
151
+ *
152
+ * for theoretical background, see:
153
+ * http://en.wikipedia.org/wiki/Continued_fraction
154
+ */
155
+static void rational_best_approximation(unsigned long given_numerator,
156
+ unsigned long given_denominator,
157
+ unsigned long max_numerator,
158
+ unsigned long max_denominator,
159
+ unsigned long *best_numerator,
160
+ unsigned long *best_denominator)
161
+{
162
+ unsigned long n, d, n0, d0, n1, d1;
163
+
164
+ n = given_numerator;
165
+ d = given_denominator;
166
+ n0 = 0;
167
+ d1 = 0;
168
+ n1 = 1;
169
+ d0 = 1;
170
+ for (;;) {
171
+ unsigned long t, a;
172
+
173
+ if (n1 > max_numerator || d1 > max_denominator) {
174
+ n1 = n0;
175
+ d1 = d0;
176
+ break;
177
+ }
178
+ if (d == 0)
179
+ break;
180
+ t = d;
181
+ a = n / d;
182
+ d = n % d;
183
+ n = t;
184
+ t = n0 + a * n1;
185
+ n0 = n1;
186
+ n1 = t;
187
+ t = d0 + a * d1;
188
+ d0 = d1;
189
+ d1 = t;
190
+ }
191
+ *best_numerator = n1;
192
+ *best_denominator = d1;
193
+}
194
+
195
+static int rk3528_armclk_set_clk(struct rk3528_clk_priv *priv, ulong new_rate)
196
+{
197
+ const struct rockchip_cpu_rate_table *rate;
198
+ struct rk3528_cru *cru = priv->cru;
199
+ ulong old_rate;
200
+
201
+ rate = rockchip_get_cpu_settings(rk3528_cpu_rates, new_rate);
202
+ if (!rate) {
203
+ printf("%s unsupported rate\n", __func__);
204
+ return -EINVAL;
205
+ }
206
+
207
+ /*
208
+ * set up dependent divisors for DBG and ACLK clocks.
209
+ */
210
+ old_rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, APLL);
211
+ if (old_rate > new_rate) {
212
+ if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL],
213
+ priv->cru, APLL, new_rate))
214
+ return -EINVAL;
215
+
216
+ rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
217
+ rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT);
218
+
219
+ rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
220
+ rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT);
221
+ } else if (old_rate < new_rate) {
222
+ rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
223
+ rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT);
224
+
225
+ rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
226
+ rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT);
227
+
228
+ if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL],
229
+ priv->cru, APLL, new_rate))
230
+ return -EINVAL;
231
+ }
232
+
233
+ return 0;
234
+}
235
+
236
+static ulong rk3528_ppll_matrix_get_rate(struct rk3528_clk_priv *priv,
237
+ ulong clk_id)
238
+{
239
+ struct rk3528_cru *cru = priv->cru;
240
+ u32 div, mask, shift;
241
+ void *reg;
242
+
243
+ switch (clk_id) {
244
+ case CLK_PPLL_50M_MATRIX:
245
+ case CLK_GMAC1_RMII_VPU:
246
+ mask = PCIE_CLK_MATRIX_50M_SRC_DIV_MASK;
247
+ shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT;
248
+ reg = &cru->pcieclksel_con[1];
249
+ break;
250
+
251
+ case CLK_PPLL_100M_MATRIX:
252
+ mask = PCIE_CLK_MATRIX_100M_SRC_DIV_MASK;
253
+ shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT;
254
+ reg = &cru->pcieclksel_con[1];
255
+ break;
256
+
257
+ case CLK_PPLL_125M_MATRIX:
258
+ case CLK_GMAC1_SRC_VPU:
259
+ mask = CLK_MATRIX_125M_SRC_DIV_MASK;
260
+ shift = CLK_MATRIX_125M_SRC_DIV_SHIFT;
261
+ reg = &cru->clksel_con[60];
262
+ break;
263
+
264
+ case CLK_GMAC1_VPU_25M:
265
+ mask = CLK_MATRIX_25M_SRC_DIV_MASK;
266
+ shift = CLK_MATRIX_25M_SRC_DIV_SHIFT;
267
+ reg = &cru->clksel_con[60];
268
+ break;
269
+ default:
270
+ return -ENOENT;
271
+ }
272
+
273
+ div = (readl(reg) & mask) >> shift;
274
+
275
+ return DIV_TO_RATE(priv->ppll_hz, div);
276
+}
277
+
278
+static ulong rk3528_ppll_matrix_set_rate(struct rk3528_clk_priv *priv,
279
+ ulong clk_id, ulong rate)
280
+{
281
+ struct rk3528_cru *cru = priv->cru;
282
+ u32 id, div, mask, shift;
283
+ u8 is_pciecru = 0;
284
+
285
+ switch (clk_id) {
286
+ case CLK_PPLL_50M_MATRIX:
287
+ id = 1;
288
+ mask = PCIE_CLK_MATRIX_50M_SRC_DIV_MASK;
289
+ shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT;
290
+ is_pciecru = 1;
291
+ break;
292
+
293
+ case CLK_PPLL_100M_MATRIX:
294
+ id = 1;
295
+ mask = PCIE_CLK_MATRIX_100M_SRC_DIV_MASK;
296
+ shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT;
297
+ is_pciecru = 1;
298
+ break;
299
+
300
+ case CLK_PPLL_125M_MATRIX:
301
+ id = 60;
302
+ mask = CLK_MATRIX_125M_SRC_DIV_MASK;
303
+ shift = CLK_MATRIX_125M_SRC_DIV_SHIFT;
304
+ break;
305
+ case CLK_GMAC1_VPU_25M:
306
+ id = 60;
307
+ mask = CLK_MATRIX_25M_SRC_DIV_MASK;
308
+ shift = CLK_MATRIX_25M_SRC_DIV_SHIFT;
309
+ break;
310
+ default:
311
+ return -ENOENT;
312
+ }
313
+
314
+ div = DIV_ROUND_UP(priv->ppll_hz, rate);
315
+ if (is_pciecru)
316
+ rk_clrsetreg(&cru->pcieclksel_con[id], mask, (div - 1) << shift);
317
+ else
318
+ rk_clrsetreg(&cru->clksel_con[id], mask, (div - 1) << shift);
319
+
320
+ return rk3528_ppll_matrix_get_rate(priv, clk_id);
321
+}
322
+
323
+static ulong rk3528_cgpll_matrix_get_rate(struct rk3528_clk_priv *priv,
324
+ ulong clk_id)
325
+{
326
+ struct rk3528_cru *cru = priv->cru;
327
+ u32 sel, div, mask, shift, con;
328
+ u32 sel_mask = 0, sel_shift;
329
+ u8 is_gpll_parent = 1;
330
+ u8 is_halfdiv = 0;
331
+ ulong prate;
332
+
333
+ switch (clk_id) {
334
+ case CLK_MATRIX_50M_SRC:
335
+ con = 0;
336
+ mask = CLK_MATRIX_50M_SRC_DIV_MASK;
337
+ shift = CLK_MATRIX_50M_SRC_DIV_SHIFT;
338
+ is_gpll_parent = 0;
339
+ break;
340
+
341
+ case CLK_MATRIX_100M_SRC:
342
+ con = 0;
343
+ mask = CLK_MATRIX_100M_SRC_DIV_MASK;
344
+ shift = CLK_MATRIX_100M_SRC_DIV_SHIFT;
345
+ is_gpll_parent = 0;
346
+ break;
347
+
348
+ case CLK_MATRIX_150M_SRC:
349
+ con = 1;
350
+ mask = CLK_MATRIX_150M_SRC_DIV_MASK;
351
+ shift = CLK_MATRIX_150M_SRC_DIV_SHIFT;
352
+ break;
353
+
354
+ case CLK_MATRIX_200M_SRC:
355
+ con = 1;
356
+ mask = CLK_MATRIX_200M_SRC_DIV_MASK;
357
+ shift = CLK_MATRIX_200M_SRC_DIV_SHIFT;
358
+ break;
359
+
360
+ case CLK_MATRIX_250M_SRC:
361
+ con = 1;
362
+ mask = CLK_MATRIX_250M_SRC_DIV_MASK;
363
+ shift = CLK_MATRIX_250M_SRC_DIV_SHIFT;
364
+ sel_mask = CLK_MATRIX_250M_SRC_SEL_MASK;
365
+ sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT;
366
+ break;
367
+
368
+ case CLK_MATRIX_300M_SRC:
369
+ con = 2;
370
+ mask = CLK_MATRIX_300M_SRC_DIV_MASK;
371
+ shift = CLK_MATRIX_300M_SRC_DIV_SHIFT;
372
+ break;
373
+
374
+ case CLK_MATRIX_339M_SRC:
375
+ con = 2;
376
+ mask = CLK_MATRIX_339M_SRC_DIV_MASK;
377
+ shift = CLK_MATRIX_339M_SRC_DIV_SHIFT;
378
+ is_halfdiv = 1;
379
+ break;
380
+
381
+ case CLK_MATRIX_400M_SRC:
382
+ con = 2;
383
+ mask = CLK_MATRIX_400M_SRC_DIV_MASK;
384
+ shift = CLK_MATRIX_400M_SRC_DIV_SHIFT;
385
+ break;
386
+
387
+ case CLK_MATRIX_500M_SRC:
388
+ con = 3;
389
+ mask = CLK_MATRIX_500M_SRC_DIV_MASK;
390
+ shift = CLK_MATRIX_500M_SRC_DIV_SHIFT;
391
+ sel_mask = CLK_MATRIX_500M_SRC_SEL_MASK;
392
+ sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT;
393
+ break;
394
+
395
+ case CLK_MATRIX_600M_SRC:
396
+ con = 4;
397
+ mask = CLK_MATRIX_600M_SRC_DIV_MASK;
398
+ shift = CLK_MATRIX_600M_SRC_DIV_SHIFT;
399
+ break;
400
+
401
+ case ACLK_BUS_VOPGL_ROOT:
402
+ case ACLK_BUS_VOPGL_BIU:
403
+ con = 43;
404
+ mask = ACLK_BUS_VOPGL_ROOT_DIV_MASK;
405
+ shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT;
406
+ break;
407
+
408
+ default:
409
+ return -ENOENT;
410
+ }
411
+
412
+ if (sel_mask) {
413
+ sel = (readl(&cru->clksel_con[con]) & sel_mask) >> sel_shift;
414
+ if (sel == CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX) // TODO
415
+ prate = priv->gpll_hz;
416
+ else
417
+ prate = priv->cpll_hz;
418
+ } else {
419
+ if (is_gpll_parent)
420
+ prate = priv->gpll_hz;
421
+ else
422
+ prate = priv->cpll_hz;
423
+ }
424
+
425
+ div = (readl(&cru->clksel_con[con]) & mask) >> shift;
426
+
427
+ /* NOTE: '-1' to balance the DIV_TO_RATE() 'div+1' */
428
+ return is_halfdiv ? DIV_TO_RATE(prate * 2, (3 + 2 * div) - 1) : DIV_TO_RATE(prate, div);
429
+}
430
+
431
+static ulong rk3528_cgpll_matrix_set_rate(struct rk3528_clk_priv *priv,
432
+ ulong clk_id, ulong rate)
433
+{
434
+ struct rk3528_cru *cru = priv->cru;
435
+ u32 sel, div, mask, shift, con;
436
+ u32 sel_mask = 0, sel_shift;
437
+ u8 is_gpll_parent = 1;
438
+ u8 is_halfdiv = 0;
439
+ ulong prate = 0;
440
+
441
+ switch (clk_id) {
442
+ case CLK_MATRIX_50M_SRC:
443
+ con = 0;
444
+ mask = CLK_MATRIX_50M_SRC_DIV_MASK;
445
+ shift = CLK_MATRIX_50M_SRC_DIV_SHIFT;
446
+ is_gpll_parent = 0;
447
+ break;
448
+
449
+ case CLK_MATRIX_100M_SRC:
450
+ con = 0;
451
+ mask = CLK_MATRIX_100M_SRC_DIV_MASK;
452
+ shift = CLK_MATRIX_100M_SRC_DIV_SHIFT;
453
+ is_gpll_parent = 0;
454
+ break;
455
+
456
+ case CLK_MATRIX_150M_SRC:
457
+ con = 1;
458
+ mask = CLK_MATRIX_150M_SRC_DIV_MASK;
459
+ shift = CLK_MATRIX_150M_SRC_DIV_SHIFT;
460
+ break;
461
+
462
+ case CLK_MATRIX_200M_SRC:
463
+ con = 1;
464
+ mask = CLK_MATRIX_200M_SRC_DIV_MASK;
465
+ shift = CLK_MATRIX_200M_SRC_DIV_SHIFT;
466
+ break;
467
+
468
+ case CLK_MATRIX_250M_SRC:
469
+ con = 1;
470
+ mask = CLK_MATRIX_250M_SRC_DIV_MASK;
471
+ shift = CLK_MATRIX_250M_SRC_DIV_SHIFT;
472
+ sel_mask = CLK_MATRIX_250M_SRC_SEL_MASK;
473
+ sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT;
474
+ break;
475
+
476
+ case CLK_MATRIX_300M_SRC:
477
+ con = 2;
478
+ mask = CLK_MATRIX_300M_SRC_DIV_MASK;
479
+ shift = CLK_MATRIX_300M_SRC_DIV_SHIFT;
480
+ break;
481
+
482
+ case CLK_MATRIX_339M_SRC:
483
+ con = 2;
484
+ mask = CLK_MATRIX_339M_SRC_DIV_MASK;
485
+ shift = CLK_MATRIX_339M_SRC_DIV_SHIFT;
486
+ is_halfdiv = 1;
487
+ break;
488
+
489
+ case CLK_MATRIX_400M_SRC:
490
+ con = 2;
491
+ mask = CLK_MATRIX_400M_SRC_DIV_MASK;
492
+ shift = CLK_MATRIX_400M_SRC_DIV_SHIFT;
493
+ break;
494
+
495
+ case CLK_MATRIX_500M_SRC:
496
+ con = 3;
497
+ mask = CLK_MATRIX_500M_SRC_DIV_MASK;
498
+ shift = CLK_MATRIX_500M_SRC_DIV_SHIFT;
499
+ sel_mask = CLK_MATRIX_500M_SRC_SEL_MASK;
500
+ sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT;
501
+ break;
502
+
503
+ case CLK_MATRIX_600M_SRC:
504
+ con = 4;
505
+ mask = CLK_MATRIX_600M_SRC_DIV_MASK;
506
+ shift = CLK_MATRIX_600M_SRC_DIV_SHIFT;
507
+ break;
508
+
509
+ case ACLK_BUS_VOPGL_ROOT:
510
+ case ACLK_BUS_VOPGL_BIU:
511
+ con = 43;
512
+ mask = ACLK_BUS_VOPGL_ROOT_DIV_MASK;
513
+ shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT;
514
+ break;
515
+
516
+ default:
517
+ return -ENOENT;
518
+ }
519
+
520
+ if (sel_mask) {
521
+ if (priv->gpll_hz % rate == 0) {
522
+ sel = CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX; // TODO
523
+ prate = priv->gpll_hz;
524
+ } else {
525
+ sel = CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX;
526
+ prate = priv->cpll_hz;
527
+ }
528
+ } else {
529
+ if (is_gpll_parent)
530
+ prate = priv->gpll_hz;
531
+ else
532
+ prate = priv->cpll_hz;
533
+ }
534
+
535
+ if (is_halfdiv)
536
+ /* NOTE: '+1' to balance the following rk_clrsetreg() 'div-1' */
537
+ div = DIV_ROUND_UP((prate * 2) - (3 * rate), 2 * rate) + 1;
538
+ else
539
+ div = DIV_ROUND_UP(prate, rate);
540
+
541
+ rk_clrsetreg(&cru->clksel_con[con], mask, (div - 1) << shift);
542
+ if (sel_mask)
543
+ rk_clrsetreg(&cru->clksel_con[con], sel_mask, sel << sel_shift);
544
+
545
+ return rk3528_cgpll_matrix_get_rate(priv, clk_id);
546
+}
547
+
548
+static ulong rk3528_i2c_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
549
+{
550
+ struct rk3528_cru *cru = priv->cru;
551
+ u32 id, sel, con, mask, shift;
552
+ u8 is_pmucru = 0;
553
+ ulong rate;
554
+
555
+ switch (clk_id) {
556
+ case CLK_I2C0:
557
+ id = 79;
558
+ mask = CLK_I2C0_SEL_MASK;
559
+ shift = CLK_I2C0_SEL_SHIFT;
560
+ break;
561
+
562
+ case CLK_I2C1:
563
+ id = 79;
564
+ mask = CLK_I2C1_SEL_MASK;
565
+ shift = CLK_I2C1_SEL_SHIFT;
566
+ break;
567
+
568
+ case CLK_I2C2:
569
+ id = 0;
570
+ mask = CLK_I2C2_SEL_MASK;
571
+ shift = CLK_I2C2_SEL_SHIFT;
572
+ is_pmucru = 1;
573
+ break;
574
+
575
+ case CLK_I2C3:
576
+ id = 63;
577
+ mask = CLK_I2C3_SEL_MASK;
578
+ shift = CLK_I2C3_SEL_SHIFT;
579
+ break;
580
+
581
+ case CLK_I2C4:
582
+ id = 85;
583
+ mask = CLK_I2C4_SEL_MASK;
584
+ shift = CLK_I2C4_SEL_SHIFT;
585
+ break;
586
+
587
+ case CLK_I2C5:
588
+ id = 63;
589
+ mask = CLK_I2C5_SEL_MASK;
590
+ shift = CLK_I2C5_SEL_SHIFT;
591
+ break;
592
+
593
+ case CLK_I2C6:
594
+ id = 64;
595
+ mask = CLK_I2C6_SEL_MASK;
596
+ shift = CLK_I2C6_SEL_SHIFT;
597
+ break;
598
+
599
+ case CLK_I2C7:
600
+ id = 86;
601
+ mask = CLK_I2C7_SEL_MASK;
602
+ shift = CLK_I2C7_SEL_SHIFT;
603
+ break;
604
+
605
+ default:
606
+ return -ENOENT;
607
+ }
608
+
609
+ if (is_pmucru)
610
+ con = readl(&cru->pmuclksel_con[id]);
611
+ else
612
+ con = readl(&cru->clksel_con[id]);
613
+ sel = (con & mask) >> shift;
614
+ if (sel == CLK_I2C3_SEL_CLK_MATRIX_200M_SRC)
615
+ rate = 200 * MHz;
616
+ else if (sel == CLK_I2C3_SEL_CLK_MATRIX_100M_SRC)
617
+ rate = 100 * MHz;
618
+ else if (sel == CLK_I2C3_SEL_CLK_MATRIX_50M_SRC)
619
+ rate = 50 * MHz;
620
+ else
621
+ rate = OSC_HZ;
622
+
623
+ return rate;
624
+}
625
+
626
+static ulong rk3528_i2c_set_clk(struct rk3528_clk_priv *priv, ulong clk_id,
627
+ ulong rate)
628
+{
629
+ struct rk3528_cru *cru = priv->cru;
630
+ u32 id, sel, mask, shift;
631
+ u8 is_pmucru = 0;
632
+
633
+ if (rate == 200 * MHz)
634
+ sel = CLK_I2C3_SEL_CLK_MATRIX_200M_SRC;
635
+ else if (rate == 100 * MHz)
636
+ sel = CLK_I2C3_SEL_CLK_MATRIX_100M_SRC;
637
+ else if (rate == 50 * MHz)
638
+ sel = CLK_I2C3_SEL_CLK_MATRIX_50M_SRC;
639
+ else
640
+ sel = CLK_I2C3_SEL_XIN_OSC0_FUNC;
641
+
642
+ switch (clk_id) {
643
+ case CLK_I2C0:
644
+ id = 79;
645
+ mask = CLK_I2C0_SEL_MASK;
646
+ shift = CLK_I2C0_SEL_SHIFT;
647
+ break;
648
+
649
+ case CLK_I2C1:
650
+ id = 79;
651
+ mask = CLK_I2C1_SEL_MASK;
652
+ shift = CLK_I2C1_SEL_SHIFT;
653
+ break;
654
+
655
+ case CLK_I2C2:
656
+ id = 0;
657
+ mask = CLK_I2C2_SEL_MASK;
658
+ shift = CLK_I2C2_SEL_SHIFT;
659
+ is_pmucru = 1;
660
+ break;
661
+
662
+ case CLK_I2C3:
663
+ id = 63;
664
+ mask = CLK_I2C3_SEL_MASK;
665
+ shift = CLK_I2C3_SEL_SHIFT;
666
+ break;
667
+
668
+ case CLK_I2C4:
669
+ id = 85;
670
+ mask = CLK_I2C4_SEL_MASK;
671
+ shift = CLK_I2C4_SEL_SHIFT;
672
+ break;
673
+
674
+ case CLK_I2C5:
675
+ id = 63;
676
+ mask = CLK_I2C5_SEL_MASK;
677
+ shift = CLK_I2C5_SEL_SHIFT;
678
+
679
+ case CLK_I2C6:
680
+ id = 64;
681
+ mask = CLK_I2C6_SEL_MASK;
682
+ shift = CLK_I2C6_SEL_SHIFT;
683
+ break;
684
+
685
+ case CLK_I2C7:
686
+ id = 86;
687
+ mask = CLK_I2C7_SEL_MASK;
688
+ shift = CLK_I2C7_SEL_SHIFT;
689
+ break;
690
+
691
+ default:
692
+ return -ENOENT;
693
+ }
694
+
695
+ if (is_pmucru)
696
+ rk_clrsetreg(&cru->pmuclksel_con[id], mask, sel << shift);
697
+ else
698
+ rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
699
+
700
+ return rk3528_i2c_get_clk(priv, clk_id);
701
+}
702
+
703
+static ulong rk3528_spi_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
704
+{
705
+ struct rk3528_cru *cru = priv->cru;
706
+ u32 id, sel, con, mask, shift;
707
+ ulong rate;
708
+
709
+ switch (clk_id) {
710
+ case CLK_SPI0:
711
+ id = 79;
712
+ mask = CLK_SPI0_SEL_MASK;
713
+ shift = CLK_SPI0_SEL_SHIFT;
714
+ break;
715
+
716
+ case CLK_SPI1:
717
+ id = 63;
718
+ mask = CLK_SPI1_SEL_MASK;
719
+ shift = CLK_SPI1_SEL_SHIFT;
720
+ break;
721
+ default:
722
+ return -ENOENT;
723
+ }
724
+
725
+ con = readl(&cru->clksel_con[id]);
726
+ sel = (con & mask) >> shift;
727
+ if (sel == CLK_SPI1_SEL_CLK_MATRIX_200M_SRC)
728
+ rate = 200 * MHz;
729
+ else if (sel == CLK_SPI1_SEL_CLK_MATRIX_100M_SRC)
730
+ rate = 100 * MHz;
731
+ else if (sel == CLK_SPI1_SEL_CLK_MATRIX_50M_SRC)
732
+ rate = 50 * MHz;
733
+ else
734
+ rate = OSC_HZ;
735
+
736
+ return rate;
737
+}
738
+
739
+static ulong rk3528_spi_set_clk(struct rk3528_clk_priv *priv,
740
+ ulong clk_id, ulong rate)
741
+{
742
+ struct rk3528_cru *cru = priv->cru;
743
+ u32 id, sel, mask, shift;
744
+
745
+ if (rate == 200 * MHz)
746
+ sel = CLK_SPI1_SEL_CLK_MATRIX_200M_SRC;
747
+ else if (rate == 100 * MHz)
748
+ sel = CLK_SPI1_SEL_CLK_MATRIX_100M_SRC;
749
+ else if (rate == 50 * MHz)
750
+ sel = CLK_SPI1_SEL_CLK_MATRIX_50M_SRC;
751
+ else
752
+ sel = CLK_SPI1_SEL_XIN_OSC0_FUNC;
753
+
754
+ switch (clk_id) {
755
+ case CLK_SPI0:
756
+ id = 79;
757
+ mask = CLK_SPI0_SEL_MASK;
758
+ shift = CLK_SPI0_SEL_SHIFT;
759
+ break;
760
+
761
+ case CLK_SPI1:
762
+ id = 63;
763
+ mask = CLK_SPI1_SEL_MASK;
764
+ shift = CLK_SPI1_SEL_SHIFT;
765
+ break;
766
+ default:
767
+ return -ENOENT;
768
+ }
769
+
770
+ rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
771
+
772
+ return rk3528_spi_get_clk(priv, clk_id);
773
+}
774
+
775
+static ulong rk3528_pwm_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
776
+{
777
+ struct rk3528_cru *cru = priv->cru;
778
+ u32 id, sel, con, mask, shift;
779
+ ulong rate;
780
+
781
+ switch (clk_id) {
782
+ case CLK_PWM0:
783
+ id = 44;
784
+ mask = CLK_PWM0_SEL_MASK;
785
+ shift = CLK_PWM0_SEL_SHIFT;
786
+ break;
787
+
788
+ case CLK_PWM1:
789
+ id = 44;
790
+ mask = CLK_PWM1_SEL_MASK;
791
+ shift = CLK_PWM1_SEL_SHIFT;
792
+ break;
793
+
794
+ default:
795
+ return -ENOENT;
796
+ }
797
+
798
+ con = readl(&cru->clksel_con[id]);
799
+ sel = (con & mask) >> shift;
800
+ if (sel == CLK_PWM0_SEL_CLK_MATRIX_100M_SRC)
801
+ rate = 100 * MHz;
802
+ if (sel == CLK_PWM0_SEL_CLK_MATRIX_50M_SRC)
803
+ rate = 50 * MHz;
804
+ else
805
+ rate = OSC_HZ;
806
+
807
+ return rate;
808
+}
809
+
810
+static ulong rk3528_pwm_set_clk(struct rk3528_clk_priv *priv,
811
+ ulong clk_id, ulong rate)
812
+{
813
+ struct rk3528_cru *cru = priv->cru;
814
+ u32 id, sel, mask, shift;
815
+
816
+ if (rate == 100 * MHz)
817
+ sel = CLK_PWM0_SEL_CLK_MATRIX_100M_SRC;
818
+ else if (rate == 50 * MHz)
819
+ sel = CLK_PWM0_SEL_CLK_MATRIX_50M_SRC;
820
+ else
821
+ sel = CLK_PWM0_SEL_XIN_OSC0_FUNC;
822
+
823
+ switch (clk_id) {
824
+ case CLK_PWM0:
825
+ id = 44;
826
+ mask = CLK_PWM0_SEL_MASK;
827
+ shift = CLK_PWM0_SEL_SHIFT;
828
+ break;
829
+
830
+ case CLK_PWM1:
831
+ id = 44;
832
+ mask = CLK_PWM1_SEL_MASK;
833
+ shift = CLK_PWM1_SEL_SHIFT;
834
+ break;
835
+
836
+ default:
837
+ return -ENOENT;
838
+ }
839
+
840
+ rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
841
+
842
+ return rk3528_pwm_get_clk(priv, clk_id);
843
+}
844
+
845
+static ulong rk3528_adc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
846
+{
847
+ struct rk3528_cru *cru = priv->cru;
848
+ u32 div, con;
849
+
850
+ con = readl(&cru->clksel_con[74]);
851
+ switch (clk_id) {
852
+ case CLK_SARADC:
853
+ div = (con & CLK_SARADC_DIV_MASK) >>
854
+ CLK_SARADC_DIV_SHIFT;
855
+ break;
856
+
857
+ case CLK_TSADC_TSEN:
858
+ div = (con & CLK_TSADC_TSEN_DIV_MASK) >>
859
+ CLK_TSADC_TSEN_DIV_SHIFT;
860
+ break;
861
+
862
+ case CLK_TSADC:
863
+ div = (con & CLK_TSADC_DIV_MASK) >>
864
+ CLK_TSADC_DIV_SHIFT;
865
+ break;
866
+
867
+ default:
868
+ return -ENOENT;
869
+ }
870
+
871
+ return DIV_TO_RATE(OSC_HZ, div);
872
+}
873
+
874
+static ulong rk3528_adc_set_clk(struct rk3528_clk_priv *priv,
875
+ ulong clk_id, ulong rate)
876
+{
877
+ struct rk3528_cru *cru = priv->cru;
878
+ u32 div, mask, shift;
879
+
880
+ switch (clk_id) {
881
+ case CLK_SARADC:
882
+ mask = CLK_SARADC_DIV_MASK;
883
+ shift = CLK_SARADC_DIV_SHIFT;
884
+ break;
885
+
886
+ case CLK_TSADC_TSEN:
887
+ mask = CLK_TSADC_TSEN_DIV_MASK;
888
+ shift = CLK_TSADC_TSEN_DIV_SHIFT;
889
+ break;
890
+
891
+ case CLK_TSADC:
892
+ mask = CLK_TSADC_DIV_MASK;
893
+ shift = CLK_TSADC_DIV_SHIFT;
894
+ break;
895
+
896
+ default:
897
+ return -ENOENT;
898
+ }
899
+
900
+ div = DIV_ROUND_UP(OSC_HZ, rate);
901
+ rk_clrsetreg(&cru->clksel_con[74], mask, (div - 1) << shift);
902
+
903
+ return rk3528_adc_get_clk(priv, clk_id);
904
+}
905
+
906
+static ulong rk3528_sdmmc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
907
+{
908
+ struct rk3528_cru *cru = priv->cru;
909
+ u32 div, sel, con;
910
+ ulong prate;
911
+
912
+ con = readl(&cru->clksel_con[85]);
913
+ div = (con & CCLK_SRC_SDMMC0_DIV_MASK) >>
914
+ CCLK_SRC_SDMMC0_DIV_SHIFT;
915
+ sel = (con & CCLK_SRC_SDMMC0_SEL_MASK) >>
916
+ CCLK_SRC_SDMMC0_SEL_SHIFT;
917
+
918
+ if (sel == CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX)
919
+ prate = priv->gpll_hz;
920
+ else if (sel == CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX)
921
+ prate = priv->cpll_hz;
922
+ else
923
+ prate = OSC_HZ;
924
+
925
+ return DIV_TO_RATE(prate, div);
926
+}
927
+
928
+static ulong rk3528_sdmmc_set_clk(struct rk3528_clk_priv *priv,
929
+ ulong clk_id, ulong rate)
930
+{
931
+ struct rk3528_cru *cru = priv->cru;
932
+ u32 div, sel;
933
+
934
+ if (OSC_HZ % rate == 0) {
935
+ div = DIV_ROUND_UP(OSC_HZ, rate);
936
+ sel = CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC;
937
+ } else if ((priv->cpll_hz % rate) == 0) {
938
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
939
+ sel = CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX;
940
+ } else {
941
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
942
+ sel = CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX;
943
+ }
944
+
945
+ assert(div - 1 <= 31);
946
+ rk_clrsetreg(&cru->clksel_con[85],
947
+ CCLK_SRC_SDMMC0_SEL_MASK |
948
+ CCLK_SRC_SDMMC0_DIV_MASK,
949
+ sel << CCLK_SRC_SDMMC0_SEL_SHIFT |
950
+ (div - 1) << CCLK_SRC_SDMMC0_DIV_SHIFT);
951
+
952
+ return rk3528_sdmmc_get_clk(priv, clk_id);
953
+}
954
+
955
+static ulong rk3528_sfc_get_clk(struct rk3528_clk_priv *priv)
956
+{
957
+ struct rk3528_cru *cru = priv->cru;
958
+ u32 div, sel, con, parent;
959
+
960
+ con = readl(&cru->clksel_con[61]);
961
+ div = (con & SCLK_SFC_DIV_MASK) >>
962
+ SCLK_SFC_DIV_SHIFT;
963
+ sel = (con & SCLK_SFC_SEL_MASK) >>
964
+ SCLK_SFC_SEL_SHIFT;
965
+ if (sel == SCLK_SFC_SEL_CLK_GPLL_MUX)
966
+ parent = priv->gpll_hz;
967
+ else if (sel == SCLK_SFC_SEL_CLK_CPLL_MUX)
968
+ parent = priv->cpll_hz;
969
+ else
970
+ parent = OSC_HZ;
971
+
972
+ return DIV_TO_RATE(parent, div);
973
+}
974
+
975
+static ulong rk3528_sfc_set_clk(struct rk3528_clk_priv *priv, ulong rate)
976
+{
977
+ struct rk3528_cru *cru = priv->cru;
978
+ int div, sel;
979
+
980
+ if (OSC_HZ % rate == 0) {
981
+ div = DIV_ROUND_UP(OSC_HZ, rate);
982
+ sel = SCLK_SFC_SEL_XIN_OSC0_FUNC;
983
+ } else if ((priv->cpll_hz % rate) == 0) {
984
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
985
+ sel = SCLK_SFC_SEL_CLK_CPLL_MUX;
986
+ } else {
987
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
988
+ sel = SCLK_SFC_SEL_CLK_GPLL_MUX;
989
+ }
990
+
991
+ assert(div - 1 <= 63);
992
+ rk_clrsetreg(&cru->clksel_con[61],
993
+ SCLK_SFC_SEL_MASK |
994
+ SCLK_SFC_DIV_MASK,
995
+ sel << SCLK_SFC_SEL_SHIFT |
996
+ (div - 1) << SCLK_SFC_DIV_SHIFT);
997
+
998
+ return rk3528_sfc_get_clk(priv);
999
+}
1000
+
1001
+static ulong rk3528_emmc_get_clk(struct rk3528_clk_priv *priv)
1002
+{
1003
+ struct rk3528_cru *cru = priv->cru;
1004
+ u32 div, sel, con, parent;
1005
+
1006
+ con = readl(&cru->clksel_con[62]);
1007
+ div = (con & CCLK_SRC_EMMC_DIV_MASK) >>
1008
+ CCLK_SRC_EMMC_DIV_SHIFT;
1009
+ sel = (con & CCLK_SRC_EMMC_SEL_MASK) >>
1010
+ CCLK_SRC_EMMC_SEL_SHIFT;
1011
+
1012
+ if (sel == CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX)
1013
+ parent = priv->gpll_hz;
1014
+ else if (sel == CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX)
1015
+ parent = priv->cpll_hz;
1016
+ else
1017
+ parent = OSC_HZ;
1018
+
1019
+ return DIV_TO_RATE(parent, div);
1020
+}
1021
+
1022
+static ulong rk3528_emmc_set_clk(struct rk3528_clk_priv *priv, ulong rate)
1023
+{
1024
+ struct rk3528_cru *cru = priv->cru;
1025
+ u32 div, sel;
1026
+
1027
+ if (OSC_HZ % rate == 0) {
1028
+ div = DIV_ROUND_UP(OSC_HZ, rate);
1029
+ sel = CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC;
1030
+ } else if ((priv->cpll_hz % rate) == 0) {
1031
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
1032
+ sel = CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX;
1033
+ } else {
1034
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
1035
+ sel = CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX;
1036
+ }
1037
+
1038
+ assert(div - 1 <= 31);
1039
+ rk_clrsetreg(&cru->clksel_con[62],
1040
+ CCLK_SRC_EMMC_SEL_MASK |
1041
+ CCLK_SRC_EMMC_DIV_MASK,
1042
+ sel << CCLK_SRC_EMMC_SEL_SHIFT |
1043
+ (div - 1) << CCLK_SRC_EMMC_DIV_SHIFT);
1044
+
1045
+ return rk3528_emmc_get_clk(priv);
1046
+}
1047
+
1048
+static ulong rk3528_dclk_vop_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
1049
+{
1050
+ struct rk3528_cru *cru = priv->cru;
1051
+ u32 div_mask, div_shift;
1052
+ u32 sel_mask, sel_shift;
1053
+ u32 id, con, sel, div;
1054
+ ulong prate;
1055
+
1056
+ switch (clk_id) {
1057
+ case DCLK_VOP0:
1058
+ id = 32;
1059
+ sel_mask = DCLK_VOP_SRC0_SEL_MASK;
1060
+ sel_shift = DCLK_VOP_SRC0_SEL_SHIFT;
1061
+ /* FIXME if need src: clk_hdmiphy_pixel_io */
1062
+ div_mask = DCLK_VOP_SRC0_DIV_MASK;
1063
+ div_shift = DCLK_VOP_SRC0_DIV_SHIFT;
1064
+ break;
1065
+
1066
+ case DCLK_VOP1:
1067
+ id = 33;
1068
+ sel_mask = DCLK_VOP_SRC1_SEL_MASK;
1069
+ sel_shift = DCLK_VOP_SRC1_SEL_SHIFT;
1070
+ div_mask = DCLK_VOP_SRC1_DIV_MASK;
1071
+ div_shift = DCLK_VOP_SRC1_DIV_SHIFT;
1072
+ break;
1073
+
1074
+ default:
1075
+ return -ENOENT;
1076
+ }
1077
+
1078
+ con = readl(&cru->clksel_con[id]);
1079
+ div = (con & div_mask) >> div_shift;
1080
+ sel = (con & sel_mask) >> sel_shift;
1081
+ if (sel == DCLK_VOP_SRC_SEL_CLK_GPLL_MUX)
1082
+ prate = priv->gpll_hz;
1083
+ else
1084
+ prate = priv->cpll_hz;
1085
+
1086
+ return DIV_TO_RATE(prate, div);
1087
+}
1088
+
1089
+static ulong rk3528_dclk_vop_set_clk(struct rk3528_clk_priv *priv,
1090
+ ulong clk_id, ulong rate)
1091
+{
1092
+ struct rk3528_cru *cru = priv->cru;
1093
+ u32 div_mask, div_shift;
1094
+ u32 sel_mask, sel_shift;
1095
+ u32 id, sel, div;
1096
+ ulong prate;
1097
+
1098
+ switch (clk_id) {
1099
+ case DCLK_VOP0:
1100
+ id = 32;
1101
+ sel_mask = DCLK_VOP_SRC0_SEL_MASK;
1102
+ sel_shift = DCLK_VOP_SRC0_SEL_SHIFT;
1103
+ /* FIXME if need src: clk_hdmiphy_pixel_io */
1104
+ div_mask = DCLK_VOP_SRC0_DIV_MASK;
1105
+ div_shift = DCLK_VOP_SRC0_DIV_SHIFT;
1106
+ break;
1107
+
1108
+ case DCLK_VOP1:
1109
+ id = 33;
1110
+ sel_mask = DCLK_VOP_SRC1_SEL_MASK;
1111
+ sel_shift = DCLK_VOP_SRC1_SEL_SHIFT;
1112
+ div_mask = DCLK_VOP_SRC1_DIV_MASK;
1113
+ div_shift = DCLK_VOP_SRC1_DIV_SHIFT;
1114
+ break;
1115
+
1116
+ default:
1117
+ return -ENOENT;
1118
+ }
1119
+
1120
+ if ((priv->gpll_hz % rate) == 0) {
1121
+ prate = priv->gpll_hz;
1122
+ sel = (DCLK_VOP_SRC_SEL_CLK_GPLL_MUX << sel_shift) & sel_mask;
1123
+ } else {
1124
+ prate = priv->cpll_hz;
1125
+ sel = (DCLK_VOP_SRC_SEL_CLK_CPLL_MUX << sel_shift) & sel_mask;
1126
+ }
1127
+
1128
+ div = ((DIV_ROUND_UP(prate, rate) - 1) << div_shift) & div_mask;
1129
+ rk_clrsetreg(&cru->clksel_con[id], sel, div);
1130
+
1131
+ return rk3528_dclk_vop_get_clk(priv, clk_id);
1132
+}
1133
+
1134
+static ulong rk3528_uart_get_rate(struct rk3528_clk_priv *priv, ulong clk_id)
1135
+{
1136
+ struct rk3528_cru *cru = priv->cru;
1137
+ u32 sel_shift, sel_mask, div_shift, div_mask;
1138
+ u32 sel, id, con, frac_div, div;
1139
+ ulong m, n, rate;
1140
+
1141
+ switch (clk_id) {
1142
+ case SCLK_UART0:
1143
+ id = 6;
1144
+ sel_shift = SCLK_UART0_SRC_SEL_SHIFT;
1145
+ sel_mask = SCLK_UART0_SRC_SEL_MASK;
1146
+ div_shift = CLK_UART0_SRC_DIV_SHIFT;
1147
+ div_mask = CLK_UART0_SRC_DIV_MASK;
1148
+ break;
1149
+
1150
+ case SCLK_UART1:
1151
+ id = 8;
1152
+ sel_shift = SCLK_UART1_SRC_SEL_SHIFT;
1153
+ sel_mask = SCLK_UART1_SRC_SEL_MASK;
1154
+ div_shift = CLK_UART1_SRC_DIV_SHIFT;
1155
+ div_mask = CLK_UART1_SRC_DIV_MASK;
1156
+ break;
1157
+
1158
+ case SCLK_UART2:
1159
+ id = 10;
1160
+ sel_shift = SCLK_UART2_SRC_SEL_SHIFT;
1161
+ sel_mask = SCLK_UART2_SRC_SEL_MASK;
1162
+ div_shift = CLK_UART2_SRC_DIV_SHIFT;
1163
+ div_mask = CLK_UART2_SRC_DIV_MASK;
1164
+ break;
1165
+
1166
+ case SCLK_UART3:
1167
+ id = 12;
1168
+ sel_shift = SCLK_UART3_SRC_SEL_SHIFT;
1169
+ sel_mask = SCLK_UART3_SRC_SEL_MASK;
1170
+ div_shift = CLK_UART3_SRC_DIV_SHIFT;
1171
+ div_mask = CLK_UART3_SRC_DIV_MASK;
1172
+ break;
1173
+
1174
+ case SCLK_UART4:
1175
+ id = 14;
1176
+ sel_shift = SCLK_UART4_SRC_SEL_SHIFT;
1177
+ sel_mask = SCLK_UART4_SRC_SEL_MASK;
1178
+ div_shift = CLK_UART4_SRC_DIV_SHIFT;
1179
+ div_mask = CLK_UART4_SRC_DIV_MASK;
1180
+ break;
1181
+
1182
+ case SCLK_UART5:
1183
+ id = 16;
1184
+ sel_shift = SCLK_UART5_SRC_SEL_SHIFT;
1185
+ sel_mask = SCLK_UART5_SRC_SEL_MASK;
1186
+ div_shift = CLK_UART5_SRC_DIV_SHIFT;
1187
+ div_mask = CLK_UART5_SRC_DIV_MASK;
1188
+ break;
1189
+
1190
+ case SCLK_UART6:
1191
+ id = 18;
1192
+ sel_shift = SCLK_UART6_SRC_SEL_SHIFT;
1193
+ sel_mask = SCLK_UART6_SRC_SEL_MASK;
1194
+ div_shift = CLK_UART6_SRC_DIV_SHIFT;
1195
+ div_mask = CLK_UART6_SRC_DIV_MASK;
1196
+ break;
1197
+
1198
+ case SCLK_UART7:
1199
+ id = 20;
1200
+ sel_shift = SCLK_UART7_SRC_SEL_SHIFT;
1201
+ sel_mask = SCLK_UART7_SRC_SEL_MASK;
1202
+ div_shift = CLK_UART7_SRC_DIV_SHIFT;
1203
+ div_mask = CLK_UART7_SRC_DIV_MASK;
1204
+ break;
1205
+
1206
+ default:
1207
+ return -ENOENT;
1208
+ }
1209
+
1210
+ con = readl(&cru->clksel_con[id - 2]);
1211
+ div = (con & div_mask) >> div_shift;
1212
+
1213
+ con = readl(&cru->clksel_con[id]);
1214
+ sel = (con & sel_mask) >> sel_shift;
1215
+
1216
+ if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_SRC) {
1217
+ rate = DIV_TO_RATE(priv->gpll_hz, div);
1218
+ } else if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_FRAC) {
1219
+ frac_div = readl(&cru->clksel_con[id - 1]);
1220
+ n = (frac_div & 0xffff0000) >> 16;
1221
+ m = frac_div & 0x0000ffff;
1222
+ rate = DIV_TO_RATE(priv->gpll_hz, div) * n / m;
1223
+ } else {
1224
+ rate = OSC_HZ;
1225
+ }
1226
+
1227
+ return rate;
1228
+}
1229
+
1230
+static ulong rk3528_uart_set_rate(struct rk3528_clk_priv *priv,
1231
+ ulong clk_id, ulong rate)
1232
+{
1233
+ struct rk3528_cru *cru = priv->cru;
1234
+ u32 sel_shift, sel_mask, div_shift, div_mask;
1235
+ u32 sel, id, div;
1236
+ ulong m = 0, n = 0, val;
1237
+
1238
+ if (rate == OSC_HZ) {
1239
+ sel = SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC;
1240
+ div = DIV_ROUND_UP(OSC_HZ, rate);
1241
+ } else if (priv->gpll_hz % rate == 0) {
1242
+ sel = SCLK_UART0_SRC_SEL_CLK_UART0_SRC;
1243
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
1244
+ } else {
1245
+ sel = SCLK_UART0_SRC_SEL_CLK_UART0_FRAC;
1246
+ div = 2;
1247
+ rational_best_approximation(rate, priv->gpll_hz / div,
1248
+ GENMASK(16 - 1, 0),
1249
+ GENMASK(16 - 1, 0),
1250
+ &n, &m);
1251
+ }
1252
+
1253
+ switch (clk_id) {
1254
+ case SCLK_UART0:
1255
+ id = 6;
1256
+ sel_shift = SCLK_UART0_SRC_SEL_SHIFT;
1257
+ sel_mask = SCLK_UART0_SRC_SEL_MASK;
1258
+ div_shift = CLK_UART0_SRC_DIV_SHIFT;
1259
+ div_mask = CLK_UART0_SRC_DIV_MASK;
1260
+ break;
1261
+
1262
+ case SCLK_UART1:
1263
+ id = 8;
1264
+ sel_shift = SCLK_UART1_SRC_SEL_SHIFT;
1265
+ sel_mask = SCLK_UART1_SRC_SEL_MASK;
1266
+ div_shift = CLK_UART1_SRC_DIV_SHIFT;
1267
+ div_mask = CLK_UART1_SRC_DIV_MASK;
1268
+ break;
1269
+
1270
+ case SCLK_UART2:
1271
+ id = 10;
1272
+ sel_shift = SCLK_UART2_SRC_SEL_SHIFT;
1273
+ sel_mask = SCLK_UART2_SRC_SEL_MASK;
1274
+ div_shift = CLK_UART2_SRC_DIV_SHIFT;
1275
+ div_mask = CLK_UART2_SRC_DIV_MASK;
1276
+ break;
1277
+
1278
+ case SCLK_UART3:
1279
+ id = 12;
1280
+ sel_shift = SCLK_UART3_SRC_SEL_SHIFT;
1281
+ sel_mask = SCLK_UART3_SRC_SEL_MASK;
1282
+ div_shift = CLK_UART3_SRC_DIV_SHIFT;
1283
+ div_mask = CLK_UART3_SRC_DIV_MASK;
1284
+ break;
1285
+
1286
+ case SCLK_UART4:
1287
+ id = 14;
1288
+ sel_shift = SCLK_UART4_SRC_SEL_SHIFT;
1289
+ sel_mask = SCLK_UART4_SRC_SEL_MASK;
1290
+ div_shift = CLK_UART4_SRC_DIV_SHIFT;
1291
+ div_mask = CLK_UART4_SRC_DIV_MASK;
1292
+ break;
1293
+
1294
+ case SCLK_UART5:
1295
+ id = 16;
1296
+ sel_shift = SCLK_UART5_SRC_SEL_SHIFT;
1297
+ sel_mask = SCLK_UART5_SRC_SEL_MASK;
1298
+ div_shift = CLK_UART5_SRC_DIV_SHIFT;
1299
+ div_mask = CLK_UART5_SRC_DIV_MASK;
1300
+ break;
1301
+
1302
+ case SCLK_UART6:
1303
+ id = 18;
1304
+ sel_shift = SCLK_UART6_SRC_SEL_SHIFT;
1305
+ sel_mask = SCLK_UART6_SRC_SEL_MASK;
1306
+ div_shift = CLK_UART6_SRC_DIV_SHIFT;
1307
+ div_mask = CLK_UART6_SRC_DIV_MASK;
1308
+ break;
1309
+
1310
+ case SCLK_UART7:
1311
+ id = 20;
1312
+ sel_shift = SCLK_UART7_SRC_SEL_SHIFT;
1313
+ sel_mask = SCLK_UART7_SRC_SEL_MASK;
1314
+ div_shift = CLK_UART7_SRC_DIV_SHIFT;
1315
+ div_mask = CLK_UART7_SRC_DIV_MASK;
1316
+ break;
1317
+
1318
+ default:
1319
+ return -ENOENT;
1320
+ }
1321
+
1322
+ rk_clrsetreg(&cru->clksel_con[id - 2], div_mask, (div - 1) << div_shift);
1323
+ rk_clrsetreg(&cru->clksel_con[id], sel_mask, sel << sel_shift);
1324
+ if (m && n) {
1325
+ val = n << 16 | m;
1326
+ writel(val, &cru->clksel_con[id - 1]);
1327
+ }
1328
+
1329
+ return rk3528_uart_get_rate(priv, clk_id);
1330
+}
1331
+
1332
+static ulong rk3528_clk_get_rate(struct clk *clk)
1333
+{
1334
+ struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
1335
+ ulong rate = 0;
1336
+
1337
+ if (!priv->gpll_hz || !priv->cpll_hz) {
1338
+ printf("%s: gpll=%lu, cpll=%ld\n",
1339
+ __func__, priv->gpll_hz, priv->cpll_hz);
1340
+ return -ENOENT;
1341
+ }
1342
+
1343
+ switch (clk->id) {
1344
+ case PLL_APLL:
1345
+ case ARMCLK:
1346
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru,
1347
+ APLL);
1348
+ break;
1349
+ case PLL_CPLL:
1350
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], priv->cru,
1351
+ CPLL);
1352
+ break;
1353
+ case PLL_GPLL:
1354
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], priv->cru,
1355
+ GPLL);
1356
+ break;
1357
+
1358
+ case PLL_PPLL:
1359
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], priv->cru,
1360
+ PPLL);
1361
+ break;
1362
+ case PLL_DPLL:
1363
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[DPLL], priv->cru,
1364
+ DPLL);
1365
+ break;
1366
+
1367
+ case TCLK_WDT_NS:
1368
+ rate = OSC_HZ;
1369
+ break;
1370
+ case CLK_I2C0:
1371
+ case CLK_I2C1:
1372
+ case CLK_I2C2:
1373
+ case CLK_I2C3:
1374
+ case CLK_I2C4:
1375
+ case CLK_I2C5:
1376
+ case CLK_I2C6:
1377
+ case CLK_I2C7:
1378
+ rate = rk3528_i2c_get_clk(priv, clk->id);
1379
+ break;
1380
+ case CLK_SPI0:
1381
+ case CLK_SPI1:
1382
+ rate = rk3528_spi_get_clk(priv, clk->id);
1383
+ break;
1384
+ case CLK_PWM0:
1385
+ case CLK_PWM1:
1386
+ rate = rk3528_pwm_get_clk(priv, clk->id);
1387
+ break;
1388
+ case CLK_SARADC:
1389
+ case CLK_TSADC:
1390
+ case CLK_TSADC_TSEN:
1391
+ rate = rk3528_adc_get_clk(priv, clk->id);
1392
+ break;
1393
+ case CCLK_SRC_EMMC:
1394
+ rate = rk3528_emmc_get_clk(priv);
1395
+ break;
1396
+ case HCLK_SDMMC0:
1397
+ case CCLK_SRC_SDMMC0:
1398
+ rate = rk3528_sdmmc_get_clk(priv, clk->id);
1399
+ break;
1400
+ case SCLK_SFC:
1401
+ rate = rk3528_sfc_get_clk(priv);
1402
+ break;
1403
+ case DCLK_VOP0:
1404
+ case DCLK_VOP1:
1405
+ rate = rk3528_dclk_vop_get_clk(priv, clk->id);
1406
+ break;
1407
+ case DCLK_CVBS:
1408
+ rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1) / 4;
1409
+ break;
1410
+ case DCLK_4X_CVBS:
1411
+ rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1);
1412
+ break;
1413
+ case SCLK_UART0:
1414
+ case SCLK_UART1:
1415
+ case SCLK_UART2:
1416
+ case SCLK_UART3:
1417
+ case SCLK_UART4:
1418
+ case SCLK_UART5:
1419
+ case SCLK_UART6:
1420
+ case SCLK_UART7:
1421
+ rate = rk3528_uart_get_rate(priv, clk->id);
1422
+ break;
1423
+ case CLK_MATRIX_50M_SRC:
1424
+ case CLK_MATRIX_100M_SRC:
1425
+ case CLK_MATRIX_150M_SRC:
1426
+ case CLK_MATRIX_200M_SRC:
1427
+ case CLK_MATRIX_250M_SRC:
1428
+ case CLK_MATRIX_300M_SRC:
1429
+ case CLK_MATRIX_339M_SRC:
1430
+ case CLK_MATRIX_400M_SRC:
1431
+ case CLK_MATRIX_500M_SRC:
1432
+ case CLK_MATRIX_600M_SRC:
1433
+ case ACLK_BUS_VOPGL_BIU:
1434
+ rate = rk3528_cgpll_matrix_get_rate(priv, clk->id);
1435
+ break;
1436
+ case CLK_PPLL_50M_MATRIX:
1437
+ case CLK_PPLL_100M_MATRIX:
1438
+ case CLK_PPLL_125M_MATRIX:
1439
+ case CLK_GMAC1_VPU_25M:
1440
+ case CLK_GMAC1_RMII_VPU:
1441
+ case CLK_GMAC1_SRC_VPU:
1442
+ rate = rk3528_ppll_matrix_get_rate(priv, clk->id);
1443
+ break;
1444
+ default:
1445
+ return -ENOENT;
1446
+ }
1447
+
1448
+ return rate;
1449
+};
1450
+
1451
+static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
1452
+{
1453
+ struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
1454
+ ulong ret = 0;
1455
+
1456
+ if (!priv->gpll_hz) {
1457
+ printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
1458
+ return -ENOENT;
1459
+ }
1460
+
1461
+ switch (clk->id) {
1462
+ case PLL_APLL:
1463
+ case ARMCLK:
1464
+ if (priv->armclk_hz)
1465
+ rk3528_armclk_set_clk(priv, rate);
1466
+ priv->armclk_hz = rate;
1467
+ break;
1468
+ case PLL_CPLL:
1469
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru,
1470
+ CPLL, rate);
1471
+ priv->cpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL],
1472
+ priv->cru, CPLL);
1473
+ break;
1474
+ case PLL_GPLL:
1475
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru,
1476
+ GPLL, rate);
1477
+ priv->gpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL],
1478
+ priv->cru, GPLL);
1479
+ break;
1480
+ case PLL_PPLL:
1481
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru,
1482
+ PPLL, rate);
1483
+ priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL],
1484
+ priv->cru, PPLL);
1485
+ break;
1486
+ case TCLK_WDT_NS:
1487
+ return (rate == OSC_HZ) ? 0 : -EINVAL;
1488
+ case CLK_I2C0:
1489
+ case CLK_I2C1:
1490
+ case CLK_I2C2:
1491
+ case CLK_I2C3:
1492
+ case CLK_I2C4:
1493
+ case CLK_I2C5:
1494
+ case CLK_I2C6:
1495
+ case CLK_I2C7:
1496
+ ret = rk3528_i2c_set_clk(priv, clk->id, rate);
1497
+ break;
1498
+ case CLK_SPI0:
1499
+ case CLK_SPI1:
1500
+ ret = rk3528_spi_set_clk(priv, clk->id, rate);
1501
+ break;
1502
+ case CLK_PWM0:
1503
+ case CLK_PWM1:
1504
+ ret = rk3528_pwm_set_clk(priv, clk->id, rate);
1505
+ break;
1506
+ case CLK_SARADC:
1507
+ case CLK_TSADC:
1508
+ case CLK_TSADC_TSEN:
1509
+ ret = rk3528_adc_set_clk(priv, clk->id, rate);
1510
+ break;
1511
+ case HCLK_SDMMC0:
1512
+ case CCLK_SRC_SDMMC0:
1513
+ ret = rk3528_sdmmc_set_clk(priv, clk->id, rate);
1514
+ break;
1515
+ case SCLK_SFC:
1516
+ ret = rk3528_sfc_set_clk(priv, rate);
1517
+ break;
1518
+ case CCLK_SRC_EMMC:
1519
+ ret = rk3528_emmc_set_clk(priv, rate);
1520
+ break;
1521
+ case DCLK_VOP0:
1522
+ case DCLK_VOP1:
1523
+ ret = rk3528_dclk_vop_set_clk(priv, clk->id, rate);
1524
+ break;
1525
+ case SCLK_UART0:
1526
+ case SCLK_UART1:
1527
+ case SCLK_UART2:
1528
+ case SCLK_UART3:
1529
+ case SCLK_UART4:
1530
+ case SCLK_UART5:
1531
+ case SCLK_UART6:
1532
+ case SCLK_UART7:
1533
+ ret = rk3528_uart_set_rate(priv, clk->id, rate);
1534
+ break;
1535
+ case CLK_MATRIX_50M_SRC:
1536
+ case CLK_MATRIX_100M_SRC:
1537
+ case CLK_MATRIX_150M_SRC:
1538
+ case CLK_MATRIX_200M_SRC:
1539
+ case CLK_MATRIX_250M_SRC:
1540
+ case CLK_MATRIX_300M_SRC:
1541
+ case CLK_MATRIX_339M_SRC:
1542
+ case CLK_MATRIX_400M_SRC:
1543
+ case CLK_MATRIX_500M_SRC:
1544
+ case CLK_MATRIX_600M_SRC:
1545
+ case ACLK_BUS_VOPGL_BIU:
1546
+ ret = rk3528_cgpll_matrix_set_rate(priv, clk->id, rate);
1547
+ break;
1548
+ case CLK_PPLL_50M_MATRIX:
1549
+ case CLK_PPLL_100M_MATRIX:
1550
+ case CLK_PPLL_125M_MATRIX:
1551
+ case CLK_GMAC1_VPU_25M:
1552
+ ret = rk3528_ppll_matrix_set_rate(priv, clk->id, rate);
1553
+ break;
1554
+ case CLK_GMAC1_RMII_VPU:
1555
+ case CLK_GMAC1_SRC_VPU:
1556
+ /* dummy set */
1557
+ ret = rk3528_ppll_matrix_get_rate(priv, clk->id);
1558
+ break;
1559
+ default:
1560
+ return -ENOENT;
1561
+ }
1562
+
1563
+ return ret;
1564
+};
1565
+
1566
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1567
+static int rk3528_clk_set_parent(struct clk *clk, struct clk *parent)
1568
+{
1569
+ struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
1570
+ const char *clock_dev_name = parent->dev->name;
1571
+
1572
+ switch (clk->id) {
1573
+ case DCLK_VOP0:
1574
+ if (!strcmp(clock_dev_name, "inno_hdmi_pll_clk"))
1575
+ /* clk_hdmiphy_pixel_io */
1576
+ rk_clrsetreg(&priv->cru->clksel_con[84], 0x1, 1);
1577
+ else
1578
+ rk_clrsetreg(&priv->cru->clksel_con[84], 0x1, 0);
1579
+ break;
1580
+
1581
+ default:
1582
+ return -ENOENT;
1583
+ }
1584
+
1585
+ return 0;
1586
+}
1587
+#endif
1588
+
1589
+static struct clk_ops rk3528_clk_ops = {
1590
+ .get_rate = rk3528_clk_get_rate,
1591
+ .set_rate = rk3528_clk_set_rate,
1592
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1593
+ .set_parent = rk3528_clk_set_parent,
1594
+#endif
1595
+};
1596
+
1597
+static ulong rk3528_grfclk_get_rate(struct clk *clk)
1598
+{
1599
+ struct rk3528_clk_priv *priv;
1600
+ struct udevice *cru_dev;
1601
+ ulong rate = 0;
1602
+ int ret;
1603
+
1604
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
1605
+ DM_GET_DRIVER(rockchip_rk3528_cru),
1606
+ &cru_dev);
1607
+ if (ret) {
1608
+ printf("%s: could not find cru device\n", __func__);
1609
+ return ret;
1610
+ }
1611
+ priv = dev_get_priv(cru_dev);
1612
+
1613
+ switch (clk->id) {
1614
+ case SCLK_SDMMC_SAMPLE:
1615
+ rate = rk3528_sdmmc_get_clk(priv, CCLK_SRC_SDMMC0) / 2;
1616
+ break;
1617
+ default:
1618
+ return -ENOENT;
1619
+ }
1620
+
1621
+ return rate;
1622
+};
1623
+
1624
+#define ROCKCHIP_MMC_DELAY_SEL BIT(11)
1625
+#define ROCKCHIP_MMC_DEGREE_MASK 0x3
1626
+#define ROCKCHIP_MMC_DELAYNUM_OFFSET 3
1627
+#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
1628
+#define PSECS_PER_SEC 1000000000000LL
1629
+/*
1630
+ * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
1631
+ * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
1632
+ */
1633
+#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
1634
+
1635
+int rk3528_mmc_get_phase(struct clk *clk)
1636
+{
1637
+ struct rk3528_grf_clk_priv *priv = dev_get_priv(clk->dev);
1638
+ u32 raw_value = 0, delay_num;
1639
+ u16 degrees = 0;
1640
+ ulong rate;
1641
+
1642
+ rate = rk3528_grfclk_get_rate(clk);
1643
+ if (rate < 0)
1644
+ return rate;
1645
+
1646
+ if (clk->id == SCLK_SDMMC_SAMPLE)
1647
+ raw_value = readl(&priv->grf->sdmmc_con1);
1648
+ else
1649
+ return -ENONET;
1650
+
1651
+ raw_value >>= 1;
1652
+ degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
1653
+
1654
+ if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
1655
+ /* degrees/delaynum * 10000 */
1656
+ unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
1657
+ 36 * (rate / 1000000);
1658
+
1659
+ delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
1660
+ delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
1661
+ degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000);
1662
+ }
1663
+
1664
+ return degrees % 360;
1665
+}
1666
+
1667
+int rk3528_mmc_set_phase(struct clk *clk, u32 degrees)
1668
+{
1669
+ struct rk3528_grf_clk_priv *priv = dev_get_priv(clk->dev);
1670
+ u8 nineties, remainder, delay_num;
1671
+ u32 raw_value, delay;
1672
+ ulong rate;
1673
+
1674
+ rate = rk3528_grfclk_get_rate(clk);
1675
+ if (rate < 0)
1676
+ return rate;
1677
+
1678
+ nineties = degrees / 90;
1679
+ remainder = (degrees % 90);
1680
+
1681
+ /*
1682
+ * Convert to delay; do a little extra work to make sure we
1683
+ * don't overflow 32-bit / 64-bit numbers.
1684
+ */
1685
+ delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
1686
+ delay *= remainder;
1687
+ delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 *
1688
+ (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
1689
+
1690
+ delay_num = (u8)min_t(u32, delay, 255);
1691
+
1692
+ raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
1693
+ raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
1694
+ raw_value |= nineties;
1695
+
1696
+ raw_value <<= 1;
1697
+ if (clk->id == SCLK_SDMMC_SAMPLE)
1698
+ writel(raw_value | 0xffff0000, &priv->grf->sdmmc_con1);
1699
+ else
1700
+ return -ENONET;
1701
+
1702
+ debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n",
1703
+ degrees, delay_num, raw_value, rk3528_mmc_get_phase(clk));
1704
+
1705
+ return 0;
1706
+}
1707
+
1708
+static int rk3528_grfclk_get_phase(struct clk *clk)
1709
+{
1710
+ int ret;
1711
+
1712
+ debug("%s %ld\n", __func__, clk->id);
1713
+ switch (clk->id) {
1714
+ case SCLK_SDMMC_SAMPLE:
1715
+ ret = rk3528_mmc_get_phase(clk);
1716
+ break;
1717
+ default:
1718
+ return -ENOENT;
1719
+ }
1720
+
1721
+ return ret;
1722
+}
1723
+
1724
+static int rk3528_grfclk_set_phase(struct clk *clk, int degrees)
1725
+{
1726
+ int ret;
1727
+
1728
+ debug("%s %ld\n", __func__, clk->id);
1729
+ switch (clk->id) {
1730
+ case SCLK_SDMMC_SAMPLE:
1731
+ ret = rk3528_mmc_set_phase(clk, degrees);
1732
+ break;
1733
+ default:
1734
+ return -ENOENT;
1735
+ }
1736
+
1737
+ return ret;
1738
+}
1739
+
1740
+static struct clk_ops rk3528_grfclk_ops = {
1741
+ .get_rate = rk3528_grfclk_get_rate,
1742
+ .get_phase = rk3528_grfclk_get_phase,
1743
+ .set_phase = rk3528_grfclk_set_phase,
1744
+};
1745
+
1746
+#ifndef CONFIG_SPL_BUILD
1747
+/**
1748
+ * soc_clk_dump() - Print clock frequencies
1749
+ * Returns zero on success
1750
+ *
1751
+ * Implementation for the clk dump command.
1752
+ */
1753
+int soc_clk_dump(void)
1754
+{
1755
+ const struct rk3528_clk_info *clk_dump;
1756
+ struct rk3528_clk_priv *priv;
1757
+ struct udevice *cru_dev;
1758
+ struct clk clk;
1759
+ ulong clk_count = ARRAY_SIZE(clks_dump);
1760
+ ulong rate;
1761
+ int i, ret;
1762
+
1763
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
1764
+ DM_GET_DRIVER(rockchip_rk3528_cru),
1765
+ &cru_dev);
1766
+ if (ret) {
1767
+ printf("%s failed to get cru device\n", __func__);
1768
+ return ret;
1769
+ }
1770
+
1771
+ priv = dev_get_priv(cru_dev);
1772
+ printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n",
1773
+ priv->sync_kernel ? "sync kernel" : "uboot",
1774
+ priv->armclk_enter_hz / 1000,
1775
+ priv->armclk_init_hz / 1000,
1776
+ priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0,
1777
+ priv->set_armclk_rate ? " KHz" : "N/A");
1778
+ for (i = 0; i < clk_count; i++) {
1779
+ clk_dump = &clks_dump[i];
1780
+ if (clk_dump->name) {
1781
+ clk.id = clk_dump->id;
1782
+ ret = clk_request(cru_dev, &clk);
1783
+ if (ret < 0)
1784
+ return ret;
1785
+
1786
+ rate = clk_get_rate(&clk);
1787
+ clk_free(&clk);
1788
+ if (i == 0) {
1789
+ if (rate < 0)
1790
+ printf(" %s %s\n", clk_dump->name,
1791
+ "unknown");
1792
+ else
1793
+ printf(" %s %lu KHz\n", clk_dump->name,
1794
+ rate / 1000);
1795
+ } else {
1796
+ if (rate < 0)
1797
+ printf(" %s %s\n", clk_dump->name,
1798
+ "unknown");
1799
+ else
1800
+ printf(" %s %lu KHz\n", clk_dump->name,
1801
+ rate / 1000);
1802
+ }
1803
+ }
1804
+ }
1805
+
1806
+ return 0;
1807
+}
1808
+#endif
1809
+
1810
+static int rk3528_grfclk_probe(struct udevice *dev)
1811
+{
1812
+ struct rk3528_grf_clk_priv *priv = dev_get_priv(dev);
1813
+
1814
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1815
+ if (IS_ERR(priv->grf))
1816
+ return PTR_ERR(priv->grf);
1817
+
1818
+ return 0;
1819
+}
1820
+
1821
+static const struct udevice_id rk3528_grf_cru_ids[] = {
1822
+ { .compatible = "rockchip,rk3528-grf-cru" },
1823
+ { }
1824
+};
1825
+
1826
+U_BOOT_DRIVER(rockchip_rk3528_grf_cru) = {
1827
+ .name = "rockchip_rk3528_grf_cru",
1828
+ .id = UCLASS_CLK,
1829
+ .of_match = rk3528_grf_cru_ids,
1830
+ .priv_auto_alloc_size = sizeof(struct rk3528_grf_clk_priv),
1831
+ .ops = &rk3528_grfclk_ops,
1832
+ .probe = rk3528_grfclk_probe,
1833
+};
1834
+
1835
+static int rk3528_clk_init(struct rk3528_clk_priv *priv)
1836
+{
1837
+ int ret;
1838
+
1839
+ priv->sync_kernel = false;
1840
+
1841
+#ifdef CONFIG_SPL_BUILD
1842
+ /*
1843
+ * BOOTROM:
1844
+ * CPU 1902/2(postdiv1)=546M
1845
+ * CPLL 996/2(postdiv1)=498M
1846
+ * GPLL 1188/2(postdiv1)=594M
1847
+ * |-- clk_matrix_200m_src_div=1 => rate: 300M
1848
+ * |-- clk_matrix_300m_src_div=2 => rate: 200M
1849
+ *
1850
+ * Avoid overclocking when change GPLL rate:
1851
+ * Change clk_matrix_200m_src_div to 5.
1852
+ * Change clk_matrix_300m_src_div to 3.
1853
+ */
1854
+ writel(0x01200120, &priv->cru->clksel_con[1]);
1855
+ writel(0x00030003, &priv->cru->clksel_con[2]);
1856
+
1857
+ if (!priv->armclk_enter_hz) {
1858
+ priv->armclk_enter_hz =
1859
+ rockchip_pll_get_rate(&rk3528_pll_clks[APLL],
1860
+ priv->cru, APLL);
1861
+ priv->armclk_init_hz = priv->armclk_enter_hz;
1862
+ }
1863
+
1864
+ if (priv->armclk_init_hz != APLL_HZ) {
1865
+ ret = rk3528_armclk_set_clk(priv, APLL_HZ);
1866
+ if (!ret)
1867
+ priv->armclk_init_hz = APLL_HZ;
1868
+ }
1869
+#else
1870
+ if (!priv->armclk_enter_hz) {
1871
+ struct clk clk;
1872
+
1873
+ ret = rockchip_get_scmi_clk(&clk.dev);
1874
+ if (ret) {
1875
+ printf("Failed to get scmi clk dev\n");
1876
+ return ret;
1877
+ }
1878
+
1879
+ clk.id = SCMI_CLK_CPU;
1880
+ ret = clk_set_rate(&clk, CPU_PVTPLL_HZ);
1881
+ if (ret < 0) {
1882
+ printf("Failed to set scmi cpu %dhz\n", CPU_PVTPLL_HZ);
1883
+ return ret;
1884
+ } else {
1885
+ priv->armclk_enter_hz =
1886
+ rockchip_pll_get_rate(&rk3528_pll_clks[APLL],
1887
+ priv->cru, APLL);
1888
+ priv->armclk_init_hz = CPU_PVTPLL_HZ;
1889
+ }
1890
+ }
1891
+#endif
1892
+ if (priv->cpll_hz != CPLL_HZ) {
1893
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru,
1894
+ CPLL, CPLL_HZ);
1895
+ if (!ret)
1896
+ priv->cpll_hz = CPLL_HZ;
1897
+ }
1898
+
1899
+ if (priv->gpll_hz != GPLL_HZ) {
1900
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru,
1901
+ GPLL, GPLL_HZ);
1902
+ if (!ret)
1903
+ priv->gpll_hz = GPLL_HZ;
1904
+ }
1905
+
1906
+ if (priv->ppll_hz != PPLL_HZ) {
1907
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru,
1908
+ PPLL, PPLL_HZ);
1909
+ if (!ret)
1910
+ priv->ppll_hz = PPLL_HZ;
1911
+ }
1912
+
1913
+#ifdef CONFIG_SPL_BUILD
1914
+ /* Init to override bootrom config */
1915
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_50M_SRC, 50000000);
1916
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_100M_SRC, 100000000);
1917
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_150M_SRC, 150000000);
1918
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_200M_SRC, 200000000);
1919
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_250M_SRC, 250000000);
1920
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_300M_SRC, 300000000);
1921
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_339M_SRC, 340000000);
1922
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_400M_SRC, 400000000);
1923
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_500M_SRC, 500000000);
1924
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_600M_SRC, 600000000);
1925
+ rk3528_cgpll_matrix_set_rate(priv, ACLK_BUS_VOPGL_BIU, 500000000);
1926
+
1927
+ /* The default rate is 100Mhz, it's not friendly for remote IR module */
1928
+ rk3528_pwm_set_clk(priv, CLK_PWM0, 24000000);
1929
+ rk3528_pwm_set_clk(priv, CLK_PWM1, 24000000);
1930
+#endif
1931
+ return 0;
1932
+}
1933
+
1934
+static int rk3528_clk_probe(struct udevice *dev)
1935
+{
1936
+ struct rk3528_clk_priv *priv = dev_get_priv(dev);
1937
+ int ret;
1938
+
1939
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1940
+ if (IS_ERR(priv->grf))
1941
+ return PTR_ERR(priv->grf);
1942
+
1943
+ ret = rk3528_clk_init(priv);
1944
+ if (ret)
1945
+ return ret;
1946
+
1947
+ /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
1948
+ ret = clk_set_defaults(dev);
1949
+ if (ret)
1950
+ debug("%s clk_set_defaults failed %d\n", __func__, ret);
1951
+ else
1952
+ priv->sync_kernel = true;
1953
+
1954
+ return 0;
1955
+}
1956
+
1957
+static int rk3528_clk_ofdata_to_platdata(struct udevice *dev)
1958
+{
1959
+ struct rk3528_clk_priv *priv = dev_get_priv(dev);
1960
+
1961
+ priv->cru = dev_read_addr_ptr(dev);
1962
+
1963
+ return 0;
1964
+}
1965
+
1966
+static int rk3528_clk_bind(struct udevice *dev)
1967
+{
1968
+ struct udevice *sys_child, *sf_child;
1969
+ struct softreset_reg *sf_priv;
1970
+ struct sysreset_reg *priv;
1971
+ int ret;
1972
+
1973
+ /* The reset driver does not have a device node, so bind it here */
1974
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1975
+ &sys_child);
1976
+ if (ret) {
1977
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
1978
+ } else {
1979
+ priv = malloc(sizeof(struct sysreset_reg));
1980
+ priv->glb_srst_fst_value = offsetof(struct rk3528_cru,
1981
+ glb_srst_fst);
1982
+ priv->glb_srst_snd_value = offsetof(struct rk3528_cru,
1983
+ glb_srst_snd);
1984
+ sys_child->priv = priv;
1985
+ }
1986
+
1987
+ ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset",
1988
+ dev_ofnode(dev), &sf_child);
1989
+ if (ret) {
1990
+ debug("Warning: No rockchip reset driver: ret=%d\n", ret);
1991
+ } else {
1992
+ sf_priv = malloc(sizeof(struct softreset_reg));
1993
+ sf_priv->sf_reset_offset = offsetof(struct rk3528_cru,
1994
+ softrst_con[0]);
1995
+ sf_priv->sf_reset_num = 47;
1996
+ sf_child->priv = sf_priv;
1997
+ }
1998
+
1999
+ return 0;
2000
+}
2001
+
2002
+static const struct udevice_id rk3528_clk_ids[] = {
2003
+ { .compatible = "rockchip,rk3528-cru" },
2004
+ { }
2005
+};
2006
+
2007
+U_BOOT_DRIVER(rockchip_rk3528_cru) = {
2008
+ .name = "rockchip_rk3528_cru",
2009
+ .id = UCLASS_CLK,
2010
+ .of_match = rk3528_clk_ids,
2011
+ .priv_auto_alloc_size = sizeof(struct rk3528_clk_priv),
2012
+ .ofdata_to_platdata = rk3528_clk_ofdata_to_platdata,
2013
+ .ops = &rk3528_clk_ops,
2014
+ .bind = rk3528_clk_bind,
2015
+ .probe = rk3528_clk_probe,
2016
+};
2017
+
2018
+/* spl scmi clk */
2019
+#ifdef CONFIG_SPL_BUILD
2020
+
2021
+static ulong rk3528_crypto_get_rate(struct rk3528_clk_priv *priv, struct clk *clk)
2022
+{
2023
+ struct rk3528_cru *cru = priv->cru;
2024
+ u32 id, sel, con, mask, shift;
2025
+ ulong rate;
2026
+
2027
+ switch (clk->id) {
2028
+ case SCMI_CORE_CRYPTO:
2029
+ id = 43;
2030
+ mask = CLK_CORE_CRYPTO_SEL_MASK;
2031
+ shift = CLK_CORE_CRYPTO_SEL_SHIFT;
2032
+ break;
2033
+
2034
+ case SCMI_PKA_CRYPTO:
2035
+ id = 44;
2036
+ mask = CLK_PKA_CRYPTO_SEL_MASK;
2037
+ shift = CLK_PKA_CRYPTO_SEL_SHIFT;
2038
+ break;
2039
+
2040
+ default:
2041
+ return -ENOENT;
2042
+ }
2043
+
2044
+ con = readl(&cru->clksel_con[id]);
2045
+ sel = (con & mask) >> shift;
2046
+ if (sel == CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC)
2047
+ rate = 300 * MHz;
2048
+ else if (sel == CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC)
2049
+ rate = 200 * MHz;
2050
+ else if (sel == CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC)
2051
+ rate = 100 * MHz;
2052
+ else
2053
+ rate = OSC_HZ;
2054
+
2055
+ return rate;
2056
+}
2057
+
2058
+static ulong rk3528_crypto_set_rate(struct rk3528_clk_priv *priv,
2059
+ struct clk *clk, ulong rate)
2060
+{
2061
+ struct rk3528_cru *cru = priv->cru;
2062
+ u32 id, sel, mask, shift;
2063
+
2064
+ if (rate == 300 * MHz)
2065
+ sel = CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC;
2066
+ else if (rate == 200 * MHz)
2067
+ sel = CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC;
2068
+ else if (rate == 100 * MHz)
2069
+ sel = CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC;
2070
+ else
2071
+ sel = CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC;
2072
+
2073
+ switch (clk->id) {
2074
+ case SCMI_CORE_CRYPTO:
2075
+ id = 43;
2076
+ mask = CLK_CORE_CRYPTO_SEL_MASK;
2077
+ shift = CLK_CORE_CRYPTO_SEL_SHIFT;
2078
+ break;
2079
+
2080
+ case SCMI_PKA_CRYPTO:
2081
+ id = 44;
2082
+ mask = CLK_PKA_CRYPTO_SEL_MASK;
2083
+ shift = CLK_PKA_CRYPTO_SEL_SHIFT;
2084
+ break;
2085
+
2086
+ default:
2087
+ return -ENOENT;
2088
+ }
2089
+
2090
+ rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
2091
+
2092
+ return rk3528_crypto_get_rate(priv, clk);
2093
+}
2094
+
2095
+static ulong rk3528_clk_scmi_get_rate(struct clk *clk)
2096
+{
2097
+ struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
2098
+
2099
+ switch (clk->id) {
2100
+ case SCMI_CORE_CRYPTO:
2101
+ case SCMI_PKA_CRYPTO:
2102
+ return rk3528_crypto_get_rate(priv, clk);
2103
+ default:
2104
+ return -ENOENT;
2105
+ }
2106
+};
2107
+
2108
+static ulong rk3528_clk_scmi_set_rate(struct clk *clk, ulong rate)
2109
+{
2110
+ struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
2111
+
2112
+ switch (clk->id) {
2113
+ case SCMI_CORE_CRYPTO:
2114
+ case SCMI_PKA_CRYPTO:
2115
+ return rk3528_crypto_set_rate(priv, clk, rate);
2116
+ default:
2117
+ return -ENOENT;
2118
+ }
2119
+
2120
+ return 0;
2121
+};
2122
+
2123
+static int rk3528_scmi_clk_ofdata_to_platdata(struct udevice *dev)
2124
+{
2125
+ struct rk3528_clk_priv *priv = dev_get_priv(dev);
2126
+
2127
+ priv->cru = (struct rk3528_cru *)0xff4a0000;
2128
+
2129
+ return 0;
2130
+}
2131
+
2132
+/* A fake scmi driver for SPL/TPL where smccc agent is not available. */
2133
+static const struct clk_ops scmi_clk_ops = {
2134
+ .get_rate = rk3528_clk_scmi_get_rate,
2135
+ .set_rate = rk3528_clk_scmi_set_rate,
2136
+};
2137
+
2138
+U_BOOT_DRIVER(scmi_clock) = {
2139
+ .name = "scmi_clk",
2140
+ .id = UCLASS_CLK,
2141
+ .ops = &scmi_clk_ops,
2142
+ .priv_auto_alloc_size = sizeof(struct rk3528_clk_priv),
2143
+ .ofdata_to_platdata = rk3528_scmi_clk_ofdata_to_platdata,
2144
+};
2145
+#endif
u-boot/drivers/clk/rockchip/clk_rk3562.c
....@@ -0,0 +1,2046 @@
1
+// SPDX-License-Identifier: GPL-2.0
2
+/*
3
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd
4
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
5
+ */
6
+
7
+#include <common.h>
8
+#include <clk-uclass.h>
9
+#include <dm.h>
10
+#include <syscon.h>
11
+#include <asm/arch/clock.h>
12
+#include <asm/arch/cru_rk3562.h>
13
+#include <asm/arch/hardware.h>
14
+#include <asm/io.h>
15
+#include <dm/lists.h>
16
+#include <dt-bindings/clock/rk3562-cru.h>
17
+
18
+DECLARE_GLOBAL_DATA_PTR;
19
+
20
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
21
+
22
+static struct rockchip_pll_rate_table rk3562_pll_rates[] = {
23
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
24
+ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
25
+ RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
26
+ RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
27
+ RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
28
+ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
29
+ RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
30
+ RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
31
+ RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
32
+ RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
33
+ RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
34
+ RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
35
+ RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
36
+ RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
37
+ RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
38
+ RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
39
+ RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
40
+ RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
41
+ { /* sentinel */ },
42
+};
43
+
44
+static struct rockchip_pll_clock rk3562_pll_clks[] = {
45
+ [APLL] = PLL(pll_rk3328, PLL_APLL, RK3562_PLL_CON(0),
46
+ RK3562_MODE_CON, 0, 10, 0, rk3562_pll_rates),
47
+ [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3562_PLL_CON(24),
48
+ RK3562_MODE_CON, 2, 10, 0, rk3562_pll_rates),
49
+ [VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3562_PLL_CON(32),
50
+ RK3562_MODE_CON, 6, 10, 0, rk3562_pll_rates),
51
+ [HPLL] = PLL(pll_rk3328, PLL_HPLL, RK3562_PLL_CON(40),
52
+ RK3562_MODE_CON, 8, 10, 0, rk3562_pll_rates),
53
+ [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3562_PMU1_PLL_CON(0),
54
+ RK3562_PMU1_MODE_CON, 0, 10, 0, rk3562_pll_rates),
55
+ [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3562_SUBDDR_PLL_CON(0),
56
+ RK3562_SUBDDR_MODE_CON, 0, 10, 0, NULL),
57
+};
58
+
59
+#define RK3562_CPUCLK_RATE(_rate, _aclk_m_core, _pclk_dbg) \
60
+{ \
61
+ .rate = _rate##U, \
62
+ .aclk_div = _aclk_m_core, \
63
+ .pclk_div = _pclk_dbg, \
64
+}
65
+
66
+static struct rockchip_cpu_rate_table rk3562_cpu_rates[] = {
67
+ RK3562_CPUCLK_RATE(1416000000, 1, 8),
68
+ RK3562_CPUCLK_RATE(1296000000, 1, 8),
69
+ RK3562_CPUCLK_RATE(1200000000, 1, 8),
70
+ RK3562_CPUCLK_RATE(1104000000, 1, 8),
71
+ RK3562_CPUCLK_RATE(1008000000, 1, 8),
72
+ RK3562_CPUCLK_RATE(912000000, 1, 6),
73
+ RK3562_CPUCLK_RATE(816000000, 1, 6),
74
+ RK3562_CPUCLK_RATE(600000000, 1, 6),
75
+ RK3562_CPUCLK_RATE(408000000, 1, 4),
76
+ { /* sentinel */ },
77
+};
78
+
79
+#ifndef CONFIG_SPL_BUILD
80
+#define RK3562_CLK_DUMP(_id, _name) \
81
+{ \
82
+ .id = _id, \
83
+ .name = _name, \
84
+}
85
+
86
+static const struct rk3562_clk_info clks_dump[] = {
87
+ RK3562_CLK_DUMP(PLL_APLL, "apll"),
88
+ RK3562_CLK_DUMP(PLL_GPLL, "gpll"),
89
+ RK3562_CLK_DUMP(PLL_VPLL, "vpll"),
90
+ RK3562_CLK_DUMP(PLL_HPLL, "hpll"),
91
+ RK3562_CLK_DUMP(PLL_CPLL, "cpll"),
92
+ RK3562_CLK_DUMP(PLL_DPLL, "dpll"),
93
+ RK3562_CLK_DUMP(ACLK_BUS, "aclk_bus"),
94
+ RK3562_CLK_DUMP(HCLK_BUS, "hclk_bus"),
95
+ RK3562_CLK_DUMP(PCLK_BUS, "pclk_bus"),
96
+ RK3562_CLK_DUMP(ACLK_PERI, "aclk_peri"),
97
+ RK3562_CLK_DUMP(HCLK_PERI, "hclk_peri"),
98
+ RK3562_CLK_DUMP(PCLK_PERI, "pclk_peri"),
99
+};
100
+#endif
101
+
102
+/*
103
+ *
104
+ * rational_best_approximation(31415, 10000,
105
+ * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
106
+ *
107
+ * you may look at given_numerator as a fixed point number,
108
+ * with the fractional part size described in given_denominator.
109
+ *
110
+ * for theoretical background, see:
111
+ * http://en.wikipedia.org/wiki/Continued_fraction
112
+ */
113
+static void rational_best_approximation(unsigned long given_numerator,
114
+ unsigned long given_denominator,
115
+ unsigned long max_numerator,
116
+ unsigned long max_denominator,
117
+ unsigned long *best_numerator,
118
+ unsigned long *best_denominator)
119
+{
120
+ unsigned long n, d, n0, d0, n1, d1;
121
+
122
+ n = given_numerator;
123
+ d = given_denominator;
124
+ n0 = 0;
125
+ d1 = 0;
126
+ n1 = 1;
127
+ d0 = 1;
128
+ for (;;) {
129
+ unsigned long t, a;
130
+
131
+ if (n1 > max_numerator || d1 > max_denominator) {
132
+ n1 = n0;
133
+ d1 = d0;
134
+ break;
135
+ }
136
+ if (d == 0)
137
+ break;
138
+ t = d;
139
+ a = n / d;
140
+ d = n % d;
141
+ n = t;
142
+ t = n0 + a * n1;
143
+ n0 = n1;
144
+ n1 = t;
145
+ t = d0 + a * d1;
146
+ d0 = d1;
147
+ d1 = t;
148
+ }
149
+ *best_numerator = n1;
150
+ *best_denominator = d1;
151
+}
152
+
153
+static int rk3562_armclk_set_rate(struct rk3562_clk_priv *priv, ulong new_rate)
154
+{
155
+ const struct rockchip_cpu_rate_table *rate;
156
+ struct rk3562_cru *cru = priv->cru;
157
+ ulong old_rate;
158
+
159
+ rate = rockchip_get_cpu_settings(rk3562_cpu_rates, new_rate);
160
+ if (!rate) {
161
+ printf("%s unsupported rate\n", __func__);
162
+ return -EINVAL;
163
+ }
164
+
165
+ /*
166
+ * set up dependent divisors for DBG and ACLK clocks.
167
+ */
168
+ old_rate = rockchip_pll_get_rate(&rk3562_pll_clks[APLL], priv->cru,
169
+ APLL);
170
+ if (old_rate == new_rate) {
171
+ rk_clrsetreg(&cru->clksel_con[11], ACLK_CORE_PRE_DIV_MASK,
172
+ rate->aclk_div << ACLK_CORE_PRE_DIV_SHIFT);
173
+ rk_clrsetreg(&cru->clksel_con[12], PCLK_DBG_PRE_DIV_MASK,
174
+ rate->pclk_div << PCLK_DBG_PRE_DIV_SHIFT);
175
+ rk_clrsetreg(&cru->clksel_con[10], CLK_CORE_PRE_DIV_MASK, 0);
176
+ } else if (old_rate > new_rate) {
177
+ if (rockchip_pll_set_rate(&rk3562_pll_clks[APLL],
178
+ priv->cru, APLL, new_rate))
179
+ return -EINVAL;
180
+ rk_clrsetreg(&cru->clksel_con[11], ACLK_CORE_PRE_DIV_MASK,
181
+ rate->aclk_div << ACLK_CORE_PRE_DIV_SHIFT);
182
+ rk_clrsetreg(&cru->clksel_con[12], PCLK_DBG_PRE_DIV_MASK,
183
+ rate->pclk_div << PCLK_DBG_PRE_DIV_SHIFT);
184
+ rk_clrsetreg(&cru->clksel_con[10], CLK_CORE_PRE_DIV_MASK, 0);
185
+ } else if (old_rate < new_rate) {
186
+ rk_clrsetreg(&cru->clksel_con[11], ACLK_CORE_PRE_DIV_MASK,
187
+ rate->aclk_div << ACLK_CORE_PRE_DIV_SHIFT);
188
+ rk_clrsetreg(&cru->clksel_con[12], PCLK_DBG_PRE_DIV_MASK,
189
+ rate->pclk_div << PCLK_DBG_PRE_DIV_SHIFT);
190
+ rk_clrsetreg(&cru->clksel_con[10], CLK_CORE_PRE_DIV_MASK, 0);
191
+
192
+ if (rockchip_pll_set_rate(&rk3562_pll_clks[APLL],
193
+ priv->cru, APLL, new_rate))
194
+ return -EINVAL;
195
+ }
196
+
197
+ return 0;
198
+}
199
+
200
+static ulong rk3562_bus_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
201
+{
202
+ struct rk3562_cru *cru = priv->cru;
203
+ u32 sel, con, div;
204
+ ulong rate;
205
+
206
+ switch (clk_id) {
207
+ case ACLK_BUS:
208
+ con = readl(&cru->clksel_con[40]);
209
+ sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT;
210
+ div = (con & ACLK_BUS_DIV_MASK) >> ACLK_BUS_DIV_SHIFT;
211
+ break;
212
+ case HCLK_BUS:
213
+ con = readl(&cru->clksel_con[40]);
214
+ sel = (con & HCLK_BUS_SEL_MASK) >> HCLK_BUS_SEL_SHIFT;
215
+ div = (con & HCLK_BUS_DIV_MASK) >> HCLK_BUS_DIV_SHIFT;
216
+ break;
217
+ case PCLK_BUS:
218
+ con = readl(&cru->clksel_con[41]);
219
+ sel = (con & PCLK_BUS_SEL_MASK) >> PCLK_BUS_SEL_SHIFT;
220
+ div = (con & PCLK_BUS_DIV_MASK) >> PCLK_BUS_DIV_SHIFT;
221
+ break;
222
+ default:
223
+ return -ENOENT;
224
+ }
225
+
226
+ if (sel == ACLK_BUS_SEL_CPLL)
227
+ rate = priv->cpll_hz;
228
+ else
229
+ rate = priv->gpll_hz;
230
+
231
+ return DIV_TO_RATE(rate, div);
232
+}
233
+
234
+static ulong rk3562_bus_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
235
+ ulong rate)
236
+{
237
+ struct rk3562_cru *cru = priv->cru;
238
+ u32 sel, div;
239
+
240
+ if (priv->cpll_hz % rate == 0) {
241
+ sel = ACLK_BUS_SEL_CPLL;
242
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
243
+ } else {
244
+ sel= ACLK_BUS_SEL_GPLL;
245
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
246
+ }
247
+
248
+ switch (clk_id) {
249
+ case ACLK_BUS:
250
+ rk_clrsetreg(&cru->clksel_con[40],
251
+ ACLK_BUS_SEL_MASK | ACLK_BUS_DIV_MASK,
252
+ (sel << ACLK_BUS_SEL_SHIFT) |
253
+ ((div - 1) << ACLK_BUS_DIV_SHIFT));
254
+ break;
255
+ case HCLK_BUS:
256
+ rk_clrsetreg(&cru->clksel_con[40],
257
+ HCLK_BUS_SEL_MASK | HCLK_BUS_DIV_MASK,
258
+ (sel << HCLK_BUS_SEL_SHIFT) |
259
+ ((div - 1) << HCLK_BUS_DIV_SHIFT));
260
+ break;
261
+ case PCLK_BUS:
262
+ rk_clrsetreg(&cru->clksel_con[41],
263
+ PCLK_BUS_SEL_MASK | PCLK_BUS_DIV_MASK,
264
+ (sel << PCLK_BUS_SEL_SHIFT) |
265
+ ((div - 1) << PCLK_BUS_DIV_SHIFT));
266
+ break;
267
+ default:
268
+ return -ENOENT;
269
+ }
270
+
271
+ return rk3562_bus_get_rate(priv, clk_id);
272
+}
273
+
274
+static ulong rk3562_peri_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
275
+{
276
+ struct rk3562_cru *cru = priv->cru;
277
+ u32 sel, con, div;
278
+ ulong rate;
279
+
280
+ switch (clk_id) {
281
+ case ACLK_PERI:
282
+ con = readl(&cru->periclksel_con[0]);
283
+ sel = (con & ACLK_PERI_SEL_MASK) >> ACLK_PERI_SEL_SHIFT;
284
+ div = (con & ACLK_PERI_DIV_MASK) >> ACLK_PERI_DIV_SHIFT;
285
+ break;
286
+ case HCLK_PERI:
287
+ con = readl(&cru->periclksel_con[0]);
288
+ sel = (con & HCLK_PERI_SEL_MASK) >> HCLK_PERI_SEL_SHIFT;
289
+ div = (con & HCLK_PERI_DIV_MASK) >> HCLK_PERI_DIV_SHIFT;
290
+ break;
291
+ case PCLK_PERI:
292
+ con = readl(&cru->periclksel_con[1]);
293
+ sel = (con & PCLK_PERI_SEL_MASK) >> PCLK_PERI_SEL_SHIFT;
294
+ div = (con & PCLK_PERI_DIV_MASK) >> PCLK_PERI_DIV_SHIFT;
295
+ break;
296
+ default:
297
+ return -ENOENT;
298
+ }
299
+
300
+ if (sel == ACLK_PERI_SEL_CPLL)
301
+ rate = priv->cpll_hz;
302
+ else
303
+ rate = priv->gpll_hz;
304
+
305
+ return DIV_TO_RATE(rate, div);
306
+}
307
+
308
+static ulong rk3562_peri_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
309
+ ulong rate)
310
+{
311
+ struct rk3562_cru *cru = priv->cru;
312
+ u32 sel, div;
313
+
314
+ if (priv->cpll_hz % rate == 0) {
315
+ sel = ACLK_PERI_SEL_CPLL;
316
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
317
+ } else {
318
+ sel= ACLK_PERI_SEL_GPLL;
319
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
320
+ }
321
+
322
+ switch (clk_id) {
323
+ case ACLK_PERI:
324
+ rk_clrsetreg(&cru->periclksel_con[0],
325
+ ACLK_PERI_SEL_MASK | ACLK_PERI_DIV_MASK,
326
+ (sel << ACLK_PERI_SEL_SHIFT) |
327
+ ((div - 1) << ACLK_PERI_DIV_SHIFT));
328
+ break;
329
+ case HCLK_PERI:
330
+ rk_clrsetreg(&cru->periclksel_con[0],
331
+ HCLK_PERI_SEL_MASK | HCLK_PERI_DIV_MASK,
332
+ (sel << HCLK_PERI_SEL_SHIFT) |
333
+ ((div - 1) << HCLK_PERI_DIV_SHIFT));
334
+ break;
335
+ case PCLK_PERI:
336
+ rk_clrsetreg(&cru->periclksel_con[1],
337
+ PCLK_PERI_SEL_MASK | PCLK_PERI_DIV_MASK,
338
+ (sel << PCLK_PERI_SEL_SHIFT) |
339
+ ((div - 1) << PCLK_PERI_DIV_SHIFT));
340
+ break;
341
+ default:
342
+ return -ENOENT;
343
+ }
344
+
345
+ return rk3562_peri_get_rate(priv, clk_id);
346
+}
347
+
348
+static ulong rk3562_i2c_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
349
+{
350
+ struct rk3562_cru *cru = priv->cru;
351
+ u32 sel, con, div;
352
+ ulong rate;
353
+
354
+ switch (clk_id) {
355
+ case CLK_PMU0_I2C0:
356
+ con = readl(&cru->pmu0clksel_con[3]);
357
+ sel = (con & CLK_PMU0_I2C0_SEL_MASK) >> CLK_PMU0_I2C0_SEL_SHIFT;
358
+ if (sel == CLK_PMU0_I2C0_SEL_200M)
359
+ rate = 200 * MHz;
360
+ else if (sel == CLK_PMU0_I2C0_SEL_24M)
361
+ rate = OSC_HZ;
362
+ else
363
+ rate = 32768;
364
+ div = (con & CLK_PMU0_I2C0_DIV_MASK) >> CLK_PMU0_I2C0_DIV_SHIFT;
365
+
366
+ return DIV_TO_RATE(rate, div);
367
+ case CLK_I2C:
368
+ case CLK_I2C1:
369
+ case CLK_I2C2:
370
+ case CLK_I2C3:
371
+ case CLK_I2C4:
372
+ case CLK_I2C5:
373
+ con = readl(&cru->clksel_con[41]);
374
+ sel = (con & CLK_I2C_SEL_MASK) >> CLK_I2C_SEL_SHIFT;
375
+ if (sel == CLK_I2C_SEL_200M)
376
+ rate = 200 * MHz;
377
+ else if (sel == CLK_I2C_SEL_100M)
378
+ rate = 100 * MHz;
379
+ else if (sel == CLK_I2C_SEL_50M)
380
+ rate = 50 * MHz;
381
+ else
382
+ rate = OSC_HZ;
383
+ break;
384
+ default:
385
+ return -ENOENT;
386
+ }
387
+
388
+ return rate;
389
+}
390
+
391
+static ulong rk3562_i2c_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
392
+ ulong rate)
393
+{
394
+ struct rk3562_cru *cru = priv->cru;
395
+ u32 sel, div;
396
+
397
+ switch (clk_id) {
398
+ case CLK_PMU0_I2C0:
399
+ if (rate == 200 * MHz) {
400
+ sel = CLK_PMU0_I2C0_SEL_200M;
401
+ div = 1;
402
+ } else if (rate == OSC_HZ) {
403
+ sel = CLK_PMU0_I2C0_SEL_24M;
404
+ div = 1;
405
+ } else if (rate == 32768) {
406
+ sel = CLK_PMU0_I2C0_SEL_32K;
407
+ div = 1;
408
+ } else {
409
+ sel = CLK_PMU0_I2C0_SEL_200M;
410
+ div = DIV_ROUND_UP(200 * MHz, rate);
411
+ assert(div - 1 <= 31);
412
+ }
413
+ rk_clrsetreg(&cru->pmu0clksel_con[3], CLK_PMU0_I2C0_DIV_MASK,
414
+ (div - 1) << CLK_PMU0_I2C0_DIV_SHIFT);
415
+ rk_clrsetreg(&cru->pmu0clksel_con[3], CLK_PMU0_I2C0_SEL_MASK,
416
+ sel << CLK_PMU0_I2C0_SEL_SHIFT);
417
+ break;
418
+ case CLK_I2C:
419
+ case CLK_I2C2:
420
+ case CLK_I2C3:
421
+ case CLK_I2C4:
422
+ case CLK_I2C5:
423
+ if (rate == 200 * MHz)
424
+ sel = CLK_I2C_SEL_200M;
425
+ else if (rate == 100 * MHz)
426
+ sel = CLK_I2C_SEL_100M;
427
+ else if (rate == 50 * MHz)
428
+ sel = CLK_I2C_SEL_50M;
429
+ else
430
+ sel = CLK_I2C_SEL_24M;
431
+ rk_clrsetreg(&cru->clksel_con[41], CLK_I2C_SEL_MASK,
432
+ sel << CLK_I2C_SEL_SHIFT);
433
+ break;
434
+ default:
435
+ return -ENOENT;
436
+ }
437
+
438
+
439
+ return rk3562_i2c_get_rate(priv, clk_id);
440
+}
441
+
442
+static ulong rk3562_uart_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
443
+{
444
+ struct rk3562_cru *cru = priv->cru;
445
+ u32 reg, con, fracdiv, div, src, p_src, p_rate;
446
+ unsigned long m, n;
447
+
448
+ switch (clk_id) {
449
+ case SCLK_PMU1_UART0:
450
+ con = readl(&cru->pmu1clksel_con[2]);
451
+ src = (con & CLK_PMU1_UART0_SEL_MASK) >>
452
+ CLK_PMU1_UART0_SEL_SHIFT;
453
+ div = (con & CLK_PMU1_UART0_SRC_DIV_MASK) >>
454
+ CLK_PMU1_UART0_SRC_DIV_SHIFT;
455
+ if (src == CLK_UART_SEL_SRC) {
456
+ return DIV_TO_RATE(priv->cpll_hz, div);
457
+ } else if (src == CLK_UART_SEL_FRAC) {
458
+ fracdiv = readl(&cru->pmu1clksel_con[3]);
459
+ n = fracdiv & CLK_UART_FRAC_NUMERATOR_MASK;
460
+ n >>= CLK_UART_FRAC_NUMERATOR_SHIFT;
461
+ m = fracdiv & CLK_UART_FRAC_DENOMINATOR_MASK;
462
+ m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT;
463
+ return DIV_TO_RATE(priv->cpll_hz, div) * n / m;
464
+ } else {
465
+ return OSC_HZ;
466
+ }
467
+ case SCLK_UART1:
468
+ reg = 21;
469
+ break;
470
+ case SCLK_UART2:
471
+ reg = 23;
472
+ break;
473
+ case SCLK_UART3:
474
+ reg = 25;
475
+ break;
476
+ case SCLK_UART4:
477
+ reg = 27;
478
+ break;
479
+ case SCLK_UART5:
480
+ reg = 29;
481
+ break;
482
+ case SCLK_UART6:
483
+ reg = 31;
484
+ break;
485
+ case SCLK_UART7:
486
+ reg = 33;
487
+ break;
488
+ case SCLK_UART8:
489
+ reg = 35;
490
+ break;
491
+ case SCLK_UART9:
492
+ reg = 37;
493
+ break;
494
+ default:
495
+ return -ENOENT;
496
+ }
497
+ con = readl(&cru->periclksel_con[reg]);
498
+ src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT;
499
+ div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT;
500
+ p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT;
501
+ if (p_src == CLK_UART_SRC_SEL_GPLL)
502
+ p_rate = priv->gpll_hz;
503
+ else
504
+ p_rate = priv->cpll_hz;
505
+ if (src == CLK_UART_SEL_SRC) {
506
+ return DIV_TO_RATE(p_rate, div);
507
+ } else if (src == CLK_UART_SEL_FRAC) {
508
+ fracdiv = readl(&cru->periclksel_con[reg + 1]);
509
+ n = fracdiv & CLK_UART_FRAC_NUMERATOR_MASK;
510
+ n >>= CLK_UART_FRAC_NUMERATOR_SHIFT;
511
+ m = fracdiv & CLK_UART_FRAC_DENOMINATOR_MASK;
512
+ m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT;
513
+ return DIV_TO_RATE(p_rate, div) * n / m;
514
+ } else {
515
+ return OSC_HZ;
516
+ }
517
+}
518
+
519
+static ulong rk3562_uart_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
520
+ ulong rate)
521
+{
522
+ struct rk3562_cru *cru = priv->cru;
523
+ u32 reg, clk_src, uart_src, div;
524
+ unsigned long m = 0, n = 0, val;
525
+
526
+ switch (clk_id) {
527
+ case SCLK_PMU1_UART0:
528
+ if (priv->cpll_hz % rate == 0) {
529
+ uart_src = CLK_UART_SEL_SRC;
530
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
531
+ } else if (rate == OSC_HZ) {
532
+ uart_src = CLK_UART_SEL_XIN24M;
533
+ div = 2;
534
+ } else {
535
+ uart_src = CLK_UART_SEL_FRAC;
536
+ div = 2;
537
+ rational_best_approximation(rate, priv->cpll_hz / div,
538
+ GENMASK(16 - 1, 0),
539
+ GENMASK(16 - 1, 0),
540
+ &n, &m);
541
+ }
542
+
543
+ rk_clrsetreg(&cru->pmu1clksel_con[2],
544
+ CLK_PMU1_UART0_SEL_MASK |
545
+ CLK_PMU1_UART0_SRC_DIV_MASK,
546
+ (uart_src << CLK_PMU1_UART0_SEL_SHIFT) |
547
+ ((div - 1) << CLK_PMU1_UART0_SRC_DIV_SHIFT));
548
+ if (m && n) {
549
+ val = n << CLK_UART_FRAC_NUMERATOR_SHIFT | m;
550
+ writel(val, &cru->pmu1clksel_con[3]);
551
+ }
552
+
553
+ return rk3562_uart_get_rate(priv, clk_id);
554
+ case SCLK_UART1:
555
+ reg = 21;
556
+ break;
557
+ case SCLK_UART2:
558
+ reg = 23;
559
+ break;
560
+ case SCLK_UART3:
561
+ reg = 25;
562
+ break;
563
+ case SCLK_UART4:
564
+ reg = 27;
565
+ break;
566
+ case SCLK_UART5:
567
+ reg = 29;
568
+ break;
569
+ case SCLK_UART6:
570
+ reg = 31;
571
+ break;
572
+ case SCLK_UART7:
573
+ reg = 33;
574
+ break;
575
+ case SCLK_UART8:
576
+ reg = 35;
577
+ break;
578
+ case SCLK_UART9:
579
+ reg = 37;
580
+ break;
581
+ default:
582
+ return -ENOENT;
583
+ }
584
+
585
+ if (priv->gpll_hz % rate == 0) {
586
+ clk_src = CLK_UART_SRC_SEL_GPLL;
587
+ uart_src = CLK_UART_SEL_SRC;
588
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
589
+ } else if (priv->cpll_hz % rate == 0) {
590
+ clk_src = CLK_UART_SRC_SEL_CPLL;
591
+ uart_src = CLK_UART_SEL_SRC;
592
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
593
+ } else if (rate == OSC_HZ) {
594
+ clk_src = CLK_UART_SRC_SEL_GPLL;
595
+ uart_src = CLK_UART_SEL_XIN24M;
596
+ div = 2;
597
+ } else {
598
+ clk_src = CLK_UART_SRC_SEL_GPLL;
599
+ uart_src = CLK_UART_SEL_FRAC;
600
+ div = 2;
601
+ rational_best_approximation(rate, priv->gpll_hz / div,
602
+ GENMASK(16 - 1, 0),
603
+ GENMASK(16 - 1, 0),
604
+ &n, &m);
605
+ }
606
+
607
+ rk_clrsetreg(&cru->periclksel_con[reg],
608
+ CLK_UART_SEL_MASK | CLK_UART_SRC_SEL_MASK |
609
+ CLK_UART_SRC_DIV_MASK,
610
+ (clk_src << CLK_UART_SRC_SEL_SHIFT) |
611
+ (uart_src << CLK_UART_SEL_SHIFT) |
612
+ ((div - 1) << CLK_UART_SRC_DIV_SHIFT));
613
+ if (m && n) {
614
+ val = n << CLK_UART_FRAC_NUMERATOR_SHIFT | m;
615
+ writel(val, &cru->periclksel_con[reg + 1]);
616
+ }
617
+
618
+ return rk3562_uart_get_rate(priv, clk_id);
619
+}
620
+
621
+static ulong rk3562_pwm_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
622
+{
623
+ struct rk3562_cru *cru = priv->cru;
624
+ u32 sel, con, div, mask, shift;
625
+ ulong rate;
626
+
627
+ switch (clk_id) {
628
+ case CLK_PMU1_PWM0:
629
+ con = readl(&cru->pmu1clksel_con[4]);
630
+ sel = (con & CLK_PMU1_PWM0_SEL_MASK) >> CLK_PMU1_PWM0_SEL_SHIFT;
631
+ if (sel == CLK_PMU1_PWM0_SEL_200M)
632
+ rate = 200 * MHz;
633
+ else if (sel == CLK_PMU1_PWM0_SEL_24M)
634
+ rate = OSC_HZ;
635
+ else
636
+ rate = 32768;
637
+ div = (con & CLK_PMU1_PWM0_DIV_MASK) >> CLK_PMU1_PWM0_DIV_SHIFT;
638
+
639
+ return DIV_TO_RATE(rate, div);
640
+ case CLK_PWM1_PERI:
641
+ mask = CLK_PWM1_PERI_SEL_MASK;
642
+ shift = CLK_PWM1_PERI_SEL_SHIFT;
643
+ break;
644
+ case CLK_PWM2_PERI:
645
+ mask = CLK_PWM2_PERI_SEL_MASK;
646
+ shift = CLK_PWM2_PERI_SEL_SHIFT;
647
+ break;
648
+ case CLK_PWM3_PERI:
649
+ mask = CLK_PWM3_PERI_SEL_MASK;
650
+ shift = CLK_PWM3_PERI_SEL_SHIFT;
651
+ break;
652
+ default:
653
+ return -ENOENT;
654
+ }
655
+
656
+ con = readl(&cru->periclksel_con[40]);
657
+ sel = (con & mask) >> shift;
658
+ if (sel == CLK_PWM_SEL_100M)
659
+ rate = 100 * MHz;
660
+ else if (sel == CLK_PWM_SEL_50M)
661
+ rate = 50 * MHz;
662
+ else
663
+ rate = OSC_HZ;
664
+
665
+ return rate;
666
+}
667
+
668
+static ulong rk3562_pwm_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
669
+ ulong rate)
670
+{
671
+ struct rk3562_cru *cru = priv->cru;
672
+ u32 sel, div, mask, shift;
673
+
674
+ switch (clk_id) {
675
+ case CLK_PMU1_PWM0:
676
+ if (rate == 200 * MHz) {
677
+ sel = CLK_PMU1_PWM0_SEL_200M;
678
+ div = 1;
679
+ } else if (rate == OSC_HZ) {
680
+ sel = CLK_PMU1_PWM0_SEL_24M;
681
+ div = 1;
682
+ } else if (rate == 32768) {
683
+ sel = CLK_PMU1_PWM0_SEL_32K;
684
+ div = 1;
685
+ } else {
686
+ sel = CLK_PMU1_PWM0_SEL_200M;
687
+ div = DIV_ROUND_UP(200 * MHz, rate);
688
+ assert(div - 1 <= 3);
689
+ }
690
+ rk_clrsetreg(&cru->pmu1clksel_con[4], CLK_PMU1_PWM0_DIV_MASK,
691
+ (div - 1) << CLK_PMU1_PWM0_DIV_SHIFT);
692
+ rk_clrsetreg(&cru->pmu1clksel_con[4], CLK_PMU1_PWM0_SEL_MASK,
693
+ sel << CLK_PMU1_PWM0_SEL_SHIFT);
694
+
695
+ return rk3562_pwm_get_rate(priv, clk_id);
696
+ case CLK_PWM1_PERI:
697
+ mask = CLK_PWM1_PERI_SEL_MASK;
698
+ shift = CLK_PWM1_PERI_SEL_SHIFT;
699
+ break;
700
+ case CLK_PWM2_PERI:
701
+ mask = CLK_PWM2_PERI_SEL_MASK;
702
+ shift = CLK_PWM2_PERI_SEL_SHIFT;
703
+ break;
704
+ case CLK_PWM3_PERI:
705
+ mask = CLK_PWM3_PERI_SEL_MASK;
706
+ shift = CLK_PWM3_PERI_SEL_SHIFT;
707
+ break;
708
+ default:
709
+ return -ENOENT;
710
+ }
711
+
712
+ if (rate == 100 * MHz)
713
+ sel = CLK_PWM_SEL_100M;
714
+ else if (rate == 50 * MHz)
715
+ sel = CLK_PWM_SEL_50M;
716
+ else
717
+ sel = CLK_PWM_SEL_24M;
718
+ rk_clrsetreg(&cru->periclksel_con[40], mask, sel << shift);
719
+
720
+ return rk3562_pwm_get_rate(priv, clk_id);
721
+}
722
+
723
+static ulong rk3562_spi_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
724
+{
725
+ struct rk3562_cru *cru = priv->cru;
726
+ u32 sel, con, div, mask, shift;
727
+ ulong rate;
728
+
729
+ switch (clk_id) {
730
+ case CLK_PMU1_SPI0:
731
+ con = readl(&cru->pmu1clksel_con[4]);
732
+ sel = (con & CLK_PMU1_SPI0_SEL_MASK) >> CLK_PMU1_SPI0_SEL_SHIFT;
733
+ if (sel == CLK_PMU1_SPI0_SEL_200M)
734
+ rate = 200 * MHz;
735
+ else if (sel == CLK_PMU1_SPI0_SEL_24M)
736
+ rate = OSC_HZ;
737
+ else
738
+ rate = 32768;
739
+ div = (con & CLK_PMU1_SPI0_DIV_MASK) >> CLK_PMU1_SPI0_DIV_SHIFT;
740
+
741
+ return DIV_TO_RATE(rate, div);
742
+ case CLK_SPI1:
743
+ mask = CLK_SPI1_SEL_MASK;
744
+ shift = CLK_SPI1_SEL_SHIFT;
745
+ break;
746
+ case CLK_SPI2:
747
+ mask = CLK_SPI2_SEL_MASK;
748
+ shift = CLK_SPI2_SEL_SHIFT;
749
+ break;
750
+ default:
751
+ return -ENOENT;
752
+ }
753
+
754
+ con = readl(&cru->periclksel_con[20]);
755
+ sel = (con & mask) >> shift;
756
+ if (sel == CLK_SPI_SEL_200M)
757
+ rate = 200 * MHz;
758
+ else if (sel == CLK_SPI_SEL_100M)
759
+ rate = 100 * MHz;
760
+ else if (sel == CLK_SPI_SEL_50M)
761
+ rate = 50 * MHz;
762
+ else
763
+ rate = OSC_HZ;
764
+
765
+ return rate;
766
+}
767
+
768
+static ulong rk3562_spi_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
769
+ ulong rate)
770
+{
771
+ struct rk3562_cru *cru = priv->cru;
772
+ u32 sel, div, mask, shift;
773
+
774
+ switch (clk_id) {
775
+ case CLK_PMU1_SPI0:
776
+ if (rate == 200 * MHz) {
777
+ sel = CLK_PMU1_SPI0_SEL_200M;
778
+ div = 1;
779
+ } else if (rate == OSC_HZ) {
780
+ sel = CLK_PMU1_SPI0_SEL_24M;
781
+ div = 1;
782
+ } else if (rate == 32768) {
783
+ sel = CLK_PMU1_SPI0_SEL_32K;
784
+ div = 1;
785
+ } else {
786
+ sel = CLK_PMU1_SPI0_SEL_200M;
787
+ div = DIV_ROUND_UP(200 * MHz, rate);
788
+ assert(div - 1 <= 3);
789
+ }
790
+ rk_clrsetreg(&cru->pmu1clksel_con[4], CLK_PMU1_SPI0_DIV_MASK,
791
+ (div - 1) << CLK_PMU1_SPI0_DIV_SHIFT);
792
+ rk_clrsetreg(&cru->pmu1clksel_con[4], CLK_PMU1_SPI0_SEL_MASK,
793
+ sel << CLK_PMU1_SPI0_SEL_SHIFT);
794
+
795
+ return rk3562_spi_get_rate(priv, clk_id);
796
+ case CLK_SPI1:
797
+ mask = CLK_SPI1_SEL_MASK;
798
+ shift = CLK_SPI1_SEL_SHIFT;
799
+ break;
800
+ case CLK_SPI2:
801
+ mask = CLK_SPI2_SEL_MASK;
802
+ shift = CLK_SPI2_SEL_SHIFT;
803
+ break;
804
+ default:
805
+ return -ENOENT;
806
+ }
807
+
808
+ if (rate == 200 * MHz)
809
+ sel = CLK_SPI_SEL_200M;
810
+ else if (rate == 100 * MHz)
811
+ sel = CLK_SPI_SEL_100M;
812
+ else if (rate == 50 * MHz)
813
+ sel = CLK_SPI_SEL_50M;
814
+ else
815
+ sel = CLK_SPI_SEL_24M;
816
+ rk_clrsetreg(&cru->periclksel_con[20], mask, sel << shift);
817
+
818
+ return rk3562_spi_get_rate(priv, clk_id);
819
+}
820
+
821
+static ulong rk3562_tsadc_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
822
+{
823
+ struct rk3562_cru *cru = priv->cru;
824
+ u32 div, con;
825
+
826
+ con = readl(&cru->clksel_con[43]);
827
+ switch (clk_id) {
828
+ case CLK_TSADC_TSEN:
829
+ div = (con & CLK_TSADC_TSEN_DIV_MASK) >>
830
+ CLK_TSADC_TSEN_DIV_SHIFT;
831
+ break;
832
+ case CLK_TSADC:
833
+ div = (con & CLK_TSADC_DIV_MASK) >> CLK_TSADC_DIV_SHIFT;
834
+ break;
835
+ default:
836
+ return -ENOENT;
837
+ }
838
+
839
+ return DIV_TO_RATE(OSC_HZ, div);
840
+}
841
+
842
+static ulong rk3562_tsadc_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
843
+ ulong rate)
844
+{
845
+ struct rk3562_cru *cru = priv->cru;
846
+ u32 div, mask, shift;
847
+
848
+ switch (clk_id) {
849
+ case CLK_TSADC_TSEN:
850
+ mask = CLK_TSADC_TSEN_DIV_MASK;
851
+ shift = CLK_TSADC_TSEN_DIV_SHIFT;
852
+ break;
853
+ case CLK_TSADC:
854
+ mask = CLK_TSADC_DIV_MASK;
855
+ shift = CLK_TSADC_DIV_SHIFT;
856
+ break;
857
+ default:
858
+ return -ENOENT;
859
+ }
860
+
861
+ div = DIV_ROUND_UP(OSC_HZ, rate);
862
+ rk_clrsetreg(&cru->clksel_con[43], mask, (div - 1) << shift);
863
+
864
+ return rk3562_tsadc_get_rate(priv, clk_id);
865
+}
866
+
867
+static ulong rk3562_saradc_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
868
+{
869
+ struct rk3562_cru *cru = priv->cru;
870
+ u32 div, con;
871
+
872
+ switch (clk_id) {
873
+ case CLK_SARADC_VCCIO156:
874
+ con = readl(&cru->clksel_con[44]);
875
+ div = (con & CLK_SARADC_VCCIO156_DIV_MASK) >>
876
+ CLK_SARADC_VCCIO156_DIV_SHIFT;
877
+ break;
878
+ case CLK_SARADC:
879
+ con = readl(&cru->periclksel_con[46]);
880
+ div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT;
881
+ break;
882
+ default:
883
+ return -ENOENT;
884
+ }
885
+
886
+ return DIV_TO_RATE(OSC_HZ, div);
887
+}
888
+
889
+static ulong rk3562_saradc_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
890
+ ulong rate)
891
+{
892
+ struct rk3562_cru *cru = priv->cru;
893
+ u32 div;
894
+
895
+ switch (clk_id) {
896
+ case CLK_SARADC_VCCIO156:
897
+ div = DIV_ROUND_UP(OSC_HZ, rate);
898
+ rk_clrsetreg(&cru->clksel_con[44], CLK_SARADC_VCCIO156_DIV_MASK,
899
+ (div - 1) << CLK_SARADC_VCCIO156_DIV_SHIFT);
900
+ break;
901
+ case CLK_SARADC:
902
+ div = DIV_ROUND_UP(OSC_HZ, rate);
903
+ rk_clrsetreg(&cru->periclksel_con[46], CLK_SARADC_DIV_MASK,
904
+ (div - 1) << CLK_SARADC_DIV_SHIFT);
905
+ break;
906
+ default:
907
+ return -ENOENT;
908
+ }
909
+
910
+ return rk3562_saradc_get_rate(priv, clk_id);
911
+}
912
+
913
+static ulong rk3562_sfc_get_rate(struct rk3562_clk_priv *priv)
914
+{
915
+ struct rk3562_cru *cru = priv->cru;
916
+ u32 div, sel, con, parent;
917
+
918
+ con = readl(&cru->periclksel_con[20]);
919
+ div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT;
920
+ sel = (con & SCLK_SFC_SEL_MASK) >> SCLK_SFC_SEL_SHIFT;
921
+ if (sel == SCLK_SFC_SRC_SEL_GPLL)
922
+ parent = priv->gpll_hz;
923
+ else if (sel == SCLK_SFC_SRC_SEL_CPLL)
924
+ parent = priv->cpll_hz;
925
+ else
926
+ parent = OSC_HZ;
927
+
928
+ return DIV_TO_RATE(parent, div);
929
+}
930
+
931
+static ulong rk3562_sfc_set_rate(struct rk3562_clk_priv *priv, ulong rate)
932
+{
933
+ struct rk3562_cru *cru = priv->cru;
934
+ int div, sel;
935
+
936
+ if (OSC_HZ % rate == 0) {
937
+ div = DIV_ROUND_UP(OSC_HZ, rate);
938
+ sel = SCLK_SFC_SRC_SEL_24M;
939
+ } else if ((priv->cpll_hz % rate) == 0) {
940
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
941
+ sel = SCLK_SFC_SRC_SEL_CPLL;
942
+ } else {
943
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
944
+ sel = SCLK_SFC_SRC_SEL_GPLL;
945
+ }
946
+
947
+ assert(div - 1 <= 255);
948
+ rk_clrsetreg(&cru->periclksel_con[20],
949
+ SCLK_SFC_SEL_MASK | SCLK_SFC_DIV_MASK,
950
+ sel << SCLK_SFC_SEL_SHIFT |
951
+ (div - 1) << SCLK_SFC_DIV_SHIFT);
952
+
953
+ return rk3562_sfc_get_rate(priv);
954
+}
955
+
956
+static ulong rk3562_emmc_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
957
+{
958
+ struct rk3562_cru *cru = priv->cru;
959
+ u32 div, sel, con, parent;
960
+
961
+ switch (clk_id) {
962
+ case CCLK_EMMC:
963
+ con = readl(&cru->periclksel_con[18]);
964
+ div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT;
965
+ sel = (con & CCLK_EMMC_SEL_MASK) >> CCLK_EMMC_SEL_SHIFT;
966
+ if (sel == CCLK_EMMC_SEL_GPLL)
967
+ parent = priv->gpll_hz;
968
+ else if (sel == CCLK_EMMC_SEL_CPLL)
969
+ parent = priv->cpll_hz;
970
+ else if (sel == CCLK_EMMC_SEL_HPLL)
971
+ parent = priv->hpll_hz;
972
+ else
973
+ parent = OSC_HZ;
974
+ break;
975
+ case BCLK_EMMC:
976
+ con = readl(&cru->periclksel_con[19]);
977
+ div = (con & BCLK_EMMC_DIV_MASK) >> BCLK_EMMC_DIV_SHIFT;
978
+ sel = (con & BCLK_EMMC_SEL_MASK) >> BCLK_EMMC_SEL_SHIFT;
979
+ if (sel == BCLK_EMMC_SEL_GPLL)
980
+ parent = priv->gpll_hz;
981
+ else
982
+ parent = priv->cpll_hz;
983
+ break;
984
+ default:
985
+ return -ENOENT;
986
+ }
987
+
988
+ return DIV_TO_RATE(parent, div);
989
+}
990
+
991
+static ulong rk3562_emmc_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
992
+ ulong rate)
993
+{
994
+ struct rk3562_cru *cru = priv->cru;
995
+ int div, sel;
996
+
997
+ switch (clk_id) {
998
+ case CCLK_EMMC:
999
+ if (OSC_HZ % rate == 0) {
1000
+ div = DIV_ROUND_UP(OSC_HZ, rate);
1001
+ sel = CCLK_EMMC_SEL_24M;
1002
+ } else if ((priv->cpll_hz % rate) == 0) {
1003
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
1004
+ sel = CCLK_EMMC_SEL_CPLL;
1005
+ } else if ((priv->hpll_hz % rate) == 0) {
1006
+ div = DIV_ROUND_UP(priv->hpll_hz, rate);
1007
+ sel = CCLK_EMMC_SEL_HPLL;
1008
+ } else {
1009
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
1010
+ sel = CCLK_EMMC_SEL_GPLL;
1011
+ }
1012
+ rk_clrsetreg(&cru->periclksel_con[18],
1013
+ CCLK_EMMC_SEL_MASK | CCLK_EMMC_DIV_MASK,
1014
+ sel << CCLK_EMMC_SEL_SHIFT |
1015
+ (div - 1) << CCLK_EMMC_DIV_SHIFT);
1016
+ break;
1017
+ case BCLK_EMMC:
1018
+ if ((priv->cpll_hz % rate) == 0) {
1019
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
1020
+ sel = BCLK_EMMC_SEL_CPLL;
1021
+ } else {
1022
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
1023
+ sel = BCLK_EMMC_SEL_GPLL;
1024
+ }
1025
+ rk_clrsetreg(&cru->periclksel_con[19],
1026
+ BCLK_EMMC_SEL_MASK | BCLK_EMMC_DIV_MASK,
1027
+ sel << BCLK_EMMC_SEL_SHIFT |
1028
+ (div - 1) << BCLK_EMMC_DIV_SHIFT);
1029
+ break;
1030
+ default:
1031
+ return -ENOENT;
1032
+ }
1033
+
1034
+ return rk3562_emmc_get_rate(priv, clk_id);
1035
+}
1036
+
1037
+static ulong rk3562_sdmmc_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
1038
+{
1039
+ struct rk3562_cru *cru = priv->cru;
1040
+ u32 div, sel, con;
1041
+ ulong prate;
1042
+
1043
+ switch (clk_id) {
1044
+ case HCLK_SDMMC0:
1045
+ case CCLK_SDMMC0:
1046
+ case SCLK_SDMMC0_SAMPLE:
1047
+ con = readl(&cru->periclksel_con[16]);
1048
+ div = (con & CCLK_SDMMC0_DIV_MASK) >> CCLK_SDMMC0_DIV_SHIFT;
1049
+ sel = (con & CCLK_SDMMC0_SEL_MASK) >> CCLK_SDMMC0_SEL_SHIFT;
1050
+ break;
1051
+ case HCLK_SDMMC1:
1052
+ case CCLK_SDMMC1:
1053
+ case SCLK_SDMMC1_SAMPLE:
1054
+ con = readl(&cru->periclksel_con[17]);
1055
+ div = (con & CCLK_SDMMC1_DIV_MASK) >> CCLK_SDMMC1_DIV_SHIFT;
1056
+ sel = (con & CCLK_SDMMC1_SEL_MASK) >> CCLK_SDMMC1_SEL_SHIFT;
1057
+ break;
1058
+ default:
1059
+ return -ENOENT;
1060
+ }
1061
+
1062
+ if (sel == CCLK_SDMMC_SEL_GPLL)
1063
+ prate = priv->gpll_hz;
1064
+ else if (sel == CCLK_SDMMC_SEL_CPLL)
1065
+ prate = priv->cpll_hz;
1066
+ else if (sel == CCLK_SDMMC_SEL_HPLL)
1067
+ prate = priv->hpll_hz;
1068
+ else
1069
+ prate = OSC_HZ;
1070
+
1071
+ return DIV_TO_RATE(prate, div);
1072
+}
1073
+
1074
+static ulong rk3562_sdmmc_set_rate(struct rk3562_clk_priv *priv,
1075
+ ulong clk_id, ulong rate)
1076
+{
1077
+ struct rk3562_cru *cru = priv->cru;
1078
+ u32 div, sel;
1079
+
1080
+ if (OSC_HZ % rate == 0) {
1081
+ div = DIV_ROUND_UP(OSC_HZ, rate);
1082
+ sel = CCLK_SDMMC_SEL_24M;
1083
+ } else if ((priv->cpll_hz % rate) == 0) {
1084
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
1085
+ sel = CCLK_SDMMC_SEL_CPLL;
1086
+ } else if ((priv->hpll_hz % rate) == 0) {
1087
+ div = DIV_ROUND_UP(priv->hpll_hz, rate);
1088
+ sel = CCLK_SDMMC_SEL_HPLL;
1089
+ } else {
1090
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
1091
+ sel = CCLK_SDMMC_SEL_CPLL;
1092
+ }
1093
+
1094
+ switch (clk_id) {
1095
+ case HCLK_SDMMC0:
1096
+ case CCLK_SDMMC0:
1097
+ rk_clrsetreg(&cru->periclksel_con[16],
1098
+ CCLK_SDMMC0_SEL_MASK | CCLK_SDMMC0_DIV_MASK,
1099
+ sel << CCLK_SDMMC0_SEL_SHIFT |
1100
+ (div - 1) << CCLK_SDMMC0_DIV_SHIFT);
1101
+ break;
1102
+ case HCLK_SDMMC1:
1103
+ case CCLK_SDMMC1:
1104
+ rk_clrsetreg(&cru->periclksel_con[17],
1105
+ CCLK_SDMMC1_SEL_MASK | CCLK_SDMMC1_DIV_MASK,
1106
+ sel << CCLK_SDMMC1_SEL_SHIFT |
1107
+ (div - 1) << CCLK_SDMMC1_DIV_SHIFT);
1108
+ break;
1109
+ default:
1110
+ return -ENOENT;
1111
+ }
1112
+
1113
+ return rk3562_sdmmc_get_rate(priv, clk_id);
1114
+}
1115
+
1116
+static ulong rk3562_vop_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
1117
+{
1118
+ struct rk3562_cru *cru = priv->cru;
1119
+ u32 con, sel, div;
1120
+ ulong prate;
1121
+
1122
+ switch (clk_id) {
1123
+ case ACLK_VOP:
1124
+ con = readl(&cru->clksel_con[28]);
1125
+ div = (con & ACLK_VOP_DIV_MASK) >> ACLK_VOP_DIV_SHIFT;
1126
+ sel = (con & ACLK_VOP_SEL_MASK) >> ACLK_VOP_SEL_SHIFT;
1127
+ if (sel == ACLK_VOP_SEL_GPLL)
1128
+ prate = priv->gpll_hz;
1129
+ else if (sel == ACLK_VOP_SEL_CPLL)
1130
+ prate = priv->cpll_hz;
1131
+ else if (sel == ACLK_VOP_SEL_HPLL)
1132
+ prate = priv->hpll_hz;
1133
+ else if (sel == ACLK_VOP_SEL_VPLL)
1134
+ prate = priv->vpll_hz;
1135
+ else
1136
+ return -ENOENT;
1137
+
1138
+ return DIV_TO_RATE(prate, div);
1139
+ case DCLK_VOP:
1140
+ con = readl(&cru->clksel_con[30]);
1141
+ div = (con & DCLK_VOP_DIV_MASK) >> DCLK_VOP_DIV_SHIFT;
1142
+ sel = (con & DCLK_VOP_SEL_MASK) >> DCLK_VOP_SEL_SHIFT;
1143
+ if (sel == DCLK_VOP_SEL_VPLL)
1144
+ priv->vpll_hz =
1145
+ rockchip_pll_get_rate(&rk3562_pll_clks[VPLL],
1146
+ priv->cru, VPLL);
1147
+ break;
1148
+ case DCLK_VOP1:
1149
+ con = readl(&cru->clksel_con[31]);
1150
+ div = (con & DCLK_VOP1_DIV_MASK) >> DCLK_VOP1_DIV_SHIFT;
1151
+ sel = (con & DCLK_VOP1_SEL_MASK) >> DCLK_VOP1_SEL_SHIFT;
1152
+ break;
1153
+ default:
1154
+ return -ENOENT;
1155
+ }
1156
+
1157
+ if (sel == DCLK_VOP_SEL_GPLL)
1158
+ prate = priv->gpll_hz;
1159
+ else if (sel == DCLK_VOP_SEL_HPLL)
1160
+ prate = priv->hpll_hz;
1161
+ else if (sel == DCLK_VOP_SEL_VPLL)
1162
+ prate = priv->vpll_hz;
1163
+ else
1164
+ return -ENOENT;
1165
+
1166
+ return DIV_TO_RATE(prate, div);
1167
+}
1168
+
1169
+#define RK3562_VOP_PLL_LIMIT_FREQ 600000000
1170
+
1171
+static ulong rk3562_vop_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
1172
+ ulong rate)
1173
+{
1174
+ struct rk3562_cru *cru = priv->cru;
1175
+ u32 i, div, sel, best_div = 0, best_sel = 0;
1176
+ ulong pll_rate, now, best_rate = 0;
1177
+
1178
+ switch (clk_id) {
1179
+ case ACLK_VOP:
1180
+ if ((priv->cpll_hz % rate) == 0) {
1181
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
1182
+ sel = ACLK_VOP_SEL_CPLL;
1183
+ } else if ((priv->hpll_hz % rate) == 0) {
1184
+ div = DIV_ROUND_UP(priv->hpll_hz, rate);
1185
+ sel = ACLK_VOP_SEL_HPLL;
1186
+ } else if ((priv->vpll_hz % rate) == 0) {
1187
+ div = DIV_ROUND_UP(priv->vpll_hz, rate);
1188
+ sel = ACLK_VOP_SEL_VPLL;
1189
+ } else {
1190
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
1191
+ sel = ACLK_VOP_SEL_GPLL;
1192
+ }
1193
+ rk_clrsetreg(&cru->clksel_con[28],
1194
+ ACLK_VOP_SEL_MASK | ACLK_VOP_DIV_MASK,
1195
+ sel << ACLK_VOP_SEL_SHIFT |
1196
+ ((div - 1) << ACLK_VOP_DIV_SHIFT));
1197
+
1198
+ return rk3562_vop_get_rate(priv, clk_id);
1199
+ case DCLK_VOP:
1200
+ div = DIV_ROUND_UP(RK3562_VOP_PLL_LIMIT_FREQ, rate);
1201
+ rk_clrsetreg(&cru->clksel_con[30],
1202
+ DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_MASK,
1203
+ DCLK_VOP_SEL_VPLL << DCLK_VOP_SEL_SHIFT |
1204
+ ((div - 1) << DCLK_VOP_DIV_SHIFT));
1205
+ rockchip_pll_set_rate(&rk3562_pll_clks[VPLL], priv->cru,
1206
+ VPLL, div * rate);
1207
+ break;
1208
+ case DCLK_VOP1:
1209
+ for (i = 0; i <= DCLK_VOP_SEL_APLL; i++) {
1210
+ switch (i) {
1211
+ case DCLK_VOP_SEL_GPLL:
1212
+ pll_rate = priv->gpll_hz;
1213
+ break;
1214
+ case DCLK_VOP_SEL_HPLL:
1215
+ pll_rate = priv->hpll_hz;
1216
+ break;
1217
+ case DCLK_VOP_SEL_VPLL:
1218
+ case DCLK_VOP_SEL_APLL:
1219
+ continue;
1220
+ default:
1221
+ printf("do not support this vop pll sel\n");
1222
+ return -EINVAL;
1223
+ }
1224
+
1225
+ div = DIV_ROUND_UP(pll_rate, rate);
1226
+ if (div > 255)
1227
+ continue;
1228
+ now = pll_rate / div;
1229
+ if (abs(rate - now) < abs(rate - best_rate)) {
1230
+ best_rate = now;
1231
+ best_div = div;
1232
+ best_sel = i;
1233
+ }
1234
+ debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n",
1235
+ pll_rate, best_rate, best_div, best_sel);
1236
+ }
1237
+ if (best_rate) {
1238
+ rk_clrsetreg(&cru->clksel_con[31],
1239
+ DCLK_VOP1_SEL_MASK | DCLK_VOP1_DIV_MASK,
1240
+ best_sel << DCLK_VOP1_SEL_SHIFT |
1241
+ (best_div - 1) << DCLK_VOP1_DIV_SHIFT);
1242
+ } else {
1243
+ printf("do not support this vop freq %lu\n", rate);
1244
+ return -EINVAL;
1245
+ }
1246
+ break;
1247
+ default:
1248
+ return -ENOENT;
1249
+ }
1250
+
1251
+ return rk3562_vop_get_rate(priv, clk_id);
1252
+}
1253
+
1254
+static ulong rk3562_gmac_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
1255
+{
1256
+ struct rk3562_cru *cru = priv->cru;
1257
+ u32 con, sel, div;
1258
+ ulong prate;
1259
+
1260
+ switch (clk_id) {
1261
+ case CLK_GMAC_125M_CRU_I:
1262
+ con = readl(&cru->clksel_con[45]);
1263
+ sel = (con & CLK_GMAC_125M_SEL_MASK) >> CLK_GMAC_125M_SEL_SHIFT;
1264
+ if (sel == CLK_GMAC_125M)
1265
+ return 125000000;
1266
+ else
1267
+ return OSC_HZ;
1268
+ case CLK_GMAC_50M_CRU_I:
1269
+ con = readl(&cru->clksel_con[45]);
1270
+ sel = (con & CLK_GMAC_50M_SEL_MASK) >> CLK_GMAC_50M_SEL_SHIFT;
1271
+ if (sel == CLK_GMAC_50M)
1272
+ return 50000000;
1273
+ else
1274
+ return OSC_HZ;
1275
+ case CLK_MAC100_50M_MATRIX:
1276
+ con = readl(&cru->clksel_con[47]);
1277
+ sel = (con & CLK_GMAC_50M_SEL_MASK) >> CLK_GMAC_50M_SEL_SHIFT;
1278
+ if (sel == CLK_GMAC_50M)
1279
+ return 50000000;
1280
+ else
1281
+ return OSC_HZ;
1282
+ case CLK_GMAC_ETH_OUT2IO:
1283
+ con = readl(&cru->clksel_con[46]);
1284
+ sel = (con & CLK_GMAC_ETH_OUT2IO_SEL_MASK) >> CLK_GMAC_ETH_OUT2IO_SEL_SHIFT;
1285
+ div = (con & CLK_GMAC_ETH_OUT2IO_DIV_MASK) >> CLK_GMAC_ETH_OUT2IO_DIV_SHIFT;
1286
+ if (sel == CLK_GMAC_ETH_OUT2IO_GPLL)
1287
+ prate = priv->gpll_hz;
1288
+ else
1289
+ prate = priv->cpll_hz;
1290
+ break;
1291
+ default:
1292
+ return -ENOENT;
1293
+ }
1294
+
1295
+ return DIV_TO_RATE(prate, div);
1296
+}
1297
+
1298
+static ulong rk3562_gmac_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
1299
+ ulong rate)
1300
+{
1301
+ struct rk3562_cru *cru = priv->cru;
1302
+ u32 sel, div;
1303
+
1304
+ switch (clk_id) {
1305
+ case CLK_GMAC_125M_CRU_I:
1306
+ if (rate == 125000000)
1307
+ sel = CLK_GMAC_125M;
1308
+ else
1309
+ sel = CLK_GMAC_24M;
1310
+ rk_clrsetreg(&cru->clksel_con[45], CLK_GMAC_125M_SEL_MASK,
1311
+ sel << CLK_GMAC_125M_SEL_SHIFT);
1312
+ break;
1313
+ case CLK_GMAC_50M_CRU_I:
1314
+ if (rate == 50000000)
1315
+ sel = CLK_GMAC_50M;
1316
+ else
1317
+ sel = CLK_GMAC_24M;
1318
+ rk_clrsetreg(&cru->clksel_con[45], CLK_GMAC_50M_SEL_MASK,
1319
+ sel << CLK_GMAC_50M_SEL_SHIFT);
1320
+ break;
1321
+ case CLK_MAC100_50M_MATRIX:
1322
+ if (rate == 50000000)
1323
+ sel = CLK_GMAC_50M;
1324
+ else
1325
+ sel = CLK_GMAC_24M;
1326
+ rk_clrsetreg(&cru->clksel_con[47], CLK_GMAC_50M_SEL_MASK,
1327
+ sel << CLK_GMAC_50M_SEL_SHIFT);
1328
+ break;
1329
+ case CLK_GMAC_ETH_OUT2IO:
1330
+ if ((priv->cpll_hz % rate) == 0) {
1331
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
1332
+ sel = CLK_GMAC_ETH_OUT2IO_CPLL;
1333
+ } else {
1334
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
1335
+ sel = CLK_GMAC_ETH_OUT2IO_GPLL;
1336
+ }
1337
+ rk_clrsetreg(&cru->clksel_con[46],
1338
+ CLK_GMAC_ETH_OUT2IO_SEL_MASK | CLK_GMAC_ETH_OUT2IO_DIV_MASK,
1339
+ sel << CLK_GMAC_ETH_OUT2IO_SEL_SHIFT |
1340
+ (div - 1) << CLK_GMAC_ETH_OUT2IO_DIV_SHIFT);
1341
+ break;
1342
+ default:
1343
+ return -ENOENT;
1344
+ }
1345
+
1346
+ return rk3562_gmac_get_rate(priv, clk_id);
1347
+}
1348
+
1349
+static ulong rk3562_clk_get_rate(struct clk *clk)
1350
+{
1351
+ struct rk3562_clk_priv *priv = dev_get_priv(clk->dev);
1352
+ ulong rate = 0;
1353
+
1354
+ if (!priv->gpll_hz || !priv->cpll_hz || !priv->hpll_hz) {
1355
+ printf("%s: gpll=%lu, cpll=%lu, hpll=%lu\n",
1356
+ __func__, priv->gpll_hz, priv->cpll_hz, priv->hpll_hz);
1357
+ return -ENOENT;
1358
+ }
1359
+
1360
+ switch (clk->id) {
1361
+ case PLL_APLL:
1362
+ case ARMCLK:
1363
+ rate = rockchip_pll_get_rate(&rk3562_pll_clks[APLL], priv->cru,
1364
+ APLL);
1365
+ break;
1366
+ case PLL_GPLL:
1367
+ rate = rockchip_pll_get_rate(&rk3562_pll_clks[GPLL], priv->cru,
1368
+ GPLL);
1369
+ break;
1370
+
1371
+ case PLL_VPLL:
1372
+ rate = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL], priv->cru,
1373
+ VPLL);
1374
+ break;
1375
+ case PLL_HPLL:
1376
+ rate = rockchip_pll_get_rate(&rk3562_pll_clks[HPLL], priv->cru,
1377
+ HPLL);
1378
+ break;
1379
+ case PLL_CPLL:
1380
+ rate = rockchip_pll_get_rate(&rk3562_pll_clks[CPLL], priv->cru,
1381
+ CPLL);
1382
+ break;
1383
+ case PLL_DPLL:
1384
+ rate = rockchip_pll_get_rate(&rk3562_pll_clks[DPLL], priv->cru,
1385
+ DPLL);
1386
+ break;
1387
+ case ACLK_BUS:
1388
+ case HCLK_BUS:
1389
+ case PCLK_BUS:
1390
+ rate = rk3562_bus_get_rate(priv, clk->id);
1391
+ break;
1392
+ case ACLK_PERI:
1393
+ case HCLK_PERI:
1394
+ case PCLK_PERI:
1395
+ rate = rk3562_peri_get_rate(priv, clk->id);
1396
+ break;
1397
+ case CLK_PMU0_I2C0:
1398
+ case CLK_I2C:
1399
+ case CLK_I2C1:
1400
+ case CLK_I2C2:
1401
+ case CLK_I2C3:
1402
+ case CLK_I2C4:
1403
+ case CLK_I2C5:
1404
+ rate = rk3562_i2c_get_rate(priv, clk->id);
1405
+ break;
1406
+ case SCLK_PMU1_UART0:
1407
+ case SCLK_UART1:
1408
+ case SCLK_UART2:
1409
+ case SCLK_UART3:
1410
+ case SCLK_UART4:
1411
+ case SCLK_UART5:
1412
+ case SCLK_UART6:
1413
+ case SCLK_UART7:
1414
+ case SCLK_UART8:
1415
+ case SCLK_UART9:
1416
+ rate = rk3562_uart_get_rate(priv, clk->id);
1417
+ break;
1418
+ case CLK_PMU1_PWM0:
1419
+ case CLK_PWM1_PERI:
1420
+ case CLK_PWM2_PERI:
1421
+ case CLK_PWM3_PERI:
1422
+ rate = rk3562_pwm_get_rate(priv, clk->id);
1423
+ break;
1424
+ case CLK_PMU1_SPI0:
1425
+ case CLK_SPI1:
1426
+ case CLK_SPI2:
1427
+ rate = rk3562_spi_get_rate(priv, clk->id);
1428
+ break;
1429
+ case CLK_TSADC:
1430
+ case CLK_TSADC_TSEN:
1431
+ rate = rk3562_tsadc_get_rate(priv, clk->id);
1432
+ break;
1433
+ case CLK_SARADC:
1434
+ case CLK_SARADC_VCCIO156:
1435
+ rate = rk3562_saradc_get_rate(priv, clk->id);
1436
+ break;
1437
+ case SCLK_SFC:
1438
+ rate = rk3562_sfc_get_rate(priv);
1439
+ break;
1440
+ case CCLK_EMMC:
1441
+ case BCLK_EMMC:
1442
+ rate = rk3562_emmc_get_rate(priv, clk->id);
1443
+ break;
1444
+ case HCLK_SDMMC0:
1445
+ case HCLK_SDMMC1:
1446
+ case CCLK_SDMMC0:
1447
+ case CCLK_SDMMC1:
1448
+ case SCLK_SDMMC0_SAMPLE:
1449
+ case SCLK_SDMMC1_SAMPLE:
1450
+ rate = rk3562_sdmmc_get_rate(priv, clk->id);
1451
+ break;
1452
+ case ACLK_VOP:
1453
+ case DCLK_VOP:
1454
+ case DCLK_VOP1:
1455
+ rate = rk3562_vop_get_rate(priv, clk->id);
1456
+ break;
1457
+ case CLK_GMAC_125M_CRU_I:
1458
+ case CLK_GMAC_50M_CRU_I:
1459
+ case CLK_GMAC_ETH_OUT2IO:
1460
+ case CLK_MAC100_50M_MATRIX:
1461
+ rate = rk3562_gmac_get_rate(priv, clk->id);
1462
+ break;
1463
+ case CLK_WDTNS:
1464
+ rate = OSC_HZ;
1465
+ break;
1466
+ default:
1467
+ return -ENOENT;
1468
+ }
1469
+
1470
+ return rate;
1471
+};
1472
+
1473
+static ulong rk3562_clk_set_rate(struct clk *clk, ulong rate)
1474
+{
1475
+ struct rk3562_clk_priv *priv = dev_get_priv(clk->dev);
1476
+ ulong ret = 0;
1477
+
1478
+ if (!priv->gpll_hz || !priv->cpll_hz || !priv->hpll_hz) {
1479
+ printf("%s: gpll=%lu, cpll=%lu, hpll=%lu\n",
1480
+ __func__, priv->gpll_hz, priv->cpll_hz, priv->hpll_hz);
1481
+ return -ENOENT;
1482
+ }
1483
+
1484
+ debug("%s: id=%ld, rate=%ld\n", __func__, clk->id, rate);
1485
+
1486
+ switch (clk->id) {
1487
+ case PLL_APLL:
1488
+ case ARMCLK:
1489
+ if (priv->armclk_hz)
1490
+ rk3562_armclk_set_rate(priv, rate);
1491
+ priv->armclk_hz = rate;
1492
+ break;
1493
+ case PLL_GPLL:
1494
+ ret = rockchip_pll_set_rate(&rk3562_pll_clks[GPLL], priv->cru,
1495
+ GPLL, rate);
1496
+ priv->gpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[GPLL],
1497
+ priv->cru, GPLL);
1498
+ break;
1499
+ case PLL_VPLL:
1500
+ ret = rockchip_pll_set_rate(&rk3562_pll_clks[VPLL], priv->cru,
1501
+ VPLL, rate);
1502
+ priv->vpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL],
1503
+ priv->cru, VPLL);
1504
+ break;
1505
+ case PLL_HPLL:
1506
+ ret = rockchip_pll_set_rate(&rk3562_pll_clks[HPLL], priv->cru,
1507
+ HPLL, rate);
1508
+ priv->hpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[HPLL],
1509
+ priv->cru, HPLL);
1510
+ break;
1511
+ case ACLK_BUS:
1512
+ case HCLK_BUS:
1513
+ case PCLK_BUS:
1514
+ ret = rk3562_bus_set_rate(priv, clk->id, rate);
1515
+ break;
1516
+ case ACLK_PERI:
1517
+ case HCLK_PERI:
1518
+ case PCLK_PERI:
1519
+ ret = rk3562_peri_set_rate(priv, clk->id, rate);
1520
+ break;
1521
+ case CLK_PMU0_I2C0:
1522
+ case CLK_I2C:
1523
+ case CLK_I2C1:
1524
+ case CLK_I2C2:
1525
+ case CLK_I2C3:
1526
+ case CLK_I2C4:
1527
+ case CLK_I2C5:
1528
+ ret = rk3562_i2c_set_rate(priv, clk->id, rate);
1529
+ break;
1530
+ case SCLK_PMU1_UART0:
1531
+ case SCLK_UART1:
1532
+ case SCLK_UART2:
1533
+ case SCLK_UART3:
1534
+ case SCLK_UART4:
1535
+ case SCLK_UART5:
1536
+ case SCLK_UART6:
1537
+ case SCLK_UART7:
1538
+ case SCLK_UART8:
1539
+ case SCLK_UART9:
1540
+ ret = rk3562_uart_set_rate(priv, clk->id, rate);
1541
+ break;
1542
+ case CLK_PMU1_PWM0:
1543
+ case CLK_PWM1_PERI:
1544
+ case CLK_PWM2_PERI:
1545
+ case CLK_PWM3_PERI:
1546
+ ret = rk3562_pwm_set_rate(priv, clk->id, rate);
1547
+ break;
1548
+ case CLK_PMU1_SPI0:
1549
+ case CLK_SPI1:
1550
+ case CLK_SPI2:
1551
+ ret = rk3562_spi_set_rate(priv, clk->id, rate);
1552
+ break;
1553
+ case CLK_TSADC:
1554
+ case CLK_TSADC_TSEN:
1555
+ ret = rk3562_tsadc_set_rate(priv, clk->id, rate);
1556
+ break;
1557
+ case CLK_SARADC:
1558
+ case CLK_SARADC_VCCIO156:
1559
+ ret = rk3562_saradc_set_rate(priv, clk->id, rate);
1560
+ break;
1561
+ case SCLK_SFC:
1562
+ ret = rk3562_sfc_set_rate(priv, rate);
1563
+ break;
1564
+ case CCLK_EMMC:
1565
+ case BCLK_EMMC:
1566
+ ret = rk3562_emmc_set_rate(priv, clk->id, rate);
1567
+ break;
1568
+ case HCLK_SDMMC0:
1569
+ case HCLK_SDMMC1:
1570
+ case CCLK_SDMMC0:
1571
+ case CCLK_SDMMC1:
1572
+ ret = rk3562_sdmmc_set_rate(priv, clk->id, rate);
1573
+ break;
1574
+ case ACLK_VOP:
1575
+ case DCLK_VOP:
1576
+ case DCLK_VOP1:
1577
+ ret = rk3562_vop_set_rate(priv, clk->id, rate);
1578
+ break;
1579
+ case CLK_GMAC_125M_CRU_I:
1580
+ case CLK_GMAC_50M_CRU_I:
1581
+ case CLK_GMAC_ETH_OUT2IO:
1582
+ case CLK_MAC100_50M_MATRIX:
1583
+ ret = rk3562_gmac_set_rate(priv, clk->id, rate);
1584
+ break;
1585
+ default:
1586
+ return -ENOENT;
1587
+ }
1588
+
1589
+ return ret;
1590
+};
1591
+
1592
+#define ROCKCHIP_MMC_DELAY_SEL BIT(11)
1593
+#define ROCKCHIP_MMC_DEGREE_SHIFT 1
1594
+#define ROCKCHIP_MMC_DEGREE_MASK (0x3 << ROCKCHIP_MMC_DEGREE_SHIFT)
1595
+#define ROCKCHIP_MMC_DELAYNUM_SHIFT 3
1596
+#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_SHIFT)
1597
+#define PSECS_PER_SEC 1000000000000LL
1598
+
1599
+/*
1600
+ * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
1601
+ * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
1602
+ */
1603
+#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
1604
+
1605
+int rk3562_mmc_get_phase(struct clk *clk)
1606
+{
1607
+ struct rk3562_clk_priv *priv = dev_get_priv(clk->dev);
1608
+ struct rk3562_cru *cru = priv->cru;
1609
+ u32 raw_value, delay_num;
1610
+ u16 degrees = 0;
1611
+ ulong rate;
1612
+
1613
+ rate = rk3562_clk_get_rate(clk);
1614
+ if (rate < 0)
1615
+ return rate;
1616
+
1617
+ if (clk->id == SCLK_SDMMC0_SAMPLE)
1618
+ raw_value = readl(&cru->sdmmc0_con[1]);
1619
+ else if (clk->id == SCLK_SDMMC0_SAMPLE)
1620
+ raw_value = readl(&cru->sdmmc1_con[1]);
1621
+ else
1622
+ return -ENONET;
1623
+
1624
+ raw_value &= ROCKCHIP_MMC_DEGREE_MASK;
1625
+ degrees = (raw_value >> ROCKCHIP_MMC_DEGREE_SHIFT) * 90;
1626
+
1627
+ if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
1628
+ /* degrees/delaynum * 10000 */
1629
+ unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
1630
+ 36 * (rate / 1000000);
1631
+
1632
+ delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
1633
+ delay_num >>= ROCKCHIP_MMC_DELAYNUM_SHIFT;
1634
+ degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000);
1635
+ }
1636
+
1637
+ return degrees % 360;
1638
+}
1639
+
1640
+int rk3562_mmc_set_phase(struct clk *clk, u32 degrees)
1641
+{
1642
+ struct rk3562_clk_priv *priv = dev_get_priv(clk->dev);
1643
+ struct rk3562_cru *cru = priv->cru;
1644
+ u8 nineties, remainder, delay_num;
1645
+ u32 raw_value, delay;
1646
+ ulong rate;
1647
+
1648
+ rate = rk3562_clk_get_rate(clk);
1649
+ if (rate < 0)
1650
+ return rate;
1651
+
1652
+ nineties = degrees / 90;
1653
+ remainder = (degrees % 90);
1654
+
1655
+ /*
1656
+ * Convert to delay; do a little extra work to make sure we
1657
+ * don't overflow 32-bit / 64-bit numbers.
1658
+ */
1659
+ delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
1660
+ delay *= remainder;
1661
+ delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 *
1662
+ (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
1663
+
1664
+ delay_num = (u8)min_t(u32, delay, 255);
1665
+
1666
+ raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
1667
+ raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_SHIFT;
1668
+ raw_value |= nineties << ROCKCHIP_MMC_DEGREE_SHIFT;
1669
+
1670
+ if (clk->id == SCLK_SDMMC0_SAMPLE)
1671
+ writel(raw_value | 0xffff0000, &cru->sdmmc0_con[1]);
1672
+ else
1673
+ writel(raw_value | 0xffff0000, &cru->sdmmc1_con[1]);
1674
+
1675
+ debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n",
1676
+ degrees, delay_num, raw_value, rk3562_mmc_get_phase(clk));
1677
+
1678
+ return 0;
1679
+}
1680
+
1681
+static int rk3562_clk_get_phase(struct clk *clk)
1682
+{
1683
+ int ret;
1684
+
1685
+ switch (clk->id) {
1686
+ case SCLK_SDMMC0_SAMPLE:
1687
+ case SCLK_SDMMC1_SAMPLE:
1688
+ ret = rk3562_mmc_get_phase(clk);
1689
+ break;
1690
+ default:
1691
+ return -ENOENT;
1692
+ }
1693
+
1694
+ return ret;
1695
+}
1696
+
1697
+static int rk3562_clk_set_phase(struct clk *clk, int degrees)
1698
+{
1699
+ int ret;
1700
+
1701
+ switch (clk->id) {
1702
+ case SCLK_SDMMC0_SAMPLE:
1703
+ case SCLK_SDMMC1_SAMPLE:
1704
+ ret = rk3562_mmc_set_phase(clk, degrees);
1705
+ break;
1706
+ default:
1707
+ return -ENOENT;
1708
+ }
1709
+
1710
+ return ret;
1711
+}
1712
+
1713
+static struct clk_ops rk3562_clk_ops = {
1714
+ .get_rate = rk3562_clk_get_rate,
1715
+ .set_rate = rk3562_clk_set_rate,
1716
+ .get_phase = rk3562_clk_get_phase,
1717
+ .set_phase = rk3562_clk_set_phase,
1718
+};
1719
+
1720
+#ifndef CONFIG_SPL_BUILD
1721
+/**
1722
+ * soc_clk_dump() - Print clock frequencies
1723
+ * Returns zero on success
1724
+ *
1725
+ * Implementation for the clk dump command.
1726
+ */
1727
+int soc_clk_dump(void)
1728
+{
1729
+ const struct rk3562_clk_info *clk_dump;
1730
+ struct rk3562_clk_priv *priv;
1731
+ struct udevice *cru_dev;
1732
+ struct clk clk;
1733
+ ulong clk_count = ARRAY_SIZE(clks_dump);
1734
+ ulong rate;
1735
+ int i, ret;
1736
+
1737
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
1738
+ DM_GET_DRIVER(rockchip_rk3562_cru),
1739
+ &cru_dev);
1740
+ if (ret) {
1741
+ printf("%s failed to get cru device\n", __func__);
1742
+ return ret;
1743
+ }
1744
+
1745
+ priv = dev_get_priv(cru_dev);
1746
+ printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n",
1747
+ priv->sync_kernel ? "sync kernel" : "uboot",
1748
+ priv->armclk_enter_hz / 1000,
1749
+ priv->armclk_init_hz / 1000,
1750
+ priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0,
1751
+ priv->set_armclk_rate ? " KHz" : "N/A");
1752
+ for (i = 0; i < clk_count; i++) {
1753
+ clk_dump = &clks_dump[i];
1754
+ if (clk_dump->name) {
1755
+ clk.id = clk_dump->id;
1756
+ ret = clk_request(cru_dev, &clk);
1757
+ if (ret < 0)
1758
+ return ret;
1759
+
1760
+ rate = clk_get_rate(&clk);
1761
+ clk_free(&clk);
1762
+ if (i == 0) {
1763
+ if (rate < 0)
1764
+ printf(" %s %s\n", clk_dump->name,
1765
+ "unknown");
1766
+ else
1767
+ printf(" %s %lu KHz\n", clk_dump->name,
1768
+ rate / 1000);
1769
+ } else {
1770
+ if (rate < 0)
1771
+ printf(" %s %s\n", clk_dump->name,
1772
+ "unknown");
1773
+ else
1774
+ printf(" %s %lu KHz\n", clk_dump->name,
1775
+ rate / 1000);
1776
+ }
1777
+ }
1778
+ }
1779
+
1780
+ return 0;
1781
+}
1782
+#endif
1783
+
1784
+static void rk3562_clk_init(struct rk3562_clk_priv *priv)
1785
+{
1786
+ int ret;
1787
+
1788
+ priv->sync_kernel = false;
1789
+ if (!priv->armclk_enter_hz)
1790
+ priv->armclk_enter_hz =
1791
+ rockchip_pll_get_rate(&rk3562_pll_clks[APLL],
1792
+ priv->cru, APLL);
1793
+
1794
+ if (!priv->armclk_init_hz) {
1795
+#ifdef CONFIG_SPL_BUILD
1796
+ ret = rk3562_armclk_set_rate(priv, APLL_HZ);
1797
+ if (!ret)
1798
+ priv->armclk_init_hz = APLL_HZ;
1799
+
1800
+#else
1801
+ struct clk clk;
1802
+
1803
+ ret = rockchip_get_scmi_clk(&clk.dev);
1804
+ if (ret) {
1805
+ printf("Failed to get scmi clk dev\n");
1806
+ return;
1807
+ }
1808
+
1809
+ clk.id = ARMCLK;
1810
+ ret = clk_set_rate(&clk, CPU_PVTPLL_HZ);
1811
+ if (ret < 0) {
1812
+ printf("Failed to set scmi cpu %dhz\n", CPU_PVTPLL_HZ);
1813
+ return;
1814
+ } else {
1815
+ priv->armclk_init_hz = CPU_PVTPLL_HZ;
1816
+ }
1817
+#endif
1818
+ }
1819
+ if (priv->cpll_hz != CPLL_HZ) {
1820
+ ret = rockchip_pll_set_rate(&rk3562_pll_clks[CPLL], priv->cru,
1821
+ CPLL, CPLL_HZ);
1822
+ if (!ret)
1823
+ priv->cpll_hz = CPLL_HZ;
1824
+ }
1825
+
1826
+ if (priv->gpll_hz != GPLL_HZ) {
1827
+ ret = rockchip_pll_set_rate(&rk3562_pll_clks[GPLL], priv->cru,
1828
+ GPLL, GPLL_HZ);
1829
+ if (!ret)
1830
+ priv->gpll_hz = GPLL_HZ;
1831
+ }
1832
+
1833
+ if (priv->hpll_hz != HPLL_HZ) {
1834
+ ret = rockchip_pll_set_rate(&rk3562_pll_clks[HPLL], priv->cru,
1835
+ HPLL, HPLL_HZ);
1836
+ if (!ret)
1837
+ priv->hpll_hz = HPLL_HZ;
1838
+ }
1839
+}
1840
+
1841
+static int rk3562_clk_probe(struct udevice *dev)
1842
+{
1843
+ struct rk3562_clk_priv *priv = dev_get_priv(dev);
1844
+ int ret;
1845
+
1846
+ rk3562_clk_init(priv);
1847
+
1848
+ /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
1849
+ ret = clk_set_defaults(dev);
1850
+ if (ret)
1851
+ debug("%s clk_set_defaults failed %d\n", __func__, ret);
1852
+ else
1853
+ priv->sync_kernel = true;
1854
+
1855
+ return 0;
1856
+}
1857
+
1858
+static int rk3562_clk_ofdata_to_platdata(struct udevice *dev)
1859
+{
1860
+ struct rk3562_clk_priv *priv = dev_get_priv(dev);
1861
+
1862
+ priv->cru = dev_read_addr_ptr(dev);
1863
+
1864
+ return 0;
1865
+}
1866
+
1867
+static int rk3562_clk_bind(struct udevice *dev)
1868
+{
1869
+ struct udevice *sys_child, *sf_child;
1870
+ struct softreset_reg *sf_priv;
1871
+ struct sysreset_reg *priv;
1872
+ int ret;
1873
+
1874
+ /* The reset driver does not have a device node, so bind it here */
1875
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1876
+ &sys_child);
1877
+ if (ret) {
1878
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
1879
+ } else {
1880
+ priv = malloc(sizeof(struct sysreset_reg));
1881
+ priv->glb_srst_fst_value = offsetof(struct rk3562_cru,
1882
+ glb_srst_fst);
1883
+ priv->glb_srst_snd_value = offsetof(struct rk3562_cru,
1884
+ glb_srst_snd);
1885
+ sys_child->priv = priv;
1886
+ }
1887
+
1888
+ ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset",
1889
+ dev_ofnode(dev), &sf_child);
1890
+ if (ret) {
1891
+ debug("Warning: No rockchip reset driver: ret=%d\n", ret);
1892
+ } else {
1893
+ sf_priv = malloc(sizeof(struct softreset_reg));
1894
+ sf_priv->sf_reset_offset = offsetof(struct rk3562_cru,
1895
+ softrst_con[0]);
1896
+ /* (0x30444 - 0x400) / 4 + 1 = 49170 */
1897
+ sf_priv->sf_reset_num = 49170;
1898
+ sf_child->priv = sf_priv;
1899
+ }
1900
+
1901
+ return 0;
1902
+}
1903
+
1904
+static const struct udevice_id rk3562_clk_ids[] = {
1905
+ { .compatible = "rockchip,rk3562-cru" },
1906
+ { }
1907
+};
1908
+
1909
+U_BOOT_DRIVER(rockchip_rk3562_cru) = {
1910
+ .name = "rockchip_rk3562_cru",
1911
+ .id = UCLASS_CLK,
1912
+ .of_match = rk3562_clk_ids,
1913
+ .priv_auto_alloc_size = sizeof(struct rk3562_clk_priv),
1914
+ .ofdata_to_platdata = rk3562_clk_ofdata_to_platdata,
1915
+ .ops = &rk3562_clk_ops,
1916
+ .bind = rk3562_clk_bind,
1917
+ .probe = rk3562_clk_probe,
1918
+};
1919
+
1920
+/* spl scmi clk */
1921
+#ifdef CONFIG_SPL_BUILD
1922
+
1923
+static ulong rk3562_crypto_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
1924
+{
1925
+ struct rk3562_cru *cru = priv->cru;
1926
+ u32 sel, con;
1927
+ ulong rate;
1928
+
1929
+ con = readl(&cru->periclksel_con[43]);
1930
+ switch (clk_id) {
1931
+ case CLK_CORE_CRYPTO:
1932
+ sel = (con & CLK_CORE_CRYPTO_SEL_MASK) >>
1933
+ CLK_CORE_CRYPTO_SEL_SHIFT;
1934
+ if (sel == CLK_CORE_CRYPTO_SEL_200M)
1935
+ rate = 200 * MHz;
1936
+ else if (sel == CLK_CORE_CRYPTO_SEL_100M)
1937
+ rate = 100 * MHz;
1938
+ else
1939
+ rate = OSC_HZ;
1940
+ break;
1941
+ case CLK_PKA_CRYPTO:
1942
+ sel = (con & CLK_PKA_CRYPTO_SEL_MASK) >>
1943
+ CLK_PKA_CRYPTO_SEL_SHIFT;
1944
+ if (sel == CLK_PKA_CRYPTO_SEL_300M)
1945
+ rate = 300 * MHz;
1946
+ else if (sel == CLK_PKA_CRYPTO_SEL_200M)
1947
+ rate = 200 * MHz;
1948
+ else if (sel == CLK_PKA_CRYPTO_SEL_100M)
1949
+ rate = 100 * MHz;
1950
+ else
1951
+ rate = OSC_HZ;
1952
+ break;
1953
+ default:
1954
+ return -ENOENT;
1955
+ }
1956
+
1957
+ return rate;
1958
+}
1959
+
1960
+static ulong rk3562_crypto_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
1961
+ ulong rate)
1962
+{
1963
+ struct rk3562_cru *cru = priv->cru;
1964
+ u32 mask, shift, sel;
1965
+
1966
+ switch (clk_id) {
1967
+ case CLK_CORE_CRYPTO:
1968
+ mask = CLK_CORE_CRYPTO_SEL_MASK;
1969
+ shift = CLK_CORE_CRYPTO_SEL_SHIFT;
1970
+ if (rate == 200 * MHz)
1971
+ sel = CLK_CORE_CRYPTO_SEL_200M;
1972
+ else if (rate == 100 * MHz)
1973
+ sel = CLK_CORE_CRYPTO_SEL_100M;
1974
+ else
1975
+ sel = CLK_CORE_CRYPTO_SEL_24M;
1976
+ break;
1977
+ case CLK_PKA_CRYPTO:
1978
+ mask = CLK_PKA_CRYPTO_SEL_MASK;
1979
+ shift = CLK_PKA_CRYPTO_SEL_SHIFT;
1980
+ if (rate == 300 * MHz)
1981
+ sel = CLK_PKA_CRYPTO_SEL_300M;
1982
+ else if (rate == 200 * MHz)
1983
+ sel = CLK_PKA_CRYPTO_SEL_200M;
1984
+ else if (rate == 100 * MHz)
1985
+ sel = CLK_PKA_CRYPTO_SEL_100M;
1986
+ else
1987
+ sel = CLK_PKA_CRYPTO_SEL_24M;
1988
+ break;
1989
+ default:
1990
+ return -ENOENT;
1991
+ }
1992
+ rk_clrsetreg(&cru->periclksel_con[43], mask, sel << shift);
1993
+
1994
+ return rk3562_crypto_get_rate(priv, clk_id);
1995
+}
1996
+
1997
+static ulong rk3562_clk_scmi_get_rate(struct clk *clk)
1998
+{
1999
+ struct rk3562_clk_priv *priv = dev_get_priv(clk->dev);
2000
+
2001
+ switch (clk->id) {
2002
+ case CLK_CORE_CRYPTO:
2003
+ case CLK_PKA_CRYPTO:
2004
+ return rk3562_crypto_get_rate(priv, clk->id);
2005
+ default:
2006
+ return -ENOENT;
2007
+ }
2008
+};
2009
+
2010
+static ulong rk3562_clk_scmi_set_rate(struct clk *clk, ulong rate)
2011
+{
2012
+ struct rk3562_clk_priv *priv = dev_get_priv(clk->dev);
2013
+
2014
+ switch (clk->id) {
2015
+ case CLK_CORE_CRYPTO:
2016
+ case CLK_PKA_CRYPTO:
2017
+ return rk3562_crypto_set_rate(priv, clk->id, rate);
2018
+ default:
2019
+ return -ENOENT;
2020
+ }
2021
+ return 0;
2022
+};
2023
+
2024
+static int rk3562_scmi_clk_ofdata_to_platdata(struct udevice *dev)
2025
+{
2026
+ struct rk3562_clk_priv *priv = dev_get_priv(dev);
2027
+
2028
+ priv->cru = (struct rk3562_cru *)0xff100000;
2029
+
2030
+ return 0;
2031
+}
2032
+
2033
+/* A fake scmi driver for SPL/TPL where smccc agent is not available. */
2034
+static const struct clk_ops scmi_clk_ops = {
2035
+ .get_rate = rk3562_clk_scmi_get_rate,
2036
+ .set_rate = rk3562_clk_scmi_set_rate,
2037
+};
2038
+
2039
+U_BOOT_DRIVER(scmi_clock) = {
2040
+ .name = "scmi_clk",
2041
+ .id = UCLASS_CLK,
2042
+ .ops = &scmi_clk_ops,
2043
+ .priv_auto_alloc_size = sizeof(struct rk3562_clk_priv),
2044
+ .ofdata_to_platdata = rk3562_scmi_clk_ofdata_to_platdata,
2045
+};
2046
+#endif
u-boot/drivers/clk/rockchip/clk_rk3568.c
....@@ -1,7 +1,7 @@
11 // SPDX-License-Identifier: GPL-2.0
22 /*
33 * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
4
- * Author: Elaine Zhang <zhangqing@rock-chips.com>
4
+ * Author: Joseph Chen <chenjh@rock-chips.com>
55 */
66
77 #include <common.h>
....@@ -1160,7 +1160,7 @@
11601160
11611161 switch (clk_id) {
11621162 case CLK_PWM1:
1163
- sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;
1163
+ sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;
11641164 break;
11651165 case CLK_PWM2:
11661166 sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;
....@@ -1850,7 +1850,7 @@
18501850 rockchip_pll_set_rate(&rk3568_pll_clks[VPLL],
18511851 priv->cru, VPLL, div * rate);
18521852 } else {
1853
- for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) {
1853
+ for (i = sel; i <= DCLK_VOP_SEL_CPLL; i++) {
18541854 switch (i) {
18551855 case DCLK_VOP_SEL_GPLL:
18561856 pll_rate = priv->gpll_hz;
....@@ -3107,9 +3107,15 @@
31073107 if (parent->id == PLL_VPLL) {
31083108 rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
31093109 DCLK_VOP_SEL_VPLL << DCLK0_VOP_SEL_SHIFT);
3110
- } else {
3110
+ } else if (parent->id == PLL_HPLL) {
31113111 rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
31123112 DCLK_VOP_SEL_HPLL << DCLK0_VOP_SEL_SHIFT);
3113
+ } else if (parent->id == PLL_CPLL) {
3114
+ rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
3115
+ DCLK_VOP_SEL_CPLL << DCLK0_VOP_SEL_SHIFT);
3116
+ } else {
3117
+ rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
3118
+ DCLK_VOP_SEL_GPLL << DCLK0_VOP_SEL_SHIFT);
31133119 }
31143120
31153121 return 0;
u-boot/drivers/clk/rockchip/clk_rk3588.c
....@@ -332,12 +332,18 @@
332332
333333 switch (clk_id) {
334334 case ACLK_TOP_ROOT:
335
- src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
335
+ if (!(priv->cpll_hz % rate)) {
336
+ src_clk = ACLK_TOP_ROOT_SRC_SEL_CPLL;
337
+ src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
338
+ } else {
339
+ src_clk = ACLK_TOP_ROOT_SRC_SEL_GPLL;
340
+ src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
341
+ }
336342 assert(src_clk_div - 1 <= 31);
337343 rk_clrsetreg(&cru->clksel_con[8],
338344 ACLK_TOP_ROOT_DIV_MASK |
339345 ACLK_TOP_ROOT_SRC_SEL_MASK,
340
- (ACLK_TOP_ROOT_SRC_SEL_GPLL <<
346
+ (src_clk <<
341347 ACLK_TOP_ROOT_SRC_SEL_SHIFT) |
342348 (src_clk_div - 1) << ACLK_TOP_ROOT_DIV_SHIFT);
343349 break;
....@@ -1148,13 +1154,23 @@
11481154 }
11491155
11501156 if (sel == DCLK_VOP_SRC_SEL_V0PLL) {
1151
- div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate);
1152
- rk_clrsetreg(&cru->clksel_con[conid],
1153
- mask,
1154
- DCLK_VOP_SRC_SEL_V0PLL << sel_shift |
1155
- ((div - 1) << div_shift));
1156
- rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL],
1157
- priv->cru, V0PLL, div * rate);
1157
+ pll_rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],
1158
+ priv->cru, V0PLL);
1159
+ if (pll_rate >= RK3588_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) {
1160
+ div = DIV_ROUND_UP(pll_rate, rate);
1161
+ rk_clrsetreg(&cru->clksel_con[conid],
1162
+ mask,
1163
+ DCLK_VOP_SRC_SEL_V0PLL << sel_shift |
1164
+ ((div - 1) << div_shift));
1165
+ } else {
1166
+ div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate);
1167
+ rk_clrsetreg(&cru->clksel_con[conid],
1168
+ mask,
1169
+ DCLK_VOP_SRC_SEL_V0PLL << sel_shift |
1170
+ ((div - 1) << div_shift));
1171
+ rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL],
1172
+ priv->cru, V0PLL, div * rate);
1173
+ }
11581174 } else {
11591175 for (i = 0; i <= DCLK_VOP_SRC_SEL_AUPLL; i++) {
11601176 switch (i) {
u-boot/drivers/core/device.c
....@@ -97,8 +97,6 @@
9797 debug("%s do not delete uboot dev: %s\n",
9898 __func__, dev->name);
9999 return 0;
100
- } else if (drv->id == UCLASS_REGULATOR) {
101
- /* stay in dm tree, in order to handle exclusion */
102100 } else {
103101 list_del_init(&dev->uclass_node);
104102 }
u-boot/drivers/core/fdtaddr.c
....@@ -127,6 +127,16 @@
127127 return devfdt_get_addr_index(dev, 0);
128128 }
129129
130
+void *devfdt_remap_addr_index(struct udevice *dev, int index)
131
+{
132
+ fdt_addr_t addr = devfdt_get_addr_index(dev, index);
133
+
134
+ if (addr == FDT_ADDR_T_NONE)
135
+ return NULL;
136
+
137
+ return map_physmem(addr, 0, MAP_NOCACHE);
138
+}
139
+
130140 void *devfdt_get_addr_ptr(struct udevice *dev)
131141 {
132142 return (void *)(uintptr_t)devfdt_get_addr_index(dev, 0);
u-boot/drivers/core/read.c
....@@ -8,6 +8,7 @@
88 #include <common.h>
99 #include <dm.h>
1010 #include <mapmem.h>
11
+#include <asm/io.h>
1112 #include <dm/of_access.h>
1213
1314 int dev_read_u32_default(struct udevice *dev, const char *propname, int def)
....@@ -63,6 +64,16 @@
6364 return dev_read_addr_index(dev, 0);
6465 }
6566
67
+void *dev_remap_addr_index(struct udevice *dev, int index)
68
+{
69
+ fdt_addr_t addr = dev_read_addr_index(dev, index);
70
+
71
+ if (addr == FDT_ADDR_T_NONE)
72
+ return NULL;
73
+
74
+ return map_physmem(addr, 0, MAP_NOCACHE);
75
+}
76
+
6677 void *dev_read_addr_ptr(struct udevice *dev)
6778 {
6879 fdt_addr_t addr = dev_read_addr(dev);
u-boot/drivers/core/root.c
....@@ -224,12 +224,8 @@
224224
225225 for (np = node_parent->child; np; np = np->sibling) {
226226 if (pre_reloc_only &&
227
-#ifdef CONFIG_USING_KERNEL_DTB
228
- (!of_find_property(np, "u-boot,dm-pre-reloc", NULL) &&
229
- !of_find_property(np, "u-boot,dm-spl", NULL)))
230
-#else
231
- !of_find_property(np, "u-boot,dm-pre-reloc", NULL))
232
-#endif
227
+ (!of_find_property(np, "u-boot,dm-pre-reloc", NULL) &&
228
+ !of_find_property(np, "u-boot,dm-spl", NULL)))
233229 continue;
234230 if (!of_device_is_available(np)) {
235231 pr_debug(" - ignoring disabled device\n");
....@@ -272,7 +268,6 @@
272268 int offset, bool pre_reloc_only)
273269 {
274270 int ret = 0, err;
275
- const char *name;
276271
277272 for (offset = fdt_first_subnode(blob, offset);
278273 offset > 0;
....@@ -291,11 +286,15 @@
291286 ret);
292287 }
293288
289
+#if CONFIG_IS_ENABLED(SCMI_FIRMWARE)
290
+ const char *name;
291
+
294292 /* There is no compatible in "/firmware", bind it by default. */
295293 name = fdt_get_name(blob, offset, NULL);
296294 if (name && !strcmp(name, "firmware"))
297295 ret = device_bind_driver_to_node(parent, "firmware",
298296 name, offset_to_ofnode(offset), NULL);
297
+#endif
299298 }
300299
301300 if (ret)
u-boot/drivers/cpu/amp.its
....@@ -1,20 +1,22 @@
11 /*
22 * Copyright (C) 2021 Fuzhou Rockchip Electronics Co., Ltd
3
+ *
34 * SPDX-License-Identifier: GPL-2.0
45 */
56
67 /dts-v1/;
78 / {
8
- description = "FIT source file for rockchip AMP";
9
+ description = "Rockchip AMP FIT Image";
910 #address-cells = <1>;
1011
1112 images {
13
+ /* ARM cortex-A core */
1214 amp1 {
1315 description = "bare-mental-core1";
1416 data = /incbin/("./amp1.bin");
15
- type = "firmware";
17
+ type = "firmware"; // must be "firmware"
1618 compression = "none";
17
- arch = "arm"; // "arm64" or "arm"
19
+ arch = "arm"; // "arm64" or "arm", the same as U-Boot state
1820 cpu = <0x100>; // mpidr
1921 thumb = <0>; // 0: arm or thumb2; 1: thumb
2022 hyp = <0>; // 0: el1/svc; 1: el2/hyp
....@@ -56,6 +58,20 @@
5658 algo = "sha256";
5759 };
5860 };
61
+
62
+ /* Other core */
63
+ amp4 {
64
+ description = "standalone-mcu1";
65
+ data = /incbin/("./mcu1.bin");
66
+ type = "standalone"; // must be "standalone"
67
+ compression = "none";
68
+ arch = "arm"; // "arm64" or "arm", the same as U-Boot state
69
+ load = <0x06800000>;
70
+ udelay = <1000000>;
71
+ hash {
72
+ algo = "sha256";
73
+ };
74
+ };
5975 };
6076
6177 configurations {
....@@ -63,7 +79,7 @@
6379 conf {
6480 description = "Rockchip AMP images";
6581 rollback-index = <0x0>;
66
- loadables = "amp1", "amp2", "amp3";
82
+ loadables = "amp1", "amp2", "amp3", "amp4";
6783
6884 signature {
6985 algo = "sha256,rsa2048";
u-boot/drivers/cpu/rockchip_amp.c
....@@ -134,7 +134,7 @@
134134 flush_dcache_all();
135135
136136 /* fixup: ramdisk/fdt/entry depend on U-Boot */
137
- *entry = env_get_ulong("kernel_addr_r", 16, 0);
137
+ *entry = (u32)images.ep;
138138
139139 return 0;
140140 }
....@@ -206,6 +206,31 @@
206206 return 0;
207207 }
208208
209
+__weak int fit_standalone_release(char *id, uintptr_t entry_point)
210
+{
211
+ return 0;
212
+}
213
+
214
+static int standalone_handler(const char *id, u32 entry_point, int data_size)
215
+{
216
+ int ret;
217
+
218
+ if (!sysmem_alloc_base_by_name(id,
219
+ (phys_addr_t)entry_point, data_size))
220
+ return -ENXIO;
221
+
222
+ printf("Handle standalone: '%s' at 0x%08x ...", id, entry_point);
223
+
224
+ ret = fit_standalone_release((char *)id, entry_point);
225
+ if (ret) {
226
+ printf("failed, ret=%d\n", ret);
227
+ return ret;
228
+ }
229
+ printf("OK\n");
230
+
231
+ return 0;
232
+}
233
+
209234 static int brought_up_amp(void *fit, int noffset,
210235 boot_cpu_t *bootcpu, int is_linux)
211236 {
....@@ -217,27 +242,38 @@
217242 int boot_on;
218243 int data_size;
219244 int i, ret;
220
- u8 arch = -ENODATA;
245
+ u8 type = -ENODATA;
246
+ u8 arch = -ENODATA;
221247
222248 desc = fdt_getprop(fit, noffset, "description", NULL);
223249 cpu = fit_get_u32_default(fit, noffset, "cpu", -ENODATA);
224250 hyp = fit_get_u32_default(fit, noffset, "hyp", 0);
225251 thumb = fit_get_u32_default(fit, noffset, "thumb", 0);
226
- load = fit_get_u32_default(fit, noffset, "load", -ENODATA);
252
+ entry = load = fit_get_u32_default(fit, noffset, "load", -ENODATA);
227253 us = fit_get_u32_default(fit, noffset, "udelay", 0);
228254 boot_on = fit_get_u32_default(fit, noffset, "boot-on", 1);
229255 fit_image_get_arch(fit, noffset, &arch);
256
+ fit_image_get_type(fit, noffset, &type);
230257 fit_image_get_data_size(fit, noffset, &data_size);
231258 memset(&args, 0, sizeof(args));
232259
233
- if (!desc || cpu == -ENODATA || arch == -ENODATA ||
260
+ /* standalone is simple, just handle it and then exit. Allow failure */
261
+ if (type == IH_TYPE_STANDALONE) {
262
+ if (!desc || load == -ENODATA) {
263
+ AMP_E("standalone: \"desc\" or \"load\" property missing!\n");
264
+ goto exit;
265
+ }
266
+ standalone_handler(desc, load, data_size);
267
+ goto exit;
268
+ }
269
+
270
+ if (!desc || cpu == -ENODATA || arch == -ENODATA || type == -ENODATA ||
234271 (load == -ENODATA && !is_linux)) {
235272 AMP_E("Property missing!\n");
236273 return -EINVAL;
237274 }
238275 aarch64 = (arch == IH_ARCH_ARM) ? 0 : 1;
239276 pe_state = PE_STATE(aarch64, hyp, thumb, 0);
240
- entry = load;
241277
242278 #ifdef DEBUG
243279 AMP_I(" desc: %s\n", desc);
....@@ -245,7 +281,7 @@
245281 AMP_I(" aarch64: %d\n", aarch64);
246282 AMP_I(" hyp: %d\n", hyp);
247283 AMP_I(" thumb: %d\n", thumb);
248
- AMP_I(" entry: 0x%08x\n", entry);
284
+ AMP_I(" load: 0x%08x\n", load);
249285 AMP_I(" pe_state: 0x%08x\n", pe_state);
250286 AMP_I(" linux-os: %d\n\n", is_linux);
251287 #endif
....@@ -294,7 +330,7 @@
294330 ret = smc_cpu_on(cpu, pe_state, entry, &args, is_linux);
295331 if (ret)
296332 return ret;
297
-
333
+exit:
298334 if (us)
299335 udelay(us);
300336
....@@ -336,7 +372,7 @@
336372
337373 /* === only boot cpu can reach here === */
338374
339
- if (!g_bootcpu.linux_os) {
375
+ if (!g_bootcpu.linux_os && g_bootcpu.entry) {
340376 flush_dcache_all();
341377 AMP_I("Brought up cpu[%x, self] with state 0x%x, entry 0x%08x ...",
342378 (u32)read_mpidr() & 0x0fff, g_bootcpu.state, g_bootcpu.entry);
u-boot/drivers/crypto/rockchip/crypto_v2.c
....@@ -8,6 +8,7 @@
88 #include <crypto.h>
99 #include <dm.h>
1010 #include <asm/io.h>
11
+#include <clk-uclass.h>
1112 #include <asm/arch/hardware.h>
1213 #include <asm/arch/clock.h>
1314 #include <rockchip/crypto_hash_cache.h>
....@@ -54,6 +55,7 @@
5455 char *clocks;
5556 u32 *frequencies;
5657 u32 nclocks;
58
+ u32 freq_nclocks;
5759 u32 length;
5860 struct rk_hash_ctx *hw_ctx;
5961 struct rk_crypto_soc_data *soc_data;
....@@ -217,6 +219,43 @@
217219
218220 for (i = 0; i < tag_len / 4; i++, chn_base += 4)
219221 word2byte_be(crypto_read(chn_base), tag + 4 * i);
222
+}
223
+
224
+static int rk_crypto_do_enable_clk(struct udevice *dev, int enable)
225
+{
226
+ struct rockchip_crypto_priv *priv = dev_get_priv(dev);
227
+ struct clk clk;
228
+ int i, ret;
229
+
230
+ for (i = 0; i < priv->nclocks; i++) {
231
+ ret = clk_get_by_index(dev, i, &clk);
232
+ if (ret < 0) {
233
+ printf("Failed to get clk index %d, ret=%d\n", i, ret);
234
+ return ret;
235
+ }
236
+
237
+ if (enable)
238
+ ret = clk_enable(&clk);
239
+ else
240
+ ret = clk_disable(&clk);
241
+ if (ret < 0 && ret != -ENOSYS) {
242
+ printf("Failed to enable(%d) clk(%ld): ret=%d\n",
243
+ enable, clk.id, ret);
244
+ return ret;
245
+ }
246
+ }
247
+
248
+ return 0;
249
+}
250
+
251
+static int rk_crypto_enable_clk(struct udevice *dev)
252
+{
253
+ return rk_crypto_do_enable_clk(dev, 1);
254
+}
255
+
256
+static int rk_crypto_disable_clk(struct udevice *dev)
257
+{
258
+ return rk_crypto_do_enable_clk(dev, 0);
220259 }
221260
222261 static u32 crypto_v3_dynamic_cap(void)
....@@ -397,7 +436,7 @@
397436
398437 if (!(*started_flag)) {
399438 lli->user_define |=
400
- (LLI_USER_STRING_START | LLI_USER_CPIHER_START);
439
+ (LLI_USER_STRING_START | LLI_USER_CIPHER_START);
401440 crypto_write((u32)virt_to_phys(lli), CRYPTO_DMA_LLI_ADDR);
402441 crypto_write((CRYPTO_HASH_ENABLE << CRYPTO_WRITE_MASK_SHIFT) |
403442 CRYPTO_HASH_ENABLE, CRYPTO_HASH_CTL);
....@@ -520,6 +559,7 @@
520559 {
521560 struct rockchip_crypto_priv *priv = dev_get_priv(dev);
522561 struct rk_hash_ctx *hash_ctx = priv->hw_ctx;
562
+ int ret = 0;
523563
524564 if (!ctx)
525565 return -EINVAL;
....@@ -535,7 +575,12 @@
535575 if (!hash_ctx->hash_cache)
536576 return -EFAULT;
537577
538
- return rk_hash_init(hash_ctx, ctx->algo);
578
+ rk_crypto_enable_clk(dev);
579
+ ret = rk_hash_init(hash_ctx, ctx->algo);
580
+ if (ret)
581
+ rk_crypto_disable_clk(dev);
582
+
583
+ return ret;
539584 }
540585
541586 static int rockchip_crypto_sha_update(struct udevice *dev,
....@@ -545,8 +590,10 @@
545590 int ret, i;
546591 u8 *p;
547592
548
- if (!len)
549
- return -EINVAL;
593
+ if (!len) {
594
+ ret = -EINVAL;
595
+ goto exit;
596
+ }
550597
551598 p = (u8 *)input;
552599
....@@ -560,6 +607,9 @@
560607 ret = rk_hash_update(priv->hw_ctx, p, len % HASH_UPDATE_LIMIT);
561608
562609 exit:
610
+ if (ret)
611
+ rk_crypto_disable_clk(dev);
612
+
563613 return ret;
564614 }
565615
....@@ -583,6 +633,8 @@
583633
584634 exit:
585635 hw_hash_clean_ctx(priv->hw_ctx);
636
+ rk_crypto_disable_clk(dev);
637
+
586638 return ret;
587639 }
588640
....@@ -614,6 +666,7 @@
614666 {
615667 struct rockchip_crypto_priv *priv = dev_get_priv(dev);
616668 struct rk_hash_ctx *hash_ctx = priv->hw_ctx;
669
+ int ret = 0;
617670
618671 if (!ctx)
619672 return -EINVAL;
....@@ -629,7 +682,12 @@
629682 if (!hash_ctx->hash_cache)
630683 return -EFAULT;
631684
632
- return rk_hmac_init(priv->hw_ctx, ctx->algo, key, key_len);
685
+ rk_crypto_enable_clk(dev);
686
+ ret = rk_hmac_init(priv->hw_ctx, ctx->algo, key, key_len);
687
+ if (ret)
688
+ rk_crypto_disable_clk(dev);
689
+
690
+ return ret;
633691 }
634692
635693 static int rockchip_crypto_hmac_update(struct udevice *dev,
....@@ -763,6 +821,11 @@
763821 {
764822 u32 i;
765823
824
+ if (aad_len == 0) {
825
+ *padding_size = 0;
826
+ return;
827
+ }
828
+
766829 i = aad_len < (0x10000 - 0x100) ? 2 : 6;
767830
768831 if (i == 2) {
....@@ -779,7 +842,7 @@
779842 *padding_size = i;
780843 }
781844
782
-static int ccm_compose_aad_iv(u8 *aad_iv, u32 data_len, u32 tag_size)
845
+static int ccm_compose_aad_iv(u8 *aad_iv, u32 data_len, u32 aad_len, u32 tag_size)
783846 {
784847 aad_iv[0] |= ((u8)(((tag_size - 2) / 2) & 7) << 3);
785848
....@@ -788,7 +851,8 @@
788851 aad_iv[14] = (u8)(data_len >> 8);
789852 aad_iv[15] = (u8)data_len;
790853
791
- aad_iv[0] |= 0x40; //set aad flag
854
+ if (aad_len)
855
+ aad_iv[0] |= 0x40; //set aad flag
792856
793857 return 0;
794858 }
....@@ -925,12 +989,14 @@
925989 data_desc->dma_ctrl |= LLI_DMA_CTRL_DST_DONE;
926990 }
927991
992
+ data_desc->user_define = LLI_USER_CIPHER_START |
993
+ LLI_USER_STRING_START |
994
+ LLI_USER_STRING_LAST |
995
+ (key_chn << 4);
996
+ crypto_write((u32)virt_to_phys(data_desc), CRYPTO_DMA_LLI_ADDR);
997
+
928998 if (rk_mode == RK_MODE_CCM || rk_mode == RK_MODE_GCM) {
929999 u32 aad_tmp_len = 0;
930
-
931
- data_desc->user_define = LLI_USER_STRING_START |
932
- LLI_USER_STRING_LAST |
933
- (key_chn << 4);
9341000
9351001 aad_desc = align_malloc(sizeof(*aad_desc), LLI_ADDR_ALIGN_SIZE);
9361002 if (!aad_desc)
....@@ -938,7 +1004,7 @@
9381004
9391005 memset(aad_desc, 0x00, sizeof(*aad_desc));
9401006 aad_desc->next_addr = (u32)virt_to_phys(data_desc);
941
- aad_desc->user_define = LLI_USER_CPIHER_START |
1007
+ aad_desc->user_define = LLI_USER_CIPHER_START |
9421008 LLI_USER_STRING_START |
9431009 LLI_USER_STRING_LAST |
9441010 LLI_USER_STRING_AAD |
....@@ -958,12 +1024,15 @@
9581024 if (!aad_tmp)
9591025 goto exit;
9601026
961
- /* read iv data from reg */
962
- get_iv_reg(key_chn, aad_tmp, AES_BLOCK_SIZE);
963
- ccm_compose_aad_iv(aad_tmp, tmp_len, tag_len);
964
- memcpy(aad_tmp + AES_BLOCK_SIZE, padding, padding_size);
1027
+ /* clear last block */
9651028 memset(aad_tmp + aad_tmp_len - AES_BLOCK_SIZE,
9661029 0x00, AES_BLOCK_SIZE);
1030
+
1031
+ /* read iv data from reg */
1032
+ get_iv_reg(key_chn, aad_tmp, AES_BLOCK_SIZE);
1033
+ ccm_compose_aad_iv(aad_tmp, tmp_len, aad_len, tag_len);
1034
+ memcpy(aad_tmp + AES_BLOCK_SIZE, padding, padding_size);
1035
+
9671036 memcpy(aad_tmp + AES_BLOCK_SIZE + padding_size,
9681037 aad, aad_len);
9691038 } else {
....@@ -985,15 +1054,15 @@
9851054
9861055 aad_desc->src_addr = (u32)virt_to_phys(aad_tmp);
9871056 aad_desc->src_len = aad_tmp_len;
988
- crypto_write((u32)virt_to_phys(aad_desc), CRYPTO_DMA_LLI_ADDR);
989
- cache_op_inner(DCACHE_AREA_CLEAN, aad_tmp, aad_tmp_len);
990
- cache_op_inner(DCACHE_AREA_CLEAN, aad_desc, sizeof(*aad_desc));
991
- } else {
992
- data_desc->user_define = LLI_USER_CPIHER_START |
993
- LLI_USER_STRING_START |
994
- LLI_USER_STRING_LAST |
995
- (key_chn << 4);
996
- crypto_write((u32)virt_to_phys(data_desc), CRYPTO_DMA_LLI_ADDR);
1057
+
1058
+ if (aad_tmp_len) {
1059
+ data_desc->user_define = LLI_USER_STRING_START |
1060
+ LLI_USER_STRING_LAST |
1061
+ (key_chn << 4);
1062
+ crypto_write((u32)virt_to_phys(aad_desc), CRYPTO_DMA_LLI_ADDR);
1063
+ cache_op_inner(DCACHE_AREA_CLEAN, aad_tmp, aad_tmp_len);
1064
+ cache_op_inner(DCACHE_AREA_CLEAN, aad_desc, sizeof(*aad_desc));
1065
+ }
9971066 }
9981067
9991068 cache_op_inner(DCACHE_AREA_CLEAN, data_desc, sizeof(*data_desc));
....@@ -1175,21 +1244,29 @@
11751244 int rockchip_crypto_cipher(struct udevice *dev, cipher_context *ctx,
11761245 const u8 *in, u8 *out, u32 len, bool enc)
11771246 {
1247
+ int ret;
1248
+
1249
+ rk_crypto_enable_clk(dev);
1250
+
11781251 switch (ctx->algo) {
11791252 case CRYPTO_DES:
1180
- return rk_crypto_des(dev, ctx->mode, ctx->key, ctx->key_len,
1181
- ctx->iv, in, out, len, enc);
1253
+ ret = rk_crypto_des(dev, ctx->mode, ctx->key, ctx->key_len,
1254
+ ctx->iv, in, out, len, enc);
11821255 case CRYPTO_AES:
1183
- return rk_crypto_aes(dev, ctx->mode,
1184
- ctx->key, ctx->twk_key, ctx->key_len,
1185
- ctx->iv, ctx->iv_len, in, out, len, enc);
1256
+ ret = rk_crypto_aes(dev, ctx->mode,
1257
+ ctx->key, ctx->twk_key, ctx->key_len,
1258
+ ctx->iv, ctx->iv_len, in, out, len, enc);
11861259 case CRYPTO_SM4:
1187
- return rk_crypto_sm4(dev, ctx->mode,
1188
- ctx->key, ctx->twk_key, ctx->key_len,
1189
- ctx->iv, ctx->iv_len, in, out, len, enc);
1260
+ ret = rk_crypto_sm4(dev, ctx->mode,
1261
+ ctx->key, ctx->twk_key, ctx->key_len,
1262
+ ctx->iv, ctx->iv_len, in, out, len, enc);
11901263 default:
1191
- return -EINVAL;
1264
+ ret = -EINVAL;
11921265 }
1266
+
1267
+ rk_crypto_disable_clk(dev);
1268
+
1269
+ return ret;
11931270 }
11941271
11951272 int rk_crypto_mac(struct udevice *dev, u32 algo, u32 mode,
....@@ -1223,8 +1300,16 @@
12231300 int rockchip_crypto_mac(struct udevice *dev, cipher_context *ctx,
12241301 const u8 *in, u32 len, u8 *tag)
12251302 {
1226
- return rk_crypto_mac(dev, ctx->algo, ctx->mode,
1227
- ctx->key, ctx->key_len, in, len, tag);
1303
+ int ret = 0;
1304
+
1305
+ rk_crypto_enable_clk(dev);
1306
+
1307
+ ret = rk_crypto_mac(dev, ctx->algo, ctx->mode,
1308
+ ctx->key, ctx->key_len, in, len, tag);
1309
+
1310
+ rk_crypto_disable_clk(dev);
1311
+
1312
+ return ret;
12281313 }
12291314
12301315 int rk_crypto_ae(struct udevice *dev, u32 algo, u32 mode,
....@@ -1236,6 +1321,9 @@
12361321 int ret;
12371322
12381323 if (!IS_AE_MODE(rk_mode))
1324
+ return -EINVAL;
1325
+
1326
+ if (len == 0)
12391327 return -EINVAL;
12401328
12411329 if (algo != CRYPTO_AES && algo != CRYPTO_SM4)
....@@ -1261,9 +1349,17 @@
12611349 u8 *out, u8 *tag)
12621350
12631351 {
1264
- return rk_crypto_ae(dev, ctx->algo, ctx->mode, ctx->key, ctx->key_len,
1265
- ctx->iv, ctx->iv_len, in, len,
1266
- aad, aad_len, out, tag);
1352
+ int ret = 0;
1353
+
1354
+ rk_crypto_enable_clk(dev);
1355
+
1356
+ ret = rk_crypto_ae(dev, ctx->algo, ctx->mode, ctx->key, ctx->key_len,
1357
+ ctx->iv, ctx->iv_len, in, len,
1358
+ aad, aad_len, out, tag);
1359
+
1360
+ rk_crypto_disable_clk(dev);
1361
+
1362
+ return ret;
12671363 }
12681364
12691365 #endif
....@@ -1312,9 +1408,11 @@
13121408 if (ret)
13131409 goto exit;
13141410
1411
+ rk_crypto_enable_clk(dev);
13151412 ret = rk_exptmod_np(mpa_m, mpa_e, mpa_n, mpa_c, mpa_result);
13161413 if (!ret)
13171414 memcpy(output, mpa_result->d, BITS2BYTE(n_bits));
1415
+ rk_crypto_disable_clk(dev);
13181416
13191417 exit:
13201418 rk_mpa_free(&mpa_m);
....@@ -1378,7 +1476,7 @@
13781476 if (!priv->clocks)
13791477 return -ENOMEM;
13801478
1381
- priv->nclocks = len / sizeof(u32);
1479
+ priv->nclocks = len / (2 * sizeof(u32));
13821480 if (dev_read_u32_array(dev, "clocks", (u32 *)priv->clocks,
13831481 priv->nclocks)) {
13841482 printf("Can't read \"clocks\" property\n");
....@@ -1386,24 +1484,19 @@
13861484 goto exit;
13871485 }
13881486
1389
- if (!dev_read_prop(dev, "clock-frequency", &len)) {
1390
- printf("Can't find \"clock-frequency\" property\n");
1391
- ret = -EINVAL;
1392
- goto exit;
1393
- }
1394
-
1395
- priv->frequencies = malloc(len);
1396
- if (!priv->frequencies) {
1397
- ret = -ENOMEM;
1398
- goto exit;
1399
- }
1400
-
1401
- priv->nclocks = len / sizeof(u32);
1402
- if (dev_read_u32_array(dev, "clock-frequency", priv->frequencies,
1403
- priv->nclocks)) {
1404
- printf("Can't read \"clock-frequency\" property\n");
1405
- ret = -EINVAL;
1406
- goto exit;
1487
+ if (dev_read_prop(dev, "clock-frequency", &len)) {
1488
+ priv->frequencies = malloc(len);
1489
+ if (!priv->frequencies) {
1490
+ ret = -ENOMEM;
1491
+ goto exit;
1492
+ }
1493
+ priv->freq_nclocks = len / sizeof(u32);
1494
+ if (dev_read_u32_array(dev, "clock-frequency", priv->frequencies,
1495
+ priv->freq_nclocks)) {
1496
+ printf("Can't read \"clock-frequency\" property\n");
1497
+ ret = -EINVAL;
1498
+ goto exit;
1499
+ }
14071500 }
14081501
14091502 return 0;
....@@ -1423,10 +1516,15 @@
14231516 struct clk clk;
14241517 int i, ret;
14251518
1426
- if (!priv->clocks && priv->nclocks == 0)
1519
+ /* use standard "assigned-clock-rates" props */
1520
+ if (dev_read_size(dev, "assigned-clock-rates") > 0)
1521
+ return clk_set_defaults(dev);
1522
+
1523
+ /* use "clock-frequency" props */
1524
+ if (priv->freq_nclocks == 0)
14271525 return 0;
14281526
1429
- for (i = 0; i < priv->nclocks; i++) {
1527
+ for (i = 0; i < priv->freq_nclocks; i++) {
14301528 ret = clk_get_by_index(dev, i, &clk);
14311529 if (ret < 0) {
14321530 printf("Failed to get clk index %d, ret=%d\n", i, ret);
....@@ -1465,7 +1563,11 @@
14651563 if (ret)
14661564 return ret;
14671565
1566
+ rk_crypto_enable_clk(dev);
1567
+
14681568 hw_crypto_reset();
1569
+
1570
+ rk_crypto_disable_clk(dev);
14691571
14701572 return 0;
14711573 }
....@@ -1557,6 +1659,10 @@
15571659 .compatible = "rockchip,crypto-v3",
15581660 .data = (ulong)&soc_data_cryptov3
15591661 },
1662
+ {
1663
+ .compatible = "rockchip,crypto-v4",
1664
+ .data = (ulong)&soc_data_cryptov3 /* reuse crypto v3 config */
1665
+ },
15601666 { }
15611667 };
15621668
u-boot/drivers/gpio/Kconfig
....@@ -24,6 +24,15 @@
2424 is a mechanism providing automatic GPIO request and config-
2525 uration as part of the gpio-controller's driver probe function.
2626
27
+config GPIO_NO_UC_FLAG_SEQ_ALIAS
28
+ bool "Disable GPIO uclass sequence themselves with aliases"
29
+ depends on USING_KERNEL_DTB
30
+ default n
31
+ help
32
+ Disable GPIO uclass sequence, this is a workaround when kernel
33
+ dtb feature is enabled. Avoid gpio device probe failed when
34
+ alloc req_seq both for gpio devices from U-Boot and kernel dtb.
35
+
2736 config ALTERA_PIO
2837 bool "Altera PIO driver"
2938 depends on DM_GPIO
....@@ -211,12 +220,6 @@
211220 Support for the GPIO controller contained in NVIDIA Tegra186. This
212221 covers both the "main" and "AON" controller instances, even though
213222 they have slightly different register layout.
214
-
215
-config GPIO_MAX96752F
216
- bool "Maxim MAX96752F GPIO"
217
- depends on DM_GPIO && I2C_MUX_MAX96752F
218
- help
219
- Say yes here to support Maxim MAX96752F GPIOs.
220223
221224 config GPIO_UNIPHIER
222225 bool "UniPhier GPIO"
u-boot/drivers/gpio/Makefile
....@@ -8,7 +8,6 @@
88 ifndef CONFIG_SPL_BUILD
99 obj-$(CONFIG_DWAPB_GPIO) += dwapb_gpio.o
1010 obj-$(CONFIG_AXP_GPIO) += axp_gpio.o
11
-obj-$(CONFIG_GPIO_MAX96752F) += gpio-max96752f.o
1211 endif
1312 obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
1413
u-boot/drivers/gpio/gpio-max96752f.c
deleted file mode 100644
....@@ -1,90 +0,0 @@
1
-// SPDX-License-Identifier: GPL-2.0+
2
-/*
3
- * (C) Copyright 2022 Rockchip Electronics Co., Ltd
4
- */
5
-
6
-#include <asm-generic/gpio.h>
7
-#include <common.h>
8
-#include <dm.h>
9
-#include <i2c.h>
10
-#include <max96752f.h>
11
-
12
-static int max96752f_gpio_direction_output(struct udevice *dev, unsigned offset,
13
- int value)
14
-{
15
- int ret;
16
-
17
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(offset),
18
- GPIO_OUT_DIS | GPIO_OUT,
19
- FIELD_PREP(GPIO_OUT_DIS, 0) |
20
- FIELD_PREP(GPIO_OUT, value));
21
- if (ret < 0)
22
- return ret;
23
-
24
- return 0;
25
-}
26
-
27
-static int max96752f_gpio_get_value(struct udevice *dev, unsigned offset)
28
-{
29
- int ret;
30
-
31
- ret = dm_i2c_reg_read(dev->parent, GPIO_A_REG(offset));
32
- if (ret < 0)
33
- return ret;
34
-
35
- return FIELD_GET(GPIO_OUT, ret);
36
-}
37
-
38
-static int max96752f_gpio_set_value(struct udevice *dev, unsigned offset,
39
- int value)
40
-{
41
- int ret;
42
-
43
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(offset), GPIO_OUT,
44
- FIELD_PREP(GPIO_OUT, value));
45
- if (ret < 0)
46
- return ret;
47
-
48
- return 0;
49
-}
50
-
51
-static int max96752f_gpio_get_function(struct udevice *dev, unsigned offset)
52
-{
53
- int ret;
54
-
55
- ret = dm_i2c_reg_read(dev->parent, GPIO_A_REG(offset));
56
- if (ret < 0)
57
- return ret;
58
-
59
- return FIELD_GET(GPIO_OUT_DIS, ret) ? GPIOF_INPUT : GPIOF_OUTPUT;
60
-}
61
-
62
-static const struct dm_gpio_ops max96752f_gpio_ops = {
63
- .direction_output = max96752f_gpio_direction_output,
64
- .get_value = max96752f_gpio_get_value,
65
- .set_value = max96752f_gpio_set_value,
66
- .get_function = max96752f_gpio_get_function,
67
-};
68
-
69
-static int max96752f_gpio_probe(struct udevice *dev)
70
-{
71
- struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
72
-
73
- uc_priv->gpio_count = 16;
74
- uc_priv->bank_name = of_node_full_name(dev_np(dev));
75
-
76
- return 0;
77
-}
78
-
79
-static const struct udevice_id max96752f_gpio_match[] = {
80
- { .compatible = "maxim,max96752f-gpio" },
81
- { }
82
-};
83
-
84
-U_BOOT_DRIVER(max96752f_gpio) = {
85
- .name = "max96752f_gpio",
86
- .id = UCLASS_GPIO,
87
- .of_match = max96752f_gpio_match,
88
- .probe = max96752f_gpio_probe,
89
- .ops = &max96752f_gpio_ops,
90
-};
u-boot/drivers/gpio/gpio-uclass.c
....@@ -1058,7 +1058,9 @@
10581058 UCLASS_DRIVER(gpio) = {
10591059 .id = UCLASS_GPIO,
10601060 .name = "gpio",
1061
+#ifndef CONFIG_GPIO_NO_UC_FLAG_SEQ_ALIAS
10611062 .flags = DM_UC_FLAG_SEQ_ALIAS,
1063
+#endif
10621064 .post_probe = gpio_post_probe,
10631065 .post_bind = gpio_post_bind,
10641066 .pre_remove = gpio_pre_remove,
u-boot/drivers/gpio/rk_gpio.c
....@@ -130,7 +130,6 @@
130130 struct rockchip_pinctrl_priv *pctrl_priv;
131131 struct rockchip_pin_bank *bank;
132132 char *end = NULL;
133
- static int gpio;
134133 int id = -1, ret;
135134
136135 priv->regs = dev_read_addr_ptr(dev);
....@@ -152,14 +151,12 @@
152151 end = strrchr(dev->name, '@');
153152 if (end)
154153 id = trailing_strtoln(dev->name, end);
155
- else
154
+ if (id < 0)
156155 dev_read_alias_seq(dev, &id);
157156
158
- if (id < 0)
159
- id = gpio++;
160
-
161
- if (id >= pctrl_priv->ctrl->nr_banks) {
162
- dev_err(dev, "bank id invalid\n");
157
+ if (id < 0 || id >= pctrl_priv->ctrl->nr_banks) {
158
+ dev_err(dev, "nr_banks=%d, bank id=%d invalid\n",
159
+ pctrl_priv->ctrl->nr_banks, id);
163160 return -EINVAL;
164161 }
165162
u-boot/drivers/i2c/muxes/Kconfig
....@@ -51,13 +51,6 @@
5151 If you say yes here you get support for the Maxim MAX96745
5252 I2C multiplexer.
5353
54
-config I2C_MUX_MAX96752F
55
- tristate "Maxim MAX96752F I2C multiplexer"
56
- depends on I2C_MUX
57
- help
58
- If you say yes here you get support for the Maxim MAX96752F
59
- I2C multiplexer.
60
-
6154 config I2C_MUX_MAX96755F
6255 tristate "Maxim MAX96755F I2C multiplexer"
6356 depends on I2C_MUX
u-boot/drivers/i2c/muxes/Makefile
....@@ -8,6 +8,5 @@
88 obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o
99 obj-$(CONFIG_I2C_MUX_GPIO) += i2c-mux-gpio.o
1010 obj-$(CONFIG_I2C_MUX_MAX96745) += max96745.o
11
-obj-$(CONFIG_I2C_MUX_MAX96752F) += max96752f.o
1211 obj-$(CONFIG_I2C_MUX_MAX96755F) += max96755f.o
1312
u-boot/drivers/i2c/muxes/max96745.c
....@@ -13,11 +13,18 @@
1313 struct max96745_priv {
1414 struct udevice *dev;
1515 struct gpio_desc enable_gpio;
16
+ struct gpio_desc pwdnb_gpio;
17
+ bool idle_disc;
1618 };
1719
1820 static int max96745_select(struct udevice *mux, struct udevice *bus,
1921 uint channel)
2022 {
23
+ struct max96745_priv *priv = dev_get_priv(mux);
24
+
25
+ if (!priv->idle_disc)
26
+ return 0;
27
+
2128 if (channel == 1)
2229 dm_i2c_reg_clrset(mux, 0x0086, DIS_REM_CC,
2330 FIELD_PREP(DIS_REM_CC, 0));
....@@ -31,6 +38,11 @@
3138 static int max96745_deselect(struct udevice *mux, struct udevice *bus,
3239 uint channel)
3340 {
41
+ struct max96745_priv *priv = dev_get_priv(mux);
42
+
43
+ if (!priv->idle_disc)
44
+ return 0;
45
+
3446 if (channel == 1)
3547 dm_i2c_reg_clrset(mux, 0x0086, DIS_REM_CC,
3648 FIELD_PREP(DIS_REM_CC, 1));
....@@ -55,15 +67,27 @@
5567 mdelay(200);
5668 }
5769
58
- ret = dm_i2c_reg_clrset(priv->dev, 0x0076, DIS_REM_CC,
59
- FIELD_PREP(DIS_REM_CC, 1));
70
+ if (dm_gpio_is_valid(&priv->pwdnb_gpio)) {
71
+ dm_gpio_set_value(&priv->pwdnb_gpio, 0);
72
+ mdelay(30);
73
+ }
74
+
75
+ /* Set for I2C Fast-mode speed */
76
+ ret = dm_i2c_reg_write(priv->dev, 0x0070, 0x16);
6077 if (ret < 0)
6178 return ret;
6279
63
- ret = dm_i2c_reg_clrset(priv->dev, 0x0086, DIS_REM_CC,
64
- FIELD_PREP(DIS_REM_CC, 1));
65
- if (ret < 0)
66
- return ret;
80
+ if (priv->idle_disc) {
81
+ ret = dm_i2c_reg_clrset(priv->dev, 0x0076, DIS_REM_CC,
82
+ FIELD_PREP(DIS_REM_CC, 1));
83
+ if (ret < 0)
84
+ return ret;
85
+
86
+ ret = dm_i2c_reg_clrset(priv->dev, 0x0086, DIS_REM_CC,
87
+ FIELD_PREP(DIS_REM_CC, 1));
88
+ if (ret < 0)
89
+ return ret;
90
+ }
6791
6892 return 0;
6993 }
....@@ -78,6 +102,7 @@
78102 return ret;
79103
80104 priv->dev = dev;
105
+ priv->idle_disc = dev_read_bool(dev, "i2c-mux-idle-disconnect");
81106
82107 ret = gpio_request_by_name(dev, "enable-gpios", 0,
83108 &priv->enable_gpio, GPIOD_IS_OUT);
....@@ -86,6 +111,13 @@
86111 return ret;
87112 }
88113
114
+ ret = gpio_request_by_name(dev, "pwdnb-gpios", 0,
115
+ &priv->pwdnb_gpio, GPIOD_IS_OUT);
116
+ if (ret && ret != -ENOENT) {
117
+ dev_err(dev, "%s: failed to get pwdnb GPIO: %d\n", __func__, ret);
118
+ return ret;
119
+ }
120
+
89121 max96745_power_on(priv);
90122
91123 return 0;
u-boot/drivers/i2c/muxes/max96752f.c
deleted file mode 100644
....@@ -1,100 +0,0 @@
1
-// SPDX-License-Identifier: GPL-2.0+
2
-/*
3
- * (C) Copyright 2022 Rockchip Electronics Co., Ltd
4
- */
5
-
6
-#include <common.h>
7
-#include <dm.h>
8
-#include <errno.h>
9
-#include <i2c.h>
10
-#include <max96752f.h>
11
-
12
-#include <asm-generic/gpio.h>
13
-
14
-static int max96752f_select(struct udevice *mux, struct udevice *bus,
15
- uint channel)
16
-{
17
- return 0;
18
-}
19
-
20
-static int max96752f_deselect(struct udevice *mux, struct udevice *bus,
21
- uint channel)
22
-{
23
- return 0;
24
-}
25
-
26
-static const struct i2c_mux_ops max96752f_ops = {
27
- .select = max96752f_select,
28
- .deselect = max96752f_deselect,
29
-};
30
-
31
-static uint addr_list[] = {
32
- 0x48, 0x68, 0x6a, 0x4a, 0x4c, 0x6c, 0x28, 0x2a
33
-};
34
-
35
-void max96752f_init(struct udevice *dev)
36
-{
37
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
38
- u32 stream_id = dev_read_u32_default(dev->parent, "reg", 0);
39
- uint addr = chip->chip_addr;
40
- int i, ret;
41
-
42
- for (i = 0; i < ARRAY_SIZE(addr_list); i++) {
43
- chip->chip_addr = addr_list[i];
44
-
45
- ret = dm_i2c_reg_read(dev, 0x000d);
46
- if (ret < 0)
47
- continue;
48
-
49
- if (ret == 0x82) {
50
- dm_i2c_reg_write(dev, 0x0000, addr << 1);
51
- break;
52
- }
53
- }
54
-
55
- chip->chip_addr = addr;
56
-
57
- dm_i2c_reg_clrset(dev, 0x0050, STR_SEL,
58
- FIELD_PREP(STR_SEL, stream_id));
59
- dm_i2c_reg_clrset(dev, 0x0073, TX_SRC_ID,
60
- FIELD_PREP(TX_SRC_ID, stream_id));
61
-}
62
-
63
-static int max96752f_probe(struct udevice *dev)
64
-{
65
- struct gpio_desc enable_gpio;
66
- int ret;
67
-
68
- ret = i2c_set_chip_offset_len(dev, 2);
69
- if (ret)
70
- return ret;
71
-
72
- ret = gpio_request_by_name(dev, "enable-gpios", 0, &enable_gpio,
73
- GPIOD_IS_OUT);
74
- if (ret && ret != -ENOENT) {
75
- dev_err(dev, "%s: failed to get enable GPIO: %d\n",
76
- __func__, ret);
77
- return ret;
78
- }
79
-
80
- if (dm_gpio_is_valid(&enable_gpio)) {
81
- dm_gpio_set_value(&enable_gpio, 1);
82
- mdelay(200);
83
- }
84
-
85
- return 0;
86
-}
87
-
88
-static const struct udevice_id max96752f_of_match[] = {
89
- { .compatible = "maxim,max96752f" },
90
- {}
91
-};
92
-
93
-U_BOOT_DRIVER(max96752f) = {
94
- .name = "max96752f",
95
- .id = UCLASS_I2C_MUX,
96
- .of_match = max96752f_of_match,
97
- .bind = dm_scan_fdt_dev,
98
- .probe = max96752f_probe,
99
- .ops = &max96752f_ops,
100
-};
u-boot/drivers/input/adc_key.c
....@@ -11,13 +11,10 @@
1111 static int adc_key_ofdata_to_platdata(struct udevice *dev)
1212 {
1313 struct dm_key_uclass_platdata *uc_key;
14
- u32 chn[2], mV;
15
- int vref, ret;
16
-#ifdef CONFIG_SARADC_ROCKCHIP_V2
17
- int range = 4096; /* 12-bit adc */
18
-#else
19
- int range = 1024; /* 10-bit adc */
20
-#endif
14
+ int t, down_threshold = -1, up_threshold;
15
+ int ret, num = 0, volt_margin = 150000; /* will be div 2 */
16
+ u32 voltage, chn[2];
17
+ ofnode node;
2118
2219 uc_key = dev_get_uclass_platdata(dev);
2320 if (!uc_key)
....@@ -33,29 +30,50 @@
3330 return -EINVAL;
3431 }
3532
36
- vref = dev_read_u32_default(dev_get_parent(dev),
33
+ up_threshold = dev_read_u32_default(dev_get_parent(dev),
3734 "keyup-threshold-microvolt", -ENODATA);
38
- if (vref < 0) {
39
- printf("%s: read 'keyup-threshold-microvolt' failed, ret=%d\n",
40
- uc_key->name, vref);
41
- return -EINVAL;
42
- }
35
+ if (up_threshold < 0)
36
+ return -ENODATA;
4337
4438 uc_key->code = dev_read_u32_default(dev, "linux,code", -ENODATA);
45
- if (uc_key->code < 0) {
46
- printf("%s: read 'linux,code' failed\n", uc_key->name);
47
- return -EINVAL;
39
+ if (uc_key->code < 0)
40
+ return -ENODATA;
41
+
42
+ voltage = dev_read_u32_default(dev, "press-threshold-microvolt", -ENODATA);
43
+ if (voltage < 0)
44
+ return -ENODATA;
45
+
46
+ dev_for_each_subnode(node, dev->parent) {
47
+ ret = ofnode_read_s32(node, "press-threshold-microvolt", &t);
48
+ if (ret)
49
+ return ret;
50
+
51
+ if (t > voltage && t < up_threshold)
52
+ up_threshold = t;
53
+ else if (t < voltage && t > down_threshold)
54
+ down_threshold = t;
55
+ num++;
4856 }
4957
50
- mV = dev_read_u32_default(dev, "press-threshold-microvolt", -ENODATA);
51
- if (mV < 0) {
52
- printf("%s: read 'press-threshold-microvolt' failed\n",
53
- uc_key->name);
54
- return -EINVAL;
58
+ /* although one node only, it doesn't mean only one key on hardware */
59
+ if (num == 1) {
60
+ down_threshold = voltage - volt_margin;
61
+ up_threshold = voltage + volt_margin;
5562 }
5663
64
+ uc_key->in_volt = 1;
5765 uc_key->channel = chn[1];
58
- uc_key->adcval = mV / (vref / range);
66
+ uc_key->center = voltage;
67
+ /*
68
+ * Define the voltage range such that the button is only pressed
69
+ * when the voltage is closest to its own press-threshold-microvolt
70
+ */
71
+ if (down_threshold < 0)
72
+ uc_key->min = 0;
73
+ else
74
+ uc_key->min = down_threshold + (voltage - down_threshold) / 2;
75
+
76
+ uc_key->max = voltage + (up_threshold - voltage) / 2;
5977
6078 return 0;
6179 }
u-boot/drivers/input/key-uclass.c
....@@ -6,6 +6,7 @@
66
77 #include <common.h>
88 #include <adc.h>
9
+#include <div64.h>
910 #include <dm.h>
1011 #include <irq-generic.h>
1112 #include <key.h>
....@@ -37,11 +38,42 @@
3738 return (cntpct > base) ? (cntpct - base) : 0;
3839 }
3940
40
-static int key_adc_event(struct dm_key_uclass_platdata *uc_key, int adcval)
41
+#ifdef CONFIG_ADC
42
+static int adc_raw_to_mV(struct udevice *dev, unsigned int raw, int *mV)
4143 {
42
- return (adcval <= uc_key->max && adcval >= uc_key->min) ?
44
+ unsigned int data_mask;
45
+ int ret, vref = 1800000;
46
+ u64 raw64 = raw;
47
+
48
+ ret = adc_data_mask(dev, &data_mask);
49
+ if (ret)
50
+ return ret;
51
+
52
+ raw64 *= vref;
53
+ do_div(raw64, data_mask);
54
+ *mV = raw64;
55
+
56
+ return 0;
57
+}
58
+
59
+static int key_adc_event(struct udevice *dev,
60
+ struct dm_key_uclass_platdata *uc_key, int adcval)
61
+{
62
+ int val = adcval;
63
+
64
+ if (uc_key->in_volt) {
65
+ if (adc_raw_to_mV(dev, adcval, &val))
66
+ return KEY_PRESS_NONE;
67
+ }
68
+
69
+ debug("[%s] <%d, %d, %d>: adcval=%d -> mV=%d\n",
70
+ uc_key->name, uc_key->min, uc_key->center, uc_key->max,
71
+ adcval, val);
72
+
73
+ return (val <= uc_key->max && val >= uc_key->min) ?
4374 KEY_PRESS_DOWN : KEY_PRESS_NONE;
4475 }
76
+#endif
4577
4678 static int key_gpio_event(struct dm_key_uclass_platdata *uc_key)
4779 {
....@@ -108,16 +140,34 @@
108140
109141 static int key_core_read(struct dm_key_uclass_platdata *uc_key)
110142 {
111
- unsigned int adcval;
112
-
113143 if (uc_key->type == ADC_KEY) {
114
- if (adc_channel_single_shot("saradc",
115
- uc_key->channel, &adcval)) {
116
- KEY_ERR("%s failed to read saradc\n", uc_key->name);
144
+#ifdef CONFIG_ADC
145
+ struct udevice *dev;
146
+ unsigned int adcval;
147
+ int ret;
148
+
149
+ ret = uclass_get_device_by_name(UCLASS_ADC, "saradc", &dev);
150
+ if (ret) {
151
+ KEY_ERR("%s: No saradc\n", uc_key->name);
117152 return KEY_NOT_EXIST;
118153 }
119154
120
- return key_adc_event(uc_key, adcval);
155
+ ret = adc_start_channel(dev, uc_key->channel);
156
+ if (ret) {
157
+ KEY_ERR("%s: Failed to start saradc\n", uc_key->name);
158
+ return KEY_NOT_EXIST;
159
+ }
160
+
161
+ ret = adc_channel_data(dev, uc_key->channel, &adcval);
162
+ if (ret) {
163
+ KEY_ERR("%s: Failed to read saradc, %d\n", uc_key->name, ret);
164
+ return KEY_NOT_EXIST;
165
+ }
166
+
167
+ return key_adc_event(dev, uc_key, adcval);
168
+#else
169
+ return KEY_NOT_EXIST;
170
+#endif
121171 }
122172
123173 return (uc_key->code == KEY_POWER) ?
....@@ -273,11 +323,7 @@
273323 {
274324 struct dm_key_uclass_platdata *uc_key;
275325 int ret;
276
-#ifdef CONFIG_SARADC_ROCKCHIP_V2
277
- int margin = 120;
278
-#else
279
- int margin = 30;
280
-#endif
326
+
281327 uc_key = dev_get_uclass_platdata(dev);
282328 if (!uc_key)
283329 return -ENXIO;
....@@ -286,11 +332,7 @@
286332 uc_key->pre_reloc = dev_read_bool(dev, "u-boot,dm-pre-reloc") ||
287333 dev_read_bool(dev, "u-boot,dm-spl");
288334
289
- if (uc_key->type == ADC_KEY) {
290
- uc_key->max = uc_key->adcval + margin;
291
- uc_key->min = uc_key->adcval > margin ?
292
- uc_key->adcval - margin : 0;
293
- } else {
335
+ if (uc_key->type != ADC_KEY) {
294336 if (uc_key->code == KEY_POWER) {
295337 #if CONFIG_IS_ENABLED(IRQ)
296338 int irq;
....@@ -337,8 +379,9 @@
337379 dev->parent->name);
338380
339381 if (uc_key->type == ADC_KEY) {
340
- printf(" adcval: %d (%d, %d)\n", uc_key->adcval,
341
- uc_key->min, uc_key->max);
382
+ printf(" %s: %d (%d, %d)\n",
383
+ uc_key->in_volt ? "volt" : " adc",
384
+ uc_key->center, uc_key->min, uc_key->max);
342385 printf(" channel: %d\n\n", uc_key->channel);
343386 } else {
344387 const char *gpio_name =
u-boot/drivers/input/rk_key.c
....@@ -27,9 +27,13 @@
2727
2828 if (dev_read_bool(dev, "rockchip,adc_value")) {
2929 uc_key->type = ADC_KEY;
30
+ uc_key->in_volt = 0;
3031 uc_key->channel = chn[1];
31
- uc_key->adcval =
32
- dev_read_u32_default(dev, "rockchip,adc_value", 0);
32
+ uc_key->center = dev_read_u32_default(dev, "rockchip,adc_value", 0);
33
+ uc_key->min = uc_key->center - 30;
34
+ if (uc_key->min < 0)
35
+ uc_key->min = 0;
36
+ uc_key->max = uc_key->center + 30;
3337 } else {
3438 uc_key->type = GPIO_KEY;
3539 if (dev_read_u32_array(dev, "gpios",
u-boot/drivers/input/spl_adc_key.c
....@@ -6,28 +6,46 @@
66
77 #include <common.h>
88 #include <adc.h>
9
+#include <div64.h>
910 #include <fdtdec.h>
11
+#include <dm/uclass.h>
1012
1113 DECLARE_GLOBAL_DATA_PTR;
14
+
15
+static int adc_raw_to_mV(struct udevice *dev, unsigned int raw, int *mV)
16
+{
17
+ unsigned int data_mask;
18
+ int ret, vref = 1800000;
19
+ u64 raw64 = raw;
20
+
21
+ ret = adc_data_mask(dev, &data_mask);
22
+ if (ret)
23
+ return ret;
24
+
25
+ raw64 *= vref;
26
+ do_div(raw64, data_mask);
27
+ *mV = raw64;
28
+
29
+ return 0;
30
+}
1231
1332 int key_read(int code)
1433 {
1534 const void *fdt_blob = gd->fdt_blob;
35
+ struct udevice *dev;
1636 int adc_node, offset;
17
- int cd, channel, adc;
18
- int ret, vref, mv;
37
+ int t, down_threshold = -1, up_threshold;
38
+ int ret, num = 0, volt_margin = 150000; /* will be div 2 */
39
+ int mV, cd, voltage = -1;
1940 int min, max;
20
- int margin;
21
- int range;
22
- uint val;
23
- u32 chn[2];
24
-#ifdef CONFIG_SARADC_ROCKCHIP_V2
25
- range = 4096; /* 12-bit adc */
26
- margin = 120;
27
-#else
28
- range = 1024; /* 10-bit adc */
29
- margin = 30;
30
-#endif
41
+ u32 chn[2], adc;
42
+
43
+ ret = uclass_get_device_by_name(UCLASS_ADC, "saradc", &dev);
44
+ if (ret) {
45
+ debug("No saradc device, ret=%d\n", ret);
46
+ return 0;
47
+ }
48
+
3149 adc_node = fdt_node_offset_by_compatible(fdt_blob, 0, "adc-keys");
3250 if (adc_node < 0) {
3351 debug("No 'adc-keys' node, ret=%d\n", adc_node);
....@@ -41,40 +59,87 @@
4159 return 0;
4260 }
4361
44
- vref = fdtdec_get_int(fdt_blob, adc_node,
45
- "keyup-threshold-microvolt", -1);
46
- if (vref < 0) {
62
+ up_threshold = fdtdec_get_int(fdt_blob, adc_node,
63
+ "keyup-threshold-microvolt", -ENODATA);
64
+ if (up_threshold < 0) {
4765 debug("Can't read 'keyup-threshold-microvolt'\n");
4866 return 0;
4967 }
5068
51
- channel = chn[1];
69
+ /* find the expected key-code */
70
+ for (offset = fdt_first_subnode(fdt_blob, adc_node);
71
+ offset >= 0;
72
+ offset = fdt_next_subnode(fdt_blob, offset)) {
73
+ cd = fdtdec_get_int(fdt_blob, offset, "linux,code", -ENODATA);
74
+ if (cd < 0) {
75
+ debug("Can't read 'linux,code', ret=%d\n", cd);
76
+ return 0;
77
+ }
78
+
79
+ if (cd == code) {
80
+ voltage = fdtdec_get_int(fdt_blob, offset,
81
+ "press-threshold-microvolt", -ENODATA);
82
+ if (voltage < 0) {
83
+ debug("Can't read 'press-threshold-microvolt'\n");
84
+ return 0;
85
+ }
86
+ break;
87
+ }
88
+ }
89
+
90
+ if (voltage < 0)
91
+ return 0;
5292
5393 for (offset = fdt_first_subnode(fdt_blob, adc_node);
5494 offset >= 0;
5595 offset = fdt_next_subnode(fdt_blob, offset)) {
56
- cd = fdtdec_get_int(fdt_blob, offset, "linux,code", -1);
57
- if (cd == code) {
58
- mv = fdtdec_get_int(fdt_blob, offset,
59
- "press-threshold-microvolt", -1);
60
- if (mv < 0) {
61
- debug("Can't read 'press-threshold-microvolt'\n");
62
- return 0;
63
- }
64
-
65
- adc = mv / (vref / range);
66
- max = adc + margin;
67
- min = adc > margin ? adc - margin : 0;
68
- ret = adc_channel_single_shot("saradc", channel, &val);
69
- if (ret) {
70
- debug("Failed to read adc%d, ret=%d\n",
71
- channel, ret);
72
- return 0;
73
- }
74
-
75
- return (val >= min && val <= max);
96
+ t = fdtdec_get_int(fdt_blob, offset,
97
+ "press-threshold-microvolt", -ENODATA);
98
+ if (t < 0) {
99
+ debug("Can't read 'press-threshold-microvolt'\n");
100
+ return 0;
76101 }
102
+
103
+ if (t > voltage && t < up_threshold)
104
+ up_threshold = t;
105
+ else if (t < voltage && t > down_threshold)
106
+ down_threshold = t;
107
+ num++;
77108 }
78109
79
- return 0;
110
+ /* although one node only, it doesn't mean only one key on hardware */
111
+ if (num == 1) {
112
+ down_threshold = voltage - volt_margin;
113
+ up_threshold = voltage + volt_margin;
114
+ }
115
+
116
+ /*
117
+ * Define the voltage range such that the button is only pressed
118
+ * when the voltage is closest to its own press-threshold-microvolt
119
+ */
120
+ if (down_threshold < 0)
121
+ min = 0;
122
+ else
123
+ min = down_threshold + (voltage - down_threshold) / 2;
124
+
125
+ max = voltage + (up_threshold - voltage) / 2;
126
+
127
+ /* now, read key status */
128
+ ret = adc_channel_single_shot("saradc", chn[1], &adc);
129
+ if (ret) {
130
+ debug("Failed to read adc%d, ret=%d\n", chn[1], ret);
131
+ return 0;
132
+ }
133
+
134
+ ret = adc_raw_to_mV(dev, adc, &mV);
135
+ if (ret) {
136
+ debug("Failed to convert adc to mV, ret=%d\n", ret);
137
+ return 0;
138
+ }
139
+
140
+ debug("key[%d] <%d, %d, %d>: adc=%d -> mV=%d\n",
141
+ code, min, voltage, max, adc, mV);
142
+
143
+ return (mV <= max && mV >= min);
80144 }
145
+
u-boot/drivers/misc/Makefile
....@@ -83,4 +83,12 @@
8383 obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_SECURE_OTP) += rk3588-secure-otp.o
8484 endif
8585
86
+ifdef CONFIG_ROCKCHIP_RK3528
87
+obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_SECURE_OTP) += rk3528-secure-otp.o
88
+endif
89
+
90
+ifdef CONFIG_ROCKCHIP_RK3562
91
+obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_SECURE_OTP) += rk3562-secure-otp.o
92
+endif
93
+
8694 obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_HW_DECOMPRESS) += rockchip_decompress.o
u-boot/drivers/misc/rk3528-secure-otp.S
....@@ -0,0 +1,15901 @@
1
+ .arch armv8-a+nosimd
2
+ .file "rk3528-secure-otp.c"
3
+ .text
4
+.Ltext0:
5
+ .cfi_sections .debug_frame
6
+ .section .text.rk3528_spl_rockchip_otp_stop,"ax",@progbits
7
+ .align 2
8
+ .type rk3528_spl_rockchip_otp_stop, %function
9
+rk3528_spl_rockchip_otp_stop:
10
+.LFB263:
11
+ .file 1 "drivers/misc/rk3528-secure-otp.c"
12
+ .loc 1 81 0
13
+ .cfi_startproc
14
+.LVL0:
15
+.LBB22:
16
+ .loc 1 82 0
17
+#APP
18
+// 82 "drivers/misc/rk3528-secure-otp.c" 1
19
+ dmb sy
20
+// 0 "" 2
21
+#NO_APP
22
+ mov w1, 16777216
23
+.LVL1:
24
+ str w1, [x0]
25
+ ret
26
+.LBE22:
27
+ .cfi_endproc
28
+.LFE263:
29
+ .size rk3528_spl_rockchip_otp_stop, .-rk3528_spl_rockchip_otp_stop
30
+ .section .text.secure_otp_ioctl,"ax",@progbits
31
+ .align 2
32
+ .type secure_otp_ioctl, %function
33
+secure_otp_ioctl:
34
+.LFB276:
35
+ .loc 1 697 0
36
+ .cfi_startproc
37
+.LVL2:
38
+ .loc 1 700 0
39
+ mov x0, 27908
40
+.LVL3:
41
+ cmp x1, x0
42
+ bne .L6
43
+.LVL4:
44
+.LBB23:
45
+.LBB24:
46
+ .loc 1 689 0
47
+ mov w0, 8
48
+ str w0, [x2]
49
+.LVL5:
50
+.LBE24:
51
+.LBE23:
52
+ .loc 1 702 0
53
+ mov w0, 0
54
+ .loc 1 703 0
55
+ ret
56
+.LVL6:
57
+.L6:
58
+ .loc 1 698 0
59
+ mov w0, -22
60
+ .loc 1 709 0
61
+ ret
62
+ .cfi_endproc
63
+.LFE276:
64
+ .size secure_otp_ioctl, .-secure_otp_ioctl
65
+ .section .text.secure_otp_write,"ax",@progbits
66
+ .align 2
67
+ .type secure_otp_write, %function
68
+secure_otp_write:
69
+.LFB274:
70
+ .loc 1 681 0
71
+ .cfi_startproc
72
+.LVL7:
73
+ stp x29, x30, [sp, -48]!
74
+ .cfi_def_cfa_offset 48
75
+ .cfi_offset 29, -48
76
+ .cfi_offset 30, -40
77
+ add x29, sp, 0
78
+ .cfi_def_cfa_register 29
79
+ stp x19, x20, [sp, 16]
80
+ .cfi_offset 19, -32
81
+ .cfi_offset 20, -24
82
+ mov x19, x0
83
+ stp x21, x22, [sp, 32]
84
+ .cfi_offset 21, -16
85
+ .cfi_offset 22, -8
86
+ .loc 1 681 0
87
+ mov w20, w1
88
+ mov x21, x2
89
+ mov w22, w3
90
+ .loc 1 682 0
91
+ bl dev_get_driver_data
92
+.LVL8:
93
+ .loc 1 684 0
94
+ ldr x4, [x0, 8]
95
+ mov w3, w22
96
+ mov x2, x21
97
+ mov w1, w20
98
+ mov x0, x19
99
+.LVL9:
100
+ .loc 1 685 0
101
+ ldp x21, x22, [sp, 32]
102
+.LVL10:
103
+ ldp x19, x20, [sp, 16]
104
+.LVL11:
105
+ ldp x29, x30, [sp], 48
106
+ .cfi_restore 30
107
+ .cfi_restore 29
108
+ .cfi_restore 21
109
+ .cfi_restore 22
110
+ .cfi_restore 19
111
+ .cfi_restore 20
112
+ .cfi_def_cfa 31, 0
113
+ .loc 1 684 0
114
+ br x4
115
+.LVL12:
116
+ .cfi_endproc
117
+.LFE274:
118
+ .size secure_otp_write, .-secure_otp_write
119
+ .section .text.secure_otp_read,"ax",@progbits
120
+ .align 2
121
+ .type secure_otp_read, %function
122
+secure_otp_read:
123
+.LFB273:
124
+ .loc 1 673 0
125
+ .cfi_startproc
126
+.LVL13:
127
+ stp x29, x30, [sp, -48]!
128
+ .cfi_def_cfa_offset 48
129
+ .cfi_offset 29, -48
130
+ .cfi_offset 30, -40
131
+ add x29, sp, 0
132
+ .cfi_def_cfa_register 29
133
+ stp x19, x20, [sp, 16]
134
+ .cfi_offset 19, -32
135
+ .cfi_offset 20, -24
136
+ mov x19, x0
137
+ stp x21, x22, [sp, 32]
138
+ .cfi_offset 21, -16
139
+ .cfi_offset 22, -8
140
+ .loc 1 673 0
141
+ mov w20, w1
142
+ mov x21, x2
143
+ mov w22, w3
144
+ .loc 1 674 0
145
+ bl dev_get_driver_data
146
+.LVL14:
147
+ .loc 1 676 0
148
+ ldr x4, [x0]
149
+ mov w3, w22
150
+ mov x2, x21
151
+ mov w1, w20
152
+ mov x0, x19
153
+.LVL15:
154
+ .loc 1 677 0
155
+ ldp x21, x22, [sp, 32]
156
+.LVL16:
157
+ ldp x19, x20, [sp, 16]
158
+.LVL17:
159
+ ldp x29, x30, [sp], 48
160
+ .cfi_restore 30
161
+ .cfi_restore 29
162
+ .cfi_restore 21
163
+ .cfi_restore 22
164
+ .cfi_restore 19
165
+ .cfi_restore 20
166
+ .cfi_def_cfa 31, 0
167
+ .loc 1 676 0
168
+ br x4
169
+.LVL18:
170
+ .cfi_endproc
171
+.LFE273:
172
+ .size secure_otp_read, .-secure_otp_read
173
+ .section .text.rockchip_secure_otp_ofdata_to_platdata,"ax",@progbits
174
+ .align 2
175
+ .type rockchip_secure_otp_ofdata_to_platdata, %function
176
+rockchip_secure_otp_ofdata_to_platdata:
177
+.LFB277:
178
+ .loc 1 718 0
179
+ .cfi_startproc
180
+.LVL19:
181
+ stp x29, x30, [sp, -32]!
182
+ .cfi_def_cfa_offset 32
183
+ .cfi_offset 29, -32
184
+ .cfi_offset 30, -24
185
+ add x29, sp, 0
186
+ .cfi_def_cfa_register 29
187
+ stp x19, x20, [sp, 16]
188
+ .cfi_offset 19, -16
189
+ .cfi_offset 20, -8
190
+ .loc 1 718 0
191
+ mov x20, x0
192
+ .loc 1 719 0
193
+ bl dev_get_platdata
194
+.LVL20:
195
+ mov x19, x0
196
+.LVL21:
197
+ .loc 1 721 0
198
+ mov x0, x20
199
+.LVL22:
200
+ bl dev_read_addr_ptr
201
+.LVL23:
202
+ .loc 1 722 0
203
+ mov w2, 0
204
+ adrp x1, .LC0
205
+ .loc 1 721 0
206
+ str x0, [x19]
207
+ .loc 1 722 0
208
+ add x1, x1, :lo12:.LC0
209
+ mov x0, x20
210
+ bl dev_read_u32_default
211
+.LVL24:
212
+ .loc 1 723 0
213
+ uxtw x0, w0
214
+ str x0, [x19, 8]
215
+ .loc 1 724 0
216
+ mov w2, 0
217
+ mov x0, x20
218
+ adrp x1, .LC1
219
+ add x1, x1, :lo12:.LC1
220
+ bl dev_read_u32_default
221
+.LVL25:
222
+ .loc 1 725 0
223
+ uxtw x0, w0
224
+ str x0, [x19, 16]
225
+ .loc 1 726 0
226
+ mov w2, 0
227
+ mov x0, x20
228
+ adrp x1, .LC2
229
+ add x1, x1, :lo12:.LC2
230
+ bl dev_read_u32_default
231
+.LVL26:
232
+ .loc 1 727 0
233
+ uxtw x0, w0
234
+ str x0, [x19, 24]
235
+ .loc 1 730 0
236
+ mov w0, 0
237
+ ldp x19, x20, [sp, 16]
238
+.LVL27:
239
+ ldp x29, x30, [sp], 32
240
+ .cfi_restore 30
241
+ .cfi_restore 29
242
+ .cfi_restore 19
243
+ .cfi_restore 20
244
+ .cfi_def_cfa 31, 0
245
+ ret
246
+ .cfi_endproc
247
+.LFE277:
248
+ .size rockchip_secure_otp_ofdata_to_platdata, .-rockchip_secure_otp_ofdata_to_platdata
249
+ .section .text.rk3528_spl_rockchip_otp_start,"ax",@progbits
250
+ .align 2
251
+ .type rk3528_spl_rockchip_otp_start, %function
252
+rk3528_spl_rockchip_otp_start:
253
+.LFB262:
254
+ .loc 1 69 0
255
+ .cfi_startproc
256
+.LVL28:
257
+ stp x29, x30, [sp, -32]!
258
+ .cfi_def_cfa_offset 32
259
+ .cfi_offset 29, -32
260
+ .cfi_offset 30, -24
261
+ add x29, sp, 0
262
+ .cfi_def_cfa_register 29
263
+ str x19, [sp, 16]
264
+ .cfi_offset 19, -16
265
+ .loc 1 69 0
266
+ mov x19, x1
267
+.LBB25:
268
+ .loc 1 71 0
269
+#APP
270
+// 71 "drivers/misc/rk3528-secure-otp.c" 1
271
+ dmb sy
272
+// 0 "" 2
273
+#NO_APP
274
+ mov w1, 16777472
275
+.LVL29:
276
+ str w1, [x0]
277
+.LVL30:
278
+.LBE25:
279
+.LBB26:
280
+ .loc 1 72 0
281
+#APP
282
+// 72 "drivers/misc/rk3528-secure-otp.c" 1
283
+ dmb sy
284
+// 0 "" 2
285
+#NO_APP
286
+ mov w0, 131074
287
+.LVL31:
288
+ str w0, [x19]
289
+.LBE26:
290
+ .loc 1 73 0
291
+ mov x0, 2
292
+ bl udelay
293
+.LVL32:
294
+.LBB27:
295
+ .loc 1 74 0
296
+#APP
297
+// 74 "drivers/misc/rk3528-secure-otp.c" 1
298
+ dmb sy
299
+// 0 "" 2
300
+#NO_APP
301
+ mov w0, 131072
302
+ str w0, [x19]
303
+.LBE27:
304
+ .loc 1 76 0
305
+ ldr x19, [sp, 16]
306
+.LVL33:
307
+ .loc 1 75 0
308
+ mov x0, 1
309
+ .loc 1 76 0
310
+ ldp x29, x30, [sp], 32
311
+ .cfi_restore 30
312
+ .cfi_restore 29
313
+ .cfi_restore 19
314
+ .cfi_def_cfa 31, 0
315
+ .loc 1 75 0
316
+ b udelay
317
+.LVL34:
318
+ .cfi_endproc
319
+.LFE262:
320
+ .size rk3528_spl_rockchip_otp_start, .-rk3528_spl_rockchip_otp_start
321
+ .section .text.rockchip_secure_otp_check_flag.isra.0,"ax",@progbits
322
+ .align 2
323
+ .type rockchip_secure_otp_check_flag.isra.0, %function
324
+rockchip_secure_otp_check_flag.isra.0:
325
+.LFB278:
326
+ .loc 1 129 0
327
+ .cfi_startproc
328
+ stp x29, x30, [sp, -32]!
329
+ .cfi_def_cfa_offset 32
330
+ .cfi_offset 29, -32
331
+ .cfi_offset 30, -24
332
+ add x29, sp, 0
333
+ .cfi_def_cfa_register 29
334
+ stp x19, x20, [sp, 16]
335
+ .cfi_offset 19, -16
336
+ .cfi_offset 20, -8
337
+ .loc 1 129 0
338
+ mov w19, 34465
339
+ mov x20, x0
340
+ movk w19, 0x1, lsl 16
341
+.L17:
342
+.LVL35:
343
+.LBB28:
344
+ .loc 1 136 0
345
+ ldr x0, [x20]
346
+ ldr w1, [x0, 44]
347
+.LVL36:
348
+#APP
349
+// 136 "drivers/misc/rk3528-secure-otp.c" 1
350
+ dmb sy
351
+// 0 "" 2
352
+.LVL37:
353
+#NO_APP
354
+.LBE28:
355
+ .loc 1 137 0
356
+ and w0, w1, 16
357
+ tbz x1, 4, .L15
358
+ .loc 1 140 0
359
+ subs w19, w19, #1
360
+.LVL38:
361
+ beq .L18
362
+.LVL39:
363
+ .loc 1 146 0
364
+ mov x0, 1
365
+ bl udelay
366
+.LVL40:
367
+ b .L17
368
+.LVL41:
369
+.L18:
370
+ .loc 1 141 0
371
+ mov w0, -1
372
+.LVL42:
373
+.L15:
374
+ .loc 1 150 0
375
+ ldp x19, x20, [sp, 16]
376
+ ldp x29, x30, [sp], 32
377
+ .cfi_restore 30
378
+ .cfi_restore 29
379
+ .cfi_restore 19
380
+ .cfi_restore 20
381
+ .cfi_def_cfa 31, 0
382
+ ret
383
+ .cfi_endproc
384
+.LFE278:
385
+ .size rockchip_secure_otp_check_flag.isra.0, .-rockchip_secure_otp_check_flag.isra.0
386
+ .section .text.rockchip_secure_otp_wait_flag.isra.1,"ax",@progbits
387
+ .align 2
388
+ .type rockchip_secure_otp_wait_flag.isra.1, %function
389
+rockchip_secure_otp_wait_flag.isra.1:
390
+.LFB279:
391
+ .loc 1 106 0
392
+ .cfi_startproc
393
+ stp x29, x30, [sp, -32]!
394
+ .cfi_def_cfa_offset 32
395
+ .cfi_offset 29, -32
396
+ .cfi_offset 30, -24
397
+ add x29, sp, 0
398
+ .cfi_def_cfa_register 29
399
+ stp x19, x20, [sp, 16]
400
+ .cfi_offset 19, -16
401
+ .cfi_offset 20, -8
402
+ .loc 1 106 0
403
+ mov x20, x0
404
+ mov w19, 20001
405
+.L25:
406
+.LVL43:
407
+.LBB29:
408
+ .loc 1 113 0
409
+ ldr x0, [x20]
410
+ ldr w0, [x0, 44]
411
+.LVL44:
412
+#APP
413
+// 113 "drivers/misc/rk3528-secure-otp.c" 1
414
+ dmb sy
415
+// 0 "" 2
416
+.LVL45:
417
+#NO_APP
418
+.LBE29:
419
+ .loc 1 114 0
420
+ tbnz x0, 4, .L26
421
+ .loc 1 117 0
422
+ subs w19, w19, #1
423
+.LVL46:
424
+ beq .L27
425
+ .loc 1 122 0
426
+ mov x0, 1
427
+.LVL47:
428
+ bl udelay
429
+.LVL48:
430
+ b .L25
431
+.LVL49:
432
+.L26:
433
+ .loc 1 110 0
434
+ mov w0, 0
435
+.LVL50:
436
+.L23:
437
+ .loc 1 127 0
438
+ ldp x19, x20, [sp, 16]
439
+ ldp x29, x30, [sp], 32
440
+ .cfi_remember_state
441
+ .cfi_restore 30
442
+ .cfi_restore 29
443
+ .cfi_restore 19
444
+ .cfi_restore 20
445
+ .cfi_def_cfa 31, 0
446
+ ret
447
+.LVL51:
448
+.L27:
449
+ .cfi_restore_state
450
+ .loc 1 118 0
451
+ mov w0, -1
452
+.LVL52:
453
+ b .L23
454
+ .cfi_endproc
455
+.LFE279:
456
+ .size rockchip_secure_otp_wait_flag.isra.1, .-rockchip_secure_otp_wait_flag.isra.1
457
+ .section .text.rockchip_secure_otp_wait_status.isra.2,"ax",@progbits
458
+ .align 2
459
+ .type rockchip_secure_otp_wait_status.isra.2, %function
460
+rockchip_secure_otp_wait_status.isra.2:
461
+.LFB280:
462
+ .loc 1 86 0
463
+ .cfi_startproc
464
+.LVL53:
465
+ stp x29, x30, [sp, -48]!
466
+ .cfi_def_cfa_offset 48
467
+ .cfi_offset 29, -48
468
+ .cfi_offset 30, -40
469
+ add x29, sp, 0
470
+ .cfi_def_cfa_register 29
471
+ stp x19, x20, [sp, 16]
472
+ .cfi_offset 19, -32
473
+ .cfi_offset 20, -24
474
+ mov w19, w1
475
+ str x21, [sp, 32]
476
+ .cfi_offset 21, -16
477
+ .loc 1 86 0
478
+ mov x21, x0
479
+ mov w20, 10000
480
+.LVL54:
481
+.L30:
482
+.LBB36:
483
+ .loc 1 91 0
484
+ ldr x0, [x21]
485
+ ldr w0, [x0, 772]
486
+.LVL55:
487
+#APP
488
+// 91 "drivers/misc/rk3528-secure-otp.c" 1
489
+ dmb sy
490
+// 0 "" 2
491
+#NO_APP
492
+.LBE36:
493
+ tst w0, w19
494
+ beq .L32
495
+.LBB37:
496
+ .loc 1 101 0
497
+ orr w19, w19, -65536
498
+.LVL56:
499
+#APP
500
+// 101 "drivers/misc/rk3528-secure-otp.c" 1
501
+ dmb sy
502
+// 0 "" 2
503
+#NO_APP
504
+ ldr x0, [x21]
505
+.LVL57:
506
+ str w19, [x0, 772]
507
+.LBE37:
508
+ .loc 1 103 0
509
+ mov w0, 0
510
+ b .L29
511
+.LVL58:
512
+.L32:
513
+ .loc 1 92 0
514
+ mov x0, 1
515
+.LVL59:
516
+ bl udelay
517
+.LVL60:
518
+ .loc 1 94 0
519
+ subs w20, w20, #1
520
+.LVL61:
521
+ bne .L30
522
+.LVL62:
523
+.LBB38:
524
+.LBB39:
525
+ .loc 1 95 0
526
+ adrp x1, .LANCHOR0
527
+ adrp x0, .LC3
528
+ add x1, x1, :lo12:.LANCHOR0
529
+ add x0, x0, :lo12:.LC3
530
+ bl printf
531
+.LVL63:
532
+ mov w0, -110
533
+.LVL64:
534
+.L29:
535
+.LBE39:
536
+.LBE38:
537
+ .loc 1 104 0
538
+ ldp x19, x20, [sp, 16]
539
+.LVL65:
540
+ ldr x21, [sp, 32]
541
+ ldp x29, x30, [sp], 48
542
+ .cfi_restore 30
543
+ .cfi_restore 29
544
+ .cfi_restore 21
545
+ .cfi_restore 19
546
+ .cfi_restore 20
547
+ .cfi_def_cfa 31, 0
548
+ ret
549
+ .cfi_endproc
550
+.LFE280:
551
+ .size rockchip_secure_otp_wait_status.isra.2, .-rockchip_secure_otp_wait_status.isra.2
552
+ .section .text.rk3528_secure_otp_write_2_bytes_noecc,"ax",@progbits
553
+ .align 2
554
+ .type rk3528_secure_otp_write_2_bytes_noecc, %function
555
+rk3528_secure_otp_write_2_bytes_noecc:
556
+.LFB269:
557
+ .loc 1 240 0
558
+ .cfi_startproc
559
+.LVL66:
560
+ stp x29, x30, [sp, -96]!
561
+ .cfi_def_cfa_offset 96
562
+ .cfi_offset 29, -96
563
+ .cfi_offset 30, -88
564
+ add x29, sp, 0
565
+ .cfi_def_cfa_register 29
566
+ stp x23, x24, [sp, 48]
567
+ .cfi_offset 23, -48
568
+ .cfi_offset 24, -40
569
+ mov w24, w2
570
+ stp x19, x20, [sp, 16]
571
+ .cfi_offset 19, -80
572
+ .cfi_offset 20, -72
573
+ .loc 1 244 0
574
+ asr w20, w24, 1
575
+ .loc 1 240 0
576
+ stp x21, x22, [sp, 32]
577
+ .cfi_offset 21, -64
578
+ .cfi_offset 22, -56
579
+ and w21, w3, 65535
580
+ stp x25, x26, [sp, 64]
581
+ .cfi_offset 25, -32
582
+ .cfi_offset 26, -24
583
+ mov x26, x1
584
+ stp x27, x28, [sp, 80]
585
+ .cfi_offset 27, -16
586
+ .cfi_offset 28, -8
587
+ .loc 1 242 0
588
+ bl dev_get_driver_data
589
+.LVL67:
590
+ .loc 1 245 0
591
+ cmp w20, 447
592
+ bgt .L43
593
+ mov x23, x0
594
+ .loc 1 249 0
595
+ sub w0, w20, #416
596
+.LVL68:
597
+ cmp w0, 15
598
+ ccmp w20, 16, 4, hi
599
+ beq .L37
600
+ .loc 1 252 0
601
+ adrp x0, .LC4
602
+ and w1, w24, -2
603
+ add x0, x0, :lo12:.LC4
604
+ bl printf
605
+.LVL69:
606
+.L43:
607
+ .loc 1 246 0
608
+ mov w0, -1
609
+.LVL70:
610
+.L35:
611
+ .loc 1 446 0
612
+ ldp x19, x20, [sp, 16]
613
+.LVL71:
614
+ ldp x21, x22, [sp, 32]
615
+ ldp x23, x24, [sp, 48]
616
+ ldp x25, x26, [sp, 64]
617
+.LVL72:
618
+ ldp x27, x28, [sp, 80]
619
+ ldp x29, x30, [sp], 96
620
+ .cfi_remember_state
621
+ .cfi_restore 30
622
+ .cfi_restore 29
623
+ .cfi_restore 27
624
+ .cfi_restore 28
625
+ .cfi_restore 25
626
+ .cfi_restore 26
627
+ .cfi_restore 23
628
+ .cfi_restore 24
629
+ .cfi_restore 21
630
+ .cfi_restore 22
631
+ .cfi_restore 19
632
+ .cfi_restore 20
633
+ .cfi_def_cfa 31, 0
634
+ ret
635
+.LVL73:
636
+.L37:
637
+ .cfi_restore_state
638
+ .loc 1 256 0
639
+ cbz w21, .L44
640
+ .loc 1 259 0
641
+ ldr x6, [x23, 16]
642
+ mov w3, w20
643
+ ldp x0, x2, [x26, 8]
644
+ ldr x1, [x26, 24]
645
+ blr x6
646
+.LVL74:
647
+.LBB40:
648
+ .loc 1 262 0
649
+#APP
650
+// 262 "drivers/misc/rk3528-secure-otp.c" 1
651
+ dmb sy
652
+// 0 "" 2
653
+#NO_APP
654
+ ldr x0, [x26]
655
+ mov w1, 65536
656
+ str w1, [x0, 256]
657
+.LVL75:
658
+.LBE40:
659
+.LBB41:
660
+ .loc 1 263 0
661
+#APP
662
+// 263 "drivers/misc/rk3528-secure-otp.c" 1
663
+ dmb sy
664
+// 0 "" 2
665
+#NO_APP
666
+ ldr x0, [x26]
667
+ mov w1, 262148
668
+ str w1, [x0, 32]
669
+.LVL76:
670
+.LBE41:
671
+.LBB42:
672
+ .loc 1 264 0
673
+#APP
674
+// 264 "drivers/misc/rk3528-secure-otp.c" 1
675
+ dmb sy
676
+// 0 "" 2
677
+#NO_APP
678
+ ldr x0, [x26]
679
+ mov w1, -65536
680
+ str w1, [x0, 40]
681
+.LVL77:
682
+.LBE42:
683
+.LBB43:
684
+ .loc 1 265 0
685
+#APP
686
+// 265 "drivers/misc/rk3528-secure-otp.c" 1
687
+ dmb sy
688
+// 0 "" 2
689
+#NO_APP
690
+ ldr x0, [x26]
691
+ mov w1, 512
692
+ movk w1, 0xff00, lsl 16
693
+ str w1, [x0, 32]
694
+.LVL78:
695
+.LBE43:
696
+.LBB44:
697
+ .loc 1 266 0
698
+#APP
699
+// 266 "drivers/misc/rk3528-secure-otp.c" 1
700
+ dmb sy
701
+// 0 "" 2
702
+#NO_APP
703
+ ldr x0, [x26]
704
+ mov w22, -65534
705
+ str w22, [x0, 36]
706
+.LVL79:
707
+.LBE44:
708
+.LBB45:
709
+ .loc 1 267 0
710
+#APP
711
+// 267 "drivers/misc/rk3528-secure-otp.c" 1
712
+ dmb sy
713
+// 0 "" 2
714
+#NO_APP
715
+ ldr x0, [x26]
716
+ mov w1, 252
717
+ str w1, [x0, 4096]
718
+.LVL80:
719
+.LBE45:
720
+.LBB46:
721
+ .loc 1 268 0
722
+#APP
723
+// 268 "drivers/misc/rk3528-secure-otp.c" 1
724
+ dmb sy
725
+// 0 "" 2
726
+#NO_APP
727
+ ldr x0, [x26]
728
+ str wzr, [x0, 4100]
729
+.LVL81:
730
+.LBE46:
731
+.LBB47:
732
+ .loc 1 269 0
733
+#APP
734
+// 269 "drivers/misc/rk3528-secure-otp.c" 1
735
+ dmb sy
736
+// 0 "" 2
737
+#NO_APP
738
+ ldr x0, [x26]
739
+ str wzr, [x0, 4104]
740
+.LVL82:
741
+.LBE47:
742
+.LBB48:
743
+ .loc 1 270 0
744
+#APP
745
+// 270 "drivers/misc/rk3528-secure-otp.c" 1
746
+ dmb sy
747
+// 0 "" 2
748
+#NO_APP
749
+ ldr x0, [x26]
750
+ mov w19, 65537
751
+.LBE48:
752
+ .loc 1 271 0
753
+ mov w1, 2
754
+.LBB49:
755
+ .loc 1 270 0
756
+ str w19, [x0, 32]
757
+.LBE49:
758
+ .loc 1 271 0
759
+ mov x0, x26
760
+ bl rockchip_secure_otp_wait_status.isra.2
761
+.LVL83:
762
+ .loc 1 272 0
763
+ tbz w0, #31, .L38
764
+.L40:
765
+ .loc 1 273 0
766
+ adrp x1, .LANCHOR1
767
+ adrp x0, .LC5
768
+.LVL84:
769
+ add x1, x1, :lo12:.LANCHOR1
770
+ add x0, x0, :lo12:.LC5
771
+.L46:
772
+ .loc 1 406 0
773
+ bl printf
774
+.LVL85:
775
+.L39:
776
+ .loc 1 442 0
777
+ ldr x5, [x23, 24]
778
+ mov w3, w20
779
+ ldp x0, x2, [x26, 8]
780
+ ldr x1, [x26, 24]
781
+ blr x5
782
+.LVL86:
783
+.L44:
784
+ .loc 1 257 0
785
+ mov w0, 0
786
+ b .L35
787
+.LVL87:
788
+.L38:
789
+.LBB50:
790
+ .loc 1 277 0
791
+#APP
792
+// 277 "drivers/misc/rk3528-secure-otp.c" 1
793
+ dmb sy
794
+// 0 "" 2
795
+#NO_APP
796
+ ldr x0, [x26]
797
+.LVL88:
798
+ mov w28, -65522
799
+ str w28, [x0, 36]
800
+.LVL89:
801
+.LBE50:
802
+.LBB51:
803
+ .loc 1 278 0
804
+#APP
805
+// 278 "drivers/misc/rk3528-secure-otp.c" 1
806
+ dmb sy
807
+// 0 "" 2
808
+#NO_APP
809
+ ldr x0, [x26]
810
+ mov w27, 240
811
+ str w27, [x0, 4096]
812
+.LVL90:
813
+.LBE51:
814
+.LBB52:
815
+ .loc 1 279 0
816
+#APP
817
+// 279 "drivers/misc/rk3528-secure-otp.c" 1
818
+ dmb sy
819
+// 0 "" 2
820
+#NO_APP
821
+ ldr x0, [x26]
822
+ mov w1, 1
823
+ str w1, [x0, 4100]
824
+.LVL91:
825
+.LBE52:
826
+.LBB53:
827
+ .loc 1 280 0
828
+#APP
829
+// 280 "drivers/misc/rk3528-secure-otp.c" 1
830
+ dmb sy
831
+// 0 "" 2
832
+#NO_APP
833
+ ldr x0, [x26]
834
+ mov w25, 122
835
+ str w25, [x0, 4104]
836
+.LVL92:
837
+.LBE53:
838
+.LBB54:
839
+ .loc 1 281 0
840
+#APP
841
+// 281 "drivers/misc/rk3528-secure-otp.c" 1
842
+ dmb sy
843
+// 0 "" 2
844
+#NO_APP
845
+ ldr x0, [x26]
846
+ mov w1, 37
847
+ str w1, [x0, 4108]
848
+.LVL93:
849
+.LBE54:
850
+.LBB55:
851
+ .loc 1 282 0
852
+#APP
853
+// 282 "drivers/misc/rk3528-secure-otp.c" 1
854
+ dmb sy
855
+// 0 "" 2
856
+#NO_APP
857
+ ldr x0, [x26]
858
+ str wzr, [x0, 4112]
859
+.LVL94:
860
+.LBE55:
861
+.LBB56:
862
+ .loc 1 283 0
863
+#APP
864
+// 283 "drivers/misc/rk3528-secure-otp.c" 1
865
+ dmb sy
866
+// 0 "" 2
867
+#NO_APP
868
+ ldr x0, [x26]
869
+ str wzr, [x0, 4116]
870
+.LVL95:
871
+.LBE56:
872
+.LBB57:
873
+ .loc 1 284 0
874
+#APP
875
+// 284 "drivers/misc/rk3528-secure-otp.c" 1
876
+ dmb sy
877
+// 0 "" 2
878
+#NO_APP
879
+ ldr x0, [x26]
880
+ str wzr, [x0, 4120]
881
+.LVL96:
882
+.LBE57:
883
+.LBB58:
884
+ .loc 1 285 0
885
+#APP
886
+// 285 "drivers/misc/rk3528-secure-otp.c" 1
887
+ dmb sy
888
+// 0 "" 2
889
+#NO_APP
890
+ ldr x0, [x26]
891
+ mov w1, 31
892
+ str w1, [x0, 4124]
893
+.LVL97:
894
+.LBE58:
895
+.LBB59:
896
+ .loc 1 286 0
897
+#APP
898
+// 286 "drivers/misc/rk3528-secure-otp.c" 1
899
+ dmb sy
900
+// 0 "" 2
901
+#NO_APP
902
+ ldr x0, [x26]
903
+ mov w1, 11
904
+ str w1, [x0, 4128]
905
+.LVL98:
906
+.LBE59:
907
+.LBB60:
908
+ .loc 1 287 0
909
+#APP
910
+// 287 "drivers/misc/rk3528-secure-otp.c" 1
911
+ dmb sy
912
+// 0 "" 2
913
+#NO_APP
914
+ ldr x0, [x26]
915
+ mov w1, 8
916
+ str w1, [x0, 4132]
917
+.LVL99:
918
+.LBE60:
919
+.LBB61:
920
+ .loc 1 288 0
921
+#APP
922
+// 288 "drivers/misc/rk3528-secure-otp.c" 1
923
+ dmb sy
924
+// 0 "" 2
925
+#NO_APP
926
+ ldr x0, [x26]
927
+ str wzr, [x0, 4136]
928
+.LVL100:
929
+.LBE61:
930
+.LBB62:
931
+ .loc 1 289 0
932
+#APP
933
+// 289 "drivers/misc/rk3528-secure-otp.c" 1
934
+ dmb sy
935
+// 0 "" 2
936
+#NO_APP
937
+ ldr x0, [x26]
938
+ str wzr, [x0, 4140]
939
+.LVL101:
940
+.LBE62:
941
+.LBB63:
942
+ .loc 1 290 0
943
+#APP
944
+// 290 "drivers/misc/rk3528-secure-otp.c" 1
945
+ dmb sy
946
+// 0 "" 2
947
+#NO_APP
948
+ ldr x0, [x26]
949
+ str wzr, [x0, 4144]
950
+.LBE63:
951
+.LBB64:
952
+ .loc 1 291 0
953
+ and w0, w20, 255
954
+#APP
955
+// 291 "drivers/misc/rk3528-secure-otp.c" 1
956
+ dmb sy
957
+// 0 "" 2
958
+#NO_APP
959
+ ldr x1, [x26]
960
+.LBE64:
961
+.LBB65:
962
+ .loc 1 292 0
963
+ ubfx x5, x24, 9, 8
964
+.LVL102:
965
+.LBE65:
966
+.LBB66:
967
+ .loc 1 291 0
968
+ str w0, [x1, 4148]
969
+.LBE66:
970
+.LBB67:
971
+ .loc 1 292 0
972
+#APP
973
+// 292 "drivers/misc/rk3528-secure-otp.c" 1
974
+ dmb sy
975
+// 0 "" 2
976
+#NO_APP
977
+ ldr x0, [x26]
978
+ str w5, [x0, 4152]
979
+.LVL103:
980
+.LBE67:
981
+.LBB68:
982
+ .loc 1 293 0
983
+#APP
984
+// 293 "drivers/misc/rk3528-secure-otp.c" 1
985
+ dmb sy
986
+// 0 "" 2
987
+#NO_APP
988
+ ldr x0, [x26]
989
+.LBE68:
990
+ .loc 1 294 0
991
+ mov w1, 2
992
+.LBB69:
993
+ .loc 1 293 0
994
+ str w19, [x0, 32]
995
+.LBE69:
996
+ .loc 1 294 0
997
+ mov x0, x26
998
+ bl rockchip_secure_otp_wait_status.isra.2
999
+.LVL104:
1000
+ .loc 1 295 0
1001
+ tbnz w0, #31, .L40
1002
+.LVL105:
1003
+.LBB70:
1004
+ .loc 1 300 0
1005
+#APP
1006
+// 300 "drivers/misc/rk3528-secure-otp.c" 1
1007
+ dmb sy
1008
+// 0 "" 2
1009
+#NO_APP
1010
+ ldr x0, [x26]
1011
+.LVL106:
1012
+ mov w1, -65535
1013
+ str w1, [x0, 36]
1014
+.LVL107:
1015
+.LBE70:
1016
+.LBB71:
1017
+ .loc 1 301 0
1018
+#APP
1019
+// 301 "drivers/misc/rk3528-secure-otp.c" 1
1020
+ dmb sy
1021
+// 0 "" 2
1022
+#NO_APP
1023
+ ldr x0, [x26]
1024
+ mov w1, 250
1025
+ str w1, [x0, 4096]
1026
+.LVL108:
1027
+.LBE71:
1028
+.LBB72:
1029
+ .loc 1 302 0
1030
+#APP
1031
+// 302 "drivers/misc/rk3528-secure-otp.c" 1
1032
+ dmb sy
1033
+// 0 "" 2
1034
+#NO_APP
1035
+ ldr x0, [x26]
1036
+ mov w1, 9
1037
+ str w1, [x0, 4100]
1038
+.LVL109:
1039
+.LBE72:
1040
+.LBB73:
1041
+ .loc 1 303 0
1042
+#APP
1043
+// 303 "drivers/misc/rk3528-secure-otp.c" 1
1044
+ dmb sy
1045
+// 0 "" 2
1046
+#NO_APP
1047
+ ldr x0, [x26]
1048
+.LBE73:
1049
+ .loc 1 304 0
1050
+ mov w1, 2
1051
+.LBB74:
1052
+ .loc 1 303 0
1053
+ str w19, [x0, 32]
1054
+.LBE74:
1055
+ .loc 1 304 0
1056
+ mov x0, x26
1057
+ bl rockchip_secure_otp_wait_status.isra.2
1058
+.LVL110:
1059
+ .loc 1 305 0
1060
+ tbnz w0, #31, .L40
1061
+.LVL111:
1062
+.LBB75:
1063
+ .loc 1 310 0
1064
+#APP
1065
+// 310 "drivers/misc/rk3528-secure-otp.c" 1
1066
+ dmb sy
1067
+// 0 "" 2
1068
+#NO_APP
1069
+ ldr x0, [x26]
1070
+.LVL112:
1071
+ mov w1, 14848
1072
+ movk w1, 0xff00, lsl 16
1073
+ str w1, [x0, 32]
1074
+.LVL113:
1075
+.LBE75:
1076
+.LBB76:
1077
+ .loc 1 311 0
1078
+#APP
1079
+// 311 "drivers/misc/rk3528-secure-otp.c" 1
1080
+ dmb sy
1081
+// 0 "" 2
1082
+#NO_APP
1083
+ ldr x0, [x26]
1084
+ str w28, [x0, 36]
1085
+.LVL114:
1086
+.LBE76:
1087
+.LBB77:
1088
+ .loc 1 312 0
1089
+#APP
1090
+// 312 "drivers/misc/rk3528-secure-otp.c" 1
1091
+ dmb sy
1092
+// 0 "" 2
1093
+#NO_APP
1094
+ ldr x0, [x26]
1095
+ str w27, [x0, 4096]
1096
+.LVL115:
1097
+.LBE77:
1098
+.LBB78:
1099
+ .loc 1 313 0
1100
+#APP
1101
+// 313 "drivers/misc/rk3528-secure-otp.c" 1
1102
+ dmb sy
1103
+// 0 "" 2
1104
+#NO_APP
1105
+ ldr x0, [x26]
1106
+ mov w1, 1
1107
+ str w1, [x0, 4100]
1108
+.LVL116:
1109
+.LBE78:
1110
+.LBB79:
1111
+ .loc 1 314 0
1112
+#APP
1113
+// 314 "drivers/misc/rk3528-secure-otp.c" 1
1114
+ dmb sy
1115
+// 0 "" 2
1116
+#NO_APP
1117
+ ldr x0, [x26]
1118
+ str w25, [x0, 4104]
1119
+.LVL117:
1120
+.LBE79:
1121
+.LBB80:
1122
+ .loc 1 315 0
1123
+#APP
1124
+// 315 "drivers/misc/rk3528-secure-otp.c" 1
1125
+ dmb sy
1126
+// 0 "" 2
1127
+#NO_APP
1128
+ ldr x0, [x26]
1129
+ mov w1, 21
1130
+ str w1, [x0, 4108]
1131
+.LVL118:
1132
+.LBE80:
1133
+.LBB81:
1134
+ .loc 1 316 0
1135
+#APP
1136
+// 316 "drivers/misc/rk3528-secure-otp.c" 1
1137
+ dmb sy
1138
+// 0 "" 2
1139
+#NO_APP
1140
+ ldr x0, [x26]
1141
+ mov w1, 220
1142
+ str w1, [x0, 4112]
1143
+.LVL119:
1144
+.LBE81:
1145
+.LBB82:
1146
+ .loc 1 317 0
1147
+#APP
1148
+// 317 "drivers/misc/rk3528-secure-otp.c" 1
1149
+ dmb sy
1150
+// 0 "" 2
1151
+#NO_APP
1152
+ ldr x0, [x26]
1153
+ mov w1, 146
1154
+ str w1, [x0, 4116]
1155
+.LVL120:
1156
+.LBE82:
1157
+.LBB83:
1158
+ .loc 1 318 0
1159
+#APP
1160
+// 318 "drivers/misc/rk3528-secure-otp.c" 1
1161
+ dmb sy
1162
+// 0 "" 2
1163
+#NO_APP
1164
+ ldr x0, [x26]
1165
+ mov w1, 121
1166
+ str w1, [x0, 4120]
1167
+.LVL121:
1168
+.LBE83:
1169
+.LBB84:
1170
+ .loc 1 319 0
1171
+#APP
1172
+// 319 "drivers/misc/rk3528-secure-otp.c" 1
1173
+ dmb sy
1174
+// 0 "" 2
1175
+#NO_APP
1176
+ ldr x0, [x26]
1177
+ mov w1, 129
1178
+ str w1, [x0, 4124]
1179
+.LVL122:
1180
+.LBE84:
1181
+.LBB85:
1182
+ .loc 1 320 0
1183
+#APP
1184
+// 320 "drivers/misc/rk3528-secure-otp.c" 1
1185
+ dmb sy
1186
+// 0 "" 2
1187
+#NO_APP
1188
+ ldr x0, [x26]
1189
+ mov w1, 126
1190
+ str w1, [x0, 4128]
1191
+.LVL123:
1192
+.LBE85:
1193
+.LBB86:
1194
+ .loc 1 321 0
1195
+#APP
1196
+// 321 "drivers/misc/rk3528-secure-otp.c" 1
1197
+ dmb sy
1198
+// 0 "" 2
1199
+#NO_APP
1200
+ ldr x0, [x26]
1201
+ mov w1, 33
1202
+ str w1, [x0, 4132]
1203
+.LVL124:
1204
+.LBE86:
1205
+.LBB87:
1206
+ .loc 1 322 0
1207
+#APP
1208
+// 322 "drivers/misc/rk3528-secure-otp.c" 1
1209
+ dmb sy
1210
+// 0 "" 2
1211
+#NO_APP
1212
+ ldr x0, [x26]
1213
+ mov w1, 17
1214
+ str w1, [x0, 4136]
1215
+.LVL125:
1216
+.LBE87:
1217
+.LBB88:
1218
+ .loc 1 323 0
1219
+#APP
1220
+// 323 "drivers/misc/rk3528-secure-otp.c" 1
1221
+ dmb sy
1222
+// 0 "" 2
1223
+#NO_APP
1224
+ ldr x0, [x26]
1225
+ mov w1, 157
1226
+ str w1, [x0, 4140]
1227
+.LVL126:
1228
+.LBE88:
1229
+.LBB89:
1230
+ .loc 1 324 0
1231
+#APP
1232
+// 324 "drivers/misc/rk3528-secure-otp.c" 1
1233
+ dmb sy
1234
+// 0 "" 2
1235
+#NO_APP
1236
+ ldr x0, [x26]
1237
+ mov w25, 2
1238
+ str w25, [x0, 4144]
1239
+.LVL127:
1240
+.LBE89:
1241
+.LBB90:
1242
+ .loc 1 325 0
1243
+#APP
1244
+// 325 "drivers/misc/rk3528-secure-otp.c" 1
1245
+ dmb sy
1246
+// 0 "" 2
1247
+#NO_APP
1248
+ ldr x0, [x26]
1249
+ str wzr, [x0, 4148]
1250
+.LVL128:
1251
+.LBE90:
1252
+.LBB91:
1253
+ .loc 1 326 0
1254
+#APP
1255
+// 326 "drivers/misc/rk3528-secure-otp.c" 1
1256
+ dmb sy
1257
+// 0 "" 2
1258
+#NO_APP
1259
+ ldr x0, [x26]
1260
+ mov w1, 64
1261
+ str w1, [x0, 4152]
1262
+.LVL129:
1263
+.LBE91:
1264
+.LBB92:
1265
+ .loc 1 327 0
1266
+#APP
1267
+// 327 "drivers/misc/rk3528-secure-otp.c" 1
1268
+ dmb sy
1269
+// 0 "" 2
1270
+#NO_APP
1271
+ ldr x0, [x26]
1272
+.LBE92:
1273
+ .loc 1 328 0
1274
+ mov w1, w25
1275
+.LBB93:
1276
+ .loc 1 327 0
1277
+ str w19, [x0, 32]
1278
+.LBE93:
1279
+ .loc 1 328 0
1280
+ mov x0, x26
1281
+ bl rockchip_secure_otp_wait_status.isra.2
1282
+.LVL130:
1283
+ .loc 1 329 0
1284
+ tbnz w0, #31, .L40
1285
+.LVL131:
1286
+.LBB94:
1287
+ .loc 1 334 0
1288
+#APP
1289
+// 334 "drivers/misc/rk3528-secure-otp.c" 1
1290
+ dmb sy
1291
+// 0 "" 2
1292
+#NO_APP
1293
+ ldr x0, [x26]
1294
+.LVL132:
1295
+ str w22, [x0, 36]
1296
+.LVL133:
1297
+.LBE94:
1298
+.LBB95:
1299
+ .loc 1 335 0
1300
+#APP
1301
+// 335 "drivers/misc/rk3528-secure-otp.c" 1
1302
+ dmb sy
1303
+// 0 "" 2
1304
+#NO_APP
1305
+ ldr x0, [x26]
1306
+ mov w1, 252
1307
+ str w1, [x0, 4096]
1308
+.LVL134:
1309
+.LBE95:
1310
+.LBB96:
1311
+ .loc 1 336 0
1312
+#APP
1313
+// 336 "drivers/misc/rk3528-secure-otp.c" 1
1314
+ dmb sy
1315
+// 0 "" 2
1316
+#NO_APP
1317
+ ldr x0, [x26]
1318
+ mov w1, 10
1319
+ str w1, [x0, 4100]
1320
+.LVL135:
1321
+.LBE96:
1322
+.LBB97:
1323
+ .loc 1 337 0
1324
+#APP
1325
+// 337 "drivers/misc/rk3528-secure-otp.c" 1
1326
+ dmb sy
1327
+// 0 "" 2
1328
+#NO_APP
1329
+ ldr x0, [x26]
1330
+ mov w1, 112
1331
+ str w1, [x0, 4104]
1332
+.LVL136:
1333
+.LBE97:
1334
+.LBB98:
1335
+ .loc 1 338 0
1336
+#APP
1337
+// 338 "drivers/misc/rk3528-secure-otp.c" 1
1338
+ dmb sy
1339
+// 0 "" 2
1340
+#NO_APP
1341
+ ldr x0, [x26]
1342
+.LBE98:
1343
+ .loc 1 339 0
1344
+ mov w1, w25
1345
+.LBB99:
1346
+ .loc 1 338 0
1347
+ str w19, [x0, 32]
1348
+.LBE99:
1349
+ .loc 1 339 0
1350
+ mov x0, x26
1351
+ bl rockchip_secure_otp_wait_status.isra.2
1352
+.LVL137:
1353
+ .loc 1 340 0
1354
+ tbnz w0, #31, .L40
1355
+.LVL138:
1356
+.LBB100:
1357
+ .loc 1 345 0
1358
+#APP
1359
+// 345 "drivers/misc/rk3528-secure-otp.c" 1
1360
+ dmb sy
1361
+// 0 "" 2
1362
+#NO_APP
1363
+ ldr x0, [x26]
1364
+.LVL139:
1365
+ mov w1, 512
1366
+ movk w1, 0xff00, lsl 16
1367
+ str w1, [x0, 32]
1368
+.LVL140:
1369
+.LBE100:
1370
+.LBB101:
1371
+ .loc 1 346 0
1372
+#APP
1373
+// 346 "drivers/misc/rk3528-secure-otp.c" 1
1374
+ dmb sy
1375
+// 0 "" 2
1376
+#NO_APP
1377
+ ldr x0, [x26]
1378
+ str w22, [x0, 36]
1379
+.LVL141:
1380
+.LBE101:
1381
+.LBB102:
1382
+ .loc 1 347 0
1383
+#APP
1384
+// 347 "drivers/misc/rk3528-secure-otp.c" 1
1385
+ dmb sy
1386
+// 0 "" 2
1387
+#NO_APP
1388
+ ldr x0, [x26]
1389
+ mov w1, 192
1390
+ str w1, [x0, 4096]
1391
+.LBE102:
1392
+.LBB103:
1393
+ .loc 1 348 0
1394
+ and w1, w21, 255
1395
+.LVL142:
1396
+#APP
1397
+// 348 "drivers/misc/rk3528-secure-otp.c" 1
1398
+ dmb sy
1399
+// 0 "" 2
1400
+#NO_APP
1401
+ ldr x0, [x26]
1402
+.LBE103:
1403
+.LBB104:
1404
+ .loc 1 349 0
1405
+ lsr w21, w21, 8
1406
+.LVL143:
1407
+.LBE104:
1408
+.LBB105:
1409
+ .loc 1 348 0
1410
+ str w1, [x0, 4100]
1411
+.LBE105:
1412
+.LBB106:
1413
+ .loc 1 349 0
1414
+#APP
1415
+// 349 "drivers/misc/rk3528-secure-otp.c" 1
1416
+ dmb sy
1417
+// 0 "" 2
1418
+#NO_APP
1419
+ ldr x0, [x26]
1420
+ str w21, [x0, 4104]
1421
+.LVL144:
1422
+.LBE106:
1423
+.LBB107:
1424
+ .loc 1 350 0
1425
+#APP
1426
+// 350 "drivers/misc/rk3528-secure-otp.c" 1
1427
+ dmb sy
1428
+// 0 "" 2
1429
+#NO_APP
1430
+ ldr x0, [x26]
1431
+.LBE107:
1432
+ .loc 1 351 0
1433
+ mov w1, w25
1434
+.LVL145:
1435
+.LBB108:
1436
+ .loc 1 350 0
1437
+ str w19, [x0, 32]
1438
+.LBE108:
1439
+ .loc 1 351 0
1440
+ mov x0, x26
1441
+ bl rockchip_secure_otp_wait_status.isra.2
1442
+.LVL146:
1443
+ .loc 1 352 0
1444
+ tbnz w0, #31, .L40
1445
+.LVL147:
1446
+.LBB109:
1447
+ .loc 1 357 0
1448
+#APP
1449
+// 357 "drivers/misc/rk3528-secure-otp.c" 1
1450
+ dmb sy
1451
+// 0 "" 2
1452
+#NO_APP
1453
+ ldr x0, [x26]
1454
+.LVL148:
1455
+ mov w1, -65535
1456
+ str w1, [x0, 36]
1457
+.LVL149:
1458
+.LBE109:
1459
+.LBB110:
1460
+ .loc 1 358 0
1461
+#APP
1462
+// 358 "drivers/misc/rk3528-secure-otp.c" 1
1463
+ dmb sy
1464
+// 0 "" 2
1465
+#NO_APP
1466
+ ldr x0, [x26]
1467
+ mov w1, 224
1468
+ str w1, [x0, 4096]
1469
+.LVL150:
1470
+.LBE110:
1471
+.LBB111:
1472
+ .loc 1 359 0
1473
+#APP
1474
+// 359 "drivers/misc/rk3528-secure-otp.c" 1
1475
+ dmb sy
1476
+// 0 "" 2
1477
+#NO_APP
1478
+ ldr x0, [x26]
1479
+ str wzr, [x0, 4100]
1480
+.LVL151:
1481
+.LBE111:
1482
+.LBB112:
1483
+ .loc 1 360 0
1484
+#APP
1485
+// 360 "drivers/misc/rk3528-secure-otp.c" 1
1486
+ dmb sy
1487
+// 0 "" 2
1488
+#NO_APP
1489
+ ldr x0, [x26]
1490
+.LBE112:
1491
+ .loc 1 361 0
1492
+ mov w1, w25
1493
+.LBB113:
1494
+ .loc 1 360 0
1495
+ str w19, [x0, 32]
1496
+.LBE113:
1497
+ .loc 1 361 0
1498
+ mov x0, x26
1499
+ bl rockchip_secure_otp_wait_status.isra.2
1500
+.LVL152:
1501
+ .loc 1 362 0
1502
+ tbnz w0, #31, .L40
1503
+.LVL153:
1504
+.LBB114:
1505
+ .loc 1 367 0
1506
+#APP
1507
+// 367 "drivers/misc/rk3528-secure-otp.c" 1
1508
+ dmb sy
1509
+// 0 "" 2
1510
+#NO_APP
1511
+ ldr x0, [x26]
1512
+.LVL154:
1513
+ mov w22, -65535
1514
+ str w22, [x0, 36]
1515
+.LVL155:
1516
+.LBE114:
1517
+.LBB115:
1518
+ .loc 1 368 0
1519
+#APP
1520
+// 368 "drivers/misc/rk3528-secure-otp.c" 1
1521
+ dmb sy
1522
+// 0 "" 2
1523
+#NO_APP
1524
+ ldr x0, [x26]
1525
+ mov w1, 14848
1526
+ movk w1, 0xff00, lsl 16
1527
+ str w1, [x0, 32]
1528
+.LVL156:
1529
+.LBE115:
1530
+.LBB116:
1531
+ .loc 1 369 0
1532
+#APP
1533
+// 369 "drivers/misc/rk3528-secure-otp.c" 1
1534
+ dmb sy
1535
+// 0 "" 2
1536
+#NO_APP
1537
+ ldr x0, [x26]
1538
+ mov w1, 255
1539
+ str w1, [x0, 4096]
1540
+.LVL157:
1541
+.LBE116:
1542
+.LBB117:
1543
+ .loc 1 370 0
1544
+#APP
1545
+// 370 "drivers/misc/rk3528-secure-otp.c" 1
1546
+ dmb sy
1547
+// 0 "" 2
1548
+#NO_APP
1549
+ ldr x0, [x26]
1550
+ mov w1, 10
1551
+ str w1, [x0, 4100]
1552
+.LVL158:
1553
+.LBE117:
1554
+.LBB118:
1555
+ .loc 1 371 0
1556
+#APP
1557
+// 371 "drivers/misc/rk3528-secure-otp.c" 1
1558
+ dmb sy
1559
+// 0 "" 2
1560
+#NO_APP
1561
+ ldr x0, [x26]
1562
+ mov w21, 65537
1563
+.LVL159:
1564
+.LBE118:
1565
+ .loc 1 372 0
1566
+ mov w1, w25
1567
+.LBB119:
1568
+ .loc 1 371 0
1569
+ str w21, [x0, 32]
1570
+.LBE119:
1571
+ .loc 1 372 0
1572
+ mov x0, x26
1573
+ bl rockchip_secure_otp_wait_status.isra.2
1574
+.LVL160:
1575
+ .loc 1 373 0
1576
+ tbnz w0, #31, .L40
1577
+.LVL161:
1578
+.LBB120:
1579
+ .loc 1 378 0
1580
+#APP
1581
+// 378 "drivers/misc/rk3528-secure-otp.c" 1
1582
+ dmb sy
1583
+// 0 "" 2
1584
+#NO_APP
1585
+ ldr x0, [x26]
1586
+.LVL162:
1587
+ str w22, [x0, 36]
1588
+.LVL163:
1589
+.LBE120:
1590
+.LBB121:
1591
+ .loc 1 379 0
1592
+#APP
1593
+// 379 "drivers/misc/rk3528-secure-otp.c" 1
1594
+ dmb sy
1595
+// 0 "" 2
1596
+#NO_APP
1597
+ ldr x0, [x26]
1598
+ mov w1, 1
1599
+ str w1, [x0, 4096]
1600
+.LVL164:
1601
+.LBE121:
1602
+.LBB122:
1603
+ .loc 1 380 0
1604
+#APP
1605
+// 380 "drivers/misc/rk3528-secure-otp.c" 1
1606
+ dmb sy
1607
+// 0 "" 2
1608
+#NO_APP
1609
+ ldr x0, [x26]
1610
+ mov w24, 191
1611
+.LVL165:
1612
+ str w24, [x0, 4100]
1613
+.LVL166:
1614
+.LBE122:
1615
+.LBB123:
1616
+ .loc 1 381 0
1617
+#APP
1618
+// 381 "drivers/misc/rk3528-secure-otp.c" 1
1619
+ dmb sy
1620
+// 0 "" 2
1621
+#NO_APP
1622
+ ldr x0, [x26]
1623
+.LBE123:
1624
+ .loc 1 382 0
1625
+ mov w1, w25
1626
+.LBB124:
1627
+ .loc 1 381 0
1628
+ str w21, [x0, 32]
1629
+.LBE124:
1630
+ .loc 1 382 0
1631
+ mov x0, x26
1632
+ bl rockchip_secure_otp_wait_status.isra.2
1633
+.LVL167:
1634
+ .loc 1 383 0
1635
+ tbnz w0, #31, .L40
1636
+ .loc 1 388 0
1637
+ mov x0, x26
1638
+.LVL168:
1639
+ bl rockchip_secure_otp_check_flag.isra.0
1640
+.LVL169:
1641
+ .loc 1 389 0
1642
+ tbz w0, #31, .L41
1643
+ .loc 1 390 0
1644
+ adrp x1, .LANCHOR1
1645
+ adrp x0, .LC6
1646
+.LVL170:
1647
+ add x1, x1, :lo12:.LANCHOR1
1648
+ add x0, x0, :lo12:.LC6
1649
+ b .L46
1650
+.LVL171:
1651
+.L41:
1652
+.LBB125:
1653
+ .loc 1 394 0
1654
+#APP
1655
+// 394 "drivers/misc/rk3528-secure-otp.c" 1
1656
+ dmb sy
1657
+// 0 "" 2
1658
+#NO_APP
1659
+ ldr x0, [x26]
1660
+.LVL172:
1661
+ str w22, [x0, 36]
1662
+.LVL173:
1663
+.LBE125:
1664
+.LBB126:
1665
+ .loc 1 395 0
1666
+#APP
1667
+// 395 "drivers/misc/rk3528-secure-otp.c" 1
1668
+ dmb sy
1669
+// 0 "" 2
1670
+#NO_APP
1671
+ ldr x0, [x26]
1672
+ mov w19, 2
1673
+ str w19, [x0, 4096]
1674
+.LVL174:
1675
+.LBE126:
1676
+.LBB127:
1677
+ .loc 1 396 0
1678
+#APP
1679
+// 396 "drivers/misc/rk3528-secure-otp.c" 1
1680
+ dmb sy
1681
+// 0 "" 2
1682
+#NO_APP
1683
+ ldr x0, [x26]
1684
+ str w24, [x0, 4100]
1685
+.LVL175:
1686
+.LBE127:
1687
+.LBB128:
1688
+ .loc 1 397 0
1689
+#APP
1690
+// 397 "drivers/misc/rk3528-secure-otp.c" 1
1691
+ dmb sy
1692
+// 0 "" 2
1693
+#NO_APP
1694
+ ldr x0, [x26]
1695
+.LBE128:
1696
+ .loc 1 398 0
1697
+ mov w1, w19
1698
+.LBB129:
1699
+ .loc 1 397 0
1700
+ str w21, [x0, 32]
1701
+.LBE129:
1702
+ .loc 1 398 0
1703
+ mov x0, x26
1704
+ bl rockchip_secure_otp_wait_status.isra.2
1705
+.LVL176:
1706
+ .loc 1 399 0
1707
+ tbnz w0, #31, .L40
1708
+ .loc 1 404 0
1709
+ mov x0, x26
1710
+.LVL177:
1711
+ bl rockchip_secure_otp_wait_flag.isra.1
1712
+.LVL178:
1713
+ .loc 1 405 0
1714
+ tbz w0, #31, .L42
1715
+ .loc 1 406 0
1716
+ adrp x1, .LANCHOR1
1717
+ adrp x0, .LC7
1718
+.LVL179:
1719
+ add x1, x1, :lo12:.LANCHOR1
1720
+ add x0, x0, :lo12:.LC7
1721
+ b .L46
1722
+.LVL180:
1723
+.L42:
1724
+.LBB130:
1725
+ .loc 1 410 0
1726
+#APP
1727
+// 410 "drivers/misc/rk3528-secure-otp.c" 1
1728
+ dmb sy
1729
+// 0 "" 2
1730
+#NO_APP
1731
+ ldr x0, [x26]
1732
+.LVL181:
1733
+ mov w1, -65533
1734
+ str w1, [x0, 772]
1735
+.LVL182:
1736
+.LBE130:
1737
+.LBB131:
1738
+ .loc 1 411 0
1739
+#APP
1740
+// 411 "drivers/misc/rk3528-secure-otp.c" 1
1741
+ dmb sy
1742
+// 0 "" 2
1743
+#NO_APP
1744
+ ldr x0, [x26]
1745
+ mov w1, 512
1746
+ movk w1, 0xff00, lsl 16
1747
+ str w1, [x0, 32]
1748
+.LVL183:
1749
+.LBE131:
1750
+.LBB132:
1751
+ .loc 1 412 0
1752
+#APP
1753
+// 412 "drivers/misc/rk3528-secure-otp.c" 1
1754
+ dmb sy
1755
+// 0 "" 2
1756
+#NO_APP
1757
+ ldr x0, [x26]
1758
+ str w22, [x0, 36]
1759
+.LVL184:
1760
+.LBE132:
1761
+.LBB133:
1762
+ .loc 1 413 0
1763
+#APP
1764
+// 413 "drivers/misc/rk3528-secure-otp.c" 1
1765
+ dmb sy
1766
+// 0 "" 2
1767
+#NO_APP
1768
+ ldr x0, [x26]
1769
+ str w19, [x0, 4096]
1770
+.LVL185:
1771
+.LBE133:
1772
+.LBB134:
1773
+ .loc 1 414 0
1774
+#APP
1775
+// 414 "drivers/misc/rk3528-secure-otp.c" 1
1776
+ dmb sy
1777
+// 0 "" 2
1778
+#NO_APP
1779
+ ldr x0, [x26]
1780
+ mov w1, 128
1781
+ str w1, [x0, 4100]
1782
+.LVL186:
1783
+.LBE134:
1784
+.LBB135:
1785
+ .loc 1 415 0
1786
+#APP
1787
+// 415 "drivers/misc/rk3528-secure-otp.c" 1
1788
+ dmb sy
1789
+// 0 "" 2
1790
+#NO_APP
1791
+ ldr x0, [x26]
1792
+.LBE135:
1793
+ .loc 1 416 0
1794
+ mov w1, w19
1795
+.LBB136:
1796
+ .loc 1 415 0
1797
+ str w21, [x0, 32]
1798
+.LBE136:
1799
+ .loc 1 416 0
1800
+ mov x0, x26
1801
+ bl rockchip_secure_otp_wait_status.isra.2
1802
+.LVL187:
1803
+ .loc 1 417 0
1804
+ tbnz w0, #31, .L40
1805
+.LVL188:
1806
+.LBB137:
1807
+ .loc 1 422 0
1808
+#APP
1809
+// 422 "drivers/misc/rk3528-secure-otp.c" 1
1810
+ dmb sy
1811
+// 0 "" 2
1812
+#NO_APP
1813
+ ldr x0, [x26]
1814
+.LVL189:
1815
+ str w22, [x0, 36]
1816
+.LVL190:
1817
+.LBE137:
1818
+.LBB138:
1819
+ .loc 1 423 0
1820
+#APP
1821
+// 423 "drivers/misc/rk3528-secure-otp.c" 1
1822
+ dmb sy
1823
+// 0 "" 2
1824
+#NO_APP
1825
+ ldr x0, [x26]
1826
+ mov w1, 160
1827
+ str w1, [x0, 4096]
1828
+.LVL191:
1829
+.LBE138:
1830
+.LBB139:
1831
+ .loc 1 424 0
1832
+#APP
1833
+// 424 "drivers/misc/rk3528-secure-otp.c" 1
1834
+ dmb sy
1835
+// 0 "" 2
1836
+#NO_APP
1837
+ ldr x0, [x26]
1838
+ str wzr, [x0, 4100]
1839
+.LVL192:
1840
+.LBE139:
1841
+.LBB140:
1842
+ .loc 1 425 0
1843
+#APP
1844
+// 425 "drivers/misc/rk3528-secure-otp.c" 1
1845
+ dmb sy
1846
+// 0 "" 2
1847
+#NO_APP
1848
+ ldr x0, [x26]
1849
+.LBE140:
1850
+ .loc 1 426 0
1851
+ mov w1, w19
1852
+.LBB141:
1853
+ .loc 1 425 0
1854
+ str w21, [x0, 32]
1855
+.LBE141:
1856
+ .loc 1 426 0
1857
+ mov x0, x26
1858
+ bl rockchip_secure_otp_wait_status.isra.2
1859
+.LVL193:
1860
+ .loc 1 427 0
1861
+ tbnz w0, #31, .L40
1862
+.LVL194:
1863
+.LBB142:
1864
+ .loc 1 432 0
1865
+#APP
1866
+// 432 "drivers/misc/rk3528-secure-otp.c" 1
1867
+ dmb sy
1868
+// 0 "" 2
1869
+#NO_APP
1870
+ ldr x0, [x26]
1871
+.LVL195:
1872
+ mov w1, 250
1873
+ str w1, [x0, 4096]
1874
+.LVL196:
1875
+.LBE142:
1876
+.LBB143:
1877
+ .loc 1 433 0
1878
+#APP
1879
+// 433 "drivers/misc/rk3528-secure-otp.c" 1
1880
+ dmb sy
1881
+// 0 "" 2
1882
+#NO_APP
1883
+ ldr x0, [x26]
1884
+ mov w1, 9
1885
+ str w1, [x0, 4100]
1886
+.LVL197:
1887
+.LBE143:
1888
+.LBB144:
1889
+ .loc 1 434 0
1890
+#APP
1891
+// 434 "drivers/misc/rk3528-secure-otp.c" 1
1892
+ dmb sy
1893
+// 0 "" 2
1894
+#NO_APP
1895
+ ldr x0, [x26]
1896
+.LBE144:
1897
+ .loc 1 435 0
1898
+ mov w1, w19
1899
+.LBB145:
1900
+ .loc 1 434 0
1901
+ str w21, [x0, 32]
1902
+.LBE145:
1903
+ .loc 1 435 0
1904
+ mov x0, x26
1905
+ bl rockchip_secure_otp_wait_status.isra.2
1906
+.LVL198:
1907
+ .loc 1 436 0
1908
+ tbz w0, #31, .L39
1909
+ b .L40
1910
+ .cfi_endproc
1911
+.LFE269:
1912
+ .size rk3528_secure_otp_write_2_bytes_noecc, .-rk3528_secure_otp_write_2_bytes_noecc
1913
+ .section .text.rockchip_secure_otp_ecc_enable,"ax",@progbits
1914
+ .align 2
1915
+ .type rockchip_secure_otp_ecc_enable, %function
1916
+rockchip_secure_otp_ecc_enable:
1917
+.LFB267:
1918
+ .loc 1 154 0
1919
+ .cfi_startproc
1920
+.LVL199:
1921
+ stp x29, x30, [sp, -32]!
1922
+ .cfi_def_cfa_offset 32
1923
+ .cfi_offset 29, -32
1924
+ .cfi_offset 30, -24
1925
+ and w1, w1, 255
1926
+ add x29, sp, 0
1927
+ .cfi_def_cfa_register 29
1928
+ str x19, [sp, 16]
1929
+ .cfi_offset 19, -16
1930
+.LBB160:
1931
+ .loc 1 157 0
1932
+#APP
1933
+// 157 "drivers/misc/rk3528-secure-otp.c" 1
1934
+ dmb sy
1935
+// 0 "" 2
1936
+#NO_APP
1937
+ ldr x2, [x0]
1938
+ mov w3, 512
1939
+ movk w3, 0xff00, lsl 16
1940
+ str w3, [x2, 32]
1941
+.LVL200:
1942
+.LBE160:
1943
+.LBB161:
1944
+ .loc 1 158 0
1945
+#APP
1946
+// 158 "drivers/misc/rk3528-secure-otp.c" 1
1947
+ dmb sy
1948
+// 0 "" 2
1949
+#NO_APP
1950
+ ldr x2, [x0]
1951
+ mov w3, -65535
1952
+ str w3, [x2, 36]
1953
+.LVL201:
1954
+.LBE161:
1955
+.LBB162:
1956
+ .loc 1 159 0
1957
+#APP
1958
+// 159 "drivers/misc/rk3528-secure-otp.c" 1
1959
+ dmb sy
1960
+// 0 "" 2
1961
+#NO_APP
1962
+ ldr x2, [x0]
1963
+ mov w3, 250
1964
+ str w3, [x2, 4096]
1965
+.LBE162:
1966
+ .loc 1 160 0
1967
+ cbz w1, .L48
1968
+.LVL202:
1969
+.LBB163:
1970
+ .loc 1 161 0
1971
+#APP
1972
+// 161 "drivers/misc/rk3528-secure-otp.c" 1
1973
+ dmb sy
1974
+// 0 "" 2
1975
+#NO_APP
1976
+ ldr x1, [x0]
1977
+.LVL203:
1978
+ str wzr, [x1, 4100]
1979
+.LVL204:
1980
+.L49:
1981
+.LBE163:
1982
+.LBB164:
1983
+ .loc 1 165 0
1984
+#APP
1985
+// 165 "drivers/misc/rk3528-secure-otp.c" 1
1986
+ dmb sy
1987
+// 0 "" 2
1988
+#NO_APP
1989
+ ldr x1, [x0]
1990
+ mov w2, 65537
1991
+ str w2, [x1, 32]
1992
+.LBE164:
1993
+ .loc 1 167 0
1994
+ mov w1, 2
1995
+ bl rockchip_secure_otp_wait_status.isra.2
1996
+.LVL205:
1997
+ mov w19, w0
1998
+.LVL206:
1999
+ .loc 1 168 0
2000
+ tbz w0, #31, .L47
2001
+.LVL207:
2002
+.LBB165:
2003
+.LBB166:
2004
+ .loc 1 169 0
2005
+ adrp x1, .LANCHOR2
2006
+ adrp x0, .LC8
2007
+.LVL208:
2008
+ add x1, x1, :lo12:.LANCHOR2
2009
+ add x0, x0, :lo12:.LC8
2010
+ bl printf
2011
+.LVL209:
2012
+.L47:
2013
+.LBE166:
2014
+.LBE165:
2015
+ .loc 1 172 0
2016
+ mov w0, w19
2017
+ ldr x19, [sp, 16]
2018
+.LVL210:
2019
+ ldp x29, x30, [sp], 32
2020
+ .cfi_remember_state
2021
+ .cfi_restore 30
2022
+ .cfi_restore 29
2023
+ .cfi_restore 19
2024
+ .cfi_def_cfa 31, 0
2025
+ ret
2026
+.LVL211:
2027
+.L48:
2028
+ .cfi_restore_state
2029
+.LBB167:
2030
+ .loc 1 163 0
2031
+#APP
2032
+// 163 "drivers/misc/rk3528-secure-otp.c" 1
2033
+ dmb sy
2034
+// 0 "" 2
2035
+#NO_APP
2036
+ ldr x1, [x0]
2037
+ mov w2, 9
2038
+ str w2, [x1, 4100]
2039
+ b .L49
2040
+.LBE167:
2041
+ .cfi_endproc
2042
+.LFE267:
2043
+ .size rockchip_secure_otp_ecc_enable, .-rockchip_secure_otp_ecc_enable
2044
+ .section .text.rk3528_secure_otp_read,"ax",@progbits
2045
+ .align 2
2046
+ .type rk3528_secure_otp_read, %function
2047
+rk3528_secure_otp_read:
2048
+.LFB268:
2049
+ .loc 1 176 0
2050
+ .cfi_startproc
2051
+.LVL212:
2052
+ stp x29, x30, [sp, -80]!
2053
+ .cfi_def_cfa_offset 80
2054
+ .cfi_offset 29, -80
2055
+ .cfi_offset 30, -72
2056
+ add x29, sp, 0
2057
+ .cfi_def_cfa_register 29
2058
+ stp x19, x20, [sp, 16]
2059
+ .cfi_offset 19, -64
2060
+ .cfi_offset 20, -56
2061
+ .loc 1 183 0
2062
+ asr w19, w1, 1
2063
+ .loc 1 176 0
2064
+ stp x21, x22, [sp, 32]
2065
+ .cfi_offset 21, -48
2066
+ .cfi_offset 22, -40
2067
+ mov x21, x2
2068
+ stp x23, x24, [sp, 48]
2069
+ mov x22, x0
2070
+ .cfi_offset 23, -32
2071
+ .cfi_offset 24, -24
2072
+ mov w23, w3
2073
+ str x25, [sp, 64]
2074
+ .cfi_offset 25, -16
2075
+ .loc 1 177 0
2076
+ bl dev_get_platdata
2077
+.LVL213:
2078
+ mov x20, x0
2079
+.LVL214:
2080
+ .loc 1 178 0
2081
+ mov x0, x22
2082
+.LVL215:
2083
+ bl dev_get_driver_data
2084
+.LVL216:
2085
+ .loc 1 184 0
2086
+ ldr x4, [x0, 16]
2087
+ .loc 1 178 0
2088
+ mov x24, x0
2089
+.LVL217:
2090
+ .loc 1 184 0
2091
+ ldr x1, [x20, 24]
2092
+ mov w3, w19
2093
+ ldp x0, x2, [x20, 8]
2094
+.LVL218:
2095
+ blr x4
2096
+.LVL219:
2097
+ .loc 1 187 0
2098
+ sub w1, w19, #16
2099
+ sub w0, w19, #416
2100
+ cmp w1, 15
2101
+ ccmp w0, 31, 0, hi
2102
+ bhi .L53
2103
+ .loc 1 188 0
2104
+ mov w1, 0
2105
+.L65:
2106
+ .loc 1 190 0
2107
+ mov x0, x20
2108
+ bl rockchip_secure_otp_ecc_enable
2109
+.LVL220:
2110
+.LBB168:
2111
+ .loc 1 192 0
2112
+#APP
2113
+// 192 "drivers/misc/rk3528-secure-otp.c" 1
2114
+ dmb sy
2115
+// 0 "" 2
2116
+#NO_APP
2117
+ ldr x0, [x20]
2118
+ mov w25, 65537
2119
+.LBE168:
2120
+ .loc 1 181 0
2121
+ mov w22, 0
2122
+.LVL221:
2123
+.LBB169:
2124
+ .loc 1 192 0
2125
+ str w25, [x0, 256]
2126
+.LBE169:
2127
+ .loc 1 193 0
2128
+ mov x0, 50
2129
+ bl udelay
2130
+.LVL222:
2131
+.L55:
2132
+ .loc 1 194 0
2133
+ cbz w23, .L60
2134
+ .loc 1 196 0
2135
+ cmp w19, 447
2136
+ ble .L56
2137
+ .loc 1 197 0
2138
+ adrp x0, .LC9
2139
+ mov w1, w19
2140
+ add x0, x0, :lo12:.LC9
2141
+.L66:
2142
+ .loc 1 205 0
2143
+ mov w22, -1
2144
+.LVL223:
2145
+ .loc 1 204 0
2146
+ bl printf
2147
+.LVL224:
2148
+.L52:
2149
+ .loc 1 235 0
2150
+ mov w0, w22
2151
+ ldr x25, [sp, 64]
2152
+ ldp x19, x20, [sp, 16]
2153
+.LVL225:
2154
+ ldp x21, x22, [sp, 32]
2155
+ ldp x23, x24, [sp, 48]
2156
+.LVL226:
2157
+ ldp x29, x30, [sp], 80
2158
+ .cfi_remember_state
2159
+ .cfi_restore 30
2160
+ .cfi_restore 29
2161
+ .cfi_restore 25
2162
+ .cfi_restore 23
2163
+ .cfi_restore 24
2164
+ .cfi_restore 21
2165
+ .cfi_restore 22
2166
+ .cfi_restore 19
2167
+ .cfi_restore 20
2168
+ .cfi_def_cfa 31, 0
2169
+ ret
2170
+.LVL227:
2171
+.L53:
2172
+ .cfi_restore_state
2173
+ .loc 1 190 0
2174
+ mov w1, 1
2175
+ b .L65
2176
+.LVL228:
2177
+.L56:
2178
+ .loc 1 201 0
2179
+ sub w0, w19, #192
2180
+ cmp w0, 31
2181
+ ccmp w19, 16, 4, hi
2182
+ beq .L58
2183
+ .loc 1 201 0 is_stmt 0 discriminator 1
2184
+ sub w0, w19, #416
2185
+ cmp w0, 15
2186
+ bls .L58
2187
+ .loc 1 204 0 is_stmt 1
2188
+ adrp x0, .LC10
2189
+ lsl w1, w19, 1
2190
+ add x0, x0, :lo12:.LC10
2191
+ b .L66
2192
+.L58:
2193
+.LBB170:
2194
+ .loc 1 208 0
2195
+ orr w1, w19, -65536
2196
+.LVL229:
2197
+#APP
2198
+// 208 "drivers/misc/rk3528-secure-otp.c" 1
2199
+ dmb sy
2200
+// 0 "" 2
2201
+#NO_APP
2202
+ ldr x0, [x20]
2203
+.LBE170:
2204
+ .loc 1 209 0
2205
+ add w19, w19, 1
2206
+.LVL230:
2207
+.LBB171:
2208
+ .loc 1 208 0
2209
+ str w1, [x0, 260]
2210
+.LBE171:
2211
+.LBB172:
2212
+ .loc 1 210 0
2213
+#APP
2214
+// 210 "drivers/misc/rk3528-secure-otp.c" 1
2215
+ dmb sy
2216
+// 0 "" 2
2217
+#NO_APP
2218
+ ldr x0, [x20]
2219
+.LBE172:
2220
+ .loc 1 212 0
2221
+ mov w1, 4
2222
+.LVL231:
2223
+.LBB173:
2224
+ .loc 1 210 0
2225
+ str w25, [x0, 264]
2226
+.LVL232:
2227
+.LBE173:
2228
+ .loc 1 212 0
2229
+ mov x0, x20
2230
+ bl rockchip_secure_otp_wait_status.isra.2
2231
+.LVL233:
2232
+ mov w22, w0
2233
+.LVL234:
2234
+ .loc 1 213 0
2235
+ tbz w0, #31, .L59
2236
+ .loc 1 214 0
2237
+ adrp x1, .LANCHOR3
2238
+ adrp x0, .LC11
2239
+.LVL235:
2240
+ add x1, x1, :lo12:.LANCHOR3
2241
+ add x0, x0, :lo12:.LC11
2242
+ bl printf
2243
+.LVL236:
2244
+.L60:
2245
+.LBB174:
2246
+ .loc 1 228 0
2247
+#APP
2248
+// 228 "drivers/misc/rk3528-secure-otp.c" 1
2249
+ dmb sy
2250
+// 0 "" 2
2251
+#NO_APP
2252
+ ldr x0, [x20]
2253
+ mov w1, 65536
2254
+.LBE174:
2255
+ .loc 1 230 0
2256
+ ldr x2, [x20, 16]
2257
+ mov w3, w19
2258
+ ldr x4, [x24, 24]
2259
+.LBB175:
2260
+ .loc 1 228 0
2261
+ str w1, [x0, 256]
2262
+.LBE175:
2263
+ .loc 1 230 0
2264
+ ldr x0, [x20, 8]
2265
+ ldr x1, [x20, 24]
2266
+ blr x4
2267
+.LVL237:
2268
+ .loc 1 234 0
2269
+ b .L52
2270
+.LVL238:
2271
+.L59:
2272
+.LBB176:
2273
+ .loc 1 218 0
2274
+ ldr x0, [x20]
2275
+.LVL239:
2276
+ ldrh w0, [x0, 292]
2277
+ and w0, w0, 65535
2278
+.LVL240:
2279
+#APP
2280
+// 218 "drivers/misc/rk3528-secure-otp.c" 1
2281
+ dmb sy
2282
+// 0 "" 2
2283
+.LVL241:
2284
+#NO_APP
2285
+.LBE176:
2286
+ .loc 1 220 0
2287
+ strb w0, [x21]
2288
+ .loc 1 221 0
2289
+ cmp w23, 1
2290
+ beq .L60
2291
+.LVL242:
2292
+ .loc 1 222 0
2293
+ lsr w0, w0, 8
2294
+.LVL243:
2295
+ .loc 1 223 0
2296
+ sub w23, w23, #2
2297
+.LVL244:
2298
+ .loc 1 222 0
2299
+ strb w0, [x21, 1]
2300
+ add x21, x21, 2
2301
+.LVL245:
2302
+ b .L55
2303
+ .cfi_endproc
2304
+.LFE268:
2305
+ .size rk3528_secure_otp_read, .-rk3528_secure_otp_read
2306
+ .section .text.rk3528_secure_otp_write,"ax",@progbits
2307
+ .align 2
2308
+ .type rk3528_secure_otp_write, %function
2309
+rk3528_secure_otp_write:
2310
+.LFB272:
2311
+ .loc 1 621 0
2312
+ .cfi_startproc
2313
+.LVL246:
2314
+ stp x29, x30, [sp, -144]!
2315
+ .cfi_def_cfa_offset 144
2316
+ .cfi_offset 29, -144
2317
+ .cfi_offset 30, -136
2318
+ add x29, sp, 0
2319
+ .cfi_def_cfa_register 29
2320
+ stp x19, x20, [sp, 16]
2321
+ .cfi_offset 19, -128
2322
+ .cfi_offset 20, -120
2323
+ mov w20, w1
2324
+ stp x21, x22, [sp, 32]
2325
+ .cfi_offset 21, -112
2326
+ .cfi_offset 22, -104
2327
+ mov w21, w3
2328
+ stp x23, x24, [sp, 48]
2329
+ .cfi_offset 23, -96
2330
+ .cfi_offset 24, -88
2331
+ mov x24, x0
2332
+ stp x27, x28, [sp, 80]
2333
+ stp x25, x26, [sp, 64]
2334
+ .cfi_offset 27, -64
2335
+ .cfi_offset 28, -56
2336
+ .cfi_offset 25, -80
2337
+ .cfi_offset 26, -72
2338
+ .loc 1 621 0
2339
+ str x2, [x29, 112]
2340
+ .loc 1 622 0
2341
+ bl dev_get_platdata
2342
+.LVL247:
2343
+ mov x28, x0
2344
+.LVL248:
2345
+ .loc 1 625 0
2346
+ sxtw x0, w21
2347
+.LVL249:
2348
+ bl malloc_simple
2349
+.LVL250:
2350
+ .loc 1 628 0
2351
+ cbnz x0, .L68
2352
+.LVL251:
2353
+.L115:
2354
+ .loc 1 643 0
2355
+ mov w27, -1
2356
+.LVL252:
2357
+.L67:
2358
+ .loc 1 669 0
2359
+ mov w0, w27
2360
+ ldp x19, x20, [sp, 16]
2361
+.LVL253:
2362
+ ldp x21, x22, [sp, 32]
2363
+ ldp x23, x24, [sp, 48]
2364
+.LVL254:
2365
+ ldp x25, x26, [sp, 64]
2366
+ ldp x27, x28, [sp, 80]
2367
+.LVL255:
2368
+ ldp x29, x30, [sp], 144
2369
+ .cfi_remember_state
2370
+ .cfi_restore 30
2371
+ .cfi_restore 29
2372
+ .cfi_restore 27
2373
+ .cfi_restore 28
2374
+ .cfi_restore 25
2375
+ .cfi_restore 26
2376
+ .cfi_restore 23
2377
+ .cfi_restore 24
2378
+ .cfi_restore 21
2379
+ .cfi_restore 22
2380
+ .cfi_restore 19
2381
+ .cfi_restore 20
2382
+ .cfi_def_cfa 31, 0
2383
+.LVL256:
2384
+ ret
2385
+.LVL257:
2386
+.L68:
2387
+ .cfi_restore_state
2388
+ mov x19, x0
2389
+ .loc 1 631 0
2390
+ sub w0, w20, #384
2391
+.LVL258:
2392
+ cmp w0, 63
2393
+ bls .L70
2394
+.LVL259:
2395
+.L77:
2396
+ .loc 1 649 0
2397
+ sub w1, w20, #832
2398
+ sub w0, w20, #32
2399
+ cmp w1, 63
2400
+ ccmp w0, 31, 0, hi
2401
+ bls .L71
2402
+ .loc 1 659 0
2403
+ mov w0, 2
2404
+.LBB244:
2405
+.LBB245:
2406
+ .loc 1 607 0
2407
+ adrp x19, .LANCHOR4
2408
+.LVL260:
2409
+ add x19, x19, :lo12:.LANCHOR4
2410
+.LBE245:
2411
+.LBE244:
2412
+ .loc 1 659 0
2413
+ mov x23, 0
2414
+ sdiv w0, w21, w0
2415
+ str w0, [x29, 108]
2416
+.LVL261:
2417
+.L78:
2418
+ .loc 1 659 0 is_stmt 0 discriminator 1
2419
+ ldr w0, [x29, 108]
2420
+ cmp w0, w23
2421
+ ble .L97
2422
+ .loc 1 660 0 is_stmt 1
2423
+ ldr x0, [x29, 112]
2424
+ add w21, w20, w23, lsl 1
2425
+.LBB324:
2426
+.LBB320:
2427
+ .loc 1 477 0
2428
+ asr w25, w21, 1
2429
+.LBE320:
2430
+.LBE324:
2431
+ .loc 1 660 0
2432
+ ldrh w26, [x0, x23, lsl 1]
2433
+.LVL262:
2434
+.LBB325:
2435
+.LBB321:
2436
+ .loc 1 475 0
2437
+ mov x0, x24
2438
+ bl dev_get_driver_data
2439
+.LVL263:
2440
+ str x0, [x29, 120]
2441
+.LVL264:
2442
+ .loc 1 478 0
2443
+ cmp w25, 447
2444
+ bgt .L99
2445
+ .loc 1 482 0
2446
+ sub w0, w25, #192
2447
+.LVL265:
2448
+ cmp w0, 31
2449
+ bls .L85
2450
+ .loc 1 485 0
2451
+ adrp x0, .LC4
2452
+ and w1, w21, -2
2453
+ add x0, x0, :lo12:.LC4
2454
+ bl printf
2455
+.LVL266:
2456
+.L99:
2457
+ .loc 1 478 0
2458
+ mov w27, -1
2459
+ b .L84
2460
+.LVL267:
2461
+.L70:
2462
+.LBE321:
2463
+.LBE325:
2464
+ .loc 1 633 0
2465
+ mov w3, w21
2466
+ mov x2, x19
2467
+ mov w1, w20
2468
+ mov x0, x24
2469
+ bl rk3528_secure_otp_read
2470
+.LVL268:
2471
+ .loc 1 634 0
2472
+ cbnz w0, .L115
2473
+ mov x0, 0
2474
+.LVL269:
2475
+.L75:
2476
+ .loc 1 639 0 discriminator 1
2477
+ cmp w21, w0
2478
+ ble .L77
2479
+ add x0, x0, 1
2480
+.LVL270:
2481
+ .loc 1 640 0
2482
+ add x1, x19, x0
2483
+ ldrb w1, [x1, -1]
2484
+ cbz w1, .L75
2485
+ .loc 1 641 0
2486
+ adrp x0, .LC12
2487
+ add x0, x0, :lo12:.LC12
2488
+ bl printf
2489
+.LVL271:
2490
+ b .L115
2491
+.LVL272:
2492
+.L83:
2493
+.LBB326:
2494
+.LBB327:
2495
+ .loc 1 455 0
2496
+ adds w25, w20, w19
2497
+.LBE327:
2498
+.LBE326:
2499
+ .loc 1 652 0
2500
+ ldr x0, [x29, 112]
2501
+.LBB332:
2502
+.LBB328:
2503
+ .loc 1 455 0
2504
+ and w26, w25, 1
2505
+ mov w3, 2
2506
+ csneg w22, w26, w26, pl
2507
+ add x2, x29, 142
2508
+ sub w22, w25, w22
2509
+.LBE328:
2510
+.LBE332:
2511
+ .loc 1 652 0
2512
+ ldrb w23, [x0, x19]
2513
+.LVL273:
2514
+.LBB333:
2515
+.LBB329:
2516
+ .loc 1 455 0
2517
+ mov w1, w22
2518
+ mov x0, x24
2519
+ bl rk3528_secure_otp_read
2520
+.LVL274:
2521
+ .loc 1 456 0
2522
+ cbnz w0, .L79
2523
+ ldrh w3, [x29, 142]
2524
+ .loc 1 459 0
2525
+ cbnz w26, .L80
2526
+.LVL275:
2527
+ .loc 1 461 0
2528
+ bic w3, w23, w3
2529
+ mov w2, w25
2530
+.LVL276:
2531
+.L112:
2532
+ .loc 1 464 0
2533
+ mov x1, x28
2534
+ mov x0, x24
2535
+.LVL277:
2536
+ add x19, x19, 1
2537
+.LVL278:
2538
+ bl rk3528_secure_otp_write_2_bytes_noecc
2539
+.LVL279:
2540
+ mov w27, w0
2541
+.LVL280:
2542
+.LBE329:
2543
+.LBE333:
2544
+ .loc 1 653 0
2545
+ cbz w0, .L82
2546
+.L98:
2547
+ .loc 1 654 0
2548
+ adrp x0, .LC13
2549
+ add x0, x0, :lo12:.LC13
2550
+.LVL281:
2551
+.L114:
2552
+ .loc 1 662 0
2553
+ bl printf
2554
+.LVL282:
2555
+ .loc 1 663 0
2556
+ b .L67
2557
+.LVL283:
2558
+.L80:
2559
+.LBB334:
2560
+.LBB330:
2561
+ .loc 1 463 0
2562
+ lsl w23, w23, 8
2563
+.LVL284:
2564
+ .loc 1 464 0
2565
+ mov w2, w22
2566
+ bic w3, w23, w3
2567
+ b .L112
2568
+.LVL285:
2569
+.L71:
2570
+.LBE330:
2571
+.LBE334:
2572
+ mov x19, 0
2573
+.LVL286:
2574
+.L82:
2575
+ .loc 1 651 0 discriminator 1
2576
+ cmp w21, w19
2577
+ bgt .L83
2578
+.LVL287:
2579
+.L97:
2580
+ .loc 1 629 0
2581
+ mov w27, 0
2582
+ b .L67
2583
+.LVL288:
2584
+.L85:
2585
+.LBB335:
2586
+.LBB322:
2587
+ .loc 1 489 0
2588
+ cbz w26, .L86
2589
+ .loc 1 492 0
2590
+ ldr x0, [x29, 120]
2591
+ mov w3, w25
2592
+ ldp x2, x1, [x28, 16]
2593
+ ldr x5, [x0, 16]
2594
+ ldr x0, [x28, 8]
2595
+ blr x5
2596
+.LVL289:
2597
+.LBB246:
2598
+ .loc 1 495 0
2599
+#APP
2600
+// 495 "drivers/misc/rk3528-secure-otp.c" 1
2601
+ dmb sy
2602
+// 0 "" 2
2603
+#NO_APP
2604
+ ldr x0, [x28]
2605
+ mov w1, 65536
2606
+ str w1, [x0, 256]
2607
+.LVL290:
2608
+.LBE246:
2609
+.LBB247:
2610
+ .loc 1 496 0
2611
+#APP
2612
+// 496 "drivers/misc/rk3528-secure-otp.c" 1
2613
+ dmb sy
2614
+// 0 "" 2
2615
+#NO_APP
2616
+ ldr x0, [x28]
2617
+ mov w1, 262148
2618
+ str w1, [x0, 32]
2619
+.LVL291:
2620
+.LBE247:
2621
+.LBB248:
2622
+ .loc 1 497 0
2623
+#APP
2624
+// 497 "drivers/misc/rk3528-secure-otp.c" 1
2625
+ dmb sy
2626
+// 0 "" 2
2627
+#NO_APP
2628
+ ldr x0, [x28]
2629
+ mov w1, -65536
2630
+ str w1, [x0, 40]
2631
+.LVL292:
2632
+.LBE248:
2633
+.LBB249:
2634
+ .loc 1 498 0
2635
+#APP
2636
+// 498 "drivers/misc/rk3528-secure-otp.c" 1
2637
+ dmb sy
2638
+// 0 "" 2
2639
+#NO_APP
2640
+ ldr x0, [x28]
2641
+ mov w1, 512
2642
+ movk w1, 0xff00, lsl 16
2643
+ str w1, [x0, 32]
2644
+.LVL293:
2645
+.LBE249:
2646
+.LBB250:
2647
+ .loc 1 499 0
2648
+#APP
2649
+// 499 "drivers/misc/rk3528-secure-otp.c" 1
2650
+ dmb sy
2651
+// 0 "" 2
2652
+#NO_APP
2653
+ ldr x0, [x28]
2654
+ mov w1, -65522
2655
+ str w1, [x0, 36]
2656
+.LVL294:
2657
+.LBE250:
2658
+.LBB251:
2659
+ .loc 1 500 0
2660
+#APP
2661
+// 500 "drivers/misc/rk3528-secure-otp.c" 1
2662
+ dmb sy
2663
+// 0 "" 2
2664
+#NO_APP
2665
+ ldr x0, [x28]
2666
+ mov w3, 240
2667
+ str w3, [x29, 100]
2668
+.LVL295:
2669
+ str w3, [x0, 4096]
2670
+.LBE251:
2671
+.LBB252:
2672
+ .loc 1 501 0
2673
+#APP
2674
+// 501 "drivers/misc/rk3528-secure-otp.c" 1
2675
+ dmb sy
2676
+// 0 "" 2
2677
+#NO_APP
2678
+ ldr x0, [x28]
2679
+ mov w1, 1
2680
+ str w1, [x0, 4100]
2681
+.LVL296:
2682
+.LBE252:
2683
+.LBB253:
2684
+ .loc 1 502 0
2685
+#APP
2686
+// 502 "drivers/misc/rk3528-secure-otp.c" 1
2687
+ dmb sy
2688
+// 0 "" 2
2689
+#NO_APP
2690
+ ldr x0, [x28]
2691
+ mov w2, 122
2692
+ str w2, [x29, 104]
2693
+.LVL297:
2694
+ str w2, [x0, 4104]
2695
+.LBE253:
2696
+.LBB254:
2697
+ .loc 1 503 0
2698
+#APP
2699
+// 503 "drivers/misc/rk3528-secure-otp.c" 1
2700
+ dmb sy
2701
+// 0 "" 2
2702
+#NO_APP
2703
+ ldr x0, [x28]
2704
+ mov w1, 37
2705
+ str w1, [x0, 4108]
2706
+.LVL298:
2707
+.LBE254:
2708
+.LBB255:
2709
+ .loc 1 504 0
2710
+#APP
2711
+// 504 "drivers/misc/rk3528-secure-otp.c" 1
2712
+ dmb sy
2713
+// 0 "" 2
2714
+#NO_APP
2715
+ ldr x0, [x28]
2716
+ str wzr, [x0, 4112]
2717
+.LVL299:
2718
+.LBE255:
2719
+.LBB256:
2720
+ .loc 1 505 0
2721
+#APP
2722
+// 505 "drivers/misc/rk3528-secure-otp.c" 1
2723
+ dmb sy
2724
+// 0 "" 2
2725
+#NO_APP
2726
+ ldr x0, [x28]
2727
+ str wzr, [x0, 4116]
2728
+.LVL300:
2729
+.LBE256:
2730
+.LBB257:
2731
+ .loc 1 506 0
2732
+#APP
2733
+// 506 "drivers/misc/rk3528-secure-otp.c" 1
2734
+ dmb sy
2735
+// 0 "" 2
2736
+#NO_APP
2737
+ ldr x0, [x28]
2738
+ str wzr, [x0, 4120]
2739
+.LVL301:
2740
+.LBE257:
2741
+.LBB258:
2742
+ .loc 1 507 0
2743
+#APP
2744
+// 507 "drivers/misc/rk3528-secure-otp.c" 1
2745
+ dmb sy
2746
+// 0 "" 2
2747
+#NO_APP
2748
+ ldr x0, [x28]
2749
+ mov w1, 31
2750
+ str w1, [x0, 4124]
2751
+.LVL302:
2752
+.LBE258:
2753
+.LBB259:
2754
+ .loc 1 508 0
2755
+#APP
2756
+// 508 "drivers/misc/rk3528-secure-otp.c" 1
2757
+ dmb sy
2758
+// 0 "" 2
2759
+#NO_APP
2760
+ ldr x0, [x28]
2761
+ mov w1, 11
2762
+ str w1, [x0, 4128]
2763
+.LVL303:
2764
+.LBE259:
2765
+.LBB260:
2766
+ .loc 1 509 0
2767
+#APP
2768
+// 509 "drivers/misc/rk3528-secure-otp.c" 1
2769
+ dmb sy
2770
+// 0 "" 2
2771
+#NO_APP
2772
+ ldr x0, [x28]
2773
+ mov w1, 8
2774
+ str w1, [x0, 4132]
2775
+.LVL304:
2776
+.LBE260:
2777
+.LBB261:
2778
+ .loc 1 510 0
2779
+#APP
2780
+// 510 "drivers/misc/rk3528-secure-otp.c" 1
2781
+ dmb sy
2782
+// 0 "" 2
2783
+#NO_APP
2784
+ ldr x0, [x28]
2785
+ str wzr, [x0, 4136]
2786
+.LVL305:
2787
+.LBE261:
2788
+.LBB262:
2789
+ .loc 1 511 0
2790
+#APP
2791
+// 511 "drivers/misc/rk3528-secure-otp.c" 1
2792
+ dmb sy
2793
+// 0 "" 2
2794
+#NO_APP
2795
+ ldr x0, [x28]
2796
+ str wzr, [x0, 4140]
2797
+.LVL306:
2798
+.LBE262:
2799
+.LBB263:
2800
+ .loc 1 512 0
2801
+#APP
2802
+// 512 "drivers/misc/rk3528-secure-otp.c" 1
2803
+ dmb sy
2804
+// 0 "" 2
2805
+#NO_APP
2806
+ ldr x0, [x28]
2807
+ str wzr, [x0, 4144]
2808
+.LVL307:
2809
+.LBE263:
2810
+.LBB264:
2811
+ .loc 1 513 0
2812
+#APP
2813
+// 513 "drivers/misc/rk3528-secure-otp.c" 1
2814
+ dmb sy
2815
+// 0 "" 2
2816
+#NO_APP
2817
+ ldr x0, [x28]
2818
+.LBE264:
2819
+.LBB265:
2820
+ .loc 1 514 0
2821
+ ubfx x21, x21, 9, 8
2822
+.LVL308:
2823
+.LBE265:
2824
+.LBB266:
2825
+ .loc 1 513 0
2826
+ str w25, [x0, 4148]
2827
+.LBE266:
2828
+.LBB267:
2829
+ .loc 1 514 0
2830
+#APP
2831
+// 514 "drivers/misc/rk3528-secure-otp.c" 1
2832
+ dmb sy
2833
+// 0 "" 2
2834
+#NO_APP
2835
+ ldr x0, [x28]
2836
+ str w21, [x0, 4152]
2837
+.LVL309:
2838
+.LBE267:
2839
+.LBB268:
2840
+ .loc 1 515 0
2841
+#APP
2842
+// 515 "drivers/misc/rk3528-secure-otp.c" 1
2843
+ dmb sy
2844
+// 0 "" 2
2845
+#NO_APP
2846
+ ldr x0, [x28]
2847
+ mov w22, 65537
2848
+.LBE268:
2849
+ .loc 1 516 0
2850
+ mov w1, 2
2851
+.LBB269:
2852
+ .loc 1 515 0
2853
+ str w22, [x0, 32]
2854
+.LBE269:
2855
+ .loc 1 516 0
2856
+ mov x0, x28
2857
+ bl rockchip_secure_otp_wait_status.isra.2
2858
+.LVL310:
2859
+ mov w27, w0
2860
+.LVL311:
2861
+ .loc 1 517 0
2862
+ ldp w3, w2, [x29, 100]
2863
+ tbz w0, #31, .L87
2864
+ .loc 1 518 0
2865
+ adrp x0, .LC5
2866
+.LVL312:
2867
+ mov x1, x19
2868
+ add x0, x0, :lo12:.LC5
2869
+.LVL313:
2870
+.L113:
2871
+ .loc 1 607 0
2872
+ bl printf
2873
+.LVL314:
2874
+.L88:
2875
+.LBB270:
2876
+ .loc 1 612 0
2877
+#APP
2878
+// 612 "drivers/misc/rk3528-secure-otp.c" 1
2879
+ dmb sy
2880
+// 0 "" 2
2881
+#NO_APP
2882
+ ldr x0, [x28]
2883
+ mov w1, -65533
2884
+.LBE270:
2885
+ .loc 1 613 0
2886
+ ldr x2, [x28, 16]
2887
+ mov w3, w25
2888
+.LBB271:
2889
+ .loc 1 612 0
2890
+ str w1, [x0, 772]
2891
+.LBE271:
2892
+ .loc 1 613 0
2893
+ ldr x0, [x29, 120]
2894
+ ldr x1, [x28, 24]
2895
+ ldr x6, [x0, 24]
2896
+ ldr x0, [x28, 8]
2897
+ blr x6
2898
+.LVL315:
2899
+.LBE322:
2900
+.LBE335:
2901
+ .loc 1 661 0
2902
+ cbz w27, .L86
2903
+.LVL316:
2904
+.L84:
2905
+ .loc 1 662 0
2906
+ adrp x0, .LC20
2907
+ add x0, x0, :lo12:.LC20
2908
+ b .L114
2909
+.LVL317:
2910
+.L87:
2911
+.LBB336:
2912
+.LBB323:
2913
+.LBB272:
2914
+ .loc 1 522 0
2915
+#APP
2916
+// 522 "drivers/misc/rk3528-secure-otp.c" 1
2917
+ dmb sy
2918
+// 0 "" 2
2919
+#NO_APP
2920
+ ldr x0, [x28]
2921
+.LVL318:
2922
+ mov w1, 14848
2923
+ movk w1, 0xff00, lsl 16
2924
+ str w1, [x0, 32]
2925
+.LVL319:
2926
+.LBE272:
2927
+.LBB273:
2928
+ .loc 1 523 0
2929
+#APP
2930
+// 523 "drivers/misc/rk3528-secure-otp.c" 1
2931
+ dmb sy
2932
+// 0 "" 2
2933
+#NO_APP
2934
+ ldr x0, [x28]
2935
+ str w3, [x0, 4096]
2936
+.LVL320:
2937
+.LBE273:
2938
+.LBB274:
2939
+ .loc 1 524 0
2940
+#APP
2941
+// 524 "drivers/misc/rk3528-secure-otp.c" 1
2942
+ dmb sy
2943
+// 0 "" 2
2944
+#NO_APP
2945
+ ldr x0, [x28]
2946
+ mov w1, 1
2947
+ str w1, [x0, 4100]
2948
+.LVL321:
2949
+.LBE274:
2950
+.LBB275:
2951
+ .loc 1 525 0
2952
+#APP
2953
+// 525 "drivers/misc/rk3528-secure-otp.c" 1
2954
+ dmb sy
2955
+// 0 "" 2
2956
+#NO_APP
2957
+ ldr x0, [x28]
2958
+ str w2, [x0, 4104]
2959
+.LVL322:
2960
+.LBE275:
2961
+.LBB276:
2962
+ .loc 1 526 0
2963
+#APP
2964
+// 526 "drivers/misc/rk3528-secure-otp.c" 1
2965
+ dmb sy
2966
+// 0 "" 2
2967
+#NO_APP
2968
+ ldr x0, [x28]
2969
+ mov w1, 21
2970
+ str w1, [x0, 4108]
2971
+.LVL323:
2972
+.LBE276:
2973
+.LBB277:
2974
+ .loc 1 527 0
2975
+#APP
2976
+// 527 "drivers/misc/rk3528-secure-otp.c" 1
2977
+ dmb sy
2978
+// 0 "" 2
2979
+#NO_APP
2980
+ ldr x0, [x28]
2981
+ mov w1, 220
2982
+ str w1, [x0, 4112]
2983
+.LVL324:
2984
+.LBE277:
2985
+.LBB278:
2986
+ .loc 1 528 0
2987
+#APP
2988
+// 528 "drivers/misc/rk3528-secure-otp.c" 1
2989
+ dmb sy
2990
+// 0 "" 2
2991
+#NO_APP
2992
+ ldr x0, [x28]
2993
+ mov w1, 146
2994
+ str w1, [x0, 4116]
2995
+.LVL325:
2996
+.LBE278:
2997
+.LBB279:
2998
+ .loc 1 529 0
2999
+#APP
3000
+// 529 "drivers/misc/rk3528-secure-otp.c" 1
3001
+ dmb sy
3002
+// 0 "" 2
3003
+#NO_APP
3004
+ ldr x0, [x28]
3005
+ mov w1, 121
3006
+ str w1, [x0, 4120]
3007
+.LVL326:
3008
+.LBE279:
3009
+.LBB280:
3010
+ .loc 1 530 0
3011
+#APP
3012
+// 530 "drivers/misc/rk3528-secure-otp.c" 1
3013
+ dmb sy
3014
+// 0 "" 2
3015
+#NO_APP
3016
+ ldr x0, [x28]
3017
+ mov w1, 129
3018
+ str w1, [x0, 4124]
3019
+.LVL327:
3020
+.LBE280:
3021
+.LBB281:
3022
+ .loc 1 531 0
3023
+#APP
3024
+// 531 "drivers/misc/rk3528-secure-otp.c" 1
3025
+ dmb sy
3026
+// 0 "" 2
3027
+#NO_APP
3028
+ ldr x0, [x28]
3029
+ mov w1, 126
3030
+ str w1, [x0, 4128]
3031
+.LVL328:
3032
+.LBE281:
3033
+.LBB282:
3034
+ .loc 1 532 0
3035
+#APP
3036
+// 532 "drivers/misc/rk3528-secure-otp.c" 1
3037
+ dmb sy
3038
+// 0 "" 2
3039
+#NO_APP
3040
+ ldr x0, [x28]
3041
+ mov w1, 33
3042
+ str w1, [x0, 4132]
3043
+.LVL329:
3044
+.LBE282:
3045
+.LBB283:
3046
+ .loc 1 533 0
3047
+#APP
3048
+// 533 "drivers/misc/rk3528-secure-otp.c" 1
3049
+ dmb sy
3050
+// 0 "" 2
3051
+#NO_APP
3052
+ ldr x0, [x28]
3053
+ mov w1, 17
3054
+ str w1, [x0, 4136]
3055
+.LVL330:
3056
+.LBE283:
3057
+.LBB284:
3058
+ .loc 1 534 0
3059
+#APP
3060
+// 534 "drivers/misc/rk3528-secure-otp.c" 1
3061
+ dmb sy
3062
+// 0 "" 2
3063
+#NO_APP
3064
+ ldr x0, [x28]
3065
+ mov w1, 157
3066
+ str w1, [x0, 4140]
3067
+.LVL331:
3068
+.LBE284:
3069
+.LBB285:
3070
+ .loc 1 535 0
3071
+#APP
3072
+// 535 "drivers/misc/rk3528-secure-otp.c" 1
3073
+ dmb sy
3074
+// 0 "" 2
3075
+#NO_APP
3076
+ ldr x0, [x28]
3077
+ mov w21, 2
3078
+.LVL332:
3079
+ str w21, [x0, 4144]
3080
+.LVL333:
3081
+.LBE285:
3082
+.LBB286:
3083
+ .loc 1 536 0
3084
+#APP
3085
+// 536 "drivers/misc/rk3528-secure-otp.c" 1
3086
+ dmb sy
3087
+// 0 "" 2
3088
+#NO_APP
3089
+ ldr x0, [x28]
3090
+ str wzr, [x0, 4148]
3091
+.LVL334:
3092
+.LBE286:
3093
+.LBB287:
3094
+ .loc 1 537 0
3095
+#APP
3096
+// 537 "drivers/misc/rk3528-secure-otp.c" 1
3097
+ dmb sy
3098
+// 0 "" 2
3099
+#NO_APP
3100
+ ldr x0, [x28]
3101
+ str wzr, [x0, 4152]
3102
+.LVL335:
3103
+.LBE287:
3104
+.LBB288:
3105
+ .loc 1 538 0
3106
+#APP
3107
+// 538 "drivers/misc/rk3528-secure-otp.c" 1
3108
+ dmb sy
3109
+// 0 "" 2
3110
+#NO_APP
3111
+ ldr x0, [x28]
3112
+.LBE288:
3113
+ .loc 1 539 0
3114
+ mov w1, w21
3115
+.LBB289:
3116
+ .loc 1 538 0
3117
+ str w22, [x0, 32]
3118
+.LBE289:
3119
+ .loc 1 539 0
3120
+ mov x0, x28
3121
+ bl rockchip_secure_otp_wait_status.isra.2
3122
+.LVL336:
3123
+ mov w27, w0
3124
+.LVL337:
3125
+ .loc 1 540 0
3126
+ tbz w0, #31, .L89
3127
+ .loc 1 541 0
3128
+ adrp x0, .LC14
3129
+.LVL338:
3130
+ mov x1, x19
3131
+ add x0, x0, :lo12:.LC14
3132
+ b .L113
3133
+.LVL339:
3134
+.L89:
3135
+.LBB290:
3136
+ .loc 1 545 0
3137
+#APP
3138
+// 545 "drivers/misc/rk3528-secure-otp.c" 1
3139
+ dmb sy
3140
+// 0 "" 2
3141
+#NO_APP
3142
+ ldr x0, [x28]
3143
+.LVL340:
3144
+ mov w1, 512
3145
+ movk w1, 0xff00, lsl 16
3146
+ str w1, [x0, 32]
3147
+.LVL341:
3148
+.LBE290:
3149
+.LBB291:
3150
+ .loc 1 546 0
3151
+#APP
3152
+// 546 "drivers/misc/rk3528-secure-otp.c" 1
3153
+ dmb sy
3154
+// 0 "" 2
3155
+#NO_APP
3156
+ ldr x0, [x28]
3157
+ mov w1, -65535
3158
+ str w1, [x0, 36]
3159
+.LVL342:
3160
+.LBE291:
3161
+.LBB292:
3162
+ .loc 1 547 0
3163
+#APP
3164
+// 547 "drivers/misc/rk3528-secure-otp.c" 1
3165
+ dmb sy
3166
+// 0 "" 2
3167
+#NO_APP
3168
+ ldr x0, [x28]
3169
+ mov w1, 251
3170
+ str w1, [x0, 4096]
3171
+.LVL343:
3172
+.LBE292:
3173
+.LBB293:
3174
+ .loc 1 548 0
3175
+#APP
3176
+// 548 "drivers/misc/rk3528-secure-otp.c" 1
3177
+ dmb sy
3178
+// 0 "" 2
3179
+#NO_APP
3180
+ ldr x0, [x28]
3181
+ str wzr, [x0, 4100]
3182
+.LVL344:
3183
+.LBE293:
3184
+.LBB294:
3185
+ .loc 1 549 0
3186
+#APP
3187
+// 549 "drivers/misc/rk3528-secure-otp.c" 1
3188
+ dmb sy
3189
+// 0 "" 2
3190
+#NO_APP
3191
+ ldr x0, [x28]
3192
+.LBE294:
3193
+ .loc 1 550 0
3194
+ mov w1, w21
3195
+.LBB295:
3196
+ .loc 1 549 0
3197
+ str w22, [x0, 32]
3198
+.LBE295:
3199
+ .loc 1 550 0
3200
+ mov x0, x28
3201
+ bl rockchip_secure_otp_wait_status.isra.2
3202
+.LVL345:
3203
+ mov w27, w0
3204
+.LVL346:
3205
+ .loc 1 551 0
3206
+ tbz w0, #31, .L90
3207
+ .loc 1 552 0
3208
+ adrp x0, .LC15
3209
+.LVL347:
3210
+ mov x1, x19
3211
+ add x0, x0, :lo12:.LC15
3212
+ b .L113
3213
+.LVL348:
3214
+.L90:
3215
+.LBB296:
3216
+ .loc 1 556 0
3217
+#APP
3218
+// 556 "drivers/misc/rk3528-secure-otp.c" 1
3219
+ dmb sy
3220
+// 0 "" 2
3221
+#NO_APP
3222
+ ldr x0, [x28]
3223
+.LVL349:
3224
+ mov w1, -65534
3225
+ str w1, [x0, 36]
3226
+.LVL350:
3227
+.LBE296:
3228
+.LBB297:
3229
+ .loc 1 557 0
3230
+#APP
3231
+// 557 "drivers/misc/rk3528-secure-otp.c" 1
3232
+ dmb sy
3233
+// 0 "" 2
3234
+#NO_APP
3235
+ ldr x0, [x28]
3236
+ mov w1, 192
3237
+ str w1, [x0, 4096]
3238
+.LBE297:
3239
+.LBB298:
3240
+ .loc 1 558 0
3241
+ and w1, w26, 255
3242
+.LVL351:
3243
+#APP
3244
+// 558 "drivers/misc/rk3528-secure-otp.c" 1
3245
+ dmb sy
3246
+// 0 "" 2
3247
+#NO_APP
3248
+ ldr x0, [x28]
3249
+.LBE298:
3250
+.LBB299:
3251
+ .loc 1 559 0
3252
+ lsr w26, w26, 8
3253
+.LVL352:
3254
+.LBE299:
3255
+.LBB300:
3256
+ .loc 1 558 0
3257
+ str w1, [x0, 4100]
3258
+.LBE300:
3259
+.LBB301:
3260
+ .loc 1 559 0
3261
+#APP
3262
+// 559 "drivers/misc/rk3528-secure-otp.c" 1
3263
+ dmb sy
3264
+// 0 "" 2
3265
+#NO_APP
3266
+ ldr x0, [x28]
3267
+ str w26, [x0, 4104]
3268
+.LVL353:
3269
+.LBE301:
3270
+.LBB302:
3271
+ .loc 1 560 0
3272
+#APP
3273
+// 560 "drivers/misc/rk3528-secure-otp.c" 1
3274
+ dmb sy
3275
+// 0 "" 2
3276
+#NO_APP
3277
+ ldr x0, [x28]
3278
+.LBE302:
3279
+ .loc 1 561 0
3280
+ mov w1, w21
3281
+.LVL354:
3282
+.LBB303:
3283
+ .loc 1 560 0
3284
+ str w22, [x0, 32]
3285
+.LBE303:
3286
+ .loc 1 561 0
3287
+ mov x0, x28
3288
+ bl rockchip_secure_otp_wait_status.isra.2
3289
+.LVL355:
3290
+ mov w27, w0
3291
+.LVL356:
3292
+ .loc 1 562 0
3293
+ tbz w0, #31, .L91
3294
+ .loc 1 563 0
3295
+ adrp x0, .LC16
3296
+.LVL357:
3297
+ mov x1, x19
3298
+ add x0, x0, :lo12:.LC16
3299
+ b .L113
3300
+.LVL358:
3301
+.L91:
3302
+.LBB304:
3303
+ .loc 1 567 0
3304
+#APP
3305
+// 567 "drivers/misc/rk3528-secure-otp.c" 1
3306
+ dmb sy
3307
+// 0 "" 2
3308
+#NO_APP
3309
+ ldr x0, [x28]
3310
+.LVL359:
3311
+ mov w1, 14848
3312
+ movk w1, 0xff00, lsl 16
3313
+ str w1, [x0, 32]
3314
+.LVL360:
3315
+.LBE304:
3316
+.LBB305:
3317
+ .loc 1 568 0
3318
+#APP
3319
+// 568 "drivers/misc/rk3528-secure-otp.c" 1
3320
+ dmb sy
3321
+// 0 "" 2
3322
+#NO_APP
3323
+ ldr x0, [x28]
3324
+ mov w1, -65535
3325
+ str w1, [x0, 36]
3326
+.LVL361:
3327
+.LBE305:
3328
+.LBB306:
3329
+ .loc 1 569 0
3330
+#APP
3331
+// 569 "drivers/misc/rk3528-secure-otp.c" 1
3332
+ dmb sy
3333
+// 0 "" 2
3334
+#NO_APP
3335
+ ldr x0, [x28]
3336
+ mov w1, 255
3337
+ str w1, [x0, 4096]
3338
+.LVL362:
3339
+.LBE306:
3340
+.LBB307:
3341
+ .loc 1 570 0
3342
+#APP
3343
+// 570 "drivers/misc/rk3528-secure-otp.c" 1
3344
+ dmb sy
3345
+// 0 "" 2
3346
+#NO_APP
3347
+ ldr x0, [x28]
3348
+ mov w1, 10
3349
+ str w1, [x0, 4100]
3350
+.LVL363:
3351
+.LBE307:
3352
+.LBB308:
3353
+ .loc 1 571 0
3354
+#APP
3355
+// 571 "drivers/misc/rk3528-secure-otp.c" 1
3356
+ dmb sy
3357
+// 0 "" 2
3358
+#NO_APP
3359
+ ldr x0, [x28]
3360
+.LBE308:
3361
+ .loc 1 572 0
3362
+ mov w1, w21
3363
+.LBB309:
3364
+ .loc 1 571 0
3365
+ str w22, [x0, 32]
3366
+.LBE309:
3367
+ .loc 1 572 0
3368
+ mov x0, x28
3369
+ bl rockchip_secure_otp_wait_status.isra.2
3370
+.LVL364:
3371
+ mov w27, w0
3372
+.LVL365:
3373
+ .loc 1 573 0
3374
+ tbz w0, #31, .L92
3375
+ .loc 1 574 0
3376
+ adrp x0, .LC17
3377
+.LVL366:
3378
+ mov x1, x19
3379
+ add x0, x0, :lo12:.LC17
3380
+ b .L113
3381
+.LVL367:
3382
+.L92:
3383
+.LBB310:
3384
+ .loc 1 578 0
3385
+#APP
3386
+// 578 "drivers/misc/rk3528-secure-otp.c" 1
3387
+ dmb sy
3388
+// 0 "" 2
3389
+#NO_APP
3390
+ ldr x0, [x28]
3391
+.LVL368:
3392
+ mov w1, -65534
3393
+ str w1, [x0, 36]
3394
+.LVL369:
3395
+.LBE310:
3396
+.LBB311:
3397
+ .loc 1 579 0
3398
+#APP
3399
+// 579 "drivers/misc/rk3528-secure-otp.c" 1
3400
+ dmb sy
3401
+// 0 "" 2
3402
+#NO_APP
3403
+ ldr x0, [x28]
3404
+ mov w1, 1
3405
+ str w1, [x0, 4096]
3406
+.LVL370:
3407
+.LBE311:
3408
+.LBB312:
3409
+ .loc 1 580 0
3410
+#APP
3411
+// 580 "drivers/misc/rk3528-secure-otp.c" 1
3412
+ dmb sy
3413
+// 0 "" 2
3414
+#NO_APP
3415
+ ldr x0, [x28]
3416
+ mov w1, 191
3417
+ str w1, [x0, 4100]
3418
+.LVL371:
3419
+.LBE312:
3420
+.LBB313:
3421
+ .loc 1 581 0
3422
+#APP
3423
+// 581 "drivers/misc/rk3528-secure-otp.c" 1
3424
+ dmb sy
3425
+// 0 "" 2
3426
+#NO_APP
3427
+ ldr x0, [x28]
3428
+ str wzr, [x0, 4104]
3429
+.LVL372:
3430
+.LBE313:
3431
+.LBB314:
3432
+ .loc 1 582 0
3433
+#APP
3434
+// 582 "drivers/misc/rk3528-secure-otp.c" 1
3435
+ dmb sy
3436
+// 0 "" 2
3437
+#NO_APP
3438
+ ldr x0, [x28]
3439
+.LBE314:
3440
+ .loc 1 583 0
3441
+ mov w1, w21
3442
+.LBB315:
3443
+ .loc 1 582 0
3444
+ str w22, [x0, 32]
3445
+.LBE315:
3446
+ .loc 1 583 0
3447
+ mov x0, x28
3448
+ bl rockchip_secure_otp_wait_status.isra.2
3449
+.LVL373:
3450
+ mov w27, w0
3451
+.LVL374:
3452
+ .loc 1 584 0
3453
+ tbz w0, #31, .L93
3454
+ .loc 1 585 0
3455
+ adrp x0, .LC18
3456
+.LVL375:
3457
+ mov x1, x19
3458
+ add x0, x0, :lo12:.LC18
3459
+ b .L113
3460
+.LVL376:
3461
+.L93:
3462
+ .loc 1 589 0
3463
+ mov x0, x28
3464
+.LVL377:
3465
+ bl rockchip_secure_otp_check_flag.isra.0
3466
+.LVL378:
3467
+ mov w27, w0
3468
+.LVL379:
3469
+ .loc 1 590 0
3470
+ tbz w0, #31, .L94
3471
+ .loc 1 591 0
3472
+ adrp x0, .LC6
3473
+.LVL380:
3474
+ mov x1, x19
3475
+ add x0, x0, :lo12:.LC6
3476
+ b .L113
3477
+.LVL381:
3478
+.L94:
3479
+.LBB316:
3480
+ .loc 1 595 0
3481
+#APP
3482
+// 595 "drivers/misc/rk3528-secure-otp.c" 1
3483
+ dmb sy
3484
+// 0 "" 2
3485
+#NO_APP
3486
+ ldr x0, [x28]
3487
+.LVL382:
3488
+ mov w1, -65535
3489
+ str w1, [x0, 36]
3490
+.LVL383:
3491
+.LBE316:
3492
+.LBB317:
3493
+ .loc 1 596 0
3494
+#APP
3495
+// 596 "drivers/misc/rk3528-secure-otp.c" 1
3496
+ dmb sy
3497
+// 0 "" 2
3498
+#NO_APP
3499
+ ldr x0, [x28]
3500
+ mov w1, 2
3501
+ str w1, [x0, 4096]
3502
+.LVL384:
3503
+.LBE317:
3504
+.LBB318:
3505
+ .loc 1 597 0
3506
+#APP
3507
+// 597 "drivers/misc/rk3528-secure-otp.c" 1
3508
+ dmb sy
3509
+// 0 "" 2
3510
+#NO_APP
3511
+ ldr x0, [x28]
3512
+ mov w2, 191
3513
+ str w2, [x0, 4100]
3514
+.LVL385:
3515
+.LBE318:
3516
+.LBB319:
3517
+ .loc 1 598 0
3518
+#APP
3519
+// 598 "drivers/misc/rk3528-secure-otp.c" 1
3520
+ dmb sy
3521
+// 0 "" 2
3522
+#NO_APP
3523
+ ldr x0, [x28]
3524
+ mov w2, 65537
3525
+ str w2, [x0, 32]
3526
+.LBE319:
3527
+ .loc 1 599 0
3528
+ mov x0, x28
3529
+ bl rockchip_secure_otp_wait_status.isra.2
3530
+.LVL386:
3531
+ mov w27, w0
3532
+.LVL387:
3533
+ .loc 1 600 0
3534
+ tbz w0, #31, .L95
3535
+ .loc 1 601 0
3536
+ adrp x0, .LC19
3537
+.LVL388:
3538
+ mov x1, x19
3539
+ add x0, x0, :lo12:.LC19
3540
+ b .L113
3541
+.LVL389:
3542
+.L95:
3543
+ .loc 1 605 0
3544
+ mov x0, x28
3545
+.LVL390:
3546
+ bl rockchip_secure_otp_wait_flag.isra.1
3547
+.LVL391:
3548
+ mov w27, w0
3549
+.LVL392:
3550
+ .loc 1 606 0
3551
+ tbz w0, #31, .L88
3552
+ .loc 1 607 0
3553
+ adrp x0, .LC7
3554
+.LVL393:
3555
+ mov x1, x19
3556
+ add x0, x0, :lo12:.LC7
3557
+ b .L113
3558
+.LVL394:
3559
+.L86:
3560
+ add x23, x23, 1
3561
+.LVL395:
3562
+ b .L78
3563
+.LVL396:
3564
+.L79:
3565
+.LBE323:
3566
+.LBE336:
3567
+.LBB337:
3568
+.LBB331:
3569
+ .loc 1 457 0
3570
+ mov w27, -1
3571
+ b .L98
3572
+.LBE331:
3573
+.LBE337:
3574
+ .cfi_endproc
3575
+.LFE272:
3576
+ .size rk3528_secure_otp_write, .-rk3528_secure_otp_write
3577
+ .global _u_boot_list_2_driver_2_rockchip_secure_otp
3578
+ .section .rodata.__func__.7575,"a",@progbits
3579
+ .align 3
3580
+ .set .LANCHOR0,. + 0
3581
+ .type __func__.7575, %object
3582
+ .size __func__.7575, 32
3583
+__func__.7575:
3584
+ .string "rockchip_secure_otp_wait_status"
3585
+ .section .rodata.__func__.7618,"a",@progbits
3586
+ .align 3
3587
+ .set .LANCHOR2,. + 0
3588
+ .type __func__.7618, %object
3589
+ .size __func__.7618, 31
3590
+__func__.7618:
3591
+ .string "rockchip_secure_otp_ecc_enable"
3592
+ .section .rodata.__func__.7636,"a",@progbits
3593
+ .align 3
3594
+ .set .LANCHOR3,. + 0
3595
+ .type __func__.7636, %object
3596
+ .size __func__.7636, 23
3597
+__func__.7636:
3598
+ .string "rk3528_secure_otp_read"
3599
+ .section .rodata.__func__.7671,"a",@progbits
3600
+ .align 3
3601
+ .set .LANCHOR1,. + 0
3602
+ .type __func__.7671, %object
3603
+ .size __func__.7671, 38
3604
+__func__.7671:
3605
+ .string "rk3528_secure_otp_write_2_bytes_noecc"
3606
+ .section .rodata.__func__.7892,"a",@progbits
3607
+ .align 3
3608
+ .set .LANCHOR4,. + 0
3609
+ .type __func__.7892, %object
3610
+ .size __func__.7892, 32
3611
+__func__.7892:
3612
+ .string "rk3528_secure_otp_write_2_bytes"
3613
+ .section .rodata.rk3528_data,"a",@progbits
3614
+ .align 3
3615
+ .type rk3528_data, %object
3616
+ .size rk3528_data, 32
3617
+rk3528_data:
3618
+ .xword rk3528_secure_otp_read
3619
+ .xword rk3528_secure_otp_write
3620
+ .xword rk3528_spl_rockchip_otp_start
3621
+ .xword rk3528_spl_rockchip_otp_stop
3622
+ .section .rodata.rk3528_secure_otp_read.str1.1,"aMS",@progbits,1
3623
+.LC9:
3624
+ .string "do not access non secure area, half word offset = %d\n"
3625
+.LC10:
3626
+ .string "Please input correct addr, offset(bytes) is 0x%x\n"
3627
+.LC11:
3628
+ .string "%s timeout during read setup\n"
3629
+ .section .rodata.rk3528_secure_otp_write.str1.1,"aMS",@progbits,1
3630
+.LC12:
3631
+ .string "The zone is written.\n"
3632
+.LC13:
3633
+ .string "rk3528_secure_otp_write_byte_noecc error\n"
3634
+.LC14:
3635
+ .string "%s timeout during write setup 2\n"
3636
+.LC15:
3637
+ .string "%s timeout during write setup 3\n"
3638
+.LC16:
3639
+ .string "%s timeout during write setup 4\n"
3640
+.LC17:
3641
+ .string "%s timeout during write setup 5\n"
3642
+.LC18:
3643
+ .string "%s timeout during write setup 6\n"
3644
+.LC19:
3645
+ .string "%s timeout during write setup 8\n"
3646
+.LC20:
3647
+ .string "rk3528_secure_otp_write_2_bytes error\n"
3648
+ .section .rodata.rk3528_secure_otp_write_2_bytes_noecc.str1.1,"aMS",@progbits,1
3649
+.LC4:
3650
+ .string "Please input correct addr, offset is 0x%x\n"
3651
+.LC5:
3652
+ .string "%s timeout during write setup 1\n"
3653
+.LC6:
3654
+ .string "%s timeout during write setup 7\n"
3655
+.LC7:
3656
+ .string "%s timeout during write setup 9\n"
3657
+ .section .rodata.rockchip_otp_ids,"a",@progbits
3658
+ .align 3
3659
+ .type rockchip_otp_ids, %object
3660
+ .size rockchip_otp_ids, 32
3661
+rockchip_otp_ids:
3662
+ .xword .LC22
3663
+ .xword rk3528_data
3664
+ .zero 16
3665
+ .section .rodata.rockchip_secure_otp_ecc_enable.str1.1,"aMS",@progbits,1
3666
+.LC8:
3667
+ .string "%s timeout during ecc_enable\n"
3668
+ .section .rodata.rockchip_secure_otp_ofdata_to_platdata.str1.1,"aMS",@progbits,1
3669
+.LC0:
3670
+ .string "secure_conf"
3671
+.LC1:
3672
+ .string "mask_addr"
3673
+.LC2:
3674
+ .string "cru_rst_addr"
3675
+ .section .rodata.rockchip_secure_otp_ops,"a",@progbits
3676
+ .align 3
3677
+ .type rockchip_secure_otp_ops, %object
3678
+ .size rockchip_secure_otp_ops, 32
3679
+rockchip_secure_otp_ops:
3680
+ .xword secure_otp_read
3681
+ .xword secure_otp_write
3682
+ .xword secure_otp_ioctl
3683
+ .zero 8
3684
+ .section .rodata.rockchip_secure_otp_wait_status.isra.2.str1.1,"aMS",@progbits,1
3685
+.LC3:
3686
+ .string "%s: wait init status timeout\n"
3687
+ .section .rodata.str1.1,"aMS",@progbits,1
3688
+.LC21:
3689
+ .string "rockchip_secure_otp"
3690
+.LC22:
3691
+ .string "rockchip,rk3528-secure-otp"
3692
+ .section .u_boot_list_2_driver_2_rockchip_secure_otp,"aw",@progbits
3693
+ .align 2
3694
+ .type _u_boot_list_2_driver_2_rockchip_secure_otp, %object
3695
+ .size _u_boot_list_2_driver_2_rockchip_secure_otp, 120
3696
+_u_boot_list_2_driver_2_rockchip_secure_otp:
3697
+ .8byte .LC21
3698
+ .word 36
3699
+ .zero 4
3700
+ .8byte rockchip_otp_ids
3701
+ .zero 32
3702
+ .8byte rockchip_secure_otp_ofdata_to_platdata
3703
+ .zero 28
3704
+ .word 32
3705
+ .zero 8
3706
+ .8byte rockchip_secure_otp_ops
3707
+ .zero 8
3708
+ .text
3709
+.Letext0:
3710
+ .file 2 "include/common.h"
3711
+ .file 3 "./arch/arm/include/asm/types.h"
3712
+ .file 4 "include/linux/types.h"
3713
+ .file 5 "include/errno.h"
3714
+ .file 6 "include/linux/string.h"
3715
+ .file 7 "include/efi.h"
3716
+ .file 8 "include/dm/device.h"
3717
+ .file 9 "include/ide.h"
3718
+ .file 10 "include/linux/list.h"
3719
+ .file 11 "include/part.h"
3720
+ .file 12 "include/flash.h"
3721
+ .file 13 "include/lmb.h"
3722
+ .file 14 "include/asm-generic/u-boot.h"
3723
+ .file 15 "./arch/arm/include/asm/u-boot-arm.h"
3724
+ .file 16 "include/linux/libfdt_env.h"
3725
+ .file 17 "include/linux/../../scripts/dtc/libfdt/fdt.h"
3726
+ .file 18 "include/linux/libfdt.h"
3727
+ .file 19 "include/image.h"
3728
+ .file 20 "./arch/arm/include/asm/global_data.h"
3729
+ .file 21 "include/asm-generic/global_data.h"
3730
+ .file 22 "include/dm/of.h"
3731
+ .file 23 "include/net.h"
3732
+ .file 24 "include/dm/uclass-id.h"
3733
+ .file 25 "include/dm/ofnode.h"
3734
+ .file 26 "include/malloc.h"
3735
+ .file 27 "include/linux/compat.h"
3736
+ .file 28 "include/dm/uclass.h"
3737
+ .file 29 "include/asm-generic/ioctl.h"
3738
+ .file 30 "include/misc.h"
3739
+ .file 31 "include/rockchip-otp.h"
3740
+ .file 32 "include/dm/read.h"
3741
+ .file 33 "include/stdio.h"
3742
+ .file 34 "include/linux/delay.h"
3743
+ .file 35 "include/log.h"
3744
+ .section .debug_info,"",@progbits
3745
+.Ldebug_info0:
3746
+ .4byte 0x42d0
3747
+ .2byte 0x4
3748
+ .4byte .Ldebug_abbrev0
3749
+ .byte 0x8
3750
+ .uleb128 0x1
3751
+ .4byte .LASF458
3752
+ .byte 0xc
3753
+ .4byte .LASF459
3754
+ .4byte .LASF460
3755
+ .4byte .Ldebug_ranges0+0x6c0
3756
+ .8byte 0
3757
+ .4byte .Ldebug_line0
3758
+ .uleb128 0x2
3759
+ .4byte .LASF4
3760
+ .byte 0x2
3761
+ .byte 0xd
3762
+ .4byte 0x34
3763
+ .uleb128 0x3
3764
+ .byte 0x1
3765
+ .byte 0x8
3766
+ .4byte .LASF0
3767
+ .uleb128 0x3
3768
+ .byte 0x8
3769
+ .byte 0x7
3770
+ .4byte .LASF1
3771
+ .uleb128 0x3
3772
+ .byte 0x2
3773
+ .byte 0x7
3774
+ .4byte .LASF2
3775
+ .uleb128 0x4
3776
+ .4byte .LASF21
3777
+ .byte 0x5
3778
+ .byte 0xc
3779
+ .4byte 0x54
3780
+ .uleb128 0x5
3781
+ .byte 0x4
3782
+ .byte 0x5
3783
+ .string "int"
3784
+ .uleb128 0x3
3785
+ .byte 0x1
3786
+ .byte 0x6
3787
+ .4byte .LASF3
3788
+ .uleb128 0x2
3789
+ .4byte .LASF5
3790
+ .byte 0x3
3791
+ .byte 0xc
3792
+ .4byte 0x34
3793
+ .uleb128 0x3
3794
+ .byte 0x2
3795
+ .byte 0x5
3796
+ .4byte .LASF6
3797
+ .uleb128 0x2
3798
+ .4byte .LASF7
3799
+ .byte 0x3
3800
+ .byte 0x12
3801
+ .4byte 0x7f
3802
+ .uleb128 0x3
3803
+ .byte 0x4
3804
+ .byte 0x7
3805
+ .4byte .LASF8
3806
+ .uleb128 0x3
3807
+ .byte 0x8
3808
+ .byte 0x5
3809
+ .4byte .LASF9
3810
+ .uleb128 0x3
3811
+ .byte 0x8
3812
+ .byte 0x7
3813
+ .4byte .LASF10
3814
+ .uleb128 0x6
3815
+ .string "u8"
3816
+ .byte 0x3
3817
+ .byte 0x1f
3818
+ .4byte 0x34
3819
+ .uleb128 0x7
3820
+ .4byte 0x94
3821
+ .uleb128 0x6
3822
+ .string "u16"
3823
+ .byte 0x3
3824
+ .byte 0x22
3825
+ .4byte 0x42
3826
+ .uleb128 0x6
3827
+ .string "u32"
3828
+ .byte 0x3
3829
+ .byte 0x25
3830
+ .4byte 0x7f
3831
+ .uleb128 0x6
3832
+ .string "u64"
3833
+ .byte 0x3
3834
+ .byte 0x28
3835
+ .4byte 0x8d
3836
+ .uleb128 0x2
3837
+ .4byte .LASF11
3838
+ .byte 0x3
3839
+ .byte 0x31
3840
+ .4byte 0x8d
3841
+ .uleb128 0x2
3842
+ .4byte .LASF12
3843
+ .byte 0x3
3844
+ .byte 0x32
3845
+ .4byte 0x8d
3846
+ .uleb128 0x3
3847
+ .byte 0x8
3848
+ .byte 0x7
3849
+ .4byte .LASF13
3850
+ .uleb128 0x8
3851
+ .byte 0x8
3852
+ .4byte 0xee
3853
+ .uleb128 0x3
3854
+ .byte 0x1
3855
+ .byte 0x8
3856
+ .4byte .LASF14
3857
+ .uleb128 0x7
3858
+ .4byte 0xe7
3859
+ .uleb128 0x3
3860
+ .byte 0x8
3861
+ .byte 0x5
3862
+ .4byte .LASF15
3863
+ .uleb128 0x8
3864
+ .byte 0x8
3865
+ .4byte 0xe7
3866
+ .uleb128 0x2
3867
+ .4byte .LASF16
3868
+ .byte 0x4
3869
+ .byte 0x59
3870
+ .4byte 0x42
3871
+ .uleb128 0x2
3872
+ .4byte .LASF17
3873
+ .byte 0x4
3874
+ .byte 0x5b
3875
+ .4byte 0x3b
3876
+ .uleb128 0x2
3877
+ .4byte .LASF18
3878
+ .byte 0x4
3879
+ .byte 0x69
3880
+ .4byte 0x62
3881
+ .uleb128 0x2
3882
+ .4byte .LASF19
3883
+ .byte 0x4
3884
+ .byte 0x6b
3885
+ .4byte 0x74
3886
+ .uleb128 0x2
3887
+ .4byte .LASF20
3888
+ .byte 0x4
3889
+ .byte 0x97
3890
+ .4byte 0x74
3891
+ .uleb128 0x9
3892
+ .byte 0x8
3893
+ .uleb128 0x4
3894
+ .4byte .LASF22
3895
+ .byte 0x6
3896
+ .byte 0xb
3897
+ .4byte 0xfa
3898
+ .uleb128 0x3
3899
+ .byte 0x1
3900
+ .byte 0x2
3901
+ .4byte .LASF23
3902
+ .uleb128 0xa
3903
+ .4byte 0xe7
3904
+ .4byte 0x156
3905
+ .uleb128 0xb
3906
+ .byte 0
3907
+ .uleb128 0xc
3908
+ .4byte .LASF24
3909
+ .byte 0x7
3910
+ .2byte 0x140
3911
+ .4byte 0x14b
3912
+ .uleb128 0xc
3913
+ .4byte .LASF25
3914
+ .byte 0x7
3915
+ .2byte 0x143
3916
+ .4byte 0x14b
3917
+ .uleb128 0xc
3918
+ .4byte .LASF26
3919
+ .byte 0x7
3920
+ .2byte 0x143
3921
+ .4byte 0x14b
3922
+ .uleb128 0xd
3923
+ .4byte .LASF45
3924
+ .byte 0xa0
3925
+ .byte 0x8
3926
+ .byte 0x83
3927
+ .4byte 0x25f
3928
+ .uleb128 0xe
3929
+ .4byte .LASF27
3930
+ .byte 0x8
3931
+ .byte 0x84
3932
+ .4byte 0x1397
3933
+ .byte 0
3934
+ .uleb128 0xe
3935
+ .4byte .LASF28
3936
+ .byte 0x8
3937
+ .byte 0x85
3938
+ .4byte 0xe1
3939
+ .byte 0x8
3940
+ .uleb128 0xe
3941
+ .4byte .LASF29
3942
+ .byte 0x8
3943
+ .byte 0x86
3944
+ .4byte 0x137
3945
+ .byte 0x10
3946
+ .uleb128 0xe
3947
+ .4byte .LASF30
3948
+ .byte 0x8
3949
+ .byte 0x87
3950
+ .4byte 0x137
3951
+ .byte 0x18
3952
+ .uleb128 0xe
3953
+ .4byte .LASF31
3954
+ .byte 0x8
3955
+ .byte 0x88
3956
+ .4byte 0x137
3957
+ .byte 0x20
3958
+ .uleb128 0xe
3959
+ .4byte .LASF32
3960
+ .byte 0x8
3961
+ .byte 0x89
3962
+ .4byte 0x133e
3963
+ .byte 0x28
3964
+ .uleb128 0xe
3965
+ .4byte .LASF33
3966
+ .byte 0x8
3967
+ .byte 0x8a
3968
+ .4byte 0x10b
3969
+ .byte 0x30
3970
+ .uleb128 0xe
3971
+ .4byte .LASF34
3972
+ .byte 0x8
3973
+ .byte 0x8b
3974
+ .4byte 0x25f
3975
+ .byte 0x38
3976
+ .uleb128 0xe
3977
+ .4byte .LASF35
3978
+ .byte 0x8
3979
+ .byte 0x8c
3980
+ .4byte 0x137
3981
+ .byte 0x40
3982
+ .uleb128 0xe
3983
+ .4byte .LASF36
3984
+ .byte 0x8
3985
+ .byte 0x8d
3986
+ .4byte 0x13e6
3987
+ .byte 0x48
3988
+ .uleb128 0xe
3989
+ .4byte .LASF37
3990
+ .byte 0x8
3991
+ .byte 0x8e
3992
+ .4byte 0x137
3993
+ .byte 0x50
3994
+ .uleb128 0xe
3995
+ .4byte .LASF38
3996
+ .byte 0x8
3997
+ .byte 0x8f
3998
+ .4byte 0x137
3999
+ .byte 0x58
4000
+ .uleb128 0xe
4001
+ .4byte .LASF39
4002
+ .byte 0x8
4003
+ .byte 0x90
4004
+ .4byte 0x292
4005
+ .byte 0x60
4006
+ .uleb128 0xe
4007
+ .4byte .LASF40
4008
+ .byte 0x8
4009
+ .byte 0x91
4010
+ .4byte 0x292
4011
+ .byte 0x70
4012
+ .uleb128 0xe
4013
+ .4byte .LASF41
4014
+ .byte 0x8
4015
+ .byte 0x92
4016
+ .4byte 0x292
4017
+ .byte 0x80
4018
+ .uleb128 0xe
4019
+ .4byte .LASF42
4020
+ .byte 0x8
4021
+ .byte 0x93
4022
+ .4byte 0x121
4023
+ .byte 0x90
4024
+ .uleb128 0xe
4025
+ .4byte .LASF43
4026
+ .byte 0x8
4027
+ .byte 0x94
4028
+ .4byte 0x54
4029
+ .byte 0x94
4030
+ .uleb128 0xf
4031
+ .string "seq"
4032
+ .byte 0x8
4033
+ .byte 0x95
4034
+ .4byte 0x54
4035
+ .byte 0x98
4036
+ .byte 0
4037
+ .uleb128 0x8
4038
+ .byte 0x8
4039
+ .4byte 0x17a
4040
+ .uleb128 0x8
4041
+ .byte 0x8
4042
+ .4byte 0x26b
4043
+ .uleb128 0x10
4044
+ .uleb128 0xa
4045
+ .4byte 0x10b
4046
+ .4byte 0x277
4047
+ .uleb128 0xb
4048
+ .byte 0
4049
+ .uleb128 0x4
4050
+ .4byte .LASF44
4051
+ .byte 0x9
4052
+ .byte 0x10
4053
+ .4byte 0x26c
4054
+ .uleb128 0xa
4055
+ .4byte 0x34
4056
+ .4byte 0x292
4057
+ .uleb128 0x11
4058
+ .4byte 0xda
4059
+ .byte 0x5
4060
+ .byte 0
4061
+ .uleb128 0xd
4062
+ .4byte .LASF46
4063
+ .byte 0x10
4064
+ .byte 0xa
4065
+ .byte 0x16
4066
+ .4byte 0x2b7
4067
+ .uleb128 0xe
4068
+ .4byte .LASF47
4069
+ .byte 0xa
4070
+ .byte 0x17
4071
+ .4byte 0x2b7
4072
+ .byte 0
4073
+ .uleb128 0xe
4074
+ .4byte .LASF48
4075
+ .byte 0xa
4076
+ .byte 0x17
4077
+ .4byte 0x2b7
4078
+ .byte 0x8
4079
+ .byte 0
4080
+ .uleb128 0x8
4081
+ .byte 0x8
4082
+ .4byte 0x292
4083
+ .uleb128 0xd
4084
+ .4byte .LASF49
4085
+ .byte 0x10
4086
+ .byte 0xb
4087
+ .byte 0xf
4088
+ .4byte 0x2e2
4089
+ .uleb128 0xe
4090
+ .4byte .LASF28
4091
+ .byte 0xb
4092
+ .byte 0x10
4093
+ .4byte 0xfa
4094
+ .byte 0
4095
+ .uleb128 0xe
4096
+ .4byte .LASF50
4097
+ .byte 0xb
4098
+ .byte 0x11
4099
+ .4byte 0x2fb
4100
+ .byte 0x8
4101
+ .byte 0
4102
+ .uleb128 0x7
4103
+ .4byte 0x2bd
4104
+ .uleb128 0x12
4105
+ .4byte 0x54
4106
+ .4byte 0x2fb
4107
+ .uleb128 0x13
4108
+ .4byte 0x54
4109
+ .uleb128 0x13
4110
+ .4byte 0x54
4111
+ .byte 0
4112
+ .uleb128 0x8
4113
+ .byte 0x8
4114
+ .4byte 0x2e7
4115
+ .uleb128 0xa
4116
+ .4byte 0x2e2
4117
+ .4byte 0x30c
4118
+ .uleb128 0xb
4119
+ .byte 0
4120
+ .uleb128 0x7
4121
+ .4byte 0x301
4122
+ .uleb128 0x4
4123
+ .4byte .LASF49
4124
+ .byte 0xb
4125
+ .byte 0xe1
4126
+ .4byte 0x30c
4127
+ .uleb128 0x14
4128
+ .2byte 0x1220
4129
+ .byte 0xc
4130
+ .byte 0x13
4131
+ .4byte 0x370
4132
+ .uleb128 0xe
4133
+ .4byte .LASF51
4134
+ .byte 0xc
4135
+ .byte 0x14
4136
+ .4byte 0x10b
4137
+ .byte 0
4138
+ .uleb128 0xe
4139
+ .4byte .LASF52
4140
+ .byte 0xc
4141
+ .byte 0x15
4142
+ .4byte 0x100
4143
+ .byte 0x8
4144
+ .uleb128 0xe
4145
+ .4byte .LASF53
4146
+ .byte 0xc
4147
+ .byte 0x16
4148
+ .4byte 0x10b
4149
+ .byte 0x10
4150
+ .uleb128 0xe
4151
+ .4byte .LASF54
4152
+ .byte 0xc
4153
+ .byte 0x17
4154
+ .4byte 0x370
4155
+ .byte 0x18
4156
+ .uleb128 0x15
4157
+ .4byte .LASF55
4158
+ .byte 0xc
4159
+ .byte 0x18
4160
+ .4byte 0x381
4161
+ .2byte 0x1018
4162
+ .uleb128 0x16
4163
+ .string "mtd"
4164
+ .byte 0xc
4165
+ .byte 0x31
4166
+ .4byte 0x397
4167
+ .2byte 0x1218
4168
+ .byte 0
4169
+ .uleb128 0xa
4170
+ .4byte 0x10b
4171
+ .4byte 0x381
4172
+ .uleb128 0x17
4173
+ .4byte 0xda
4174
+ .2byte 0x1ff
4175
+ .byte 0
4176
+ .uleb128 0xa
4177
+ .4byte 0x29
4178
+ .4byte 0x392
4179
+ .uleb128 0x17
4180
+ .4byte 0xda
4181
+ .2byte 0x1ff
4182
+ .byte 0
4183
+ .uleb128 0x18
4184
+ .4byte .LASF317
4185
+ .uleb128 0x8
4186
+ .byte 0x8
4187
+ .4byte 0x392
4188
+ .uleb128 0x2
4189
+ .4byte .LASF56
4190
+ .byte 0xc
4191
+ .byte 0x37
4192
+ .4byte 0x31c
4193
+ .uleb128 0xa
4194
+ .4byte 0x39d
4195
+ .4byte 0x3b3
4196
+ .uleb128 0xb
4197
+ .byte 0
4198
+ .uleb128 0x4
4199
+ .4byte .LASF57
4200
+ .byte 0xc
4201
+ .byte 0x39
4202
+ .4byte 0x3a8
4203
+ .uleb128 0x3
4204
+ .byte 0x10
4205
+ .byte 0x4
4206
+ .4byte .LASF58
4207
+ .uleb128 0xd
4208
+ .4byte .LASF59
4209
+ .byte 0x10
4210
+ .byte 0xd
4211
+ .byte 0x10
4212
+ .4byte 0x3ea
4213
+ .uleb128 0xe
4214
+ .4byte .LASF60
4215
+ .byte 0xd
4216
+ .byte 0x11
4217
+ .4byte 0xc4
4218
+ .byte 0
4219
+ .uleb128 0xe
4220
+ .4byte .LASF51
4221
+ .byte 0xd
4222
+ .byte 0x12
4223
+ .4byte 0xcf
4224
+ .byte 0x8
4225
+ .byte 0
4226
+ .uleb128 0x19
4227
+ .4byte .LASF61
4228
+ .2byte 0x120
4229
+ .byte 0xd
4230
+ .byte 0x15
4231
+ .4byte 0x41c
4232
+ .uleb128 0xf
4233
+ .string "cnt"
4234
+ .byte 0xd
4235
+ .byte 0x16
4236
+ .4byte 0x3b
4237
+ .byte 0
4238
+ .uleb128 0xe
4239
+ .4byte .LASF51
4240
+ .byte 0xd
4241
+ .byte 0x17
4242
+ .4byte 0xcf
4243
+ .byte 0x8
4244
+ .uleb128 0xe
4245
+ .4byte .LASF62
4246
+ .byte 0xd
4247
+ .byte 0x18
4248
+ .4byte 0x41c
4249
+ .byte 0x10
4250
+ .byte 0
4251
+ .uleb128 0xa
4252
+ .4byte 0x3c5
4253
+ .4byte 0x42c
4254
+ .uleb128 0x11
4255
+ .4byte 0xda
4256
+ .byte 0x10
4257
+ .byte 0
4258
+ .uleb128 0x1a
4259
+ .string "lmb"
4260
+ .2byte 0x240
4261
+ .byte 0xd
4262
+ .byte 0x1b
4263
+ .4byte 0x453
4264
+ .uleb128 0xe
4265
+ .4byte .LASF63
4266
+ .byte 0xd
4267
+ .byte 0x1c
4268
+ .4byte 0x3ea
4269
+ .byte 0
4270
+ .uleb128 0x15
4271
+ .4byte .LASF64
4272
+ .byte 0xd
4273
+ .byte 0x1d
4274
+ .4byte 0x3ea
4275
+ .2byte 0x120
4276
+ .byte 0
4277
+ .uleb128 0x1b
4278
+ .string "lmb"
4279
+ .byte 0xd
4280
+ .byte 0x20
4281
+ .4byte 0x42c
4282
+ .uleb128 0x1c
4283
+ .byte 0x10
4284
+ .byte 0xe
4285
+ .byte 0x5d
4286
+ .4byte 0x47f
4287
+ .uleb128 0xe
4288
+ .4byte .LASF54
4289
+ .byte 0xe
4290
+ .byte 0x5e
4291
+ .4byte 0xb9
4292
+ .byte 0
4293
+ .uleb128 0xe
4294
+ .4byte .LASF51
4295
+ .byte 0xe
4296
+ .byte 0x5f
4297
+ .4byte 0xb9
4298
+ .byte 0x8
4299
+ .byte 0
4300
+ .uleb128 0xd
4301
+ .4byte .LASF65
4302
+ .byte 0xb0
4303
+ .byte 0xe
4304
+ .byte 0x1b
4305
+ .4byte 0x57c
4306
+ .uleb128 0xe
4307
+ .4byte .LASF66
4308
+ .byte 0xe
4309
+ .byte 0x1c
4310
+ .4byte 0x3b
4311
+ .byte 0
4312
+ .uleb128 0xe
4313
+ .4byte .LASF67
4314
+ .byte 0xe
4315
+ .byte 0x1d
4316
+ .4byte 0xcf
4317
+ .byte 0x8
4318
+ .uleb128 0xe
4319
+ .4byte .LASF68
4320
+ .byte 0xe
4321
+ .byte 0x1e
4322
+ .4byte 0x3b
4323
+ .byte 0x10
4324
+ .uleb128 0xe
4325
+ .4byte .LASF69
4326
+ .byte 0xe
4327
+ .byte 0x1f
4328
+ .4byte 0x3b
4329
+ .byte 0x18
4330
+ .uleb128 0xe
4331
+ .4byte .LASF70
4332
+ .byte 0xe
4333
+ .byte 0x20
4334
+ .4byte 0x3b
4335
+ .byte 0x20
4336
+ .uleb128 0xe
4337
+ .4byte .LASF71
4338
+ .byte 0xe
4339
+ .byte 0x21
4340
+ .4byte 0x3b
4341
+ .byte 0x28
4342
+ .uleb128 0xe
4343
+ .4byte .LASF72
4344
+ .byte 0xe
4345
+ .byte 0x22
4346
+ .4byte 0x3b
4347
+ .byte 0x30
4348
+ .uleb128 0xe
4349
+ .4byte .LASF73
4350
+ .byte 0xe
4351
+ .byte 0x24
4352
+ .4byte 0x3b
4353
+ .byte 0x38
4354
+ .uleb128 0xe
4355
+ .4byte .LASF74
4356
+ .byte 0xe
4357
+ .byte 0x25
4358
+ .4byte 0x3b
4359
+ .byte 0x40
4360
+ .uleb128 0xe
4361
+ .4byte .LASF75
4362
+ .byte 0xe
4363
+ .byte 0x26
4364
+ .4byte 0x3b
4365
+ .byte 0x48
4366
+ .uleb128 0xe
4367
+ .4byte .LASF76
4368
+ .byte 0xe
4369
+ .byte 0x31
4370
+ .4byte 0x3b
4371
+ .byte 0x50
4372
+ .uleb128 0xe
4373
+ .4byte .LASF77
4374
+ .byte 0xe
4375
+ .byte 0x32
4376
+ .4byte 0x3b
4377
+ .byte 0x58
4378
+ .uleb128 0xe
4379
+ .4byte .LASF78
4380
+ .byte 0xe
4381
+ .byte 0x33
4382
+ .4byte 0x282
4383
+ .byte 0x60
4384
+ .uleb128 0xe
4385
+ .4byte .LASF79
4386
+ .byte 0xe
4387
+ .byte 0x34
4388
+ .4byte 0x42
4389
+ .byte 0x66
4390
+ .uleb128 0xe
4391
+ .4byte .LASF80
4392
+ .byte 0xe
4393
+ .byte 0x35
4394
+ .4byte 0x3b
4395
+ .byte 0x68
4396
+ .uleb128 0xe
4397
+ .4byte .LASF81
4398
+ .byte 0xe
4399
+ .byte 0x36
4400
+ .4byte 0x3b
4401
+ .byte 0x70
4402
+ .uleb128 0xe
4403
+ .4byte .LASF82
4404
+ .byte 0xe
4405
+ .byte 0x57
4406
+ .4byte 0x10b
4407
+ .byte 0x78
4408
+ .uleb128 0xe
4409
+ .4byte .LASF83
4410
+ .byte 0xe
4411
+ .byte 0x58
4412
+ .4byte 0x10b
4413
+ .byte 0x80
4414
+ .uleb128 0xe
4415
+ .4byte .LASF84
4416
+ .byte 0xe
4417
+ .byte 0x5b
4418
+ .4byte 0x7f
4419
+ .byte 0x88
4420
+ .uleb128 0xe
4421
+ .4byte .LASF85
4422
+ .byte 0xe
4423
+ .byte 0x60
4424
+ .4byte 0x57c
4425
+ .byte 0x90
4426
+ .byte 0
4427
+ .uleb128 0xa
4428
+ .4byte 0x45e
4429
+ .4byte 0x58c
4430
+ .uleb128 0x11
4431
+ .4byte 0xda
4432
+ .byte 0x1
4433
+ .byte 0
4434
+ .uleb128 0x2
4435
+ .4byte .LASF86
4436
+ .byte 0xe
4437
+ .byte 0x62
4438
+ .4byte 0x47f
4439
+ .uleb128 0x4
4440
+ .4byte .LASF87
4441
+ .byte 0xf
4442
+ .byte 0x13
4443
+ .4byte 0x10b
4444
+ .uleb128 0x4
4445
+ .4byte .LASF88
4446
+ .byte 0xf
4447
+ .byte 0x14
4448
+ .4byte 0x10b
4449
+ .uleb128 0x4
4450
+ .4byte .LASF89
4451
+ .byte 0xf
4452
+ .byte 0x15
4453
+ .4byte 0x10b
4454
+ .uleb128 0x4
4455
+ .4byte .LASF90
4456
+ .byte 0xf
4457
+ .byte 0x16
4458
+ .4byte 0x10b
4459
+ .uleb128 0x4
4460
+ .4byte .LASF91
4461
+ .byte 0xf
4462
+ .byte 0x17
4463
+ .4byte 0x10b
4464
+ .uleb128 0x4
4465
+ .4byte .LASF92
4466
+ .byte 0xf
4467
+ .byte 0x18
4468
+ .4byte 0x10b
4469
+ .uleb128 0x4
4470
+ .4byte .LASF93
4471
+ .byte 0xf
4472
+ .byte 0x19
4473
+ .4byte 0x10b
4474
+ .uleb128 0x2
4475
+ .4byte .LASF94
4476
+ .byte 0x10
4477
+ .byte 0x11
4478
+ .4byte 0x12c
4479
+ .uleb128 0xd
4480
+ .4byte .LASF95
4481
+ .byte 0x28
4482
+ .byte 0x11
4483
+ .byte 0x39
4484
+ .4byte 0x674
4485
+ .uleb128 0xe
4486
+ .4byte .LASF96
4487
+ .byte 0x11
4488
+ .byte 0x3a
4489
+ .4byte 0x5e4
4490
+ .byte 0
4491
+ .uleb128 0xe
4492
+ .4byte .LASF97
4493
+ .byte 0x11
4494
+ .byte 0x3b
4495
+ .4byte 0x5e4
4496
+ .byte 0x4
4497
+ .uleb128 0xe
4498
+ .4byte .LASF98
4499
+ .byte 0x11
4500
+ .byte 0x3c
4501
+ .4byte 0x5e4
4502
+ .byte 0x8
4503
+ .uleb128 0xe
4504
+ .4byte .LASF99
4505
+ .byte 0x11
4506
+ .byte 0x3d
4507
+ .4byte 0x5e4
4508
+ .byte 0xc
4509
+ .uleb128 0xe
4510
+ .4byte .LASF100
4511
+ .byte 0x11
4512
+ .byte 0x3e
4513
+ .4byte 0x5e4
4514
+ .byte 0x10
4515
+ .uleb128 0xe
4516
+ .4byte .LASF101
4517
+ .byte 0x11
4518
+ .byte 0x3f
4519
+ .4byte 0x5e4
4520
+ .byte 0x14
4521
+ .uleb128 0xe
4522
+ .4byte .LASF102
4523
+ .byte 0x11
4524
+ .byte 0x40
4525
+ .4byte 0x5e4
4526
+ .byte 0x18
4527
+ .uleb128 0xe
4528
+ .4byte .LASF103
4529
+ .byte 0x11
4530
+ .byte 0x43
4531
+ .4byte 0x5e4
4532
+ .byte 0x1c
4533
+ .uleb128 0xe
4534
+ .4byte .LASF104
4535
+ .byte 0x11
4536
+ .byte 0x46
4537
+ .4byte 0x5e4
4538
+ .byte 0x20
4539
+ .uleb128 0xe
4540
+ .4byte .LASF105
4541
+ .byte 0x11
4542
+ .byte 0x49
4543
+ .4byte 0x5e4
4544
+ .byte 0x24
4545
+ .byte 0
4546
+ .uleb128 0xc
4547
+ .4byte .LASF106
4548
+ .byte 0x12
4549
+ .2byte 0x136
4550
+ .4byte 0x680
4551
+ .uleb128 0x8
4552
+ .byte 0x8
4553
+ .4byte 0x5ef
4554
+ .uleb128 0x1d
4555
+ .4byte .LASF107
4556
+ .byte 0x40
4557
+ .byte 0x13
4558
+ .2byte 0x137
4559
+ .4byte 0x730
4560
+ .uleb128 0x1e
4561
+ .4byte .LASF108
4562
+ .byte 0x13
4563
+ .2byte 0x138
4564
+ .4byte 0x12c
4565
+ .byte 0
4566
+ .uleb128 0x1e
4567
+ .4byte .LASF109
4568
+ .byte 0x13
4569
+ .2byte 0x139
4570
+ .4byte 0x12c
4571
+ .byte 0x4
4572
+ .uleb128 0x1e
4573
+ .4byte .LASF110
4574
+ .byte 0x13
4575
+ .2byte 0x13a
4576
+ .4byte 0x12c
4577
+ .byte 0x8
4578
+ .uleb128 0x1e
4579
+ .4byte .LASF111
4580
+ .byte 0x13
4581
+ .2byte 0x13b
4582
+ .4byte 0x12c
4583
+ .byte 0xc
4584
+ .uleb128 0x1e
4585
+ .4byte .LASF112
4586
+ .byte 0x13
4587
+ .2byte 0x13c
4588
+ .4byte 0x12c
4589
+ .byte 0x10
4590
+ .uleb128 0x1e
4591
+ .4byte .LASF113
4592
+ .byte 0x13
4593
+ .2byte 0x13d
4594
+ .4byte 0x12c
4595
+ .byte 0x14
4596
+ .uleb128 0x1e
4597
+ .4byte .LASF114
4598
+ .byte 0x13
4599
+ .2byte 0x13e
4600
+ .4byte 0x12c
4601
+ .byte 0x18
4602
+ .uleb128 0x1e
4603
+ .4byte .LASF115
4604
+ .byte 0x13
4605
+ .2byte 0x13f
4606
+ .4byte 0x116
4607
+ .byte 0x1c
4608
+ .uleb128 0x1e
4609
+ .4byte .LASF116
4610
+ .byte 0x13
4611
+ .2byte 0x140
4612
+ .4byte 0x116
4613
+ .byte 0x1d
4614
+ .uleb128 0x1e
4615
+ .4byte .LASF117
4616
+ .byte 0x13
4617
+ .2byte 0x141
4618
+ .4byte 0x116
4619
+ .byte 0x1e
4620
+ .uleb128 0x1e
4621
+ .4byte .LASF118
4622
+ .byte 0x13
4623
+ .2byte 0x142
4624
+ .4byte 0x116
4625
+ .byte 0x1f
4626
+ .uleb128 0x1e
4627
+ .4byte .LASF119
4628
+ .byte 0x13
4629
+ .2byte 0x143
4630
+ .4byte 0x730
4631
+ .byte 0x20
4632
+ .byte 0
4633
+ .uleb128 0xa
4634
+ .4byte 0x116
4635
+ .4byte 0x740
4636
+ .uleb128 0x11
4637
+ .4byte 0xda
4638
+ .byte 0x1f
4639
+ .byte 0
4640
+ .uleb128 0x1f
4641
+ .4byte .LASF120
4642
+ .byte 0x13
4643
+ .2byte 0x144
4644
+ .4byte 0x686
4645
+ .uleb128 0x1d
4646
+ .4byte .LASF121
4647
+ .byte 0x30
4648
+ .byte 0x13
4649
+ .2byte 0x146
4650
+ .4byte 0x7ce
4651
+ .uleb128 0x1e
4652
+ .4byte .LASF54
4653
+ .byte 0x13
4654
+ .2byte 0x147
4655
+ .4byte 0x10b
4656
+ .byte 0
4657
+ .uleb128 0x20
4658
+ .string "end"
4659
+ .byte 0x13
4660
+ .2byte 0x147
4661
+ .4byte 0x10b
4662
+ .byte 0x8
4663
+ .uleb128 0x1e
4664
+ .4byte .LASF122
4665
+ .byte 0x13
4666
+ .2byte 0x148
4667
+ .4byte 0x10b
4668
+ .byte 0x10
4669
+ .uleb128 0x1e
4670
+ .4byte .LASF123
4671
+ .byte 0x13
4672
+ .2byte 0x148
4673
+ .4byte 0x10b
4674
+ .byte 0x18
4675
+ .uleb128 0x1e
4676
+ .4byte .LASF124
4677
+ .byte 0x13
4678
+ .2byte 0x149
4679
+ .4byte 0x10b
4680
+ .byte 0x20
4681
+ .uleb128 0x1e
4682
+ .4byte .LASF125
4683
+ .byte 0x13
4684
+ .2byte 0x14a
4685
+ .4byte 0x116
4686
+ .byte 0x28
4687
+ .uleb128 0x1e
4688
+ .4byte .LASF126
4689
+ .byte 0x13
4690
+ .2byte 0x14a
4691
+ .4byte 0x116
4692
+ .byte 0x29
4693
+ .uleb128 0x20
4694
+ .string "os"
4695
+ .byte 0x13
4696
+ .2byte 0x14a
4697
+ .4byte 0x116
4698
+ .byte 0x2a
4699
+ .uleb128 0x1e
4700
+ .4byte .LASF127
4701
+ .byte 0x13
4702
+ .2byte 0x14b
4703
+ .4byte 0x116
4704
+ .byte 0x2b
4705
+ .byte 0
4706
+ .uleb128 0x1f
4707
+ .4byte .LASF128
4708
+ .byte 0x13
4709
+ .2byte 0x14c
4710
+ .4byte 0x74c
4711
+ .uleb128 0x21
4712
+ .4byte .LASF129
4713
+ .2byte 0x380
4714
+ .byte 0x13
4715
+ .2byte 0x152
4716
+ .4byte 0x977
4717
+ .uleb128 0x1e
4718
+ .4byte .LASF130
4719
+ .byte 0x13
4720
+ .2byte 0x158
4721
+ .4byte 0x977
4722
+ .byte 0
4723
+ .uleb128 0x1e
4724
+ .4byte .LASF131
4725
+ .byte 0x13
4726
+ .2byte 0x159
4727
+ .4byte 0x740
4728
+ .byte 0x8
4729
+ .uleb128 0x1e
4730
+ .4byte .LASF132
4731
+ .byte 0x13
4732
+ .2byte 0x15a
4733
+ .4byte 0x10b
4734
+ .byte 0x48
4735
+ .uleb128 0x1e
4736
+ .4byte .LASF133
4737
+ .byte 0x13
4738
+ .2byte 0x15d
4739
+ .4byte 0xe1
4740
+ .byte 0x50
4741
+ .uleb128 0x1e
4742
+ .4byte .LASF134
4743
+ .byte 0x13
4744
+ .2byte 0x15f
4745
+ .4byte 0x137
4746
+ .byte 0x58
4747
+ .uleb128 0x1e
4748
+ .4byte .LASF135
4749
+ .byte 0x13
4750
+ .2byte 0x160
4751
+ .4byte 0xe1
4752
+ .byte 0x60
4753
+ .uleb128 0x1e
4754
+ .4byte .LASF136
4755
+ .byte 0x13
4756
+ .2byte 0x161
4757
+ .4byte 0x54
4758
+ .byte 0x68
4759
+ .uleb128 0x1e
4760
+ .4byte .LASF137
4761
+ .byte 0x13
4762
+ .2byte 0x163
4763
+ .4byte 0x137
4764
+ .byte 0x70
4765
+ .uleb128 0x1e
4766
+ .4byte .LASF138
4767
+ .byte 0x13
4768
+ .2byte 0x164
4769
+ .4byte 0xe1
4770
+ .byte 0x78
4771
+ .uleb128 0x1e
4772
+ .4byte .LASF139
4773
+ .byte 0x13
4774
+ .2byte 0x165
4775
+ .4byte 0x54
4776
+ .byte 0x80
4777
+ .uleb128 0x1e
4778
+ .4byte .LASF140
4779
+ .byte 0x13
4780
+ .2byte 0x167
4781
+ .4byte 0x137
4782
+ .byte 0x88
4783
+ .uleb128 0x1e
4784
+ .4byte .LASF141
4785
+ .byte 0x13
4786
+ .2byte 0x168
4787
+ .4byte 0xe1
4788
+ .byte 0x90
4789
+ .uleb128 0x1e
4790
+ .4byte .LASF142
4791
+ .byte 0x13
4792
+ .2byte 0x169
4793
+ .4byte 0x54
4794
+ .byte 0x98
4795
+ .uleb128 0x1e
4796
+ .4byte .LASF143
4797
+ .byte 0x13
4798
+ .2byte 0x16b
4799
+ .4byte 0x137
4800
+ .byte 0xa0
4801
+ .uleb128 0x1e
4802
+ .4byte .LASF144
4803
+ .byte 0x13
4804
+ .2byte 0x16c
4805
+ .4byte 0xe1
4806
+ .byte 0xa8
4807
+ .uleb128 0x1e
4808
+ .4byte .LASF145
4809
+ .byte 0x13
4810
+ .2byte 0x16d
4811
+ .4byte 0x54
4812
+ .byte 0xb0
4813
+ .uleb128 0x20
4814
+ .string "os"
4815
+ .byte 0x13
4816
+ .2byte 0x171
4817
+ .4byte 0x7ce
4818
+ .byte 0xb8
4819
+ .uleb128 0x20
4820
+ .string "ep"
4821
+ .byte 0x13
4822
+ .2byte 0x172
4823
+ .4byte 0x10b
4824
+ .byte 0xe8
4825
+ .uleb128 0x1e
4826
+ .4byte .LASF146
4827
+ .byte 0x13
4828
+ .2byte 0x174
4829
+ .4byte 0x10b
4830
+ .byte 0xf0
4831
+ .uleb128 0x1e
4832
+ .4byte .LASF147
4833
+ .byte 0x13
4834
+ .2byte 0x174
4835
+ .4byte 0x10b
4836
+ .byte 0xf8
4837
+ .uleb128 0x22
4838
+ .4byte .LASF148
4839
+ .byte 0x13
4840
+ .2byte 0x176
4841
+ .4byte 0xfa
4842
+ .2byte 0x100
4843
+ .uleb128 0x22
4844
+ .4byte .LASF149
4845
+ .byte 0x13
4846
+ .2byte 0x177
4847
+ .4byte 0x10b
4848
+ .2byte 0x108
4849
+ .uleb128 0x22
4850
+ .4byte .LASF150
4851
+ .byte 0x13
4852
+ .2byte 0x179
4853
+ .4byte 0x10b
4854
+ .2byte 0x110
4855
+ .uleb128 0x22
4856
+ .4byte .LASF151
4857
+ .byte 0x13
4858
+ .2byte 0x17a
4859
+ .4byte 0x10b
4860
+ .2byte 0x118
4861
+ .uleb128 0x22
4862
+ .4byte .LASF152
4863
+ .byte 0x13
4864
+ .2byte 0x17b
4865
+ .4byte 0x10b
4866
+ .2byte 0x120
4867
+ .uleb128 0x22
4868
+ .4byte .LASF153
4869
+ .byte 0x13
4870
+ .2byte 0x17c
4871
+ .4byte 0x10b
4872
+ .2byte 0x128
4873
+ .uleb128 0x23
4874
+ .string "kbd"
4875
+ .byte 0x13
4876
+ .2byte 0x17d
4877
+ .4byte 0x97d
4878
+ .2byte 0x130
4879
+ .uleb128 0x22
4880
+ .4byte .LASF154
4881
+ .byte 0x13
4882
+ .2byte 0x180
4883
+ .4byte 0x54
4884
+ .2byte 0x138
4885
+ .uleb128 0x22
4886
+ .4byte .LASF155
4887
+ .byte 0x13
4888
+ .2byte 0x18d
4889
+ .4byte 0x54
4890
+ .2byte 0x13c
4891
+ .uleb128 0x23
4892
+ .string "lmb"
4893
+ .byte 0x13
4894
+ .2byte 0x190
4895
+ .4byte 0x42c
4896
+ .2byte 0x140
4897
+ .byte 0
4898
+ .uleb128 0x8
4899
+ .byte 0x8
4900
+ .4byte 0x740
4901
+ .uleb128 0x8
4902
+ .byte 0x8
4903
+ .4byte 0x58c
4904
+ .uleb128 0x1f
4905
+ .4byte .LASF156
4906
+ .byte 0x13
4907
+ .2byte 0x196
4908
+ .4byte 0x7da
4909
+ .uleb128 0xc
4910
+ .4byte .LASF157
4911
+ .byte 0x13
4912
+ .2byte 0x198
4913
+ .4byte 0x983
4914
+ .uleb128 0xa
4915
+ .4byte 0xe7
4916
+ .4byte 0x9ac
4917
+ .uleb128 0x17
4918
+ .4byte 0xda
4919
+ .2byte 0x3ff
4920
+ .byte 0
4921
+ .uleb128 0x24
4922
+ .4byte .LASF351
4923
+ .byte 0x4
4924
+ .4byte 0x54
4925
+ .byte 0x18
4926
+ .byte 0xe
4927
+ .4byte 0xc0f
4928
+ .uleb128 0x25
4929
+ .4byte .LASF158
4930
+ .byte 0
4931
+ .uleb128 0x25
4932
+ .4byte .LASF159
4933
+ .byte 0x1
4934
+ .uleb128 0x25
4935
+ .4byte .LASF160
4936
+ .byte 0x2
4937
+ .uleb128 0x25
4938
+ .4byte .LASF161
4939
+ .byte 0x3
4940
+ .uleb128 0x25
4941
+ .4byte .LASF162
4942
+ .byte 0x4
4943
+ .uleb128 0x25
4944
+ .4byte .LASF163
4945
+ .byte 0x5
4946
+ .uleb128 0x25
4947
+ .4byte .LASF164
4948
+ .byte 0x6
4949
+ .uleb128 0x25
4950
+ .4byte .LASF165
4951
+ .byte 0x7
4952
+ .uleb128 0x25
4953
+ .4byte .LASF166
4954
+ .byte 0x8
4955
+ .uleb128 0x25
4956
+ .4byte .LASF167
4957
+ .byte 0x9
4958
+ .uleb128 0x25
4959
+ .4byte .LASF168
4960
+ .byte 0xa
4961
+ .uleb128 0x25
4962
+ .4byte .LASF169
4963
+ .byte 0xb
4964
+ .uleb128 0x25
4965
+ .4byte .LASF170
4966
+ .byte 0xc
4967
+ .uleb128 0x25
4968
+ .4byte .LASF171
4969
+ .byte 0xd
4970
+ .uleb128 0x25
4971
+ .4byte .LASF172
4972
+ .byte 0xe
4973
+ .uleb128 0x25
4974
+ .4byte .LASF173
4975
+ .byte 0xf
4976
+ .uleb128 0x25
4977
+ .4byte .LASF174
4978
+ .byte 0x10
4979
+ .uleb128 0x25
4980
+ .4byte .LASF175
4981
+ .byte 0x11
4982
+ .uleb128 0x25
4983
+ .4byte .LASF176
4984
+ .byte 0x12
4985
+ .uleb128 0x25
4986
+ .4byte .LASF177
4987
+ .byte 0x13
4988
+ .uleb128 0x25
4989
+ .4byte .LASF178
4990
+ .byte 0x14
4991
+ .uleb128 0x25
4992
+ .4byte .LASF179
4993
+ .byte 0x15
4994
+ .uleb128 0x25
4995
+ .4byte .LASF180
4996
+ .byte 0x16
4997
+ .uleb128 0x25
4998
+ .4byte .LASF181
4999
+ .byte 0x17
5000
+ .uleb128 0x25
5001
+ .4byte .LASF182
5002
+ .byte 0x18
5003
+ .uleb128 0x25
5004
+ .4byte .LASF183
5005
+ .byte 0x19
5006
+ .uleb128 0x25
5007
+ .4byte .LASF184
5008
+ .byte 0x1a
5009
+ .uleb128 0x25
5010
+ .4byte .LASF185
5011
+ .byte 0x1b
5012
+ .uleb128 0x25
5013
+ .4byte .LASF186
5014
+ .byte 0x1c
5015
+ .uleb128 0x25
5016
+ .4byte .LASF187
5017
+ .byte 0x1d
5018
+ .uleb128 0x25
5019
+ .4byte .LASF188
5020
+ .byte 0x1e
5021
+ .uleb128 0x25
5022
+ .4byte .LASF189
5023
+ .byte 0x1f
5024
+ .uleb128 0x25
5025
+ .4byte .LASF190
5026
+ .byte 0x20
5027
+ .uleb128 0x25
5028
+ .4byte .LASF191
5029
+ .byte 0x21
5030
+ .uleb128 0x25
5031
+ .4byte .LASF192
5032
+ .byte 0x22
5033
+ .uleb128 0x25
5034
+ .4byte .LASF193
5035
+ .byte 0x23
5036
+ .uleb128 0x25
5037
+ .4byte .LASF194
5038
+ .byte 0x24
5039
+ .uleb128 0x25
5040
+ .4byte .LASF195
5041
+ .byte 0x25
5042
+ .uleb128 0x25
5043
+ .4byte .LASF196
5044
+ .byte 0x26
5045
+ .uleb128 0x25
5046
+ .4byte .LASF197
5047
+ .byte 0x27
5048
+ .uleb128 0x25
5049
+ .4byte .LASF198
5050
+ .byte 0x28
5051
+ .uleb128 0x25
5052
+ .4byte .LASF199
5053
+ .byte 0x29
5054
+ .uleb128 0x25
5055
+ .4byte .LASF200
5056
+ .byte 0x2a
5057
+ .uleb128 0x25
5058
+ .4byte .LASF201
5059
+ .byte 0x2b
5060
+ .uleb128 0x25
5061
+ .4byte .LASF202
5062
+ .byte 0x2c
5063
+ .uleb128 0x25
5064
+ .4byte .LASF203
5065
+ .byte 0x2d
5066
+ .uleb128 0x25
5067
+ .4byte .LASF204
5068
+ .byte 0x2e
5069
+ .uleb128 0x25
5070
+ .4byte .LASF205
5071
+ .byte 0x2f
5072
+ .uleb128 0x25
5073
+ .4byte .LASF206
5074
+ .byte 0x30
5075
+ .uleb128 0x25
5076
+ .4byte .LASF207
5077
+ .byte 0x31
5078
+ .uleb128 0x25
5079
+ .4byte .LASF208
5080
+ .byte 0x32
5081
+ .uleb128 0x25
5082
+ .4byte .LASF209
5083
+ .byte 0x33
5084
+ .uleb128 0x25
5085
+ .4byte .LASF210
5086
+ .byte 0x34
5087
+ .uleb128 0x25
5088
+ .4byte .LASF211
5089
+ .byte 0x35
5090
+ .uleb128 0x25
5091
+ .4byte .LASF212
5092
+ .byte 0x36
5093
+ .uleb128 0x25
5094
+ .4byte .LASF213
5095
+ .byte 0x37
5096
+ .uleb128 0x25
5097
+ .4byte .LASF214
5098
+ .byte 0x38
5099
+ .uleb128 0x25
5100
+ .4byte .LASF215
5101
+ .byte 0x39
5102
+ .uleb128 0x25
5103
+ .4byte .LASF216
5104
+ .byte 0x3a
5105
+ .uleb128 0x25
5106
+ .4byte .LASF217
5107
+ .byte 0x3b
5108
+ .uleb128 0x25
5109
+ .4byte .LASF218
5110
+ .byte 0x3c
5111
+ .uleb128 0x25
5112
+ .4byte .LASF219
5113
+ .byte 0x3d
5114
+ .uleb128 0x25
5115
+ .4byte .LASF220
5116
+ .byte 0x3e
5117
+ .uleb128 0x25
5118
+ .4byte .LASF221
5119
+ .byte 0x3f
5120
+ .uleb128 0x25
5121
+ .4byte .LASF222
5122
+ .byte 0x40
5123
+ .uleb128 0x25
5124
+ .4byte .LASF223
5125
+ .byte 0x41
5126
+ .uleb128 0x25
5127
+ .4byte .LASF224
5128
+ .byte 0x42
5129
+ .uleb128 0x25
5130
+ .4byte .LASF225
5131
+ .byte 0x43
5132
+ .uleb128 0x25
5133
+ .4byte .LASF226
5134
+ .byte 0x44
5135
+ .uleb128 0x25
5136
+ .4byte .LASF227
5137
+ .byte 0x45
5138
+ .uleb128 0x25
5139
+ .4byte .LASF228
5140
+ .byte 0x46
5141
+ .uleb128 0x25
5142
+ .4byte .LASF229
5143
+ .byte 0x47
5144
+ .uleb128 0x25
5145
+ .4byte .LASF230
5146
+ .byte 0x48
5147
+ .uleb128 0x25
5148
+ .4byte .LASF231
5149
+ .byte 0x49
5150
+ .uleb128 0x25
5151
+ .4byte .LASF232
5152
+ .byte 0x4a
5153
+ .uleb128 0x25
5154
+ .4byte .LASF233
5155
+ .byte 0x4b
5156
+ .uleb128 0x25
5157
+ .4byte .LASF234
5158
+ .byte 0x4c
5159
+ .uleb128 0x25
5160
+ .4byte .LASF235
5161
+ .byte 0x4d
5162
+ .uleb128 0x25
5163
+ .4byte .LASF236
5164
+ .byte 0x4e
5165
+ .uleb128 0x25
5166
+ .4byte .LASF237
5167
+ .byte 0x4f
5168
+ .uleb128 0x25
5169
+ .4byte .LASF238
5170
+ .byte 0x50
5171
+ .uleb128 0x25
5172
+ .4byte .LASF239
5173
+ .byte 0x51
5174
+ .uleb128 0x25
5175
+ .4byte .LASF240
5176
+ .byte 0x52
5177
+ .uleb128 0x25
5178
+ .4byte .LASF241
5179
+ .byte 0x53
5180
+ .uleb128 0x25
5181
+ .4byte .LASF242
5182
+ .byte 0x54
5183
+ .uleb128 0x25
5184
+ .4byte .LASF243
5185
+ .byte 0x55
5186
+ .uleb128 0x25
5187
+ .4byte .LASF244
5188
+ .byte 0x56
5189
+ .uleb128 0x25
5190
+ .4byte .LASF245
5191
+ .byte 0x57
5192
+ .uleb128 0x25
5193
+ .4byte .LASF246
5194
+ .byte 0x58
5195
+ .uleb128 0x25
5196
+ .4byte .LASF247
5197
+ .byte 0x59
5198
+ .uleb128 0x25
5199
+ .4byte .LASF248
5200
+ .byte 0x5a
5201
+ .uleb128 0x25
5202
+ .4byte .LASF249
5203
+ .byte 0x5b
5204
+ .uleb128 0x25
5205
+ .4byte .LASF250
5206
+ .byte 0x5c
5207
+ .uleb128 0x25
5208
+ .4byte .LASF251
5209
+ .byte 0x5d
5210
+ .uleb128 0x25
5211
+ .4byte .LASF252
5212
+ .byte 0x5e
5213
+ .uleb128 0x25
5214
+ .4byte .LASF253
5215
+ .byte 0x5f
5216
+ .uleb128 0x25
5217
+ .4byte .LASF254
5218
+ .byte 0x60
5219
+ .uleb128 0x25
5220
+ .4byte .LASF255
5221
+ .byte 0x61
5222
+ .uleb128 0x26
5223
+ .4byte .LASF256
5224
+ .sleb128 -1
5225
+ .byte 0
5226
+ .uleb128 0x27
5227
+ .byte 0x4
5228
+ .4byte 0x7f
5229
+ .byte 0x23
5230
+ .byte 0xf6
5231
+ .4byte 0xc22
5232
+ .uleb128 0x25
5233
+ .4byte .LASF257
5234
+ .byte 0x5
5235
+ .byte 0
5236
+ .uleb128 0xd
5237
+ .4byte .LASF258
5238
+ .byte 0x40
5239
+ .byte 0x14
5240
+ .byte 0xc
5241
+ .4byte 0xc9b
5242
+ .uleb128 0xe
5243
+ .4byte .LASF259
5244
+ .byte 0x14
5245
+ .byte 0x22
5246
+ .4byte 0x3b
5247
+ .byte 0
5248
+ .uleb128 0xf
5249
+ .string "tbu"
5250
+ .byte 0x14
5251
+ .byte 0x23
5252
+ .4byte 0x7f
5253
+ .byte 0x8
5254
+ .uleb128 0xf
5255
+ .string "tbl"
5256
+ .byte 0x14
5257
+ .byte 0x24
5258
+ .4byte 0x7f
5259
+ .byte 0xc
5260
+ .uleb128 0xe
5261
+ .4byte .LASF260
5262
+ .byte 0x14
5263
+ .byte 0x25
5264
+ .4byte 0x3b
5265
+ .byte 0x10
5266
+ .uleb128 0xe
5267
+ .4byte .LASF261
5268
+ .byte 0x14
5269
+ .byte 0x26
5270
+ .4byte 0x8d
5271
+ .byte 0x18
5272
+ .uleb128 0xe
5273
+ .4byte .LASF262
5274
+ .byte 0x14
5275
+ .byte 0x29
5276
+ .4byte 0x3b
5277
+ .byte 0x20
5278
+ .uleb128 0xe
5279
+ .4byte .LASF263
5280
+ .byte 0x14
5281
+ .byte 0x2a
5282
+ .4byte 0x3b
5283
+ .byte 0x28
5284
+ .uleb128 0xe
5285
+ .4byte .LASF264
5286
+ .byte 0x14
5287
+ .byte 0x2c
5288
+ .4byte 0x3b
5289
+ .byte 0x30
5290
+ .uleb128 0xe
5291
+ .4byte .LASF265
5292
+ .byte 0x14
5293
+ .byte 0x2d
5294
+ .4byte 0x3b
5295
+ .byte 0x38
5296
+ .byte 0
5297
+ .uleb128 0xd
5298
+ .4byte .LASF266
5299
+ .byte 0x18
5300
+ .byte 0x15
5301
+ .byte 0x22
5302
+ .4byte 0xce3
5303
+ .uleb128 0xe
5304
+ .4byte .LASF267
5305
+ .byte 0x15
5306
+ .byte 0x23
5307
+ .4byte 0xae
5308
+ .byte 0
5309
+ .uleb128 0xe
5310
+ .4byte .LASF268
5311
+ .byte 0x15
5312
+ .byte 0x24
5313
+ .4byte 0xae
5314
+ .byte 0x4
5315
+ .uleb128 0xf
5316
+ .string "id"
5317
+ .byte 0x15
5318
+ .byte 0x25
5319
+ .4byte 0xae
5320
+ .byte 0x8
5321
+ .uleb128 0xe
5322
+ .4byte .LASF269
5323
+ .byte 0x15
5324
+ .byte 0x26
5325
+ .4byte 0xae
5326
+ .byte 0xc
5327
+ .uleb128 0xe
5328
+ .4byte .LASF270
5329
+ .byte 0x15
5330
+ .byte 0x27
5331
+ .4byte 0x10b
5332
+ .byte 0x10
5333
+ .byte 0
5334
+ .uleb128 0x19
5335
+ .4byte .LASF271
5336
+ .2byte 0x1c0
5337
+ .byte 0x15
5338
+ .byte 0x2a
5339
+ .4byte 0xf0c
5340
+ .uleb128 0xf
5341
+ .string "bd"
5342
+ .byte 0x15
5343
+ .byte 0x2b
5344
+ .4byte 0x97d
5345
+ .byte 0
5346
+ .uleb128 0xe
5347
+ .4byte .LASF42
5348
+ .byte 0x15
5349
+ .byte 0x2c
5350
+ .4byte 0x3b
5351
+ .byte 0x8
5352
+ .uleb128 0xe
5353
+ .4byte .LASF269
5354
+ .byte 0x15
5355
+ .byte 0x2d
5356
+ .4byte 0x7f
5357
+ .byte 0x10
5358
+ .uleb128 0xe
5359
+ .4byte .LASF272
5360
+ .byte 0x15
5361
+ .byte 0x2e
5362
+ .4byte 0x3b
5363
+ .byte 0x18
5364
+ .uleb128 0xe
5365
+ .4byte .LASF273
5366
+ .byte 0x15
5367
+ .byte 0x2f
5368
+ .4byte 0x3b
5369
+ .byte 0x20
5370
+ .uleb128 0xe
5371
+ .4byte .LASF274
5372
+ .byte 0x15
5373
+ .byte 0x31
5374
+ .4byte 0x3b
5375
+ .byte 0x28
5376
+ .uleb128 0xe
5377
+ .4byte .LASF275
5378
+ .byte 0x15
5379
+ .byte 0x32
5380
+ .4byte 0x3b
5381
+ .byte 0x30
5382
+ .uleb128 0xe
5383
+ .4byte .LASF276
5384
+ .byte 0x15
5385
+ .byte 0x3e
5386
+ .4byte 0x3b
5387
+ .byte 0x38
5388
+ .uleb128 0xe
5389
+ .4byte .LASF277
5390
+ .byte 0x15
5391
+ .byte 0x42
5392
+ .4byte 0x3b
5393
+ .byte 0x40
5394
+ .uleb128 0xe
5395
+ .4byte .LASF278
5396
+ .byte 0x15
5397
+ .byte 0x43
5398
+ .4byte 0x3b
5399
+ .byte 0x48
5400
+ .uleb128 0xe
5401
+ .4byte .LASF279
5402
+ .byte 0x15
5403
+ .byte 0x45
5404
+ .4byte 0x3b
5405
+ .byte 0x50
5406
+ .uleb128 0xe
5407
+ .4byte .LASF280
5408
+ .byte 0x15
5409
+ .byte 0x46
5410
+ .4byte 0x3b
5411
+ .byte 0x58
5412
+ .uleb128 0xe
5413
+ .4byte .LASF281
5414
+ .byte 0x15
5415
+ .byte 0x47
5416
+ .4byte 0x3b
5417
+ .byte 0x60
5418
+ .uleb128 0xe
5419
+ .4byte .LASF282
5420
+ .byte 0x15
5421
+ .byte 0x48
5422
+ .4byte 0xcf
5423
+ .byte 0x68
5424
+ .uleb128 0xe
5425
+ .4byte .LASF283
5426
+ .byte 0x15
5427
+ .byte 0x49
5428
+ .4byte 0x3b
5429
+ .byte 0x70
5430
+ .uleb128 0xe
5431
+ .4byte .LASF284
5432
+ .byte 0x15
5433
+ .byte 0x4a
5434
+ .4byte 0x3b
5435
+ .byte 0x78
5436
+ .uleb128 0xe
5437
+ .4byte .LASF285
5438
+ .byte 0x15
5439
+ .byte 0x4b
5440
+ .4byte 0x3b
5441
+ .byte 0x80
5442
+ .uleb128 0xe
5443
+ .4byte .LASF286
5444
+ .byte 0x15
5445
+ .byte 0x4c
5446
+ .4byte 0x3b
5447
+ .byte 0x88
5448
+ .uleb128 0xe
5449
+ .4byte .LASF287
5450
+ .byte 0x15
5451
+ .byte 0x4d
5452
+ .4byte 0xf0c
5453
+ .byte 0x90
5454
+ .uleb128 0xe
5455
+ .4byte .LASF288
5456
+ .byte 0x15
5457
+ .byte 0x50
5458
+ .4byte 0x25f
5459
+ .byte 0x98
5460
+ .uleb128 0xe
5461
+ .4byte .LASF289
5462
+ .byte 0x15
5463
+ .byte 0x51
5464
+ .4byte 0x25f
5465
+ .byte 0xa0
5466
+ .uleb128 0xe
5467
+ .4byte .LASF290
5468
+ .byte 0x15
5469
+ .byte 0x52
5470
+ .4byte 0x292
5471
+ .byte 0xa8
5472
+ .uleb128 0xe
5473
+ .4byte .LASF291
5474
+ .byte 0x15
5475
+ .byte 0x57
5476
+ .4byte 0x265
5477
+ .byte 0xb8
5478
+ .uleb128 0xe
5479
+ .4byte .LASF292
5480
+ .byte 0x15
5481
+ .byte 0x58
5482
+ .4byte 0x137
5483
+ .byte 0xc0
5484
+ .uleb128 0xe
5485
+ .4byte .LASF293
5486
+ .byte 0x15
5487
+ .byte 0x59
5488
+ .4byte 0x3b
5489
+ .byte 0xc8
5490
+ .uleb128 0xe
5491
+ .4byte .LASF294
5492
+ .byte 0x15
5493
+ .byte 0x5b
5494
+ .4byte 0xf84
5495
+ .byte 0xd0
5496
+ .uleb128 0xe
5497
+ .4byte .LASF295
5498
+ .byte 0x15
5499
+ .byte 0x5c
5500
+ .4byte 0xf84
5501
+ .byte 0xd8
5502
+ .uleb128 0xe
5503
+ .4byte .LASF296
5504
+ .byte 0x15
5505
+ .byte 0x5e
5506
+ .4byte 0x265
5507
+ .byte 0xe0
5508
+ .uleb128 0xe
5509
+ .4byte .LASF297
5510
+ .byte 0x15
5511
+ .byte 0x5f
5512
+ .4byte 0x265
5513
+ .byte 0xe8
5514
+ .uleb128 0xf
5515
+ .string "jt"
5516
+ .byte 0x15
5517
+ .byte 0x60
5518
+ .4byte 0xf8f
5519
+ .byte 0xf0
5520
+ .uleb128 0xe
5521
+ .4byte .LASF298
5522
+ .byte 0x15
5523
+ .byte 0x61
5524
+ .4byte 0xf95
5525
+ .byte 0xf8
5526
+ .uleb128 0x15
5527
+ .4byte .LASF299
5528
+ .byte 0x15
5529
+ .byte 0x6b
5530
+ .4byte 0x7f
5531
+ .2byte 0x118
5532
+ .uleb128 0x15
5533
+ .4byte .LASF300
5534
+ .byte 0x15
5535
+ .byte 0x6c
5536
+ .4byte 0x7f
5537
+ .2byte 0x11c
5538
+ .uleb128 0x15
5539
+ .4byte .LASF301
5540
+ .byte 0x15
5541
+ .byte 0x6e
5542
+ .4byte 0x3b
5543
+ .2byte 0x120
5544
+ .uleb128 0x15
5545
+ .4byte .LASF302
5546
+ .byte 0x15
5547
+ .byte 0x6f
5548
+ .4byte 0x3b
5549
+ .2byte 0x128
5550
+ .uleb128 0x15
5551
+ .4byte .LASF303
5552
+ .byte 0x15
5553
+ .byte 0x70
5554
+ .4byte 0x3b
5555
+ .2byte 0x130
5556
+ .uleb128 0x15
5557
+ .4byte .LASF304
5558
+ .byte 0x15
5559
+ .byte 0x79
5560
+ .4byte 0x25f
5561
+ .2byte 0x138
5562
+ .uleb128 0x15
5563
+ .4byte .LASF127
5564
+ .byte 0x15
5565
+ .byte 0x7a
5566
+ .4byte 0xc22
5567
+ .2byte 0x140
5568
+ .uleb128 0x15
5569
+ .4byte .LASF305
5570
+ .byte 0x15
5571
+ .byte 0x80
5572
+ .4byte 0x10b
5573
+ .2byte 0x180
5574
+ .uleb128 0x15
5575
+ .4byte .LASF306
5576
+ .byte 0x15
5577
+ .byte 0x81
5578
+ .4byte 0x10b
5579
+ .2byte 0x188
5580
+ .uleb128 0x15
5581
+ .4byte .LASF307
5582
+ .byte 0x15
5583
+ .byte 0x87
5584
+ .4byte 0xc4
5585
+ .2byte 0x190
5586
+ .uleb128 0x15
5587
+ .4byte .LASF308
5588
+ .byte 0x15
5589
+ .byte 0x8c
5590
+ .4byte 0xc9b
5591
+ .2byte 0x198
5592
+ .uleb128 0x15
5593
+ .4byte .LASF309
5594
+ .byte 0x15
5595
+ .byte 0x8d
5596
+ .4byte 0x10b
5597
+ .2byte 0x1b0
5598
+ .uleb128 0x15
5599
+ .4byte .LASF310
5600
+ .byte 0x15
5601
+ .byte 0x8e
5602
+ .4byte 0x54
5603
+ .2byte 0x1b8
5604
+ .byte 0
5605
+ .uleb128 0x8
5606
+ .byte 0x8
5607
+ .4byte 0xce3
5608
+ .uleb128 0xd
5609
+ .4byte .LASF311
5610
+ .byte 0x40
5611
+ .byte 0x16
5612
+ .byte 0x2c
5613
+ .4byte 0xf7f
5614
+ .uleb128 0xe
5615
+ .4byte .LASF28
5616
+ .byte 0x16
5617
+ .byte 0x2d
5618
+ .4byte 0xe1
5619
+ .byte 0
5620
+ .uleb128 0xe
5621
+ .4byte .LASF126
5622
+ .byte 0x16
5623
+ .byte 0x2e
5624
+ .4byte 0xe1
5625
+ .byte 0x8
5626
+ .uleb128 0xe
5627
+ .4byte .LASF312
5628
+ .byte 0x16
5629
+ .byte 0x2f
5630
+ .4byte 0x12b8
5631
+ .byte 0x10
5632
+ .uleb128 0xe
5633
+ .4byte .LASF313
5634
+ .byte 0x16
5635
+ .byte 0x30
5636
+ .4byte 0xe1
5637
+ .byte 0x18
5638
+ .uleb128 0xe
5639
+ .4byte .LASF314
5640
+ .byte 0x16
5641
+ .byte 0x32
5642
+ .4byte 0x1300
5643
+ .byte 0x20
5644
+ .uleb128 0xe
5645
+ .4byte .LASF34
5646
+ .byte 0x16
5647
+ .byte 0x33
5648
+ .4byte 0xf84
5649
+ .byte 0x28
5650
+ .uleb128 0xe
5651
+ .4byte .LASF315
5652
+ .byte 0x16
5653
+ .byte 0x34
5654
+ .4byte 0xf84
5655
+ .byte 0x30
5656
+ .uleb128 0xe
5657
+ .4byte .LASF316
5658
+ .byte 0x16
5659
+ .byte 0x35
5660
+ .4byte 0xf84
5661
+ .byte 0x38
5662
+ .byte 0
5663
+ .uleb128 0x7
5664
+ .4byte 0xf12
5665
+ .uleb128 0x8
5666
+ .byte 0x8
5667
+ .4byte 0xf12
5668
+ .uleb128 0x18
5669
+ .4byte .LASF318
5670
+ .uleb128 0x8
5671
+ .byte 0x8
5672
+ .4byte 0xf8a
5673
+ .uleb128 0xa
5674
+ .4byte 0xe7
5675
+ .4byte 0xfa5
5676
+ .uleb128 0x11
5677
+ .4byte 0xda
5678
+ .byte 0x1f
5679
+ .byte 0
5680
+ .uleb128 0x2
5681
+ .4byte .LASF319
5682
+ .byte 0x15
5683
+ .byte 0x9b
5684
+ .4byte 0xce3
5685
+ .uleb128 0x28
5686
+ .4byte 0xfa5
5687
+ .uleb128 0x4
5688
+ .4byte .LASF320
5689
+ .byte 0x2
5690
+ .byte 0xad
5691
+ .4byte 0x10b
5692
+ .uleb128 0xa
5693
+ .4byte 0x94
5694
+ .4byte 0xfcb
5695
+ .uleb128 0xb
5696
+ .byte 0
5697
+ .uleb128 0x4
5698
+ .4byte .LASF321
5699
+ .byte 0x2
5700
+ .byte 0xaf
5701
+ .4byte 0xfc0
5702
+ .uleb128 0x4
5703
+ .4byte .LASF322
5704
+ .byte 0x2
5705
+ .byte 0xb0
5706
+ .4byte 0xfc0
5707
+ .uleb128 0x4
5708
+ .4byte .LASF323
5709
+ .byte 0x2
5710
+ .byte 0xfe
5711
+ .4byte 0x10b
5712
+ .uleb128 0x4
5713
+ .4byte .LASF324
5714
+ .byte 0x2
5715
+ .byte 0xff
5716
+ .4byte 0x10b
5717
+ .uleb128 0xc
5718
+ .4byte .LASF325
5719
+ .byte 0x2
5720
+ .2byte 0x100
5721
+ .4byte 0x10b
5722
+ .uleb128 0xd
5723
+ .4byte .LASF326
5724
+ .byte 0x4
5725
+ .byte 0x17
5726
+ .byte 0x2e
5727
+ .4byte 0x101c
5728
+ .uleb128 0xe
5729
+ .4byte .LASF327
5730
+ .byte 0x17
5731
+ .byte 0x2f
5732
+ .4byte 0x12c
5733
+ .byte 0
5734
+ .byte 0
5735
+ .uleb128 0x8
5736
+ .byte 0x8
5737
+ .4byte 0x29
5738
+ .uleb128 0x12
5739
+ .4byte 0x54
5740
+ .4byte 0x1031
5741
+ .uleb128 0x13
5742
+ .4byte 0x25f
5743
+ .byte 0
5744
+ .uleb128 0x8
5745
+ .byte 0x8
5746
+ .4byte 0x1022
5747
+ .uleb128 0xa
5748
+ .4byte 0x94
5749
+ .4byte 0x1047
5750
+ .uleb128 0x11
5751
+ .4byte 0xda
5752
+ .byte 0x5
5753
+ .byte 0
5754
+ .uleb128 0xc
5755
+ .4byte .LASF328
5756
+ .byte 0x17
5757
+ .2byte 0x1fd
5758
+ .4byte 0x1003
5759
+ .uleb128 0xc
5760
+ .4byte .LASF329
5761
+ .byte 0x17
5762
+ .2byte 0x1fe
5763
+ .4byte 0x1003
5764
+ .uleb128 0xc
5765
+ .4byte .LASF330
5766
+ .byte 0x17
5767
+ .2byte 0x200
5768
+ .4byte 0x1003
5769
+ .uleb128 0xc
5770
+ .4byte .LASF331
5771
+ .byte 0x17
5772
+ .2byte 0x205
5773
+ .4byte 0xf95
5774
+ .uleb128 0xc
5775
+ .4byte .LASF332
5776
+ .byte 0x17
5777
+ .2byte 0x206
5778
+ .4byte 0xf95
5779
+ .uleb128 0xa
5780
+ .4byte 0xe7
5781
+ .4byte 0x1093
5782
+ .uleb128 0x11
5783
+ .4byte 0xda
5784
+ .byte 0x3f
5785
+ .byte 0
5786
+ .uleb128 0xc
5787
+ .4byte .LASF333
5788
+ .byte 0x17
5789
+ .2byte 0x207
5790
+ .4byte 0x1083
5791
+ .uleb128 0xc
5792
+ .4byte .LASF334
5793
+ .byte 0x17
5794
+ .2byte 0x209
5795
+ .4byte 0x1037
5796
+ .uleb128 0xc
5797
+ .4byte .LASF335
5798
+ .byte 0x17
5799
+ .2byte 0x20a
5800
+ .4byte 0x1037
5801
+ .uleb128 0xc
5802
+ .4byte .LASF336
5803
+ .byte 0x17
5804
+ .2byte 0x20b
5805
+ .4byte 0x1003
5806
+ .uleb128 0xc
5807
+ .4byte .LASF337
5808
+ .byte 0x17
5809
+ .2byte 0x20c
5810
+ .4byte 0x1003
5811
+ .uleb128 0xc
5812
+ .4byte .LASF338
5813
+ .byte 0x17
5814
+ .2byte 0x20d
5815
+ .4byte 0x101c
5816
+ .uleb128 0xa
5817
+ .4byte 0x101c
5818
+ .4byte 0x10eb
5819
+ .uleb128 0x11
5820
+ .4byte 0xda
5821
+ .byte 0x3
5822
+ .byte 0
5823
+ .uleb128 0xc
5824
+ .4byte .LASF339
5825
+ .byte 0x17
5826
+ .2byte 0x20e
5827
+ .4byte 0x10db
5828
+ .uleb128 0xc
5829
+ .4byte .LASF340
5830
+ .byte 0x17
5831
+ .2byte 0x20f
5832
+ .4byte 0x101c
5833
+ .uleb128 0xc
5834
+ .4byte .LASF341
5835
+ .byte 0x17
5836
+ .2byte 0x210
5837
+ .4byte 0x54
5838
+ .uleb128 0xa
5839
+ .4byte 0x9e
5840
+ .4byte 0x111f
5841
+ .uleb128 0x11
5842
+ .4byte 0xda
5843
+ .byte 0x5
5844
+ .byte 0
5845
+ .uleb128 0x7
5846
+ .4byte 0x110f
5847
+ .uleb128 0xc
5848
+ .4byte .LASF342
5849
+ .byte 0x17
5850
+ .2byte 0x211
5851
+ .4byte 0x111f
5852
+ .uleb128 0xc
5853
+ .4byte .LASF343
5854
+ .byte 0x17
5855
+ .2byte 0x212
5856
+ .4byte 0x111f
5857
+ .uleb128 0xc
5858
+ .4byte .LASF344
5859
+ .byte 0x17
5860
+ .2byte 0x216
5861
+ .4byte 0x100
5862
+ .uleb128 0xc
5863
+ .4byte .LASF345
5864
+ .byte 0x17
5865
+ .2byte 0x217
5866
+ .4byte 0x100
5867
+ .uleb128 0xc
5868
+ .4byte .LASF346
5869
+ .byte 0x17
5870
+ .2byte 0x219
5871
+ .4byte 0x54
5872
+ .uleb128 0xc
5873
+ .4byte .LASF347
5874
+ .byte 0x17
5875
+ .2byte 0x220
5876
+ .4byte 0x99b
5877
+ .uleb128 0xc
5878
+ .4byte .LASF348
5879
+ .byte 0x17
5880
+ .2byte 0x222
5881
+ .4byte 0xae
5882
+ .uleb128 0xc
5883
+ .4byte .LASF349
5884
+ .byte 0x17
5885
+ .2byte 0x224
5886
+ .4byte 0xae
5887
+ .uleb128 0xc
5888
+ .4byte .LASF350
5889
+ .byte 0x17
5890
+ .2byte 0x230
5891
+ .4byte 0x1003
5892
+ .uleb128 0x29
5893
+ .4byte .LASF352
5894
+ .byte 0x4
5895
+ .4byte 0x7f
5896
+ .byte 0x17
5897
+ .2byte 0x286
5898
+ .4byte 0x11ba
5899
+ .uleb128 0x25
5900
+ .4byte .LASF353
5901
+ .byte 0
5902
+ .uleb128 0x25
5903
+ .4byte .LASF354
5904
+ .byte 0x1
5905
+ .uleb128 0x25
5906
+ .4byte .LASF355
5907
+ .byte 0x2
5908
+ .uleb128 0x25
5909
+ .4byte .LASF356
5910
+ .byte 0x3
5911
+ .byte 0
5912
+ .uleb128 0xc
5913
+ .4byte .LASF357
5914
+ .byte 0x17
5915
+ .2byte 0x28c
5916
+ .4byte 0x1190
5917
+ .uleb128 0x8
5918
+ .byte 0x8
5919
+ .4byte 0x94
5920
+ .uleb128 0x8
5921
+ .byte 0x8
5922
+ .4byte 0xa3
5923
+ .uleb128 0x8
5924
+ .byte 0x8
5925
+ .4byte 0xae
5926
+ .uleb128 0xd
5927
+ .4byte .LASF27
5928
+ .byte 0x78
5929
+ .byte 0x8
5930
+ .byte 0xf1
5931
+ .4byte 0x12b3
5932
+ .uleb128 0xe
5933
+ .4byte .LASF28
5934
+ .byte 0x8
5935
+ .byte 0xf2
5936
+ .4byte 0xfa
5937
+ .byte 0
5938
+ .uleb128 0xf
5939
+ .string "id"
5940
+ .byte 0x8
5941
+ .byte 0xf3
5942
+ .4byte 0x9ac
5943
+ .byte 0x8
5944
+ .uleb128 0xe
5945
+ .4byte .LASF358
5946
+ .byte 0x8
5947
+ .byte 0xf4
5948
+ .4byte 0x1416
5949
+ .byte 0x10
5950
+ .uleb128 0xe
5951
+ .4byte .LASF359
5952
+ .byte 0x8
5953
+ .byte 0xf5
5954
+ .4byte 0x1031
5955
+ .byte 0x18
5956
+ .uleb128 0xe
5957
+ .4byte .LASF360
5958
+ .byte 0x8
5959
+ .byte 0xf6
5960
+ .4byte 0x1031
5961
+ .byte 0x20
5962
+ .uleb128 0xe
5963
+ .4byte .LASF361
5964
+ .byte 0x8
5965
+ .byte 0xf7
5966
+ .4byte 0x1031
5967
+ .byte 0x28
5968
+ .uleb128 0xe
5969
+ .4byte .LASF362
5970
+ .byte 0x8
5971
+ .byte 0xf8
5972
+ .4byte 0x1031
5973
+ .byte 0x30
5974
+ .uleb128 0xe
5975
+ .4byte .LASF363
5976
+ .byte 0x8
5977
+ .byte 0xf9
5978
+ .4byte 0x1031
5979
+ .byte 0x38
5980
+ .uleb128 0xe
5981
+ .4byte .LASF364
5982
+ .byte 0x8
5983
+ .byte 0xfa
5984
+ .4byte 0x1031
5985
+ .byte 0x40
5986
+ .uleb128 0xe
5987
+ .4byte .LASF365
5988
+ .byte 0x8
5989
+ .byte 0xfb
5990
+ .4byte 0x1031
5991
+ .byte 0x48
5992
+ .uleb128 0xe
5993
+ .4byte .LASF366
5994
+ .byte 0x8
5995
+ .byte 0xfc
5996
+ .4byte 0x1031
5997
+ .byte 0x50
5998
+ .uleb128 0xe
5999
+ .4byte .LASF367
6000
+ .byte 0x8
6001
+ .byte 0xfd
6002
+ .4byte 0x54
6003
+ .byte 0x58
6004
+ .uleb128 0xe
6005
+ .4byte .LASF368
6006
+ .byte 0x8
6007
+ .byte 0xfe
6008
+ .4byte 0x54
6009
+ .byte 0x5c
6010
+ .uleb128 0xe
6011
+ .4byte .LASF369
6012
+ .byte 0x8
6013
+ .byte 0xff
6014
+ .4byte 0x54
6015
+ .byte 0x60
6016
+ .uleb128 0x1e
6017
+ .4byte .LASF370
6018
+ .byte 0x8
6019
+ .2byte 0x100
6020
+ .4byte 0x54
6021
+ .byte 0x64
6022
+ .uleb128 0x20
6023
+ .string "ops"
6024
+ .byte 0x8
6025
+ .2byte 0x101
6026
+ .4byte 0x265
6027
+ .byte 0x68
6028
+ .uleb128 0x1e
6029
+ .4byte .LASF42
6030
+ .byte 0x8
6031
+ .2byte 0x102
6032
+ .4byte 0x121
6033
+ .byte 0x70
6034
+ .byte 0
6035
+ .uleb128 0x7
6036
+ .4byte 0x11d8
6037
+ .uleb128 0x2
6038
+ .4byte .LASF312
6039
+ .byte 0x16
6040
+ .byte 0xf
6041
+ .4byte 0xae
6042
+ .uleb128 0xd
6043
+ .4byte .LASF371
6044
+ .byte 0x20
6045
+ .byte 0x16
6046
+ .byte 0x19
6047
+ .4byte 0x1300
6048
+ .uleb128 0xe
6049
+ .4byte .LASF28
6050
+ .byte 0x16
6051
+ .byte 0x1a
6052
+ .4byte 0xfa
6053
+ .byte 0
6054
+ .uleb128 0xe
6055
+ .4byte .LASF372
6056
+ .byte 0x16
6057
+ .byte 0x1b
6058
+ .4byte 0x54
6059
+ .byte 0x8
6060
+ .uleb128 0xe
6061
+ .4byte .LASF373
6062
+ .byte 0x16
6063
+ .byte 0x1c
6064
+ .4byte 0x137
6065
+ .byte 0x10
6066
+ .uleb128 0xe
6067
+ .4byte .LASF47
6068
+ .byte 0x16
6069
+ .byte 0x1d
6070
+ .4byte 0x1300
6071
+ .byte 0x18
6072
+ .byte 0
6073
+ .uleb128 0x8
6074
+ .byte 0x8
6075
+ .4byte 0x12c3
6076
+ .uleb128 0x2a
6077
+ .string "gd"
6078
+ .byte 0x16
6079
+ .byte 0x57
6080
+ .4byte 0x1310
6081
+ .uleb128 0x8
6082
+ .byte 0x8
6083
+ .4byte 0xfb0
6084
+ .uleb128 0x2b
6085
+ .4byte .LASF461
6086
+ .byte 0x8
6087
+ .byte 0x19
6088
+ .byte 0x33
6089
+ .4byte 0x1338
6090
+ .uleb128 0x2c
6091
+ .string "np"
6092
+ .byte 0x19
6093
+ .byte 0x34
6094
+ .4byte 0x1338
6095
+ .uleb128 0x2d
6096
+ .4byte .LASF374
6097
+ .byte 0x19
6098
+ .byte 0x35
6099
+ .4byte 0xf3
6100
+ .byte 0
6101
+ .uleb128 0x8
6102
+ .byte 0x8
6103
+ .4byte 0xf7f
6104
+ .uleb128 0x2
6105
+ .4byte .LASF375
6106
+ .byte 0x19
6107
+ .byte 0x36
6108
+ .4byte 0x1316
6109
+ .uleb128 0xc
6110
+ .4byte .LASF376
6111
+ .byte 0x1a
6112
+ .2byte 0x3ba
6113
+ .4byte 0x10b
6114
+ .uleb128 0xc
6115
+ .4byte .LASF377
6116
+ .byte 0x1a
6117
+ .2byte 0x3bb
6118
+ .4byte 0x10b
6119
+ .uleb128 0xc
6120
+ .4byte .LASF378
6121
+ .byte 0x1a
6122
+ .2byte 0x3bc
6123
+ .4byte 0x10b
6124
+ .uleb128 0xd
6125
+ .4byte .LASF379
6126
+ .byte 0x4
6127
+ .byte 0x1b
6128
+ .byte 0xd
6129
+ .4byte 0x1386
6130
+ .uleb128 0xf
6131
+ .string "pid"
6132
+ .byte 0x1b
6133
+ .byte 0xe
6134
+ .4byte 0x54
6135
+ .byte 0
6136
+ .byte 0
6137
+ .uleb128 0x4
6138
+ .4byte .LASF380
6139
+ .byte 0x1b
6140
+ .byte 0x11
6141
+ .4byte 0x1391
6142
+ .uleb128 0x8
6143
+ .byte 0x8
6144
+ .4byte 0x136d
6145
+ .uleb128 0x8
6146
+ .byte 0x8
6147
+ .4byte 0x12b3
6148
+ .uleb128 0xd
6149
+ .4byte .LASF36
6150
+ .byte 0x38
6151
+ .byte 0x1c
6152
+ .byte 0x23
6153
+ .4byte 0x13e6
6154
+ .uleb128 0xe
6155
+ .4byte .LASF35
6156
+ .byte 0x1c
6157
+ .byte 0x24
6158
+ .4byte 0x137
6159
+ .byte 0
6160
+ .uleb128 0xe
6161
+ .4byte .LASF381
6162
+ .byte 0x1c
6163
+ .byte 0x25
6164
+ .4byte 0x1500
6165
+ .byte 0x8
6166
+ .uleb128 0xe
6167
+ .4byte .LASF382
6168
+ .byte 0x1c
6169
+ .byte 0x26
6170
+ .4byte 0x292
6171
+ .byte 0x10
6172
+ .uleb128 0xe
6173
+ .4byte .LASF41
6174
+ .byte 0x1c
6175
+ .byte 0x27
6176
+ .4byte 0x292
6177
+ .byte 0x20
6178
+ .uleb128 0xe
6179
+ .4byte .LASF383
6180
+ .byte 0x1c
6181
+ .byte 0x29
6182
+ .4byte 0x2b7
6183
+ .byte 0x30
6184
+ .byte 0
6185
+ .uleb128 0x8
6186
+ .byte 0x8
6187
+ .4byte 0x139d
6188
+ .uleb128 0xd
6189
+ .4byte .LASF384
6190
+ .byte 0x10
6191
+ .byte 0x8
6192
+ .byte 0xb8
6193
+ .4byte 0x1411
6194
+ .uleb128 0xe
6195
+ .4byte .LASF385
6196
+ .byte 0x8
6197
+ .byte 0xb9
6198
+ .4byte 0xe1
6199
+ .byte 0
6200
+ .uleb128 0xe
6201
+ .4byte .LASF386
6202
+ .byte 0x8
6203
+ .byte 0xba
6204
+ .4byte 0x10b
6205
+ .byte 0x8
6206
+ .byte 0
6207
+ .uleb128 0x7
6208
+ .4byte 0x13ec
6209
+ .uleb128 0x8
6210
+ .byte 0x8
6211
+ .4byte 0x1411
6212
+ .uleb128 0xd
6213
+ .4byte .LASF387
6214
+ .byte 0x80
6215
+ .byte 0x1c
6216
+ .byte 0x57
6217
+ .4byte 0x1500
6218
+ .uleb128 0xe
6219
+ .4byte .LASF28
6220
+ .byte 0x1c
6221
+ .byte 0x58
6222
+ .4byte 0xe1
6223
+ .byte 0
6224
+ .uleb128 0xf
6225
+ .string "id"
6226
+ .byte 0x1c
6227
+ .byte 0x59
6228
+ .4byte 0x9ac
6229
+ .byte 0x8
6230
+ .uleb128 0xe
6231
+ .4byte .LASF388
6232
+ .byte 0x1c
6233
+ .byte 0x5a
6234
+ .4byte 0x1031
6235
+ .byte 0x10
6236
+ .uleb128 0xe
6237
+ .4byte .LASF389
6238
+ .byte 0x1c
6239
+ .byte 0x5b
6240
+ .4byte 0x1031
6241
+ .byte 0x18
6242
+ .uleb128 0xe
6243
+ .4byte .LASF390
6244
+ .byte 0x1c
6245
+ .byte 0x5c
6246
+ .4byte 0x1031
6247
+ .byte 0x20
6248
+ .uleb128 0xe
6249
+ .4byte .LASF391
6250
+ .byte 0x1c
6251
+ .byte 0x5d
6252
+ .4byte 0x1031
6253
+ .byte 0x28
6254
+ .uleb128 0xe
6255
+ .4byte .LASF392
6256
+ .byte 0x1c
6257
+ .byte 0x5e
6258
+ .4byte 0x1031
6259
+ .byte 0x30
6260
+ .uleb128 0xe
6261
+ .4byte .LASF364
6262
+ .byte 0x1c
6263
+ .byte 0x5f
6264
+ .4byte 0x1031
6265
+ .byte 0x38
6266
+ .uleb128 0xe
6267
+ .4byte .LASF365
6268
+ .byte 0x1c
6269
+ .byte 0x60
6270
+ .4byte 0x1031
6271
+ .byte 0x40
6272
+ .uleb128 0xe
6273
+ .4byte .LASF393
6274
+ .byte 0x1c
6275
+ .byte 0x61
6276
+ .4byte 0x1515
6277
+ .byte 0x48
6278
+ .uleb128 0xe
6279
+ .4byte .LASF394
6280
+ .byte 0x1c
6281
+ .byte 0x62
6282
+ .4byte 0x1515
6283
+ .byte 0x50
6284
+ .uleb128 0xe
6285
+ .4byte .LASF367
6286
+ .byte 0x1c
6287
+ .byte 0x63
6288
+ .4byte 0x54
6289
+ .byte 0x58
6290
+ .uleb128 0xe
6291
+ .4byte .LASF395
6292
+ .byte 0x1c
6293
+ .byte 0x64
6294
+ .4byte 0x54
6295
+ .byte 0x5c
6296
+ .uleb128 0xe
6297
+ .4byte .LASF396
6298
+ .byte 0x1c
6299
+ .byte 0x65
6300
+ .4byte 0x54
6301
+ .byte 0x60
6302
+ .uleb128 0xe
6303
+ .4byte .LASF369
6304
+ .byte 0x1c
6305
+ .byte 0x66
6306
+ .4byte 0x54
6307
+ .byte 0x64
6308
+ .uleb128 0xe
6309
+ .4byte .LASF370
6310
+ .byte 0x1c
6311
+ .byte 0x67
6312
+ .4byte 0x54
6313
+ .byte 0x68
6314
+ .uleb128 0xf
6315
+ .string "ops"
6316
+ .byte 0x1c
6317
+ .byte 0x68
6318
+ .4byte 0x265
6319
+ .byte 0x70
6320
+ .uleb128 0xe
6321
+ .4byte .LASF42
6322
+ .byte 0x1c
6323
+ .byte 0x69
6324
+ .4byte 0x121
6325
+ .byte 0x78
6326
+ .byte 0
6327
+ .uleb128 0x8
6328
+ .byte 0x8
6329
+ .4byte 0x141c
6330
+ .uleb128 0x12
6331
+ .4byte 0x54
6332
+ .4byte 0x1515
6333
+ .uleb128 0x13
6334
+ .4byte 0x13e6
6335
+ .byte 0
6336
+ .uleb128 0x8
6337
+ .byte 0x8
6338
+ .4byte 0x1506
6339
+ .uleb128 0x4
6340
+ .4byte .LASF397
6341
+ .byte 0x1d
6342
+ .byte 0x49
6343
+ .4byte 0x7f
6344
+ .uleb128 0x24
6345
+ .4byte .LASF398
6346
+ .byte 0x4
6347
+ .4byte 0x7f
6348
+ .byte 0x1e
6349
+ .byte 0x15
6350
+ .4byte 0x1555
6351
+ .uleb128 0x25
6352
+ .4byte .LASF399
6353
+ .byte 0x1
6354
+ .uleb128 0x25
6355
+ .4byte .LASF400
6356
+ .byte 0x2
6357
+ .uleb128 0x25
6358
+ .4byte .LASF401
6359
+ .byte 0x4
6360
+ .uleb128 0x25
6361
+ .4byte .LASF402
6362
+ .byte 0x8
6363
+ .uleb128 0x25
6364
+ .4byte .LASF403
6365
+ .byte 0x10
6366
+ .byte 0
6367
+ .uleb128 0xd
6368
+ .4byte .LASF404
6369
+ .byte 0x20
6370
+ .byte 0x1e
6371
+ .byte 0x61
6372
+ .4byte 0x1592
6373
+ .uleb128 0xe
6374
+ .4byte .LASF405
6375
+ .byte 0x1e
6376
+ .byte 0x6b
6377
+ .4byte 0x15b5
6378
+ .byte 0
6379
+ .uleb128 0xe
6380
+ .4byte .LASF406
6381
+ .byte 0x1e
6382
+ .byte 0x75
6383
+ .4byte 0x15d9
6384
+ .byte 0x8
6385
+ .uleb128 0xe
6386
+ .4byte .LASF407
6387
+ .byte 0x1e
6388
+ .byte 0x7f
6389
+ .4byte 0x15f8
6390
+ .byte 0x10
6391
+ .uleb128 0xe
6392
+ .4byte .LASF408
6393
+ .byte 0x1e
6394
+ .byte 0x8c
6395
+ .4byte 0x1626
6396
+ .byte 0x18
6397
+ .byte 0
6398
+ .uleb128 0x7
6399
+ .4byte 0x1555
6400
+ .uleb128 0x12
6401
+ .4byte 0x54
6402
+ .4byte 0x15b5
6403
+ .uleb128 0x13
6404
+ .4byte 0x25f
6405
+ .uleb128 0x13
6406
+ .4byte 0x54
6407
+ .uleb128 0x13
6408
+ .4byte 0x137
6409
+ .uleb128 0x13
6410
+ .4byte 0x54
6411
+ .byte 0
6412
+ .uleb128 0x8
6413
+ .byte 0x8
6414
+ .4byte 0x1597
6415
+ .uleb128 0x12
6416
+ .4byte 0x54
6417
+ .4byte 0x15d9
6418
+ .uleb128 0x13
6419
+ .4byte 0x25f
6420
+ .uleb128 0x13
6421
+ .4byte 0x54
6422
+ .uleb128 0x13
6423
+ .4byte 0x265
6424
+ .uleb128 0x13
6425
+ .4byte 0x54
6426
+ .byte 0
6427
+ .uleb128 0x8
6428
+ .byte 0x8
6429
+ .4byte 0x15bb
6430
+ .uleb128 0x12
6431
+ .4byte 0x54
6432
+ .4byte 0x15f8
6433
+ .uleb128 0x13
6434
+ .4byte 0x25f
6435
+ .uleb128 0x13
6436
+ .4byte 0x3b
6437
+ .uleb128 0x13
6438
+ .4byte 0x137
6439
+ .byte 0
6440
+ .uleb128 0x8
6441
+ .byte 0x8
6442
+ .4byte 0x15df
6443
+ .uleb128 0x12
6444
+ .4byte 0x54
6445
+ .4byte 0x1626
6446
+ .uleb128 0x13
6447
+ .4byte 0x25f
6448
+ .uleb128 0x13
6449
+ .4byte 0x54
6450
+ .uleb128 0x13
6451
+ .4byte 0x137
6452
+ .uleb128 0x13
6453
+ .4byte 0x54
6454
+ .uleb128 0x13
6455
+ .4byte 0x137
6456
+ .uleb128 0x13
6457
+ .4byte 0x54
6458
+ .byte 0
6459
+ .uleb128 0x8
6460
+ .byte 0x8
6461
+ .4byte 0x15fe
6462
+ .uleb128 0xd
6463
+ .4byte .LASF409
6464
+ .byte 0x20
6465
+ .byte 0x1f
6466
+ .byte 0x5e
6467
+ .4byte 0x1669
6468
+ .uleb128 0xe
6469
+ .4byte .LASF60
6470
+ .byte 0x1f
6471
+ .byte 0x5f
6472
+ .4byte 0x137
6473
+ .byte 0
6474
+ .uleb128 0xe
6475
+ .4byte .LASF410
6476
+ .byte 0x1f
6477
+ .byte 0x60
6478
+ .4byte 0x3b
6479
+ .byte 0x8
6480
+ .uleb128 0xe
6481
+ .4byte .LASF411
6482
+ .byte 0x1f
6483
+ .byte 0x61
6484
+ .4byte 0x3b
6485
+ .byte 0x10
6486
+ .uleb128 0xe
6487
+ .4byte .LASF412
6488
+ .byte 0x1f
6489
+ .byte 0x62
6490
+ .4byte 0x3b
6491
+ .byte 0x18
6492
+ .byte 0
6493
+ .uleb128 0xd
6494
+ .4byte .LASF413
6495
+ .byte 0x20
6496
+ .byte 0x1
6497
+ .byte 0xf
6498
+ .4byte 0x16a6
6499
+ .uleb128 0xe
6500
+ .4byte .LASF405
6501
+ .byte 0x1
6502
+ .byte 0x10
6503
+ .4byte 0x15b5
6504
+ .byte 0
6505
+ .uleb128 0xe
6506
+ .4byte .LASF406
6507
+ .byte 0x1
6508
+ .byte 0x11
6509
+ .4byte 0x15d9
6510
+ .byte 0x8
6511
+ .uleb128 0xe
6512
+ .4byte .LASF414
6513
+ .byte 0x1
6514
+ .byte 0x12
6515
+ .4byte 0x16c5
6516
+ .byte 0x10
6517
+ .uleb128 0xe
6518
+ .4byte .LASF415
6519
+ .byte 0x1
6520
+ .byte 0x15
6521
+ .4byte 0x16c5
6522
+ .byte 0x18
6523
+ .byte 0
6524
+ .uleb128 0x7
6525
+ .4byte 0x1669
6526
+ .uleb128 0x2e
6527
+ .4byte 0x16c5
6528
+ .uleb128 0x13
6529
+ .4byte 0x11d2
6530
+ .uleb128 0x13
6531
+ .4byte 0x11d2
6532
+ .uleb128 0x13
6533
+ .4byte 0x3b
6534
+ .uleb128 0x13
6535
+ .4byte 0x54
6536
+ .byte 0
6537
+ .uleb128 0x8
6538
+ .byte 0x8
6539
+ .4byte 0x16ab
6540
+ .uleb128 0x2f
6541
+ .4byte .LASF416
6542
+ .byte 0x1
6543
+ .2byte 0x2c7
6544
+ .4byte 0x1592
6545
+ .uleb128 0x9
6546
+ .byte 0x3
6547
+ .8byte rockchip_secure_otp_ops
6548
+ .uleb128 0x2f
6549
+ .4byte .LASF417
6550
+ .byte 0x1
6551
+ .2byte 0x2dc
6552
+ .4byte 0x16a6
6553
+ .uleb128 0x9
6554
+ .byte 0x3
6555
+ .8byte rk3528_data
6556
+ .uleb128 0xa
6557
+ .4byte 0x1411
6558
+ .4byte 0x1707
6559
+ .uleb128 0x11
6560
+ .4byte 0xda
6561
+ .byte 0x1
6562
+ .byte 0
6563
+ .uleb128 0x7
6564
+ .4byte 0x16f7
6565
+ .uleb128 0x2f
6566
+ .4byte .LASF418
6567
+ .byte 0x1
6568
+ .2byte 0x2e3
6569
+ .4byte 0x1707
6570
+ .uleb128 0x9
6571
+ .byte 0x3
6572
+ .8byte rockchip_otp_ids
6573
+ .uleb128 0x30
6574
+ .4byte .LASF419
6575
+ .byte 0x1
6576
+ .2byte 0x2eb
6577
+ .4byte 0x11d8
6578
+ .uleb128 0x9
6579
+ .byte 0x3
6580
+ .8byte _u_boot_list_2_driver_2_rockchip_secure_otp
6581
+ .uleb128 0x31
6582
+ .4byte .LASF420
6583
+ .byte 0x1
6584
+ .2byte 0x2cd
6585
+ .4byte 0x54
6586
+ .8byte .LFB277
6587
+ .8byte .LFE277-.LFB277
6588
+ .uleb128 0x1
6589
+ .byte 0x9c
6590
+ .4byte 0x1825
6591
+ .uleb128 0x32
6592
+ .string "dev"
6593
+ .byte 0x1
6594
+ .2byte 0x2cd
6595
+ .4byte 0x25f
6596
+ .4byte .LLST14
6597
+ .uleb128 0x33
6598
+ .string "otp"
6599
+ .byte 0x1
6600
+ .2byte 0x2cf
6601
+ .4byte 0x1825
6602
+ .4byte .LLST15
6603
+ .uleb128 0x34
6604
+ .8byte .LVL20
6605
+ .4byte 0x4283
6606
+ .4byte 0x1792
6607
+ .uleb128 0x35
6608
+ .uleb128 0x1
6609
+ .byte 0x50
6610
+ .uleb128 0x2
6611
+ .byte 0x84
6612
+ .sleb128 0
6613
+ .byte 0
6614
+ .uleb128 0x34
6615
+ .8byte .LVL23
6616
+ .4byte 0x428f
6617
+ .4byte 0x17aa
6618
+ .uleb128 0x35
6619
+ .uleb128 0x1
6620
+ .byte 0x50
6621
+ .uleb128 0x2
6622
+ .byte 0x84
6623
+ .sleb128 0
6624
+ .byte 0
6625
+ .uleb128 0x34
6626
+ .8byte .LVL24
6627
+ .4byte 0x429a
6628
+ .4byte 0x17d4
6629
+ .uleb128 0x35
6630
+ .uleb128 0x1
6631
+ .byte 0x50
6632
+ .uleb128 0x2
6633
+ .byte 0x84
6634
+ .sleb128 0
6635
+ .uleb128 0x35
6636
+ .uleb128 0x1
6637
+ .byte 0x51
6638
+ .uleb128 0x9
6639
+ .byte 0x3
6640
+ .8byte .LC0
6641
+ .uleb128 0x35
6642
+ .uleb128 0x1
6643
+ .byte 0x52
6644
+ .uleb128 0x1
6645
+ .byte 0x30
6646
+ .byte 0
6647
+ .uleb128 0x34
6648
+ .8byte .LVL25
6649
+ .4byte 0x429a
6650
+ .4byte 0x17fe
6651
+ .uleb128 0x35
6652
+ .uleb128 0x1
6653
+ .byte 0x50
6654
+ .uleb128 0x2
6655
+ .byte 0x84
6656
+ .sleb128 0
6657
+ .uleb128 0x35
6658
+ .uleb128 0x1
6659
+ .byte 0x51
6660
+ .uleb128 0x9
6661
+ .byte 0x3
6662
+ .8byte .LC1
6663
+ .uleb128 0x35
6664
+ .uleb128 0x1
6665
+ .byte 0x52
6666
+ .uleb128 0x1
6667
+ .byte 0x30
6668
+ .byte 0
6669
+ .uleb128 0x36
6670
+ .8byte .LVL26
6671
+ .4byte 0x429a
6672
+ .uleb128 0x35
6673
+ .uleb128 0x1
6674
+ .byte 0x50
6675
+ .uleb128 0x2
6676
+ .byte 0x84
6677
+ .sleb128 0
6678
+ .uleb128 0x35
6679
+ .uleb128 0x1
6680
+ .byte 0x51
6681
+ .uleb128 0x9
6682
+ .byte 0x3
6683
+ .8byte .LC2
6684
+ .uleb128 0x35
6685
+ .uleb128 0x1
6686
+ .byte 0x52
6687
+ .uleb128 0x1
6688
+ .byte 0x30
6689
+ .byte 0
6690
+ .byte 0
6691
+ .uleb128 0x8
6692
+ .byte 0x8
6693
+ .4byte 0x162c
6694
+ .uleb128 0x31
6695
+ .4byte .LASF421
6696
+ .byte 0x1
6697
+ .2byte 0x2b6
6698
+ .4byte 0x54
6699
+ .8byte .LFB276
6700
+ .8byte .LFE276-.LFB276
6701
+ .uleb128 0x1
6702
+ .byte 0x9c
6703
+ .4byte 0x18ac
6704
+ .uleb128 0x32
6705
+ .string "dev"
6706
+ .byte 0x1
6707
+ .2byte 0x2b6
6708
+ .4byte 0x25f
6709
+ .4byte .LLST1
6710
+ .uleb128 0x37
6711
+ .4byte .LASF422
6712
+ .byte 0x1
6713
+ .2byte 0x2b7
6714
+ .4byte 0x3b
6715
+ .uleb128 0x1
6716
+ .byte 0x51
6717
+ .uleb128 0x38
6718
+ .string "buf"
6719
+ .byte 0x1
6720
+ .2byte 0x2b8
6721
+ .4byte 0x137
6722
+ .uleb128 0x1
6723
+ .byte 0x52
6724
+ .uleb128 0x33
6725
+ .string "ret"
6726
+ .byte 0x1
6727
+ .2byte 0x2ba
6728
+ .4byte 0x54
6729
+ .4byte .LLST2
6730
+ .uleb128 0x39
6731
+ .4byte 0x18ac
6732
+ .8byte .LBB23
6733
+ .8byte .LBE23-.LBB23
6734
+ .byte 0x1
6735
+ .2byte 0x2be
6736
+ .uleb128 0x3a
6737
+ .4byte 0x18bd
6738
+ .4byte .LLST3
6739
+ .byte 0
6740
+ .byte 0
6741
+ .uleb128 0x3b
6742
+ .4byte .LASF430
6743
+ .byte 0x1
6744
+ .2byte 0x2af
6745
+ .4byte 0x54
6746
+ .byte 0x1
6747
+ .4byte 0x18ca
6748
+ .uleb128 0x3c
6749
+ .string "buf"
6750
+ .byte 0x1
6751
+ .2byte 0x2af
6752
+ .4byte 0x11d2
6753
+ .byte 0
6754
+ .uleb128 0x31
6755
+ .4byte .LASF423
6756
+ .byte 0x1
6757
+ .2byte 0x2a7
6758
+ .4byte 0x54
6759
+ .8byte .LFB274
6760
+ .8byte .LFE274-.LFB274
6761
+ .uleb128 0x1
6762
+ .byte 0x9c
6763
+ .4byte 0x197b
6764
+ .uleb128 0x32
6765
+ .string "dev"
6766
+ .byte 0x1
6767
+ .2byte 0x2a7
6768
+ .4byte 0x25f
6769
+ .4byte .LLST4
6770
+ .uleb128 0x3d
6771
+ .4byte .LASF424
6772
+ .byte 0x1
6773
+ .2byte 0x2a7
6774
+ .4byte 0x54
6775
+ .4byte .LLST5
6776
+ .uleb128 0x32
6777
+ .string "buf"
6778
+ .byte 0x1
6779
+ .2byte 0x2a8
6780
+ .4byte 0x265
6781
+ .4byte .LLST6
6782
+ .uleb128 0x3d
6783
+ .4byte .LASF51
6784
+ .byte 0x1
6785
+ .2byte 0x2a8
6786
+ .4byte 0x54
6787
+ .4byte .LLST7
6788
+ .uleb128 0x3e
6789
+ .4byte .LASF425
6790
+ .byte 0x1
6791
+ .2byte 0x2aa
6792
+ .4byte 0x197b
6793
+ .4byte .LLST8
6794
+ .uleb128 0x34
6795
+ .8byte .LVL8
6796
+ .4byte 0x42a5
6797
+ .4byte 0x1954
6798
+ .uleb128 0x35
6799
+ .uleb128 0x1
6800
+ .byte 0x50
6801
+ .uleb128 0x2
6802
+ .byte 0x83
6803
+ .sleb128 0
6804
+ .byte 0
6805
+ .uleb128 0x3f
6806
+ .8byte .LVL12
6807
+ .uleb128 0x35
6808
+ .uleb128 0x1
6809
+ .byte 0x50
6810
+ .uleb128 0x3
6811
+ .byte 0xf3
6812
+ .uleb128 0x1
6813
+ .byte 0x50
6814
+ .uleb128 0x35
6815
+ .uleb128 0x1
6816
+ .byte 0x51
6817
+ .uleb128 0x3
6818
+ .byte 0xf3
6819
+ .uleb128 0x1
6820
+ .byte 0x51
6821
+ .uleb128 0x35
6822
+ .uleb128 0x1
6823
+ .byte 0x52
6824
+ .uleb128 0x3
6825
+ .byte 0xf3
6826
+ .uleb128 0x1
6827
+ .byte 0x52
6828
+ .uleb128 0x35
6829
+ .uleb128 0x1
6830
+ .byte 0x53
6831
+ .uleb128 0x3
6832
+ .byte 0xf3
6833
+ .uleb128 0x1
6834
+ .byte 0x53
6835
+ .byte 0
6836
+ .byte 0
6837
+ .uleb128 0x8
6838
+ .byte 0x8
6839
+ .4byte 0x1669
6840
+ .uleb128 0x31
6841
+ .4byte .LASF426
6842
+ .byte 0x1
6843
+ .2byte 0x29f
6844
+ .4byte 0x54
6845
+ .8byte .LFB273
6846
+ .8byte .LFE273-.LFB273
6847
+ .uleb128 0x1
6848
+ .byte 0x9c
6849
+ .4byte 0x1a32
6850
+ .uleb128 0x32
6851
+ .string "dev"
6852
+ .byte 0x1
6853
+ .2byte 0x29f
6854
+ .4byte 0x25f
6855
+ .4byte .LLST9
6856
+ .uleb128 0x3d
6857
+ .4byte .LASF424
6858
+ .byte 0x1
6859
+ .2byte 0x29f
6860
+ .4byte 0x54
6861
+ .4byte .LLST10
6862
+ .uleb128 0x32
6863
+ .string "buf"
6864
+ .byte 0x1
6865
+ .2byte 0x2a0
6866
+ .4byte 0x137
6867
+ .4byte .LLST11
6868
+ .uleb128 0x3d
6869
+ .4byte .LASF51
6870
+ .byte 0x1
6871
+ .2byte 0x2a0
6872
+ .4byte 0x54
6873
+ .4byte .LLST12
6874
+ .uleb128 0x3e
6875
+ .4byte .LASF425
6876
+ .byte 0x1
6877
+ .2byte 0x2a2
6878
+ .4byte 0x197b
6879
+ .4byte .LLST13
6880
+ .uleb128 0x34
6881
+ .8byte .LVL14
6882
+ .4byte 0x42a5
6883
+ .4byte 0x1a0b
6884
+ .uleb128 0x35
6885
+ .uleb128 0x1
6886
+ .byte 0x50
6887
+ .uleb128 0x2
6888
+ .byte 0x83
6889
+ .sleb128 0
6890
+ .byte 0
6891
+ .uleb128 0x3f
6892
+ .8byte .LVL18
6893
+ .uleb128 0x35
6894
+ .uleb128 0x1
6895
+ .byte 0x50
6896
+ .uleb128 0x3
6897
+ .byte 0xf3
6898
+ .uleb128 0x1
6899
+ .byte 0x50
6900
+ .uleb128 0x35
6901
+ .uleb128 0x1
6902
+ .byte 0x51
6903
+ .uleb128 0x3
6904
+ .byte 0xf3
6905
+ .uleb128 0x1
6906
+ .byte 0x51
6907
+ .uleb128 0x35
6908
+ .uleb128 0x1
6909
+ .byte 0x52
6910
+ .uleb128 0x3
6911
+ .byte 0xf3
6912
+ .uleb128 0x1
6913
+ .byte 0x52
6914
+ .uleb128 0x35
6915
+ .uleb128 0x1
6916
+ .byte 0x53
6917
+ .uleb128 0x3
6918
+ .byte 0xf3
6919
+ .uleb128 0x1
6920
+ .byte 0x53
6921
+ .byte 0
6922
+ .byte 0
6923
+ .uleb128 0x31
6924
+ .4byte .LASF427
6925
+ .byte 0x1
6926
+ .2byte 0x26c
6927
+ .4byte 0x54
6928
+ .8byte .LFB272
6929
+ .8byte .LFE272-.LFB272
6930
+ .uleb128 0x1
6931
+ .byte 0x9c
6932
+ .4byte 0x255e
6933
+ .uleb128 0x32
6934
+ .string "dev"
6935
+ .byte 0x1
6936
+ .2byte 0x26c
6937
+ .4byte 0x25f
6938
+ .4byte .LLST69
6939
+ .uleb128 0x3d
6940
+ .4byte .LASF424
6941
+ .byte 0x1
6942
+ .2byte 0x26c
6943
+ .4byte 0x54
6944
+ .4byte .LLST70
6945
+ .uleb128 0x32
6946
+ .string "buf"
6947
+ .byte 0x1
6948
+ .2byte 0x26c
6949
+ .4byte 0x265
6950
+ .4byte .LLST71
6951
+ .uleb128 0x3d
6952
+ .4byte .LASF51
6953
+ .byte 0x1
6954
+ .2byte 0x26c
6955
+ .4byte 0x54
6956
+ .4byte .LLST72
6957
+ .uleb128 0x33
6958
+ .string "otp"
6959
+ .byte 0x1
6960
+ .2byte 0x26e
6961
+ .4byte 0x1825
6962
+ .4byte .LLST73
6963
+ .uleb128 0x3e
6964
+ .4byte .LASF386
6965
+ .byte 0x1
6966
+ .2byte 0x26f
6967
+ .4byte 0x11cc
6968
+ .4byte .LLST74
6969
+ .uleb128 0x3e
6970
+ .4byte .LASF428
6971
+ .byte 0x1
6972
+ .2byte 0x270
6973
+ .4byte 0xfa
6974
+ .4byte .LLST74
6975
+ .uleb128 0x3e
6976
+ .4byte .LASF429
6977
+ .byte 0x1
6978
+ .2byte 0x271
6979
+ .4byte 0xfa
6980
+ .4byte .LLST76
6981
+ .uleb128 0x33
6982
+ .string "i"
6983
+ .byte 0x1
6984
+ .2byte 0x272
6985
+ .4byte 0x54
6986
+ .4byte .LLST77
6987
+ .uleb128 0x33
6988
+ .string "ret"
6989
+ .byte 0x1
6990
+ .2byte 0x272
6991
+ .4byte 0x54
6992
+ .4byte .LLST78
6993
+ .uleb128 0x40
6994
+ .4byte 0x255e
6995
+ .8byte .LBB244
6996
+ .4byte .Ldebug_ranges0+0x3f0
6997
+ .byte 0x1
6998
+ .2byte 0x294
6999
+ .4byte 0x2430
7000
+ .uleb128 0x3a
7001
+ .4byte 0x2593
7002
+ .4byte .LLST79
7003
+ .uleb128 0x3a
7004
+ .4byte 0x2587
7005
+ .4byte .LLST80
7006
+ .uleb128 0x3a
7007
+ .4byte 0x257b
7008
+ .4byte .LLST81
7009
+ .uleb128 0x3a
7010
+ .4byte 0x256f
7011
+ .4byte .LLST82
7012
+ .uleb128 0x41
7013
+ .4byte .Ldebug_ranges0+0x3f0
7014
+ .uleb128 0x42
7015
+ .4byte 0x259f
7016
+ .4byte .LLST83
7017
+ .uleb128 0x42
7018
+ .4byte 0x25ab
7019
+ .4byte .LLST84
7020
+ .uleb128 0x43
7021
+ .4byte 0x25c4
7022
+ .8byte .L88
7023
+ .uleb128 0x44
7024
+ .4byte 0x25b7
7025
+ .uleb128 0x45
7026
+ .8byte .LBB246
7027
+ .8byte .LBE246-.LBB246
7028
+ .4byte 0x1b76
7029
+ .uleb128 0x42
7030
+ .4byte 0x25d1
7031
+ .4byte .LLST85
7032
+ .byte 0
7033
+ .uleb128 0x45
7034
+ .8byte .LBB247
7035
+ .8byte .LBE247-.LBB247
7036
+ .4byte 0x1b95
7037
+ .uleb128 0x42
7038
+ .4byte 0x25e3
7039
+ .4byte .LLST86
7040
+ .byte 0
7041
+ .uleb128 0x45
7042
+ .8byte .LBB248
7043
+ .8byte .LBE248-.LBB248
7044
+ .4byte 0x1bb4
7045
+ .uleb128 0x42
7046
+ .4byte 0x25f5
7047
+ .4byte .LLST87
7048
+ .byte 0
7049
+ .uleb128 0x45
7050
+ .8byte .LBB249
7051
+ .8byte .LBE249-.LBB249
7052
+ .4byte 0x1bd3
7053
+ .uleb128 0x42
7054
+ .4byte 0x2607
7055
+ .4byte .LLST88
7056
+ .byte 0
7057
+ .uleb128 0x45
7058
+ .8byte .LBB250
7059
+ .8byte .LBE250-.LBB250
7060
+ .4byte 0x1bf2
7061
+ .uleb128 0x42
7062
+ .4byte 0x2619
7063
+ .4byte .LLST89
7064
+ .byte 0
7065
+ .uleb128 0x45
7066
+ .8byte .LBB251
7067
+ .8byte .LBE251-.LBB251
7068
+ .4byte 0x1c11
7069
+ .uleb128 0x42
7070
+ .4byte 0x262b
7071
+ .4byte .LLST90
7072
+ .byte 0
7073
+ .uleb128 0x45
7074
+ .8byte .LBB252
7075
+ .8byte .LBE252-.LBB252
7076
+ .4byte 0x1c30
7077
+ .uleb128 0x42
7078
+ .4byte 0x263d
7079
+ .4byte .LLST91
7080
+ .byte 0
7081
+ .uleb128 0x45
7082
+ .8byte .LBB253
7083
+ .8byte .LBE253-.LBB253
7084
+ .4byte 0x1c4f
7085
+ .uleb128 0x42
7086
+ .4byte 0x264f
7087
+ .4byte .LLST92
7088
+ .byte 0
7089
+ .uleb128 0x45
7090
+ .8byte .LBB254
7091
+ .8byte .LBE254-.LBB254
7092
+ .4byte 0x1c6e
7093
+ .uleb128 0x42
7094
+ .4byte 0x2661
7095
+ .4byte .LLST93
7096
+ .byte 0
7097
+ .uleb128 0x45
7098
+ .8byte .LBB255
7099
+ .8byte .LBE255-.LBB255
7100
+ .4byte 0x1c8d
7101
+ .uleb128 0x42
7102
+ .4byte 0x2673
7103
+ .4byte .LLST94
7104
+ .byte 0
7105
+ .uleb128 0x45
7106
+ .8byte .LBB256
7107
+ .8byte .LBE256-.LBB256
7108
+ .4byte 0x1cac
7109
+ .uleb128 0x42
7110
+ .4byte 0x2685
7111
+ .4byte .LLST95
7112
+ .byte 0
7113
+ .uleb128 0x45
7114
+ .8byte .LBB257
7115
+ .8byte .LBE257-.LBB257
7116
+ .4byte 0x1ccb
7117
+ .uleb128 0x42
7118
+ .4byte 0x2697
7119
+ .4byte .LLST96
7120
+ .byte 0
7121
+ .uleb128 0x45
7122
+ .8byte .LBB258
7123
+ .8byte .LBE258-.LBB258
7124
+ .4byte 0x1cea
7125
+ .uleb128 0x42
7126
+ .4byte 0x26a9
7127
+ .4byte .LLST97
7128
+ .byte 0
7129
+ .uleb128 0x45
7130
+ .8byte .LBB259
7131
+ .8byte .LBE259-.LBB259
7132
+ .4byte 0x1d09
7133
+ .uleb128 0x42
7134
+ .4byte 0x26bb
7135
+ .4byte .LLST98
7136
+ .byte 0
7137
+ .uleb128 0x45
7138
+ .8byte .LBB260
7139
+ .8byte .LBE260-.LBB260
7140
+ .4byte 0x1d28
7141
+ .uleb128 0x42
7142
+ .4byte 0x26cd
7143
+ .4byte .LLST99
7144
+ .byte 0
7145
+ .uleb128 0x45
7146
+ .8byte .LBB261
7147
+ .8byte .LBE261-.LBB261
7148
+ .4byte 0x1d47
7149
+ .uleb128 0x42
7150
+ .4byte 0x26df
7151
+ .4byte .LLST100
7152
+ .byte 0
7153
+ .uleb128 0x45
7154
+ .8byte .LBB262
7155
+ .8byte .LBE262-.LBB262
7156
+ .4byte 0x1d66
7157
+ .uleb128 0x42
7158
+ .4byte 0x26f1
7159
+ .4byte .LLST101
7160
+ .byte 0
7161
+ .uleb128 0x45
7162
+ .8byte .LBB263
7163
+ .8byte .LBE263-.LBB263
7164
+ .4byte 0x1d85
7165
+ .uleb128 0x42
7166
+ .4byte 0x2703
7167
+ .4byte .LLST102
7168
+ .byte 0
7169
+ .uleb128 0x46
7170
+ .4byte .Ldebug_ranges0+0x450
7171
+ .4byte 0x1d98
7172
+ .uleb128 0x42
7173
+ .4byte 0x2715
7174
+ .4byte .LLST103
7175
+ .byte 0
7176
+ .uleb128 0x46
7177
+ .4byte .Ldebug_ranges0+0x480
7178
+ .4byte 0x1dab
7179
+ .uleb128 0x42
7180
+ .4byte 0x2727
7181
+ .4byte .LLST104
7182
+ .byte 0
7183
+ .uleb128 0x46
7184
+ .4byte .Ldebug_ranges0+0x4b0
7185
+ .4byte 0x1dbe
7186
+ .uleb128 0x42
7187
+ .4byte 0x2739
7188
+ .4byte .LLST105
7189
+ .byte 0
7190
+ .uleb128 0x46
7191
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7192
+ .4byte 0x1dd1
7193
+ .uleb128 0x42
7194
+ .4byte 0x2a29
7195
+ .4byte .LLST106
7196
+ .byte 0
7197
+ .uleb128 0x45
7198
+ .8byte .LBB272
7199
+ .8byte .LBE272-.LBB272
7200
+ .4byte 0x1df0
7201
+ .uleb128 0x42
7202
+ .4byte 0x274b
7203
+ .4byte .LLST107
7204
+ .byte 0
7205
+ .uleb128 0x45
7206
+ .8byte .LBB273
7207
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7208
+ .4byte 0x1e0f
7209
+ .uleb128 0x42
7210
+ .4byte 0x275d
7211
+ .4byte .LLST108
7212
+ .byte 0
7213
+ .uleb128 0x45
7214
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7215
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7216
+ .4byte 0x1e2e
7217
+ .uleb128 0x42
7218
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7219
+ .4byte .LLST109
7220
+ .byte 0
7221
+ .uleb128 0x45
7222
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7223
+ .8byte .LBE275-.LBB275
7224
+ .4byte 0x1e4d
7225
+ .uleb128 0x42
7226
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7227
+ .4byte .LLST110
7228
+ .byte 0
7229
+ .uleb128 0x45
7230
+ .8byte .LBB276
7231
+ .8byte .LBE276-.LBB276
7232
+ .4byte 0x1e6c
7233
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7234
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7235
+ .4byte .LLST111
7236
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7237
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7238
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7239
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7240
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7241
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7242
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7243
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7244
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7245
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7246
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7247
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7248
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7249
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7250
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7251
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7252
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7253
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7254
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7255
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7256
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7257
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7258
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7259
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7260
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7261
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7262
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7263
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7264
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7265
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7266
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7267
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7268
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7269
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7270
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7271
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7272
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7273
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7274
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7275
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7276
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7277
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7278
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7279
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7280
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7281
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7282
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7283
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7284
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7285
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7286
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7287
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7288
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7289
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7290
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7291
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7292
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7293
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7294
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7295
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7296
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7297
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7298
+ .4byte 0x2823
7299
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7300
+ .byte 0
7301
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7302
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7303
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7304
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7305
+ .uleb128 0x42
7306
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7307
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7308
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7309
+ .uleb128 0x45
7310
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7311
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7312
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7313
+ .uleb128 0x42
7314
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7315
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7316
+ .byte 0
7317
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7318
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7319
+ .8byte .LBE287-.LBB287
7320
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7321
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7322
+ .4byte 0x2859
7323
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7324
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7325
+ .uleb128 0x46
7326
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7327
+ .4byte 0x1fd4
7328
+ .uleb128 0x42
7329
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7330
+ .4byte .LLST123
7331
+ .byte 0
7332
+ .uleb128 0x45
7333
+ .8byte .LBB290
7334
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7335
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7336
+ .uleb128 0x42
7337
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7338
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7339
+ .byte 0
7340
+ .uleb128 0x45
7341
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7342
+ .8byte .LBE291-.LBB291
7343
+ .4byte 0x2012
7344
+ .uleb128 0x42
7345
+ .4byte 0x288f
7346
+ .4byte .LLST125
7347
+ .byte 0
7348
+ .uleb128 0x45
7349
+ .8byte .LBB292
7350
+ .8byte .LBE292-.LBB292
7351
+ .4byte 0x2031
7352
+ .uleb128 0x42
7353
+ .4byte 0x28a1
7354
+ .4byte .LLST126
7355
+ .byte 0
7356
+ .uleb128 0x45
7357
+ .8byte .LBB293
7358
+ .8byte .LBE293-.LBB293
7359
+ .4byte 0x2050
7360
+ .uleb128 0x42
7361
+ .4byte 0x28b3
7362
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7363
+ .byte 0
7364
+ .uleb128 0x46
7365
+ .4byte .Ldebug_ranges0+0x540
7366
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7367
+ .uleb128 0x42
7368
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7369
+ .4byte .LLST128
7370
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7371
+ .uleb128 0x45
7372
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7373
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7374
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7375
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7376
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7377
+ .4byte .LLST129
7378
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7379
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7380
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7381
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7382
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7383
+ .uleb128 0x42
7384
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7385
+ .4byte .LLST130
7386
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7387
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7388
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7389
+ .4byte 0x20b4
7390
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7391
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7392
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7393
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7394
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7395
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7396
+ .4byte 0x20c7
7397
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7398
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7399
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7400
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7401
+ .uleb128 0x46
7402
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7403
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7404
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7405
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7406
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7407
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7408
+ .uleb128 0x45
7409
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7410
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7411
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7412
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7413
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7414
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7415
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7416
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7417
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7418
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7419
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7420
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7421
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7422
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7423
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7424
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7425
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7426
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7427
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7428
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7429
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7430
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7431
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7432
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7433
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7434
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7435
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7436
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7437
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7438
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7439
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7440
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7441
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7442
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7443
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7444
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7445
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7446
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7447
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7448
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7449
+ .8byte .LBE310-.LBB310
7450
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7451
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7452
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7453
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7454
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7455
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7456
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7457
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7458
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7459
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7460
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7461
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7462
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7463
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7464
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7465
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7466
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7467
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7468
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7469
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7470
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7471
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7472
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7473
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7474
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7475
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7476
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7477
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7478
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7479
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7480
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7481
+ .4byte 0x21f8
7482
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7483
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7484
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7485
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7486
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7487
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7488
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7489
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7490
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7491
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7492
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7493
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7494
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7495
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7496
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7497
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7498
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7499
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7500
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7501
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7502
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7503
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7504
+ .8byte .LBE318-.LBB318
7505
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7506
+ .uleb128 0x42
7507
+ .4byte 0x2a09
7508
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7509
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7510
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7511
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7512
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7513
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7514
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7515
+ .4byte 0x2a1b
7516
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7517
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7518
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7519
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7520
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7521
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7522
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7523
+ .uleb128 0x1
7524
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7525
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7526
+ .byte 0x88
7527
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7528
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7529
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7530
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7531
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7532
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7533
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7534
+ .uleb128 0x1
7535
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7536
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7537
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7538
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7539
+ .uleb128 0x35
7540
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7541
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7542
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7543
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7544
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7545
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7546
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7547
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7548
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7549
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7550
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7551
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7552
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7553
+ .uleb128 0x1
7554
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7555
+ .uleb128 0x2
7556
+ .byte 0x89
7557
+ .sleb128 0
7558
+ .byte 0
7559
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7560
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7561
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7562
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7563
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7564
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7565
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7566
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7567
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7568
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7569
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7570
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7571
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7572
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7573
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7574
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7575
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7576
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7577
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7578
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7579
+ .byte 0
7580
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7581
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7582
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7583
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7584
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7585
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7586
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7587
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7588
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7589
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7590
+ .byte 0x89
7591
+ .sleb128 0
7592
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7593
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7594
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7595
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7596
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7597
+ .uleb128 0x35
7598
+ .uleb128 0x1
7599
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7600
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7601
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7602
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7603
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7604
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7605
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7606
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7607
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7608
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7609
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7610
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7611
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7612
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7613
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7614
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7615
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7616
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7617
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7618
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7619
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7620
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7621
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7622
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7623
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7624
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7625
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7626
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7627
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7628
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7629
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7630
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7631
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7632
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7633
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7634
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7635
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7636
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7637
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7638
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7639
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7640
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7641
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7642
+ .uleb128 0x1
7643
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7644
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7645
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7646
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7647
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7648
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7649
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7650
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7651
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7652
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7653
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7654
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7655
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7656
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7657
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7658
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7659
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7660
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7661
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7662
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7663
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7664
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7665
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7666
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7667
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7668
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7669
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7670
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7671
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7672
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7673
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7674
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7675
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7676
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7677
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7678
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7679
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7680
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7681
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7682
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7683
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7684
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7685
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7686
+ .uleb128 0x1
7687
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7688
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7689
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7690
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7691
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7692
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7693
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7694
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7695
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7696
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7697
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7698
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7699
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7700
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7701
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7702
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7703
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7704
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7705
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7706
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7707
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7708
+ .uleb128 0x1
7709
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7710
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7711
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7712
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7713
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7714
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7715
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7716
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7717
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7718
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7719
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7720
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7721
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7722
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7723
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7724
+ .uleb128 0x1
7725
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7726
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7727
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7728
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7729
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7730
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7731
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7732
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7733
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7734
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7735
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7736
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7737
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7738
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7739
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7740
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7741
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7742
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7743
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7744
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7745
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7746
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7747
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7748
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7749
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7750
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7751
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7752
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7753
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7754
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7755
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7756
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7757
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7758
+ .uleb128 0x40
7759
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7760
+ .8byte .LBB326
7761
+ .4byte .Ldebug_ranges0+0x660
7762
+ .byte 0x1
7763
+ .2byte 0x28c
7764
+ .4byte 0x24d1
7765
+ .uleb128 0x3a
7766
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7767
+ .4byte .LLST148
7768
+ .uleb128 0x3a
7769
+ .4byte 0x2a75
7770
+ .4byte .LLST149
7771
+ .uleb128 0x3a
7772
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7773
+ .4byte .LLST150
7774
+ .uleb128 0x3a
7775
+ .4byte 0x2a5d
7776
+ .4byte .LLST151
7777
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7778
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8397
+ .byte 0x1
8398
+ .2byte 0x244
8399
+ .4byte 0xae
8400
+ .byte 0
8401
+ .uleb128 0x50
8402
+ .4byte 0x29ce
8403
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8404
+ .string "__v"
8405
+ .byte 0x1
8406
+ .2byte 0x245
8407
+ .4byte 0xae
8408
+ .byte 0
8409
+ .uleb128 0x50
8410
+ .4byte 0x29e0
8411
+ .uleb128 0x4c
8412
+ .string "__v"
8413
+ .byte 0x1
8414
+ .2byte 0x246
8415
+ .4byte 0xae
8416
+ .byte 0
8417
+ .uleb128 0x50
8418
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8419
+ .uleb128 0x4c
8420
+ .string "__v"
8421
+ .byte 0x1
8422
+ .2byte 0x253
8423
+ .4byte 0xae
8424
+ .byte 0
8425
+ .uleb128 0x50
8426
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8427
+ .uleb128 0x4c
8428
+ .string "__v"
8429
+ .byte 0x1
8430
+ .2byte 0x254
8431
+ .4byte 0xae
8432
+ .byte 0
8433
+ .uleb128 0x50
8434
+ .4byte 0x2a16
8435
+ .uleb128 0x4c
8436
+ .string "__v"
8437
+ .byte 0x1
8438
+ .2byte 0x255
8439
+ .4byte 0xae
8440
+ .byte 0
8441
+ .uleb128 0x50
8442
+ .4byte 0x2a28
8443
+ .uleb128 0x4c
8444
+ .string "__v"
8445
+ .byte 0x1
8446
+ .2byte 0x256
8447
+ .4byte 0xae
8448
+ .byte 0
8449
+ .uleb128 0x51
8450
+ .uleb128 0x4c
8451
+ .string "__v"
8452
+ .byte 0x1
8453
+ .2byte 0x264
8454
+ .4byte 0xae
8455
+ .byte 0
8456
+ .byte 0
8457
+ .uleb128 0xa
8458
+ .4byte 0xee
8459
+ .4byte 0x2a47
8460
+ .uleb128 0x11
8461
+ .4byte 0xda
8462
+ .byte 0x1f
8463
+ .byte 0
8464
+ .uleb128 0x7
8465
+ .4byte 0x2a37
8466
+ .uleb128 0x3b
8467
+ .4byte .LASF433
8468
+ .byte 0x1
8469
+ .2byte 0x1c0
8470
+ .4byte 0x54
8471
+ .byte 0x1
8472
+ .4byte 0x2ab2
8473
+ .uleb128 0x3c
8474
+ .string "dev"
8475
+ .byte 0x1
8476
+ .2byte 0x1c0
8477
+ .4byte 0x25f
8478
+ .uleb128 0x3c
8479
+ .string "otp"
8480
+ .byte 0x1
8481
+ .2byte 0x1c1
8482
+ .4byte 0x1825
8483
+ .uleb128 0x4b
8484
+ .4byte .LASF424
8485
+ .byte 0x1
8486
+ .2byte 0x1c2
8487
+ .4byte 0x54
8488
+ .uleb128 0x4b
8489
+ .4byte .LASF386
8490
+ .byte 0x1
8491
+ .2byte 0x1c2
8492
+ .4byte 0x94
8493
+ .uleb128 0x4d
8494
+ .4byte .LASF434
8495
+ .byte 0x1
8496
+ .2byte 0x1c4
8497
+ .4byte 0xa3
8498
+ .uleb128 0x4d
8499
+ .4byte .LASF429
8500
+ .byte 0x1
8501
+ .2byte 0x1c4
8502
+ .4byte 0xa3
8503
+ .uleb128 0x4c
8504
+ .string "ret"
8505
+ .byte 0x1
8506
+ .2byte 0x1c5
8507
+ .4byte 0x54
8508
+ .byte 0
8509
+ .uleb128 0x52
8510
+ .4byte .LASF435
8511
+ .byte 0x1
8512
+ .byte 0xed
8513
+ .4byte 0x54
8514
+ .8byte .LFB269
8515
+ .8byte .LFE269-.LFB269
8516
+ .uleb128 0x1
8517
+ .byte 0x9c
8518
+ .4byte 0x39ba
8519
+ .uleb128 0x53
8520
+ .string "dev"
8521
+ .byte 0x1
8522
+ .byte 0xed
8523
+ .4byte 0x25f
8524
+ .4byte .LLST30
8525
+ .uleb128 0x53
8526
+ .string "otp"
8527
+ .byte 0x1
8528
+ .byte 0xee
8529
+ .4byte 0x1825
8530
+ .4byte .LLST31
8531
+ .uleb128 0x54
8532
+ .4byte .LASF424
8533
+ .byte 0x1
8534
+ .byte 0xef
8535
+ .4byte 0x54
8536
+ .4byte .LLST32
8537
+ .uleb128 0x54
8538
+ .4byte .LASF386
8539
+ .byte 0x1
8540
+ .byte 0xef
8541
+ .4byte 0xa3
8542
+ .4byte .LLST33
8543
+ .uleb128 0x55
8544
+ .string "ret"
8545
+ .byte 0x1
8546
+ .byte 0xf1
8547
+ .4byte 0x54
8548
+ .4byte .LLST34
8549
+ .uleb128 0x56
8550
+ .4byte .LASF425
8551
+ .byte 0x1
8552
+ .byte 0xf2
8553
+ .4byte 0x197b
8554
+ .4byte .LLST35
8555
+ .uleb128 0x57
8556
+ .4byte .LASF432
8557
+ .4byte 0x39ca
8558
+ .uleb128 0x9
8559
+ .byte 0x3
8560
+ .8byte __func__.7671
8561
+ .uleb128 0x58
8562
+ .4byte .LASF438
8563
+ .byte 0x1
8564
+ .2byte 0x1b9
8565
+ .8byte .L39
8566
+ .uleb128 0x45
8567
+ .8byte .LBB40
8568
+ .8byte .LBE40-.LBB40
8569
+ .4byte 0x2b76
8570
+ .uleb128 0x33
8571
+ .string "__v"
8572
+ .byte 0x1
8573
+ .2byte 0x106
8574
+ .4byte 0xae
8575
+ .4byte .LLST36
8576
+ .byte 0
8577
+ .uleb128 0x45
8578
+ .8byte .LBB41
8579
+ .8byte .LBE41-.LBB41
8580
+ .4byte 0x2b9c
8581
+ .uleb128 0x33
8582
+ .string "__v"
8583
+ .byte 0x1
8584
+ .2byte 0x107
8585
+ .4byte 0xae
8586
+ .4byte .LLST37
8587
+ .byte 0
8588
+ .uleb128 0x45
8589
+ .8byte .LBB42
8590
+ .8byte .LBE42-.LBB42
8591
+ .4byte 0x2bc2
8592
+ .uleb128 0x33
8593
+ .string "__v"
8594
+ .byte 0x1
8595
+ .2byte 0x108
8596
+ .4byte 0xae
8597
+ .4byte .LLST38
8598
+ .byte 0
8599
+ .uleb128 0x45
8600
+ .8byte .LBB43
8601
+ .8byte .LBE43-.LBB43
8602
+ .4byte 0x2be8
8603
+ .uleb128 0x33
8604
+ .string "__v"
8605
+ .byte 0x1
8606
+ .2byte 0x109
8607
+ .4byte 0xae
8608
+ .4byte .LLST39
8609
+ .byte 0
8610
+ .uleb128 0x45
8611
+ .8byte .LBB44
8612
+ .8byte .LBE44-.LBB44
8613
+ .4byte 0x2c0e
8614
+ .uleb128 0x33
8615
+ .string "__v"
8616
+ .byte 0x1
8617
+ .2byte 0x10a
8618
+ .4byte 0xae
8619
+ .4byte .LLST40
8620
+ .byte 0
8621
+ .uleb128 0x45
8622
+ .8byte .LBB45
8623
+ .8byte .LBE45-.LBB45
8624
+ .4byte 0x2c34
8625
+ .uleb128 0x33
8626
+ .string "__v"
8627
+ .byte 0x1
8628
+ .2byte 0x10b
8629
+ .4byte 0xae
8630
+ .4byte .LLST41
8631
+ .byte 0
8632
+ .uleb128 0x45
8633
+ .8byte .LBB46
8634
+ .8byte .LBE46-.LBB46
8635
+ .4byte 0x2c5a
8636
+ .uleb128 0x33
8637
+ .string "__v"
8638
+ .byte 0x1
8639
+ .2byte 0x10c
8640
+ .4byte 0xae
8641
+ .4byte .LLST42
8642
+ .byte 0
8643
+ .uleb128 0x45
8644
+ .8byte .LBB47
8645
+ .8byte .LBE47-.LBB47
8646
+ .4byte 0x2c80
8647
+ .uleb128 0x33
8648
+ .string "__v"
8649
+ .byte 0x1
8650
+ .2byte 0x10d
8651
+ .4byte 0xae
8652
+ .4byte .LLST43
8653
+ .byte 0
8654
+ .uleb128 0x46
8655
+ .4byte .Ldebug_ranges0+0
8656
+ .4byte 0x2c9a
8657
+ .uleb128 0x33
8658
+ .string "__v"
8659
+ .byte 0x1
8660
+ .2byte 0x10e
8661
+ .4byte 0xae
8662
+ .4byte .LLST44
8663
+ .byte 0
8664
+ .uleb128 0x45
8665
+ .8byte .LBB50
8666
+ .8byte .LBE50-.LBB50
8667
+ .4byte 0x2cbf
8668
+ .uleb128 0x59
8669
+ .string "__v"
8670
+ .byte 0x1
8671
+ .2byte 0x115
8672
+ .4byte 0xae
8673
+ .sleb128 -65522
8674
+ .byte 0
8675
+ .uleb128 0x45
8676
+ .8byte .LBB51
8677
+ .8byte .LBE51-.LBB51
8678
+ .4byte 0x2ce2
8679
+ .uleb128 0x5a
8680
+ .string "__v"
8681
+ .byte 0x1
8682
+ .2byte 0x116
8683
+ .4byte 0xae
8684
+ .byte 0xf0
8685
+ .byte 0
8686
+ .uleb128 0x45
8687
+ .8byte .LBB52
8688
+ .8byte .LBE52-.LBB52
8689
+ .4byte 0x2d05
8690
+ .uleb128 0x5a
8691
+ .string "__v"
8692
+ .byte 0x1
8693
+ .2byte 0x117
8694
+ .4byte 0xae
8695
+ .byte 0x1
8696
+ .byte 0
8697
+ .uleb128 0x45
8698
+ .8byte .LBB53
8699
+ .8byte .LBE53-.LBB53
8700
+ .4byte 0x2d28
8701
+ .uleb128 0x5a
8702
+ .string "__v"
8703
+ .byte 0x1
8704
+ .2byte 0x118
8705
+ .4byte 0xae
8706
+ .byte 0x7a
8707
+ .byte 0
8708
+ .uleb128 0x45
8709
+ .8byte .LBB54
8710
+ .8byte .LBE54-.LBB54
8711
+ .4byte 0x2d4b
8712
+ .uleb128 0x5a
8713
+ .string "__v"
8714
+ .byte 0x1
8715
+ .2byte 0x119
8716
+ .4byte 0xae
8717
+ .byte 0x25
8718
+ .byte 0
8719
+ .uleb128 0x45
8720
+ .8byte .LBB55
8721
+ .8byte .LBE55-.LBB55
8722
+ .4byte 0x2d6e
8723
+ .uleb128 0x5a
8724
+ .string "__v"
8725
+ .byte 0x1
8726
+ .2byte 0x11a
8727
+ .4byte 0xae
8728
+ .byte 0
8729
+ .byte 0
8730
+ .uleb128 0x45
8731
+ .8byte .LBB56
8732
+ .8byte .LBE56-.LBB56
8733
+ .4byte 0x2d91
8734
+ .uleb128 0x5a
8735
+ .string "__v"
8736
+ .byte 0x1
8737
+ .2byte 0x11b
8738
+ .4byte 0xae
8739
+ .byte 0
8740
+ .byte 0
8741
+ .uleb128 0x45
8742
+ .8byte .LBB57
8743
+ .8byte .LBE57-.LBB57
8744
+ .4byte 0x2db4
8745
+ .uleb128 0x5a
8746
+ .string "__v"
8747
+ .byte 0x1
8748
+ .2byte 0x11c
8749
+ .4byte 0xae
8750
+ .byte 0
8751
+ .byte 0
8752
+ .uleb128 0x45
8753
+ .8byte .LBB58
8754
+ .8byte .LBE58-.LBB58
8755
+ .4byte 0x2dd7
8756
+ .uleb128 0x5a
8757
+ .string "__v"
8758
+ .byte 0x1
8759
+ .2byte 0x11d
8760
+ .4byte 0xae
8761
+ .byte 0x1f
8762
+ .byte 0
8763
+ .uleb128 0x45
8764
+ .8byte .LBB59
8765
+ .8byte .LBE59-.LBB59
8766
+ .4byte 0x2dfa
8767
+ .uleb128 0x5a
8768
+ .string "__v"
8769
+ .byte 0x1
8770
+ .2byte 0x11e
8771
+ .4byte 0xae
8772
+ .byte 0xb
8773
+ .byte 0
8774
+ .uleb128 0x45
8775
+ .8byte .LBB60
8776
+ .8byte .LBE60-.LBB60
8777
+ .4byte 0x2e1d
8778
+ .uleb128 0x5a
8779
+ .string "__v"
8780
+ .byte 0x1
8781
+ .2byte 0x11f
8782
+ .4byte 0xae
8783
+ .byte 0x8
8784
+ .byte 0
8785
+ .uleb128 0x45
8786
+ .8byte .LBB61
8787
+ .8byte .LBE61-.LBB61
8788
+ .4byte 0x2e40
8789
+ .uleb128 0x5a
8790
+ .string "__v"
8791
+ .byte 0x1
8792
+ .2byte 0x120
8793
+ .4byte 0xae
8794
+ .byte 0
8795
+ .byte 0
8796
+ .uleb128 0x45
8797
+ .8byte .LBB62
8798
+ .8byte .LBE62-.LBB62
8799
+ .4byte 0x2e63
8800
+ .uleb128 0x5a
8801
+ .string "__v"
8802
+ .byte 0x1
8803
+ .2byte 0x121
8804
+ .4byte 0xae
8805
+ .byte 0
8806
+ .byte 0
8807
+ .uleb128 0x45
8808
+ .8byte .LBB63
8809
+ .8byte .LBE63-.LBB63
8810
+ .4byte 0x2e86
8811
+ .uleb128 0x5a
8812
+ .string "__v"
8813
+ .byte 0x1
8814
+ .2byte 0x122
8815
+ .4byte 0xae
8816
+ .byte 0
8817
+ .byte 0
8818
+ .uleb128 0x46
8819
+ .4byte .Ldebug_ranges0+0x30
8820
+ .4byte 0x2e9e
8821
+ .uleb128 0x5b
8822
+ .string "__v"
8823
+ .byte 0x1
8824
+ .2byte 0x123
8825
+ .4byte 0xae
8826
+ .uleb128 0x1
8827
+ .byte 0x50
8828
+ .byte 0
8829
+ .uleb128 0x46
8830
+ .4byte .Ldebug_ranges0+0x60
8831
+ .4byte 0x2eb8
8832
+ .uleb128 0x33
8833
+ .string "__v"
8834
+ .byte 0x1
8835
+ .2byte 0x124
8836
+ .4byte 0xae
8837
+ .4byte .LLST45
8838
+ .byte 0
8839
+ .uleb128 0x46
8840
+ .4byte .Ldebug_ranges0+0x90
8841
+ .4byte 0x2ed2
8842
+ .uleb128 0x5c
8843
+ .string "__v"
8844
+ .byte 0x1
8845
+ .2byte 0x125
8846
+ .4byte 0xae
8847
+ .4byte 0x10001
8848
+ .byte 0
8849
+ .uleb128 0x45
8850
+ .8byte .LBB70
8851
+ .8byte .LBE70-.LBB70
8852
+ .4byte 0x2ef7
8853
+ .uleb128 0x59
8854
+ .string "__v"
8855
+ .byte 0x1
8856
+ .2byte 0x12c
8857
+ .4byte 0xae
8858
+ .sleb128 -65535
8859
+ .byte 0
8860
+ .uleb128 0x45
8861
+ .8byte .LBB71
8862
+ .8byte .LBE71-.LBB71
8863
+ .4byte 0x2f1a
8864
+ .uleb128 0x5a
8865
+ .string "__v"
8866
+ .byte 0x1
8867
+ .2byte 0x12d
8868
+ .4byte 0xae
8869
+ .byte 0xfa
8870
+ .byte 0
8871
+ .uleb128 0x45
8872
+ .8byte .LBB72
8873
+ .8byte .LBE72-.LBB72
8874
+ .4byte 0x2f3d
8875
+ .uleb128 0x5a
8876
+ .string "__v"
8877
+ .byte 0x1
8878
+ .2byte 0x12e
8879
+ .4byte 0xae
8880
+ .byte 0x9
8881
+ .byte 0
8882
+ .uleb128 0x46
8883
+ .4byte .Ldebug_ranges0+0xc0
8884
+ .4byte 0x2f57
8885
+ .uleb128 0x5c
8886
+ .string "__v"
8887
+ .byte 0x1
8888
+ .2byte 0x12f
8889
+ .4byte 0xae
8890
+ .4byte 0x10001
8891
+ .byte 0
8892
+ .uleb128 0x45
8893
+ .8byte .LBB75
8894
+ .8byte .LBE75-.LBB75
8895
+ .4byte 0x2f7d
8896
+ .uleb128 0x59
8897
+ .string "__v"
8898
+ .byte 0x1
8899
+ .2byte 0x136
8900
+ .4byte 0xae
8901
+ .sleb128 -16762368
8902
+ .byte 0
8903
+ .uleb128 0x45
8904
+ .8byte .LBB76
8905
+ .8byte .LBE76-.LBB76
8906
+ .4byte 0x2fa2
8907
+ .uleb128 0x59
8908
+ .string "__v"
8909
+ .byte 0x1
8910
+ .2byte 0x137
8911
+ .4byte 0xae
8912
+ .sleb128 -65522
8913
+ .byte 0
8914
+ .uleb128 0x45
8915
+ .8byte .LBB77
8916
+ .8byte .LBE77-.LBB77
8917
+ .4byte 0x2fc5
8918
+ .uleb128 0x5a
8919
+ .string "__v"
8920
+ .byte 0x1
8921
+ .2byte 0x138
8922
+ .4byte 0xae
8923
+ .byte 0xf0
8924
+ .byte 0
8925
+ .uleb128 0x45
8926
+ .8byte .LBB78
8927
+ .8byte .LBE78-.LBB78
8928
+ .4byte 0x2fe8
8929
+ .uleb128 0x5a
8930
+ .string "__v"
8931
+ .byte 0x1
8932
+ .2byte 0x139
8933
+ .4byte 0xae
8934
+ .byte 0x1
8935
+ .byte 0
8936
+ .uleb128 0x45
8937
+ .8byte .LBB79
8938
+ .8byte .LBE79-.LBB79
8939
+ .4byte 0x300b
8940
+ .uleb128 0x5a
8941
+ .string "__v"
8942
+ .byte 0x1
8943
+ .2byte 0x13a
8944
+ .4byte 0xae
8945
+ .byte 0x7a
8946
+ .byte 0
8947
+ .uleb128 0x45
8948
+ .8byte .LBB80
8949
+ .8byte .LBE80-.LBB80
8950
+ .4byte 0x302e
8951
+ .uleb128 0x5a
8952
+ .string "__v"
8953
+ .byte 0x1
8954
+ .2byte 0x13b
8955
+ .4byte 0xae
8956
+ .byte 0x15
8957
+ .byte 0
8958
+ .uleb128 0x45
8959
+ .8byte .LBB81
8960
+ .8byte .LBE81-.LBB81
8961
+ .4byte 0x3051
8962
+ .uleb128 0x5a
8963
+ .string "__v"
8964
+ .byte 0x1
8965
+ .2byte 0x13c
8966
+ .4byte 0xae
8967
+ .byte 0xdc
8968
+ .byte 0
8969
+ .uleb128 0x45
8970
+ .8byte .LBB82
8971
+ .8byte .LBE82-.LBB82
8972
+ .4byte 0x3074
8973
+ .uleb128 0x5a
8974
+ .string "__v"
8975
+ .byte 0x1
8976
+ .2byte 0x13d
8977
+ .4byte 0xae
8978
+ .byte 0x92
8979
+ .byte 0
8980
+ .uleb128 0x45
8981
+ .8byte .LBB83
8982
+ .8byte .LBE83-.LBB83
8983
+ .4byte 0x3097
8984
+ .uleb128 0x5a
8985
+ .string "__v"
8986
+ .byte 0x1
8987
+ .2byte 0x13e
8988
+ .4byte 0xae
8989
+ .byte 0x79
8990
+ .byte 0
8991
+ .uleb128 0x45
8992
+ .8byte .LBB84
8993
+ .8byte .LBE84-.LBB84
8994
+ .4byte 0x30ba
8995
+ .uleb128 0x5a
8996
+ .string "__v"
8997
+ .byte 0x1
8998
+ .2byte 0x13f
8999
+ .4byte 0xae
9000
+ .byte 0x81
9001
+ .byte 0
9002
+ .uleb128 0x45
9003
+ .8byte .LBB85
9004
+ .8byte .LBE85-.LBB85
9005
+ .4byte 0x30dd
9006
+ .uleb128 0x5a
9007
+ .string "__v"
9008
+ .byte 0x1
9009
+ .2byte 0x140
9010
+ .4byte 0xae
9011
+ .byte 0x7e
9012
+ .byte 0
9013
+ .uleb128 0x45
9014
+ .8byte .LBB86
9015
+ .8byte .LBE86-.LBB86
9016
+ .4byte 0x3100
9017
+ .uleb128 0x5a
9018
+ .string "__v"
9019
+ .byte 0x1
9020
+ .2byte 0x141
9021
+ .4byte 0xae
9022
+ .byte 0x21
9023
+ .byte 0
9024
+ .uleb128 0x45
9025
+ .8byte .LBB87
9026
+ .8byte .LBE87-.LBB87
9027
+ .4byte 0x3123
9028
+ .uleb128 0x5a
9029
+ .string "__v"
9030
+ .byte 0x1
9031
+ .2byte 0x142
9032
+ .4byte 0xae
9033
+ .byte 0x11
9034
+ .byte 0
9035
+ .uleb128 0x45
9036
+ .8byte .LBB88
9037
+ .8byte .LBE88-.LBB88
9038
+ .4byte 0x3146
9039
+ .uleb128 0x5a
9040
+ .string "__v"
9041
+ .byte 0x1
9042
+ .2byte 0x143
9043
+ .4byte 0xae
9044
+ .byte 0x9d
9045
+ .byte 0
9046
+ .uleb128 0x45
9047
+ .8byte .LBB89
9048
+ .8byte .LBE89-.LBB89
9049
+ .4byte 0x3169
9050
+ .uleb128 0x5a
9051
+ .string "__v"
9052
+ .byte 0x1
9053
+ .2byte 0x144
9054
+ .4byte 0xae
9055
+ .byte 0x2
9056
+ .byte 0
9057
+ .uleb128 0x45
9058
+ .8byte .LBB90
9059
+ .8byte .LBE90-.LBB90
9060
+ .4byte 0x318c
9061
+ .uleb128 0x5a
9062
+ .string "__v"
9063
+ .byte 0x1
9064
+ .2byte 0x145
9065
+ .4byte 0xae
9066
+ .byte 0
9067
+ .byte 0
9068
+ .uleb128 0x45
9069
+ .8byte .LBB91
9070
+ .8byte .LBE91-.LBB91
9071
+ .4byte 0x31af
9072
+ .uleb128 0x5a
9073
+ .string "__v"
9074
+ .byte 0x1
9075
+ .2byte 0x146
9076
+ .4byte 0xae
9077
+ .byte 0x40
9078
+ .byte 0
9079
+ .uleb128 0x46
9080
+ .4byte .Ldebug_ranges0+0xf0
9081
+ .4byte 0x31c9
9082
+ .uleb128 0x5c
9083
+ .string "__v"
9084
+ .byte 0x1
9085
+ .2byte 0x147
9086
+ .4byte 0xae
9087
+ .4byte 0x10001
9088
+ .byte 0
9089
+ .uleb128 0x45
9090
+ .8byte .LBB94
9091
+ .8byte .LBE94-.LBB94
9092
+ .4byte 0x31ee
9093
+ .uleb128 0x59
9094
+ .string "__v"
9095
+ .byte 0x1
9096
+ .2byte 0x14e
9097
+ .4byte 0xae
9098
+ .sleb128 -65534
9099
+ .byte 0
9100
+ .uleb128 0x45
9101
+ .8byte .LBB95
9102
+ .8byte .LBE95-.LBB95
9103
+ .4byte 0x3211
9104
+ .uleb128 0x5a
9105
+ .string "__v"
9106
+ .byte 0x1
9107
+ .2byte 0x14f
9108
+ .4byte 0xae
9109
+ .byte 0xfc
9110
+ .byte 0
9111
+ .uleb128 0x45
9112
+ .8byte .LBB96
9113
+ .8byte .LBE96-.LBB96
9114
+ .4byte 0x3234
9115
+ .uleb128 0x5a
9116
+ .string "__v"
9117
+ .byte 0x1
9118
+ .2byte 0x150
9119
+ .4byte 0xae
9120
+ .byte 0xa
9121
+ .byte 0
9122
+ .uleb128 0x45
9123
+ .8byte .LBB97
9124
+ .8byte .LBE97-.LBB97
9125
+ .4byte 0x3257
9126
+ .uleb128 0x5a
9127
+ .string "__v"
9128
+ .byte 0x1
9129
+ .2byte 0x151
9130
+ .4byte 0xae
9131
+ .byte 0x70
9132
+ .byte 0
9133
+ .uleb128 0x46
9134
+ .4byte .Ldebug_ranges0+0x120
9135
+ .4byte 0x3271
9136
+ .uleb128 0x5c
9137
+ .string "__v"
9138
+ .byte 0x1
9139
+ .2byte 0x152
9140
+ .4byte 0xae
9141
+ .4byte 0x10001
9142
+ .byte 0
9143
+ .uleb128 0x45
9144
+ .8byte .LBB100
9145
+ .8byte .LBE100-.LBB100
9146
+ .4byte 0x3297
9147
+ .uleb128 0x59
9148
+ .string "__v"
9149
+ .byte 0x1
9150
+ .2byte 0x159
9151
+ .4byte 0xae
9152
+ .sleb128 -16776704
9153
+ .byte 0
9154
+ .uleb128 0x45
9155
+ .8byte .LBB101
9156
+ .8byte .LBE101-.LBB101
9157
+ .4byte 0x32bc
9158
+ .uleb128 0x59
9159
+ .string "__v"
9160
+ .byte 0x1
9161
+ .2byte 0x15a
9162
+ .4byte 0xae
9163
+ .sleb128 -65534
9164
+ .byte 0
9165
+ .uleb128 0x45
9166
+ .8byte .LBB102
9167
+ .8byte .LBE102-.LBB102
9168
+ .4byte 0x32df
9169
+ .uleb128 0x5a
9170
+ .string "__v"
9171
+ .byte 0x1
9172
+ .2byte 0x15b
9173
+ .4byte 0xae
9174
+ .byte 0xc0
9175
+ .byte 0
9176
+ .uleb128 0x46
9177
+ .4byte .Ldebug_ranges0+0x150
9178
+ .4byte 0x32f9
9179
+ .uleb128 0x33
9180
+ .string "__v"
9181
+ .byte 0x1
9182
+ .2byte 0x15c
9183
+ .4byte 0xae
9184
+ .4byte .LLST46
9185
+ .byte 0
9186
+ .uleb128 0x46
9187
+ .4byte .Ldebug_ranges0+0x180
9188
+ .4byte 0x3313
9189
+ .uleb128 0x33
9190
+ .string "__v"
9191
+ .byte 0x1
9192
+ .2byte 0x15d
9193
+ .4byte 0xae
9194
+ .4byte .LLST47
9195
+ .byte 0
9196
+ .uleb128 0x46
9197
+ .4byte .Ldebug_ranges0+0x1b0
9198
+ .4byte 0x332d
9199
+ .uleb128 0x5c
9200
+ .string "__v"
9201
+ .byte 0x1
9202
+ .2byte 0x15e
9203
+ .4byte 0xae
9204
+ .4byte 0x10001
9205
+ .byte 0
9206
+ .uleb128 0x45
9207
+ .8byte .LBB109
9208
+ .8byte .LBE109-.LBB109
9209
+ .4byte 0x3352
9210
+ .uleb128 0x59
9211
+ .string "__v"
9212
+ .byte 0x1
9213
+ .2byte 0x165
9214
+ .4byte 0xae
9215
+ .sleb128 -65535
9216
+ .byte 0
9217
+ .uleb128 0x45
9218
+ .8byte .LBB110
9219
+ .8byte .LBE110-.LBB110
9220
+ .4byte 0x3375
9221
+ .uleb128 0x5a
9222
+ .string "__v"
9223
+ .byte 0x1
9224
+ .2byte 0x166
9225
+ .4byte 0xae
9226
+ .byte 0xe0
9227
+ .byte 0
9228
+ .uleb128 0x45
9229
+ .8byte .LBB111
9230
+ .8byte .LBE111-.LBB111
9231
+ .4byte 0x3398
9232
+ .uleb128 0x5a
9233
+ .string "__v"
9234
+ .byte 0x1
9235
+ .2byte 0x167
9236
+ .4byte 0xae
9237
+ .byte 0
9238
+ .byte 0
9239
+ .uleb128 0x46
9240
+ .4byte .Ldebug_ranges0+0x1e0
9241
+ .4byte 0x33b2
9242
+ .uleb128 0x5c
9243
+ .string "__v"
9244
+ .byte 0x1
9245
+ .2byte 0x168
9246
+ .4byte 0xae
9247
+ .4byte 0x10001
9248
+ .byte 0
9249
+ .uleb128 0x45
9250
+ .8byte .LBB114
9251
+ .8byte .LBE114-.LBB114
9252
+ .4byte 0x33d7
9253
+ .uleb128 0x59
9254
+ .string "__v"
9255
+ .byte 0x1
9256
+ .2byte 0x16f
9257
+ .4byte 0xae
9258
+ .sleb128 -65535
9259
+ .byte 0
9260
+ .uleb128 0x45
9261
+ .8byte .LBB115
9262
+ .8byte .LBE115-.LBB115
9263
+ .4byte 0x33fd
9264
+ .uleb128 0x59
9265
+ .string "__v"
9266
+ .byte 0x1
9267
+ .2byte 0x170
9268
+ .4byte 0xae
9269
+ .sleb128 -16762368
9270
+ .byte 0
9271
+ .uleb128 0x45
9272
+ .8byte .LBB116
9273
+ .8byte .LBE116-.LBB116
9274
+ .4byte 0x3420
9275
+ .uleb128 0x5a
9276
+ .string "__v"
9277
+ .byte 0x1
9278
+ .2byte 0x171
9279
+ .4byte 0xae
9280
+ .byte 0xff
9281
+ .byte 0
9282
+ .uleb128 0x45
9283
+ .8byte .LBB117
9284
+ .8byte .LBE117-.LBB117
9285
+ .4byte 0x3443
9286
+ .uleb128 0x5a
9287
+ .string "__v"
9288
+ .byte 0x1
9289
+ .2byte 0x172
9290
+ .4byte 0xae
9291
+ .byte 0xa
9292
+ .byte 0
9293
+ .uleb128 0x46
9294
+ .4byte .Ldebug_ranges0+0x210
9295
+ .4byte 0x345d
9296
+ .uleb128 0x5c
9297
+ .string "__v"
9298
+ .byte 0x1
9299
+ .2byte 0x173
9300
+ .4byte 0xae
9301
+ .4byte 0x10001
9302
+ .byte 0
9303
+ .uleb128 0x45
9304
+ .8byte .LBB120
9305
+ .8byte .LBE120-.LBB120
9306
+ .4byte 0x3482
9307
+ .uleb128 0x59
9308
+ .string "__v"
9309
+ .byte 0x1
9310
+ .2byte 0x17a
9311
+ .4byte 0xae
9312
+ .sleb128 -65535
9313
+ .byte 0
9314
+ .uleb128 0x45
9315
+ .8byte .LBB121
9316
+ .8byte .LBE121-.LBB121
9317
+ .4byte 0x34a5
9318
+ .uleb128 0x5a
9319
+ .string "__v"
9320
+ .byte 0x1
9321
+ .2byte 0x17b
9322
+ .4byte 0xae
9323
+ .byte 0x1
9324
+ .byte 0
9325
+ .uleb128 0x45
9326
+ .8byte .LBB122
9327
+ .8byte .LBE122-.LBB122
9328
+ .4byte 0x34c8
9329
+ .uleb128 0x5a
9330
+ .string "__v"
9331
+ .byte 0x1
9332
+ .2byte 0x17c
9333
+ .4byte 0xae
9334
+ .byte 0xbf
9335
+ .byte 0
9336
+ .uleb128 0x46
9337
+ .4byte .Ldebug_ranges0+0x240
9338
+ .4byte 0x34e2
9339
+ .uleb128 0x5c
9340
+ .string "__v"
9341
+ .byte 0x1
9342
+ .2byte 0x17d
9343
+ .4byte 0xae
9344
+ .4byte 0x10001
9345
+ .byte 0
9346
+ .uleb128 0x45
9347
+ .8byte .LBB125
9348
+ .8byte .LBE125-.LBB125
9349
+ .4byte 0x3507
9350
+ .uleb128 0x59
9351
+ .string "__v"
9352
+ .byte 0x1
9353
+ .2byte 0x18a
9354
+ .4byte 0xae
9355
+ .sleb128 -65535
9356
+ .byte 0
9357
+ .uleb128 0x45
9358
+ .8byte .LBB126
9359
+ .8byte .LBE126-.LBB126
9360
+ .4byte 0x352a
9361
+ .uleb128 0x5a
9362
+ .string "__v"
9363
+ .byte 0x1
9364
+ .2byte 0x18b
9365
+ .4byte 0xae
9366
+ .byte 0x2
9367
+ .byte 0
9368
+ .uleb128 0x45
9369
+ .8byte .LBB127
9370
+ .8byte .LBE127-.LBB127
9371
+ .4byte 0x354d
9372
+ .uleb128 0x5a
9373
+ .string "__v"
9374
+ .byte 0x1
9375
+ .2byte 0x18c
9376
+ .4byte 0xae
9377
+ .byte 0xbf
9378
+ .byte 0
9379
+ .uleb128 0x46
9380
+ .4byte .Ldebug_ranges0+0x270
9381
+ .4byte 0x3567
9382
+ .uleb128 0x5c
9383
+ .string "__v"
9384
+ .byte 0x1
9385
+ .2byte 0x18d
9386
+ .4byte 0xae
9387
+ .4byte 0x10001
9388
+ .byte 0
9389
+ .uleb128 0x45
9390
+ .8byte .LBB130
9391
+ .8byte .LBE130-.LBB130
9392
+ .4byte 0x358c
9393
+ .uleb128 0x59
9394
+ .string "__v"
9395
+ .byte 0x1
9396
+ .2byte 0x19a
9397
+ .4byte 0xae
9398
+ .sleb128 -65533
9399
+ .byte 0
9400
+ .uleb128 0x45
9401
+ .8byte .LBB131
9402
+ .8byte .LBE131-.LBB131
9403
+ .4byte 0x35b2
9404
+ .uleb128 0x59
9405
+ .string "__v"
9406
+ .byte 0x1
9407
+ .2byte 0x19b
9408
+ .4byte 0xae
9409
+ .sleb128 -16776704
9410
+ .byte 0
9411
+ .uleb128 0x45
9412
+ .8byte .LBB132
9413
+ .8byte .LBE132-.LBB132
9414
+ .4byte 0x35d7
9415
+ .uleb128 0x59
9416
+ .string "__v"
9417
+ .byte 0x1
9418
+ .2byte 0x19c
9419
+ .4byte 0xae
9420
+ .sleb128 -65535
9421
+ .byte 0
9422
+ .uleb128 0x45
9423
+ .8byte .LBB133
9424
+ .8byte .LBE133-.LBB133
9425
+ .4byte 0x35fa
9426
+ .uleb128 0x5a
9427
+ .string "__v"
9428
+ .byte 0x1
9429
+ .2byte 0x19d
9430
+ .4byte 0xae
9431
+ .byte 0x2
9432
+ .byte 0
9433
+ .uleb128 0x45
9434
+ .8byte .LBB134
9435
+ .8byte .LBE134-.LBB134
9436
+ .4byte 0x361d
9437
+ .uleb128 0x5a
9438
+ .string "__v"
9439
+ .byte 0x1
9440
+ .2byte 0x19e
9441
+ .4byte 0xae
9442
+ .byte 0x80
9443
+ .byte 0
9444
+ .uleb128 0x46
9445
+ .4byte .Ldebug_ranges0+0x2a0
9446
+ .4byte 0x3637
9447
+ .uleb128 0x5c
9448
+ .string "__v"
9449
+ .byte 0x1
9450
+ .2byte 0x19f
9451
+ .4byte 0xae
9452
+ .4byte 0x10001
9453
+ .byte 0
9454
+ .uleb128 0x45
9455
+ .8byte .LBB137
9456
+ .8byte .LBE137-.LBB137
9457
+ .4byte 0x365c
9458
+ .uleb128 0x59
9459
+ .string "__v"
9460
+ .byte 0x1
9461
+ .2byte 0x1a6
9462
+ .4byte 0xae
9463
+ .sleb128 -65535
9464
+ .byte 0
9465
+ .uleb128 0x45
9466
+ .8byte .LBB138
9467
+ .8byte .LBE138-.LBB138
9468
+ .4byte 0x367f
9469
+ .uleb128 0x5a
9470
+ .string "__v"
9471
+ .byte 0x1
9472
+ .2byte 0x1a7
9473
+ .4byte 0xae
9474
+ .byte 0xa0
9475
+ .byte 0
9476
+ .uleb128 0x45
9477
+ .8byte .LBB139
9478
+ .8byte .LBE139-.LBB139
9479
+ .4byte 0x36a2
9480
+ .uleb128 0x5a
9481
+ .string "__v"
9482
+ .byte 0x1
9483
+ .2byte 0x1a8
9484
+ .4byte 0xae
9485
+ .byte 0
9486
+ .byte 0
9487
+ .uleb128 0x46
9488
+ .4byte .Ldebug_ranges0+0x2d0
9489
+ .4byte 0x36bc
9490
+ .uleb128 0x5c
9491
+ .string "__v"
9492
+ .byte 0x1
9493
+ .2byte 0x1a9
9494
+ .4byte 0xae
9495
+ .4byte 0x10001
9496
+ .byte 0
9497
+ .uleb128 0x45
9498
+ .8byte .LBB142
9499
+ .8byte .LBE142-.LBB142
9500
+ .4byte 0x36df
9501
+ .uleb128 0x5a
9502
+ .string "__v"
9503
+ .byte 0x1
9504
+ .2byte 0x1b0
9505
+ .4byte 0xae
9506
+ .byte 0xfa
9507
+ .byte 0
9508
+ .uleb128 0x45
9509
+ .8byte .LBB143
9510
+ .8byte .LBE143-.LBB143
9511
+ .4byte 0x3702
9512
+ .uleb128 0x5a
9513
+ .string "__v"
9514
+ .byte 0x1
9515
+ .2byte 0x1b1
9516
+ .4byte 0xae
9517
+ .byte 0x9
9518
+ .byte 0
9519
+ .uleb128 0x46
9520
+ .4byte .Ldebug_ranges0+0x300
9521
+ .4byte 0x371c
9522
+ .uleb128 0x5c
9523
+ .string "__v"
9524
+ .byte 0x1
9525
+ .2byte 0x1b2
9526
+ .4byte 0xae
9527
+ .4byte 0x10001
9528
+ .byte 0
9529
+ .uleb128 0x34
9530
+ .8byte .LVL67
9531
+ .4byte 0x42a5
9532
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9533
+ .uleb128 0x35
9534
+ .uleb128 0x1
9535
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9536
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9537
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9538
+ .uleb128 0x1
9539
+ .byte 0x50
9540
+ .byte 0
9541
+ .uleb128 0x34
9542
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9543
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9544
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9545
+ .uleb128 0x35
9546
+ .uleb128 0x1
9547
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9548
+ .uleb128 0x9
9549
+ .byte 0x3
9550
+ .8byte .LC4
9551
+ .uleb128 0x35
9552
+ .uleb128 0x1
9553
+ .byte 0x51
9554
+ .uleb128 0x5
9555
+ .byte 0x88
9556
+ .sleb128 0
9557
+ .byte 0x9
9558
+ .byte 0xfe
9559
+ .byte 0x1a
9560
+ .byte 0
9561
+ .uleb128 0x47
9562
+ .8byte .LVL74
9563
+ .4byte 0x3771
9564
+ .uleb128 0x35
9565
+ .uleb128 0x1
9566
+ .byte 0x53
9567
+ .uleb128 0x2
9568
+ .byte 0x84
9569
+ .sleb128 0
9570
+ .byte 0
9571
+ .uleb128 0x34
9572
+ .8byte .LVL83
9573
+ .4byte 0x4018
9574
+ .4byte 0x3796
9575
+ .uleb128 0x35
9576
+ .uleb128 0x1
9577
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9578
+ .uleb128 0x2
9579
+ .byte 0x8a
9580
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9581
+ .uleb128 0x35
9582
+ .uleb128 0x1
9583
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9584
+ .uleb128 0x1
9585
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9586
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9587
+ .4byte 0x3d74
9588
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9589
+ .byte 0x8a
9590
+ .sleb128 0
9591
+ .byte 0
9592
+ .uleb128 0x49
9593
+ .8byte .LVL85
9594
+ .4byte 0x42b1
9595
+ .uleb128 0x47
9596
+ .8byte .LVL86
9597
+ .4byte 0x37b7
9598
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9599
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9600
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9601
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9602
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9603
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9604
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9605
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9606
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9607
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9608
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9609
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9610
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9611
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9612
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9613
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9614
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9615
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9616
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9617
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9618
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9619
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9620
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9621
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9622
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9623
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9624
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9625
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9626
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9627
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9628
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9629
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9630
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9631
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9632
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9633
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9634
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9635
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9636
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9637
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9638
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9639
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9640
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9641
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9642
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9643
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9644
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9645
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9646
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9647
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9648
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9649
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9650
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9651
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9652
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9653
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9654
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9655
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9656
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9657
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9658
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9659
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9660
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9661
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9662
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9663
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9664
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9665
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9666
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9667
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9668
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9669
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9670
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9671
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9672
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9673
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9674
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9675
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9676
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9677
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9678
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9679
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9680
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9681
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9682
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9683
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9684
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9685
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9686
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9687
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9688
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9689
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9690
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9691
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9692
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9693
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9694
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9695
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9696
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9697
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9698
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9699
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9700
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9701
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9702
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9703
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9704
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9705
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9706
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9707
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9708
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9709
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9710
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9711
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9712
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9713
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9714
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9715
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9716
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9717
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9718
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9719
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9720
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9721
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9722
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9723
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9724
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9725
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9726
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9727
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9728
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9729
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9730
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9731
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9732
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9733
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9734
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9735
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9736
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9737
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9738
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9739
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9740
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9741
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9742
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9743
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9744
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9745
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9746
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9747
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9748
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9749
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9750
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9751
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9752
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9753
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9754
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9755
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9756
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9757
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9758
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9759
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9760
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9761
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9762
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9763
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9764
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9765
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9766
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9767
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9768
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9769
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9770
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9771
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9772
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9773
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9774
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9775
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9776
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9777
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9778
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9779
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9780
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9781
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9782
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9783
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9784
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9785
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9786
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9787
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9788
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9789
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9790
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9791
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9792
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9793
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9794
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9795
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9796
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9797
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9798
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9799
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9800
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9801
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9802
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9803
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9804
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9805
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9806
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9807
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9808
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9809
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9810
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9811
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9812
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9813
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9814
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9815
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9816
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9817
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9818
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9819
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9820
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9821
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9822
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9823
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9824
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9825
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9826
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9827
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9828
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9829
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9830
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9831
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9832
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9833
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9834
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9835
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9836
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9837
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9838
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9839
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9840
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9841
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9842
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9843
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9844
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9845
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9846
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9847
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9848
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9849
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9850
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9851
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9852
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9853
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9854
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9855
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9856
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9857
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9858
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9859
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9860
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9861
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9862
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9863
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9864
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9865
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9866
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9867
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9868
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9869
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9870
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9871
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9872
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9873
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9874
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9875
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9876
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9877
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9878
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9879
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9880
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9881
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9882
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9883
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9884
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9885
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9886
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9887
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9888
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9889
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9890
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9891
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9892
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9893
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9894
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9895
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9896
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9897
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9898
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9899
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9900
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9901
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9902
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9903
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9904
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9905
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9906
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9907
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9908
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9909
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9910
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9911
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9912
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9913
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9914
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9915
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9916
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9917
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9918
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9919
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9920
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9921
+ .byte 0xae
9922
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9923
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9924
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9925
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9926
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9927
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9928
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9929
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9930
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9931
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9932
+ .byte 0x1
9933
+ .byte 0xaf
9934
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9935
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9936
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9937
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9938
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9939
+ .byte 0xaf
9940
+ .4byte 0x54
9941
+ .4byte .LLST58
9942
+ .uleb128 0x55
9943
+ .string "otp"
9944
+ .byte 0x1
9945
+ .byte 0xb1
9946
+ .4byte 0x1825
9947
+ .4byte .LLST59
9948
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9949
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9950
+ .byte 0x1
9951
+ .byte 0xb2
9952
+ .4byte 0x197b
9953
+ .4byte .LLST60
9954
+ .uleb128 0x56
9955
+ .4byte .LASF437
9956
+ .byte 0x1
9957
+ .byte 0xb3
9958
+ .4byte 0x11c6
9959
+ .4byte .LLST61
9960
+ .uleb128 0x56
9961
+ .4byte .LASF429
9962
+ .byte 0x1
9963
+ .byte 0xb4
9964
+ .4byte 0xa3
9965
+ .4byte .LLST62
9966
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9967
+ .string "ret"
9968
+ .byte 0x1
9969
+ .byte 0xb5
9970
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9971
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9972
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9973
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9974
+ .4byte 0x3c15
9975
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9976
+ .byte 0x3
9977
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9978
+ .uleb128 0x5d
9979
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9980
+ .byte 0x1
9981
+ .byte 0xe3
9982
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9983
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9984
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9985
+ .4byte 0x3ab2
9986
+ .uleb128 0x55
9987
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9988
+ .byte 0x1
9989
+ .byte 0xc0
9990
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9991
+ .4byte .LLST64
9992
+ .byte 0
9993
+ .uleb128 0x46
9994
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9995
+ .4byte 0x3acb
9996
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9997
+ .string "__v"
9998
+ .byte 0x1
9999
+ .byte 0xd0
10000
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10001
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10002
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10003
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10004
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10005
+ .4byte 0x3ae4
10006
+ .uleb128 0x55
10007
+ .string "__v"
10008
+ .byte 0x1
10009
+ .byte 0xd2
10010
+ .4byte 0xae
10011
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10012
+ .byte 0
10013
+ .uleb128 0x45
10014
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10015
+ .8byte .LBE176-.LBB176
10016
+ .4byte 0x3b09
10017
+ .uleb128 0x55
10018
+ .string "__v"
10019
+ .byte 0x1
10020
+ .byte 0xda
10021
+ .4byte 0xa3
10022
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10023
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10024
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10025
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10026
+ .4byte 0x3b22
10027
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10028
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10029
+ .byte 0x1
10030
+ .byte 0xe4
10031
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10032
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10033
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10034
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10035
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10036
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10037
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10038
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10039
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10040
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10041
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10042
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10043
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10044
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10045
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10046
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10047
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10048
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10049
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10050
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10051
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10052
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10053
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10054
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10055
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10056
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10057
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10058
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10059
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10060
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10061
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10062
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10063
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10064
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10065
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10066
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10067
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10068
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10069
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10070
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10071
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10072
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10073
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10074
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10075
+ .sleb128 0
10076
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10077
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10078
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10079
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10080
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10081
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10082
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10083
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10084
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10085
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10086
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10087
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10088
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10089
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10090
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10091
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10092
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10093
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10094
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10095
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10096
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10097
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10098
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10099
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10100
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10101
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10102
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10103
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10104
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10105
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10106
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10107
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10108
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10109
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10110
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10111
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10112
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10113
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10114
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10115
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10116
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10117
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10118
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10119
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10120
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10121
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10122
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10123
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10124
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10125
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10126
+ .byte 0x3
10127
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10128
+ .byte 0
10129
+ .uleb128 0x5e
10130
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10131
+ .uleb128 0x35
10132
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10133
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10134
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10135
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10136
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10137
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10138
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10139
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10140
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10141
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10142
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10143
+ .4byte 0xda
10144
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10145
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10146
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10147
+ .4byte 0x3c05
10148
+ .uleb128 0x5f
10149
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10150
+ .byte 0x1
10151
+ .byte 0x98
10152
+ .4byte 0x54
10153
+ .byte 0x1
10154
+ .4byte 0x3cbb
10155
+ .uleb128 0x60
10156
+ .string "otp"
10157
+ .byte 0x1
10158
+ .byte 0x98
10159
+ .4byte 0x1825
10160
+ .uleb128 0x61
10161
+ .4byte .LASF268
10162
+ .byte 0x1
10163
+ .byte 0x99
10164
+ .4byte 0x144
10165
+ .uleb128 0x62
10166
+ .string "ret"
10167
+ .byte 0x1
10168
+ .byte 0x9b
10169
+ .4byte 0x54
10170
+ .uleb128 0x4e
10171
+ .4byte .LASF432
10172
+ .4byte 0x3ccb
10173
+ .4byte .LASF440
10174
+ .uleb128 0x50
10175
+ .4byte 0x3c69
10176
+ .uleb128 0x62
10177
+ .string "__v"
10178
+ .byte 0x1
10179
+ .byte 0x9d
10180
+ .4byte 0xae
10181
+ .byte 0
10182
+ .uleb128 0x50
10183
+ .4byte 0x3c7a
10184
+ .uleb128 0x62
10185
+ .string "__v"
10186
+ .byte 0x1
10187
+ .byte 0x9e
10188
+ .4byte 0xae
10189
+ .byte 0
10190
+ .uleb128 0x50
10191
+ .4byte 0x3c8b
10192
+ .uleb128 0x62
10193
+ .string "__v"
10194
+ .byte 0x1
10195
+ .byte 0x9f
10196
+ .4byte 0xae
10197
+ .byte 0
10198
+ .uleb128 0x50
10199
+ .4byte 0x3c9c
10200
+ .uleb128 0x62
10201
+ .string "__v"
10202
+ .byte 0x1
10203
+ .byte 0xa1
10204
+ .4byte 0xae
10205
+ .byte 0
10206
+ .uleb128 0x50
10207
+ .4byte 0x3cad
10208
+ .uleb128 0x62
10209
+ .string "__v"
10210
+ .byte 0x1
10211
+ .byte 0xa3
10212
+ .4byte 0xae
10213
+ .byte 0
10214
+ .uleb128 0x51
10215
+ .uleb128 0x62
10216
+ .string "__v"
10217
+ .byte 0x1
10218
+ .byte 0xa5
10219
+ .4byte 0xae
10220
+ .byte 0
10221
+ .byte 0
10222
+ .uleb128 0xa
10223
+ .4byte 0xee
10224
+ .4byte 0x3ccb
10225
+ .uleb128 0x11
10226
+ .4byte 0xda
10227
+ .byte 0x1e
10228
+ .byte 0
10229
+ .uleb128 0x7
10230
+ .4byte 0x3cbb
10231
+ .uleb128 0x5f
10232
+ .4byte .LASF441
10233
+ .byte 0x1
10234
+ .byte 0x81
10235
+ .4byte 0x54
10236
+ .byte 0x1
10237
+ .4byte 0x3d1a
10238
+ .uleb128 0x60
10239
+ .string "otp"
10240
+ .byte 0x1
10241
+ .byte 0x81
10242
+ .4byte 0x1825
10243
+ .uleb128 0x63
10244
+ .4byte .LASF442
10245
+ .byte 0x1
10246
+ .byte 0x83
10247
+ .4byte 0x54
10248
+ .uleb128 0x63
10249
+ .4byte .LASF429
10250
+ .byte 0x1
10251
+ .byte 0x84
10252
+ .4byte 0x54
10253
+ .uleb128 0x62
10254
+ .string "ret"
10255
+ .byte 0x1
10256
+ .byte 0x85
10257
+ .4byte 0x54
10258
+ .uleb128 0x51
10259
+ .uleb128 0x62
10260
+ .string "__v"
10261
+ .byte 0x1
10262
+ .byte 0x88
10263
+ .4byte 0xae
10264
+ .byte 0
10265
+ .byte 0
10266
+ .uleb128 0x5f
10267
+ .4byte .LASF443
10268
+ .byte 0x1
10269
+ .byte 0x6a
10270
+ .4byte 0x54
10271
+ .byte 0x1
10272
+ .4byte 0x3d64
10273
+ .uleb128 0x60
10274
+ .string "otp"
10275
+ .byte 0x1
10276
+ .byte 0x6a
10277
+ .4byte 0x1825
10278
+ .uleb128 0x63
10279
+ .4byte .LASF442
10280
+ .byte 0x1
10281
+ .byte 0x6c
10282
+ .4byte 0x54
10283
+ .uleb128 0x63
10284
+ .4byte .LASF429
10285
+ .byte 0x1
10286
+ .byte 0x6d
10287
+ .4byte 0x54
10288
+ .uleb128 0x62
10289
+ .string "ret"
10290
+ .byte 0x1
10291
+ .byte 0x6e
10292
+ .4byte 0x54
10293
+ .uleb128 0x51
10294
+ .uleb128 0x62
10295
+ .string "__v"
10296
+ .byte 0x1
10297
+ .byte 0x71
10298
+ .4byte 0xae
10299
+ .byte 0
10300
+ .byte 0
10301
+ .uleb128 0x5f
10302
+ .4byte .LASF444
10303
+ .byte 0x1
10304
+ .byte 0x56
10305
+ .4byte 0x54
10306
+ .byte 0x1
10307
+ .4byte 0x3dc1
10308
+ .uleb128 0x60
10309
+ .string "otp"
10310
+ .byte 0x1
10311
+ .byte 0x56
10312
+ .4byte 0x1825
10313
+ .uleb128 0x61
10314
+ .4byte .LASF445
10315
+ .byte 0x1
10316
+ .byte 0x57
10317
+ .4byte 0xae
10318
+ .uleb128 0x63
10319
+ .4byte .LASF442
10320
+ .byte 0x1
10321
+ .byte 0x59
10322
+ .4byte 0x54
10323
+ .uleb128 0x4e
10324
+ .4byte .LASF432
10325
+ .4byte 0x2a47
10326
+ .4byte .LASF444
10327
+ .uleb128 0x50
10328
+ .4byte 0x3db3
10329
+ .uleb128 0x62
10330
+ .string "__v"
10331
+ .byte 0x1
10332
+ .byte 0x5b
10333
+ .4byte 0xae
10334
+ .byte 0
10335
+ .uleb128 0x51
10336
+ .uleb128 0x62
10337
+ .string "__v"
10338
+ .byte 0x1
10339
+ .byte 0x65
10340
+ .4byte 0xae
10341
+ .byte 0
10342
+ .byte 0
10343
+ .uleb128 0x64
10344
+ .4byte .LASF449
10345
+ .byte 0x1
10346
+ .byte 0x4e
10347
+ .8byte .LFB263
10348
+ .8byte .LFE263-.LFB263
10349
+ .uleb128 0x1
10350
+ .byte 0x9c
10351
+ .4byte 0x3e36
10352
+ .uleb128 0x65
10353
+ .4byte .LASF446
10354
+ .byte 0x1
10355
+ .byte 0x4e
10356
+ .4byte 0x11d2
10357
+ .uleb128 0x1
10358
+ .byte 0x50
10359
+ .uleb128 0x54
10360
+ .4byte .LASF447
10361
+ .byte 0x1
10362
+ .byte 0x4f
10363
+ .4byte 0x11d2
10364
+ .4byte .LLST0
10365
+ .uleb128 0x65
10366
+ .4byte .LASF448
10367
+ .byte 0x1
10368
+ .byte 0x50
10369
+ .4byte 0x3b
10370
+ .uleb128 0x1
10371
+ .byte 0x52
10372
+ .uleb128 0x65
10373
+ .4byte .LASF424
10374
+ .byte 0x1
10375
+ .byte 0x50
10376
+ .4byte 0x54
10377
+ .uleb128 0x1
10378
+ .byte 0x53
10379
+ .uleb128 0x66
10380
+ .8byte .LBB22
10381
+ .8byte .LBE22-.LBB22
10382
+ .uleb128 0x67
10383
+ .string "__v"
10384
+ .byte 0x1
10385
+ .byte 0x52
10386
+ .4byte 0xae
10387
+ .4byte 0x1000000
10388
+ .byte 0
10389
+ .byte 0
10390
+ .uleb128 0x64
10391
+ .4byte .LASF450
10392
+ .byte 0x1
10393
+ .byte 0x42
10394
+ .8byte .LFB262
10395
+ .8byte .LFE262-.LFB262
10396
+ .uleb128 0x1
10397
+ .byte 0x9c
10398
+ .4byte 0x3f29
10399
+ .uleb128 0x54
10400
+ .4byte .LASF446
10401
+ .byte 0x1
10402
+ .byte 0x42
10403
+ .4byte 0x11d2
10404
+ .4byte .LLST16
10405
+ .uleb128 0x54
10406
+ .4byte .LASF447
10407
+ .byte 0x1
10408
+ .byte 0x43
10409
+ .4byte 0x11d2
10410
+ .4byte .LLST17
10411
+ .uleb128 0x54
10412
+ .4byte .LASF448
10413
+ .byte 0x1
10414
+ .byte 0x44
10415
+ .4byte 0x3b
10416
+ .4byte .LLST18
10417
+ .uleb128 0x54
10418
+ .4byte .LASF424
10419
+ .byte 0x1
10420
+ .byte 0x44
10421
+ .4byte 0x54
10422
+ .4byte .LLST19
10423
+ .uleb128 0x45
10424
+ .8byte .LBB25
10425
+ .8byte .LBE25-.LBB25
10426
+ .4byte 0x3eb4
10427
+ .uleb128 0x67
10428
+ .string "__v"
10429
+ .byte 0x1
10430
+ .byte 0x47
10431
+ .4byte 0xae
10432
+ .4byte 0x1000100
10433
+ .byte 0
10434
+ .uleb128 0x45
10435
+ .8byte .LBB26
10436
+ .8byte .LBE26-.LBB26
10437
+ .4byte 0x3ed9
10438
+ .uleb128 0x67
10439
+ .string "__v"
10440
+ .byte 0x1
10441
+ .byte 0x48
10442
+ .4byte 0xae
10443
+ .4byte 0x20002
10444
+ .byte 0
10445
+ .uleb128 0x45
10446
+ .8byte .LBB27
10447
+ .8byte .LBE27-.LBB27
10448
+ .4byte 0x3efe
10449
+ .uleb128 0x67
10450
+ .string "__v"
10451
+ .byte 0x1
10452
+ .byte 0x4a
10453
+ .4byte 0xae
10454
+ .4byte 0x20000
10455
+ .byte 0
10456
+ .uleb128 0x34
10457
+ .8byte .LVL32
10458
+ .4byte 0x42c8
10459
+ .4byte 0x3f15
10460
+ .uleb128 0x35
10461
+ .uleb128 0x1
10462
+ .byte 0x50
10463
+ .uleb128 0x1
10464
+ .byte 0x32
10465
+ .byte 0
10466
+ .uleb128 0x68
10467
+ .8byte .LVL34
10468
+ .4byte 0x42c8
10469
+ .uleb128 0x35
10470
+ .uleb128 0x1
10471
+ .byte 0x50
10472
+ .uleb128 0x1
10473
+ .byte 0x31
10474
+ .byte 0
10475
+ .byte 0
10476
+ .uleb128 0x69
10477
+ .4byte .LASF462
10478
+ .byte 0x1a
10479
+ .2byte 0x36f
10480
+ .byte 0x3
10481
+ .4byte 0x3f43
10482
+ .uleb128 0x3c
10483
+ .string "ptr"
10484
+ .byte 0x1a
10485
+ .2byte 0x36f
10486
+ .4byte 0x137
10487
+ .byte 0
10488
+ .uleb128 0x6a
10489
+ .4byte 0x3cd0
10490
+ .8byte .LFB278
10491
+ .8byte .LFE278-.LFB278
10492
+ .uleb128 0x1
10493
+ .byte 0x9c
10494
+ .4byte 0x3fad
10495
+ .uleb128 0x6b
10496
+ .4byte 0x3ce0
10497
+ .uleb128 0x42
10498
+ .4byte 0x3ceb
10499
+ .4byte .LLST20
10500
+ .uleb128 0x42
10501
+ .4byte 0x3cf6
10502
+ .4byte .LLST21
10503
+ .uleb128 0x44
10504
+ .4byte 0x3d01
10505
+ .uleb128 0x45
10506
+ .8byte .LBB28
10507
+ .8byte .LBE28-.LBB28
10508
+ .4byte 0x3f99
10509
+ .uleb128 0x42
10510
+ .4byte 0x3d0d
10511
+ .4byte .LLST22
10512
+ .byte 0
10513
+ .uleb128 0x36
10514
+ .8byte .LVL40
10515
+ .4byte 0x42c8
10516
+ .uleb128 0x35
10517
+ .uleb128 0x1
10518
+ .byte 0x50
10519
+ .uleb128 0x1
10520
+ .byte 0x31
10521
+ .byte 0
10522
+ .byte 0
10523
+ .uleb128 0x6a
10524
+ .4byte 0x3d1a
10525
+ .8byte .LFB279
10526
+ .8byte .LFE279-.LFB279
10527
+ .uleb128 0x1
10528
+ .byte 0x9c
10529
+ .4byte 0x4018
10530
+ .uleb128 0x6b
10531
+ .4byte 0x3d2a
10532
+ .uleb128 0x42
10533
+ .4byte 0x3d35
10534
+ .4byte .LLST23
10535
+ .uleb128 0x42
10536
+ .4byte 0x3d40
10537
+ .4byte .LLST24
10538
+ .uleb128 0x6c
10539
+ .4byte 0x3d4b
10540
+ .sleb128 -1
10541
+ .uleb128 0x45
10542
+ .8byte .LBB29
10543
+ .8byte .LBE29-.LBB29
10544
+ .4byte 0x4004
10545
+ .uleb128 0x42
10546
+ .4byte 0x3d57
10547
+ .4byte .LLST25
10548
+ .byte 0
10549
+ .uleb128 0x36
10550
+ .8byte .LVL48
10551
+ .4byte 0x42c8
10552
+ .uleb128 0x35
10553
+ .uleb128 0x1
10554
+ .byte 0x50
10555
+ .uleb128 0x1
10556
+ .byte 0x31
10557
+ .byte 0
10558
+ .byte 0
10559
+ .uleb128 0x6a
10560
+ .4byte 0x3d64
10561
+ .8byte .LFB280
10562
+ .8byte .LFE280-.LFB280
10563
+ .uleb128 0x1
10564
+ .byte 0x9c
10565
+ .4byte 0x4105
10566
+ .uleb128 0x3a
10567
+ .4byte 0x3d7f
10568
+ .4byte .LLST26
10569
+ .uleb128 0x6b
10570
+ .4byte 0x3d74
10571
+ .uleb128 0x42
10572
+ .4byte 0x3d8a
10573
+ .4byte .LLST27
10574
+ .uleb128 0x44
10575
+ .4byte 0x3d95
10576
+ .uleb128 0x45
10577
+ .8byte .LBB36
10578
+ .8byte .LBE36-.LBB36
10579
+ .4byte 0x406e
10580
+ .uleb128 0x42
10581
+ .4byte 0x3da7
10582
+ .4byte .LLST28
10583
+ .byte 0
10584
+ .uleb128 0x45
10585
+ .8byte .LBB37
10586
+ .8byte .LBE37-.LBB37
10587
+ .4byte 0x408d
10588
+ .uleb128 0x42
10589
+ .4byte 0x3db4
10590
+ .4byte .LLST29
10591
+ .byte 0
10592
+ .uleb128 0x45
10593
+ .8byte .LBB38
10594
+ .8byte .LBE38-.LBB38
10595
+ .4byte 0x40f1
10596
+ .uleb128 0x6b
10597
+ .4byte 0x3d7f
10598
+ .uleb128 0x6b
10599
+ .4byte 0x3d74
10600
+ .uleb128 0x66
10601
+ .8byte .LBB39
10602
+ .8byte .LBE39-.LBB39
10603
+ .uleb128 0x44
10604
+ .4byte 0x3d8a
10605
+ .uleb128 0x44
10606
+ .4byte 0x3d95
10607
+ .uleb128 0x36
10608
+ .8byte .LVL63
10609
+ .4byte 0x42b1
10610
+ .uleb128 0x35
10611
+ .uleb128 0x1
10612
+ .byte 0x50
10613
+ .uleb128 0x9
10614
+ .byte 0x3
10615
+ .8byte .LC3
10616
+ .uleb128 0x35
10617
+ .uleb128 0x1
10618
+ .byte 0x51
10619
+ .uleb128 0x9
10620
+ .byte 0x3
10621
+ .8byte .LANCHOR0
10622
+ .byte 0
10623
+ .byte 0
10624
+ .byte 0
10625
+ .uleb128 0x36
10626
+ .8byte .LVL60
10627
+ .4byte 0x42c8
10628
+ .uleb128 0x35
10629
+ .uleb128 0x1
10630
+ .byte 0x50
10631
+ .uleb128 0x1
10632
+ .byte 0x31
10633
+ .byte 0
10634
+ .byte 0
10635
+ .uleb128 0x6a
10636
+ .4byte 0x3c1a
10637
+ .8byte .LFB267
10638
+ .8byte .LFE267-.LFB267
10639
+ .uleb128 0x1
10640
+ .byte 0x9c
10641
+ .4byte 0x4283
10642
+ .uleb128 0x3a
10643
+ .4byte 0x3c2a
10644
+ .4byte .LLST48
10645
+ .uleb128 0x3a
10646
+ .4byte 0x3c35
10647
+ .4byte .LLST49
10648
+ .uleb128 0x42
10649
+ .4byte 0x3c40
10650
+ .4byte .LLST50
10651
+ .uleb128 0x44
10652
+ .4byte 0x3c4b
10653
+ .uleb128 0x45
10654
+ .8byte .LBB160
10655
+ .8byte .LBE160-.LBB160
10656
+ .4byte 0x415f
10657
+ .uleb128 0x6c
10658
+ .4byte 0x3c5d
10659
+ .sleb128 -16776704
10660
+ .byte 0
10661
+ .uleb128 0x45
10662
+ .8byte .LBB161
10663
+ .8byte .LBE161-.LBB161
10664
+ .4byte 0x417d
10665
+ .uleb128 0x6c
10666
+ .4byte 0x3c6e
10667
+ .sleb128 -65535
10668
+ .byte 0
10669
+ .uleb128 0x45
10670
+ .8byte .LBB162
10671
+ .8byte .LBE162-.LBB162
10672
+ .4byte 0x4199
10673
+ .uleb128 0x6d
10674
+ .4byte 0x3c7f
10675
+ .byte 0xfa
10676
+ .byte 0
10677
+ .uleb128 0x45
10678
+ .8byte .LBB163
10679
+ .8byte .LBE163-.LBB163
10680
+ .4byte 0x41b8
10681
+ .uleb128 0x42
10682
+ .4byte 0x3c90
10683
+ .4byte .LLST51
10684
+ .byte 0
10685
+ .uleb128 0x45
10686
+ .8byte .LBB164
10687
+ .8byte .LBE164-.LBB164
10688
+ .4byte 0x41d7
10689
+ .uleb128 0x42
10690
+ .4byte 0x3cae
10691
+ .4byte .LLST52
10692
+ .byte 0
10693
+ .uleb128 0x45
10694
+ .8byte .LBB165
10695
+ .8byte .LBE165-.LBB165
10696
+ .4byte 0x4243
10697
+ .uleb128 0x3a
10698
+ .4byte 0x3c2a
10699
+ .4byte .LLST53
10700
+ .uleb128 0x3a
10701
+ .4byte 0x3c35
10702
+ .4byte .LLST54
10703
+ .uleb128 0x66
10704
+ .8byte .LBB166
10705
+ .8byte .LBE166-.LBB166
10706
+ .uleb128 0x44
10707
+ .4byte 0x4132
10708
+ .uleb128 0x44
10709
+ .4byte 0x413b
10710
+ .uleb128 0x36
10711
+ .8byte .LVL209
10712
+ .4byte 0x42b1
10713
+ .uleb128 0x35
10714
+ .uleb128 0x1
10715
+ .byte 0x50
10716
+ .uleb128 0x9
10717
+ .byte 0x3
10718
+ .8byte .LC8
10719
+ .uleb128 0x35
10720
+ .uleb128 0x1
10721
+ .byte 0x51
10722
+ .uleb128 0x9
10723
+ .byte 0x3
10724
+ .8byte .LANCHOR2
10725
+ .byte 0
10726
+ .byte 0
10727
+ .byte 0
10728
+ .uleb128 0x45
10729
+ .8byte .LBB167
10730
+ .8byte .LBE167-.LBB167
10731
+ .4byte 0x425f
10732
+ .uleb128 0x6d
10733
+ .4byte 0x3ca1
10734
+ .byte 0x9
10735
+ .byte 0
10736
+ .uleb128 0x36
10737
+ .8byte .LVL205
10738
+ .4byte 0x4018
10739
+ .uleb128 0x35
10740
+ .uleb128 0x1
10741
+ .byte 0x50
10742
+ .uleb128 0x3
10743
+ .byte 0xf3
10744
+ .uleb128 0x1
10745
+ .byte 0x50
10746
+ .uleb128 0x35
10747
+ .uleb128 0x1
10748
+ .byte 0x51
10749
+ .uleb128 0x1
10750
+ .byte 0x32
10751
+ .uleb128 0x48
10752
+ .4byte 0x3d74
10753
+ .uleb128 0x3
10754
+ .byte 0xf3
10755
+ .uleb128 0x1
10756
+ .byte 0x50
10757
+ .byte 0
10758
+ .byte 0
10759
+ .uleb128 0x6e
10760
+ .4byte .LASF451
10761
+ .4byte .LASF451
10762
+ .byte 0x8
10763
+ .2byte 0x115
10764
+ .uleb128 0x6f
10765
+ .4byte .LASF452
10766
+ .4byte .LASF452
10767
+ .byte 0x20
10768
+ .byte 0x85
10769
+ .uleb128 0x6f
10770
+ .4byte .LASF453
10771
+ .4byte .LASF453
10772
+ .byte 0x20
10773
+ .byte 0x38
10774
+ .uleb128 0x6e
10775
+ .4byte .LASF454
10776
+ .4byte .LASF454
10777
+ .byte 0x8
10778
+ .2byte 0x16e
10779
+ .uleb128 0x6f
10780
+ .4byte .LASF455
10781
+ .4byte .LASF455
10782
+ .byte 0x21
10783
+ .byte 0x13
10784
+ .uleb128 0x6e
10785
+ .4byte .LASF456
10786
+ .4byte .LASF456
10787
+ .byte 0x1a
10788
+ .2byte 0x393
10789
+ .uleb128 0x6f
10790
+ .4byte .LASF457
10791
+ .4byte .LASF457
10792
+ .byte 0x22
10793
+ .byte 0xb
10794
+ .byte 0
10795
+ .section .debug_abbrev,"",@progbits
10796
+.Ldebug_abbrev0:
10797
+ .uleb128 0x1
10798
+ .uleb128 0x11
10799
+ .byte 0x1
10800
+ .uleb128 0x25
10801
+ .uleb128 0xe
10802
+ .uleb128 0x13
10803
+ .uleb128 0xb
10804
+ .uleb128 0x3
10805
+ .uleb128 0xe
10806
+ .uleb128 0x1b
10807
+ .uleb128 0xe
10808
+ .uleb128 0x55
10809
+ .uleb128 0x17
10810
+ .uleb128 0x11
10811
+ .uleb128 0x1
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12060
+ .byte 0x1
12061
+ .uleb128 0x3
12062
+ .uleb128 0xe
12063
+ .uleb128 0x3a
12064
+ .uleb128 0xb
12065
+ .uleb128 0x3b
12066
+ .uleb128 0xb
12067
+ .uleb128 0x27
12068
+ .uleb128 0x19
12069
+ .uleb128 0x11
12070
+ .uleb128 0x1
12071
+ .uleb128 0x12
12072
+ .uleb128 0x7
12073
+ .uleb128 0x40
12074
+ .uleb128 0x18
12075
+ .uleb128 0x2117
12076
+ .uleb128 0x19
12077
+ .uleb128 0x1
12078
+ .uleb128 0x13
12079
+ .byte 0
12080
+ .byte 0
12081
+ .uleb128 0x65
12082
+ .uleb128 0x5
12083
+ .byte 0
12084
+ .uleb128 0x3
12085
+ .uleb128 0xe
12086
+ .uleb128 0x3a
12087
+ .uleb128 0xb
12088
+ .uleb128 0x3b
12089
+ .uleb128 0xb
12090
+ .uleb128 0x49
12091
+ .uleb128 0x13
12092
+ .uleb128 0x2
12093
+ .uleb128 0x18
12094
+ .byte 0
12095
+ .byte 0
12096
+ .uleb128 0x66
12097
+ .uleb128 0xb
12098
+ .byte 0x1
12099
+ .uleb128 0x11
12100
+ .uleb128 0x1
12101
+ .uleb128 0x12
12102
+ .uleb128 0x7
12103
+ .byte 0
12104
+ .byte 0
12105
+ .uleb128 0x67
12106
+ .uleb128 0x34
12107
+ .byte 0
12108
+ .uleb128 0x3
12109
+ .uleb128 0x8
12110
+ .uleb128 0x3a
12111
+ .uleb128 0xb
12112
+ .uleb128 0x3b
12113
+ .uleb128 0xb
12114
+ .uleb128 0x49
12115
+ .uleb128 0x13
12116
+ .uleb128 0x1c
12117
+ .uleb128 0x6
12118
+ .byte 0
12119
+ .byte 0
12120
+ .uleb128 0x68
12121
+ .uleb128 0x4109
12122
+ .byte 0x1
12123
+ .uleb128 0x11
12124
+ .uleb128 0x1
12125
+ .uleb128 0x2115
12126
+ .uleb128 0x19
12127
+ .uleb128 0x31
12128
+ .uleb128 0x13
12129
+ .byte 0
12130
+ .byte 0
12131
+ .uleb128 0x69
12132
+ .uleb128 0x2e
12133
+ .byte 0x1
12134
+ .uleb128 0x3
12135
+ .uleb128 0xe
12136
+ .uleb128 0x3a
12137
+ .uleb128 0xb
12138
+ .uleb128 0x3b
12139
+ .uleb128 0x5
12140
+ .uleb128 0x27
12141
+ .uleb128 0x19
12142
+ .uleb128 0x20
12143
+ .uleb128 0xb
12144
+ .uleb128 0x1
12145
+ .uleb128 0x13
12146
+ .byte 0
12147
+ .byte 0
12148
+ .uleb128 0x6a
12149
+ .uleb128 0x2e
12150
+ .byte 0x1
12151
+ .uleb128 0x31
12152
+ .uleb128 0x13
12153
+ .uleb128 0x11
12154
+ .uleb128 0x1
12155
+ .uleb128 0x12
12156
+ .uleb128 0x7
12157
+ .uleb128 0x40
12158
+ .uleb128 0x18
12159
+ .uleb128 0x2117
12160
+ .uleb128 0x19
12161
+ .uleb128 0x1
12162
+ .uleb128 0x13
12163
+ .byte 0
12164
+ .byte 0
12165
+ .uleb128 0x6b
12166
+ .uleb128 0x5
12167
+ .byte 0
12168
+ .uleb128 0x31
12169
+ .uleb128 0x13
12170
+ .byte 0
12171
+ .byte 0
12172
+ .uleb128 0x6c
12173
+ .uleb128 0x34
12174
+ .byte 0
12175
+ .uleb128 0x31
12176
+ .uleb128 0x13
12177
+ .uleb128 0x1c
12178
+ .uleb128 0xd
12179
+ .byte 0
12180
+ .byte 0
12181
+ .uleb128 0x6d
12182
+ .uleb128 0x34
12183
+ .byte 0
12184
+ .uleb128 0x31
12185
+ .uleb128 0x13
12186
+ .uleb128 0x1c
12187
+ .uleb128 0xb
12188
+ .byte 0
12189
+ .byte 0
12190
+ .uleb128 0x6e
12191
+ .uleb128 0x2e
12192
+ .byte 0
12193
+ .uleb128 0x3f
12194
+ .uleb128 0x19
12195
+ .uleb128 0x3c
12196
+ .uleb128 0x19
12197
+ .uleb128 0x6e
12198
+ .uleb128 0xe
12199
+ .uleb128 0x3
12200
+ .uleb128 0xe
12201
+ .uleb128 0x3a
12202
+ .uleb128 0xb
12203
+ .uleb128 0x3b
12204
+ .uleb128 0x5
12205
+ .byte 0
12206
+ .byte 0
12207
+ .uleb128 0x6f
12208
+ .uleb128 0x2e
12209
+ .byte 0
12210
+ .uleb128 0x3f
12211
+ .uleb128 0x19
12212
+ .uleb128 0x3c
12213
+ .uleb128 0x19
12214
+ .uleb128 0x6e
12215
+ .uleb128 0xe
12216
+ .uleb128 0x3
12217
+ .uleb128 0xe
12218
+ .uleb128 0x3a
12219
+ .uleb128 0xb
12220
+ .uleb128 0x3b
12221
+ .uleb128 0xb
12222
+ .byte 0
12223
+ .byte 0
12224
+ .byte 0
12225
+ .section .debug_loc,"",@progbits
12226
+.Ldebug_loc0:
12227
+.LLST14:
12228
+ .8byte .LVL19
12229
+ .8byte .LVL20-1
12230
+ .2byte 0x1
12231
+ .byte 0x50
12232
+ .8byte .LVL20-1
12233
+ .8byte .LVL27
12234
+ .2byte 0x1
12235
+ .byte 0x64
12236
+ .8byte .LVL27
12237
+ .8byte .LFE277
12238
+ .2byte 0x4
12239
+ .byte 0xf3
12240
+ .uleb128 0x1
12241
+ .byte 0x50
12242
+ .byte 0x9f
12243
+ .8byte 0
12244
+ .8byte 0
12245
+.LLST15:
12246
+ .8byte .LVL21
12247
+ .8byte .LVL22
12248
+ .2byte 0x1
12249
+ .byte 0x50
12250
+ .8byte .LVL22
12251
+ .8byte .LVL27
12252
+ .2byte 0x1
12253
+ .byte 0x63
12254
+ .8byte 0
12255
+ .8byte 0
12256
+.LLST1:
12257
+ .8byte .LVL2
12258
+ .8byte .LVL3
12259
+ .2byte 0x1
12260
+ .byte 0x50
12261
+ .8byte .LVL3
12262
+ .8byte .LFE276
12263
+ .2byte 0x4
12264
+ .byte 0xf3
12265
+ .uleb128 0x1
12266
+ .byte 0x50
12267
+ .byte 0x9f
12268
+ .8byte 0
12269
+ .8byte 0
12270
+.LLST2:
12271
+ .8byte .LVL2
12272
+ .8byte .LVL5
12273
+ .2byte 0x3
12274
+ .byte 0x9
12275
+ .byte 0xea
12276
+ .byte 0x9f
12277
+ .8byte .LVL6
12278
+ .8byte .LFE276
12279
+ .2byte 0x3
12280
+ .byte 0x9
12281
+ .byte 0xea
12282
+ .byte 0x9f
12283
+ .8byte 0
12284
+ .8byte 0
12285
+.LLST3:
12286
+ .8byte .LVL4
12287
+ .8byte .LVL5
12288
+ .2byte 0x1
12289
+ .byte 0x52
12290
+ .8byte 0
12291
+ .8byte 0
12292
+.LLST4:
12293
+ .8byte .LVL7
12294
+ .8byte .LVL8-1
12295
+ .2byte 0x1
12296
+ .byte 0x50
12297
+ .8byte .LVL8-1
12298
+ .8byte .LVL11
12299
+ .2byte 0x1
12300
+ .byte 0x63
12301
+ .8byte .LVL11
12302
+ .8byte .LVL12-1
12303
+ .2byte 0x1
12304
+ .byte 0x50
12305
+ .8byte .LVL12-1
12306
+ .8byte .LFE274
12307
+ .2byte 0x4
12308
+ .byte 0xf3
12309
+ .uleb128 0x1
12310
+ .byte 0x50
12311
+ .byte 0x9f
12312
+ .8byte 0
12313
+ .8byte 0
12314
+.LLST5:
12315
+ .8byte .LVL7
12316
+ .8byte .LVL8-1
12317
+ .2byte 0x1
12318
+ .byte 0x51
12319
+ .8byte .LVL8-1
12320
+ .8byte .LVL11
12321
+ .2byte 0x1
12322
+ .byte 0x64
12323
+ .8byte .LVL11
12324
+ .8byte .LVL12-1
12325
+ .2byte 0x1
12326
+ .byte 0x51
12327
+ .8byte .LVL12-1
12328
+ .8byte .LFE274
12329
+ .2byte 0x4
12330
+ .byte 0xf3
12331
+ .uleb128 0x1
12332
+ .byte 0x51
12333
+ .byte 0x9f
12334
+ .8byte 0
12335
+ .8byte 0
12336
+.LLST6:
12337
+ .8byte .LVL7
12338
+ .8byte .LVL8-1
12339
+ .2byte 0x1
12340
+ .byte 0x52
12341
+ .8byte .LVL8-1
12342
+ .8byte .LVL10
12343
+ .2byte 0x1
12344
+ .byte 0x65
12345
+ .8byte .LVL10
12346
+ .8byte .LVL12-1
12347
+ .2byte 0x1
12348
+ .byte 0x52
12349
+ .8byte .LVL12-1
12350
+ .8byte .LFE274
12351
+ .2byte 0x4
12352
+ .byte 0xf3
12353
+ .uleb128 0x1
12354
+ .byte 0x52
12355
+ .byte 0x9f
12356
+ .8byte 0
12357
+ .8byte 0
12358
+.LLST7:
12359
+ .8byte .LVL7
12360
+ .8byte .LVL8-1
12361
+ .2byte 0x1
12362
+ .byte 0x53
12363
+ .8byte .LVL8-1
12364
+ .8byte .LVL10
12365
+ .2byte 0x1
12366
+ .byte 0x66
12367
+ .8byte .LVL10
12368
+ .8byte .LVL12-1
12369
+ .2byte 0x1
12370
+ .byte 0x53
12371
+ .8byte .LVL12-1
12372
+ .8byte .LFE274
12373
+ .2byte 0x4
12374
+ .byte 0xf3
12375
+ .uleb128 0x1
12376
+ .byte 0x53
12377
+ .byte 0x9f
12378
+ .8byte 0
12379
+ .8byte 0
12380
+.LLST8:
12381
+ .8byte .LVL8
12382
+ .8byte .LVL9
12383
+ .2byte 0x1
12384
+ .byte 0x50
12385
+ .8byte 0
12386
+ .8byte 0
12387
+.LLST9:
12388
+ .8byte .LVL13
12389
+ .8byte .LVL14-1
12390
+ .2byte 0x1
12391
+ .byte 0x50
12392
+ .8byte .LVL14-1
12393
+ .8byte .LVL17
12394
+ .2byte 0x1
12395
+ .byte 0x63
12396
+ .8byte .LVL17
12397
+ .8byte .LVL18-1
12398
+ .2byte 0x1
12399
+ .byte 0x50
12400
+ .8byte .LVL18-1
12401
+ .8byte .LFE273
12402
+ .2byte 0x4
12403
+ .byte 0xf3
12404
+ .uleb128 0x1
12405
+ .byte 0x50
12406
+ .byte 0x9f
12407
+ .8byte 0
12408
+ .8byte 0
12409
+.LLST10:
12410
+ .8byte .LVL13
12411
+ .8byte .LVL14-1
12412
+ .2byte 0x1
12413
+ .byte 0x51
12414
+ .8byte .LVL14-1
12415
+ .8byte .LVL17
12416
+ .2byte 0x1
12417
+ .byte 0x64
12418
+ .8byte .LVL17
12419
+ .8byte .LVL18-1
12420
+ .2byte 0x1
12421
+ .byte 0x51
12422
+ .8byte .LVL18-1
12423
+ .8byte .LFE273
12424
+ .2byte 0x4
12425
+ .byte 0xf3
12426
+ .uleb128 0x1
12427
+ .byte 0x51
12428
+ .byte 0x9f
12429
+ .8byte 0
12430
+ .8byte 0
12431
+.LLST11:
12432
+ .8byte .LVL13
12433
+ .8byte .LVL14-1
12434
+ .2byte 0x1
12435
+ .byte 0x52
12436
+ .8byte .LVL14-1
12437
+ .8byte .LVL16
12438
+ .2byte 0x1
12439
+ .byte 0x65
12440
+ .8byte .LVL16
12441
+ .8byte .LVL18-1
12442
+ .2byte 0x1
12443
+ .byte 0x52
12444
+ .8byte .LVL18-1
12445
+ .8byte .LFE273
12446
+ .2byte 0x4
12447
+ .byte 0xf3
12448
+ .uleb128 0x1
12449
+ .byte 0x52
12450
+ .byte 0x9f
12451
+ .8byte 0
12452
+ .8byte 0
12453
+.LLST12:
12454
+ .8byte .LVL13
12455
+ .8byte .LVL14-1
12456
+ .2byte 0x1
12457
+ .byte 0x53
12458
+ .8byte .LVL14-1
12459
+ .8byte .LVL16
12460
+ .2byte 0x1
12461
+ .byte 0x66
12462
+ .8byte .LVL16
12463
+ .8byte .LVL18-1
12464
+ .2byte 0x1
12465
+ .byte 0x53
12466
+ .8byte .LVL18-1
12467
+ .8byte .LFE273
12468
+ .2byte 0x4
12469
+ .byte 0xf3
12470
+ .uleb128 0x1
12471
+ .byte 0x53
12472
+ .byte 0x9f
12473
+ .8byte 0
12474
+ .8byte 0
12475
+.LLST13:
12476
+ .8byte .LVL14
12477
+ .8byte .LVL15
12478
+ .2byte 0x1
12479
+ .byte 0x50
12480
+ .8byte 0
12481
+ .8byte 0
12482
+.LLST69:
12483
+ .8byte .LVL246
12484
+ .8byte .LVL247-1
12485
+ .2byte 0x1
12486
+ .byte 0x50
12487
+ .8byte .LVL247-1
12488
+ .8byte .LVL254
12489
+ .2byte 0x1
12490
+ .byte 0x68
12491
+ .8byte .LVL254
12492
+ .8byte .LVL257
12493
+ .2byte 0x4
12494
+ .byte 0xf3
12495
+ .uleb128 0x1
12496
+ .byte 0x50
12497
+ .byte 0x9f
12498
+ .8byte .LVL257
12499
+ .8byte .LFE272
12500
+ .2byte 0x1
12501
+ .byte 0x68
12502
+ .8byte 0
12503
+ .8byte 0
12504
+.LLST70:
12505
+ .8byte .LVL246
12506
+ .8byte .LVL247-1
12507
+ .2byte 0x1
12508
+ .byte 0x51
12509
+ .8byte .LVL247-1
12510
+ .8byte .LVL253
12511
+ .2byte 0x1
12512
+ .byte 0x64
12513
+ .8byte .LVL253
12514
+ .8byte .LVL257
12515
+ .2byte 0x4
12516
+ .byte 0xf3
12517
+ .uleb128 0x1
12518
+ .byte 0x51
12519
+ .byte 0x9f
12520
+ .8byte .LVL257
12521
+ .8byte .LFE272
12522
+ .2byte 0x1
12523
+ .byte 0x64
12524
+ .8byte 0
12525
+ .8byte 0
12526
+.LLST71:
12527
+ .8byte .LVL246
12528
+ .8byte .LVL247-1
12529
+ .2byte 0x1
12530
+ .byte 0x52
12531
+ .8byte .LVL247-1
12532
+ .8byte .LVL256
12533
+ .2byte 0x3
12534
+ .byte 0x8f
12535
+ .sleb128 224
12536
+ .8byte .LVL256
12537
+ .8byte .LVL257
12538
+ .2byte 0x3
12539
+ .byte 0x8f
12540
+ .sleb128 80
12541
+ .8byte .LVL257
12542
+ .8byte .LFE272
12543
+ .2byte 0x3
12544
+ .byte 0x8f
12545
+ .sleb128 224
12546
+ .8byte 0
12547
+ .8byte 0
12548
+.LLST72:
12549
+ .8byte .LVL246
12550
+ .8byte .LVL247-1
12551
+ .2byte 0x1
12552
+ .byte 0x53
12553
+ .8byte .LVL247-1
12554
+ .8byte .LVL252
12555
+ .2byte 0x1
12556
+ .byte 0x65
12557
+ .8byte .LVL252
12558
+ .8byte .LVL257
12559
+ .2byte 0x4
12560
+ .byte 0xf3
12561
+ .uleb128 0x1
12562
+ .byte 0x53
12563
+ .byte 0x9f
12564
+ .8byte .LVL257
12565
+ .8byte .LVL261
12566
+ .2byte 0x1
12567
+ .byte 0x65
12568
+ .8byte .LVL261
12569
+ .8byte .LVL267
12570
+ .2byte 0x4
12571
+ .byte 0xf3
12572
+ .uleb128 0x1
12573
+ .byte 0x53
12574
+ .byte 0x9f
12575
+ .8byte .LVL267
12576
+ .8byte .LVL281
12577
+ .2byte 0x1
12578
+ .byte 0x65
12579
+ .8byte .LVL281
12580
+ .8byte .LVL283
12581
+ .2byte 0x4
12582
+ .byte 0xf3
12583
+ .uleb128 0x1
12584
+ .byte 0x53
12585
+ .byte 0x9f
12586
+ .8byte .LVL283
12587
+ .8byte .LVL287
12588
+ .2byte 0x1
12589
+ .byte 0x65
12590
+ .8byte .LVL287
12591
+ .8byte .LVL396
12592
+ .2byte 0x4
12593
+ .byte 0xf3
12594
+ .uleb128 0x1
12595
+ .byte 0x53
12596
+ .byte 0x9f
12597
+ .8byte .LVL396
12598
+ .8byte .LFE272
12599
+ .2byte 0x1
12600
+ .byte 0x65
12601
+ .8byte 0
12602
+ .8byte 0
12603
+.LLST73:
12604
+ .8byte .LVL248
12605
+ .8byte .LVL249
12606
+ .2byte 0x1
12607
+ .byte 0x50
12608
+ .8byte .LVL249
12609
+ .8byte .LVL255
12610
+ .2byte 0x1
12611
+ .byte 0x6c
12612
+ .8byte .LVL257
12613
+ .8byte .LFE272
12614
+ .2byte 0x1
12615
+ .byte 0x6c
12616
+ .8byte 0
12617
+ .8byte 0
12618
+.LLST74:
12619
+ .8byte .LVL248
12620
+ .8byte .LVL256
12621
+ .2byte 0x3
12622
+ .byte 0x8f
12623
+ .sleb128 224
12624
+ .8byte .LVL256
12625
+ .8byte .LVL257
12626
+ .2byte 0x3
12627
+ .byte 0x8f
12628
+ .sleb128 80
12629
+ .8byte .LVL257
12630
+ .8byte .LFE272
12631
+ .2byte 0x3
12632
+ .byte 0x8f
12633
+ .sleb128 224
12634
+ .8byte 0
12635
+ .8byte 0
12636
+.LLST76:
12637
+ .8byte .LVL250
12638
+ .8byte .LVL251
12639
+ .2byte 0x1
12640
+ .byte 0x50
12641
+ .8byte .LVL257
12642
+ .8byte .LVL258
12643
+ .2byte 0x1
12644
+ .byte 0x50
12645
+ .8byte .LVL258
12646
+ .8byte .LVL260
12647
+ .2byte 0x1
12648
+ .byte 0x63
12649
+ .8byte .LVL267
12650
+ .8byte .LVL272
12651
+ .2byte 0x1
12652
+ .byte 0x63
12653
+ .8byte .LVL285
12654
+ .8byte .LVL286
12655
+ .2byte 0x1
12656
+ .byte 0x63
12657
+ .8byte 0
12658
+ .8byte 0
12659
+.LLST77:
12660
+ .8byte .LVL261
12661
+ .8byte .LVL267
12662
+ .2byte 0x1
12663
+ .byte 0x67
12664
+ .8byte .LVL269
12665
+ .8byte .LVL270
12666
+ .2byte 0x1
12667
+ .byte 0x50
12668
+ .8byte .LVL272
12669
+ .8byte .LVL278
12670
+ .2byte 0x1
12671
+ .byte 0x63
12672
+ .8byte .LVL283
12673
+ .8byte .LVL285
12674
+ .2byte 0x1
12675
+ .byte 0x63
12676
+ .8byte .LVL286
12677
+ .8byte .LVL287
12678
+ .2byte 0x1
12679
+ .byte 0x63
12680
+ .8byte .LVL288
12681
+ .8byte .LVL394
12682
+ .2byte 0x1
12683
+ .byte 0x67
12684
+ .8byte .LVL394
12685
+ .8byte .LVL395
12686
+ .2byte 0x3
12687
+ .byte 0x87
12688
+ .sleb128 1
12689
+ .byte 0x9f
12690
+ .8byte .LVL396
12691
+ .8byte .LFE272
12692
+ .2byte 0x1
12693
+ .byte 0x63
12694
+ .8byte 0
12695
+ .8byte 0
12696
+.LLST78:
12697
+ .8byte .LVL250
12698
+ .8byte .LVL251
12699
+ .2byte 0x2
12700
+ .byte 0x30
12701
+ .byte 0x9f
12702
+ .8byte .LVL257
12703
+ .8byte .LVL268
12704
+ .2byte 0x2
12705
+ .byte 0x30
12706
+ .byte 0x9f
12707
+ .8byte .LVL268
12708
+ .8byte .LVL269
12709
+ .2byte 0x1
12710
+ .byte 0x50
12711
+ .8byte .LVL272
12712
+ .8byte .LVL280
12713
+ .2byte 0x2
12714
+ .byte 0x30
12715
+ .byte 0x9f
12716
+ .8byte .LVL283
12717
+ .8byte .LVL315
12718
+ .2byte 0x2
12719
+ .byte 0x30
12720
+ .byte 0x9f
12721
+ .8byte .LVL317
12722
+ .8byte .LVL394
12723
+ .2byte 0x2
12724
+ .byte 0x30
12725
+ .byte 0x9f
12726
+ .8byte 0
12727
+ .8byte 0
12728
+.LLST79:
12729
+ .8byte .LVL262
12730
+ .8byte .LVL267
12731
+ .2byte 0x1
12732
+ .byte 0x6a
12733
+ .8byte .LVL288
12734
+ .8byte .LVL313
12735
+ .2byte 0x1
12736
+ .byte 0x6a
12737
+ .8byte .LVL317
12738
+ .8byte .LVL352
12739
+ .2byte 0x1
12740
+ .byte 0x6a
12741
+ .8byte 0
12742
+ .8byte 0
12743
+.LLST80:
12744
+ .8byte .LVL262
12745
+ .8byte .LVL264
12746
+ .2byte 0x1
12747
+ .byte 0x65
12748
+ .8byte .LVL264
12749
+ .8byte .LVL267
12750
+ .2byte 0x1
12751
+ .byte 0x69
12752
+ .8byte .LVL288
12753
+ .8byte .LVL315
12754
+ .2byte 0x1
12755
+ .byte 0x69
12756
+ .8byte .LVL317
12757
+ .8byte .LVL394
12758
+ .2byte 0x1
12759
+ .byte 0x69
12760
+ .8byte 0
12761
+ .8byte 0
12762
+.LLST81:
12763
+ .8byte .LVL262
12764
+ .8byte .LVL267
12765
+ .2byte 0x1
12766
+ .byte 0x6c
12767
+ .8byte .LVL288
12768
+ .8byte .LVL315
12769
+ .2byte 0x1
12770
+ .byte 0x6c
12771
+ .8byte .LVL317
12772
+ .8byte .LVL394
12773
+ .2byte 0x1
12774
+ .byte 0x6c
12775
+ .8byte 0
12776
+ .8byte 0
12777
+.LLST82:
12778
+ .8byte .LVL262
12779
+ .8byte .LVL267
12780
+ .2byte 0x1
12781
+ .byte 0x68
12782
+ .8byte .LVL288
12783
+ .8byte .LVL315
12784
+ .2byte 0x1
12785
+ .byte 0x68
12786
+ .8byte .LVL317
12787
+ .8byte .LVL394
12788
+ .2byte 0x1
12789
+ .byte 0x68
12790
+ .8byte 0
12791
+ .8byte 0
12792
+.LLST83:
12793
+ .8byte .LVL262
12794
+ .8byte .LVL267
12795
+ .2byte 0x2
12796
+ .byte 0x30
12797
+ .byte 0x9f
12798
+ .8byte .LVL288
12799
+ .8byte .LVL311
12800
+ .2byte 0x2
12801
+ .byte 0x30
12802
+ .byte 0x9f
12803
+ .8byte .LVL311
12804
+ .8byte .LVL312
12805
+ .2byte 0x1
12806
+ .byte 0x50
12807
+ .8byte .LVL312
12808
+ .8byte .LVL315
12809
+ .2byte 0x1
12810
+ .byte 0x6b
12811
+ .8byte .LVL317
12812
+ .8byte .LVL318
12813
+ .2byte 0x1
12814
+ .byte 0x50
12815
+ .8byte .LVL318
12816
+ .8byte .LVL337
12817
+ .2byte 0x1
12818
+ .byte 0x6b
12819
+ .8byte .LVL337
12820
+ .8byte .LVL338
12821
+ .2byte 0x1
12822
+ .byte 0x50
12823
+ .8byte .LVL338
12824
+ .8byte .LVL339
12825
+ .2byte 0x1
12826
+ .byte 0x6b
12827
+ .8byte .LVL339
12828
+ .8byte .LVL340
12829
+ .2byte 0x1
12830
+ .byte 0x50
12831
+ .8byte .LVL340
12832
+ .8byte .LVL346
12833
+ .2byte 0x1
12834
+ .byte 0x6b
12835
+ .8byte .LVL346
12836
+ .8byte .LVL347
12837
+ .2byte 0x1
12838
+ .byte 0x50
12839
+ .8byte .LVL347
12840
+ .8byte .LVL348
12841
+ .2byte 0x1
12842
+ .byte 0x6b
12843
+ .8byte .LVL348
12844
+ .8byte .LVL349
12845
+ .2byte 0x1
12846
+ .byte 0x50
12847
+ .8byte .LVL349
12848
+ .8byte .LVL356
12849
+ .2byte 0x1
12850
+ .byte 0x6b
12851
+ .8byte .LVL356
12852
+ .8byte .LVL357
12853
+ .2byte 0x1
12854
+ .byte 0x50
12855
+ .8byte .LVL357
12856
+ .8byte .LVL358
12857
+ .2byte 0x1
12858
+ .byte 0x6b
12859
+ .8byte .LVL358
12860
+ .8byte .LVL359
12861
+ .2byte 0x1
12862
+ .byte 0x50
12863
+ .8byte .LVL359
12864
+ .8byte .LVL365
12865
+ .2byte 0x1
12866
+ .byte 0x6b
12867
+ .8byte .LVL365
12868
+ .8byte .LVL366
12869
+ .2byte 0x1
12870
+ .byte 0x50
12871
+ .8byte .LVL366
12872
+ .8byte .LVL367
12873
+ .2byte 0x1
12874
+ .byte 0x6b
12875
+ .8byte .LVL367
12876
+ .8byte .LVL368
12877
+ .2byte 0x1
12878
+ .byte 0x50
12879
+ .8byte .LVL368
12880
+ .8byte .LVL374
12881
+ .2byte 0x1
12882
+ .byte 0x6b
12883
+ .8byte .LVL374
12884
+ .8byte .LVL375
12885
+ .2byte 0x1
12886
+ .byte 0x50
12887
+ .8byte .LVL375
12888
+ .8byte .LVL376
12889
+ .2byte 0x1
12890
+ .byte 0x6b
12891
+ .8byte .LVL376
12892
+ .8byte .LVL377
12893
+ .2byte 0x1
12894
+ .byte 0x50
12895
+ .8byte .LVL377
12896
+ .8byte .LVL379
12897
+ .2byte 0x1
12898
+ .byte 0x6b
12899
+ .8byte .LVL379
12900
+ .8byte .LVL380
12901
+ .2byte 0x1
12902
+ .byte 0x50
12903
+ .8byte .LVL380
12904
+ .8byte .LVL381
12905
+ .2byte 0x1
12906
+ .byte 0x6b
12907
+ .8byte .LVL381
12908
+ .8byte .LVL382
12909
+ .2byte 0x1
12910
+ .byte 0x50
12911
+ .8byte .LVL382
12912
+ .8byte .LVL387
12913
+ .2byte 0x1
12914
+ .byte 0x6b
12915
+ .8byte .LVL387
12916
+ .8byte .LVL388
12917
+ .2byte 0x1
12918
+ .byte 0x50
12919
+ .8byte .LVL388
12920
+ .8byte .LVL389
12921
+ .2byte 0x1
12922
+ .byte 0x6b
12923
+ .8byte .LVL389
12924
+ .8byte .LVL390
12925
+ .2byte 0x1
12926
+ .byte 0x50
12927
+ .8byte .LVL390
12928
+ .8byte .LVL392
12929
+ .2byte 0x1
12930
+ .byte 0x6b
12931
+ .8byte .LVL392
12932
+ .8byte .LVL393
12933
+ .2byte 0x1
12934
+ .byte 0x50
12935
+ .8byte .LVL393
12936
+ .8byte .LVL394
12937
+ .2byte 0x1
12938
+ .byte 0x6b
12939
+ .8byte 0
12940
+ .8byte 0
12941
+.LLST84:
12942
+ .8byte .LVL264
12943
+ .8byte .LVL265
12944
+ .2byte 0x1
12945
+ .byte 0x50
12946
+ .8byte .LVL265
12947
+ .8byte .LVL267
12948
+ .2byte 0x3
12949
+ .byte 0x8f
12950
+ .sleb128 232
12951
+ .8byte .LVL288
12952
+ .8byte .LVL315
12953
+ .2byte 0x3
12954
+ .byte 0x8f
12955
+ .sleb128 232
12956
+ .8byte .LVL317
12957
+ .8byte .LVL394
12958
+ .2byte 0x3
12959
+ .byte 0x8f
12960
+ .sleb128 232
12961
+ .8byte 0
12962
+ .8byte 0
12963
+.LLST85:
12964
+ .8byte .LVL289
12965
+ .8byte .LVL316
12966
+ .2byte 0x4
12967
+ .byte 0x40
12968
+ .byte 0x3c
12969
+ .byte 0x24
12970
+ .byte 0x9f
12971
+ .8byte .LVL317
12972
+ .8byte .LVL394
12973
+ .2byte 0x4
12974
+ .byte 0x40
12975
+ .byte 0x3c
12976
+ .byte 0x24
12977
+ .byte 0x9f
12978
+ .8byte 0
12979
+ .8byte 0
12980
+.LLST86:
12981
+ .8byte .LVL290
12982
+ .8byte .LVL316
12983
+ .2byte 0x6
12984
+ .byte 0xc
12985
+ .4byte 0x40004
12986
+ .byte 0x9f
12987
+ .8byte .LVL317
12988
+ .8byte .LVL394
12989
+ .2byte 0x6
12990
+ .byte 0xc
12991
+ .4byte 0x40004
12992
+ .byte 0x9f
12993
+ .8byte 0
12994
+ .8byte 0
12995
+.LLST87:
12996
+ .8byte .LVL291
12997
+ .8byte .LVL316
12998
+ .2byte 0x5
12999
+ .byte 0x11
13000
+ .sleb128 -65536
13001
+ .byte 0x9f
13002
+ .8byte .LVL317
13003
+ .8byte .LVL394
13004
+ .2byte 0x5
13005
+ .byte 0x11
13006
+ .sleb128 -65536
13007
+ .byte 0x9f
13008
+ .8byte 0
13009
+ .8byte 0
13010
+.LLST88:
13011
+ .8byte .LVL292
13012
+ .8byte .LVL316
13013
+ .2byte 0x6
13014
+ .byte 0x11
13015
+ .sleb128 -16776704
13016
+ .byte 0x9f
13017
+ .8byte .LVL317
13018
+ .8byte .LVL394
13019
+ .2byte 0x6
13020
+ .byte 0x11
13021
+ .sleb128 -16776704
13022
+ .byte 0x9f
13023
+ .8byte 0
13024
+ .8byte 0
13025
+.LLST89:
13026
+ .8byte .LVL293
13027
+ .8byte .LVL316
13028
+ .2byte 0x5
13029
+ .byte 0x11
13030
+ .sleb128 -65522
13031
+ .byte 0x9f
13032
+ .8byte .LVL317
13033
+ .8byte .LVL394
13034
+ .2byte 0x5
13035
+ .byte 0x11
13036
+ .sleb128 -65522
13037
+ .byte 0x9f
13038
+ .8byte 0
13039
+ .8byte 0
13040
+.LLST90:
13041
+ .8byte .LVL294
13042
+ .8byte .LVL316
13043
+ .2byte 0x3
13044
+ .byte 0x8
13045
+ .byte 0xf0
13046
+ .byte 0x9f
13047
+ .8byte .LVL317
13048
+ .8byte .LVL394
13049
+ .2byte 0x3
13050
+ .byte 0x8
13051
+ .byte 0xf0
13052
+ .byte 0x9f
13053
+ .8byte 0
13054
+ .8byte 0
13055
+.LLST91:
13056
+ .8byte .LVL295
13057
+ .8byte .LVL316
13058
+ .2byte 0x2
13059
+ .byte 0x31
13060
+ .byte 0x9f
13061
+ .8byte .LVL317
13062
+ .8byte .LVL394
13063
+ .2byte 0x2
13064
+ .byte 0x31
13065
+ .byte 0x9f
13066
+ .8byte 0
13067
+ .8byte 0
13068
+.LLST92:
13069
+ .8byte .LVL296
13070
+ .8byte .LVL316
13071
+ .2byte 0x3
13072
+ .byte 0x8
13073
+ .byte 0x7a
13074
+ .byte 0x9f
13075
+ .8byte .LVL317
13076
+ .8byte .LVL394
13077
+ .2byte 0x3
13078
+ .byte 0x8
13079
+ .byte 0x7a
13080
+ .byte 0x9f
13081
+ .8byte 0
13082
+ .8byte 0
13083
+.LLST93:
13084
+ .8byte .LVL297
13085
+ .8byte .LVL316
13086
+ .2byte 0x3
13087
+ .byte 0x8
13088
+ .byte 0x25
13089
+ .byte 0x9f
13090
+ .8byte .LVL317
13091
+ .8byte .LVL394
13092
+ .2byte 0x3
13093
+ .byte 0x8
13094
+ .byte 0x25
13095
+ .byte 0x9f
13096
+ .8byte 0
13097
+ .8byte 0
13098
+.LLST94:
13099
+ .8byte .LVL298
13100
+ .8byte .LVL316
13101
+ .2byte 0x2
13102
+ .byte 0x30
13103
+ .byte 0x9f
13104
+ .8byte .LVL317
13105
+ .8byte .LVL394
13106
+ .2byte 0x2
13107
+ .byte 0x30
13108
+ .byte 0x9f
13109
+ .8byte 0
13110
+ .8byte 0
13111
+.LLST95:
13112
+ .8byte .LVL299
13113
+ .8byte .LVL316
13114
+ .2byte 0x2
13115
+ .byte 0x30
13116
+ .byte 0x9f
13117
+ .8byte .LVL317
13118
+ .8byte .LVL394
13119
+ .2byte 0x2
13120
+ .byte 0x30
13121
+ .byte 0x9f
13122
+ .8byte 0
13123
+ .8byte 0
13124
+.LLST96:
13125
+ .8byte .LVL300
13126
+ .8byte .LVL316
13127
+ .2byte 0x2
13128
+ .byte 0x30
13129
+ .byte 0x9f
13130
+ .8byte .LVL317
13131
+ .8byte .LVL394
13132
+ .2byte 0x2
13133
+ .byte 0x30
13134
+ .byte 0x9f
13135
+ .8byte 0
13136
+ .8byte 0
13137
+.LLST97:
13138
+ .8byte .LVL301
13139
+ .8byte .LVL316
13140
+ .2byte 0x2
13141
+ .byte 0x4f
13142
+ .byte 0x9f
13143
+ .8byte .LVL317
13144
+ .8byte .LVL394
13145
+ .2byte 0x2
13146
+ .byte 0x4f
13147
+ .byte 0x9f
13148
+ .8byte 0
13149
+ .8byte 0
13150
+.LLST98:
13151
+ .8byte .LVL302
13152
+ .8byte .LVL316
13153
+ .2byte 0x2
13154
+ .byte 0x3b
13155
+ .byte 0x9f
13156
+ .8byte .LVL317
13157
+ .8byte .LVL394
13158
+ .2byte 0x2
13159
+ .byte 0x3b
13160
+ .byte 0x9f
13161
+ .8byte 0
13162
+ .8byte 0
13163
+.LLST99:
13164
+ .8byte .LVL303
13165
+ .8byte .LVL316
13166
+ .2byte 0x2
13167
+ .byte 0x38
13168
+ .byte 0x9f
13169
+ .8byte .LVL317
13170
+ .8byte .LVL394
13171
+ .2byte 0x2
13172
+ .byte 0x38
13173
+ .byte 0x9f
13174
+ .8byte 0
13175
+ .8byte 0
13176
+.LLST100:
13177
+ .8byte .LVL304
13178
+ .8byte .LVL316
13179
+ .2byte 0x2
13180
+ .byte 0x30
13181
+ .byte 0x9f
13182
+ .8byte .LVL317
13183
+ .8byte .LVL394
13184
+ .2byte 0x2
13185
+ .byte 0x30
13186
+ .byte 0x9f
13187
+ .8byte 0
13188
+ .8byte 0
13189
+.LLST101:
13190
+ .8byte .LVL305
13191
+ .8byte .LVL316
13192
+ .2byte 0x2
13193
+ .byte 0x30
13194
+ .byte 0x9f
13195
+ .8byte .LVL317
13196
+ .8byte .LVL394
13197
+ .2byte 0x2
13198
+ .byte 0x30
13199
+ .byte 0x9f
13200
+ .8byte 0
13201
+ .8byte 0
13202
+.LLST102:
13203
+ .8byte .LVL306
13204
+ .8byte .LVL316
13205
+ .2byte 0x2
13206
+ .byte 0x30
13207
+ .byte 0x9f
13208
+ .8byte .LVL317
13209
+ .8byte .LVL394
13210
+ .2byte 0x2
13211
+ .byte 0x30
13212
+ .byte 0x9f
13213
+ .8byte 0
13214
+ .8byte 0
13215
+.LLST103:
13216
+ .8byte .LVL307
13217
+ .8byte .LVL315
13218
+ .2byte 0x1
13219
+ .byte 0x69
13220
+ .8byte .LVL317
13221
+ .8byte .LVL394
13222
+ .2byte 0x1
13223
+ .byte 0x69
13224
+ .8byte 0
13225
+ .8byte 0
13226
+.LLST104:
13227
+ .8byte .LVL308
13228
+ .8byte .LVL313
13229
+ .2byte 0x1
13230
+ .byte 0x65
13231
+ .8byte .LVL317
13232
+ .8byte .LVL332
13233
+ .2byte 0x1
13234
+ .byte 0x65
13235
+ .8byte 0
13236
+ .8byte 0
13237
+.LLST105:
13238
+ .8byte .LVL309
13239
+ .8byte .LVL316
13240
+ .2byte 0x6
13241
+ .byte 0xc
13242
+ .4byte 0x10001
13243
+ .byte 0x9f
13244
+ .8byte .LVL317
13245
+ .8byte .LVL394
13246
+ .2byte 0x6
13247
+ .byte 0xc
13248
+ .4byte 0x10001
13249
+ .byte 0x9f
13250
+ .8byte 0
13251
+ .8byte 0
13252
+.LLST106:
13253
+ .8byte .LVL314
13254
+ .8byte .LVL316
13255
+ .2byte 0x5
13256
+ .byte 0x11
13257
+ .sleb128 -65533
13258
+ .byte 0x9f
13259
+ .8byte 0
13260
+ .8byte 0
13261
+.LLST107:
13262
+ .8byte .LVL317
13263
+ .8byte .LVL394
13264
+ .2byte 0x6
13265
+ .byte 0x11
13266
+ .sleb128 -16762368
13267
+ .byte 0x9f
13268
+ .8byte 0
13269
+ .8byte 0
13270
+.LLST108:
13271
+ .8byte .LVL319
13272
+ .8byte .LVL394
13273
+ .2byte 0x3
13274
+ .byte 0x8
13275
+ .byte 0xf0
13276
+ .byte 0x9f
13277
+ .8byte 0
13278
+ .8byte 0
13279
+.LLST109:
13280
+ .8byte .LVL320
13281
+ .8byte .LVL394
13282
+ .2byte 0x2
13283
+ .byte 0x31
13284
+ .byte 0x9f
13285
+ .8byte 0
13286
+ .8byte 0
13287
+.LLST110:
13288
+ .8byte .LVL321
13289
+ .8byte .LVL394
13290
+ .2byte 0x3
13291
+ .byte 0x8
13292
+ .byte 0x7a
13293
+ .byte 0x9f
13294
+ .8byte 0
13295
+ .8byte 0
13296
+.LLST111:
13297
+ .8byte .LVL322
13298
+ .8byte .LVL394
13299
+ .2byte 0x2
13300
+ .byte 0x45
13301
+ .byte 0x9f
13302
+ .8byte 0
13303
+ .8byte 0
13304
+.LLST112:
13305
+ .8byte .LVL323
13306
+ .8byte .LVL394
13307
+ .2byte 0x3
13308
+ .byte 0x8
13309
+ .byte 0xdc
13310
+ .byte 0x9f
13311
+ .8byte 0
13312
+ .8byte 0
13313
+.LLST113:
13314
+ .8byte .LVL324
13315
+ .8byte .LVL394
13316
+ .2byte 0x3
13317
+ .byte 0x8
13318
+ .byte 0x92
13319
+ .byte 0x9f
13320
+ .8byte 0
13321
+ .8byte 0
13322
+.LLST114:
13323
+ .8byte .LVL325
13324
+ .8byte .LVL394
13325
+ .2byte 0x3
13326
+ .byte 0x8
13327
+ .byte 0x79
13328
+ .byte 0x9f
13329
+ .8byte 0
13330
+ .8byte 0
13331
+.LLST115:
13332
+ .8byte .LVL326
13333
+ .8byte .LVL394
13334
+ .2byte 0x3
13335
+ .byte 0x8
13336
+ .byte 0x81
13337
+ .byte 0x9f
13338
+ .8byte 0
13339
+ .8byte 0
13340
+.LLST116:
13341
+ .8byte .LVL327
13342
+ .8byte .LVL394
13343
+ .2byte 0x3
13344
+ .byte 0x8
13345
+ .byte 0x7e
13346
+ .byte 0x9f
13347
+ .8byte 0
13348
+ .8byte 0
13349
+.LLST117:
13350
+ .8byte .LVL328
13351
+ .8byte .LVL394
13352
+ .2byte 0x3
13353
+ .byte 0x8
13354
+ .byte 0x21
13355
+ .byte 0x9f
13356
+ .8byte 0
13357
+ .8byte 0
13358
+.LLST118:
13359
+ .8byte .LVL329
13360
+ .8byte .LVL394
13361
+ .2byte 0x2
13362
+ .byte 0x41
13363
+ .byte 0x9f
13364
+ .8byte 0
13365
+ .8byte 0
13366
+.LLST119:
13367
+ .8byte .LVL330
13368
+ .8byte .LVL394
13369
+ .2byte 0x3
13370
+ .byte 0x8
13371
+ .byte 0x9d
13372
+ .byte 0x9f
13373
+ .8byte 0
13374
+ .8byte 0
13375
+.LLST120:
13376
+ .8byte .LVL331
13377
+ .8byte .LVL394
13378
+ .2byte 0x2
13379
+ .byte 0x32
13380
+ .byte 0x9f
13381
+ .8byte 0
13382
+ .8byte 0
13383
+.LLST121:
13384
+ .8byte .LVL333
13385
+ .8byte .LVL394
13386
+ .2byte 0x2
13387
+ .byte 0x30
13388
+ .byte 0x9f
13389
+ .8byte 0
13390
+ .8byte 0
13391
+.LLST122:
13392
+ .8byte .LVL334
13393
+ .8byte .LVL394
13394
+ .2byte 0x2
13395
+ .byte 0x30
13396
+ .byte 0x9f
13397
+ .8byte 0
13398
+ .8byte 0
13399
+.LLST123:
13400
+ .8byte .LVL335
13401
+ .8byte .LVL394
13402
+ .2byte 0x6
13403
+ .byte 0xc
13404
+ .4byte 0x10001
13405
+ .byte 0x9f
13406
+ .8byte 0
13407
+ .8byte 0
13408
+.LLST124:
13409
+ .8byte .LVL339
13410
+ .8byte .LVL394
13411
+ .2byte 0x6
13412
+ .byte 0x11
13413
+ .sleb128 -16776704
13414
+ .byte 0x9f
13415
+ .8byte 0
13416
+ .8byte 0
13417
+.LLST125:
13418
+ .8byte .LVL341
13419
+ .8byte .LVL394
13420
+ .2byte 0x5
13421
+ .byte 0x11
13422
+ .sleb128 -65535
13423
+ .byte 0x9f
13424
+ .8byte 0
13425
+ .8byte 0
13426
+.LLST126:
13427
+ .8byte .LVL342
13428
+ .8byte .LVL394
13429
+ .2byte 0x3
13430
+ .byte 0x8
13431
+ .byte 0xfb
13432
+ .byte 0x9f
13433
+ .8byte 0
13434
+ .8byte 0
13435
+.LLST127:
13436
+ .8byte .LVL343
13437
+ .8byte .LVL394
13438
+ .2byte 0x2
13439
+ .byte 0x30
13440
+ .byte 0x9f
13441
+ .8byte 0
13442
+ .8byte 0
13443
+.LLST128:
13444
+ .8byte .LVL344
13445
+ .8byte .LVL394
13446
+ .2byte 0x6
13447
+ .byte 0xc
13448
+ .4byte 0x10001
13449
+ .byte 0x9f
13450
+ .8byte 0
13451
+ .8byte 0
13452
+.LLST129:
13453
+ .8byte .LVL348
13454
+ .8byte .LVL394
13455
+ .2byte 0x5
13456
+ .byte 0x11
13457
+ .sleb128 -65534
13458
+ .byte 0x9f
13459
+ .8byte 0
13460
+ .8byte 0
13461
+.LLST130:
13462
+ .8byte .LVL350
13463
+ .8byte .LVL394
13464
+ .2byte 0x3
13465
+ .byte 0x8
13466
+ .byte 0xc0
13467
+ .byte 0x9f
13468
+ .8byte 0
13469
+ .8byte 0
13470
+.LLST131:
13471
+ .8byte .LVL351
13472
+ .8byte .LVL354
13473
+ .2byte 0x1
13474
+ .byte 0x51
13475
+ .8byte 0
13476
+ .8byte 0
13477
+.LLST132:
13478
+ .8byte .LVL352
13479
+ .8byte .LVL394
13480
+ .2byte 0x1
13481
+ .byte 0x6a
13482
+ .8byte 0
13483
+ .8byte 0
13484
+.LLST133:
13485
+ .8byte .LVL353
13486
+ .8byte .LVL394
13487
+ .2byte 0x6
13488
+ .byte 0xc
13489
+ .4byte 0x10001
13490
+ .byte 0x9f
13491
+ .8byte 0
13492
+ .8byte 0
13493
+.LLST134:
13494
+ .8byte .LVL358
13495
+ .8byte .LVL394
13496
+ .2byte 0x6
13497
+ .byte 0x11
13498
+ .sleb128 -16762368
13499
+ .byte 0x9f
13500
+ .8byte 0
13501
+ .8byte 0
13502
+.LLST135:
13503
+ .8byte .LVL360
13504
+ .8byte .LVL394
13505
+ .2byte 0x5
13506
+ .byte 0x11
13507
+ .sleb128 -65535
13508
+ .byte 0x9f
13509
+ .8byte 0
13510
+ .8byte 0
13511
+.LLST136:
13512
+ .8byte .LVL361
13513
+ .8byte .LVL394
13514
+ .2byte 0x3
13515
+ .byte 0x8
13516
+ .byte 0xff
13517
+ .byte 0x9f
13518
+ .8byte 0
13519
+ .8byte 0
13520
+.LLST137:
13521
+ .8byte .LVL362
13522
+ .8byte .LVL394
13523
+ .2byte 0x2
13524
+ .byte 0x3a
13525
+ .byte 0x9f
13526
+ .8byte 0
13527
+ .8byte 0
13528
+.LLST138:
13529
+ .8byte .LVL363
13530
+ .8byte .LVL394
13531
+ .2byte 0x6
13532
+ .byte 0xc
13533
+ .4byte 0x10001
13534
+ .byte 0x9f
13535
+ .8byte 0
13536
+ .8byte 0
13537
+.LLST139:
13538
+ .8byte .LVL367
13539
+ .8byte .LVL394
13540
+ .2byte 0x5
13541
+ .byte 0x11
13542
+ .sleb128 -65534
13543
+ .byte 0x9f
13544
+ .8byte 0
13545
+ .8byte 0
13546
+.LLST140:
13547
+ .8byte .LVL369
13548
+ .8byte .LVL394
13549
+ .2byte 0x2
13550
+ .byte 0x31
13551
+ .byte 0x9f
13552
+ .8byte 0
13553
+ .8byte 0
13554
+.LLST141:
13555
+ .8byte .LVL370
13556
+ .8byte .LVL394
13557
+ .2byte 0x3
13558
+ .byte 0x8
13559
+ .byte 0xbf
13560
+ .byte 0x9f
13561
+ .8byte 0
13562
+ .8byte 0
13563
+.LLST142:
13564
+ .8byte .LVL371
13565
+ .8byte .LVL394
13566
+ .2byte 0x2
13567
+ .byte 0x30
13568
+ .byte 0x9f
13569
+ .8byte 0
13570
+ .8byte 0
13571
+.LLST143:
13572
+ .8byte .LVL372
13573
+ .8byte .LVL394
13574
+ .2byte 0x6
13575
+ .byte 0xc
13576
+ .4byte 0x10001
13577
+ .byte 0x9f
13578
+ .8byte 0
13579
+ .8byte 0
13580
+.LLST144:
13581
+ .8byte .LVL381
13582
+ .8byte .LVL394
13583
+ .2byte 0x5
13584
+ .byte 0x11
13585
+ .sleb128 -65535
13586
+ .byte 0x9f
13587
+ .8byte 0
13588
+ .8byte 0
13589
+.LLST145:
13590
+ .8byte .LVL383
13591
+ .8byte .LVL394
13592
+ .2byte 0x2
13593
+ .byte 0x32
13594
+ .byte 0x9f
13595
+ .8byte 0
13596
+ .8byte 0
13597
+.LLST146:
13598
+ .8byte .LVL384
13599
+ .8byte .LVL394
13600
+ .2byte 0x3
13601
+ .byte 0x8
13602
+ .byte 0xbf
13603
+ .byte 0x9f
13604
+ .8byte 0
13605
+ .8byte 0
13606
+.LLST147:
13607
+ .8byte .LVL385
13608
+ .8byte .LVL394
13609
+ .2byte 0x6
13610
+ .byte 0xc
13611
+ .4byte 0x10001
13612
+ .byte 0x9f
13613
+ .8byte 0
13614
+ .8byte 0
13615
+.LLST148:
13616
+ .8byte .LVL273
13617
+ .8byte .LVL276
13618
+ .2byte 0x1
13619
+ .byte 0x67
13620
+ .8byte .LVL283
13621
+ .8byte .LVL284
13622
+ .2byte 0x1
13623
+ .byte 0x67
13624
+ .8byte 0
13625
+ .8byte 0
13626
+.LLST149:
13627
+ .8byte .LVL273
13628
+ .8byte .LVL280
13629
+ .2byte 0x1
13630
+ .byte 0x69
13631
+ .8byte .LVL283
13632
+ .8byte .LVL285
13633
+ .2byte 0x1
13634
+ .byte 0x69
13635
+ .8byte 0
13636
+ .8byte 0
13637
+.LLST150:
13638
+ .8byte .LVL273
13639
+ .8byte .LVL280
13640
+ .2byte 0x1
13641
+ .byte 0x6c
13642
+ .8byte .LVL283
13643
+ .8byte .LVL285
13644
+ .2byte 0x1
13645
+ .byte 0x6c
13646
+ .8byte 0
13647
+ .8byte 0
13648
+.LLST151:
13649
+ .8byte .LVL273
13650
+ .8byte .LVL280
13651
+ .2byte 0x1
13652
+ .byte 0x68
13653
+ .8byte .LVL283
13654
+ .8byte .LVL285
13655
+ .2byte 0x1
13656
+ .byte 0x68
13657
+ .8byte 0
13658
+ .8byte 0
13659
+.LLST152:
13660
+ .8byte .LVL275
13661
+ .8byte .LVL276
13662
+ .2byte 0xd
13663
+ .byte 0x8f
13664
+ .sleb128 254
13665
+ .byte 0x94
13666
+ .byte 0x2
13667
+ .byte 0x20
13668
+ .byte 0x87
13669
+ .sleb128 0
13670
+ .byte 0x8
13671
+ .byte 0xff
13672
+ .byte 0x1a
13673
+ .byte 0x1a
13674
+ .byte 0x9f
13675
+ .8byte .LVL283
13676
+ .8byte .LVL284
13677
+ .2byte 0xf
13678
+ .byte 0x8f
13679
+ .sleb128 254
13680
+ .byte 0x94
13681
+ .byte 0x2
13682
+ .byte 0x20
13683
+ .byte 0x87
13684
+ .sleb128 0
13685
+ .byte 0x8
13686
+ .byte 0xff
13687
+ .byte 0x1a
13688
+ .byte 0x38
13689
+ .byte 0x24
13690
+ .byte 0x1a
13691
+ .byte 0x9f
13692
+ .8byte 0
13693
+ .8byte 0
13694
+.LLST153:
13695
+ .8byte .LVL274
13696
+ .8byte .LVL277
13697
+ .2byte 0x1
13698
+ .byte 0x50
13699
+ .8byte .LVL283
13700
+ .8byte .LVL285
13701
+ .2byte 0x1
13702
+ .byte 0x50
13703
+ .8byte 0
13704
+ .8byte 0
13705
+.LLST30:
13706
+ .8byte .LVL66
13707
+ .8byte .LVL67-1
13708
+ .2byte 0x1
13709
+ .byte 0x50
13710
+ .8byte .LVL67-1
13711
+ .8byte .LFE269
13712
+ .2byte 0x4
13713
+ .byte 0xf3
13714
+ .uleb128 0x1
13715
+ .byte 0x50
13716
+ .byte 0x9f
13717
+ .8byte 0
13718
+ .8byte 0
13719
+.LLST31:
13720
+ .8byte .LVL66
13721
+ .8byte .LVL67-1
13722
+ .2byte 0x1
13723
+ .byte 0x51
13724
+ .8byte .LVL67-1
13725
+ .8byte .LVL72
13726
+ .2byte 0x1
13727
+ .byte 0x6a
13728
+ .8byte .LVL72
13729
+ .8byte .LVL73
13730
+ .2byte 0x4
13731
+ .byte 0xf3
13732
+ .uleb128 0x1
13733
+ .byte 0x51
13734
+ .byte 0x9f
13735
+ .8byte .LVL73
13736
+ .8byte .LFE269
13737
+ .2byte 0x1
13738
+ .byte 0x6a
13739
+ .8byte 0
13740
+ .8byte 0
13741
+.LLST32:
13742
+ .8byte .LVL66
13743
+ .8byte .LVL67-1
13744
+ .2byte 0x1
13745
+ .byte 0x52
13746
+ .8byte .LVL67-1
13747
+ .8byte .LVL67
13748
+ .2byte 0x1
13749
+ .byte 0x68
13750
+ .8byte .LVL67
13751
+ .8byte .LVL71
13752
+ .2byte 0x1
13753
+ .byte 0x64
13754
+ .8byte .LVL71
13755
+ .8byte .LVL73
13756
+ .2byte 0x6
13757
+ .byte 0xf3
13758
+ .uleb128 0x1
13759
+ .byte 0x52
13760
+ .byte 0x31
13761
+ .byte 0x26
13762
+ .byte 0x9f
13763
+ .8byte .LVL73
13764
+ .8byte .LFE269
13765
+ .2byte 0x1
13766
+ .byte 0x64
13767
+ .8byte 0
13768
+ .8byte 0
13769
+.LLST33:
13770
+ .8byte .LVL66
13771
+ .8byte .LVL67-1
13772
+ .2byte 0x1
13773
+ .byte 0x53
13774
+ .8byte .LVL67-1
13775
+ .8byte .LVL70
13776
+ .2byte 0x1
13777
+ .byte 0x65
13778
+ .8byte .LVL70
13779
+ .8byte .LFE269
13780
+ .2byte 0x4
13781
+ .byte 0xf3
13782
+ .uleb128 0x1
13783
+ .byte 0x53
13784
+ .byte 0x9f
13785
+ .8byte 0
13786
+ .8byte 0
13787
+.LLST34:
13788
+ .8byte .LVL66
13789
+ .8byte .LVL70
13790
+ .2byte 0x2
13791
+ .byte 0x30
13792
+ .byte 0x9f
13793
+ .8byte .LVL73
13794
+ .8byte .LVL83
13795
+ .2byte 0x2
13796
+ .byte 0x30
13797
+ .byte 0x9f
13798
+ .8byte .LVL83
13799
+ .8byte .LVL84
13800
+ .2byte 0x1
13801
+ .byte 0x50
13802
+ .8byte .LVL87
13803
+ .8byte .LVL88
13804
+ .2byte 0x1
13805
+ .byte 0x50
13806
+ .8byte .LVL104
13807
+ .8byte .LVL106
13808
+ .2byte 0x1
13809
+ .byte 0x50
13810
+ .8byte .LVL110
13811
+ .8byte .LVL112
13812
+ .2byte 0x1
13813
+ .byte 0x50
13814
+ .8byte .LVL130
13815
+ .8byte .LVL132
13816
+ .2byte 0x1
13817
+ .byte 0x50
13818
+ .8byte .LVL137
13819
+ .8byte .LVL139
13820
+ .2byte 0x1
13821
+ .byte 0x50
13822
+ .8byte .LVL146
13823
+ .8byte .LVL148
13824
+ .2byte 0x1
13825
+ .byte 0x50
13826
+ .8byte .LVL152
13827
+ .8byte .LVL154
13828
+ .2byte 0x1
13829
+ .byte 0x50
13830
+ .8byte .LVL160
13831
+ .8byte .LVL162
13832
+ .2byte 0x1
13833
+ .byte 0x50
13834
+ .8byte .LVL167
13835
+ .8byte .LVL168
13836
+ .2byte 0x1
13837
+ .byte 0x50
13838
+ .8byte .LVL169
13839
+ .8byte .LVL170
13840
+ .2byte 0x1
13841
+ .byte 0x50
13842
+ .8byte .LVL171
13843
+ .8byte .LVL172
13844
+ .2byte 0x1
13845
+ .byte 0x50
13846
+ .8byte .LVL176
13847
+ .8byte .LVL177
13848
+ .2byte 0x1
13849
+ .byte 0x50
13850
+ .8byte .LVL178
13851
+ .8byte .LVL179
13852
+ .2byte 0x1
13853
+ .byte 0x50
13854
+ .8byte .LVL180
13855
+ .8byte .LVL181
13856
+ .2byte 0x1
13857
+ .byte 0x50
13858
+ .8byte .LVL187
13859
+ .8byte .LVL189
13860
+ .2byte 0x1
13861
+ .byte 0x50
13862
+ .8byte .LVL193
13863
+ .8byte .LVL195
13864
+ .2byte 0x1
13865
+ .byte 0x50
13866
+ .8byte .LVL198
13867
+ .8byte .LFE269
13868
+ .2byte 0x1
13869
+ .byte 0x50
13870
+ .8byte 0
13871
+ .8byte 0
13872
+.LLST35:
13873
+ .8byte .LVL67
13874
+ .8byte .LVL68
13875
+ .2byte 0x1
13876
+ .byte 0x50
13877
+ .8byte .LVL68
13878
+ .8byte .LVL69
13879
+ .2byte 0x1
13880
+ .byte 0x67
13881
+ .8byte .LVL73
13882
+ .8byte .LFE269
13883
+ .2byte 0x1
13884
+ .byte 0x67
13885
+ .8byte 0
13886
+ .8byte 0
13887
+.LLST36:
13888
+ .8byte .LVL74
13889
+ .8byte .LVL86
13890
+ .2byte 0x4
13891
+ .byte 0x40
13892
+ .byte 0x3c
13893
+ .byte 0x24
13894
+ .byte 0x9f
13895
+ .8byte .LVL87
13896
+ .8byte .LFE269
13897
+ .2byte 0x4
13898
+ .byte 0x40
13899
+ .byte 0x3c
13900
+ .byte 0x24
13901
+ .byte 0x9f
13902
+ .8byte 0
13903
+ .8byte 0
13904
+.LLST37:
13905
+ .8byte .LVL75
13906
+ .8byte .LVL86
13907
+ .2byte 0x6
13908
+ .byte 0xc
13909
+ .4byte 0x40004
13910
+ .byte 0x9f
13911
+ .8byte .LVL87
13912
+ .8byte .LFE269
13913
+ .2byte 0x6
13914
+ .byte 0xc
13915
+ .4byte 0x40004
13916
+ .byte 0x9f
13917
+ .8byte 0
13918
+ .8byte 0
13919
+.LLST38:
13920
+ .8byte .LVL76
13921
+ .8byte .LVL86
13922
+ .2byte 0x5
13923
+ .byte 0x11
13924
+ .sleb128 -65536
13925
+ .byte 0x9f
13926
+ .8byte .LVL87
13927
+ .8byte .LFE269
13928
+ .2byte 0x5
13929
+ .byte 0x11
13930
+ .sleb128 -65536
13931
+ .byte 0x9f
13932
+ .8byte 0
13933
+ .8byte 0
13934
+.LLST39:
13935
+ .8byte .LVL77
13936
+ .8byte .LVL86
13937
+ .2byte 0x6
13938
+ .byte 0x11
13939
+ .sleb128 -16776704
13940
+ .byte 0x9f
13941
+ .8byte .LVL87
13942
+ .8byte .LFE269
13943
+ .2byte 0x6
13944
+ .byte 0x11
13945
+ .sleb128 -16776704
13946
+ .byte 0x9f
13947
+ .8byte 0
13948
+ .8byte 0
13949
+.LLST40:
13950
+ .8byte .LVL78
13951
+ .8byte .LVL86
13952
+ .2byte 0x5
13953
+ .byte 0x11
13954
+ .sleb128 -65534
13955
+ .byte 0x9f
13956
+ .8byte .LVL87
13957
+ .8byte .LFE269
13958
+ .2byte 0x5
13959
+ .byte 0x11
13960
+ .sleb128 -65534
13961
+ .byte 0x9f
13962
+ .8byte 0
13963
+ .8byte 0
13964
+.LLST41:
13965
+ .8byte .LVL79
13966
+ .8byte .LVL86
13967
+ .2byte 0x3
13968
+ .byte 0x8
13969
+ .byte 0xfc
13970
+ .byte 0x9f
13971
+ .8byte .LVL87
13972
+ .8byte .LFE269
13973
+ .2byte 0x3
13974
+ .byte 0x8
13975
+ .byte 0xfc
13976
+ .byte 0x9f
13977
+ .8byte 0
13978
+ .8byte 0
13979
+.LLST42:
13980
+ .8byte .LVL80
13981
+ .8byte .LVL86
13982
+ .2byte 0x2
13983
+ .byte 0x30
13984
+ .byte 0x9f
13985
+ .8byte .LVL87
13986
+ .8byte .LFE269
13987
+ .2byte 0x2
13988
+ .byte 0x30
13989
+ .byte 0x9f
13990
+ .8byte 0
13991
+ .8byte 0
13992
+.LLST43:
13993
+ .8byte .LVL81
13994
+ .8byte .LVL86
13995
+ .2byte 0x2
13996
+ .byte 0x30
13997
+ .byte 0x9f
13998
+ .8byte .LVL87
13999
+ .8byte .LFE269
14000
+ .2byte 0x2
14001
+ .byte 0x30
14002
+ .byte 0x9f
14003
+ .8byte 0
14004
+ .8byte 0
14005
+.LLST44:
14006
+ .8byte .LVL82
14007
+ .8byte .LVL86
14008
+ .2byte 0x6
14009
+ .byte 0xc
14010
+ .4byte 0x10001
14011
+ .byte 0x9f
14012
+ .8byte .LVL87
14013
+ .8byte .LFE269
14014
+ .2byte 0x6
14015
+ .byte 0xc
14016
+ .4byte 0x10001
14017
+ .byte 0x9f
14018
+ .8byte 0
14019
+ .8byte 0
14020
+.LLST45:
14021
+ .8byte .LVL102
14022
+ .8byte .LVL104-1
14023
+ .2byte 0x1
14024
+ .byte 0x55
14025
+ .8byte .LVL104-1
14026
+ .8byte .LVL165
14027
+ .2byte 0x6
14028
+ .byte 0x88
14029
+ .sleb128 0
14030
+ .byte 0x9
14031
+ .byte 0xf7
14032
+ .byte 0x24
14033
+ .byte 0x9f
14034
+ .8byte 0
14035
+ .8byte 0
14036
+.LLST46:
14037
+ .8byte .LVL142
14038
+ .8byte .LVL145
14039
+ .2byte 0x1
14040
+ .byte 0x51
14041
+ .8byte 0
14042
+ .8byte 0
14043
+.LLST47:
14044
+ .8byte .LVL143
14045
+ .8byte .LVL159
14046
+ .2byte 0x1
14047
+ .byte 0x65
14048
+ .8byte .LVL159
14049
+ .8byte .LFE269
14050
+ .2byte 0xa
14051
+ .byte 0xf3
14052
+ .uleb128 0x1
14053
+ .byte 0x53
14054
+ .byte 0xa
14055
+ .2byte 0xffff
14056
+ .byte 0x1a
14057
+ .byte 0x38
14058
+ .byte 0x25
14059
+ .byte 0x9f
14060
+ .8byte 0
14061
+ .8byte 0
14062
+.LLST55:
14063
+ .8byte .LVL212
14064
+ .8byte .LVL213-1
14065
+ .2byte 0x1
14066
+ .byte 0x50
14067
+ .8byte .LVL213-1
14068
+ .8byte .LVL221
14069
+ .2byte 0x1
14070
+ .byte 0x66
14071
+ .8byte .LVL221
14072
+ .8byte .LVL227
14073
+ .2byte 0x4
14074
+ .byte 0xf3
14075
+ .uleb128 0x1
14076
+ .byte 0x50
14077
+ .byte 0x9f
14078
+ .8byte .LVL227
14079
+ .8byte .LVL228
14080
+ .2byte 0x1
14081
+ .byte 0x66
14082
+ .8byte .LVL228
14083
+ .8byte .LFE268
14084
+ .2byte 0x4
14085
+ .byte 0xf3
14086
+ .uleb128 0x1
14087
+ .byte 0x50
14088
+ .byte 0x9f
14089
+ .8byte 0
14090
+ .8byte 0
14091
+.LLST56:
14092
+ .8byte .LVL212
14093
+ .8byte .LVL213-1
14094
+ .2byte 0x1
14095
+ .byte 0x51
14096
+ .8byte .LVL213-1
14097
+ .8byte .LVL217
14098
+ .2byte 0x4
14099
+ .byte 0xf3
14100
+ .uleb128 0x1
14101
+ .byte 0x51
14102
+ .byte 0x9f
14103
+ .8byte .LVL217
14104
+ .8byte .LVL225
14105
+ .2byte 0x1
14106
+ .byte 0x63
14107
+ .8byte .LVL227
14108
+ .8byte .LFE268
14109
+ .2byte 0x1
14110
+ .byte 0x63
14111
+ .8byte 0
14112
+ .8byte 0
14113
+.LLST57:
14114
+ .8byte .LVL212
14115
+ .8byte .LVL213-1
14116
+ .2byte 0x1
14117
+ .byte 0x52
14118
+ .8byte .LVL213-1
14119
+ .8byte .LVL222
14120
+ .2byte 0x1
14121
+ .byte 0x65
14122
+ .8byte .LVL222
14123
+ .8byte .LVL227
14124
+ .2byte 0x4
14125
+ .byte 0xf3
14126
+ .uleb128 0x1
14127
+ .byte 0x52
14128
+ .byte 0x9f
14129
+ .8byte .LVL227
14130
+ .8byte .LVL228
14131
+ .2byte 0x1
14132
+ .byte 0x65
14133
+ .8byte .LVL228
14134
+ .8byte .LFE268
14135
+ .2byte 0x4
14136
+ .byte 0xf3
14137
+ .uleb128 0x1
14138
+ .byte 0x52
14139
+ .byte 0x9f
14140
+ .8byte 0
14141
+ .8byte 0
14142
+.LLST58:
14143
+ .8byte .LVL212
14144
+ .8byte .LVL213-1
14145
+ .2byte 0x1
14146
+ .byte 0x53
14147
+ .8byte .LVL213-1
14148
+ .8byte .LVL222
14149
+ .2byte 0x1
14150
+ .byte 0x67
14151
+ .8byte .LVL222
14152
+ .8byte .LVL226
14153
+ .2byte 0x3
14154
+ .byte 0x87
14155
+ .sleb128 -1
14156
+ .byte 0x9f
14157
+ .8byte .LVL227
14158
+ .8byte .LVL228
14159
+ .2byte 0x1
14160
+ .byte 0x67
14161
+ .8byte .LVL228
14162
+ .8byte .LVL244
14163
+ .2byte 0x3
14164
+ .byte 0x87
14165
+ .sleb128 -1
14166
+ .byte 0x9f
14167
+ .8byte .LVL244
14168
+ .8byte .LFE268
14169
+ .2byte 0x1
14170
+ .byte 0x67
14171
+ .8byte 0
14172
+ .8byte 0
14173
+.LLST59:
14174
+ .8byte .LVL214
14175
+ .8byte .LVL215
14176
+ .2byte 0x1
14177
+ .byte 0x50
14178
+ .8byte .LVL215
14179
+ .8byte .LVL225
14180
+ .2byte 0x1
14181
+ .byte 0x64
14182
+ .8byte .LVL227
14183
+ .8byte .LFE268
14184
+ .2byte 0x1
14185
+ .byte 0x64
14186
+ .8byte 0
14187
+ .8byte 0
14188
+.LLST60:
14189
+ .8byte .LVL217
14190
+ .8byte .LVL218
14191
+ .2byte 0x1
14192
+ .byte 0x50
14193
+ .8byte .LVL218
14194
+ .8byte .LVL226
14195
+ .2byte 0x1
14196
+ .byte 0x68
14197
+ .8byte .LVL227
14198
+ .8byte .LFE268
14199
+ .2byte 0x1
14200
+ .byte 0x68
14201
+ .8byte 0
14202
+ .8byte 0
14203
+.LLST61:
14204
+ .8byte .LVL217
14205
+ .8byte .LVL224
14206
+ .2byte 0x1
14207
+ .byte 0x65
14208
+ .8byte .LVL227
14209
+ .8byte .LVL236
14210
+ .2byte 0x1
14211
+ .byte 0x65
14212
+ .8byte .LVL238
14213
+ .8byte .LVL241
14214
+ .2byte 0x1
14215
+ .byte 0x65
14216
+ .8byte .LVL241
14217
+ .8byte .LVL242
14218
+ .2byte 0x3
14219
+ .byte 0x85
14220
+ .sleb128 1
14221
+ .byte 0x9f
14222
+ .8byte .LVL242
14223
+ .8byte .LVL245
14224
+ .2byte 0x3
14225
+ .byte 0x85
14226
+ .sleb128 2
14227
+ .byte 0x9f
14228
+ .8byte .LVL245
14229
+ .8byte .LFE268
14230
+ .2byte 0x1
14231
+ .byte 0x65
14232
+ .8byte 0
14233
+ .8byte 0
14234
+.LLST62:
14235
+ .8byte .LVL241
14236
+ .8byte .LVL243
14237
+ .2byte 0x1
14238
+ .byte 0x50
14239
+ .8byte 0
14240
+ .8byte 0
14241
+.LLST63:
14242
+ .8byte .LVL217
14243
+ .8byte .LVL222
14244
+ .2byte 0x2
14245
+ .byte 0x30
14246
+ .byte 0x9f
14247
+ .8byte .LVL222
14248
+ .8byte .LVL223
14249
+ .2byte 0x1
14250
+ .byte 0x66
14251
+ .8byte .LVL227
14252
+ .8byte .LVL228
14253
+ .2byte 0x2
14254
+ .byte 0x30
14255
+ .byte 0x9f
14256
+ .8byte .LVL228
14257
+ .8byte .LVL234
14258
+ .2byte 0x1
14259
+ .byte 0x66
14260
+ .8byte .LVL234
14261
+ .8byte .LVL235
14262
+ .2byte 0x1
14263
+ .byte 0x50
14264
+ .8byte .LVL235
14265
+ .8byte .LVL238
14266
+ .2byte 0x1
14267
+ .byte 0x66
14268
+ .8byte .LVL238
14269
+ .8byte .LVL239
14270
+ .2byte 0x1
14271
+ .byte 0x50
14272
+ .8byte .LVL239
14273
+ .8byte .LFE268
14274
+ .2byte 0x1
14275
+ .byte 0x66
14276
+ .8byte 0
14277
+ .8byte 0
14278
+.LLST64:
14279
+ .8byte .LVL220
14280
+ .8byte .LVL227
14281
+ .2byte 0x6
14282
+ .byte 0xc
14283
+ .4byte 0x10001
14284
+ .byte 0x9f
14285
+ .8byte .LVL228
14286
+ .8byte .LFE268
14287
+ .2byte 0x6
14288
+ .byte 0xc
14289
+ .4byte 0x10001
14290
+ .byte 0x9f
14291
+ .8byte 0
14292
+ .8byte 0
14293
+.LLST65:
14294
+ .8byte .LVL229
14295
+ .8byte .LVL231
14296
+ .2byte 0x1
14297
+ .byte 0x51
14298
+ .8byte .LVL231
14299
+ .8byte .LVL232
14300
+ .2byte 0x6
14301
+ .byte 0x84
14302
+ .sleb128 0
14303
+ .byte 0x6
14304
+ .byte 0x23
14305
+ .uleb128 0x104
14306
+ .8byte .LVL232
14307
+ .8byte .LVL236
14308
+ .2byte 0x8
14309
+ .byte 0x83
14310
+ .sleb128 -1
14311
+ .byte 0x11
14312
+ .sleb128 -65536
14313
+ .byte 0x21
14314
+ .byte 0x9f
14315
+ .8byte .LVL238
14316
+ .8byte .LFE268
14317
+ .2byte 0x8
14318
+ .byte 0x83
14319
+ .sleb128 -1
14320
+ .byte 0x11
14321
+ .sleb128 -65536
14322
+ .byte 0x21
14323
+ .byte 0x9f
14324
+ .8byte 0
14325
+ .8byte 0
14326
+.LLST66:
14327
+ .8byte .LVL230
14328
+ .8byte .LVL236
14329
+ .2byte 0x6
14330
+ .byte 0xc
14331
+ .4byte 0x10001
14332
+ .byte 0x9f
14333
+ .8byte .LVL238
14334
+ .8byte .LFE268
14335
+ .2byte 0x6
14336
+ .byte 0xc
14337
+ .4byte 0x10001
14338
+ .byte 0x9f
14339
+ .8byte 0
14340
+ .8byte 0
14341
+.LLST68:
14342
+ .8byte .LVL240
14343
+ .8byte .LVL243
14344
+ .2byte 0x1
14345
+ .byte 0x50
14346
+ .8byte 0
14347
+ .8byte 0
14348
+.LLST67:
14349
+ .8byte .LVL236
14350
+ .8byte .LVL238
14351
+ .2byte 0x4
14352
+ .byte 0x40
14353
+ .byte 0x3c
14354
+ .byte 0x24
14355
+ .byte 0x9f
14356
+ .8byte 0
14357
+ .8byte 0
14358
+.LLST0:
14359
+ .8byte .LVL0
14360
+ .8byte .LVL1
14361
+ .2byte 0x1
14362
+ .byte 0x51
14363
+ .8byte .LVL1
14364
+ .8byte .LFE263
14365
+ .2byte 0x4
14366
+ .byte 0xf3
14367
+ .uleb128 0x1
14368
+ .byte 0x51
14369
+ .byte 0x9f
14370
+ .8byte 0
14371
+ .8byte 0
14372
+.LLST16:
14373
+ .8byte .LVL28
14374
+ .8byte .LVL31
14375
+ .2byte 0x1
14376
+ .byte 0x50
14377
+ .8byte .LVL31
14378
+ .8byte .LFE262
14379
+ .2byte 0x4
14380
+ .byte 0xf3
14381
+ .uleb128 0x1
14382
+ .byte 0x50
14383
+ .byte 0x9f
14384
+ .8byte 0
14385
+ .8byte 0
14386
+.LLST17:
14387
+ .8byte .LVL28
14388
+ .8byte .LVL29
14389
+ .2byte 0x1
14390
+ .byte 0x51
14391
+ .8byte .LVL29
14392
+ .8byte .LVL33
14393
+ .2byte 0x1
14394
+ .byte 0x63
14395
+ .8byte .LVL33
14396
+ .8byte .LFE262
14397
+ .2byte 0x4
14398
+ .byte 0xf3
14399
+ .uleb128 0x1
14400
+ .byte 0x51
14401
+ .byte 0x9f
14402
+ .8byte 0
14403
+ .8byte 0
14404
+.LLST18:
14405
+ .8byte .LVL28
14406
+ .8byte .LVL32-1
14407
+ .2byte 0x1
14408
+ .byte 0x52
14409
+ .8byte .LVL32-1
14410
+ .8byte .LFE262
14411
+ .2byte 0x4
14412
+ .byte 0xf3
14413
+ .uleb128 0x1
14414
+ .byte 0x52
14415
+ .byte 0x9f
14416
+ .8byte 0
14417
+ .8byte 0
14418
+.LLST19:
14419
+ .8byte .LVL28
14420
+ .8byte .LVL32-1
14421
+ .2byte 0x1
14422
+ .byte 0x53
14423
+ .8byte .LVL32-1
14424
+ .8byte .LFE262
14425
+ .2byte 0x4
14426
+ .byte 0xf3
14427
+ .uleb128 0x1
14428
+ .byte 0x53
14429
+ .byte 0x9f
14430
+ .8byte 0
14431
+ .8byte 0
14432
+.LLST20:
14433
+ .8byte .LVL35
14434
+ .8byte .LVL38
14435
+ .2byte 0x3
14436
+ .byte 0x83
14437
+ .sleb128 -1
14438
+ .byte 0x9f
14439
+ .8byte .LVL38
14440
+ .8byte .LVL39
14441
+ .2byte 0x1
14442
+ .byte 0x63
14443
+ .8byte .LVL39
14444
+ .8byte .LVL41
14445
+ .2byte 0x3
14446
+ .byte 0x83
14447
+ .sleb128 -1
14448
+ .byte 0x9f
14449
+ .8byte .LVL41
14450
+ .8byte .LVL42
14451
+ .2byte 0x1
14452
+ .byte 0x63
14453
+ .8byte 0
14454
+ .8byte 0
14455
+.LLST21:
14456
+ .8byte .LVL37
14457
+ .8byte .LVL40-1
14458
+ .2byte 0x1
14459
+ .byte 0x51
14460
+ .8byte .LVL41
14461
+ .8byte .LFE278
14462
+ .2byte 0x1
14463
+ .byte 0x51
14464
+ .8byte 0
14465
+ .8byte 0
14466
+.LLST22:
14467
+ .8byte .LVL36
14468
+ .8byte .LVL40-1
14469
+ .2byte 0x1
14470
+ .byte 0x51
14471
+ .8byte .LVL41
14472
+ .8byte .LFE278
14473
+ .2byte 0x1
14474
+ .byte 0x51
14475
+ .8byte 0
14476
+ .8byte 0
14477
+.LLST23:
14478
+ .8byte .LVL43
14479
+ .8byte .LVL46
14480
+ .2byte 0x3
14481
+ .byte 0x83
14482
+ .sleb128 -1
14483
+ .byte 0x9f
14484
+ .8byte .LVL46
14485
+ .8byte .LVL48
14486
+ .2byte 0x1
14487
+ .byte 0x63
14488
+ .8byte .LVL48
14489
+ .8byte .LVL50
14490
+ .2byte 0x3
14491
+ .byte 0x83
14492
+ .sleb128 -1
14493
+ .byte 0x9f
14494
+ .8byte .LVL51
14495
+ .8byte .LFE279
14496
+ .2byte 0x1
14497
+ .byte 0x63
14498
+ .8byte 0
14499
+ .8byte 0
14500
+.LLST24:
14501
+ .8byte .LVL45
14502
+ .8byte .LVL47
14503
+ .2byte 0x1
14504
+ .byte 0x50
14505
+ .8byte .LVL49
14506
+ .8byte .LVL50
14507
+ .2byte 0x1
14508
+ .byte 0x50
14509
+ .8byte .LVL51
14510
+ .8byte .LVL52
14511
+ .2byte 0x1
14512
+ .byte 0x50
14513
+ .8byte 0
14514
+ .8byte 0
14515
+.LLST25:
14516
+ .8byte .LVL44
14517
+ .8byte .LVL47
14518
+ .2byte 0x1
14519
+ .byte 0x50
14520
+ .8byte .LVL49
14521
+ .8byte .LVL50
14522
+ .2byte 0x1
14523
+ .byte 0x50
14524
+ .8byte .LVL51
14525
+ .8byte .LVL52
14526
+ .2byte 0x1
14527
+ .byte 0x50
14528
+ .8byte 0
14529
+ .8byte 0
14530
+.LLST26:
14531
+ .8byte .LVL53
14532
+ .8byte .LVL54
14533
+ .2byte 0x1
14534
+ .byte 0x51
14535
+ .8byte .LVL54
14536
+ .8byte .LVL56
14537
+ .2byte 0x1
14538
+ .byte 0x63
14539
+ .8byte .LVL56
14540
+ .8byte .LVL58
14541
+ .2byte 0x4
14542
+ .byte 0xf3
14543
+ .uleb128 0x1
14544
+ .byte 0x51
14545
+ .byte 0x9f
14546
+ .8byte .LVL58
14547
+ .8byte .LVL64
14548
+ .2byte 0x1
14549
+ .byte 0x63
14550
+ .8byte .LVL64
14551
+ .8byte .LFE280
14552
+ .2byte 0x4
14553
+ .byte 0xf3
14554
+ .uleb128 0x1
14555
+ .byte 0x51
14556
+ .byte 0x9f
14557
+ .8byte 0
14558
+ .8byte 0
14559
+.LLST27:
14560
+ .8byte .LVL54
14561
+ .8byte .LVL60
14562
+ .2byte 0x1
14563
+ .byte 0x64
14564
+ .8byte .LVL60
14565
+ .8byte .LVL61
14566
+ .2byte 0x3
14567
+ .byte 0x84
14568
+ .sleb128 -1
14569
+ .byte 0x9f
14570
+ .8byte .LVL61
14571
+ .8byte .LVL65
14572
+ .2byte 0x1
14573
+ .byte 0x64
14574
+ .8byte 0
14575
+ .8byte 0
14576
+.LLST28:
14577
+ .8byte .LVL55
14578
+ .8byte .LVL57
14579
+ .2byte 0x1
14580
+ .byte 0x50
14581
+ .8byte .LVL58
14582
+ .8byte .LVL59
14583
+ .2byte 0x1
14584
+ .byte 0x50
14585
+ .8byte 0
14586
+ .8byte 0
14587
+.LLST29:
14588
+ .8byte .LVL56
14589
+ .8byte .LVL58
14590
+ .2byte 0x1
14591
+ .byte 0x63
14592
+ .8byte 0
14593
+ .8byte 0
14594
+.LLST48:
14595
+ .8byte .LVL199
14596
+ .8byte .LVL205-1
14597
+ .2byte 0x1
14598
+ .byte 0x50
14599
+ .8byte .LVL205-1
14600
+ .8byte .LVL211
14601
+ .2byte 0x4
14602
+ .byte 0xf3
14603
+ .uleb128 0x1
14604
+ .byte 0x50
14605
+ .byte 0x9f
14606
+ .8byte .LVL211
14607
+ .8byte .LFE267
14608
+ .2byte 0x1
14609
+ .byte 0x50
14610
+ .8byte 0
14611
+ .8byte 0
14612
+.LLST49:
14613
+ .8byte .LVL199
14614
+ .8byte .LVL203
14615
+ .2byte 0x1
14616
+ .byte 0x51
14617
+ .8byte .LVL203
14618
+ .8byte .LFE267
14619
+ .2byte 0x4
14620
+ .byte 0xf3
14621
+ .uleb128 0x1
14622
+ .byte 0x51
14623
+ .byte 0x9f
14624
+ .8byte 0
14625
+ .8byte 0
14626
+.LLST50:
14627
+ .8byte .LVL199
14628
+ .8byte .LVL206
14629
+ .2byte 0x2
14630
+ .byte 0x30
14631
+ .byte 0x9f
14632
+ .8byte .LVL206
14633
+ .8byte .LVL208
14634
+ .2byte 0x1
14635
+ .byte 0x50
14636
+ .8byte .LVL208
14637
+ .8byte .LVL210
14638
+ .2byte 0x1
14639
+ .byte 0x63
14640
+ .8byte .LVL210
14641
+ .8byte .LVL211
14642
+ .2byte 0x1
14643
+ .byte 0x50
14644
+ .8byte .LVL211
14645
+ .8byte .LFE267
14646
+ .2byte 0x2
14647
+ .byte 0x30
14648
+ .byte 0x9f
14649
+ .8byte 0
14650
+ .8byte 0
14651
+.LLST51:
14652
+ .8byte .LVL202
14653
+ .8byte .LVL204
14654
+ .2byte 0x2
14655
+ .byte 0x30
14656
+ .byte 0x9f
14657
+ .8byte 0
14658
+ .8byte 0
14659
+.LLST52:
14660
+ .8byte .LVL204
14661
+ .8byte .LVL211
14662
+ .2byte 0x6
14663
+ .byte 0xc
14664
+ .4byte 0x10001
14665
+ .byte 0x9f
14666
+ .8byte 0
14667
+ .8byte 0
14668
+.LLST53:
14669
+ .8byte .LVL207
14670
+ .8byte .LVL209
14671
+ .2byte 0x4
14672
+ .byte 0xf3
14673
+ .uleb128 0x1
14674
+ .byte 0x50
14675
+ .byte 0x9f
14676
+ .8byte 0
14677
+ .8byte 0
14678
+.LLST54:
14679
+ .8byte .LVL207
14680
+ .8byte .LVL209
14681
+ .2byte 0x4
14682
+ .byte 0xf3
14683
+ .uleb128 0x1
14684
+ .byte 0x51
14685
+ .byte 0x9f
14686
+ .8byte 0
14687
+ .8byte 0
14688
+ .section .debug_aranges,"",@progbits
14689
+ .4byte 0xec
14690
+ .2byte 0x2
14691
+ .4byte .Ldebug_info0
14692
+ .byte 0x8
14693
+ .byte 0
14694
+ .2byte 0
14695
+ .2byte 0
14696
+ .8byte .LFB263
14697
+ .8byte .LFE263-.LFB263
14698
+ .8byte .LFB276
14699
+ .8byte .LFE276-.LFB276
14700
+ .8byte .LFB274
14701
+ .8byte .LFE274-.LFB274
14702
+ .8byte .LFB273
14703
+ .8byte .LFE273-.LFB273
14704
+ .8byte .LFB277
14705
+ .8byte .LFE277-.LFB277
14706
+ .8byte .LFB262
14707
+ .8byte .LFE262-.LFB262
14708
+ .8byte .LFB278
14709
+ .8byte .LFE278-.LFB278
14710
+ .8byte .LFB279
14711
+ .8byte .LFE279-.LFB279
14712
+ .8byte .LFB280
14713
+ .8byte .LFE280-.LFB280
14714
+ .8byte .LFB269
14715
+ .8byte .LFE269-.LFB269
14716
+ .8byte .LFB267
14717
+ .8byte .LFE267-.LFB267
14718
+ .8byte .LFB268
14719
+ .8byte .LFE268-.LFB268
14720
+ .8byte .LFB272
14721
+ .8byte .LFE272-.LFB272
14722
+ .8byte 0
14723
+ .8byte 0
14724
+ .section .debug_ranges,"",@progbits
14725
+.Ldebug_ranges0:
14726
+ .8byte .LBB48
14727
+ .8byte .LBE48
14728
+ .8byte .LBB49
14729
+ .8byte .LBE49
14730
+ .8byte 0
14731
+ .8byte 0
14732
+ .8byte .LBB64
14733
+ .8byte .LBE64
14734
+ .8byte .LBB66
14735
+ .8byte .LBE66
14736
+ .8byte 0
14737
+ .8byte 0
14738
+ .8byte .LBB65
14739
+ .8byte .LBE65
14740
+ .8byte .LBB67
14741
+ .8byte .LBE67
14742
+ .8byte 0
14743
+ .8byte 0
14744
+ .8byte .LBB68
14745
+ .8byte .LBE68
14746
+ .8byte .LBB69
14747
+ .8byte .LBE69
14748
+ .8byte 0
14749
+ .8byte 0
14750
+ .8byte .LBB73
14751
+ .8byte .LBE73
14752
+ .8byte .LBB74
14753
+ .8byte .LBE74
14754
+ .8byte 0
14755
+ .8byte 0
14756
+ .8byte .LBB92
14757
+ .8byte .LBE92
14758
+ .8byte .LBB93
14759
+ .8byte .LBE93
14760
+ .8byte 0
14761
+ .8byte 0
14762
+ .8byte .LBB98
14763
+ .8byte .LBE98
14764
+ .8byte .LBB99
14765
+ .8byte .LBE99
14766
+ .8byte 0
14767
+ .8byte 0
14768
+ .8byte .LBB103
14769
+ .8byte .LBE103
14770
+ .8byte .LBB105
14771
+ .8byte .LBE105
14772
+ .8byte 0
14773
+ .8byte 0
14774
+ .8byte .LBB104
14775
+ .8byte .LBE104
14776
+ .8byte .LBB106
14777
+ .8byte .LBE106
14778
+ .8byte 0
14779
+ .8byte 0
14780
+ .8byte .LBB107
14781
+ .8byte .LBE107
14782
+ .8byte .LBB108
14783
+ .8byte .LBE108
14784
+ .8byte 0
14785
+ .8byte 0
14786
+ .8byte .LBB112
14787
+ .8byte .LBE112
14788
+ .8byte .LBB113
14789
+ .8byte .LBE113
14790
+ .8byte 0
14791
+ .8byte 0
14792
+ .8byte .LBB118
14793
+ .8byte .LBE118
14794
+ .8byte .LBB119
14795
+ .8byte .LBE119
14796
+ .8byte 0
14797
+ .8byte 0
14798
+ .8byte .LBB123
14799
+ .8byte .LBE123
14800
+ .8byte .LBB124
14801
+ .8byte .LBE124
14802
+ .8byte 0
14803
+ .8byte 0
14804
+ .8byte .LBB128
14805
+ .8byte .LBE128
14806
+ .8byte .LBB129
14807
+ .8byte .LBE129
14808
+ .8byte 0
14809
+ .8byte 0
14810
+ .8byte .LBB135
14811
+ .8byte .LBE135
14812
+ .8byte .LBB136
14813
+ .8byte .LBE136
14814
+ .8byte 0
14815
+ .8byte 0
14816
+ .8byte .LBB140
14817
+ .8byte .LBE140
14818
+ .8byte .LBB141
14819
+ .8byte .LBE141
14820
+ .8byte 0
14821
+ .8byte 0
14822
+ .8byte .LBB144
14823
+ .8byte .LBE144
14824
+ .8byte .LBB145
14825
+ .8byte .LBE145
14826
+ .8byte 0
14827
+ .8byte 0
14828
+ .8byte .LBB168
14829
+ .8byte .LBE168
14830
+ .8byte .LBB169
14831
+ .8byte .LBE169
14832
+ .8byte 0
14833
+ .8byte 0
14834
+ .8byte .LBB170
14835
+ .8byte .LBE170
14836
+ .8byte .LBB171
14837
+ .8byte .LBE171
14838
+ .8byte 0
14839
+ .8byte 0
14840
+ .8byte .LBB172
14841
+ .8byte .LBE172
14842
+ .8byte .LBB173
14843
+ .8byte .LBE173
14844
+ .8byte 0
14845
+ .8byte 0
14846
+ .8byte .LBB174
14847
+ .8byte .LBE174
14848
+ .8byte .LBB175
14849
+ .8byte .LBE175
14850
+ .8byte 0
14851
+ .8byte 0
14852
+ .8byte .LBB244
14853
+ .8byte .LBE244
14854
+ .8byte .LBB324
14855
+ .8byte .LBE324
14856
+ .8byte .LBB325
14857
+ .8byte .LBE325
14858
+ .8byte .LBB335
14859
+ .8byte .LBE335
14860
+ .8byte .LBB336
14861
+ .8byte .LBE336
14862
+ .8byte 0
14863
+ .8byte 0
14864
+ .8byte .LBB264
14865
+ .8byte .LBE264
14866
+ .8byte .LBB266
14867
+ .8byte .LBE266
14868
+ .8byte 0
14869
+ .8byte 0
14870
+ .8byte .LBB265
14871
+ .8byte .LBE265
14872
+ .8byte .LBB267
14873
+ .8byte .LBE267
14874
+ .8byte 0
14875
+ .8byte 0
14876
+ .8byte .LBB268
14877
+ .8byte .LBE268
14878
+ .8byte .LBB269
14879
+ .8byte .LBE269
14880
+ .8byte 0
14881
+ .8byte 0
14882
+ .8byte .LBB270
14883
+ .8byte .LBE270
14884
+ .8byte .LBB271
14885
+ .8byte .LBE271
14886
+ .8byte 0
14887
+ .8byte 0
14888
+ .8byte .LBB288
14889
+ .8byte .LBE288
14890
+ .8byte .LBB289
14891
+ .8byte .LBE289
14892
+ .8byte 0
14893
+ .8byte 0
14894
+ .8byte .LBB294
14895
+ .8byte .LBE294
14896
+ .8byte .LBB295
14897
+ .8byte .LBE295
14898
+ .8byte 0
14899
+ .8byte 0
14900
+ .8byte .LBB298
14901
+ .8byte .LBE298
14902
+ .8byte .LBB300
14903
+ .8byte .LBE300
14904
+ .8byte 0
14905
+ .8byte 0
14906
+ .8byte .LBB299
14907
+ .8byte .LBE299
14908
+ .8byte .LBB301
14909
+ .8byte .LBE301
14910
+ .8byte 0
14911
+ .8byte 0
14912
+ .8byte .LBB302
14913
+ .8byte .LBE302
14914
+ .8byte .LBB303
14915
+ .8byte .LBE303
14916
+ .8byte 0
14917
+ .8byte 0
14918
+ .8byte .LBB308
14919
+ .8byte .LBE308
14920
+ .8byte .LBB309
14921
+ .8byte .LBE309
14922
+ .8byte 0
14923
+ .8byte 0
14924
+ .8byte .LBB314
14925
+ .8byte .LBE314
14926
+ .8byte .LBB315
14927
+ .8byte .LBE315
14928
+ .8byte 0
14929
+ .8byte 0
14930
+ .8byte .LBB326
14931
+ .8byte .LBE326
14932
+ .8byte .LBB332
14933
+ .8byte .LBE332
14934
+ .8byte .LBB333
14935
+ .8byte .LBE333
14936
+ .8byte .LBB334
14937
+ .8byte .LBE334
14938
+ .8byte .LBB337
14939
+ .8byte .LBE337
14940
+ .8byte 0
14941
+ .8byte 0
14942
+ .8byte .LFB263
14943
+ .8byte .LFE263
14944
+ .8byte .LFB276
14945
+ .8byte .LFE276
14946
+ .8byte .LFB274
14947
+ .8byte .LFE274
14948
+ .8byte .LFB273
14949
+ .8byte .LFE273
14950
+ .8byte .LFB277
14951
+ .8byte .LFE277
14952
+ .8byte .LFB262
14953
+ .8byte .LFE262
14954
+ .8byte .LFB278
14955
+ .8byte .LFE278
14956
+ .8byte .LFB279
14957
+ .8byte .LFE279
14958
+ .8byte .LFB280
14959
+ .8byte .LFE280
14960
+ .8byte .LFB269
14961
+ .8byte .LFE269
14962
+ .8byte .LFB267
14963
+ .8byte .LFE267
14964
+ .8byte .LFB268
14965
+ .8byte .LFE268
14966
+ .8byte .LFB272
14967
+ .8byte .LFE272
14968
+ .8byte 0
14969
+ .8byte 0
14970
+ .section .debug_line,"",@progbits
14971
+.Ldebug_line0:
14972
+ .section .debug_str,"MS",@progbits,1
14973
+.LASF222:
14974
+ .string "UCLASS_SERIAL"
14975
+.LASF319:
14976
+ .string "gd_t"
14977
+.LASF15:
14978
+ .string "long int"
14979
+.LASF39:
14980
+ .string "uclass_node"
14981
+.LASF422:
14982
+ .string "request"
14983
+.LASF312:
14984
+ .string "phandle"
14985
+.LASF53:
14986
+ .string "flash_id"
14987
+.LASF404:
14988
+ .string "misc_ops"
14989
+.LASF376:
14990
+ .string "mem_malloc_start"
14991
+.LASF332:
14992
+ .string "net_hostname"
14993
+.LASF28:
14994
+ .string "name"
14995
+.LASF248:
14996
+ .string "UCLASS_ETH_PHY"
14997
+.LASF229:
14998
+ .string "UCLASS_THERMAL"
14999
+.LASF60:
15000
+ .string "base"
15001
+.LASF354:
15002
+ .string "NETLOOP_RESTART"
15003
+.LASF287:
15004
+ .string "new_gd"
15005
+.LASF348:
15006
+ .string "net_boot_file_size"
15007
+.LASF134:
15008
+ .string "fit_hdr_os"
15009
+.LASF181:
15010
+ .string "UCLASS_FIRMWARE"
15011
+.LASF457:
15012
+ .string "udelay"
15013
+.LASF142:
15014
+ .string "fit_noffset_fdt"
15015
+.LASF74:
15016
+ .string "bi_dsp_freq"
15017
+.LASF303:
15018
+ .string "malloc_ptr"
15019
+.LASF91:
15020
+ .string "_datarellocal_start_ofs"
15021
+.LASF94:
15022
+ .string "fdt32_t"
15023
+.LASF146:
15024
+ .string "rd_start"
15025
+.LASF371:
15026
+ .string "property"
15027
+.LASF265:
15028
+ .string "tlb_emerg"
15029
+.LASF78:
15030
+ .string "bi_enetaddr"
15031
+.LASF290:
15032
+ .string "uclass_root"
15033
+.LASF188:
15034
+ .string "UCLASS_IRQ"
15035
+.LASF420:
15036
+ .string "rockchip_secure_otp_ofdata_to_platdata"
15037
+.LASF437:
15038
+ .string "buffer"
15039
+.LASF234:
15040
+ .string "UCLASS_USB_HUB"
15041
+.LASF230:
15042
+ .string "UCLASS_TIMER"
15043
+.LASF42:
15044
+ .string "flags"
15045
+.LASF139:
15046
+ .string "fit_noffset_rd"
15047
+.LASF269:
15048
+ .string "baudrate"
15049
+.LASF334:
15050
+ .string "net_ethaddr"
15051
+.LASF300:
15052
+ .string "timebase_l"
15053
+.LASF21:
15054
+ .string "errno"
15055
+.LASF32:
15056
+ .string "node"
15057
+.LASF359:
15058
+ .string "bind"
15059
+.LASF455:
15060
+ .string "printf"
15061
+.LASF401:
15062
+ .string "DECOM_ZLIB"
15063
+.LASF8:
15064
+ .string "unsigned int"
15065
+.LASF47:
15066
+ .string "next"
15067
+.LASF101:
15068
+ .string "version"
15069
+.LASF396:
15070
+ .string "per_device_platdata_auto_alloc_size"
15071
+.LASF131:
15072
+ .string "legacy_hdr_os_copy"
15073
+.LASF195:
15074
+ .string "UCLASS_MMC"
15075
+.LASF289:
15076
+ .string "dm_root_f"
15077
+.LASF340:
15078
+ .string "net_rx_packet"
15079
+.LASF38:
15080
+ .string "parent_priv"
15081
+.LASF176:
15082
+ .string "UCLASS_CROS_EC"
15083
+.LASF310:
15084
+ .string "console_evt"
15085
+.LASF191:
15086
+ .string "UCLASS_LPC"
15087
+.LASF105:
15088
+ .string "size_dt_struct"
15089
+.LASF379:
15090
+ .string "p_current"
15091
+.LASF344:
15092
+ .string "net_our_vlan"
15093
+.LASF22:
15094
+ .string "___strtok"
15095
+.LASF67:
15096
+ .string "bi_memsize"
15097
+.LASF121:
15098
+ .string "image_info"
15099
+.LASF200:
15100
+ .string "UCLASS_NVME"
15101
+.LASF156:
15102
+ .string "bootm_headers_t"
15103
+.LASF252:
15104
+ .string "UCLASS_RNG"
15105
+.LASF249:
15106
+ .string "UCLASS_MDIO"
15107
+.LASF187:
15108
+ .string "UCLASS_IDE"
15109
+.LASF273:
15110
+ .string "bus_clk"
15111
+.LASF377:
15112
+ .string "mem_malloc_end"
15113
+.LASF225:
15114
+ .string "UCLASS_SPI_FLASH"
15115
+.LASF189:
15116
+ .string "UCLASS_KEYBOARD"
15117
+.LASF72:
15118
+ .string "bi_sramsize"
15119
+.LASF185:
15120
+ .string "UCLASS_I2C_MUX"
15121
+.LASF297:
15122
+ .string "fdt_blob_kern"
15123
+.LASF277:
15124
+ .string "env_addr"
15125
+.LASF48:
15126
+ .string "prev"
15127
+.LASF227:
15128
+ .string "UCLASS_SYSCON"
15129
+.LASF171:
15130
+ .string "UCLASS_BLK"
15131
+.LASF212:
15132
+ .string "UCLASS_PWRSEQ"
15133
+.LASF132:
15134
+ .string "legacy_hdr_valid"
15135
+.LASF264:
15136
+ .string "tlb_fillptr"
15137
+.LASF82:
15138
+ .string "bi_arch_number"
15139
+.LASF323:
15140
+ .string "load_addr"
15141
+.LASF291:
15142
+ .string "fdt_blob"
15143
+.LASF328:
15144
+ .string "net_gateway"
15145
+.LASF166:
15146
+ .string "UCLASS_PCI_EMUL"
15147
+.LASF424:
15148
+ .string "offset"
15149
+.LASF426:
15150
+ .string "secure_otp_read"
15151
+.LASF349:
15152
+ .string "net_boot_file_expected_size_in_blocks"
15153
+.LASF403:
15154
+ .string "OTP_NS"
15155
+.LASF414:
15156
+ .string "spl_rockchip_otp_start"
15157
+.LASF206:
15158
+ .string "UCLASS_PHY"
15159
+.LASF454:
15160
+ .string "dev_get_driver_data"
15161
+.LASF3:
15162
+ .string "signed char"
15163
+.LASF203:
15164
+ .string "UCLASS_PCH"
15165
+.LASF100:
15166
+ .string "off_mem_rsvmap"
15167
+.LASF163:
15168
+ .string "UCLASS_TEST_PROBE"
15169
+.LASF149:
15170
+ .string "ft_len"
15171
+.LASF19:
15172
+ .string "uint32_t"
15173
+.LASF384:
15174
+ .string "udevice_id"
15175
+.LASF325:
15176
+ .string "save_size"
15177
+.LASF439:
15178
+ .string "read_end"
15179
+.LASF378:
15180
+ .string "mem_malloc_brk"
15181
+.LASF124:
15182
+ .string "load"
15183
+.LASF143:
15184
+ .string "fit_hdr_setup"
15185
+.LASF299:
15186
+ .string "timebase_h"
15187
+.LASF160:
15188
+ .string "UCLASS_TEST"
15189
+.LASF87:
15190
+ .string "IRQ_STACK_START"
15191
+.LASF419:
15192
+ .string "_u_boot_list_2_driver_2_rockchip_secure_otp"
15193
+.LASF125:
15194
+ .string "comp"
15195
+.LASF70:
15196
+ .string "bi_flashoffset"
15197
+.LASF201:
15198
+ .string "UCLASS_PANEL"
15199
+.LASF266:
15200
+ .string "pre_serial"
15201
+.LASF36:
15202
+ .string "uclass"
15203
+.LASF162:
15204
+ .string "UCLASS_TEST_BUS"
15205
+.LASF460:
15206
+ .string "/home/lxh/uboot/u-boot"
15207
+.LASF238:
15208
+ .string "UCLASS_VIDEO_CONSOLE"
15209
+.LASF360:
15210
+ .string "probe"
15211
+.LASF10:
15212
+ .string "long long unsigned int"
15213
+.LASF260:
15214
+ .string "lastinc"
15215
+.LASF388:
15216
+ .string "post_bind"
15217
+.LASF284:
15218
+ .string "irq_sp"
15219
+.LASF449:
15220
+ .string "rk3528_spl_rockchip_otp_stop"
15221
+.LASF197:
15222
+ .string "UCLASS_MTD"
15223
+.LASF216:
15224
+ .string "UCLASS_RESET"
15225
+.LASF117:
15226
+ .string "ih_type"
15227
+.LASF80:
15228
+ .string "bi_intfreq"
15229
+.LASF172:
15230
+ .string "UCLASS_CLK"
15231
+.LASF350:
15232
+ .string "net_ping_ip"
15233
+.LASF79:
15234
+ .string "bi_ethspeed"
15235
+.LASF375:
15236
+ .string "ofnode"
15237
+.LASF435:
15238
+ .string "rk3528_secure_otp_write_2_bytes_noecc"
15239
+.LASF231:
15240
+ .string "UCLASS_TPM"
15241
+.LASF315:
15242
+ .string "child"
15243
+.LASF443:
15244
+ .string "rockchip_secure_otp_wait_flag"
15245
+.LASF456:
15246
+ .string "malloc_simple"
15247
+.LASF59:
15248
+ .string "lmb_property"
15249
+.LASF268:
15250
+ .string "enable"
15251
+.LASF262:
15252
+ .string "tlb_addr"
15253
+.LASF373:
15254
+ .string "value"
15255
+.LASF184:
15256
+ .string "UCLASS_I2C_GENERIC"
15257
+.LASF99:
15258
+ .string "off_dt_strings"
15259
+.LASF418:
15260
+ .string "rockchip_otp_ids"
15261
+.LASF103:
15262
+ .string "boot_cpuid_phys"
15263
+.LASF361:
15264
+ .string "remove"
15265
+.LASF133:
15266
+ .string "fit_uname_cfg"
15267
+.LASF106:
15268
+ .string "working_fdt"
15269
+.LASF316:
15270
+ .string "sibling"
15271
+.LASF118:
15272
+ .string "ih_comp"
15273
+.LASF202:
15274
+ .string "UCLASS_PANEL_BACKLIGHT"
15275
+.LASF81:
15276
+ .string "bi_busfreq"
15277
+.LASF296:
15278
+ .string "ufdt_blob"
15279
+.LASF279:
15280
+ .string "ram_top"
15281
+.LASF271:
15282
+ .string "global_data"
15283
+.LASF327:
15284
+ .string "s_addr"
15285
+.LASF127:
15286
+ .string "arch"
15287
+.LASF226:
15288
+ .string "UCLASS_SPI_GENERIC"
15289
+.LASF317:
15290
+ .string "mtd_info"
15291
+.LASF95:
15292
+ .string "fdt_header"
15293
+.LASF177:
15294
+ .string "UCLASS_DISPLAY"
15295
+.LASF390:
15296
+ .string "pre_probe"
15297
+.LASF352:
15298
+ .string "net_loop_state"
15299
+.LASF55:
15300
+ .string "protect"
15301
+.LASF306:
15302
+ .string "video_bottom"
15303
+.LASF438:
15304
+ .string "write_end"
15305
+.LASF71:
15306
+ .string "bi_sramstart"
15307
+.LASF224:
15308
+ .string "UCLASS_SPMI"
15309
+.LASF220:
15310
+ .string "UCLASS_SCMI_AGENT"
15311
+.LASF23:
15312
+ .string "_Bool"
15313
+.LASF12:
15314
+ .string "phys_size_t"
15315
+.LASF45:
15316
+ .string "udevice"
15317
+.LASF37:
15318
+ .string "uclass_priv"
15319
+.LASF123:
15320
+ .string "image_len"
15321
+.LASF318:
15322
+ .string "jt_funcs"
15323
+.LASF408:
15324
+ .string "call"
15325
+.LASF330:
15326
+ .string "net_dns_server"
15327
+.LASF427:
15328
+ .string "rk3528_secure_otp_write"
15329
+.LASF397:
15330
+ .string "__invalid_size_argument_for_IOC"
15331
+.LASF57:
15332
+ .string "flash_info"
15333
+.LASF462:
15334
+ .string "free"
15335
+.LASF288:
15336
+ .string "dm_root"
15337
+.LASF108:
15338
+ .string "ih_magic"
15339
+.LASF218:
15340
+ .string "UCLASS_RAMDISK"
15341
+.LASF450:
15342
+ .string "rk3528_spl_rockchip_otp_start"
15343
+.LASF26:
15344
+ .string "_binary_u_boot_bin_end"
15345
+.LASF141:
15346
+ .string "fit_uname_fdt"
15347
+.LASF190:
15348
+ .string "UCLASS_LED"
15349
+.LASF292:
15350
+ .string "new_fdt"
15351
+.LASF407:
15352
+ .string "ioctl"
15353
+.LASF170:
15354
+ .string "UCLASS_AHCI"
15355
+.LASF41:
15356
+ .string "sibling_node"
15357
+.LASF333:
15358
+ .string "net_root_path"
15359
+.LASF49:
15360
+ .string "block_drvr"
15361
+.LASF9:
15362
+ .string "long long int"
15363
+.LASF250:
15364
+ .string "UCLASS_EBC"
15365
+.LASF324:
15366
+ .string "save_addr"
15367
+.LASF35:
15368
+ .string "priv"
15369
+.LASF209:
15370
+ .string "UCLASS_PMIC"
15371
+.LASF302:
15372
+ .string "malloc_limit"
15373
+.LASF14:
15374
+ .string "char"
15375
+.LASF413:
15376
+ .string "secure_otp_data"
15377
+.LASF180:
15378
+ .string "UCLASS_GPIO"
15379
+.LASF44:
15380
+ .string "ide_bus_offset"
15381
+.LASF254:
15382
+ .string "UCLASS_PD"
15383
+.LASF52:
15384
+ .string "sector_count"
15385
+.LASF145:
15386
+ .string "fit_noffset_setup"
15387
+.LASF122:
15388
+ .string "image_start"
15389
+.LASF56:
15390
+ .string "flash_info_t"
15391
+.LASF228:
15392
+ .string "UCLASS_SYSRESET"
15393
+.LASF115:
15394
+ .string "ih_os"
15395
+.LASF31:
15396
+ .string "uclass_platdata"
15397
+.LASF336:
15398
+ .string "net_ip"
15399
+.LASF458:
15400
+ .ascii "GNU C11 6.3.1 201"
15401
+ .string "70404 -mstrict-align -march=armv8-a+nosimd -mlittle-endian -mabi=lp64 -g -Os -fno-builtin -ffreestanding -fshort-wchar -fno-stack-protector -fno-delete-null-pointer-checks -fstack-usage -ffunction-sections -fdata-sections -ffixed-r9 -fno-common -ffixed-x18"
15402
+.LASF305:
15403
+ .string "video_top"
15404
+.LASF257:
15405
+ .string "LOGF_MAX_CATEGORIES"
15406
+.LASF357:
15407
+ .string "net_state"
15408
+.LASF459:
15409
+ .string "drivers/misc/rk3528-secure-otp.c"
15410
+.LASF285:
15411
+ .string "start_addr_sp"
15412
+.LASF135:
15413
+ .string "fit_uname_os"
15414
+.LASF18:
15415
+ .string "uint8_t"
15416
+.LASF7:
15417
+ .string "__u32"
15418
+.LASF362:
15419
+ .string "unbind"
15420
+.LASF283:
15421
+ .string "mon_len"
15422
+.LASF356:
15423
+ .string "NETLOOP_FAIL"
15424
+.LASF428:
15425
+ .string "data_byte"
15426
+.LASF364:
15427
+ .string "child_post_bind"
15428
+.LASF313:
15429
+ .string "full_name"
15430
+.LASF214:
15431
+ .string "UCLASS_REGULATOR"
15432
+.LASF183:
15433
+ .string "UCLASS_I2C_EEPROM"
15434
+.LASF370:
15435
+ .string "per_child_platdata_auto_alloc_size"
15436
+.LASF444:
15437
+ .string "rockchip_secure_otp_wait_status"
15438
+.LASF129:
15439
+ .string "bootm_headers"
15440
+.LASF275:
15441
+ .string "mem_clk"
15442
+.LASF358:
15443
+ .string "of_match"
15444
+.LASF351:
15445
+ .string "uclass_id"
15446
+.LASF320:
15447
+ .string "monitor_flash_len"
15448
+.LASF366:
15449
+ .string "child_post_remove"
15450
+.LASF369:
15451
+ .string "per_child_auto_alloc_size"
15452
+.LASF213:
15453
+ .string "UCLASS_RAM"
15454
+.LASF293:
15455
+ .string "fdt_size"
15456
+.LASF363:
15457
+ .string "ofdata_to_platdata"
15458
+.LASF208:
15459
+ .string "UCLASS_PINCTRL"
15460
+.LASF29:
15461
+ .string "platdata"
15462
+.LASF259:
15463
+ .string "timer_rate_hz"
15464
+.LASF433:
15465
+ .string "rk3528_secure_otp_write_byte_noecc"
15466
+.LASF434:
15467
+ .string "data_2b"
15468
+.LASF90:
15469
+ .string "_datarelrolocal_start_ofs"
15470
+.LASF164:
15471
+ .string "UCLASS_SPI_EMUL"
15472
+.LASF196:
15473
+ .string "UCLASS_MOD_EXP"
15474
+.LASF97:
15475
+ .string "totalsize"
15476
+.LASF387:
15477
+ .string "uclass_driver"
15478
+.LASF73:
15479
+ .string "bi_arm_freq"
15480
+.LASF199:
15481
+ .string "UCLASS_NORTHBRIDGE"
15482
+.LASF235:
15483
+ .string "UCLASS_USB_GADGET_GENERIC"
15484
+.LASF120:
15485
+ .string "image_header_t"
15486
+.LASF68:
15487
+ .string "bi_flashstart"
15488
+.LASF92:
15489
+ .string "_datarelro_start_ofs"
15490
+.LASF346:
15491
+ .string "net_restart_wrap"
15492
+.LASF385:
15493
+ .string "compatible"
15494
+.LASF165:
15495
+ .string "UCLASS_I2C_EMUL"
15496
+.LASF274:
15497
+ .string "pci_clk"
15498
+.LASF173:
15499
+ .string "UCLASS_CPU"
15500
+.LASF343:
15501
+ .string "net_null_ethaddr"
15502
+.LASF86:
15503
+ .string "bd_t"
15504
+.LASF174:
15505
+ .string "UCLASS_AMP"
15506
+.LASF243:
15507
+ .string "UCLASS_RC"
15508
+.LASF453:
15509
+ .string "dev_read_u32_default"
15510
+.LASF337:
15511
+ .string "net_server_ip"
15512
+.LASF280:
15513
+ .string "ram_top_ext_size"
15514
+.LASF51:
15515
+ .string "size"
15516
+.LASF58:
15517
+ .string "long double"
15518
+.LASF76:
15519
+ .string "bi_bootflags"
15520
+.LASF83:
15521
+ .string "bi_boot_params"
15522
+.LASF441:
15523
+ .string "rockchip_secure_otp_check_flag"
15524
+.LASF448:
15525
+ .string "mask"
15526
+.LASF246:
15527
+ .string "UCLASS_IO_DOMAIN"
15528
+.LASF25:
15529
+ .string "_binary_u_boot_bin_start"
15530
+.LASF159:
15531
+ .string "UCLASS_DEMO"
15532
+.LASF107:
15533
+ .string "image_header"
15534
+.LASF102:
15535
+ .string "last_comp_version"
15536
+.LASF321:
15537
+ .string "__dtb_dt_begin"
15538
+.LASF251:
15539
+ .string "UCLASS_EINK_DISPLAY"
15540
+.LASF309:
15541
+ .string "sys_start_tick"
15542
+.LASF168:
15543
+ .string "UCLASS_SIMPLE_BUS"
15544
+.LASF179:
15545
+ .string "UCLASS_ETH"
15546
+.LASF153:
15547
+ .string "cmdline_end"
15548
+.LASF75:
15549
+ .string "bi_ddr_freq"
15550
+.LASF98:
15551
+ .string "off_dt_struct"
15552
+.LASF440:
15553
+ .string "rockchip_secure_otp_ecc_enable"
15554
+.LASF301:
15555
+ .string "malloc_base"
15556
+.LASF308:
15557
+ .string "serial"
15558
+.LASF386:
15559
+ .string "data"
15560
+.LASF329:
15561
+ .string "net_netmask"
15562
+.LASF322:
15563
+ .string "__dtb_dt_spl_begin"
15564
+.LASF65:
15565
+ .string "bd_info"
15566
+.LASF152:
15567
+ .string "cmdline_start"
15568
+.LASF157:
15569
+ .string "images"
15570
+.LASF267:
15571
+ .string "using_pre_serial"
15572
+.LASF130:
15573
+ .string "legacy_hdr_os"
15574
+.LASF425:
15575
+ .string "otp_data"
15576
+.LASF192:
15577
+ .string "UCLASS_MAILBOX"
15578
+.LASF217:
15579
+ .string "UCLASS_RKNAND"
15580
+.LASF138:
15581
+ .string "fit_uname_rd"
15582
+.LASF77:
15583
+ .string "bi_ip_addr"
15584
+.LASF307:
15585
+ .string "pm_ctx_phys"
15586
+.LASF295:
15587
+ .string "of_root_f"
15588
+.LASF281:
15589
+ .string "relocaddr"
15590
+.LASF33:
15591
+ .string "driver_data"
15592
+.LASF0:
15593
+ .string "unsigned char"
15594
+.LASF11:
15595
+ .string "phys_addr_t"
15596
+.LASF389:
15597
+ .string "pre_unbind"
15598
+.LASF13:
15599
+ .string "sizetype"
15600
+.LASF338:
15601
+ .string "net_tx_packet"
15602
+.LASF395:
15603
+ .string "per_device_auto_alloc_size"
15604
+.LASF150:
15605
+ .string "initrd_start"
15606
+.LASF34:
15607
+ .string "parent"
15608
+.LASF380:
15609
+ .string "current"
15610
+.LASF6:
15611
+ .string "short int"
15612
+.LASF116:
15613
+ .string "ih_arch"
15614
+.LASF400:
15615
+ .string "DECOM_GZIP"
15616
+.LASF314:
15617
+ .string "properties"
15618
+.LASF240:
15619
+ .string "UCLASS_WDT"
15620
+.LASF442:
15621
+ .string "delay"
15622
+.LASF372:
15623
+ .string "length"
15624
+.LASF331:
15625
+ .string "net_nis_domain"
15626
+.LASF112:
15627
+ .string "ih_load"
15628
+.LASF298:
15629
+ .string "env_buf"
15630
+.LASF355:
15631
+ .string "NETLOOP_SUCCESS"
15632
+.LASF167:
15633
+ .string "UCLASS_USB_EMUL"
15634
+.LASF429:
15635
+ .string "temp"
15636
+.LASF161:
15637
+ .string "UCLASS_TEST_FDT"
15638
+.LASF415:
15639
+ .string "spl_rockchip_otp_stop"
15640
+.LASF445:
15641
+ .string "flag"
15642
+.LASF17:
15643
+ .string "ulong"
15644
+.LASF110:
15645
+ .string "ih_time"
15646
+.LASF111:
15647
+ .string "ih_size"
15648
+.LASF178:
15649
+ .string "UCLASS_DMA"
15650
+.LASF253:
15651
+ .string "UCLASS_DMC"
15652
+.LASF215:
15653
+ .string "UCLASS_REMOTEPROC"
15654
+.LASF353:
15655
+ .string "NETLOOP_CONTINUE"
15656
+.LASF219:
15657
+ .string "UCLASS_RTC"
15658
+.LASF261:
15659
+ .string "timer_reset_value"
15660
+.LASF294:
15661
+ .string "of_root"
15662
+.LASF339:
15663
+ .string "net_rx_packets"
15664
+.LASF194:
15665
+ .string "UCLASS_MISC"
15666
+.LASF62:
15667
+ .string "region"
15668
+.LASF148:
15669
+ .string "ft_addr"
15670
+.LASF416:
15671
+ .string "rockchip_secure_otp_ops"
15672
+.LASF405:
15673
+ .string "read"
15674
+.LASF54:
15675
+ .string "start"
15676
+.LASF144:
15677
+ .string "fit_uname_setup"
15678
+.LASF114:
15679
+ .string "ih_dcrc"
15680
+.LASF24:
15681
+ .string "image_base"
15682
+.LASF392:
15683
+ .string "pre_remove"
15684
+.LASF158:
15685
+ .string "UCLASS_ROOT"
15686
+.LASF96:
15687
+ .string "magic"
15688
+.LASF241:
15689
+ .string "UCLASS_FG"
15690
+.LASF137:
15691
+ .string "fit_hdr_rd"
15692
+.LASF140:
15693
+ .string "fit_hdr_fdt"
15694
+.LASF113:
15695
+ .string "ih_ep"
15696
+.LASF286:
15697
+ .string "reloc_off"
15698
+.LASF393:
15699
+ .string "init"
15700
+.LASF239:
15701
+ .string "UCLASS_VIDEO_CRTC"
15702
+.LASF236:
15703
+ .string "UCLASS_VIDEO"
15704
+.LASF446:
15705
+ .string "secure_conf"
15706
+.LASF205:
15707
+ .string "UCLASS_PCI_GENERIC"
15708
+.LASF1:
15709
+ .string "long unsigned int"
15710
+.LASF5:
15711
+ .string "__u8"
15712
+.LASF374:
15713
+ .string "of_offset"
15714
+.LASF258:
15715
+ .string "arch_global_data"
15716
+.LASF89:
15717
+ .string "_datarel_start_ofs"
15718
+.LASF311:
15719
+ .string "device_node"
15720
+.LASF263:
15721
+ .string "tlb_size"
15722
+.LASF66:
15723
+ .string "bi_memstart"
15724
+.LASF109:
15725
+ .string "ih_hcrc"
15726
+.LASF104:
15727
+ .string "size_dt_strings"
15728
+.LASF128:
15729
+ .string "image_info_t"
15730
+.LASF63:
15731
+ .string "memory"
15732
+.LASF27:
15733
+ .string "driver"
15734
+.LASF147:
15735
+ .string "rd_end"
15736
+.LASF193:
15737
+ .string "UCLASS_MASS_STORAGE"
15738
+.LASF326:
15739
+ .string "in_addr"
15740
+.LASF151:
15741
+ .string "initrd_end"
15742
+.LASF210:
15743
+ .string "UCLASS_PWM"
15744
+.LASF93:
15745
+ .string "IRQ_STACK_START_IN"
15746
+.LASF84:
15747
+ .string "bi_andr_version"
15748
+.LASF126:
15749
+ .string "type"
15750
+.LASF341:
15751
+ .string "net_rx_packet_len"
15752
+.LASF383:
15753
+ .string "u_boot_dev_head"
15754
+.LASF431:
15755
+ .string "rk3528_secure_otp_write_2_bytes"
15756
+.LASF221:
15757
+ .string "UCLASS_SCSI"
15758
+.LASF16:
15759
+ .string "ushort"
15760
+.LASF204:
15761
+ .string "UCLASS_PCI"
15762
+.LASF198:
15763
+ .string "UCLASS_NOP"
15764
+.LASF394:
15765
+ .string "destroy"
15766
+.LASF447:
15767
+ .string "otp_cru_rst"
15768
+.LASF247:
15769
+ .string "UCLASS_CRYPTO"
15770
+.LASF452:
15771
+ .string "dev_read_addr_ptr"
15772
+.LASF276:
15773
+ .string "have_console"
15774
+.LASF399:
15775
+ .string "DECOM_LZ4"
15776
+.LASF175:
15777
+ .string "UCLASS_CODEC"
15778
+.LASF381:
15779
+ .string "uc_drv"
15780
+.LASF232:
15781
+ .string "UCLASS_USB"
15782
+.LASF304:
15783
+ .string "cur_serial_dev"
15784
+.LASF270:
15785
+ .string "addr"
15786
+.LASF46:
15787
+ .string "list_head"
15788
+.LASF155:
15789
+ .string "state"
15790
+.LASF20:
15791
+ .string "__be32"
15792
+.LASF207:
15793
+ .string "UCLASS_PINCONFIG"
15794
+.LASF233:
15795
+ .string "UCLASS_USB_DEV_GENERIC"
15796
+.LASF342:
15797
+ .string "net_bcast_ethaddr"
15798
+.LASF136:
15799
+ .string "fit_noffset_os"
15800
+.LASF223:
15801
+ .string "UCLASS_SPI"
15802
+.LASF436:
15803
+ .string "rk3528_secure_otp_read"
15804
+.LASF335:
15805
+ .string "net_server_ethaddr"
15806
+.LASF255:
15807
+ .string "UCLASS_COUNT"
15808
+.LASF278:
15809
+ .string "env_valid"
15810
+.LASF245:
15811
+ .string "UCLASS_DVFS"
15812
+.LASF412:
15813
+ .string "otp_cru_rst_base"
15814
+.LASF40:
15815
+ .string "child_head"
15816
+.LASF50:
15817
+ .string "select_hwpart"
15818
+.LASF4:
15819
+ .string "uchar"
15820
+.LASF69:
15821
+ .string "bi_flashsize"
15822
+.LASF382:
15823
+ .string "dev_head"
15824
+.LASF409:
15825
+ .string "rockchip_otp_platdata"
15826
+.LASF2:
15827
+ .string "short unsigned int"
15828
+.LASF391:
15829
+ .string "post_probe"
15830
+.LASF365:
15831
+ .string "child_pre_probe"
15832
+.LASF421:
15833
+ .string "secure_otp_ioctl"
15834
+.LASF347:
15835
+ .string "net_boot_file_name"
15836
+.LASF406:
15837
+ .string "write"
15838
+.LASF244:
15839
+ .string "UCLASS_CHARGE_DISPLAY"
15840
+.LASF256:
15841
+ .string "UCLASS_INVALID"
15842
+.LASF402:
15843
+ .string "OTP_S"
15844
+.LASF432:
15845
+ .string "__func__"
15846
+.LASF64:
15847
+ .string "reserved"
15848
+.LASF417:
15849
+ .string "rk3528_data"
15850
+.LASF182:
15851
+ .string "UCLASS_I2C"
15852
+.LASF119:
15853
+ .string "ih_name"
15854
+.LASF461:
15855
+ .string "ofnode_union"
15856
+.LASF411:
15857
+ .string "otp_mask_base"
15858
+.LASF169:
15859
+ .string "UCLASS_ADC"
15860
+.LASF43:
15861
+ .string "req_seq"
15862
+.LASF282:
15863
+ .string "ram_size"
15864
+.LASF451:
15865
+ .string "dev_get_platdata"
15866
+.LASF186:
15867
+ .string "UCLASS_I2S"
15868
+.LASF367:
15869
+ .string "priv_auto_alloc_size"
15870
+.LASF30:
15871
+ .string "parent_platdata"
15872
+.LASF410:
15873
+ .string "secure_conf_base"
15874
+.LASF154:
15875
+ .string "verify"
15876
+.LASF88:
15877
+ .string "FIQ_STACK_START"
15878
+.LASF85:
15879
+ .string "bi_dram"
15880
+.LASF430:
15881
+ .string "rockchip_secure_otp_capability"
15882
+.LASF345:
15883
+ .string "net_native_vlan"
15884
+.LASF423:
15885
+ .string "secure_otp_write"
15886
+.LASF211:
15887
+ .string "UCLASS_POWER_DOMAIN"
15888
+.LASF398:
15889
+ .string "misc_mode"
15890
+.LASF272:
15891
+ .string "cpu_clk"
15892
+.LASF237:
15893
+ .string "UCLASS_VIDEO_BRIDGE"
15894
+.LASF368:
15895
+ .string "platdata_auto_alloc_size"
15896
+.LASF61:
15897
+ .string "lmb_region"
15898
+.LASF242:
15899
+ .string "UCLASS_KEY"
15900
+ .ident "GCC: (Linaro GCC 6.3-2017.05) 6.3.1 20170404"
15901
+ .section .note.GNU-stack,"",@progbits
u-boot/drivers/misc/rk3562-secure-otp.S
....@@ -0,0 +1,15906 @@
1
+ .arch armv8-a+nosimd
2
+ .file "rk3562-secure-otp.c"
3
+ .text
4
+.Ltext0:
5
+ .cfi_sections .debug_frame
6
+ .section .text.rk3562_spl_rockchip_otp_stop,"ax",@progbits
7
+ .align 2
8
+ .type rk3562_spl_rockchip_otp_stop, %function
9
+rk3562_spl_rockchip_otp_stop:
10
+.LFB263:
11
+ .file 1 "drivers/misc/rk3562-secure-otp.c"
12
+ .loc 1 81 0
13
+ .cfi_startproc
14
+.LVL0:
15
+.LBB22:
16
+ .loc 1 82 0
17
+#APP
18
+// 82 "drivers/misc/rk3562-secure-otp.c" 1
19
+ dmb sy
20
+// 0 "" 2
21
+#NO_APP
22
+ mov w1, 524288
23
+.LVL1:
24
+ str w1, [x0]
25
+ ret
26
+.LBE22:
27
+ .cfi_endproc
28
+.LFE263:
29
+ .size rk3562_spl_rockchip_otp_stop, .-rk3562_spl_rockchip_otp_stop
30
+ .section .text.secure_otp_ioctl,"ax",@progbits
31
+ .align 2
32
+ .type secure_otp_ioctl, %function
33
+secure_otp_ioctl:
34
+.LFB276:
35
+ .loc 1 697 0
36
+ .cfi_startproc
37
+.LVL2:
38
+ .loc 1 700 0
39
+ mov x0, 27908
40
+.LVL3:
41
+ cmp x1, x0
42
+ bne .L6
43
+.LVL4:
44
+.LBB23:
45
+.LBB24:
46
+ .loc 1 689 0
47
+ mov w0, 8
48
+ str w0, [x2]
49
+.LVL5:
50
+.LBE24:
51
+.LBE23:
52
+ .loc 1 702 0
53
+ mov w0, 0
54
+ .loc 1 703 0
55
+ ret
56
+.LVL6:
57
+.L6:
58
+ .loc 1 698 0
59
+ mov w0, -22
60
+ .loc 1 709 0
61
+ ret
62
+ .cfi_endproc
63
+.LFE276:
64
+ .size secure_otp_ioctl, .-secure_otp_ioctl
65
+ .section .text.secure_otp_write,"ax",@progbits
66
+ .align 2
67
+ .type secure_otp_write, %function
68
+secure_otp_write:
69
+.LFB274:
70
+ .loc 1 681 0
71
+ .cfi_startproc
72
+.LVL7:
73
+ stp x29, x30, [sp, -48]!
74
+ .cfi_def_cfa_offset 48
75
+ .cfi_offset 29, -48
76
+ .cfi_offset 30, -40
77
+ add x29, sp, 0
78
+ .cfi_def_cfa_register 29
79
+ stp x19, x20, [sp, 16]
80
+ .cfi_offset 19, -32
81
+ .cfi_offset 20, -24
82
+ mov x19, x0
83
+ stp x21, x22, [sp, 32]
84
+ .cfi_offset 21, -16
85
+ .cfi_offset 22, -8
86
+ .loc 1 681 0
87
+ mov w20, w1
88
+ mov x21, x2
89
+ mov w22, w3
90
+ .loc 1 682 0
91
+ bl dev_get_driver_data
92
+.LVL8:
93
+ .loc 1 684 0
94
+ ldr x4, [x0, 8]
95
+ mov w3, w22
96
+ mov x2, x21
97
+ mov w1, w20
98
+ mov x0, x19
99
+.LVL9:
100
+ .loc 1 685 0
101
+ ldp x21, x22, [sp, 32]
102
+.LVL10:
103
+ ldp x19, x20, [sp, 16]
104
+.LVL11:
105
+ ldp x29, x30, [sp], 48
106
+ .cfi_restore 30
107
+ .cfi_restore 29
108
+ .cfi_restore 21
109
+ .cfi_restore 22
110
+ .cfi_restore 19
111
+ .cfi_restore 20
112
+ .cfi_def_cfa 31, 0
113
+ .loc 1 684 0
114
+ br x4
115
+.LVL12:
116
+ .cfi_endproc
117
+.LFE274:
118
+ .size secure_otp_write, .-secure_otp_write
119
+ .section .text.secure_otp_read,"ax",@progbits
120
+ .align 2
121
+ .type secure_otp_read, %function
122
+secure_otp_read:
123
+.LFB273:
124
+ .loc 1 673 0
125
+ .cfi_startproc
126
+.LVL13:
127
+ stp x29, x30, [sp, -48]!
128
+ .cfi_def_cfa_offset 48
129
+ .cfi_offset 29, -48
130
+ .cfi_offset 30, -40
131
+ add x29, sp, 0
132
+ .cfi_def_cfa_register 29
133
+ stp x19, x20, [sp, 16]
134
+ .cfi_offset 19, -32
135
+ .cfi_offset 20, -24
136
+ mov x19, x0
137
+ stp x21, x22, [sp, 32]
138
+ .cfi_offset 21, -16
139
+ .cfi_offset 22, -8
140
+ .loc 1 673 0
141
+ mov w20, w1
142
+ mov x21, x2
143
+ mov w22, w3
144
+ .loc 1 674 0
145
+ bl dev_get_driver_data
146
+.LVL14:
147
+ .loc 1 676 0
148
+ ldr x4, [x0]
149
+ mov w3, w22
150
+ mov x2, x21
151
+ mov w1, w20
152
+ mov x0, x19
153
+.LVL15:
154
+ .loc 1 677 0
155
+ ldp x21, x22, [sp, 32]
156
+.LVL16:
157
+ ldp x19, x20, [sp, 16]
158
+.LVL17:
159
+ ldp x29, x30, [sp], 48
160
+ .cfi_restore 30
161
+ .cfi_restore 29
162
+ .cfi_restore 21
163
+ .cfi_restore 22
164
+ .cfi_restore 19
165
+ .cfi_restore 20
166
+ .cfi_def_cfa 31, 0
167
+ .loc 1 676 0
168
+ br x4
169
+.LVL18:
170
+ .cfi_endproc
171
+.LFE273:
172
+ .size secure_otp_read, .-secure_otp_read
173
+ .section .text.rockchip_secure_otp_ofdata_to_platdata,"ax",@progbits
174
+ .align 2
175
+ .type rockchip_secure_otp_ofdata_to_platdata, %function
176
+rockchip_secure_otp_ofdata_to_platdata:
177
+.LFB277:
178
+ .loc 1 718 0
179
+ .cfi_startproc
180
+.LVL19:
181
+ stp x29, x30, [sp, -32]!
182
+ .cfi_def_cfa_offset 32
183
+ .cfi_offset 29, -32
184
+ .cfi_offset 30, -24
185
+ add x29, sp, 0
186
+ .cfi_def_cfa_register 29
187
+ stp x19, x20, [sp, 16]
188
+ .cfi_offset 19, -16
189
+ .cfi_offset 20, -8
190
+ .loc 1 718 0
191
+ mov x20, x0
192
+ .loc 1 719 0
193
+ bl dev_get_platdata
194
+.LVL20:
195
+ mov x19, x0
196
+.LVL21:
197
+ .loc 1 721 0
198
+ mov x0, x20
199
+.LVL22:
200
+ bl dev_read_addr_ptr
201
+.LVL23:
202
+ .loc 1 722 0
203
+ mov w2, 0
204
+ adrp x1, .LC0
205
+ .loc 1 721 0
206
+ str x0, [x19]
207
+ .loc 1 722 0
208
+ add x1, x1, :lo12:.LC0
209
+ mov x0, x20
210
+ bl dev_read_u32_default
211
+.LVL24:
212
+ .loc 1 723 0
213
+ uxtw x0, w0
214
+ str x0, [x19, 8]
215
+ .loc 1 724 0
216
+ mov w2, 0
217
+ mov x0, x20
218
+ adrp x1, .LC1
219
+ add x1, x1, :lo12:.LC1
220
+ bl dev_read_u32_default
221
+.LVL25:
222
+ .loc 1 725 0
223
+ uxtw x0, w0
224
+ str x0, [x19, 16]
225
+ .loc 1 726 0
226
+ mov w2, 0
227
+ mov x0, x20
228
+ adrp x1, .LC2
229
+ add x1, x1, :lo12:.LC2
230
+ bl dev_read_u32_default
231
+.LVL26:
232
+ .loc 1 727 0
233
+ uxtw x0, w0
234
+ str x0, [x19, 24]
235
+ .loc 1 730 0
236
+ mov w0, 0
237
+ ldp x19, x20, [sp, 16]
238
+.LVL27:
239
+ ldp x29, x30, [sp], 32
240
+ .cfi_restore 30
241
+ .cfi_restore 29
242
+ .cfi_restore 19
243
+ .cfi_restore 20
244
+ .cfi_def_cfa 31, 0
245
+ ret
246
+ .cfi_endproc
247
+.LFE277:
248
+ .size rockchip_secure_otp_ofdata_to_platdata, .-rockchip_secure_otp_ofdata_to_platdata
249
+ .section .text.rk3562_spl_rockchip_otp_start,"ax",@progbits
250
+ .align 2
251
+ .type rk3562_spl_rockchip_otp_start, %function
252
+rk3562_spl_rockchip_otp_start:
253
+.LFB262:
254
+ .loc 1 69 0
255
+ .cfi_startproc
256
+.LVL28:
257
+ stp x29, x30, [sp, -32]!
258
+ .cfi_def_cfa_offset 32
259
+ .cfi_offset 29, -32
260
+ .cfi_offset 30, -24
261
+ add x29, sp, 0
262
+ .cfi_def_cfa_register 29
263
+ str x19, [sp, 16]
264
+ .cfi_offset 19, -16
265
+ .loc 1 69 0
266
+ mov x19, x1
267
+.LBB25:
268
+ .loc 1 71 0
269
+#APP
270
+// 71 "drivers/misc/rk3562-secure-otp.c" 1
271
+ dmb sy
272
+// 0 "" 2
273
+#NO_APP
274
+ mov w1, 524296
275
+.LVL29:
276
+ str w1, [x0]
277
+.LVL30:
278
+.LBE25:
279
+.LBB26:
280
+ .loc 1 72 0
281
+#APP
282
+// 72 "drivers/misc/rk3562-secure-otp.c" 1
283
+ dmb sy
284
+// 0 "" 2
285
+#NO_APP
286
+ mov w0, 1048592
287
+.LVL31:
288
+ str w0, [x19]
289
+.LBE26:
290
+ .loc 1 73 0
291
+ mov x0, 2
292
+ bl udelay
293
+.LVL32:
294
+.LBB27:
295
+ .loc 1 74 0
296
+#APP
297
+// 74 "drivers/misc/rk3562-secure-otp.c" 1
298
+ dmb sy
299
+// 0 "" 2
300
+#NO_APP
301
+ mov w0, 1048576
302
+ str w0, [x19]
303
+.LBE27:
304
+ .loc 1 76 0
305
+ ldr x19, [sp, 16]
306
+.LVL33:
307
+ .loc 1 75 0
308
+ mov x0, 1
309
+ .loc 1 76 0
310
+ ldp x29, x30, [sp], 32
311
+ .cfi_restore 30
312
+ .cfi_restore 29
313
+ .cfi_restore 19
314
+ .cfi_def_cfa 31, 0
315
+ .loc 1 75 0
316
+ b udelay
317
+.LVL34:
318
+ .cfi_endproc
319
+.LFE262:
320
+ .size rk3562_spl_rockchip_otp_start, .-rk3562_spl_rockchip_otp_start
321
+ .section .text.rockchip_secure_otp_check_flag.isra.0,"ax",@progbits
322
+ .align 2
323
+ .type rockchip_secure_otp_check_flag.isra.0, %function
324
+rockchip_secure_otp_check_flag.isra.0:
325
+.LFB278:
326
+ .loc 1 129 0
327
+ .cfi_startproc
328
+ stp x29, x30, [sp, -32]!
329
+ .cfi_def_cfa_offset 32
330
+ .cfi_offset 29, -32
331
+ .cfi_offset 30, -24
332
+ add x29, sp, 0
333
+ .cfi_def_cfa_register 29
334
+ stp x19, x20, [sp, 16]
335
+ .cfi_offset 19, -16
336
+ .cfi_offset 20, -8
337
+ .loc 1 129 0
338
+ mov w19, 34465
339
+ mov x20, x0
340
+ movk w19, 0x1, lsl 16
341
+.L17:
342
+.LVL35:
343
+.LBB28:
344
+ .loc 1 136 0
345
+ ldr x0, [x20]
346
+ ldr w1, [x0, 44]
347
+.LVL36:
348
+#APP
349
+// 136 "drivers/misc/rk3562-secure-otp.c" 1
350
+ dmb sy
351
+// 0 "" 2
352
+.LVL37:
353
+#NO_APP
354
+.LBE28:
355
+ .loc 1 137 0
356
+ and w0, w1, 16
357
+ tbz x1, 4, .L15
358
+ .loc 1 140 0
359
+ subs w19, w19, #1
360
+.LVL38:
361
+ beq .L18
362
+.LVL39:
363
+ .loc 1 146 0
364
+ mov x0, 1
365
+ bl udelay
366
+.LVL40:
367
+ b .L17
368
+.LVL41:
369
+.L18:
370
+ .loc 1 141 0
371
+ mov w0, -1
372
+.LVL42:
373
+.L15:
374
+ .loc 1 150 0
375
+ ldp x19, x20, [sp, 16]
376
+ ldp x29, x30, [sp], 32
377
+ .cfi_restore 30
378
+ .cfi_restore 29
379
+ .cfi_restore 19
380
+ .cfi_restore 20
381
+ .cfi_def_cfa 31, 0
382
+ ret
383
+ .cfi_endproc
384
+.LFE278:
385
+ .size rockchip_secure_otp_check_flag.isra.0, .-rockchip_secure_otp_check_flag.isra.0
386
+ .section .text.rockchip_secure_otp_wait_flag.isra.1,"ax",@progbits
387
+ .align 2
388
+ .type rockchip_secure_otp_wait_flag.isra.1, %function
389
+rockchip_secure_otp_wait_flag.isra.1:
390
+.LFB279:
391
+ .loc 1 106 0
392
+ .cfi_startproc
393
+ stp x29, x30, [sp, -32]!
394
+ .cfi_def_cfa_offset 32
395
+ .cfi_offset 29, -32
396
+ .cfi_offset 30, -24
397
+ add x29, sp, 0
398
+ .cfi_def_cfa_register 29
399
+ stp x19, x20, [sp, 16]
400
+ .cfi_offset 19, -16
401
+ .cfi_offset 20, -8
402
+ .loc 1 106 0
403
+ mov x20, x0
404
+ mov w19, 20001
405
+.L25:
406
+.LVL43:
407
+.LBB29:
408
+ .loc 1 113 0
409
+ ldr x0, [x20]
410
+ ldr w0, [x0, 44]
411
+.LVL44:
412
+#APP
413
+// 113 "drivers/misc/rk3562-secure-otp.c" 1
414
+ dmb sy
415
+// 0 "" 2
416
+.LVL45:
417
+#NO_APP
418
+.LBE29:
419
+ .loc 1 114 0
420
+ tbnz x0, 4, .L26
421
+ .loc 1 117 0
422
+ subs w19, w19, #1
423
+.LVL46:
424
+ beq .L27
425
+ .loc 1 122 0
426
+ mov x0, 1
427
+.LVL47:
428
+ bl udelay
429
+.LVL48:
430
+ b .L25
431
+.LVL49:
432
+.L26:
433
+ .loc 1 110 0
434
+ mov w0, 0
435
+.LVL50:
436
+.L23:
437
+ .loc 1 127 0
438
+ ldp x19, x20, [sp, 16]
439
+ ldp x29, x30, [sp], 32
440
+ .cfi_remember_state
441
+ .cfi_restore 30
442
+ .cfi_restore 29
443
+ .cfi_restore 19
444
+ .cfi_restore 20
445
+ .cfi_def_cfa 31, 0
446
+ ret
447
+.LVL51:
448
+.L27:
449
+ .cfi_restore_state
450
+ .loc 1 118 0
451
+ mov w0, -1
452
+.LVL52:
453
+ b .L23
454
+ .cfi_endproc
455
+.LFE279:
456
+ .size rockchip_secure_otp_wait_flag.isra.1, .-rockchip_secure_otp_wait_flag.isra.1
457
+ .section .text.rockchip_secure_otp_wait_status.isra.2,"ax",@progbits
458
+ .align 2
459
+ .type rockchip_secure_otp_wait_status.isra.2, %function
460
+rockchip_secure_otp_wait_status.isra.2:
461
+.LFB280:
462
+ .loc 1 86 0
463
+ .cfi_startproc
464
+.LVL53:
465
+ stp x29, x30, [sp, -48]!
466
+ .cfi_def_cfa_offset 48
467
+ .cfi_offset 29, -48
468
+ .cfi_offset 30, -40
469
+ add x29, sp, 0
470
+ .cfi_def_cfa_register 29
471
+ stp x19, x20, [sp, 16]
472
+ .cfi_offset 19, -32
473
+ .cfi_offset 20, -24
474
+ mov w19, w1
475
+ str x21, [sp, 32]
476
+ .cfi_offset 21, -16
477
+ .loc 1 86 0
478
+ mov x21, x0
479
+ mov w20, 10000
480
+.LVL54:
481
+.L30:
482
+.LBB36:
483
+ .loc 1 91 0
484
+ ldr x0, [x21]
485
+ ldr w0, [x0, 772]
486
+.LVL55:
487
+#APP
488
+// 91 "drivers/misc/rk3562-secure-otp.c" 1
489
+ dmb sy
490
+// 0 "" 2
491
+#NO_APP
492
+.LBE36:
493
+ tst w0, w19
494
+ beq .L32
495
+.LBB37:
496
+ .loc 1 101 0
497
+ orr w19, w19, -65536
498
+.LVL56:
499
+#APP
500
+// 101 "drivers/misc/rk3562-secure-otp.c" 1
501
+ dmb sy
502
+// 0 "" 2
503
+#NO_APP
504
+ ldr x0, [x21]
505
+.LVL57:
506
+ str w19, [x0, 772]
507
+.LBE37:
508
+ .loc 1 103 0
509
+ mov w0, 0
510
+ b .L29
511
+.LVL58:
512
+.L32:
513
+ .loc 1 92 0
514
+ mov x0, 1
515
+.LVL59:
516
+ bl udelay
517
+.LVL60:
518
+ .loc 1 94 0
519
+ subs w20, w20, #1
520
+.LVL61:
521
+ bne .L30
522
+.LVL62:
523
+.LBB38:
524
+.LBB39:
525
+ .loc 1 95 0
526
+ adrp x1, .LANCHOR0
527
+ adrp x0, .LC3
528
+ add x1, x1, :lo12:.LANCHOR0
529
+ add x0, x0, :lo12:.LC3
530
+ bl printf
531
+.LVL63:
532
+ mov w0, -110
533
+.LVL64:
534
+.L29:
535
+.LBE39:
536
+.LBE38:
537
+ .loc 1 104 0
538
+ ldp x19, x20, [sp, 16]
539
+.LVL65:
540
+ ldr x21, [sp, 32]
541
+ ldp x29, x30, [sp], 48
542
+ .cfi_restore 30
543
+ .cfi_restore 29
544
+ .cfi_restore 21
545
+ .cfi_restore 19
546
+ .cfi_restore 20
547
+ .cfi_def_cfa 31, 0
548
+ ret
549
+ .cfi_endproc
550
+.LFE280:
551
+ .size rockchip_secure_otp_wait_status.isra.2, .-rockchip_secure_otp_wait_status.isra.2
552
+ .section .text.rk3562_secure_otp_write_2_bytes_noecc,"ax",@progbits
553
+ .align 2
554
+ .type rk3562_secure_otp_write_2_bytes_noecc, %function
555
+rk3562_secure_otp_write_2_bytes_noecc:
556
+.LFB269:
557
+ .loc 1 240 0
558
+ .cfi_startproc
559
+.LVL66:
560
+ stp x29, x30, [sp, -96]!
561
+ .cfi_def_cfa_offset 96
562
+ .cfi_offset 29, -96
563
+ .cfi_offset 30, -88
564
+ add x29, sp, 0
565
+ .cfi_def_cfa_register 29
566
+ stp x23, x24, [sp, 48]
567
+ .cfi_offset 23, -48
568
+ .cfi_offset 24, -40
569
+ mov w24, w2
570
+ stp x19, x20, [sp, 16]
571
+ .cfi_offset 19, -80
572
+ .cfi_offset 20, -72
573
+ .loc 1 244 0
574
+ asr w20, w24, 1
575
+ .loc 1 240 0
576
+ stp x21, x22, [sp, 32]
577
+ .cfi_offset 21, -64
578
+ .cfi_offset 22, -56
579
+ and w21, w3, 65535
580
+ stp x25, x26, [sp, 64]
581
+ .cfi_offset 25, -32
582
+ .cfi_offset 26, -24
583
+ mov x26, x1
584
+ stp x27, x28, [sp, 80]
585
+ .cfi_offset 27, -16
586
+ .cfi_offset 28, -8
587
+ .loc 1 242 0
588
+ bl dev_get_driver_data
589
+.LVL67:
590
+ .loc 1 245 0
591
+ cmp w20, 447
592
+ bgt .L43
593
+ mov x23, x0
594
+ .loc 1 249 0
595
+ sub w0, w20, #416
596
+.LVL68:
597
+ cmp w0, 15
598
+ ccmp w20, 16, 4, hi
599
+ beq .L37
600
+ .loc 1 252 0
601
+ adrp x0, .LC4
602
+ and w1, w24, -2
603
+ add x0, x0, :lo12:.LC4
604
+ bl printf
605
+.LVL69:
606
+.L43:
607
+ .loc 1 246 0
608
+ mov w0, -1
609
+.LVL70:
610
+.L35:
611
+ .loc 1 446 0
612
+ ldp x19, x20, [sp, 16]
613
+.LVL71:
614
+ ldp x21, x22, [sp, 32]
615
+ ldp x23, x24, [sp, 48]
616
+ ldp x25, x26, [sp, 64]
617
+.LVL72:
618
+ ldp x27, x28, [sp, 80]
619
+ ldp x29, x30, [sp], 96
620
+ .cfi_remember_state
621
+ .cfi_restore 30
622
+ .cfi_restore 29
623
+ .cfi_restore 27
624
+ .cfi_restore 28
625
+ .cfi_restore 25
626
+ .cfi_restore 26
627
+ .cfi_restore 23
628
+ .cfi_restore 24
629
+ .cfi_restore 21
630
+ .cfi_restore 22
631
+ .cfi_restore 19
632
+ .cfi_restore 20
633
+ .cfi_def_cfa 31, 0
634
+ ret
635
+.LVL73:
636
+.L37:
637
+ .cfi_restore_state
638
+ .loc 1 256 0
639
+ cbz w21, .L44
640
+ .loc 1 259 0
641
+ ldr x6, [x23, 16]
642
+ mov w3, w20
643
+ ldp x0, x2, [x26, 8]
644
+ ldr x1, [x26, 24]
645
+ blr x6
646
+.LVL74:
647
+.LBB40:
648
+ .loc 1 262 0
649
+#APP
650
+// 262 "drivers/misc/rk3562-secure-otp.c" 1
651
+ dmb sy
652
+// 0 "" 2
653
+#NO_APP
654
+ ldr x0, [x26]
655
+ mov w1, 65536
656
+ str w1, [x0, 256]
657
+.LVL75:
658
+.LBE40:
659
+.LBB41:
660
+ .loc 1 263 0
661
+#APP
662
+// 263 "drivers/misc/rk3562-secure-otp.c" 1
663
+ dmb sy
664
+// 0 "" 2
665
+#NO_APP
666
+ ldr x0, [x26]
667
+ mov w1, 262148
668
+ str w1, [x0, 32]
669
+.LVL76:
670
+.LBE41:
671
+.LBB42:
672
+ .loc 1 264 0
673
+#APP
674
+// 264 "drivers/misc/rk3562-secure-otp.c" 1
675
+ dmb sy
676
+// 0 "" 2
677
+#NO_APP
678
+ ldr x0, [x26]
679
+ mov w1, -65536
680
+ str w1, [x0, 40]
681
+.LVL77:
682
+.LBE42:
683
+.LBB43:
684
+ .loc 1 265 0
685
+#APP
686
+// 265 "drivers/misc/rk3562-secure-otp.c" 1
687
+ dmb sy
688
+// 0 "" 2
689
+#NO_APP
690
+ ldr x0, [x26]
691
+ mov w1, 512
692
+ movk w1, 0xff00, lsl 16
693
+ str w1, [x0, 32]
694
+.LVL78:
695
+.LBE43:
696
+.LBB44:
697
+ .loc 1 266 0
698
+#APP
699
+// 266 "drivers/misc/rk3562-secure-otp.c" 1
700
+ dmb sy
701
+// 0 "" 2
702
+#NO_APP
703
+ ldr x0, [x26]
704
+ mov w22, -65534
705
+ str w22, [x0, 36]
706
+.LVL79:
707
+.LBE44:
708
+.LBB45:
709
+ .loc 1 267 0
710
+#APP
711
+// 267 "drivers/misc/rk3562-secure-otp.c" 1
712
+ dmb sy
713
+// 0 "" 2
714
+#NO_APP
715
+ ldr x0, [x26]
716
+ mov w1, 252
717
+ str w1, [x0, 4096]
718
+.LVL80:
719
+.LBE45:
720
+.LBB46:
721
+ .loc 1 268 0
722
+#APP
723
+// 268 "drivers/misc/rk3562-secure-otp.c" 1
724
+ dmb sy
725
+// 0 "" 2
726
+#NO_APP
727
+ ldr x0, [x26]
728
+ str wzr, [x0, 4100]
729
+.LVL81:
730
+.LBE46:
731
+.LBB47:
732
+ .loc 1 269 0
733
+#APP
734
+// 269 "drivers/misc/rk3562-secure-otp.c" 1
735
+ dmb sy
736
+// 0 "" 2
737
+#NO_APP
738
+ ldr x0, [x26]
739
+ str wzr, [x0, 4104]
740
+.LVL82:
741
+.LBE47:
742
+.LBB48:
743
+ .loc 1 270 0
744
+#APP
745
+// 270 "drivers/misc/rk3562-secure-otp.c" 1
746
+ dmb sy
747
+// 0 "" 2
748
+#NO_APP
749
+ ldr x0, [x26]
750
+ mov w19, 65537
751
+.LBE48:
752
+ .loc 1 271 0
753
+ mov w1, 2
754
+.LBB49:
755
+ .loc 1 270 0
756
+ str w19, [x0, 32]
757
+.LBE49:
758
+ .loc 1 271 0
759
+ mov x0, x26
760
+ bl rockchip_secure_otp_wait_status.isra.2
761
+.LVL83:
762
+ .loc 1 272 0
763
+ tbz w0, #31, .L38
764
+.L40:
765
+ .loc 1 273 0
766
+ adrp x1, .LANCHOR1
767
+ adrp x0, .LC5
768
+.LVL84:
769
+ add x1, x1, :lo12:.LANCHOR1
770
+ add x0, x0, :lo12:.LC5
771
+.L46:
772
+ .loc 1 406 0
773
+ bl printf
774
+.LVL85:
775
+.L39:
776
+ .loc 1 442 0
777
+ ldr x5, [x23, 24]
778
+ mov w3, w20
779
+ ldp x0, x2, [x26, 8]
780
+ ldr x1, [x26, 24]
781
+ blr x5
782
+.LVL86:
783
+.L44:
784
+ .loc 1 257 0
785
+ mov w0, 0
786
+ b .L35
787
+.LVL87:
788
+.L38:
789
+.LBB50:
790
+ .loc 1 277 0
791
+#APP
792
+// 277 "drivers/misc/rk3562-secure-otp.c" 1
793
+ dmb sy
794
+// 0 "" 2
795
+#NO_APP
796
+ ldr x0, [x26]
797
+.LVL88:
798
+ mov w28, -65522
799
+ str w28, [x0, 36]
800
+.LVL89:
801
+.LBE50:
802
+.LBB51:
803
+ .loc 1 278 0
804
+#APP
805
+// 278 "drivers/misc/rk3562-secure-otp.c" 1
806
+ dmb sy
807
+// 0 "" 2
808
+#NO_APP
809
+ ldr x0, [x26]
810
+ mov w27, 240
811
+ str w27, [x0, 4096]
812
+.LVL90:
813
+.LBE51:
814
+.LBB52:
815
+ .loc 1 279 0
816
+#APP
817
+// 279 "drivers/misc/rk3562-secure-otp.c" 1
818
+ dmb sy
819
+// 0 "" 2
820
+#NO_APP
821
+ ldr x0, [x26]
822
+ mov w1, 1
823
+ str w1, [x0, 4100]
824
+.LVL91:
825
+.LBE52:
826
+.LBB53:
827
+ .loc 1 280 0
828
+#APP
829
+// 280 "drivers/misc/rk3562-secure-otp.c" 1
830
+ dmb sy
831
+// 0 "" 2
832
+#NO_APP
833
+ ldr x0, [x26]
834
+ mov w25, 122
835
+ str w25, [x0, 4104]
836
+.LVL92:
837
+.LBE53:
838
+.LBB54:
839
+ .loc 1 281 0
840
+#APP
841
+// 281 "drivers/misc/rk3562-secure-otp.c" 1
842
+ dmb sy
843
+// 0 "" 2
844
+#NO_APP
845
+ ldr x0, [x26]
846
+ mov w1, 37
847
+ str w1, [x0, 4108]
848
+.LVL93:
849
+.LBE54:
850
+.LBB55:
851
+ .loc 1 282 0
852
+#APP
853
+// 282 "drivers/misc/rk3562-secure-otp.c" 1
854
+ dmb sy
855
+// 0 "" 2
856
+#NO_APP
857
+ ldr x0, [x26]
858
+ str wzr, [x0, 4112]
859
+.LVL94:
860
+.LBE55:
861
+.LBB56:
862
+ .loc 1 283 0
863
+#APP
864
+// 283 "drivers/misc/rk3562-secure-otp.c" 1
865
+ dmb sy
866
+// 0 "" 2
867
+#NO_APP
868
+ ldr x0, [x26]
869
+ str wzr, [x0, 4116]
870
+.LVL95:
871
+.LBE56:
872
+.LBB57:
873
+ .loc 1 284 0
874
+#APP
875
+// 284 "drivers/misc/rk3562-secure-otp.c" 1
876
+ dmb sy
877
+// 0 "" 2
878
+#NO_APP
879
+ ldr x0, [x26]
880
+ str wzr, [x0, 4120]
881
+.LVL96:
882
+.LBE57:
883
+.LBB58:
884
+ .loc 1 285 0
885
+#APP
886
+// 285 "drivers/misc/rk3562-secure-otp.c" 1
887
+ dmb sy
888
+// 0 "" 2
889
+#NO_APP
890
+ ldr x0, [x26]
891
+ mov w1, 31
892
+ str w1, [x0, 4124]
893
+.LVL97:
894
+.LBE58:
895
+.LBB59:
896
+ .loc 1 286 0
897
+#APP
898
+// 286 "drivers/misc/rk3562-secure-otp.c" 1
899
+ dmb sy
900
+// 0 "" 2
901
+#NO_APP
902
+ ldr x0, [x26]
903
+ mov w1, 11
904
+ str w1, [x0, 4128]
905
+.LVL98:
906
+.LBE59:
907
+.LBB60:
908
+ .loc 1 287 0
909
+#APP
910
+// 287 "drivers/misc/rk3562-secure-otp.c" 1
911
+ dmb sy
912
+// 0 "" 2
913
+#NO_APP
914
+ ldr x0, [x26]
915
+ mov w1, 8
916
+ str w1, [x0, 4132]
917
+.LVL99:
918
+.LBE60:
919
+.LBB61:
920
+ .loc 1 288 0
921
+#APP
922
+// 288 "drivers/misc/rk3562-secure-otp.c" 1
923
+ dmb sy
924
+// 0 "" 2
925
+#NO_APP
926
+ ldr x0, [x26]
927
+ str wzr, [x0, 4136]
928
+.LVL100:
929
+.LBE61:
930
+.LBB62:
931
+ .loc 1 289 0
932
+#APP
933
+// 289 "drivers/misc/rk3562-secure-otp.c" 1
934
+ dmb sy
935
+// 0 "" 2
936
+#NO_APP
937
+ ldr x0, [x26]
938
+ str wzr, [x0, 4140]
939
+.LVL101:
940
+.LBE62:
941
+.LBB63:
942
+ .loc 1 290 0
943
+#APP
944
+// 290 "drivers/misc/rk3562-secure-otp.c" 1
945
+ dmb sy
946
+// 0 "" 2
947
+#NO_APP
948
+ ldr x0, [x26]
949
+ str wzr, [x0, 4144]
950
+.LBE63:
951
+.LBB64:
952
+ .loc 1 291 0
953
+ and w0, w20, 255
954
+#APP
955
+// 291 "drivers/misc/rk3562-secure-otp.c" 1
956
+ dmb sy
957
+// 0 "" 2
958
+#NO_APP
959
+ ldr x1, [x26]
960
+.LBE64:
961
+.LBB65:
962
+ .loc 1 292 0
963
+ ubfx x5, x24, 9, 8
964
+.LVL102:
965
+.LBE65:
966
+.LBB66:
967
+ .loc 1 291 0
968
+ str w0, [x1, 4148]
969
+.LBE66:
970
+.LBB67:
971
+ .loc 1 292 0
972
+#APP
973
+// 292 "drivers/misc/rk3562-secure-otp.c" 1
974
+ dmb sy
975
+// 0 "" 2
976
+#NO_APP
977
+ ldr x0, [x26]
978
+ str w5, [x0, 4152]
979
+.LVL103:
980
+.LBE67:
981
+.LBB68:
982
+ .loc 1 293 0
983
+#APP
984
+// 293 "drivers/misc/rk3562-secure-otp.c" 1
985
+ dmb sy
986
+// 0 "" 2
987
+#NO_APP
988
+ ldr x0, [x26]
989
+.LBE68:
990
+ .loc 1 294 0
991
+ mov w1, 2
992
+.LBB69:
993
+ .loc 1 293 0
994
+ str w19, [x0, 32]
995
+.LBE69:
996
+ .loc 1 294 0
997
+ mov x0, x26
998
+ bl rockchip_secure_otp_wait_status.isra.2
999
+.LVL104:
1000
+ .loc 1 295 0
1001
+ tbnz w0, #31, .L40
1002
+.LVL105:
1003
+.LBB70:
1004
+ .loc 1 300 0
1005
+#APP
1006
+// 300 "drivers/misc/rk3562-secure-otp.c" 1
1007
+ dmb sy
1008
+// 0 "" 2
1009
+#NO_APP
1010
+ ldr x0, [x26]
1011
+.LVL106:
1012
+ mov w1, -65535
1013
+ str w1, [x0, 36]
1014
+.LVL107:
1015
+.LBE70:
1016
+.LBB71:
1017
+ .loc 1 301 0
1018
+#APP
1019
+// 301 "drivers/misc/rk3562-secure-otp.c" 1
1020
+ dmb sy
1021
+// 0 "" 2
1022
+#NO_APP
1023
+ ldr x0, [x26]
1024
+ mov w1, 250
1025
+ str w1, [x0, 4096]
1026
+.LVL108:
1027
+.LBE71:
1028
+.LBB72:
1029
+ .loc 1 302 0
1030
+#APP
1031
+// 302 "drivers/misc/rk3562-secure-otp.c" 1
1032
+ dmb sy
1033
+// 0 "" 2
1034
+#NO_APP
1035
+ ldr x0, [x26]
1036
+ mov w1, 9
1037
+ str w1, [x0, 4100]
1038
+.LVL109:
1039
+.LBE72:
1040
+.LBB73:
1041
+ .loc 1 303 0
1042
+#APP
1043
+// 303 "drivers/misc/rk3562-secure-otp.c" 1
1044
+ dmb sy
1045
+// 0 "" 2
1046
+#NO_APP
1047
+ ldr x0, [x26]
1048
+.LBE73:
1049
+ .loc 1 304 0
1050
+ mov w1, 2
1051
+.LBB74:
1052
+ .loc 1 303 0
1053
+ str w19, [x0, 32]
1054
+.LBE74:
1055
+ .loc 1 304 0
1056
+ mov x0, x26
1057
+ bl rockchip_secure_otp_wait_status.isra.2
1058
+.LVL110:
1059
+ .loc 1 305 0
1060
+ tbnz w0, #31, .L40
1061
+.LVL111:
1062
+.LBB75:
1063
+ .loc 1 310 0
1064
+#APP
1065
+// 310 "drivers/misc/rk3562-secure-otp.c" 1
1066
+ dmb sy
1067
+// 0 "" 2
1068
+#NO_APP
1069
+ ldr x0, [x26]
1070
+.LVL112:
1071
+ mov w1, 14848
1072
+ movk w1, 0xff00, lsl 16
1073
+ str w1, [x0, 32]
1074
+.LVL113:
1075
+.LBE75:
1076
+.LBB76:
1077
+ .loc 1 311 0
1078
+#APP
1079
+// 311 "drivers/misc/rk3562-secure-otp.c" 1
1080
+ dmb sy
1081
+// 0 "" 2
1082
+#NO_APP
1083
+ ldr x0, [x26]
1084
+ str w28, [x0, 36]
1085
+.LVL114:
1086
+.LBE76:
1087
+.LBB77:
1088
+ .loc 1 312 0
1089
+#APP
1090
+// 312 "drivers/misc/rk3562-secure-otp.c" 1
1091
+ dmb sy
1092
+// 0 "" 2
1093
+#NO_APP
1094
+ ldr x0, [x26]
1095
+ str w27, [x0, 4096]
1096
+.LVL115:
1097
+.LBE77:
1098
+.LBB78:
1099
+ .loc 1 313 0
1100
+#APP
1101
+// 313 "drivers/misc/rk3562-secure-otp.c" 1
1102
+ dmb sy
1103
+// 0 "" 2
1104
+#NO_APP
1105
+ ldr x0, [x26]
1106
+ mov w1, 1
1107
+ str w1, [x0, 4100]
1108
+.LVL116:
1109
+.LBE78:
1110
+.LBB79:
1111
+ .loc 1 314 0
1112
+#APP
1113
+// 314 "drivers/misc/rk3562-secure-otp.c" 1
1114
+ dmb sy
1115
+// 0 "" 2
1116
+#NO_APP
1117
+ ldr x0, [x26]
1118
+ str w25, [x0, 4104]
1119
+.LVL117:
1120
+.LBE79:
1121
+.LBB80:
1122
+ .loc 1 315 0
1123
+#APP
1124
+// 315 "drivers/misc/rk3562-secure-otp.c" 1
1125
+ dmb sy
1126
+// 0 "" 2
1127
+#NO_APP
1128
+ ldr x0, [x26]
1129
+ mov w1, 21
1130
+ str w1, [x0, 4108]
1131
+.LVL118:
1132
+.LBE80:
1133
+.LBB81:
1134
+ .loc 1 316 0
1135
+#APP
1136
+// 316 "drivers/misc/rk3562-secure-otp.c" 1
1137
+ dmb sy
1138
+// 0 "" 2
1139
+#NO_APP
1140
+ ldr x0, [x26]
1141
+ mov w1, 220
1142
+ str w1, [x0, 4112]
1143
+.LVL119:
1144
+.LBE81:
1145
+.LBB82:
1146
+ .loc 1 317 0
1147
+#APP
1148
+// 317 "drivers/misc/rk3562-secure-otp.c" 1
1149
+ dmb sy
1150
+// 0 "" 2
1151
+#NO_APP
1152
+ ldr x0, [x26]
1153
+ mov w1, 146
1154
+ str w1, [x0, 4116]
1155
+.LVL120:
1156
+.LBE82:
1157
+.LBB83:
1158
+ .loc 1 318 0
1159
+#APP
1160
+// 318 "drivers/misc/rk3562-secure-otp.c" 1
1161
+ dmb sy
1162
+// 0 "" 2
1163
+#NO_APP
1164
+ ldr x0, [x26]
1165
+ mov w1, 121
1166
+ str w1, [x0, 4120]
1167
+.LVL121:
1168
+.LBE83:
1169
+.LBB84:
1170
+ .loc 1 319 0
1171
+#APP
1172
+// 319 "drivers/misc/rk3562-secure-otp.c" 1
1173
+ dmb sy
1174
+// 0 "" 2
1175
+#NO_APP
1176
+ ldr x0, [x26]
1177
+ mov w1, 129
1178
+ str w1, [x0, 4124]
1179
+.LVL122:
1180
+.LBE84:
1181
+.LBB85:
1182
+ .loc 1 320 0
1183
+#APP
1184
+// 320 "drivers/misc/rk3562-secure-otp.c" 1
1185
+ dmb sy
1186
+// 0 "" 2
1187
+#NO_APP
1188
+ ldr x0, [x26]
1189
+ mov w1, 126
1190
+ str w1, [x0, 4128]
1191
+.LVL123:
1192
+.LBE85:
1193
+.LBB86:
1194
+ .loc 1 321 0
1195
+#APP
1196
+// 321 "drivers/misc/rk3562-secure-otp.c" 1
1197
+ dmb sy
1198
+// 0 "" 2
1199
+#NO_APP
1200
+ ldr x0, [x26]
1201
+ mov w1, 33
1202
+ str w1, [x0, 4132]
1203
+.LVL124:
1204
+.LBE86:
1205
+.LBB87:
1206
+ .loc 1 322 0
1207
+#APP
1208
+// 322 "drivers/misc/rk3562-secure-otp.c" 1
1209
+ dmb sy
1210
+// 0 "" 2
1211
+#NO_APP
1212
+ ldr x0, [x26]
1213
+ mov w1, 17
1214
+ str w1, [x0, 4136]
1215
+.LVL125:
1216
+.LBE87:
1217
+.LBB88:
1218
+ .loc 1 323 0
1219
+#APP
1220
+// 323 "drivers/misc/rk3562-secure-otp.c" 1
1221
+ dmb sy
1222
+// 0 "" 2
1223
+#NO_APP
1224
+ ldr x0, [x26]
1225
+ mov w1, 157
1226
+ str w1, [x0, 4140]
1227
+.LVL126:
1228
+.LBE88:
1229
+.LBB89:
1230
+ .loc 1 324 0
1231
+#APP
1232
+// 324 "drivers/misc/rk3562-secure-otp.c" 1
1233
+ dmb sy
1234
+// 0 "" 2
1235
+#NO_APP
1236
+ ldr x0, [x26]
1237
+ mov w25, 2
1238
+ str w25, [x0, 4144]
1239
+.LVL127:
1240
+.LBE89:
1241
+.LBB90:
1242
+ .loc 1 325 0
1243
+#APP
1244
+// 325 "drivers/misc/rk3562-secure-otp.c" 1
1245
+ dmb sy
1246
+// 0 "" 2
1247
+#NO_APP
1248
+ ldr x0, [x26]
1249
+ str wzr, [x0, 4148]
1250
+.LVL128:
1251
+.LBE90:
1252
+.LBB91:
1253
+ .loc 1 326 0
1254
+#APP
1255
+// 326 "drivers/misc/rk3562-secure-otp.c" 1
1256
+ dmb sy
1257
+// 0 "" 2
1258
+#NO_APP
1259
+ ldr x0, [x26]
1260
+ mov w1, 64
1261
+ str w1, [x0, 4152]
1262
+.LVL129:
1263
+.LBE91:
1264
+.LBB92:
1265
+ .loc 1 327 0
1266
+#APP
1267
+// 327 "drivers/misc/rk3562-secure-otp.c" 1
1268
+ dmb sy
1269
+// 0 "" 2
1270
+#NO_APP
1271
+ ldr x0, [x26]
1272
+.LBE92:
1273
+ .loc 1 328 0
1274
+ mov w1, w25
1275
+.LBB93:
1276
+ .loc 1 327 0
1277
+ str w19, [x0, 32]
1278
+.LBE93:
1279
+ .loc 1 328 0
1280
+ mov x0, x26
1281
+ bl rockchip_secure_otp_wait_status.isra.2
1282
+.LVL130:
1283
+ .loc 1 329 0
1284
+ tbnz w0, #31, .L40
1285
+.LVL131:
1286
+.LBB94:
1287
+ .loc 1 334 0
1288
+#APP
1289
+// 334 "drivers/misc/rk3562-secure-otp.c" 1
1290
+ dmb sy
1291
+// 0 "" 2
1292
+#NO_APP
1293
+ ldr x0, [x26]
1294
+.LVL132:
1295
+ str w22, [x0, 36]
1296
+.LVL133:
1297
+.LBE94:
1298
+.LBB95:
1299
+ .loc 1 335 0
1300
+#APP
1301
+// 335 "drivers/misc/rk3562-secure-otp.c" 1
1302
+ dmb sy
1303
+// 0 "" 2
1304
+#NO_APP
1305
+ ldr x0, [x26]
1306
+ mov w1, 252
1307
+ str w1, [x0, 4096]
1308
+.LVL134:
1309
+.LBE95:
1310
+.LBB96:
1311
+ .loc 1 336 0
1312
+#APP
1313
+// 336 "drivers/misc/rk3562-secure-otp.c" 1
1314
+ dmb sy
1315
+// 0 "" 2
1316
+#NO_APP
1317
+ ldr x0, [x26]
1318
+ mov w1, 10
1319
+ str w1, [x0, 4100]
1320
+.LVL135:
1321
+.LBE96:
1322
+.LBB97:
1323
+ .loc 1 337 0
1324
+#APP
1325
+// 337 "drivers/misc/rk3562-secure-otp.c" 1
1326
+ dmb sy
1327
+// 0 "" 2
1328
+#NO_APP
1329
+ ldr x0, [x26]
1330
+ mov w1, 112
1331
+ str w1, [x0, 4104]
1332
+.LVL136:
1333
+.LBE97:
1334
+.LBB98:
1335
+ .loc 1 338 0
1336
+#APP
1337
+// 338 "drivers/misc/rk3562-secure-otp.c" 1
1338
+ dmb sy
1339
+// 0 "" 2
1340
+#NO_APP
1341
+ ldr x0, [x26]
1342
+.LBE98:
1343
+ .loc 1 339 0
1344
+ mov w1, w25
1345
+.LBB99:
1346
+ .loc 1 338 0
1347
+ str w19, [x0, 32]
1348
+.LBE99:
1349
+ .loc 1 339 0
1350
+ mov x0, x26
1351
+ bl rockchip_secure_otp_wait_status.isra.2
1352
+.LVL137:
1353
+ .loc 1 340 0
1354
+ tbnz w0, #31, .L40
1355
+.LVL138:
1356
+.LBB100:
1357
+ .loc 1 345 0
1358
+#APP
1359
+// 345 "drivers/misc/rk3562-secure-otp.c" 1
1360
+ dmb sy
1361
+// 0 "" 2
1362
+#NO_APP
1363
+ ldr x0, [x26]
1364
+.LVL139:
1365
+ mov w1, 512
1366
+ movk w1, 0xff00, lsl 16
1367
+ str w1, [x0, 32]
1368
+.LVL140:
1369
+.LBE100:
1370
+.LBB101:
1371
+ .loc 1 346 0
1372
+#APP
1373
+// 346 "drivers/misc/rk3562-secure-otp.c" 1
1374
+ dmb sy
1375
+// 0 "" 2
1376
+#NO_APP
1377
+ ldr x0, [x26]
1378
+ str w22, [x0, 36]
1379
+.LVL141:
1380
+.LBE101:
1381
+.LBB102:
1382
+ .loc 1 347 0
1383
+#APP
1384
+// 347 "drivers/misc/rk3562-secure-otp.c" 1
1385
+ dmb sy
1386
+// 0 "" 2
1387
+#NO_APP
1388
+ ldr x0, [x26]
1389
+ mov w1, 192
1390
+ str w1, [x0, 4096]
1391
+.LBE102:
1392
+.LBB103:
1393
+ .loc 1 348 0
1394
+ and w1, w21, 255
1395
+.LVL142:
1396
+#APP
1397
+// 348 "drivers/misc/rk3562-secure-otp.c" 1
1398
+ dmb sy
1399
+// 0 "" 2
1400
+#NO_APP
1401
+ ldr x0, [x26]
1402
+.LBE103:
1403
+.LBB104:
1404
+ .loc 1 349 0
1405
+ lsr w21, w21, 8
1406
+.LVL143:
1407
+.LBE104:
1408
+.LBB105:
1409
+ .loc 1 348 0
1410
+ str w1, [x0, 4100]
1411
+.LBE105:
1412
+.LBB106:
1413
+ .loc 1 349 0
1414
+#APP
1415
+// 349 "drivers/misc/rk3562-secure-otp.c" 1
1416
+ dmb sy
1417
+// 0 "" 2
1418
+#NO_APP
1419
+ ldr x0, [x26]
1420
+ str w21, [x0, 4104]
1421
+.LVL144:
1422
+.LBE106:
1423
+.LBB107:
1424
+ .loc 1 350 0
1425
+#APP
1426
+// 350 "drivers/misc/rk3562-secure-otp.c" 1
1427
+ dmb sy
1428
+// 0 "" 2
1429
+#NO_APP
1430
+ ldr x0, [x26]
1431
+.LBE107:
1432
+ .loc 1 351 0
1433
+ mov w1, w25
1434
+.LVL145:
1435
+.LBB108:
1436
+ .loc 1 350 0
1437
+ str w19, [x0, 32]
1438
+.LBE108:
1439
+ .loc 1 351 0
1440
+ mov x0, x26
1441
+ bl rockchip_secure_otp_wait_status.isra.2
1442
+.LVL146:
1443
+ .loc 1 352 0
1444
+ tbnz w0, #31, .L40
1445
+.LVL147:
1446
+.LBB109:
1447
+ .loc 1 357 0
1448
+#APP
1449
+// 357 "drivers/misc/rk3562-secure-otp.c" 1
1450
+ dmb sy
1451
+// 0 "" 2
1452
+#NO_APP
1453
+ ldr x0, [x26]
1454
+.LVL148:
1455
+ mov w1, -65535
1456
+ str w1, [x0, 36]
1457
+.LVL149:
1458
+.LBE109:
1459
+.LBB110:
1460
+ .loc 1 358 0
1461
+#APP
1462
+// 358 "drivers/misc/rk3562-secure-otp.c" 1
1463
+ dmb sy
1464
+// 0 "" 2
1465
+#NO_APP
1466
+ ldr x0, [x26]
1467
+ mov w1, 224
1468
+ str w1, [x0, 4096]
1469
+.LVL150:
1470
+.LBE110:
1471
+.LBB111:
1472
+ .loc 1 359 0
1473
+#APP
1474
+// 359 "drivers/misc/rk3562-secure-otp.c" 1
1475
+ dmb sy
1476
+// 0 "" 2
1477
+#NO_APP
1478
+ ldr x0, [x26]
1479
+ str wzr, [x0, 4100]
1480
+.LVL151:
1481
+.LBE111:
1482
+.LBB112:
1483
+ .loc 1 360 0
1484
+#APP
1485
+// 360 "drivers/misc/rk3562-secure-otp.c" 1
1486
+ dmb sy
1487
+// 0 "" 2
1488
+#NO_APP
1489
+ ldr x0, [x26]
1490
+.LBE112:
1491
+ .loc 1 361 0
1492
+ mov w1, w25
1493
+.LBB113:
1494
+ .loc 1 360 0
1495
+ str w19, [x0, 32]
1496
+.LBE113:
1497
+ .loc 1 361 0
1498
+ mov x0, x26
1499
+ bl rockchip_secure_otp_wait_status.isra.2
1500
+.LVL152:
1501
+ .loc 1 362 0
1502
+ tbnz w0, #31, .L40
1503
+.LVL153:
1504
+.LBB114:
1505
+ .loc 1 367 0
1506
+#APP
1507
+// 367 "drivers/misc/rk3562-secure-otp.c" 1
1508
+ dmb sy
1509
+// 0 "" 2
1510
+#NO_APP
1511
+ ldr x0, [x26]
1512
+.LVL154:
1513
+ mov w22, -65535
1514
+ str w22, [x0, 36]
1515
+.LVL155:
1516
+.LBE114:
1517
+.LBB115:
1518
+ .loc 1 368 0
1519
+#APP
1520
+// 368 "drivers/misc/rk3562-secure-otp.c" 1
1521
+ dmb sy
1522
+// 0 "" 2
1523
+#NO_APP
1524
+ ldr x0, [x26]
1525
+ mov w1, 14848
1526
+ movk w1, 0xff00, lsl 16
1527
+ str w1, [x0, 32]
1528
+.LVL156:
1529
+.LBE115:
1530
+.LBB116:
1531
+ .loc 1 369 0
1532
+#APP
1533
+// 369 "drivers/misc/rk3562-secure-otp.c" 1
1534
+ dmb sy
1535
+// 0 "" 2
1536
+#NO_APP
1537
+ ldr x0, [x26]
1538
+ mov w1, 255
1539
+ str w1, [x0, 4096]
1540
+.LVL157:
1541
+.LBE116:
1542
+.LBB117:
1543
+ .loc 1 370 0
1544
+#APP
1545
+// 370 "drivers/misc/rk3562-secure-otp.c" 1
1546
+ dmb sy
1547
+// 0 "" 2
1548
+#NO_APP
1549
+ ldr x0, [x26]
1550
+ mov w1, 10
1551
+ str w1, [x0, 4100]
1552
+.LVL158:
1553
+.LBE117:
1554
+.LBB118:
1555
+ .loc 1 371 0
1556
+#APP
1557
+// 371 "drivers/misc/rk3562-secure-otp.c" 1
1558
+ dmb sy
1559
+// 0 "" 2
1560
+#NO_APP
1561
+ ldr x0, [x26]
1562
+ mov w21, 65537
1563
+.LVL159:
1564
+.LBE118:
1565
+ .loc 1 372 0
1566
+ mov w1, w25
1567
+.LBB119:
1568
+ .loc 1 371 0
1569
+ str w21, [x0, 32]
1570
+.LBE119:
1571
+ .loc 1 372 0
1572
+ mov x0, x26
1573
+ bl rockchip_secure_otp_wait_status.isra.2
1574
+.LVL160:
1575
+ .loc 1 373 0
1576
+ tbnz w0, #31, .L40
1577
+.LVL161:
1578
+.LBB120:
1579
+ .loc 1 378 0
1580
+#APP
1581
+// 378 "drivers/misc/rk3562-secure-otp.c" 1
1582
+ dmb sy
1583
+// 0 "" 2
1584
+#NO_APP
1585
+ ldr x0, [x26]
1586
+.LVL162:
1587
+ str w22, [x0, 36]
1588
+.LVL163:
1589
+.LBE120:
1590
+.LBB121:
1591
+ .loc 1 379 0
1592
+#APP
1593
+// 379 "drivers/misc/rk3562-secure-otp.c" 1
1594
+ dmb sy
1595
+// 0 "" 2
1596
+#NO_APP
1597
+ ldr x0, [x26]
1598
+ mov w1, 1
1599
+ str w1, [x0, 4096]
1600
+.LVL164:
1601
+.LBE121:
1602
+.LBB122:
1603
+ .loc 1 380 0
1604
+#APP
1605
+// 380 "drivers/misc/rk3562-secure-otp.c" 1
1606
+ dmb sy
1607
+// 0 "" 2
1608
+#NO_APP
1609
+ ldr x0, [x26]
1610
+ mov w24, 191
1611
+.LVL165:
1612
+ str w24, [x0, 4100]
1613
+.LVL166:
1614
+.LBE122:
1615
+.LBB123:
1616
+ .loc 1 381 0
1617
+#APP
1618
+// 381 "drivers/misc/rk3562-secure-otp.c" 1
1619
+ dmb sy
1620
+// 0 "" 2
1621
+#NO_APP
1622
+ ldr x0, [x26]
1623
+.LBE123:
1624
+ .loc 1 382 0
1625
+ mov w1, w25
1626
+.LBB124:
1627
+ .loc 1 381 0
1628
+ str w21, [x0, 32]
1629
+.LBE124:
1630
+ .loc 1 382 0
1631
+ mov x0, x26
1632
+ bl rockchip_secure_otp_wait_status.isra.2
1633
+.LVL167:
1634
+ .loc 1 383 0
1635
+ tbnz w0, #31, .L40
1636
+ .loc 1 388 0
1637
+ mov x0, x26
1638
+.LVL168:
1639
+ bl rockchip_secure_otp_check_flag.isra.0
1640
+.LVL169:
1641
+ .loc 1 389 0
1642
+ tbz w0, #31, .L41
1643
+ .loc 1 390 0
1644
+ adrp x1, .LANCHOR1
1645
+ adrp x0, .LC6
1646
+.LVL170:
1647
+ add x1, x1, :lo12:.LANCHOR1
1648
+ add x0, x0, :lo12:.LC6
1649
+ b .L46
1650
+.LVL171:
1651
+.L41:
1652
+.LBB125:
1653
+ .loc 1 394 0
1654
+#APP
1655
+// 394 "drivers/misc/rk3562-secure-otp.c" 1
1656
+ dmb sy
1657
+// 0 "" 2
1658
+#NO_APP
1659
+ ldr x0, [x26]
1660
+.LVL172:
1661
+ str w22, [x0, 36]
1662
+.LVL173:
1663
+.LBE125:
1664
+.LBB126:
1665
+ .loc 1 395 0
1666
+#APP
1667
+// 395 "drivers/misc/rk3562-secure-otp.c" 1
1668
+ dmb sy
1669
+// 0 "" 2
1670
+#NO_APP
1671
+ ldr x0, [x26]
1672
+ mov w19, 2
1673
+ str w19, [x0, 4096]
1674
+.LVL174:
1675
+.LBE126:
1676
+.LBB127:
1677
+ .loc 1 396 0
1678
+#APP
1679
+// 396 "drivers/misc/rk3562-secure-otp.c" 1
1680
+ dmb sy
1681
+// 0 "" 2
1682
+#NO_APP
1683
+ ldr x0, [x26]
1684
+ str w24, [x0, 4100]
1685
+.LVL175:
1686
+.LBE127:
1687
+.LBB128:
1688
+ .loc 1 397 0
1689
+#APP
1690
+// 397 "drivers/misc/rk3562-secure-otp.c" 1
1691
+ dmb sy
1692
+// 0 "" 2
1693
+#NO_APP
1694
+ ldr x0, [x26]
1695
+.LBE128:
1696
+ .loc 1 398 0
1697
+ mov w1, w19
1698
+.LBB129:
1699
+ .loc 1 397 0
1700
+ str w21, [x0, 32]
1701
+.LBE129:
1702
+ .loc 1 398 0
1703
+ mov x0, x26
1704
+ bl rockchip_secure_otp_wait_status.isra.2
1705
+.LVL176:
1706
+ .loc 1 399 0
1707
+ tbnz w0, #31, .L40
1708
+ .loc 1 404 0
1709
+ mov x0, x26
1710
+.LVL177:
1711
+ bl rockchip_secure_otp_wait_flag.isra.1
1712
+.LVL178:
1713
+ .loc 1 405 0
1714
+ tbz w0, #31, .L42
1715
+ .loc 1 406 0
1716
+ adrp x1, .LANCHOR1
1717
+ adrp x0, .LC7
1718
+.LVL179:
1719
+ add x1, x1, :lo12:.LANCHOR1
1720
+ add x0, x0, :lo12:.LC7
1721
+ b .L46
1722
+.LVL180:
1723
+.L42:
1724
+.LBB130:
1725
+ .loc 1 410 0
1726
+#APP
1727
+// 410 "drivers/misc/rk3562-secure-otp.c" 1
1728
+ dmb sy
1729
+// 0 "" 2
1730
+#NO_APP
1731
+ ldr x0, [x26]
1732
+.LVL181:
1733
+ mov w1, -65533
1734
+ str w1, [x0, 772]
1735
+.LVL182:
1736
+.LBE130:
1737
+.LBB131:
1738
+ .loc 1 411 0
1739
+#APP
1740
+// 411 "drivers/misc/rk3562-secure-otp.c" 1
1741
+ dmb sy
1742
+// 0 "" 2
1743
+#NO_APP
1744
+ ldr x0, [x26]
1745
+ mov w1, 512
1746
+ movk w1, 0xff00, lsl 16
1747
+ str w1, [x0, 32]
1748
+.LVL183:
1749
+.LBE131:
1750
+.LBB132:
1751
+ .loc 1 412 0
1752
+#APP
1753
+// 412 "drivers/misc/rk3562-secure-otp.c" 1
1754
+ dmb sy
1755
+// 0 "" 2
1756
+#NO_APP
1757
+ ldr x0, [x26]
1758
+ str w22, [x0, 36]
1759
+.LVL184:
1760
+.LBE132:
1761
+.LBB133:
1762
+ .loc 1 413 0
1763
+#APP
1764
+// 413 "drivers/misc/rk3562-secure-otp.c" 1
1765
+ dmb sy
1766
+// 0 "" 2
1767
+#NO_APP
1768
+ ldr x0, [x26]
1769
+ str w19, [x0, 4096]
1770
+.LVL185:
1771
+.LBE133:
1772
+.LBB134:
1773
+ .loc 1 414 0
1774
+#APP
1775
+// 414 "drivers/misc/rk3562-secure-otp.c" 1
1776
+ dmb sy
1777
+// 0 "" 2
1778
+#NO_APP
1779
+ ldr x0, [x26]
1780
+ mov w1, 128
1781
+ str w1, [x0, 4100]
1782
+.LVL186:
1783
+.LBE134:
1784
+.LBB135:
1785
+ .loc 1 415 0
1786
+#APP
1787
+// 415 "drivers/misc/rk3562-secure-otp.c" 1
1788
+ dmb sy
1789
+// 0 "" 2
1790
+#NO_APP
1791
+ ldr x0, [x26]
1792
+.LBE135:
1793
+ .loc 1 416 0
1794
+ mov w1, w19
1795
+.LBB136:
1796
+ .loc 1 415 0
1797
+ str w21, [x0, 32]
1798
+.LBE136:
1799
+ .loc 1 416 0
1800
+ mov x0, x26
1801
+ bl rockchip_secure_otp_wait_status.isra.2
1802
+.LVL187:
1803
+ .loc 1 417 0
1804
+ tbnz w0, #31, .L40
1805
+.LVL188:
1806
+.LBB137:
1807
+ .loc 1 422 0
1808
+#APP
1809
+// 422 "drivers/misc/rk3562-secure-otp.c" 1
1810
+ dmb sy
1811
+// 0 "" 2
1812
+#NO_APP
1813
+ ldr x0, [x26]
1814
+.LVL189:
1815
+ str w22, [x0, 36]
1816
+.LVL190:
1817
+.LBE137:
1818
+.LBB138:
1819
+ .loc 1 423 0
1820
+#APP
1821
+// 423 "drivers/misc/rk3562-secure-otp.c" 1
1822
+ dmb sy
1823
+// 0 "" 2
1824
+#NO_APP
1825
+ ldr x0, [x26]
1826
+ mov w1, 160
1827
+ str w1, [x0, 4096]
1828
+.LVL191:
1829
+.LBE138:
1830
+.LBB139:
1831
+ .loc 1 424 0
1832
+#APP
1833
+// 424 "drivers/misc/rk3562-secure-otp.c" 1
1834
+ dmb sy
1835
+// 0 "" 2
1836
+#NO_APP
1837
+ ldr x0, [x26]
1838
+ str wzr, [x0, 4100]
1839
+.LVL192:
1840
+.LBE139:
1841
+.LBB140:
1842
+ .loc 1 425 0
1843
+#APP
1844
+// 425 "drivers/misc/rk3562-secure-otp.c" 1
1845
+ dmb sy
1846
+// 0 "" 2
1847
+#NO_APP
1848
+ ldr x0, [x26]
1849
+.LBE140:
1850
+ .loc 1 426 0
1851
+ mov w1, w19
1852
+.LBB141:
1853
+ .loc 1 425 0
1854
+ str w21, [x0, 32]
1855
+.LBE141:
1856
+ .loc 1 426 0
1857
+ mov x0, x26
1858
+ bl rockchip_secure_otp_wait_status.isra.2
1859
+.LVL193:
1860
+ .loc 1 427 0
1861
+ tbnz w0, #31, .L40
1862
+.LVL194:
1863
+.LBB142:
1864
+ .loc 1 432 0
1865
+#APP
1866
+// 432 "drivers/misc/rk3562-secure-otp.c" 1
1867
+ dmb sy
1868
+// 0 "" 2
1869
+#NO_APP
1870
+ ldr x0, [x26]
1871
+.LVL195:
1872
+ mov w1, 250
1873
+ str w1, [x0, 4096]
1874
+.LVL196:
1875
+.LBE142:
1876
+.LBB143:
1877
+ .loc 1 433 0
1878
+#APP
1879
+// 433 "drivers/misc/rk3562-secure-otp.c" 1
1880
+ dmb sy
1881
+// 0 "" 2
1882
+#NO_APP
1883
+ ldr x0, [x26]
1884
+ mov w1, 9
1885
+ str w1, [x0, 4100]
1886
+.LVL197:
1887
+.LBE143:
1888
+.LBB144:
1889
+ .loc 1 434 0
1890
+#APP
1891
+// 434 "drivers/misc/rk3562-secure-otp.c" 1
1892
+ dmb sy
1893
+// 0 "" 2
1894
+#NO_APP
1895
+ ldr x0, [x26]
1896
+.LBE144:
1897
+ .loc 1 435 0
1898
+ mov w1, w19
1899
+.LBB145:
1900
+ .loc 1 434 0
1901
+ str w21, [x0, 32]
1902
+.LBE145:
1903
+ .loc 1 435 0
1904
+ mov x0, x26
1905
+ bl rockchip_secure_otp_wait_status.isra.2
1906
+.LVL198:
1907
+ .loc 1 436 0
1908
+ tbz w0, #31, .L39
1909
+ b .L40
1910
+ .cfi_endproc
1911
+.LFE269:
1912
+ .size rk3562_secure_otp_write_2_bytes_noecc, .-rk3562_secure_otp_write_2_bytes_noecc
1913
+ .section .text.rockchip_secure_otp_ecc_enable,"ax",@progbits
1914
+ .align 2
1915
+ .type rockchip_secure_otp_ecc_enable, %function
1916
+rockchip_secure_otp_ecc_enable:
1917
+.LFB267:
1918
+ .loc 1 154 0
1919
+ .cfi_startproc
1920
+.LVL199:
1921
+ stp x29, x30, [sp, -32]!
1922
+ .cfi_def_cfa_offset 32
1923
+ .cfi_offset 29, -32
1924
+ .cfi_offset 30, -24
1925
+ and w1, w1, 255
1926
+ add x29, sp, 0
1927
+ .cfi_def_cfa_register 29
1928
+ str x19, [sp, 16]
1929
+ .cfi_offset 19, -16
1930
+.LBB160:
1931
+ .loc 1 157 0
1932
+#APP
1933
+// 157 "drivers/misc/rk3562-secure-otp.c" 1
1934
+ dmb sy
1935
+// 0 "" 2
1936
+#NO_APP
1937
+ ldr x2, [x0]
1938
+ mov w3, 512
1939
+ movk w3, 0xff00, lsl 16
1940
+ str w3, [x2, 32]
1941
+.LVL200:
1942
+.LBE160:
1943
+.LBB161:
1944
+ .loc 1 158 0
1945
+#APP
1946
+// 158 "drivers/misc/rk3562-secure-otp.c" 1
1947
+ dmb sy
1948
+// 0 "" 2
1949
+#NO_APP
1950
+ ldr x2, [x0]
1951
+ mov w3, -65535
1952
+ str w3, [x2, 36]
1953
+.LVL201:
1954
+.LBE161:
1955
+.LBB162:
1956
+ .loc 1 159 0
1957
+#APP
1958
+// 159 "drivers/misc/rk3562-secure-otp.c" 1
1959
+ dmb sy
1960
+// 0 "" 2
1961
+#NO_APP
1962
+ ldr x2, [x0]
1963
+ mov w3, 250
1964
+ str w3, [x2, 4096]
1965
+.LBE162:
1966
+ .loc 1 160 0
1967
+ cbz w1, .L48
1968
+.LVL202:
1969
+.LBB163:
1970
+ .loc 1 161 0
1971
+#APP
1972
+// 161 "drivers/misc/rk3562-secure-otp.c" 1
1973
+ dmb sy
1974
+// 0 "" 2
1975
+#NO_APP
1976
+ ldr x1, [x0]
1977
+.LVL203:
1978
+ str wzr, [x1, 4100]
1979
+.LVL204:
1980
+.L49:
1981
+.LBE163:
1982
+.LBB164:
1983
+ .loc 1 165 0
1984
+#APP
1985
+// 165 "drivers/misc/rk3562-secure-otp.c" 1
1986
+ dmb sy
1987
+// 0 "" 2
1988
+#NO_APP
1989
+ ldr x1, [x0]
1990
+ mov w2, 65537
1991
+ str w2, [x1, 32]
1992
+.LBE164:
1993
+ .loc 1 167 0
1994
+ mov w1, 2
1995
+ bl rockchip_secure_otp_wait_status.isra.2
1996
+.LVL205:
1997
+ mov w19, w0
1998
+.LVL206:
1999
+ .loc 1 168 0
2000
+ tbz w0, #31, .L47
2001
+.LVL207:
2002
+.LBB165:
2003
+.LBB166:
2004
+ .loc 1 169 0
2005
+ adrp x1, .LANCHOR2
2006
+ adrp x0, .LC8
2007
+.LVL208:
2008
+ add x1, x1, :lo12:.LANCHOR2
2009
+ add x0, x0, :lo12:.LC8
2010
+ bl printf
2011
+.LVL209:
2012
+.L47:
2013
+.LBE166:
2014
+.LBE165:
2015
+ .loc 1 172 0
2016
+ mov w0, w19
2017
+ ldr x19, [sp, 16]
2018
+.LVL210:
2019
+ ldp x29, x30, [sp], 32
2020
+ .cfi_remember_state
2021
+ .cfi_restore 30
2022
+ .cfi_restore 29
2023
+ .cfi_restore 19
2024
+ .cfi_def_cfa 31, 0
2025
+ ret
2026
+.LVL211:
2027
+.L48:
2028
+ .cfi_restore_state
2029
+.LBB167:
2030
+ .loc 1 163 0
2031
+#APP
2032
+// 163 "drivers/misc/rk3562-secure-otp.c" 1
2033
+ dmb sy
2034
+// 0 "" 2
2035
+#NO_APP
2036
+ ldr x1, [x0]
2037
+ mov w2, 9
2038
+ str w2, [x1, 4100]
2039
+ b .L49
2040
+.LBE167:
2041
+ .cfi_endproc
2042
+.LFE267:
2043
+ .size rockchip_secure_otp_ecc_enable, .-rockchip_secure_otp_ecc_enable
2044
+ .section .text.rk3562_secure_otp_read,"ax",@progbits
2045
+ .align 2
2046
+ .type rk3562_secure_otp_read, %function
2047
+rk3562_secure_otp_read:
2048
+.LFB268:
2049
+ .loc 1 176 0
2050
+ .cfi_startproc
2051
+.LVL212:
2052
+ stp x29, x30, [sp, -80]!
2053
+ .cfi_def_cfa_offset 80
2054
+ .cfi_offset 29, -80
2055
+ .cfi_offset 30, -72
2056
+ add x29, sp, 0
2057
+ .cfi_def_cfa_register 29
2058
+ stp x19, x20, [sp, 16]
2059
+ .cfi_offset 19, -64
2060
+ .cfi_offset 20, -56
2061
+ .loc 1 183 0
2062
+ asr w19, w1, 1
2063
+ .loc 1 176 0
2064
+ stp x21, x22, [sp, 32]
2065
+ .cfi_offset 21, -48
2066
+ .cfi_offset 22, -40
2067
+ mov x21, x2
2068
+ stp x23, x24, [sp, 48]
2069
+ mov x22, x0
2070
+ .cfi_offset 23, -32
2071
+ .cfi_offset 24, -24
2072
+ mov w23, w3
2073
+ str x25, [sp, 64]
2074
+ .cfi_offset 25, -16
2075
+ .loc 1 177 0
2076
+ bl dev_get_platdata
2077
+.LVL213:
2078
+ mov x20, x0
2079
+.LVL214:
2080
+ .loc 1 178 0
2081
+ mov x0, x22
2082
+.LVL215:
2083
+ bl dev_get_driver_data
2084
+.LVL216:
2085
+ .loc 1 184 0
2086
+ ldr x4, [x0, 16]
2087
+ .loc 1 178 0
2088
+ mov x24, x0
2089
+.LVL217:
2090
+ .loc 1 184 0
2091
+ ldr x1, [x20, 24]
2092
+ mov w3, w19
2093
+ ldp x0, x2, [x20, 8]
2094
+.LVL218:
2095
+ blr x4
2096
+.LVL219:
2097
+ .loc 1 187 0
2098
+ sub w1, w19, #16
2099
+ sub w0, w19, #416
2100
+ cmp w1, 15
2101
+ ccmp w0, 31, 0, hi
2102
+ bhi .L53
2103
+ .loc 1 188 0
2104
+ mov w1, 0
2105
+.L65:
2106
+ .loc 1 190 0
2107
+ mov x0, x20
2108
+ bl rockchip_secure_otp_ecc_enable
2109
+.LVL220:
2110
+.LBB168:
2111
+ .loc 1 192 0
2112
+#APP
2113
+// 192 "drivers/misc/rk3562-secure-otp.c" 1
2114
+ dmb sy
2115
+// 0 "" 2
2116
+#NO_APP
2117
+ ldr x0, [x20]
2118
+ mov w25, 65537
2119
+.LBE168:
2120
+ .loc 1 181 0
2121
+ mov w22, 0
2122
+.LVL221:
2123
+.LBB169:
2124
+ .loc 1 192 0
2125
+ str w25, [x0, 256]
2126
+.LBE169:
2127
+ .loc 1 193 0
2128
+ mov x0, 50
2129
+ bl udelay
2130
+.LVL222:
2131
+.L55:
2132
+ .loc 1 194 0
2133
+ cbz w23, .L60
2134
+ .loc 1 196 0
2135
+ cmp w19, 447
2136
+ ble .L56
2137
+ .loc 1 197 0
2138
+ adrp x0, .LC9
2139
+ mov w1, w19
2140
+ add x0, x0, :lo12:.LC9
2141
+.L66:
2142
+ .loc 1 205 0
2143
+ mov w22, -1
2144
+.LVL223:
2145
+ .loc 1 204 0
2146
+ bl printf
2147
+.LVL224:
2148
+.L52:
2149
+ .loc 1 235 0
2150
+ mov w0, w22
2151
+ ldr x25, [sp, 64]
2152
+ ldp x19, x20, [sp, 16]
2153
+.LVL225:
2154
+ ldp x21, x22, [sp, 32]
2155
+ ldp x23, x24, [sp, 48]
2156
+.LVL226:
2157
+ ldp x29, x30, [sp], 80
2158
+ .cfi_remember_state
2159
+ .cfi_restore 30
2160
+ .cfi_restore 29
2161
+ .cfi_restore 25
2162
+ .cfi_restore 23
2163
+ .cfi_restore 24
2164
+ .cfi_restore 21
2165
+ .cfi_restore 22
2166
+ .cfi_restore 19
2167
+ .cfi_restore 20
2168
+ .cfi_def_cfa 31, 0
2169
+ ret
2170
+.LVL227:
2171
+.L53:
2172
+ .cfi_restore_state
2173
+ .loc 1 190 0
2174
+ mov w1, 1
2175
+ b .L65
2176
+.LVL228:
2177
+.L56:
2178
+ .loc 1 201 0
2179
+ sub w0, w19, #192
2180
+ cmp w0, 31
2181
+ ccmp w19, 16, 4, hi
2182
+ beq .L58
2183
+ .loc 1 201 0 is_stmt 0 discriminator 1
2184
+ sub w0, w19, #416
2185
+ cmp w0, 15
2186
+ bls .L58
2187
+ .loc 1 204 0 is_stmt 1
2188
+ adrp x0, .LC10
2189
+ lsl w1, w19, 1
2190
+ add x0, x0, :lo12:.LC10
2191
+ b .L66
2192
+.L58:
2193
+.LBB170:
2194
+ .loc 1 208 0
2195
+ orr w1, w19, -65536
2196
+.LVL229:
2197
+#APP
2198
+// 208 "drivers/misc/rk3562-secure-otp.c" 1
2199
+ dmb sy
2200
+// 0 "" 2
2201
+#NO_APP
2202
+ ldr x0, [x20]
2203
+.LBE170:
2204
+ .loc 1 209 0
2205
+ add w19, w19, 1
2206
+.LVL230:
2207
+.LBB171:
2208
+ .loc 1 208 0
2209
+ str w1, [x0, 260]
2210
+.LBE171:
2211
+.LBB172:
2212
+ .loc 1 210 0
2213
+#APP
2214
+// 210 "drivers/misc/rk3562-secure-otp.c" 1
2215
+ dmb sy
2216
+// 0 "" 2
2217
+#NO_APP
2218
+ ldr x0, [x20]
2219
+.LBE172:
2220
+ .loc 1 212 0
2221
+ mov w1, 4
2222
+.LVL231:
2223
+.LBB173:
2224
+ .loc 1 210 0
2225
+ str w25, [x0, 264]
2226
+.LVL232:
2227
+.LBE173:
2228
+ .loc 1 212 0
2229
+ mov x0, x20
2230
+ bl rockchip_secure_otp_wait_status.isra.2
2231
+.LVL233:
2232
+ mov w22, w0
2233
+.LVL234:
2234
+ .loc 1 213 0
2235
+ tbz w0, #31, .L59
2236
+ .loc 1 214 0
2237
+ adrp x1, .LANCHOR3
2238
+ adrp x0, .LC11
2239
+.LVL235:
2240
+ add x1, x1, :lo12:.LANCHOR3
2241
+ add x0, x0, :lo12:.LC11
2242
+ bl printf
2243
+.LVL236:
2244
+.L60:
2245
+.LBB174:
2246
+ .loc 1 228 0
2247
+#APP
2248
+// 228 "drivers/misc/rk3562-secure-otp.c" 1
2249
+ dmb sy
2250
+// 0 "" 2
2251
+#NO_APP
2252
+ ldr x0, [x20]
2253
+ mov w1, 65536
2254
+.LBE174:
2255
+ .loc 1 230 0
2256
+ ldr x2, [x20, 16]
2257
+ mov w3, w19
2258
+ ldr x4, [x24, 24]
2259
+.LBB175:
2260
+ .loc 1 228 0
2261
+ str w1, [x0, 256]
2262
+.LBE175:
2263
+ .loc 1 230 0
2264
+ ldr x0, [x20, 8]
2265
+ ldr x1, [x20, 24]
2266
+ blr x4
2267
+.LVL237:
2268
+ .loc 1 234 0
2269
+ b .L52
2270
+.LVL238:
2271
+.L59:
2272
+.LBB176:
2273
+ .loc 1 218 0
2274
+ ldr x0, [x20]
2275
+.LVL239:
2276
+ ldrh w0, [x0, 292]
2277
+ and w0, w0, 65535
2278
+.LVL240:
2279
+#APP
2280
+// 218 "drivers/misc/rk3562-secure-otp.c" 1
2281
+ dmb sy
2282
+// 0 "" 2
2283
+.LVL241:
2284
+#NO_APP
2285
+.LBE176:
2286
+ .loc 1 220 0
2287
+ strb w0, [x21]
2288
+ .loc 1 221 0
2289
+ cmp w23, 1
2290
+ beq .L60
2291
+.LVL242:
2292
+ .loc 1 222 0
2293
+ lsr w0, w0, 8
2294
+.LVL243:
2295
+ .loc 1 223 0
2296
+ sub w23, w23, #2
2297
+.LVL244:
2298
+ .loc 1 222 0
2299
+ strb w0, [x21, 1]
2300
+ add x21, x21, 2
2301
+.LVL245:
2302
+ b .L55
2303
+ .cfi_endproc
2304
+.LFE268:
2305
+ .size rk3562_secure_otp_read, .-rk3562_secure_otp_read
2306
+ .section .text.rk3562_secure_otp_write,"ax",@progbits
2307
+ .align 2
2308
+ .type rk3562_secure_otp_write, %function
2309
+rk3562_secure_otp_write:
2310
+.LFB272:
2311
+ .loc 1 621 0
2312
+ .cfi_startproc
2313
+.LVL246:
2314
+ stp x29, x30, [sp, -144]!
2315
+ .cfi_def_cfa_offset 144
2316
+ .cfi_offset 29, -144
2317
+ .cfi_offset 30, -136
2318
+ add x29, sp, 0
2319
+ .cfi_def_cfa_register 29
2320
+ stp x19, x20, [sp, 16]
2321
+ .cfi_offset 19, -128
2322
+ .cfi_offset 20, -120
2323
+ mov w20, w1
2324
+ stp x21, x22, [sp, 32]
2325
+ .cfi_offset 21, -112
2326
+ .cfi_offset 22, -104
2327
+ mov w21, w3
2328
+ stp x23, x24, [sp, 48]
2329
+ .cfi_offset 23, -96
2330
+ .cfi_offset 24, -88
2331
+ mov x24, x0
2332
+ stp x27, x28, [sp, 80]
2333
+ stp x25, x26, [sp, 64]
2334
+ .cfi_offset 27, -64
2335
+ .cfi_offset 28, -56
2336
+ .cfi_offset 25, -80
2337
+ .cfi_offset 26, -72
2338
+ .loc 1 621 0
2339
+ str x2, [x29, 112]
2340
+ .loc 1 622 0
2341
+ bl dev_get_platdata
2342
+.LVL247:
2343
+ mov x28, x0
2344
+.LVL248:
2345
+ .loc 1 625 0
2346
+ sxtw x0, w21
2347
+.LVL249:
2348
+ bl malloc_simple
2349
+.LVL250:
2350
+ .loc 1 628 0
2351
+ cbnz x0, .L68
2352
+.LVL251:
2353
+.L115:
2354
+ .loc 1 643 0
2355
+ mov w27, -1
2356
+.LVL252:
2357
+.L67:
2358
+ .loc 1 669 0
2359
+ mov w0, w27
2360
+ ldp x19, x20, [sp, 16]
2361
+.LVL253:
2362
+ ldp x21, x22, [sp, 32]
2363
+ ldp x23, x24, [sp, 48]
2364
+.LVL254:
2365
+ ldp x25, x26, [sp, 64]
2366
+ ldp x27, x28, [sp, 80]
2367
+.LVL255:
2368
+ ldp x29, x30, [sp], 144
2369
+ .cfi_remember_state
2370
+ .cfi_restore 30
2371
+ .cfi_restore 29
2372
+ .cfi_restore 27
2373
+ .cfi_restore 28
2374
+ .cfi_restore 25
2375
+ .cfi_restore 26
2376
+ .cfi_restore 23
2377
+ .cfi_restore 24
2378
+ .cfi_restore 21
2379
+ .cfi_restore 22
2380
+ .cfi_restore 19
2381
+ .cfi_restore 20
2382
+ .cfi_def_cfa 31, 0
2383
+.LVL256:
2384
+ ret
2385
+.LVL257:
2386
+.L68:
2387
+ .cfi_restore_state
2388
+ mov x19, x0
2389
+ .loc 1 631 0
2390
+ sub w0, w20, #384
2391
+.LVL258:
2392
+ cmp w0, 63
2393
+ bls .L70
2394
+.LVL259:
2395
+.L77:
2396
+ .loc 1 649 0
2397
+ sub w1, w20, #832
2398
+ sub w0, w20, #32
2399
+ cmp w1, 63
2400
+ ccmp w0, 31, 0, hi
2401
+ bls .L71
2402
+ .loc 1 659 0
2403
+ mov w0, 2
2404
+.LBB244:
2405
+.LBB245:
2406
+ .loc 1 607 0
2407
+ adrp x19, .LANCHOR4
2408
+.LVL260:
2409
+ add x19, x19, :lo12:.LANCHOR4
2410
+.LBE245:
2411
+.LBE244:
2412
+ .loc 1 659 0
2413
+ mov x23, 0
2414
+ sdiv w0, w21, w0
2415
+ str w0, [x29, 108]
2416
+.LVL261:
2417
+.L78:
2418
+ .loc 1 659 0 is_stmt 0 discriminator 1
2419
+ ldr w0, [x29, 108]
2420
+ cmp w0, w23
2421
+ ble .L97
2422
+ .loc 1 660 0 is_stmt 1
2423
+ ldr x0, [x29, 112]
2424
+ add w21, w20, w23, lsl 1
2425
+.LBB324:
2426
+.LBB320:
2427
+ .loc 1 477 0
2428
+ asr w25, w21, 1
2429
+.LBE320:
2430
+.LBE324:
2431
+ .loc 1 660 0
2432
+ ldrh w26, [x0, x23, lsl 1]
2433
+.LVL262:
2434
+.LBB325:
2435
+.LBB321:
2436
+ .loc 1 475 0
2437
+ mov x0, x24
2438
+ bl dev_get_driver_data
2439
+.LVL263:
2440
+ str x0, [x29, 120]
2441
+.LVL264:
2442
+ .loc 1 478 0
2443
+ cmp w25, 447
2444
+ bgt .L99
2445
+ .loc 1 482 0
2446
+ sub w0, w25, #192
2447
+.LVL265:
2448
+ cmp w0, 31
2449
+ bls .L85
2450
+ .loc 1 485 0
2451
+ adrp x0, .LC4
2452
+ and w1, w21, -2
2453
+ add x0, x0, :lo12:.LC4
2454
+ bl printf
2455
+.LVL266:
2456
+.L99:
2457
+ .loc 1 478 0
2458
+ mov w27, -1
2459
+ b .L84
2460
+.LVL267:
2461
+.L70:
2462
+.LBE321:
2463
+.LBE325:
2464
+ .loc 1 633 0
2465
+ mov w3, w21
2466
+ mov x2, x19
2467
+ mov w1, w20
2468
+ mov x0, x24
2469
+ bl rk3562_secure_otp_read
2470
+.LVL268:
2471
+ .loc 1 634 0
2472
+ cbnz w0, .L115
2473
+ mov x0, 0
2474
+.LVL269:
2475
+.L75:
2476
+ .loc 1 639 0 discriminator 1
2477
+ cmp w21, w0
2478
+ ble .L77
2479
+ add x0, x0, 1
2480
+.LVL270:
2481
+ .loc 1 640 0
2482
+ add x1, x19, x0
2483
+ ldrb w1, [x1, -1]
2484
+ cbz w1, .L75
2485
+ .loc 1 641 0
2486
+ adrp x0, .LC12
2487
+ add x0, x0, :lo12:.LC12
2488
+ bl printf
2489
+.LVL271:
2490
+ b .L115
2491
+.LVL272:
2492
+.L83:
2493
+.LBB326:
2494
+.LBB327:
2495
+ .loc 1 455 0
2496
+ adds w25, w20, w19
2497
+.LBE327:
2498
+.LBE326:
2499
+ .loc 1 652 0
2500
+ ldr x0, [x29, 112]
2501
+.LBB332:
2502
+.LBB328:
2503
+ .loc 1 455 0
2504
+ and w26, w25, 1
2505
+ mov w3, 2
2506
+ csneg w22, w26, w26, pl
2507
+ add x2, x29, 142
2508
+ sub w22, w25, w22
2509
+.LBE328:
2510
+.LBE332:
2511
+ .loc 1 652 0
2512
+ ldrb w23, [x0, x19]
2513
+.LVL273:
2514
+.LBB333:
2515
+.LBB329:
2516
+ .loc 1 455 0
2517
+ mov w1, w22
2518
+ mov x0, x24
2519
+ bl rk3562_secure_otp_read
2520
+.LVL274:
2521
+ .loc 1 456 0
2522
+ cbnz w0, .L79
2523
+ ldrh w3, [x29, 142]
2524
+ .loc 1 459 0
2525
+ cbnz w26, .L80
2526
+.LVL275:
2527
+ .loc 1 461 0
2528
+ bic w3, w23, w3
2529
+ mov w2, w25
2530
+.LVL276:
2531
+.L112:
2532
+ .loc 1 464 0
2533
+ mov x1, x28
2534
+ mov x0, x24
2535
+.LVL277:
2536
+ add x19, x19, 1
2537
+.LVL278:
2538
+ bl rk3562_secure_otp_write_2_bytes_noecc
2539
+.LVL279:
2540
+ mov w27, w0
2541
+.LVL280:
2542
+.LBE329:
2543
+.LBE333:
2544
+ .loc 1 653 0
2545
+ cbz w0, .L82
2546
+.L98:
2547
+ .loc 1 654 0
2548
+ adrp x0, .LC13
2549
+ add x0, x0, :lo12:.LC13
2550
+.LVL281:
2551
+.L114:
2552
+ .loc 1 662 0
2553
+ bl printf
2554
+.LVL282:
2555
+ .loc 1 663 0
2556
+ b .L67
2557
+.LVL283:
2558
+.L80:
2559
+.LBB334:
2560
+.LBB330:
2561
+ .loc 1 463 0
2562
+ lsl w23, w23, 8
2563
+.LVL284:
2564
+ .loc 1 464 0
2565
+ mov w2, w22
2566
+ bic w3, w23, w3
2567
+ b .L112
2568
+.LVL285:
2569
+.L71:
2570
+.LBE330:
2571
+.LBE334:
2572
+ mov x19, 0
2573
+.LVL286:
2574
+.L82:
2575
+ .loc 1 651 0 discriminator 1
2576
+ cmp w21, w19
2577
+ bgt .L83
2578
+.LVL287:
2579
+.L97:
2580
+ .loc 1 629 0
2581
+ mov w27, 0
2582
+ b .L67
2583
+.LVL288:
2584
+.L85:
2585
+.LBB335:
2586
+.LBB322:
2587
+ .loc 1 489 0
2588
+ cbz w26, .L86
2589
+ .loc 1 492 0
2590
+ ldr x0, [x29, 120]
2591
+ mov w3, w25
2592
+ ldp x2, x1, [x28, 16]
2593
+ ldr x5, [x0, 16]
2594
+ ldr x0, [x28, 8]
2595
+ blr x5
2596
+.LVL289:
2597
+.LBB246:
2598
+ .loc 1 495 0
2599
+#APP
2600
+// 495 "drivers/misc/rk3562-secure-otp.c" 1
2601
+ dmb sy
2602
+// 0 "" 2
2603
+#NO_APP
2604
+ ldr x0, [x28]
2605
+ mov w1, 65536
2606
+ str w1, [x0, 256]
2607
+.LVL290:
2608
+.LBE246:
2609
+.LBB247:
2610
+ .loc 1 496 0
2611
+#APP
2612
+// 496 "drivers/misc/rk3562-secure-otp.c" 1
2613
+ dmb sy
2614
+// 0 "" 2
2615
+#NO_APP
2616
+ ldr x0, [x28]
2617
+ mov w1, 262148
2618
+ str w1, [x0, 32]
2619
+.LVL291:
2620
+.LBE247:
2621
+.LBB248:
2622
+ .loc 1 497 0
2623
+#APP
2624
+// 497 "drivers/misc/rk3562-secure-otp.c" 1
2625
+ dmb sy
2626
+// 0 "" 2
2627
+#NO_APP
2628
+ ldr x0, [x28]
2629
+ mov w1, -65536
2630
+ str w1, [x0, 40]
2631
+.LVL292:
2632
+.LBE248:
2633
+.LBB249:
2634
+ .loc 1 498 0
2635
+#APP
2636
+// 498 "drivers/misc/rk3562-secure-otp.c" 1
2637
+ dmb sy
2638
+// 0 "" 2
2639
+#NO_APP
2640
+ ldr x0, [x28]
2641
+ mov w1, 512
2642
+ movk w1, 0xff00, lsl 16
2643
+ str w1, [x0, 32]
2644
+.LVL293:
2645
+.LBE249:
2646
+.LBB250:
2647
+ .loc 1 499 0
2648
+#APP
2649
+// 499 "drivers/misc/rk3562-secure-otp.c" 1
2650
+ dmb sy
2651
+// 0 "" 2
2652
+#NO_APP
2653
+ ldr x0, [x28]
2654
+ mov w1, -65522
2655
+ str w1, [x0, 36]
2656
+.LVL294:
2657
+.LBE250:
2658
+.LBB251:
2659
+ .loc 1 500 0
2660
+#APP
2661
+// 500 "drivers/misc/rk3562-secure-otp.c" 1
2662
+ dmb sy
2663
+// 0 "" 2
2664
+#NO_APP
2665
+ ldr x0, [x28]
2666
+ mov w3, 240
2667
+ str w3, [x29, 100]
2668
+.LVL295:
2669
+ str w3, [x0, 4096]
2670
+.LBE251:
2671
+.LBB252:
2672
+ .loc 1 501 0
2673
+#APP
2674
+// 501 "drivers/misc/rk3562-secure-otp.c" 1
2675
+ dmb sy
2676
+// 0 "" 2
2677
+#NO_APP
2678
+ ldr x0, [x28]
2679
+ mov w1, 1
2680
+ str w1, [x0, 4100]
2681
+.LVL296:
2682
+.LBE252:
2683
+.LBB253:
2684
+ .loc 1 502 0
2685
+#APP
2686
+// 502 "drivers/misc/rk3562-secure-otp.c" 1
2687
+ dmb sy
2688
+// 0 "" 2
2689
+#NO_APP
2690
+ ldr x0, [x28]
2691
+ mov w2, 122
2692
+ str w2, [x29, 104]
2693
+.LVL297:
2694
+ str w2, [x0, 4104]
2695
+.LBE253:
2696
+.LBB254:
2697
+ .loc 1 503 0
2698
+#APP
2699
+// 503 "drivers/misc/rk3562-secure-otp.c" 1
2700
+ dmb sy
2701
+// 0 "" 2
2702
+#NO_APP
2703
+ ldr x0, [x28]
2704
+ mov w1, 37
2705
+ str w1, [x0, 4108]
2706
+.LVL298:
2707
+.LBE254:
2708
+.LBB255:
2709
+ .loc 1 504 0
2710
+#APP
2711
+// 504 "drivers/misc/rk3562-secure-otp.c" 1
2712
+ dmb sy
2713
+// 0 "" 2
2714
+#NO_APP
2715
+ ldr x0, [x28]
2716
+ str wzr, [x0, 4112]
2717
+.LVL299:
2718
+.LBE255:
2719
+.LBB256:
2720
+ .loc 1 505 0
2721
+#APP
2722
+// 505 "drivers/misc/rk3562-secure-otp.c" 1
2723
+ dmb sy
2724
+// 0 "" 2
2725
+#NO_APP
2726
+ ldr x0, [x28]
2727
+ str wzr, [x0, 4116]
2728
+.LVL300:
2729
+.LBE256:
2730
+.LBB257:
2731
+ .loc 1 506 0
2732
+#APP
2733
+// 506 "drivers/misc/rk3562-secure-otp.c" 1
2734
+ dmb sy
2735
+// 0 "" 2
2736
+#NO_APP
2737
+ ldr x0, [x28]
2738
+ str wzr, [x0, 4120]
2739
+.LVL301:
2740
+.LBE257:
2741
+.LBB258:
2742
+ .loc 1 507 0
2743
+#APP
2744
+// 507 "drivers/misc/rk3562-secure-otp.c" 1
2745
+ dmb sy
2746
+// 0 "" 2
2747
+#NO_APP
2748
+ ldr x0, [x28]
2749
+ mov w1, 31
2750
+ str w1, [x0, 4124]
2751
+.LVL302:
2752
+.LBE258:
2753
+.LBB259:
2754
+ .loc 1 508 0
2755
+#APP
2756
+// 508 "drivers/misc/rk3562-secure-otp.c" 1
2757
+ dmb sy
2758
+// 0 "" 2
2759
+#NO_APP
2760
+ ldr x0, [x28]
2761
+ mov w1, 11
2762
+ str w1, [x0, 4128]
2763
+.LVL303:
2764
+.LBE259:
2765
+.LBB260:
2766
+ .loc 1 509 0
2767
+#APP
2768
+// 509 "drivers/misc/rk3562-secure-otp.c" 1
2769
+ dmb sy
2770
+// 0 "" 2
2771
+#NO_APP
2772
+ ldr x0, [x28]
2773
+ mov w1, 8
2774
+ str w1, [x0, 4132]
2775
+.LVL304:
2776
+.LBE260:
2777
+.LBB261:
2778
+ .loc 1 510 0
2779
+#APP
2780
+// 510 "drivers/misc/rk3562-secure-otp.c" 1
2781
+ dmb sy
2782
+// 0 "" 2
2783
+#NO_APP
2784
+ ldr x0, [x28]
2785
+ str wzr, [x0, 4136]
2786
+.LVL305:
2787
+.LBE261:
2788
+.LBB262:
2789
+ .loc 1 511 0
2790
+#APP
2791
+// 511 "drivers/misc/rk3562-secure-otp.c" 1
2792
+ dmb sy
2793
+// 0 "" 2
2794
+#NO_APP
2795
+ ldr x0, [x28]
2796
+ str wzr, [x0, 4140]
2797
+.LVL306:
2798
+.LBE262:
2799
+.LBB263:
2800
+ .loc 1 512 0
2801
+#APP
2802
+// 512 "drivers/misc/rk3562-secure-otp.c" 1
2803
+ dmb sy
2804
+// 0 "" 2
2805
+#NO_APP
2806
+ ldr x0, [x28]
2807
+ str wzr, [x0, 4144]
2808
+.LVL307:
2809
+.LBE263:
2810
+.LBB264:
2811
+ .loc 1 513 0
2812
+#APP
2813
+// 513 "drivers/misc/rk3562-secure-otp.c" 1
2814
+ dmb sy
2815
+// 0 "" 2
2816
+#NO_APP
2817
+ ldr x0, [x28]
2818
+.LBE264:
2819
+.LBB265:
2820
+ .loc 1 514 0
2821
+ ubfx x21, x21, 9, 8
2822
+.LVL308:
2823
+.LBE265:
2824
+.LBB266:
2825
+ .loc 1 513 0
2826
+ str w25, [x0, 4148]
2827
+.LBE266:
2828
+.LBB267:
2829
+ .loc 1 514 0
2830
+#APP
2831
+// 514 "drivers/misc/rk3562-secure-otp.c" 1
2832
+ dmb sy
2833
+// 0 "" 2
2834
+#NO_APP
2835
+ ldr x0, [x28]
2836
+ str w21, [x0, 4152]
2837
+.LVL309:
2838
+.LBE267:
2839
+.LBB268:
2840
+ .loc 1 515 0
2841
+#APP
2842
+// 515 "drivers/misc/rk3562-secure-otp.c" 1
2843
+ dmb sy
2844
+// 0 "" 2
2845
+#NO_APP
2846
+ ldr x0, [x28]
2847
+ mov w22, 65537
2848
+.LBE268:
2849
+ .loc 1 516 0
2850
+ mov w1, 2
2851
+.LBB269:
2852
+ .loc 1 515 0
2853
+ str w22, [x0, 32]
2854
+.LBE269:
2855
+ .loc 1 516 0
2856
+ mov x0, x28
2857
+ bl rockchip_secure_otp_wait_status.isra.2
2858
+.LVL310:
2859
+ mov w27, w0
2860
+.LVL311:
2861
+ .loc 1 517 0
2862
+ ldp w3, w2, [x29, 100]
2863
+ tbz w0, #31, .L87
2864
+ .loc 1 518 0
2865
+ adrp x0, .LC5
2866
+.LVL312:
2867
+ mov x1, x19
2868
+ add x0, x0, :lo12:.LC5
2869
+.LVL313:
2870
+.L113:
2871
+ .loc 1 607 0
2872
+ bl printf
2873
+.LVL314:
2874
+.L88:
2875
+.LBB270:
2876
+ .loc 1 612 0
2877
+#APP
2878
+// 612 "drivers/misc/rk3562-secure-otp.c" 1
2879
+ dmb sy
2880
+// 0 "" 2
2881
+#NO_APP
2882
+ ldr x0, [x28]
2883
+ mov w1, -65533
2884
+.LBE270:
2885
+ .loc 1 613 0
2886
+ ldr x2, [x28, 16]
2887
+ mov w3, w25
2888
+.LBB271:
2889
+ .loc 1 612 0
2890
+ str w1, [x0, 772]
2891
+.LBE271:
2892
+ .loc 1 613 0
2893
+ ldr x0, [x29, 120]
2894
+ ldr x1, [x28, 24]
2895
+ ldr x6, [x0, 24]
2896
+ ldr x0, [x28, 8]
2897
+ blr x6
2898
+.LVL315:
2899
+.LBE322:
2900
+.LBE335:
2901
+ .loc 1 661 0
2902
+ cbz w27, .L86
2903
+.LVL316:
2904
+.L84:
2905
+ .loc 1 662 0
2906
+ adrp x0, .LC20
2907
+ add x0, x0, :lo12:.LC20
2908
+ b .L114
2909
+.LVL317:
2910
+.L87:
2911
+.LBB336:
2912
+.LBB323:
2913
+.LBB272:
2914
+ .loc 1 522 0
2915
+#APP
2916
+// 522 "drivers/misc/rk3562-secure-otp.c" 1
2917
+ dmb sy
2918
+// 0 "" 2
2919
+#NO_APP
2920
+ ldr x0, [x28]
2921
+.LVL318:
2922
+ mov w1, 14848
2923
+ movk w1, 0xff00, lsl 16
2924
+ str w1, [x0, 32]
2925
+.LVL319:
2926
+.LBE272:
2927
+.LBB273:
2928
+ .loc 1 523 0
2929
+#APP
2930
+// 523 "drivers/misc/rk3562-secure-otp.c" 1
2931
+ dmb sy
2932
+// 0 "" 2
2933
+#NO_APP
2934
+ ldr x0, [x28]
2935
+ str w3, [x0, 4096]
2936
+.LVL320:
2937
+.LBE273:
2938
+.LBB274:
2939
+ .loc 1 524 0
2940
+#APP
2941
+// 524 "drivers/misc/rk3562-secure-otp.c" 1
2942
+ dmb sy
2943
+// 0 "" 2
2944
+#NO_APP
2945
+ ldr x0, [x28]
2946
+ mov w1, 1
2947
+ str w1, [x0, 4100]
2948
+.LVL321:
2949
+.LBE274:
2950
+.LBB275:
2951
+ .loc 1 525 0
2952
+#APP
2953
+// 525 "drivers/misc/rk3562-secure-otp.c" 1
2954
+ dmb sy
2955
+// 0 "" 2
2956
+#NO_APP
2957
+ ldr x0, [x28]
2958
+ str w2, [x0, 4104]
2959
+.LVL322:
2960
+.LBE275:
2961
+.LBB276:
2962
+ .loc 1 526 0
2963
+#APP
2964
+// 526 "drivers/misc/rk3562-secure-otp.c" 1
2965
+ dmb sy
2966
+// 0 "" 2
2967
+#NO_APP
2968
+ ldr x0, [x28]
2969
+ mov w1, 21
2970
+ str w1, [x0, 4108]
2971
+.LVL323:
2972
+.LBE276:
2973
+.LBB277:
2974
+ .loc 1 527 0
2975
+#APP
2976
+// 527 "drivers/misc/rk3562-secure-otp.c" 1
2977
+ dmb sy
2978
+// 0 "" 2
2979
+#NO_APP
2980
+ ldr x0, [x28]
2981
+ mov w1, 220
2982
+ str w1, [x0, 4112]
2983
+.LVL324:
2984
+.LBE277:
2985
+.LBB278:
2986
+ .loc 1 528 0
2987
+#APP
2988
+// 528 "drivers/misc/rk3562-secure-otp.c" 1
2989
+ dmb sy
2990
+// 0 "" 2
2991
+#NO_APP
2992
+ ldr x0, [x28]
2993
+ mov w1, 146
2994
+ str w1, [x0, 4116]
2995
+.LVL325:
2996
+.LBE278:
2997
+.LBB279:
2998
+ .loc 1 529 0
2999
+#APP
3000
+// 529 "drivers/misc/rk3562-secure-otp.c" 1
3001
+ dmb sy
3002
+// 0 "" 2
3003
+#NO_APP
3004
+ ldr x0, [x28]
3005
+ mov w1, 121
3006
+ str w1, [x0, 4120]
3007
+.LVL326:
3008
+.LBE279:
3009
+.LBB280:
3010
+ .loc 1 530 0
3011
+#APP
3012
+// 530 "drivers/misc/rk3562-secure-otp.c" 1
3013
+ dmb sy
3014
+// 0 "" 2
3015
+#NO_APP
3016
+ ldr x0, [x28]
3017
+ mov w1, 129
3018
+ str w1, [x0, 4124]
3019
+.LVL327:
3020
+.LBE280:
3021
+.LBB281:
3022
+ .loc 1 531 0
3023
+#APP
3024
+// 531 "drivers/misc/rk3562-secure-otp.c" 1
3025
+ dmb sy
3026
+// 0 "" 2
3027
+#NO_APP
3028
+ ldr x0, [x28]
3029
+ mov w1, 126
3030
+ str w1, [x0, 4128]
3031
+.LVL328:
3032
+.LBE281:
3033
+.LBB282:
3034
+ .loc 1 532 0
3035
+#APP
3036
+// 532 "drivers/misc/rk3562-secure-otp.c" 1
3037
+ dmb sy
3038
+// 0 "" 2
3039
+#NO_APP
3040
+ ldr x0, [x28]
3041
+ mov w1, 33
3042
+ str w1, [x0, 4132]
3043
+.LVL329:
3044
+.LBE282:
3045
+.LBB283:
3046
+ .loc 1 533 0
3047
+#APP
3048
+// 533 "drivers/misc/rk3562-secure-otp.c" 1
3049
+ dmb sy
3050
+// 0 "" 2
3051
+#NO_APP
3052
+ ldr x0, [x28]
3053
+ mov w1, 17
3054
+ str w1, [x0, 4136]
3055
+.LVL330:
3056
+.LBE283:
3057
+.LBB284:
3058
+ .loc 1 534 0
3059
+#APP
3060
+// 534 "drivers/misc/rk3562-secure-otp.c" 1
3061
+ dmb sy
3062
+// 0 "" 2
3063
+#NO_APP
3064
+ ldr x0, [x28]
3065
+ mov w1, 157
3066
+ str w1, [x0, 4140]
3067
+.LVL331:
3068
+.LBE284:
3069
+.LBB285:
3070
+ .loc 1 535 0
3071
+#APP
3072
+// 535 "drivers/misc/rk3562-secure-otp.c" 1
3073
+ dmb sy
3074
+// 0 "" 2
3075
+#NO_APP
3076
+ ldr x0, [x28]
3077
+ mov w21, 2
3078
+.LVL332:
3079
+ str w21, [x0, 4144]
3080
+.LVL333:
3081
+.LBE285:
3082
+.LBB286:
3083
+ .loc 1 536 0
3084
+#APP
3085
+// 536 "drivers/misc/rk3562-secure-otp.c" 1
3086
+ dmb sy
3087
+// 0 "" 2
3088
+#NO_APP
3089
+ ldr x0, [x28]
3090
+ str wzr, [x0, 4148]
3091
+.LVL334:
3092
+.LBE286:
3093
+.LBB287:
3094
+ .loc 1 537 0
3095
+#APP
3096
+// 537 "drivers/misc/rk3562-secure-otp.c" 1
3097
+ dmb sy
3098
+// 0 "" 2
3099
+#NO_APP
3100
+ ldr x0, [x28]
3101
+ str wzr, [x0, 4152]
3102
+.LVL335:
3103
+.LBE287:
3104
+.LBB288:
3105
+ .loc 1 538 0
3106
+#APP
3107
+// 538 "drivers/misc/rk3562-secure-otp.c" 1
3108
+ dmb sy
3109
+// 0 "" 2
3110
+#NO_APP
3111
+ ldr x0, [x28]
3112
+.LBE288:
3113
+ .loc 1 539 0
3114
+ mov w1, w21
3115
+.LBB289:
3116
+ .loc 1 538 0
3117
+ str w22, [x0, 32]
3118
+.LBE289:
3119
+ .loc 1 539 0
3120
+ mov x0, x28
3121
+ bl rockchip_secure_otp_wait_status.isra.2
3122
+.LVL336:
3123
+ mov w27, w0
3124
+.LVL337:
3125
+ .loc 1 540 0
3126
+ tbz w0, #31, .L89
3127
+ .loc 1 541 0
3128
+ adrp x0, .LC14
3129
+.LVL338:
3130
+ mov x1, x19
3131
+ add x0, x0, :lo12:.LC14
3132
+ b .L113
3133
+.LVL339:
3134
+.L89:
3135
+.LBB290:
3136
+ .loc 1 545 0
3137
+#APP
3138
+// 545 "drivers/misc/rk3562-secure-otp.c" 1
3139
+ dmb sy
3140
+// 0 "" 2
3141
+#NO_APP
3142
+ ldr x0, [x28]
3143
+.LVL340:
3144
+ mov w1, 512
3145
+ movk w1, 0xff00, lsl 16
3146
+ str w1, [x0, 32]
3147
+.LVL341:
3148
+.LBE290:
3149
+.LBB291:
3150
+ .loc 1 546 0
3151
+#APP
3152
+// 546 "drivers/misc/rk3562-secure-otp.c" 1
3153
+ dmb sy
3154
+// 0 "" 2
3155
+#NO_APP
3156
+ ldr x0, [x28]
3157
+ mov w1, -65535
3158
+ str w1, [x0, 36]
3159
+.LVL342:
3160
+.LBE291:
3161
+.LBB292:
3162
+ .loc 1 547 0
3163
+#APP
3164
+// 547 "drivers/misc/rk3562-secure-otp.c" 1
3165
+ dmb sy
3166
+// 0 "" 2
3167
+#NO_APP
3168
+ ldr x0, [x28]
3169
+ mov w1, 251
3170
+ str w1, [x0, 4096]
3171
+.LVL343:
3172
+.LBE292:
3173
+.LBB293:
3174
+ .loc 1 548 0
3175
+#APP
3176
+// 548 "drivers/misc/rk3562-secure-otp.c" 1
3177
+ dmb sy
3178
+// 0 "" 2
3179
+#NO_APP
3180
+ ldr x0, [x28]
3181
+ str wzr, [x0, 4100]
3182
+.LVL344:
3183
+.LBE293:
3184
+.LBB294:
3185
+ .loc 1 549 0
3186
+#APP
3187
+// 549 "drivers/misc/rk3562-secure-otp.c" 1
3188
+ dmb sy
3189
+// 0 "" 2
3190
+#NO_APP
3191
+ ldr x0, [x28]
3192
+.LBE294:
3193
+ .loc 1 550 0
3194
+ mov w1, w21
3195
+.LBB295:
3196
+ .loc 1 549 0
3197
+ str w22, [x0, 32]
3198
+.LBE295:
3199
+ .loc 1 550 0
3200
+ mov x0, x28
3201
+ bl rockchip_secure_otp_wait_status.isra.2
3202
+.LVL345:
3203
+ mov w27, w0
3204
+.LVL346:
3205
+ .loc 1 551 0
3206
+ tbz w0, #31, .L90
3207
+ .loc 1 552 0
3208
+ adrp x0, .LC15
3209
+.LVL347:
3210
+ mov x1, x19
3211
+ add x0, x0, :lo12:.LC15
3212
+ b .L113
3213
+.LVL348:
3214
+.L90:
3215
+.LBB296:
3216
+ .loc 1 556 0
3217
+#APP
3218
+// 556 "drivers/misc/rk3562-secure-otp.c" 1
3219
+ dmb sy
3220
+// 0 "" 2
3221
+#NO_APP
3222
+ ldr x0, [x28]
3223
+.LVL349:
3224
+ mov w1, -65534
3225
+ str w1, [x0, 36]
3226
+.LVL350:
3227
+.LBE296:
3228
+.LBB297:
3229
+ .loc 1 557 0
3230
+#APP
3231
+// 557 "drivers/misc/rk3562-secure-otp.c" 1
3232
+ dmb sy
3233
+// 0 "" 2
3234
+#NO_APP
3235
+ ldr x0, [x28]
3236
+ mov w1, 192
3237
+ str w1, [x0, 4096]
3238
+.LBE297:
3239
+.LBB298:
3240
+ .loc 1 558 0
3241
+ and w1, w26, 255
3242
+.LVL351:
3243
+#APP
3244
+// 558 "drivers/misc/rk3562-secure-otp.c" 1
3245
+ dmb sy
3246
+// 0 "" 2
3247
+#NO_APP
3248
+ ldr x0, [x28]
3249
+.LBE298:
3250
+.LBB299:
3251
+ .loc 1 559 0
3252
+ lsr w26, w26, 8
3253
+.LVL352:
3254
+.LBE299:
3255
+.LBB300:
3256
+ .loc 1 558 0
3257
+ str w1, [x0, 4100]
3258
+.LBE300:
3259
+.LBB301:
3260
+ .loc 1 559 0
3261
+#APP
3262
+// 559 "drivers/misc/rk3562-secure-otp.c" 1
3263
+ dmb sy
3264
+// 0 "" 2
3265
+#NO_APP
3266
+ ldr x0, [x28]
3267
+ str w26, [x0, 4104]
3268
+.LVL353:
3269
+.LBE301:
3270
+.LBB302:
3271
+ .loc 1 560 0
3272
+#APP
3273
+// 560 "drivers/misc/rk3562-secure-otp.c" 1
3274
+ dmb sy
3275
+// 0 "" 2
3276
+#NO_APP
3277
+ ldr x0, [x28]
3278
+.LBE302:
3279
+ .loc 1 561 0
3280
+ mov w1, w21
3281
+.LVL354:
3282
+.LBB303:
3283
+ .loc 1 560 0
3284
+ str w22, [x0, 32]
3285
+.LBE303:
3286
+ .loc 1 561 0
3287
+ mov x0, x28
3288
+ bl rockchip_secure_otp_wait_status.isra.2
3289
+.LVL355:
3290
+ mov w27, w0
3291
+.LVL356:
3292
+ .loc 1 562 0
3293
+ tbz w0, #31, .L91
3294
+ .loc 1 563 0
3295
+ adrp x0, .LC16
3296
+.LVL357:
3297
+ mov x1, x19
3298
+ add x0, x0, :lo12:.LC16
3299
+ b .L113
3300
+.LVL358:
3301
+.L91:
3302
+.LBB304:
3303
+ .loc 1 567 0
3304
+#APP
3305
+// 567 "drivers/misc/rk3562-secure-otp.c" 1
3306
+ dmb sy
3307
+// 0 "" 2
3308
+#NO_APP
3309
+ ldr x0, [x28]
3310
+.LVL359:
3311
+ mov w1, 14848
3312
+ movk w1, 0xff00, lsl 16
3313
+ str w1, [x0, 32]
3314
+.LVL360:
3315
+.LBE304:
3316
+.LBB305:
3317
+ .loc 1 568 0
3318
+#APP
3319
+// 568 "drivers/misc/rk3562-secure-otp.c" 1
3320
+ dmb sy
3321
+// 0 "" 2
3322
+#NO_APP
3323
+ ldr x0, [x28]
3324
+ mov w1, -65535
3325
+ str w1, [x0, 36]
3326
+.LVL361:
3327
+.LBE305:
3328
+.LBB306:
3329
+ .loc 1 569 0
3330
+#APP
3331
+// 569 "drivers/misc/rk3562-secure-otp.c" 1
3332
+ dmb sy
3333
+// 0 "" 2
3334
+#NO_APP
3335
+ ldr x0, [x28]
3336
+ mov w1, 255
3337
+ str w1, [x0, 4096]
3338
+.LVL362:
3339
+.LBE306:
3340
+.LBB307:
3341
+ .loc 1 570 0
3342
+#APP
3343
+// 570 "drivers/misc/rk3562-secure-otp.c" 1
3344
+ dmb sy
3345
+// 0 "" 2
3346
+#NO_APP
3347
+ ldr x0, [x28]
3348
+ mov w1, 10
3349
+ str w1, [x0, 4100]
3350
+.LVL363:
3351
+.LBE307:
3352
+.LBB308:
3353
+ .loc 1 571 0
3354
+#APP
3355
+// 571 "drivers/misc/rk3562-secure-otp.c" 1
3356
+ dmb sy
3357
+// 0 "" 2
3358
+#NO_APP
3359
+ ldr x0, [x28]
3360
+.LBE308:
3361
+ .loc 1 572 0
3362
+ mov w1, w21
3363
+.LBB309:
3364
+ .loc 1 571 0
3365
+ str w22, [x0, 32]
3366
+.LBE309:
3367
+ .loc 1 572 0
3368
+ mov x0, x28
3369
+ bl rockchip_secure_otp_wait_status.isra.2
3370
+.LVL364:
3371
+ mov w27, w0
3372
+.LVL365:
3373
+ .loc 1 573 0
3374
+ tbz w0, #31, .L92
3375
+ .loc 1 574 0
3376
+ adrp x0, .LC17
3377
+.LVL366:
3378
+ mov x1, x19
3379
+ add x0, x0, :lo12:.LC17
3380
+ b .L113
3381
+.LVL367:
3382
+.L92:
3383
+.LBB310:
3384
+ .loc 1 578 0
3385
+#APP
3386
+// 578 "drivers/misc/rk3562-secure-otp.c" 1
3387
+ dmb sy
3388
+// 0 "" 2
3389
+#NO_APP
3390
+ ldr x0, [x28]
3391
+.LVL368:
3392
+ mov w1, -65534
3393
+ str w1, [x0, 36]
3394
+.LVL369:
3395
+.LBE310:
3396
+.LBB311:
3397
+ .loc 1 579 0
3398
+#APP
3399
+// 579 "drivers/misc/rk3562-secure-otp.c" 1
3400
+ dmb sy
3401
+// 0 "" 2
3402
+#NO_APP
3403
+ ldr x0, [x28]
3404
+ mov w1, 1
3405
+ str w1, [x0, 4096]
3406
+.LVL370:
3407
+.LBE311:
3408
+.LBB312:
3409
+ .loc 1 580 0
3410
+#APP
3411
+// 580 "drivers/misc/rk3562-secure-otp.c" 1
3412
+ dmb sy
3413
+// 0 "" 2
3414
+#NO_APP
3415
+ ldr x0, [x28]
3416
+ mov w1, 191
3417
+ str w1, [x0, 4100]
3418
+.LVL371:
3419
+.LBE312:
3420
+.LBB313:
3421
+ .loc 1 581 0
3422
+#APP
3423
+// 581 "drivers/misc/rk3562-secure-otp.c" 1
3424
+ dmb sy
3425
+// 0 "" 2
3426
+#NO_APP
3427
+ ldr x0, [x28]
3428
+ str wzr, [x0, 4104]
3429
+.LVL372:
3430
+.LBE313:
3431
+.LBB314:
3432
+ .loc 1 582 0
3433
+#APP
3434
+// 582 "drivers/misc/rk3562-secure-otp.c" 1
3435
+ dmb sy
3436
+// 0 "" 2
3437
+#NO_APP
3438
+ ldr x0, [x28]
3439
+.LBE314:
3440
+ .loc 1 583 0
3441
+ mov w1, w21
3442
+.LBB315:
3443
+ .loc 1 582 0
3444
+ str w22, [x0, 32]
3445
+.LBE315:
3446
+ .loc 1 583 0
3447
+ mov x0, x28
3448
+ bl rockchip_secure_otp_wait_status.isra.2
3449
+.LVL373:
3450
+ mov w27, w0
3451
+.LVL374:
3452
+ .loc 1 584 0
3453
+ tbz w0, #31, .L93
3454
+ .loc 1 585 0
3455
+ adrp x0, .LC18
3456
+.LVL375:
3457
+ mov x1, x19
3458
+ add x0, x0, :lo12:.LC18
3459
+ b .L113
3460
+.LVL376:
3461
+.L93:
3462
+ .loc 1 589 0
3463
+ mov x0, x28
3464
+.LVL377:
3465
+ bl rockchip_secure_otp_check_flag.isra.0
3466
+.LVL378:
3467
+ mov w27, w0
3468
+.LVL379:
3469
+ .loc 1 590 0
3470
+ tbz w0, #31, .L94
3471
+ .loc 1 591 0
3472
+ adrp x0, .LC6
3473
+.LVL380:
3474
+ mov x1, x19
3475
+ add x0, x0, :lo12:.LC6
3476
+ b .L113
3477
+.LVL381:
3478
+.L94:
3479
+.LBB316:
3480
+ .loc 1 595 0
3481
+#APP
3482
+// 595 "drivers/misc/rk3562-secure-otp.c" 1
3483
+ dmb sy
3484
+// 0 "" 2
3485
+#NO_APP
3486
+ ldr x0, [x28]
3487
+.LVL382:
3488
+ mov w1, -65535
3489
+ str w1, [x0, 36]
3490
+.LVL383:
3491
+.LBE316:
3492
+.LBB317:
3493
+ .loc 1 596 0
3494
+#APP
3495
+// 596 "drivers/misc/rk3562-secure-otp.c" 1
3496
+ dmb sy
3497
+// 0 "" 2
3498
+#NO_APP
3499
+ ldr x0, [x28]
3500
+ mov w1, 2
3501
+ str w1, [x0, 4096]
3502
+.LVL384:
3503
+.LBE317:
3504
+.LBB318:
3505
+ .loc 1 597 0
3506
+#APP
3507
+// 597 "drivers/misc/rk3562-secure-otp.c" 1
3508
+ dmb sy
3509
+// 0 "" 2
3510
+#NO_APP
3511
+ ldr x0, [x28]
3512
+ mov w2, 191
3513
+ str w2, [x0, 4100]
3514
+.LVL385:
3515
+.LBE318:
3516
+.LBB319:
3517
+ .loc 1 598 0
3518
+#APP
3519
+// 598 "drivers/misc/rk3562-secure-otp.c" 1
3520
+ dmb sy
3521
+// 0 "" 2
3522
+#NO_APP
3523
+ ldr x0, [x28]
3524
+ mov w2, 65537
3525
+ str w2, [x0, 32]
3526
+.LBE319:
3527
+ .loc 1 599 0
3528
+ mov x0, x28
3529
+ bl rockchip_secure_otp_wait_status.isra.2
3530
+.LVL386:
3531
+ mov w27, w0
3532
+.LVL387:
3533
+ .loc 1 600 0
3534
+ tbz w0, #31, .L95
3535
+ .loc 1 601 0
3536
+ adrp x0, .LC19
3537
+.LVL388:
3538
+ mov x1, x19
3539
+ add x0, x0, :lo12:.LC19
3540
+ b .L113
3541
+.LVL389:
3542
+.L95:
3543
+ .loc 1 605 0
3544
+ mov x0, x28
3545
+.LVL390:
3546
+ bl rockchip_secure_otp_wait_flag.isra.1
3547
+.LVL391:
3548
+ mov w27, w0
3549
+.LVL392:
3550
+ .loc 1 606 0
3551
+ tbz w0, #31, .L88
3552
+ .loc 1 607 0
3553
+ adrp x0, .LC7
3554
+.LVL393:
3555
+ mov x1, x19
3556
+ add x0, x0, :lo12:.LC7
3557
+ b .L113
3558
+.LVL394:
3559
+.L86:
3560
+ add x23, x23, 1
3561
+.LVL395:
3562
+ b .L78
3563
+.LVL396:
3564
+.L79:
3565
+.LBE323:
3566
+.LBE336:
3567
+.LBB337:
3568
+.LBB331:
3569
+ .loc 1 457 0
3570
+ mov w27, -1
3571
+ b .L98
3572
+.LBE331:
3573
+.LBE337:
3574
+ .cfi_endproc
3575
+.LFE272:
3576
+ .size rk3562_secure_otp_write, .-rk3562_secure_otp_write
3577
+ .global _u_boot_list_2_driver_2_rockchip_secure_otp
3578
+ .section .rodata.__func__.7582,"a",@progbits
3579
+ .align 3
3580
+ .set .LANCHOR0,. + 0
3581
+ .type __func__.7582, %object
3582
+ .size __func__.7582, 32
3583
+__func__.7582:
3584
+ .string "rockchip_secure_otp_wait_status"
3585
+ .section .rodata.__func__.7625,"a",@progbits
3586
+ .align 3
3587
+ .set .LANCHOR2,. + 0
3588
+ .type __func__.7625, %object
3589
+ .size __func__.7625, 31
3590
+__func__.7625:
3591
+ .string "rockchip_secure_otp_ecc_enable"
3592
+ .section .rodata.__func__.7643,"a",@progbits
3593
+ .align 3
3594
+ .set .LANCHOR3,. + 0
3595
+ .type __func__.7643, %object
3596
+ .size __func__.7643, 23
3597
+__func__.7643:
3598
+ .string "rk3562_secure_otp_read"
3599
+ .section .rodata.__func__.7678,"a",@progbits
3600
+ .align 3
3601
+ .set .LANCHOR1,. + 0
3602
+ .type __func__.7678, %object
3603
+ .size __func__.7678, 38
3604
+__func__.7678:
3605
+ .string "rk3562_secure_otp_write_2_bytes_noecc"
3606
+ .section .rodata.__func__.7899,"a",@progbits
3607
+ .align 3
3608
+ .set .LANCHOR4,. + 0
3609
+ .type __func__.7899, %object
3610
+ .size __func__.7899, 32
3611
+__func__.7899:
3612
+ .string "rk3562_secure_otp_write_2_bytes"
3613
+ .section .rodata.rk3562_data,"a",@progbits
3614
+ .align 3
3615
+ .type rk3562_data, %object
3616
+ .size rk3562_data, 32
3617
+rk3562_data:
3618
+ .xword rk3562_secure_otp_read
3619
+ .xword rk3562_secure_otp_write
3620
+ .xword rk3562_spl_rockchip_otp_start
3621
+ .xword rk3562_spl_rockchip_otp_stop
3622
+ .section .rodata.rk3562_secure_otp_read.str1.1,"aMS",@progbits,1
3623
+.LC9:
3624
+ .string "do not access non secure area, half word offset = %d\n"
3625
+.LC10:
3626
+ .string "Please input correct addr, offset(bytes) is 0x%x\n"
3627
+.LC11:
3628
+ .string "%s timeout during read setup\n"
3629
+ .section .rodata.rk3562_secure_otp_write.str1.1,"aMS",@progbits,1
3630
+.LC12:
3631
+ .string "The zone is written.\n"
3632
+.LC13:
3633
+ .string "rk3562_secure_otp_write_byte_noecc error\n"
3634
+.LC14:
3635
+ .string "%s timeout during write setup 2\n"
3636
+.LC15:
3637
+ .string "%s timeout during write setup 3\n"
3638
+.LC16:
3639
+ .string "%s timeout during write setup 4\n"
3640
+.LC17:
3641
+ .string "%s timeout during write setup 5\n"
3642
+.LC18:
3643
+ .string "%s timeout during write setup 6\n"
3644
+.LC19:
3645
+ .string "%s timeout during write setup 8\n"
3646
+.LC20:
3647
+ .string "rk3562_secure_otp_write_2_bytes error\n"
3648
+ .section .rodata.rk3562_secure_otp_write_2_bytes_noecc.str1.1,"aMS",@progbits,1
3649
+.LC4:
3650
+ .string "Please input correct addr, offset is 0x%x\n"
3651
+.LC5:
3652
+ .string "%s timeout during write setup 1\n"
3653
+.LC6:
3654
+ .string "%s timeout during write setup 7\n"
3655
+.LC7:
3656
+ .string "%s timeout during write setup 9\n"
3657
+ .section .rodata.rockchip_otp_ids,"a",@progbits
3658
+ .align 3
3659
+ .type rockchip_otp_ids, %object
3660
+ .size rockchip_otp_ids, 32
3661
+rockchip_otp_ids:
3662
+ .xword .LC22
3663
+ .xword rk3562_data
3664
+ .zero 16
3665
+ .section .rodata.rockchip_secure_otp_ecc_enable.str1.1,"aMS",@progbits,1
3666
+.LC8:
3667
+ .string "%s timeout during ecc_enable\n"
3668
+ .section .rodata.rockchip_secure_otp_ofdata_to_platdata.str1.1,"aMS",@progbits,1
3669
+.LC0:
3670
+ .string "secure_conf"
3671
+.LC1:
3672
+ .string "mask_addr"
3673
+.LC2:
3674
+ .string "cru_rst_addr"
3675
+ .section .rodata.rockchip_secure_otp_ops,"a",@progbits
3676
+ .align 3
3677
+ .type rockchip_secure_otp_ops, %object
3678
+ .size rockchip_secure_otp_ops, 32
3679
+rockchip_secure_otp_ops:
3680
+ .xword secure_otp_read
3681
+ .xword secure_otp_write
3682
+ .xword secure_otp_ioctl
3683
+ .zero 8
3684
+ .section .rodata.rockchip_secure_otp_wait_status.isra.2.str1.1,"aMS",@progbits,1
3685
+.LC3:
3686
+ .string "%s: wait init status timeout\n"
3687
+ .section .rodata.str1.1,"aMS",@progbits,1
3688
+.LC21:
3689
+ .string "rockchip_secure_otp"
3690
+.LC22:
3691
+ .string "rockchip,rk3562-secure-otp"
3692
+ .section .u_boot_list_2_driver_2_rockchip_secure_otp,"aw",@progbits
3693
+ .align 2
3694
+ .type _u_boot_list_2_driver_2_rockchip_secure_otp, %object
3695
+ .size _u_boot_list_2_driver_2_rockchip_secure_otp, 120
3696
+_u_boot_list_2_driver_2_rockchip_secure_otp:
3697
+ .8byte .LC21
3698
+ .word 36
3699
+ .zero 4
3700
+ .8byte rockchip_otp_ids
3701
+ .zero 32
3702
+ .8byte rockchip_secure_otp_ofdata_to_platdata
3703
+ .zero 28
3704
+ .word 32
3705
+ .zero 8
3706
+ .8byte rockchip_secure_otp_ops
3707
+ .zero 8
3708
+ .text
3709
+.Letext0:
3710
+ .file 2 "include/common.h"
3711
+ .file 3 "./arch/arm/include/asm/types.h"
3712
+ .file 4 "include/linux/types.h"
3713
+ .file 5 "include/errno.h"
3714
+ .file 6 "include/linux/string.h"
3715
+ .file 7 "include/efi.h"
3716
+ .file 8 "include/dm/device.h"
3717
+ .file 9 "include/ide.h"
3718
+ .file 10 "include/linux/list.h"
3719
+ .file 11 "include/part.h"
3720
+ .file 12 "include/flash.h"
3721
+ .file 13 "include/lmb.h"
3722
+ .file 14 "include/asm-generic/u-boot.h"
3723
+ .file 15 "./arch/arm/include/asm/u-boot-arm.h"
3724
+ .file 16 "include/linux/libfdt_env.h"
3725
+ .file 17 "include/linux/../../scripts/dtc/libfdt/fdt.h"
3726
+ .file 18 "include/linux/libfdt.h"
3727
+ .file 19 "include/image.h"
3728
+ .file 20 "./arch/arm/include/asm/global_data.h"
3729
+ .file 21 "include/asm-generic/global_data.h"
3730
+ .file 22 "include/dm/of.h"
3731
+ .file 23 "include/net.h"
3732
+ .file 24 "include/dm/uclass-id.h"
3733
+ .file 25 "include/dm/ofnode.h"
3734
+ .file 26 "include/malloc.h"
3735
+ .file 27 "include/linux/compat.h"
3736
+ .file 28 "include/dm/uclass.h"
3737
+ .file 29 "include/asm-generic/ioctl.h"
3738
+ .file 30 "include/misc.h"
3739
+ .file 31 "include/rockchip-otp.h"
3740
+ .file 32 "include/dm/read.h"
3741
+ .file 33 "include/stdio.h"
3742
+ .file 34 "include/linux/delay.h"
3743
+ .file 35 "include/log.h"
3744
+ .section .debug_info,"",@progbits
3745
+.Ldebug_info0:
3746
+ .4byte 0x42d6
3747
+ .2byte 0x4
3748
+ .4byte .Ldebug_abbrev0
3749
+ .byte 0x8
3750
+ .uleb128 0x1
3751
+ .4byte .LASF459
3752
+ .byte 0xc
3753
+ .4byte .LASF460
3754
+ .4byte .LASF461
3755
+ .4byte .Ldebug_ranges0+0x6c0
3756
+ .8byte 0
3757
+ .4byte .Ldebug_line0
3758
+ .uleb128 0x2
3759
+ .4byte .LASF4
3760
+ .byte 0x2
3761
+ .byte 0xd
3762
+ .4byte 0x34
3763
+ .uleb128 0x3
3764
+ .byte 0x1
3765
+ .byte 0x8
3766
+ .4byte .LASF0
3767
+ .uleb128 0x3
3768
+ .byte 0x8
3769
+ .byte 0x7
3770
+ .4byte .LASF1
3771
+ .uleb128 0x3
3772
+ .byte 0x2
3773
+ .byte 0x7
3774
+ .4byte .LASF2
3775
+ .uleb128 0x4
3776
+ .4byte .LASF21
3777
+ .byte 0x5
3778
+ .byte 0xc
3779
+ .4byte 0x54
3780
+ .uleb128 0x5
3781
+ .byte 0x4
3782
+ .byte 0x5
3783
+ .string "int"
3784
+ .uleb128 0x3
3785
+ .byte 0x1
3786
+ .byte 0x6
3787
+ .4byte .LASF3
3788
+ .uleb128 0x2
3789
+ .4byte .LASF5
3790
+ .byte 0x3
3791
+ .byte 0xc
3792
+ .4byte 0x34
3793
+ .uleb128 0x3
3794
+ .byte 0x2
3795
+ .byte 0x5
3796
+ .4byte .LASF6
3797
+ .uleb128 0x2
3798
+ .4byte .LASF7
3799
+ .byte 0x3
3800
+ .byte 0x12
3801
+ .4byte 0x7f
3802
+ .uleb128 0x3
3803
+ .byte 0x4
3804
+ .byte 0x7
3805
+ .4byte .LASF8
3806
+ .uleb128 0x3
3807
+ .byte 0x8
3808
+ .byte 0x5
3809
+ .4byte .LASF9
3810
+ .uleb128 0x3
3811
+ .byte 0x8
3812
+ .byte 0x7
3813
+ .4byte .LASF10
3814
+ .uleb128 0x6
3815
+ .string "u8"
3816
+ .byte 0x3
3817
+ .byte 0x1f
3818
+ .4byte 0x34
3819
+ .uleb128 0x7
3820
+ .4byte 0x94
3821
+ .uleb128 0x6
3822
+ .string "u16"
3823
+ .byte 0x3
3824
+ .byte 0x22
3825
+ .4byte 0x42
3826
+ .uleb128 0x6
3827
+ .string "u32"
3828
+ .byte 0x3
3829
+ .byte 0x25
3830
+ .4byte 0x7f
3831
+ .uleb128 0x6
3832
+ .string "u64"
3833
+ .byte 0x3
3834
+ .byte 0x28
3835
+ .4byte 0x8d
3836
+ .uleb128 0x2
3837
+ .4byte .LASF11
3838
+ .byte 0x3
3839
+ .byte 0x31
3840
+ .4byte 0x8d
3841
+ .uleb128 0x2
3842
+ .4byte .LASF12
3843
+ .byte 0x3
3844
+ .byte 0x32
3845
+ .4byte 0x8d
3846
+ .uleb128 0x3
3847
+ .byte 0x8
3848
+ .byte 0x7
3849
+ .4byte .LASF13
3850
+ .uleb128 0x8
3851
+ .byte 0x8
3852
+ .4byte 0xee
3853
+ .uleb128 0x3
3854
+ .byte 0x1
3855
+ .byte 0x8
3856
+ .4byte .LASF14
3857
+ .uleb128 0x7
3858
+ .4byte 0xe7
3859
+ .uleb128 0x3
3860
+ .byte 0x8
3861
+ .byte 0x5
3862
+ .4byte .LASF15
3863
+ .uleb128 0x8
3864
+ .byte 0x8
3865
+ .4byte 0xe7
3866
+ .uleb128 0x2
3867
+ .4byte .LASF16
3868
+ .byte 0x4
3869
+ .byte 0x59
3870
+ .4byte 0x42
3871
+ .uleb128 0x2
3872
+ .4byte .LASF17
3873
+ .byte 0x4
3874
+ .byte 0x5b
3875
+ .4byte 0x3b
3876
+ .uleb128 0x2
3877
+ .4byte .LASF18
3878
+ .byte 0x4
3879
+ .byte 0x69
3880
+ .4byte 0x62
3881
+ .uleb128 0x2
3882
+ .4byte .LASF19
3883
+ .byte 0x4
3884
+ .byte 0x6b
3885
+ .4byte 0x74
3886
+ .uleb128 0x2
3887
+ .4byte .LASF20
3888
+ .byte 0x4
3889
+ .byte 0x97
3890
+ .4byte 0x74
3891
+ .uleb128 0x9
3892
+ .byte 0x8
3893
+ .uleb128 0x4
3894
+ .4byte .LASF22
3895
+ .byte 0x6
3896
+ .byte 0xb
3897
+ .4byte 0xfa
3898
+ .uleb128 0x3
3899
+ .byte 0x1
3900
+ .byte 0x2
3901
+ .4byte .LASF23
3902
+ .uleb128 0xa
3903
+ .4byte 0xe7
3904
+ .4byte 0x156
3905
+ .uleb128 0xb
3906
+ .byte 0
3907
+ .uleb128 0xc
3908
+ .4byte .LASF24
3909
+ .byte 0x7
3910
+ .2byte 0x140
3911
+ .4byte 0x14b
3912
+ .uleb128 0xc
3913
+ .4byte .LASF25
3914
+ .byte 0x7
3915
+ .2byte 0x143
3916
+ .4byte 0x14b
3917
+ .uleb128 0xc
3918
+ .4byte .LASF26
3919
+ .byte 0x7
3920
+ .2byte 0x143
3921
+ .4byte 0x14b
3922
+ .uleb128 0xd
3923
+ .4byte .LASF45
3924
+ .byte 0xa0
3925
+ .byte 0x8
3926
+ .byte 0x83
3927
+ .4byte 0x25f
3928
+ .uleb128 0xe
3929
+ .4byte .LASF27
3930
+ .byte 0x8
3931
+ .byte 0x84
3932
+ .4byte 0x139d
3933
+ .byte 0
3934
+ .uleb128 0xe
3935
+ .4byte .LASF28
3936
+ .byte 0x8
3937
+ .byte 0x85
3938
+ .4byte 0xe1
3939
+ .byte 0x8
3940
+ .uleb128 0xe
3941
+ .4byte .LASF29
3942
+ .byte 0x8
3943
+ .byte 0x86
3944
+ .4byte 0x137
3945
+ .byte 0x10
3946
+ .uleb128 0xe
3947
+ .4byte .LASF30
3948
+ .byte 0x8
3949
+ .byte 0x87
3950
+ .4byte 0x137
3951
+ .byte 0x18
3952
+ .uleb128 0xe
3953
+ .4byte .LASF31
3954
+ .byte 0x8
3955
+ .byte 0x88
3956
+ .4byte 0x137
3957
+ .byte 0x20
3958
+ .uleb128 0xe
3959
+ .4byte .LASF32
3960
+ .byte 0x8
3961
+ .byte 0x89
3962
+ .4byte 0x1344
3963
+ .byte 0x28
3964
+ .uleb128 0xe
3965
+ .4byte .LASF33
3966
+ .byte 0x8
3967
+ .byte 0x8a
3968
+ .4byte 0x10b
3969
+ .byte 0x30
3970
+ .uleb128 0xe
3971
+ .4byte .LASF34
3972
+ .byte 0x8
3973
+ .byte 0x8b
3974
+ .4byte 0x25f
3975
+ .byte 0x38
3976
+ .uleb128 0xe
3977
+ .4byte .LASF35
3978
+ .byte 0x8
3979
+ .byte 0x8c
3980
+ .4byte 0x137
3981
+ .byte 0x40
3982
+ .uleb128 0xe
3983
+ .4byte .LASF36
3984
+ .byte 0x8
3985
+ .byte 0x8d
3986
+ .4byte 0x13ec
3987
+ .byte 0x48
3988
+ .uleb128 0xe
3989
+ .4byte .LASF37
3990
+ .byte 0x8
3991
+ .byte 0x8e
3992
+ .4byte 0x137
3993
+ .byte 0x50
3994
+ .uleb128 0xe
3995
+ .4byte .LASF38
3996
+ .byte 0x8
3997
+ .byte 0x8f
3998
+ .4byte 0x137
3999
+ .byte 0x58
4000
+ .uleb128 0xe
4001
+ .4byte .LASF39
4002
+ .byte 0x8
4003
+ .byte 0x90
4004
+ .4byte 0x292
4005
+ .byte 0x60
4006
+ .uleb128 0xe
4007
+ .4byte .LASF40
4008
+ .byte 0x8
4009
+ .byte 0x91
4010
+ .4byte 0x292
4011
+ .byte 0x70
4012
+ .uleb128 0xe
4013
+ .4byte .LASF41
4014
+ .byte 0x8
4015
+ .byte 0x92
4016
+ .4byte 0x292
4017
+ .byte 0x80
4018
+ .uleb128 0xe
4019
+ .4byte .LASF42
4020
+ .byte 0x8
4021
+ .byte 0x93
4022
+ .4byte 0x121
4023
+ .byte 0x90
4024
+ .uleb128 0xe
4025
+ .4byte .LASF43
4026
+ .byte 0x8
4027
+ .byte 0x94
4028
+ .4byte 0x54
4029
+ .byte 0x94
4030
+ .uleb128 0xf
4031
+ .string "seq"
4032
+ .byte 0x8
4033
+ .byte 0x95
4034
+ .4byte 0x54
4035
+ .byte 0x98
4036
+ .byte 0
4037
+ .uleb128 0x8
4038
+ .byte 0x8
4039
+ .4byte 0x17a
4040
+ .uleb128 0x8
4041
+ .byte 0x8
4042
+ .4byte 0x26b
4043
+ .uleb128 0x10
4044
+ .uleb128 0xa
4045
+ .4byte 0x10b
4046
+ .4byte 0x277
4047
+ .uleb128 0xb
4048
+ .byte 0
4049
+ .uleb128 0x4
4050
+ .4byte .LASF44
4051
+ .byte 0x9
4052
+ .byte 0x10
4053
+ .4byte 0x26c
4054
+ .uleb128 0xa
4055
+ .4byte 0x34
4056
+ .4byte 0x292
4057
+ .uleb128 0x11
4058
+ .4byte 0xda
4059
+ .byte 0x5
4060
+ .byte 0
4061
+ .uleb128 0xd
4062
+ .4byte .LASF46
4063
+ .byte 0x10
4064
+ .byte 0xa
4065
+ .byte 0x16
4066
+ .4byte 0x2b7
4067
+ .uleb128 0xe
4068
+ .4byte .LASF47
4069
+ .byte 0xa
4070
+ .byte 0x17
4071
+ .4byte 0x2b7
4072
+ .byte 0
4073
+ .uleb128 0xe
4074
+ .4byte .LASF48
4075
+ .byte 0xa
4076
+ .byte 0x17
4077
+ .4byte 0x2b7
4078
+ .byte 0x8
4079
+ .byte 0
4080
+ .uleb128 0x8
4081
+ .byte 0x8
4082
+ .4byte 0x292
4083
+ .uleb128 0xd
4084
+ .4byte .LASF49
4085
+ .byte 0x10
4086
+ .byte 0xb
4087
+ .byte 0xf
4088
+ .4byte 0x2e2
4089
+ .uleb128 0xe
4090
+ .4byte .LASF28
4091
+ .byte 0xb
4092
+ .byte 0x10
4093
+ .4byte 0xfa
4094
+ .byte 0
4095
+ .uleb128 0xe
4096
+ .4byte .LASF50
4097
+ .byte 0xb
4098
+ .byte 0x11
4099
+ .4byte 0x2fb
4100
+ .byte 0x8
4101
+ .byte 0
4102
+ .uleb128 0x7
4103
+ .4byte 0x2bd
4104
+ .uleb128 0x12
4105
+ .4byte 0x54
4106
+ .4byte 0x2fb
4107
+ .uleb128 0x13
4108
+ .4byte 0x54
4109
+ .uleb128 0x13
4110
+ .4byte 0x54
4111
+ .byte 0
4112
+ .uleb128 0x8
4113
+ .byte 0x8
4114
+ .4byte 0x2e7
4115
+ .uleb128 0xa
4116
+ .4byte 0x2e2
4117
+ .4byte 0x30c
4118
+ .uleb128 0xb
4119
+ .byte 0
4120
+ .uleb128 0x7
4121
+ .4byte 0x301
4122
+ .uleb128 0x4
4123
+ .4byte .LASF49
4124
+ .byte 0xb
4125
+ .byte 0xe1
4126
+ .4byte 0x30c
4127
+ .uleb128 0x14
4128
+ .2byte 0x1220
4129
+ .byte 0xc
4130
+ .byte 0x13
4131
+ .4byte 0x370
4132
+ .uleb128 0xe
4133
+ .4byte .LASF51
4134
+ .byte 0xc
4135
+ .byte 0x14
4136
+ .4byte 0x10b
4137
+ .byte 0
4138
+ .uleb128 0xe
4139
+ .4byte .LASF52
4140
+ .byte 0xc
4141
+ .byte 0x15
4142
+ .4byte 0x100
4143
+ .byte 0x8
4144
+ .uleb128 0xe
4145
+ .4byte .LASF53
4146
+ .byte 0xc
4147
+ .byte 0x16
4148
+ .4byte 0x10b
4149
+ .byte 0x10
4150
+ .uleb128 0xe
4151
+ .4byte .LASF54
4152
+ .byte 0xc
4153
+ .byte 0x17
4154
+ .4byte 0x370
4155
+ .byte 0x18
4156
+ .uleb128 0x15
4157
+ .4byte .LASF55
4158
+ .byte 0xc
4159
+ .byte 0x18
4160
+ .4byte 0x381
4161
+ .2byte 0x1018
4162
+ .uleb128 0x16
4163
+ .string "mtd"
4164
+ .byte 0xc
4165
+ .byte 0x31
4166
+ .4byte 0x397
4167
+ .2byte 0x1218
4168
+ .byte 0
4169
+ .uleb128 0xa
4170
+ .4byte 0x10b
4171
+ .4byte 0x381
4172
+ .uleb128 0x17
4173
+ .4byte 0xda
4174
+ .2byte 0x1ff
4175
+ .byte 0
4176
+ .uleb128 0xa
4177
+ .4byte 0x29
4178
+ .4byte 0x392
4179
+ .uleb128 0x17
4180
+ .4byte 0xda
4181
+ .2byte 0x1ff
4182
+ .byte 0
4183
+ .uleb128 0x18
4184
+ .4byte .LASF318
4185
+ .uleb128 0x8
4186
+ .byte 0x8
4187
+ .4byte 0x392
4188
+ .uleb128 0x2
4189
+ .4byte .LASF56
4190
+ .byte 0xc
4191
+ .byte 0x37
4192
+ .4byte 0x31c
4193
+ .uleb128 0xa
4194
+ .4byte 0x39d
4195
+ .4byte 0x3b3
4196
+ .uleb128 0xb
4197
+ .byte 0
4198
+ .uleb128 0x4
4199
+ .4byte .LASF57
4200
+ .byte 0xc
4201
+ .byte 0x39
4202
+ .4byte 0x3a8
4203
+ .uleb128 0x3
4204
+ .byte 0x10
4205
+ .byte 0x4
4206
+ .4byte .LASF58
4207
+ .uleb128 0xd
4208
+ .4byte .LASF59
4209
+ .byte 0x10
4210
+ .byte 0xd
4211
+ .byte 0x10
4212
+ .4byte 0x3ea
4213
+ .uleb128 0xe
4214
+ .4byte .LASF60
4215
+ .byte 0xd
4216
+ .byte 0x11
4217
+ .4byte 0xc4
4218
+ .byte 0
4219
+ .uleb128 0xe
4220
+ .4byte .LASF51
4221
+ .byte 0xd
4222
+ .byte 0x12
4223
+ .4byte 0xcf
4224
+ .byte 0x8
4225
+ .byte 0
4226
+ .uleb128 0x19
4227
+ .4byte .LASF61
4228
+ .2byte 0x120
4229
+ .byte 0xd
4230
+ .byte 0x15
4231
+ .4byte 0x41c
4232
+ .uleb128 0xf
4233
+ .string "cnt"
4234
+ .byte 0xd
4235
+ .byte 0x16
4236
+ .4byte 0x3b
4237
+ .byte 0
4238
+ .uleb128 0xe
4239
+ .4byte .LASF51
4240
+ .byte 0xd
4241
+ .byte 0x17
4242
+ .4byte 0xcf
4243
+ .byte 0x8
4244
+ .uleb128 0xe
4245
+ .4byte .LASF62
4246
+ .byte 0xd
4247
+ .byte 0x18
4248
+ .4byte 0x41c
4249
+ .byte 0x10
4250
+ .byte 0
4251
+ .uleb128 0xa
4252
+ .4byte 0x3c5
4253
+ .4byte 0x42c
4254
+ .uleb128 0x11
4255
+ .4byte 0xda
4256
+ .byte 0x10
4257
+ .byte 0
4258
+ .uleb128 0x1a
4259
+ .string "lmb"
4260
+ .2byte 0x240
4261
+ .byte 0xd
4262
+ .byte 0x1b
4263
+ .4byte 0x453
4264
+ .uleb128 0xe
4265
+ .4byte .LASF63
4266
+ .byte 0xd
4267
+ .byte 0x1c
4268
+ .4byte 0x3ea
4269
+ .byte 0
4270
+ .uleb128 0x15
4271
+ .4byte .LASF64
4272
+ .byte 0xd
4273
+ .byte 0x1d
4274
+ .4byte 0x3ea
4275
+ .2byte 0x120
4276
+ .byte 0
4277
+ .uleb128 0x1b
4278
+ .string "lmb"
4279
+ .byte 0xd
4280
+ .byte 0x20
4281
+ .4byte 0x42c
4282
+ .uleb128 0x1c
4283
+ .byte 0x10
4284
+ .byte 0xe
4285
+ .byte 0x5d
4286
+ .4byte 0x47f
4287
+ .uleb128 0xe
4288
+ .4byte .LASF54
4289
+ .byte 0xe
4290
+ .byte 0x5e
4291
+ .4byte 0xb9
4292
+ .byte 0
4293
+ .uleb128 0xe
4294
+ .4byte .LASF51
4295
+ .byte 0xe
4296
+ .byte 0x5f
4297
+ .4byte 0xb9
4298
+ .byte 0x8
4299
+ .byte 0
4300
+ .uleb128 0xd
4301
+ .4byte .LASF65
4302
+ .byte 0xb0
4303
+ .byte 0xe
4304
+ .byte 0x1b
4305
+ .4byte 0x57c
4306
+ .uleb128 0xe
4307
+ .4byte .LASF66
4308
+ .byte 0xe
4309
+ .byte 0x1c
4310
+ .4byte 0x3b
4311
+ .byte 0
4312
+ .uleb128 0xe
4313
+ .4byte .LASF67
4314
+ .byte 0xe
4315
+ .byte 0x1d
4316
+ .4byte 0xcf
4317
+ .byte 0x8
4318
+ .uleb128 0xe
4319
+ .4byte .LASF68
4320
+ .byte 0xe
4321
+ .byte 0x1e
4322
+ .4byte 0x3b
4323
+ .byte 0x10
4324
+ .uleb128 0xe
4325
+ .4byte .LASF69
4326
+ .byte 0xe
4327
+ .byte 0x1f
4328
+ .4byte 0x3b
4329
+ .byte 0x18
4330
+ .uleb128 0xe
4331
+ .4byte .LASF70
4332
+ .byte 0xe
4333
+ .byte 0x20
4334
+ .4byte 0x3b
4335
+ .byte 0x20
4336
+ .uleb128 0xe
4337
+ .4byte .LASF71
4338
+ .byte 0xe
4339
+ .byte 0x21
4340
+ .4byte 0x3b
4341
+ .byte 0x28
4342
+ .uleb128 0xe
4343
+ .4byte .LASF72
4344
+ .byte 0xe
4345
+ .byte 0x22
4346
+ .4byte 0x3b
4347
+ .byte 0x30
4348
+ .uleb128 0xe
4349
+ .4byte .LASF73
4350
+ .byte 0xe
4351
+ .byte 0x24
4352
+ .4byte 0x3b
4353
+ .byte 0x38
4354
+ .uleb128 0xe
4355
+ .4byte .LASF74
4356
+ .byte 0xe
4357
+ .byte 0x25
4358
+ .4byte 0x3b
4359
+ .byte 0x40
4360
+ .uleb128 0xe
4361
+ .4byte .LASF75
4362
+ .byte 0xe
4363
+ .byte 0x26
4364
+ .4byte 0x3b
4365
+ .byte 0x48
4366
+ .uleb128 0xe
4367
+ .4byte .LASF76
4368
+ .byte 0xe
4369
+ .byte 0x31
4370
+ .4byte 0x3b
4371
+ .byte 0x50
4372
+ .uleb128 0xe
4373
+ .4byte .LASF77
4374
+ .byte 0xe
4375
+ .byte 0x32
4376
+ .4byte 0x3b
4377
+ .byte 0x58
4378
+ .uleb128 0xe
4379
+ .4byte .LASF78
4380
+ .byte 0xe
4381
+ .byte 0x33
4382
+ .4byte 0x282
4383
+ .byte 0x60
4384
+ .uleb128 0xe
4385
+ .4byte .LASF79
4386
+ .byte 0xe
4387
+ .byte 0x34
4388
+ .4byte 0x42
4389
+ .byte 0x66
4390
+ .uleb128 0xe
4391
+ .4byte .LASF80
4392
+ .byte 0xe
4393
+ .byte 0x35
4394
+ .4byte 0x3b
4395
+ .byte 0x68
4396
+ .uleb128 0xe
4397
+ .4byte .LASF81
4398
+ .byte 0xe
4399
+ .byte 0x36
4400
+ .4byte 0x3b
4401
+ .byte 0x70
4402
+ .uleb128 0xe
4403
+ .4byte .LASF82
4404
+ .byte 0xe
4405
+ .byte 0x57
4406
+ .4byte 0x10b
4407
+ .byte 0x78
4408
+ .uleb128 0xe
4409
+ .4byte .LASF83
4410
+ .byte 0xe
4411
+ .byte 0x58
4412
+ .4byte 0x10b
4413
+ .byte 0x80
4414
+ .uleb128 0xe
4415
+ .4byte .LASF84
4416
+ .byte 0xe
4417
+ .byte 0x5b
4418
+ .4byte 0x7f
4419
+ .byte 0x88
4420
+ .uleb128 0xe
4421
+ .4byte .LASF85
4422
+ .byte 0xe
4423
+ .byte 0x60
4424
+ .4byte 0x57c
4425
+ .byte 0x90
4426
+ .byte 0
4427
+ .uleb128 0xa
4428
+ .4byte 0x45e
4429
+ .4byte 0x58c
4430
+ .uleb128 0x11
4431
+ .4byte 0xda
4432
+ .byte 0x1
4433
+ .byte 0
4434
+ .uleb128 0x2
4435
+ .4byte .LASF86
4436
+ .byte 0xe
4437
+ .byte 0x62
4438
+ .4byte 0x47f
4439
+ .uleb128 0x4
4440
+ .4byte .LASF87
4441
+ .byte 0xf
4442
+ .byte 0x13
4443
+ .4byte 0x10b
4444
+ .uleb128 0x4
4445
+ .4byte .LASF88
4446
+ .byte 0xf
4447
+ .byte 0x14
4448
+ .4byte 0x10b
4449
+ .uleb128 0x4
4450
+ .4byte .LASF89
4451
+ .byte 0xf
4452
+ .byte 0x15
4453
+ .4byte 0x10b
4454
+ .uleb128 0x4
4455
+ .4byte .LASF90
4456
+ .byte 0xf
4457
+ .byte 0x16
4458
+ .4byte 0x10b
4459
+ .uleb128 0x4
4460
+ .4byte .LASF91
4461
+ .byte 0xf
4462
+ .byte 0x17
4463
+ .4byte 0x10b
4464
+ .uleb128 0x4
4465
+ .4byte .LASF92
4466
+ .byte 0xf
4467
+ .byte 0x18
4468
+ .4byte 0x10b
4469
+ .uleb128 0x4
4470
+ .4byte .LASF93
4471
+ .byte 0xf
4472
+ .byte 0x19
4473
+ .4byte 0x10b
4474
+ .uleb128 0x2
4475
+ .4byte .LASF94
4476
+ .byte 0x10
4477
+ .byte 0x11
4478
+ .4byte 0x12c
4479
+ .uleb128 0xd
4480
+ .4byte .LASF95
4481
+ .byte 0x28
4482
+ .byte 0x11
4483
+ .byte 0x39
4484
+ .4byte 0x674
4485
+ .uleb128 0xe
4486
+ .4byte .LASF96
4487
+ .byte 0x11
4488
+ .byte 0x3a
4489
+ .4byte 0x5e4
4490
+ .byte 0
4491
+ .uleb128 0xe
4492
+ .4byte .LASF97
4493
+ .byte 0x11
4494
+ .byte 0x3b
4495
+ .4byte 0x5e4
4496
+ .byte 0x4
4497
+ .uleb128 0xe
4498
+ .4byte .LASF98
4499
+ .byte 0x11
4500
+ .byte 0x3c
4501
+ .4byte 0x5e4
4502
+ .byte 0x8
4503
+ .uleb128 0xe
4504
+ .4byte .LASF99
4505
+ .byte 0x11
4506
+ .byte 0x3d
4507
+ .4byte 0x5e4
4508
+ .byte 0xc
4509
+ .uleb128 0xe
4510
+ .4byte .LASF100
4511
+ .byte 0x11
4512
+ .byte 0x3e
4513
+ .4byte 0x5e4
4514
+ .byte 0x10
4515
+ .uleb128 0xe
4516
+ .4byte .LASF101
4517
+ .byte 0x11
4518
+ .byte 0x3f
4519
+ .4byte 0x5e4
4520
+ .byte 0x14
4521
+ .uleb128 0xe
4522
+ .4byte .LASF102
4523
+ .byte 0x11
4524
+ .byte 0x40
4525
+ .4byte 0x5e4
4526
+ .byte 0x18
4527
+ .uleb128 0xe
4528
+ .4byte .LASF103
4529
+ .byte 0x11
4530
+ .byte 0x43
4531
+ .4byte 0x5e4
4532
+ .byte 0x1c
4533
+ .uleb128 0xe
4534
+ .4byte .LASF104
4535
+ .byte 0x11
4536
+ .byte 0x46
4537
+ .4byte 0x5e4
4538
+ .byte 0x20
4539
+ .uleb128 0xe
4540
+ .4byte .LASF105
4541
+ .byte 0x11
4542
+ .byte 0x49
4543
+ .4byte 0x5e4
4544
+ .byte 0x24
4545
+ .byte 0
4546
+ .uleb128 0xc
4547
+ .4byte .LASF106
4548
+ .byte 0x12
4549
+ .2byte 0x136
4550
+ .4byte 0x680
4551
+ .uleb128 0x8
4552
+ .byte 0x8
4553
+ .4byte 0x5ef
4554
+ .uleb128 0x1d
4555
+ .4byte .LASF107
4556
+ .byte 0x40
4557
+ .byte 0x13
4558
+ .2byte 0x137
4559
+ .4byte 0x730
4560
+ .uleb128 0x1e
4561
+ .4byte .LASF108
4562
+ .byte 0x13
4563
+ .2byte 0x138
4564
+ .4byte 0x12c
4565
+ .byte 0
4566
+ .uleb128 0x1e
4567
+ .4byte .LASF109
4568
+ .byte 0x13
4569
+ .2byte 0x139
4570
+ .4byte 0x12c
4571
+ .byte 0x4
4572
+ .uleb128 0x1e
4573
+ .4byte .LASF110
4574
+ .byte 0x13
4575
+ .2byte 0x13a
4576
+ .4byte 0x12c
4577
+ .byte 0x8
4578
+ .uleb128 0x1e
4579
+ .4byte .LASF111
4580
+ .byte 0x13
4581
+ .2byte 0x13b
4582
+ .4byte 0x12c
4583
+ .byte 0xc
4584
+ .uleb128 0x1e
4585
+ .4byte .LASF112
4586
+ .byte 0x13
4587
+ .2byte 0x13c
4588
+ .4byte 0x12c
4589
+ .byte 0x10
4590
+ .uleb128 0x1e
4591
+ .4byte .LASF113
4592
+ .byte 0x13
4593
+ .2byte 0x13d
4594
+ .4byte 0x12c
4595
+ .byte 0x14
4596
+ .uleb128 0x1e
4597
+ .4byte .LASF114
4598
+ .byte 0x13
4599
+ .2byte 0x13e
4600
+ .4byte 0x12c
4601
+ .byte 0x18
4602
+ .uleb128 0x1e
4603
+ .4byte .LASF115
4604
+ .byte 0x13
4605
+ .2byte 0x13f
4606
+ .4byte 0x116
4607
+ .byte 0x1c
4608
+ .uleb128 0x1e
4609
+ .4byte .LASF116
4610
+ .byte 0x13
4611
+ .2byte 0x140
4612
+ .4byte 0x116
4613
+ .byte 0x1d
4614
+ .uleb128 0x1e
4615
+ .4byte .LASF117
4616
+ .byte 0x13
4617
+ .2byte 0x141
4618
+ .4byte 0x116
4619
+ .byte 0x1e
4620
+ .uleb128 0x1e
4621
+ .4byte .LASF118
4622
+ .byte 0x13
4623
+ .2byte 0x142
4624
+ .4byte 0x116
4625
+ .byte 0x1f
4626
+ .uleb128 0x1e
4627
+ .4byte .LASF119
4628
+ .byte 0x13
4629
+ .2byte 0x143
4630
+ .4byte 0x730
4631
+ .byte 0x20
4632
+ .byte 0
4633
+ .uleb128 0xa
4634
+ .4byte 0x116
4635
+ .4byte 0x740
4636
+ .uleb128 0x11
4637
+ .4byte 0xda
4638
+ .byte 0x1f
4639
+ .byte 0
4640
+ .uleb128 0x1f
4641
+ .4byte .LASF120
4642
+ .byte 0x13
4643
+ .2byte 0x144
4644
+ .4byte 0x686
4645
+ .uleb128 0x1d
4646
+ .4byte .LASF121
4647
+ .byte 0x30
4648
+ .byte 0x13
4649
+ .2byte 0x146
4650
+ .4byte 0x7ce
4651
+ .uleb128 0x1e
4652
+ .4byte .LASF54
4653
+ .byte 0x13
4654
+ .2byte 0x147
4655
+ .4byte 0x10b
4656
+ .byte 0
4657
+ .uleb128 0x20
4658
+ .string "end"
4659
+ .byte 0x13
4660
+ .2byte 0x147
4661
+ .4byte 0x10b
4662
+ .byte 0x8
4663
+ .uleb128 0x1e
4664
+ .4byte .LASF122
4665
+ .byte 0x13
4666
+ .2byte 0x148
4667
+ .4byte 0x10b
4668
+ .byte 0x10
4669
+ .uleb128 0x1e
4670
+ .4byte .LASF123
4671
+ .byte 0x13
4672
+ .2byte 0x148
4673
+ .4byte 0x10b
4674
+ .byte 0x18
4675
+ .uleb128 0x1e
4676
+ .4byte .LASF124
4677
+ .byte 0x13
4678
+ .2byte 0x149
4679
+ .4byte 0x10b
4680
+ .byte 0x20
4681
+ .uleb128 0x1e
4682
+ .4byte .LASF125
4683
+ .byte 0x13
4684
+ .2byte 0x14a
4685
+ .4byte 0x116
4686
+ .byte 0x28
4687
+ .uleb128 0x1e
4688
+ .4byte .LASF126
4689
+ .byte 0x13
4690
+ .2byte 0x14a
4691
+ .4byte 0x116
4692
+ .byte 0x29
4693
+ .uleb128 0x20
4694
+ .string "os"
4695
+ .byte 0x13
4696
+ .2byte 0x14a
4697
+ .4byte 0x116
4698
+ .byte 0x2a
4699
+ .uleb128 0x1e
4700
+ .4byte .LASF127
4701
+ .byte 0x13
4702
+ .2byte 0x14b
4703
+ .4byte 0x116
4704
+ .byte 0x2b
4705
+ .byte 0
4706
+ .uleb128 0x1f
4707
+ .4byte .LASF128
4708
+ .byte 0x13
4709
+ .2byte 0x14c
4710
+ .4byte 0x74c
4711
+ .uleb128 0x21
4712
+ .4byte .LASF129
4713
+ .2byte 0x380
4714
+ .byte 0x13
4715
+ .2byte 0x152
4716
+ .4byte 0x977
4717
+ .uleb128 0x1e
4718
+ .4byte .LASF130
4719
+ .byte 0x13
4720
+ .2byte 0x158
4721
+ .4byte 0x977
4722
+ .byte 0
4723
+ .uleb128 0x1e
4724
+ .4byte .LASF131
4725
+ .byte 0x13
4726
+ .2byte 0x159
4727
+ .4byte 0x740
4728
+ .byte 0x8
4729
+ .uleb128 0x1e
4730
+ .4byte .LASF132
4731
+ .byte 0x13
4732
+ .2byte 0x15a
4733
+ .4byte 0x10b
4734
+ .byte 0x48
4735
+ .uleb128 0x1e
4736
+ .4byte .LASF133
4737
+ .byte 0x13
4738
+ .2byte 0x15d
4739
+ .4byte 0xe1
4740
+ .byte 0x50
4741
+ .uleb128 0x1e
4742
+ .4byte .LASF134
4743
+ .byte 0x13
4744
+ .2byte 0x15f
4745
+ .4byte 0x137
4746
+ .byte 0x58
4747
+ .uleb128 0x1e
4748
+ .4byte .LASF135
4749
+ .byte 0x13
4750
+ .2byte 0x160
4751
+ .4byte 0xe1
4752
+ .byte 0x60
4753
+ .uleb128 0x1e
4754
+ .4byte .LASF136
4755
+ .byte 0x13
4756
+ .2byte 0x161
4757
+ .4byte 0x54
4758
+ .byte 0x68
4759
+ .uleb128 0x1e
4760
+ .4byte .LASF137
4761
+ .byte 0x13
4762
+ .2byte 0x163
4763
+ .4byte 0x137
4764
+ .byte 0x70
4765
+ .uleb128 0x1e
4766
+ .4byte .LASF138
4767
+ .byte 0x13
4768
+ .2byte 0x164
4769
+ .4byte 0xe1
4770
+ .byte 0x78
4771
+ .uleb128 0x1e
4772
+ .4byte .LASF139
4773
+ .byte 0x13
4774
+ .2byte 0x165
4775
+ .4byte 0x54
4776
+ .byte 0x80
4777
+ .uleb128 0x1e
4778
+ .4byte .LASF140
4779
+ .byte 0x13
4780
+ .2byte 0x167
4781
+ .4byte 0x137
4782
+ .byte 0x88
4783
+ .uleb128 0x1e
4784
+ .4byte .LASF141
4785
+ .byte 0x13
4786
+ .2byte 0x168
4787
+ .4byte 0xe1
4788
+ .byte 0x90
4789
+ .uleb128 0x1e
4790
+ .4byte .LASF142
4791
+ .byte 0x13
4792
+ .2byte 0x169
4793
+ .4byte 0x54
4794
+ .byte 0x98
4795
+ .uleb128 0x1e
4796
+ .4byte .LASF143
4797
+ .byte 0x13
4798
+ .2byte 0x16b
4799
+ .4byte 0x137
4800
+ .byte 0xa0
4801
+ .uleb128 0x1e
4802
+ .4byte .LASF144
4803
+ .byte 0x13
4804
+ .2byte 0x16c
4805
+ .4byte 0xe1
4806
+ .byte 0xa8
4807
+ .uleb128 0x1e
4808
+ .4byte .LASF145
4809
+ .byte 0x13
4810
+ .2byte 0x16d
4811
+ .4byte 0x54
4812
+ .byte 0xb0
4813
+ .uleb128 0x20
4814
+ .string "os"
4815
+ .byte 0x13
4816
+ .2byte 0x171
4817
+ .4byte 0x7ce
4818
+ .byte 0xb8
4819
+ .uleb128 0x20
4820
+ .string "ep"
4821
+ .byte 0x13
4822
+ .2byte 0x172
4823
+ .4byte 0x10b
4824
+ .byte 0xe8
4825
+ .uleb128 0x1e
4826
+ .4byte .LASF146
4827
+ .byte 0x13
4828
+ .2byte 0x174
4829
+ .4byte 0x10b
4830
+ .byte 0xf0
4831
+ .uleb128 0x1e
4832
+ .4byte .LASF147
4833
+ .byte 0x13
4834
+ .2byte 0x174
4835
+ .4byte 0x10b
4836
+ .byte 0xf8
4837
+ .uleb128 0x22
4838
+ .4byte .LASF148
4839
+ .byte 0x13
4840
+ .2byte 0x176
4841
+ .4byte 0xfa
4842
+ .2byte 0x100
4843
+ .uleb128 0x22
4844
+ .4byte .LASF149
4845
+ .byte 0x13
4846
+ .2byte 0x177
4847
+ .4byte 0x10b
4848
+ .2byte 0x108
4849
+ .uleb128 0x22
4850
+ .4byte .LASF150
4851
+ .byte 0x13
4852
+ .2byte 0x179
4853
+ .4byte 0x10b
4854
+ .2byte 0x110
4855
+ .uleb128 0x22
4856
+ .4byte .LASF151
4857
+ .byte 0x13
4858
+ .2byte 0x17a
4859
+ .4byte 0x10b
4860
+ .2byte 0x118
4861
+ .uleb128 0x22
4862
+ .4byte .LASF152
4863
+ .byte 0x13
4864
+ .2byte 0x17b
4865
+ .4byte 0x10b
4866
+ .2byte 0x120
4867
+ .uleb128 0x22
4868
+ .4byte .LASF153
4869
+ .byte 0x13
4870
+ .2byte 0x17c
4871
+ .4byte 0x10b
4872
+ .2byte 0x128
4873
+ .uleb128 0x23
4874
+ .string "kbd"
4875
+ .byte 0x13
4876
+ .2byte 0x17d
4877
+ .4byte 0x97d
4878
+ .2byte 0x130
4879
+ .uleb128 0x22
4880
+ .4byte .LASF154
4881
+ .byte 0x13
4882
+ .2byte 0x180
4883
+ .4byte 0x54
4884
+ .2byte 0x138
4885
+ .uleb128 0x22
4886
+ .4byte .LASF155
4887
+ .byte 0x13
4888
+ .2byte 0x18d
4889
+ .4byte 0x54
4890
+ .2byte 0x13c
4891
+ .uleb128 0x23
4892
+ .string "lmb"
4893
+ .byte 0x13
4894
+ .2byte 0x190
4895
+ .4byte 0x42c
4896
+ .2byte 0x140
4897
+ .byte 0
4898
+ .uleb128 0x8
4899
+ .byte 0x8
4900
+ .4byte 0x740
4901
+ .uleb128 0x8
4902
+ .byte 0x8
4903
+ .4byte 0x58c
4904
+ .uleb128 0x1f
4905
+ .4byte .LASF156
4906
+ .byte 0x13
4907
+ .2byte 0x196
4908
+ .4byte 0x7da
4909
+ .uleb128 0xc
4910
+ .4byte .LASF157
4911
+ .byte 0x13
4912
+ .2byte 0x198
4913
+ .4byte 0x983
4914
+ .uleb128 0xa
4915
+ .4byte 0xe7
4916
+ .4byte 0x9ac
4917
+ .uleb128 0x17
4918
+ .4byte 0xda
4919
+ .2byte 0x3ff
4920
+ .byte 0
4921
+ .uleb128 0x24
4922
+ .4byte .LASF352
4923
+ .byte 0x4
4924
+ .4byte 0x54
4925
+ .byte 0x18
4926
+ .byte 0xe
4927
+ .4byte 0xc15
4928
+ .uleb128 0x25
4929
+ .4byte .LASF158
4930
+ .byte 0
4931
+ .uleb128 0x25
4932
+ .4byte .LASF159
4933
+ .byte 0x1
4934
+ .uleb128 0x25
4935
+ .4byte .LASF160
4936
+ .byte 0x2
4937
+ .uleb128 0x25
4938
+ .4byte .LASF161
4939
+ .byte 0x3
4940
+ .uleb128 0x25
4941
+ .4byte .LASF162
4942
+ .byte 0x4
4943
+ .uleb128 0x25
4944
+ .4byte .LASF163
4945
+ .byte 0x5
4946
+ .uleb128 0x25
4947
+ .4byte .LASF164
4948
+ .byte 0x6
4949
+ .uleb128 0x25
4950
+ .4byte .LASF165
4951
+ .byte 0x7
4952
+ .uleb128 0x25
4953
+ .4byte .LASF166
4954
+ .byte 0x8
4955
+ .uleb128 0x25
4956
+ .4byte .LASF167
4957
+ .byte 0x9
4958
+ .uleb128 0x25
4959
+ .4byte .LASF168
4960
+ .byte 0xa
4961
+ .uleb128 0x25
4962
+ .4byte .LASF169
4963
+ .byte 0xb
4964
+ .uleb128 0x25
4965
+ .4byte .LASF170
4966
+ .byte 0xc
4967
+ .uleb128 0x25
4968
+ .4byte .LASF171
4969
+ .byte 0xd
4970
+ .uleb128 0x25
4971
+ .4byte .LASF172
4972
+ .byte 0xe
4973
+ .uleb128 0x25
4974
+ .4byte .LASF173
4975
+ .byte 0xf
4976
+ .uleb128 0x25
4977
+ .4byte .LASF174
4978
+ .byte 0x10
4979
+ .uleb128 0x25
4980
+ .4byte .LASF175
4981
+ .byte 0x11
4982
+ .uleb128 0x25
4983
+ .4byte .LASF176
4984
+ .byte 0x12
4985
+ .uleb128 0x25
4986
+ .4byte .LASF177
4987
+ .byte 0x13
4988
+ .uleb128 0x25
4989
+ .4byte .LASF178
4990
+ .byte 0x14
4991
+ .uleb128 0x25
4992
+ .4byte .LASF179
4993
+ .byte 0x15
4994
+ .uleb128 0x25
4995
+ .4byte .LASF180
4996
+ .byte 0x16
4997
+ .uleb128 0x25
4998
+ .4byte .LASF181
4999
+ .byte 0x17
5000
+ .uleb128 0x25
5001
+ .4byte .LASF182
5002
+ .byte 0x18
5003
+ .uleb128 0x25
5004
+ .4byte .LASF183
5005
+ .byte 0x19
5006
+ .uleb128 0x25
5007
+ .4byte .LASF184
5008
+ .byte 0x1a
5009
+ .uleb128 0x25
5010
+ .4byte .LASF185
5011
+ .byte 0x1b
5012
+ .uleb128 0x25
5013
+ .4byte .LASF186
5014
+ .byte 0x1c
5015
+ .uleb128 0x25
5016
+ .4byte .LASF187
5017
+ .byte 0x1d
5018
+ .uleb128 0x25
5019
+ .4byte .LASF188
5020
+ .byte 0x1e
5021
+ .uleb128 0x25
5022
+ .4byte .LASF189
5023
+ .byte 0x1f
5024
+ .uleb128 0x25
5025
+ .4byte .LASF190
5026
+ .byte 0x20
5027
+ .uleb128 0x25
5028
+ .4byte .LASF191
5029
+ .byte 0x21
5030
+ .uleb128 0x25
5031
+ .4byte .LASF192
5032
+ .byte 0x22
5033
+ .uleb128 0x25
5034
+ .4byte .LASF193
5035
+ .byte 0x23
5036
+ .uleb128 0x25
5037
+ .4byte .LASF194
5038
+ .byte 0x24
5039
+ .uleb128 0x25
5040
+ .4byte .LASF195
5041
+ .byte 0x25
5042
+ .uleb128 0x25
5043
+ .4byte .LASF196
5044
+ .byte 0x26
5045
+ .uleb128 0x25
5046
+ .4byte .LASF197
5047
+ .byte 0x27
5048
+ .uleb128 0x25
5049
+ .4byte .LASF198
5050
+ .byte 0x28
5051
+ .uleb128 0x25
5052
+ .4byte .LASF199
5053
+ .byte 0x29
5054
+ .uleb128 0x25
5055
+ .4byte .LASF200
5056
+ .byte 0x2a
5057
+ .uleb128 0x25
5058
+ .4byte .LASF201
5059
+ .byte 0x2b
5060
+ .uleb128 0x25
5061
+ .4byte .LASF202
5062
+ .byte 0x2c
5063
+ .uleb128 0x25
5064
+ .4byte .LASF203
5065
+ .byte 0x2d
5066
+ .uleb128 0x25
5067
+ .4byte .LASF204
5068
+ .byte 0x2e
5069
+ .uleb128 0x25
5070
+ .4byte .LASF205
5071
+ .byte 0x2f
5072
+ .uleb128 0x25
5073
+ .4byte .LASF206
5074
+ .byte 0x30
5075
+ .uleb128 0x25
5076
+ .4byte .LASF207
5077
+ .byte 0x31
5078
+ .uleb128 0x25
5079
+ .4byte .LASF208
5080
+ .byte 0x32
5081
+ .uleb128 0x25
5082
+ .4byte .LASF209
5083
+ .byte 0x33
5084
+ .uleb128 0x25
5085
+ .4byte .LASF210
5086
+ .byte 0x34
5087
+ .uleb128 0x25
5088
+ .4byte .LASF211
5089
+ .byte 0x35
5090
+ .uleb128 0x25
5091
+ .4byte .LASF212
5092
+ .byte 0x36
5093
+ .uleb128 0x25
5094
+ .4byte .LASF213
5095
+ .byte 0x37
5096
+ .uleb128 0x25
5097
+ .4byte .LASF214
5098
+ .byte 0x38
5099
+ .uleb128 0x25
5100
+ .4byte .LASF215
5101
+ .byte 0x39
5102
+ .uleb128 0x25
5103
+ .4byte .LASF216
5104
+ .byte 0x3a
5105
+ .uleb128 0x25
5106
+ .4byte .LASF217
5107
+ .byte 0x3b
5108
+ .uleb128 0x25
5109
+ .4byte .LASF218
5110
+ .byte 0x3c
5111
+ .uleb128 0x25
5112
+ .4byte .LASF219
5113
+ .byte 0x3d
5114
+ .uleb128 0x25
5115
+ .4byte .LASF220
5116
+ .byte 0x3e
5117
+ .uleb128 0x25
5118
+ .4byte .LASF221
5119
+ .byte 0x3f
5120
+ .uleb128 0x25
5121
+ .4byte .LASF222
5122
+ .byte 0x40
5123
+ .uleb128 0x25
5124
+ .4byte .LASF223
5125
+ .byte 0x41
5126
+ .uleb128 0x25
5127
+ .4byte .LASF224
5128
+ .byte 0x42
5129
+ .uleb128 0x25
5130
+ .4byte .LASF225
5131
+ .byte 0x43
5132
+ .uleb128 0x25
5133
+ .4byte .LASF226
5134
+ .byte 0x44
5135
+ .uleb128 0x25
5136
+ .4byte .LASF227
5137
+ .byte 0x45
5138
+ .uleb128 0x25
5139
+ .4byte .LASF228
5140
+ .byte 0x46
5141
+ .uleb128 0x25
5142
+ .4byte .LASF229
5143
+ .byte 0x47
5144
+ .uleb128 0x25
5145
+ .4byte .LASF230
5146
+ .byte 0x48
5147
+ .uleb128 0x25
5148
+ .4byte .LASF231
5149
+ .byte 0x49
5150
+ .uleb128 0x25
5151
+ .4byte .LASF232
5152
+ .byte 0x4a
5153
+ .uleb128 0x25
5154
+ .4byte .LASF233
5155
+ .byte 0x4b
5156
+ .uleb128 0x25
5157
+ .4byte .LASF234
5158
+ .byte 0x4c
5159
+ .uleb128 0x25
5160
+ .4byte .LASF235
5161
+ .byte 0x4d
5162
+ .uleb128 0x25
5163
+ .4byte .LASF236
5164
+ .byte 0x4e
5165
+ .uleb128 0x25
5166
+ .4byte .LASF237
5167
+ .byte 0x4f
5168
+ .uleb128 0x25
5169
+ .4byte .LASF238
5170
+ .byte 0x50
5171
+ .uleb128 0x25
5172
+ .4byte .LASF239
5173
+ .byte 0x51
5174
+ .uleb128 0x25
5175
+ .4byte .LASF240
5176
+ .byte 0x52
5177
+ .uleb128 0x25
5178
+ .4byte .LASF241
5179
+ .byte 0x53
5180
+ .uleb128 0x25
5181
+ .4byte .LASF242
5182
+ .byte 0x54
5183
+ .uleb128 0x25
5184
+ .4byte .LASF243
5185
+ .byte 0x55
5186
+ .uleb128 0x25
5187
+ .4byte .LASF244
5188
+ .byte 0x56
5189
+ .uleb128 0x25
5190
+ .4byte .LASF245
5191
+ .byte 0x57
5192
+ .uleb128 0x25
5193
+ .4byte .LASF246
5194
+ .byte 0x58
5195
+ .uleb128 0x25
5196
+ .4byte .LASF247
5197
+ .byte 0x59
5198
+ .uleb128 0x25
5199
+ .4byte .LASF248
5200
+ .byte 0x5a
5201
+ .uleb128 0x25
5202
+ .4byte .LASF249
5203
+ .byte 0x5b
5204
+ .uleb128 0x25
5205
+ .4byte .LASF250
5206
+ .byte 0x5c
5207
+ .uleb128 0x25
5208
+ .4byte .LASF251
5209
+ .byte 0x5d
5210
+ .uleb128 0x25
5211
+ .4byte .LASF252
5212
+ .byte 0x5e
5213
+ .uleb128 0x25
5214
+ .4byte .LASF253
5215
+ .byte 0x5f
5216
+ .uleb128 0x25
5217
+ .4byte .LASF254
5218
+ .byte 0x60
5219
+ .uleb128 0x25
5220
+ .4byte .LASF255
5221
+ .byte 0x61
5222
+ .uleb128 0x25
5223
+ .4byte .LASF256
5224
+ .byte 0x62
5225
+ .uleb128 0x26
5226
+ .4byte .LASF257
5227
+ .sleb128 -1
5228
+ .byte 0
5229
+ .uleb128 0x27
5230
+ .byte 0x4
5231
+ .4byte 0x7f
5232
+ .byte 0x23
5233
+ .byte 0xf6
5234
+ .4byte 0xc28
5235
+ .uleb128 0x25
5236
+ .4byte .LASF258
5237
+ .byte 0x5
5238
+ .byte 0
5239
+ .uleb128 0xd
5240
+ .4byte .LASF259
5241
+ .byte 0x40
5242
+ .byte 0x14
5243
+ .byte 0xc
5244
+ .4byte 0xca1
5245
+ .uleb128 0xe
5246
+ .4byte .LASF260
5247
+ .byte 0x14
5248
+ .byte 0x22
5249
+ .4byte 0x3b
5250
+ .byte 0
5251
+ .uleb128 0xf
5252
+ .string "tbu"
5253
+ .byte 0x14
5254
+ .byte 0x23
5255
+ .4byte 0x7f
5256
+ .byte 0x8
5257
+ .uleb128 0xf
5258
+ .string "tbl"
5259
+ .byte 0x14
5260
+ .byte 0x24
5261
+ .4byte 0x7f
5262
+ .byte 0xc
5263
+ .uleb128 0xe
5264
+ .4byte .LASF261
5265
+ .byte 0x14
5266
+ .byte 0x25
5267
+ .4byte 0x3b
5268
+ .byte 0x10
5269
+ .uleb128 0xe
5270
+ .4byte .LASF262
5271
+ .byte 0x14
5272
+ .byte 0x26
5273
+ .4byte 0x8d
5274
+ .byte 0x18
5275
+ .uleb128 0xe
5276
+ .4byte .LASF263
5277
+ .byte 0x14
5278
+ .byte 0x29
5279
+ .4byte 0x3b
5280
+ .byte 0x20
5281
+ .uleb128 0xe
5282
+ .4byte .LASF264
5283
+ .byte 0x14
5284
+ .byte 0x2a
5285
+ .4byte 0x3b
5286
+ .byte 0x28
5287
+ .uleb128 0xe
5288
+ .4byte .LASF265
5289
+ .byte 0x14
5290
+ .byte 0x2c
5291
+ .4byte 0x3b
5292
+ .byte 0x30
5293
+ .uleb128 0xe
5294
+ .4byte .LASF266
5295
+ .byte 0x14
5296
+ .byte 0x2d
5297
+ .4byte 0x3b
5298
+ .byte 0x38
5299
+ .byte 0
5300
+ .uleb128 0xd
5301
+ .4byte .LASF267
5302
+ .byte 0x18
5303
+ .byte 0x15
5304
+ .byte 0x22
5305
+ .4byte 0xce9
5306
+ .uleb128 0xe
5307
+ .4byte .LASF268
5308
+ .byte 0x15
5309
+ .byte 0x23
5310
+ .4byte 0xae
5311
+ .byte 0
5312
+ .uleb128 0xe
5313
+ .4byte .LASF269
5314
+ .byte 0x15
5315
+ .byte 0x24
5316
+ .4byte 0xae
5317
+ .byte 0x4
5318
+ .uleb128 0xf
5319
+ .string "id"
5320
+ .byte 0x15
5321
+ .byte 0x25
5322
+ .4byte 0xae
5323
+ .byte 0x8
5324
+ .uleb128 0xe
5325
+ .4byte .LASF270
5326
+ .byte 0x15
5327
+ .byte 0x26
5328
+ .4byte 0xae
5329
+ .byte 0xc
5330
+ .uleb128 0xe
5331
+ .4byte .LASF271
5332
+ .byte 0x15
5333
+ .byte 0x27
5334
+ .4byte 0x10b
5335
+ .byte 0x10
5336
+ .byte 0
5337
+ .uleb128 0x19
5338
+ .4byte .LASF272
5339
+ .2byte 0x1c0
5340
+ .byte 0x15
5341
+ .byte 0x2a
5342
+ .4byte 0xf12
5343
+ .uleb128 0xf
5344
+ .string "bd"
5345
+ .byte 0x15
5346
+ .byte 0x2b
5347
+ .4byte 0x97d
5348
+ .byte 0
5349
+ .uleb128 0xe
5350
+ .4byte .LASF42
5351
+ .byte 0x15
5352
+ .byte 0x2c
5353
+ .4byte 0x3b
5354
+ .byte 0x8
5355
+ .uleb128 0xe
5356
+ .4byte .LASF270
5357
+ .byte 0x15
5358
+ .byte 0x2d
5359
+ .4byte 0x7f
5360
+ .byte 0x10
5361
+ .uleb128 0xe
5362
+ .4byte .LASF273
5363
+ .byte 0x15
5364
+ .byte 0x2e
5365
+ .4byte 0x3b
5366
+ .byte 0x18
5367
+ .uleb128 0xe
5368
+ .4byte .LASF274
5369
+ .byte 0x15
5370
+ .byte 0x2f
5371
+ .4byte 0x3b
5372
+ .byte 0x20
5373
+ .uleb128 0xe
5374
+ .4byte .LASF275
5375
+ .byte 0x15
5376
+ .byte 0x31
5377
+ .4byte 0x3b
5378
+ .byte 0x28
5379
+ .uleb128 0xe
5380
+ .4byte .LASF276
5381
+ .byte 0x15
5382
+ .byte 0x32
5383
+ .4byte 0x3b
5384
+ .byte 0x30
5385
+ .uleb128 0xe
5386
+ .4byte .LASF277
5387
+ .byte 0x15
5388
+ .byte 0x3e
5389
+ .4byte 0x3b
5390
+ .byte 0x38
5391
+ .uleb128 0xe
5392
+ .4byte .LASF278
5393
+ .byte 0x15
5394
+ .byte 0x42
5395
+ .4byte 0x3b
5396
+ .byte 0x40
5397
+ .uleb128 0xe
5398
+ .4byte .LASF279
5399
+ .byte 0x15
5400
+ .byte 0x43
5401
+ .4byte 0x3b
5402
+ .byte 0x48
5403
+ .uleb128 0xe
5404
+ .4byte .LASF280
5405
+ .byte 0x15
5406
+ .byte 0x45
5407
+ .4byte 0x3b
5408
+ .byte 0x50
5409
+ .uleb128 0xe
5410
+ .4byte .LASF281
5411
+ .byte 0x15
5412
+ .byte 0x46
5413
+ .4byte 0x3b
5414
+ .byte 0x58
5415
+ .uleb128 0xe
5416
+ .4byte .LASF282
5417
+ .byte 0x15
5418
+ .byte 0x47
5419
+ .4byte 0x3b
5420
+ .byte 0x60
5421
+ .uleb128 0xe
5422
+ .4byte .LASF283
5423
+ .byte 0x15
5424
+ .byte 0x48
5425
+ .4byte 0xcf
5426
+ .byte 0x68
5427
+ .uleb128 0xe
5428
+ .4byte .LASF284
5429
+ .byte 0x15
5430
+ .byte 0x49
5431
+ .4byte 0x3b
5432
+ .byte 0x70
5433
+ .uleb128 0xe
5434
+ .4byte .LASF285
5435
+ .byte 0x15
5436
+ .byte 0x4a
5437
+ .4byte 0x3b
5438
+ .byte 0x78
5439
+ .uleb128 0xe
5440
+ .4byte .LASF286
5441
+ .byte 0x15
5442
+ .byte 0x4b
5443
+ .4byte 0x3b
5444
+ .byte 0x80
5445
+ .uleb128 0xe
5446
+ .4byte .LASF287
5447
+ .byte 0x15
5448
+ .byte 0x4c
5449
+ .4byte 0x3b
5450
+ .byte 0x88
5451
+ .uleb128 0xe
5452
+ .4byte .LASF288
5453
+ .byte 0x15
5454
+ .byte 0x4d
5455
+ .4byte 0xf12
5456
+ .byte 0x90
5457
+ .uleb128 0xe
5458
+ .4byte .LASF289
5459
+ .byte 0x15
5460
+ .byte 0x50
5461
+ .4byte 0x25f
5462
+ .byte 0x98
5463
+ .uleb128 0xe
5464
+ .4byte .LASF290
5465
+ .byte 0x15
5466
+ .byte 0x51
5467
+ .4byte 0x25f
5468
+ .byte 0xa0
5469
+ .uleb128 0xe
5470
+ .4byte .LASF291
5471
+ .byte 0x15
5472
+ .byte 0x52
5473
+ .4byte 0x292
5474
+ .byte 0xa8
5475
+ .uleb128 0xe
5476
+ .4byte .LASF292
5477
+ .byte 0x15
5478
+ .byte 0x57
5479
+ .4byte 0x265
5480
+ .byte 0xb8
5481
+ .uleb128 0xe
5482
+ .4byte .LASF293
5483
+ .byte 0x15
5484
+ .byte 0x58
5485
+ .4byte 0x137
5486
+ .byte 0xc0
5487
+ .uleb128 0xe
5488
+ .4byte .LASF294
5489
+ .byte 0x15
5490
+ .byte 0x59
5491
+ .4byte 0x3b
5492
+ .byte 0xc8
5493
+ .uleb128 0xe
5494
+ .4byte .LASF295
5495
+ .byte 0x15
5496
+ .byte 0x5b
5497
+ .4byte 0xf8a
5498
+ .byte 0xd0
5499
+ .uleb128 0xe
5500
+ .4byte .LASF296
5501
+ .byte 0x15
5502
+ .byte 0x5c
5503
+ .4byte 0xf8a
5504
+ .byte 0xd8
5505
+ .uleb128 0xe
5506
+ .4byte .LASF297
5507
+ .byte 0x15
5508
+ .byte 0x5e
5509
+ .4byte 0x265
5510
+ .byte 0xe0
5511
+ .uleb128 0xe
5512
+ .4byte .LASF298
5513
+ .byte 0x15
5514
+ .byte 0x5f
5515
+ .4byte 0x265
5516
+ .byte 0xe8
5517
+ .uleb128 0xf
5518
+ .string "jt"
5519
+ .byte 0x15
5520
+ .byte 0x60
5521
+ .4byte 0xf95
5522
+ .byte 0xf0
5523
+ .uleb128 0xe
5524
+ .4byte .LASF299
5525
+ .byte 0x15
5526
+ .byte 0x61
5527
+ .4byte 0xf9b
5528
+ .byte 0xf8
5529
+ .uleb128 0x15
5530
+ .4byte .LASF300
5531
+ .byte 0x15
5532
+ .byte 0x6b
5533
+ .4byte 0x7f
5534
+ .2byte 0x118
5535
+ .uleb128 0x15
5536
+ .4byte .LASF301
5537
+ .byte 0x15
5538
+ .byte 0x6c
5539
+ .4byte 0x7f
5540
+ .2byte 0x11c
5541
+ .uleb128 0x15
5542
+ .4byte .LASF302
5543
+ .byte 0x15
5544
+ .byte 0x6e
5545
+ .4byte 0x3b
5546
+ .2byte 0x120
5547
+ .uleb128 0x15
5548
+ .4byte .LASF303
5549
+ .byte 0x15
5550
+ .byte 0x6f
5551
+ .4byte 0x3b
5552
+ .2byte 0x128
5553
+ .uleb128 0x15
5554
+ .4byte .LASF304
5555
+ .byte 0x15
5556
+ .byte 0x70
5557
+ .4byte 0x3b
5558
+ .2byte 0x130
5559
+ .uleb128 0x15
5560
+ .4byte .LASF305
5561
+ .byte 0x15
5562
+ .byte 0x79
5563
+ .4byte 0x25f
5564
+ .2byte 0x138
5565
+ .uleb128 0x15
5566
+ .4byte .LASF127
5567
+ .byte 0x15
5568
+ .byte 0x7a
5569
+ .4byte 0xc28
5570
+ .2byte 0x140
5571
+ .uleb128 0x15
5572
+ .4byte .LASF306
5573
+ .byte 0x15
5574
+ .byte 0x80
5575
+ .4byte 0x10b
5576
+ .2byte 0x180
5577
+ .uleb128 0x15
5578
+ .4byte .LASF307
5579
+ .byte 0x15
5580
+ .byte 0x81
5581
+ .4byte 0x10b
5582
+ .2byte 0x188
5583
+ .uleb128 0x15
5584
+ .4byte .LASF308
5585
+ .byte 0x15
5586
+ .byte 0x87
5587
+ .4byte 0xc4
5588
+ .2byte 0x190
5589
+ .uleb128 0x15
5590
+ .4byte .LASF309
5591
+ .byte 0x15
5592
+ .byte 0x8c
5593
+ .4byte 0xca1
5594
+ .2byte 0x198
5595
+ .uleb128 0x15
5596
+ .4byte .LASF310
5597
+ .byte 0x15
5598
+ .byte 0x8d
5599
+ .4byte 0x10b
5600
+ .2byte 0x1b0
5601
+ .uleb128 0x15
5602
+ .4byte .LASF311
5603
+ .byte 0x15
5604
+ .byte 0x8e
5605
+ .4byte 0x54
5606
+ .2byte 0x1b8
5607
+ .byte 0
5608
+ .uleb128 0x8
5609
+ .byte 0x8
5610
+ .4byte 0xce9
5611
+ .uleb128 0xd
5612
+ .4byte .LASF312
5613
+ .byte 0x40
5614
+ .byte 0x16
5615
+ .byte 0x2c
5616
+ .4byte 0xf85
5617
+ .uleb128 0xe
5618
+ .4byte .LASF28
5619
+ .byte 0x16
5620
+ .byte 0x2d
5621
+ .4byte 0xe1
5622
+ .byte 0
5623
+ .uleb128 0xe
5624
+ .4byte .LASF126
5625
+ .byte 0x16
5626
+ .byte 0x2e
5627
+ .4byte 0xe1
5628
+ .byte 0x8
5629
+ .uleb128 0xe
5630
+ .4byte .LASF313
5631
+ .byte 0x16
5632
+ .byte 0x2f
5633
+ .4byte 0x12be
5634
+ .byte 0x10
5635
+ .uleb128 0xe
5636
+ .4byte .LASF314
5637
+ .byte 0x16
5638
+ .byte 0x30
5639
+ .4byte 0xe1
5640
+ .byte 0x18
5641
+ .uleb128 0xe
5642
+ .4byte .LASF315
5643
+ .byte 0x16
5644
+ .byte 0x32
5645
+ .4byte 0x1306
5646
+ .byte 0x20
5647
+ .uleb128 0xe
5648
+ .4byte .LASF34
5649
+ .byte 0x16
5650
+ .byte 0x33
5651
+ .4byte 0xf8a
5652
+ .byte 0x28
5653
+ .uleb128 0xe
5654
+ .4byte .LASF316
5655
+ .byte 0x16
5656
+ .byte 0x34
5657
+ .4byte 0xf8a
5658
+ .byte 0x30
5659
+ .uleb128 0xe
5660
+ .4byte .LASF317
5661
+ .byte 0x16
5662
+ .byte 0x35
5663
+ .4byte 0xf8a
5664
+ .byte 0x38
5665
+ .byte 0
5666
+ .uleb128 0x7
5667
+ .4byte 0xf18
5668
+ .uleb128 0x8
5669
+ .byte 0x8
5670
+ .4byte 0xf18
5671
+ .uleb128 0x18
5672
+ .4byte .LASF319
5673
+ .uleb128 0x8
5674
+ .byte 0x8
5675
+ .4byte 0xf90
5676
+ .uleb128 0xa
5677
+ .4byte 0xe7
5678
+ .4byte 0xfab
5679
+ .uleb128 0x11
5680
+ .4byte 0xda
5681
+ .byte 0x1f
5682
+ .byte 0
5683
+ .uleb128 0x2
5684
+ .4byte .LASF320
5685
+ .byte 0x15
5686
+ .byte 0x9b
5687
+ .4byte 0xce9
5688
+ .uleb128 0x28
5689
+ .4byte 0xfab
5690
+ .uleb128 0x4
5691
+ .4byte .LASF321
5692
+ .byte 0x2
5693
+ .byte 0xad
5694
+ .4byte 0x10b
5695
+ .uleb128 0xa
5696
+ .4byte 0x94
5697
+ .4byte 0xfd1
5698
+ .uleb128 0xb
5699
+ .byte 0
5700
+ .uleb128 0x4
5701
+ .4byte .LASF322
5702
+ .byte 0x2
5703
+ .byte 0xaf
5704
+ .4byte 0xfc6
5705
+ .uleb128 0x4
5706
+ .4byte .LASF323
5707
+ .byte 0x2
5708
+ .byte 0xb0
5709
+ .4byte 0xfc6
5710
+ .uleb128 0x4
5711
+ .4byte .LASF324
5712
+ .byte 0x2
5713
+ .byte 0xfe
5714
+ .4byte 0x10b
5715
+ .uleb128 0x4
5716
+ .4byte .LASF325
5717
+ .byte 0x2
5718
+ .byte 0xff
5719
+ .4byte 0x10b
5720
+ .uleb128 0xc
5721
+ .4byte .LASF326
5722
+ .byte 0x2
5723
+ .2byte 0x100
5724
+ .4byte 0x10b
5725
+ .uleb128 0xd
5726
+ .4byte .LASF327
5727
+ .byte 0x4
5728
+ .byte 0x17
5729
+ .byte 0x2e
5730
+ .4byte 0x1022
5731
+ .uleb128 0xe
5732
+ .4byte .LASF328
5733
+ .byte 0x17
5734
+ .byte 0x2f
5735
+ .4byte 0x12c
5736
+ .byte 0
5737
+ .byte 0
5738
+ .uleb128 0x8
5739
+ .byte 0x8
5740
+ .4byte 0x29
5741
+ .uleb128 0x12
5742
+ .4byte 0x54
5743
+ .4byte 0x1037
5744
+ .uleb128 0x13
5745
+ .4byte 0x25f
5746
+ .byte 0
5747
+ .uleb128 0x8
5748
+ .byte 0x8
5749
+ .4byte 0x1028
5750
+ .uleb128 0xa
5751
+ .4byte 0x94
5752
+ .4byte 0x104d
5753
+ .uleb128 0x11
5754
+ .4byte 0xda
5755
+ .byte 0x5
5756
+ .byte 0
5757
+ .uleb128 0xc
5758
+ .4byte .LASF329
5759
+ .byte 0x17
5760
+ .2byte 0x1fd
5761
+ .4byte 0x1009
5762
+ .uleb128 0xc
5763
+ .4byte .LASF330
5764
+ .byte 0x17
5765
+ .2byte 0x1fe
5766
+ .4byte 0x1009
5767
+ .uleb128 0xc
5768
+ .4byte .LASF331
5769
+ .byte 0x17
5770
+ .2byte 0x200
5771
+ .4byte 0x1009
5772
+ .uleb128 0xc
5773
+ .4byte .LASF332
5774
+ .byte 0x17
5775
+ .2byte 0x205
5776
+ .4byte 0xf9b
5777
+ .uleb128 0xc
5778
+ .4byte .LASF333
5779
+ .byte 0x17
5780
+ .2byte 0x206
5781
+ .4byte 0xf9b
5782
+ .uleb128 0xa
5783
+ .4byte 0xe7
5784
+ .4byte 0x1099
5785
+ .uleb128 0x11
5786
+ .4byte 0xda
5787
+ .byte 0x3f
5788
+ .byte 0
5789
+ .uleb128 0xc
5790
+ .4byte .LASF334
5791
+ .byte 0x17
5792
+ .2byte 0x207
5793
+ .4byte 0x1089
5794
+ .uleb128 0xc
5795
+ .4byte .LASF335
5796
+ .byte 0x17
5797
+ .2byte 0x209
5798
+ .4byte 0x103d
5799
+ .uleb128 0xc
5800
+ .4byte .LASF336
5801
+ .byte 0x17
5802
+ .2byte 0x20a
5803
+ .4byte 0x103d
5804
+ .uleb128 0xc
5805
+ .4byte .LASF337
5806
+ .byte 0x17
5807
+ .2byte 0x20b
5808
+ .4byte 0x1009
5809
+ .uleb128 0xc
5810
+ .4byte .LASF338
5811
+ .byte 0x17
5812
+ .2byte 0x20c
5813
+ .4byte 0x1009
5814
+ .uleb128 0xc
5815
+ .4byte .LASF339
5816
+ .byte 0x17
5817
+ .2byte 0x20d
5818
+ .4byte 0x1022
5819
+ .uleb128 0xa
5820
+ .4byte 0x1022
5821
+ .4byte 0x10f1
5822
+ .uleb128 0x11
5823
+ .4byte 0xda
5824
+ .byte 0x3
5825
+ .byte 0
5826
+ .uleb128 0xc
5827
+ .4byte .LASF340
5828
+ .byte 0x17
5829
+ .2byte 0x20e
5830
+ .4byte 0x10e1
5831
+ .uleb128 0xc
5832
+ .4byte .LASF341
5833
+ .byte 0x17
5834
+ .2byte 0x20f
5835
+ .4byte 0x1022
5836
+ .uleb128 0xc
5837
+ .4byte .LASF342
5838
+ .byte 0x17
5839
+ .2byte 0x210
5840
+ .4byte 0x54
5841
+ .uleb128 0xa
5842
+ .4byte 0x9e
5843
+ .4byte 0x1125
5844
+ .uleb128 0x11
5845
+ .4byte 0xda
5846
+ .byte 0x5
5847
+ .byte 0
5848
+ .uleb128 0x7
5849
+ .4byte 0x1115
5850
+ .uleb128 0xc
5851
+ .4byte .LASF343
5852
+ .byte 0x17
5853
+ .2byte 0x211
5854
+ .4byte 0x1125
5855
+ .uleb128 0xc
5856
+ .4byte .LASF344
5857
+ .byte 0x17
5858
+ .2byte 0x212
5859
+ .4byte 0x1125
5860
+ .uleb128 0xc
5861
+ .4byte .LASF345
5862
+ .byte 0x17
5863
+ .2byte 0x216
5864
+ .4byte 0x100
5865
+ .uleb128 0xc
5866
+ .4byte .LASF346
5867
+ .byte 0x17
5868
+ .2byte 0x217
5869
+ .4byte 0x100
5870
+ .uleb128 0xc
5871
+ .4byte .LASF347
5872
+ .byte 0x17
5873
+ .2byte 0x219
5874
+ .4byte 0x54
5875
+ .uleb128 0xc
5876
+ .4byte .LASF348
5877
+ .byte 0x17
5878
+ .2byte 0x220
5879
+ .4byte 0x99b
5880
+ .uleb128 0xc
5881
+ .4byte .LASF349
5882
+ .byte 0x17
5883
+ .2byte 0x222
5884
+ .4byte 0xae
5885
+ .uleb128 0xc
5886
+ .4byte .LASF350
5887
+ .byte 0x17
5888
+ .2byte 0x224
5889
+ .4byte 0xae
5890
+ .uleb128 0xc
5891
+ .4byte .LASF351
5892
+ .byte 0x17
5893
+ .2byte 0x230
5894
+ .4byte 0x1009
5895
+ .uleb128 0x29
5896
+ .4byte .LASF353
5897
+ .byte 0x4
5898
+ .4byte 0x7f
5899
+ .byte 0x17
5900
+ .2byte 0x286
5901
+ .4byte 0x11c0
5902
+ .uleb128 0x25
5903
+ .4byte .LASF354
5904
+ .byte 0
5905
+ .uleb128 0x25
5906
+ .4byte .LASF355
5907
+ .byte 0x1
5908
+ .uleb128 0x25
5909
+ .4byte .LASF356
5910
+ .byte 0x2
5911
+ .uleb128 0x25
5912
+ .4byte .LASF357
5913
+ .byte 0x3
5914
+ .byte 0
5915
+ .uleb128 0xc
5916
+ .4byte .LASF358
5917
+ .byte 0x17
5918
+ .2byte 0x28c
5919
+ .4byte 0x1196
5920
+ .uleb128 0x8
5921
+ .byte 0x8
5922
+ .4byte 0x94
5923
+ .uleb128 0x8
5924
+ .byte 0x8
5925
+ .4byte 0xa3
5926
+ .uleb128 0x8
5927
+ .byte 0x8
5928
+ .4byte 0xae
5929
+ .uleb128 0xd
5930
+ .4byte .LASF27
5931
+ .byte 0x78
5932
+ .byte 0x8
5933
+ .byte 0xf1
5934
+ .4byte 0x12b9
5935
+ .uleb128 0xe
5936
+ .4byte .LASF28
5937
+ .byte 0x8
5938
+ .byte 0xf2
5939
+ .4byte 0xfa
5940
+ .byte 0
5941
+ .uleb128 0xf
5942
+ .string "id"
5943
+ .byte 0x8
5944
+ .byte 0xf3
5945
+ .4byte 0x9ac
5946
+ .byte 0x8
5947
+ .uleb128 0xe
5948
+ .4byte .LASF359
5949
+ .byte 0x8
5950
+ .byte 0xf4
5951
+ .4byte 0x141c
5952
+ .byte 0x10
5953
+ .uleb128 0xe
5954
+ .4byte .LASF360
5955
+ .byte 0x8
5956
+ .byte 0xf5
5957
+ .4byte 0x1037
5958
+ .byte 0x18
5959
+ .uleb128 0xe
5960
+ .4byte .LASF361
5961
+ .byte 0x8
5962
+ .byte 0xf6
5963
+ .4byte 0x1037
5964
+ .byte 0x20
5965
+ .uleb128 0xe
5966
+ .4byte .LASF362
5967
+ .byte 0x8
5968
+ .byte 0xf7
5969
+ .4byte 0x1037
5970
+ .byte 0x28
5971
+ .uleb128 0xe
5972
+ .4byte .LASF363
5973
+ .byte 0x8
5974
+ .byte 0xf8
5975
+ .4byte 0x1037
5976
+ .byte 0x30
5977
+ .uleb128 0xe
5978
+ .4byte .LASF364
5979
+ .byte 0x8
5980
+ .byte 0xf9
5981
+ .4byte 0x1037
5982
+ .byte 0x38
5983
+ .uleb128 0xe
5984
+ .4byte .LASF365
5985
+ .byte 0x8
5986
+ .byte 0xfa
5987
+ .4byte 0x1037
5988
+ .byte 0x40
5989
+ .uleb128 0xe
5990
+ .4byte .LASF366
5991
+ .byte 0x8
5992
+ .byte 0xfb
5993
+ .4byte 0x1037
5994
+ .byte 0x48
5995
+ .uleb128 0xe
5996
+ .4byte .LASF367
5997
+ .byte 0x8
5998
+ .byte 0xfc
5999
+ .4byte 0x1037
6000
+ .byte 0x50
6001
+ .uleb128 0xe
6002
+ .4byte .LASF368
6003
+ .byte 0x8
6004
+ .byte 0xfd
6005
+ .4byte 0x54
6006
+ .byte 0x58
6007
+ .uleb128 0xe
6008
+ .4byte .LASF369
6009
+ .byte 0x8
6010
+ .byte 0xfe
6011
+ .4byte 0x54
6012
+ .byte 0x5c
6013
+ .uleb128 0xe
6014
+ .4byte .LASF370
6015
+ .byte 0x8
6016
+ .byte 0xff
6017
+ .4byte 0x54
6018
+ .byte 0x60
6019
+ .uleb128 0x1e
6020
+ .4byte .LASF371
6021
+ .byte 0x8
6022
+ .2byte 0x100
6023
+ .4byte 0x54
6024
+ .byte 0x64
6025
+ .uleb128 0x20
6026
+ .string "ops"
6027
+ .byte 0x8
6028
+ .2byte 0x101
6029
+ .4byte 0x265
6030
+ .byte 0x68
6031
+ .uleb128 0x1e
6032
+ .4byte .LASF42
6033
+ .byte 0x8
6034
+ .2byte 0x102
6035
+ .4byte 0x121
6036
+ .byte 0x70
6037
+ .byte 0
6038
+ .uleb128 0x7
6039
+ .4byte 0x11de
6040
+ .uleb128 0x2
6041
+ .4byte .LASF313
6042
+ .byte 0x16
6043
+ .byte 0xf
6044
+ .4byte 0xae
6045
+ .uleb128 0xd
6046
+ .4byte .LASF372
6047
+ .byte 0x20
6048
+ .byte 0x16
6049
+ .byte 0x19
6050
+ .4byte 0x1306
6051
+ .uleb128 0xe
6052
+ .4byte .LASF28
6053
+ .byte 0x16
6054
+ .byte 0x1a
6055
+ .4byte 0xfa
6056
+ .byte 0
6057
+ .uleb128 0xe
6058
+ .4byte .LASF373
6059
+ .byte 0x16
6060
+ .byte 0x1b
6061
+ .4byte 0x54
6062
+ .byte 0x8
6063
+ .uleb128 0xe
6064
+ .4byte .LASF374
6065
+ .byte 0x16
6066
+ .byte 0x1c
6067
+ .4byte 0x137
6068
+ .byte 0x10
6069
+ .uleb128 0xe
6070
+ .4byte .LASF47
6071
+ .byte 0x16
6072
+ .byte 0x1d
6073
+ .4byte 0x1306
6074
+ .byte 0x18
6075
+ .byte 0
6076
+ .uleb128 0x8
6077
+ .byte 0x8
6078
+ .4byte 0x12c9
6079
+ .uleb128 0x2a
6080
+ .string "gd"
6081
+ .byte 0x16
6082
+ .byte 0x57
6083
+ .4byte 0x1316
6084
+ .uleb128 0x8
6085
+ .byte 0x8
6086
+ .4byte 0xfb6
6087
+ .uleb128 0x2b
6088
+ .4byte .LASF462
6089
+ .byte 0x8
6090
+ .byte 0x19
6091
+ .byte 0x33
6092
+ .4byte 0x133e
6093
+ .uleb128 0x2c
6094
+ .string "np"
6095
+ .byte 0x19
6096
+ .byte 0x34
6097
+ .4byte 0x133e
6098
+ .uleb128 0x2d
6099
+ .4byte .LASF375
6100
+ .byte 0x19
6101
+ .byte 0x35
6102
+ .4byte 0xf3
6103
+ .byte 0
6104
+ .uleb128 0x8
6105
+ .byte 0x8
6106
+ .4byte 0xf85
6107
+ .uleb128 0x2
6108
+ .4byte .LASF376
6109
+ .byte 0x19
6110
+ .byte 0x36
6111
+ .4byte 0x131c
6112
+ .uleb128 0xc
6113
+ .4byte .LASF377
6114
+ .byte 0x1a
6115
+ .2byte 0x3ba
6116
+ .4byte 0x10b
6117
+ .uleb128 0xc
6118
+ .4byte .LASF378
6119
+ .byte 0x1a
6120
+ .2byte 0x3bb
6121
+ .4byte 0x10b
6122
+ .uleb128 0xc
6123
+ .4byte .LASF379
6124
+ .byte 0x1a
6125
+ .2byte 0x3bc
6126
+ .4byte 0x10b
6127
+ .uleb128 0xd
6128
+ .4byte .LASF380
6129
+ .byte 0x4
6130
+ .byte 0x1b
6131
+ .byte 0xd
6132
+ .4byte 0x138c
6133
+ .uleb128 0xf
6134
+ .string "pid"
6135
+ .byte 0x1b
6136
+ .byte 0xe
6137
+ .4byte 0x54
6138
+ .byte 0
6139
+ .byte 0
6140
+ .uleb128 0x4
6141
+ .4byte .LASF381
6142
+ .byte 0x1b
6143
+ .byte 0x11
6144
+ .4byte 0x1397
6145
+ .uleb128 0x8
6146
+ .byte 0x8
6147
+ .4byte 0x1373
6148
+ .uleb128 0x8
6149
+ .byte 0x8
6150
+ .4byte 0x12b9
6151
+ .uleb128 0xd
6152
+ .4byte .LASF36
6153
+ .byte 0x38
6154
+ .byte 0x1c
6155
+ .byte 0x23
6156
+ .4byte 0x13ec
6157
+ .uleb128 0xe
6158
+ .4byte .LASF35
6159
+ .byte 0x1c
6160
+ .byte 0x24
6161
+ .4byte 0x137
6162
+ .byte 0
6163
+ .uleb128 0xe
6164
+ .4byte .LASF382
6165
+ .byte 0x1c
6166
+ .byte 0x25
6167
+ .4byte 0x1506
6168
+ .byte 0x8
6169
+ .uleb128 0xe
6170
+ .4byte .LASF383
6171
+ .byte 0x1c
6172
+ .byte 0x26
6173
+ .4byte 0x292
6174
+ .byte 0x10
6175
+ .uleb128 0xe
6176
+ .4byte .LASF41
6177
+ .byte 0x1c
6178
+ .byte 0x27
6179
+ .4byte 0x292
6180
+ .byte 0x20
6181
+ .uleb128 0xe
6182
+ .4byte .LASF384
6183
+ .byte 0x1c
6184
+ .byte 0x29
6185
+ .4byte 0x2b7
6186
+ .byte 0x30
6187
+ .byte 0
6188
+ .uleb128 0x8
6189
+ .byte 0x8
6190
+ .4byte 0x13a3
6191
+ .uleb128 0xd
6192
+ .4byte .LASF385
6193
+ .byte 0x10
6194
+ .byte 0x8
6195
+ .byte 0xb8
6196
+ .4byte 0x1417
6197
+ .uleb128 0xe
6198
+ .4byte .LASF386
6199
+ .byte 0x8
6200
+ .byte 0xb9
6201
+ .4byte 0xe1
6202
+ .byte 0
6203
+ .uleb128 0xe
6204
+ .4byte .LASF387
6205
+ .byte 0x8
6206
+ .byte 0xba
6207
+ .4byte 0x10b
6208
+ .byte 0x8
6209
+ .byte 0
6210
+ .uleb128 0x7
6211
+ .4byte 0x13f2
6212
+ .uleb128 0x8
6213
+ .byte 0x8
6214
+ .4byte 0x1417
6215
+ .uleb128 0xd
6216
+ .4byte .LASF388
6217
+ .byte 0x80
6218
+ .byte 0x1c
6219
+ .byte 0x57
6220
+ .4byte 0x1506
6221
+ .uleb128 0xe
6222
+ .4byte .LASF28
6223
+ .byte 0x1c
6224
+ .byte 0x58
6225
+ .4byte 0xe1
6226
+ .byte 0
6227
+ .uleb128 0xf
6228
+ .string "id"
6229
+ .byte 0x1c
6230
+ .byte 0x59
6231
+ .4byte 0x9ac
6232
+ .byte 0x8
6233
+ .uleb128 0xe
6234
+ .4byte .LASF389
6235
+ .byte 0x1c
6236
+ .byte 0x5a
6237
+ .4byte 0x1037
6238
+ .byte 0x10
6239
+ .uleb128 0xe
6240
+ .4byte .LASF390
6241
+ .byte 0x1c
6242
+ .byte 0x5b
6243
+ .4byte 0x1037
6244
+ .byte 0x18
6245
+ .uleb128 0xe
6246
+ .4byte .LASF391
6247
+ .byte 0x1c
6248
+ .byte 0x5c
6249
+ .4byte 0x1037
6250
+ .byte 0x20
6251
+ .uleb128 0xe
6252
+ .4byte .LASF392
6253
+ .byte 0x1c
6254
+ .byte 0x5d
6255
+ .4byte 0x1037
6256
+ .byte 0x28
6257
+ .uleb128 0xe
6258
+ .4byte .LASF393
6259
+ .byte 0x1c
6260
+ .byte 0x5e
6261
+ .4byte 0x1037
6262
+ .byte 0x30
6263
+ .uleb128 0xe
6264
+ .4byte .LASF365
6265
+ .byte 0x1c
6266
+ .byte 0x5f
6267
+ .4byte 0x1037
6268
+ .byte 0x38
6269
+ .uleb128 0xe
6270
+ .4byte .LASF366
6271
+ .byte 0x1c
6272
+ .byte 0x60
6273
+ .4byte 0x1037
6274
+ .byte 0x40
6275
+ .uleb128 0xe
6276
+ .4byte .LASF394
6277
+ .byte 0x1c
6278
+ .byte 0x61
6279
+ .4byte 0x151b
6280
+ .byte 0x48
6281
+ .uleb128 0xe
6282
+ .4byte .LASF395
6283
+ .byte 0x1c
6284
+ .byte 0x62
6285
+ .4byte 0x151b
6286
+ .byte 0x50
6287
+ .uleb128 0xe
6288
+ .4byte .LASF368
6289
+ .byte 0x1c
6290
+ .byte 0x63
6291
+ .4byte 0x54
6292
+ .byte 0x58
6293
+ .uleb128 0xe
6294
+ .4byte .LASF396
6295
+ .byte 0x1c
6296
+ .byte 0x64
6297
+ .4byte 0x54
6298
+ .byte 0x5c
6299
+ .uleb128 0xe
6300
+ .4byte .LASF397
6301
+ .byte 0x1c
6302
+ .byte 0x65
6303
+ .4byte 0x54
6304
+ .byte 0x60
6305
+ .uleb128 0xe
6306
+ .4byte .LASF370
6307
+ .byte 0x1c
6308
+ .byte 0x66
6309
+ .4byte 0x54
6310
+ .byte 0x64
6311
+ .uleb128 0xe
6312
+ .4byte .LASF371
6313
+ .byte 0x1c
6314
+ .byte 0x67
6315
+ .4byte 0x54
6316
+ .byte 0x68
6317
+ .uleb128 0xf
6318
+ .string "ops"
6319
+ .byte 0x1c
6320
+ .byte 0x68
6321
+ .4byte 0x265
6322
+ .byte 0x70
6323
+ .uleb128 0xe
6324
+ .4byte .LASF42
6325
+ .byte 0x1c
6326
+ .byte 0x69
6327
+ .4byte 0x121
6328
+ .byte 0x78
6329
+ .byte 0
6330
+ .uleb128 0x8
6331
+ .byte 0x8
6332
+ .4byte 0x1422
6333
+ .uleb128 0x12
6334
+ .4byte 0x54
6335
+ .4byte 0x151b
6336
+ .uleb128 0x13
6337
+ .4byte 0x13ec
6338
+ .byte 0
6339
+ .uleb128 0x8
6340
+ .byte 0x8
6341
+ .4byte 0x150c
6342
+ .uleb128 0x4
6343
+ .4byte .LASF398
6344
+ .byte 0x1d
6345
+ .byte 0x49
6346
+ .4byte 0x7f
6347
+ .uleb128 0x24
6348
+ .4byte .LASF399
6349
+ .byte 0x4
6350
+ .4byte 0x7f
6351
+ .byte 0x1e
6352
+ .byte 0x15
6353
+ .4byte 0x155b
6354
+ .uleb128 0x25
6355
+ .4byte .LASF400
6356
+ .byte 0x1
6357
+ .uleb128 0x25
6358
+ .4byte .LASF401
6359
+ .byte 0x2
6360
+ .uleb128 0x25
6361
+ .4byte .LASF402
6362
+ .byte 0x4
6363
+ .uleb128 0x25
6364
+ .4byte .LASF403
6365
+ .byte 0x8
6366
+ .uleb128 0x25
6367
+ .4byte .LASF404
6368
+ .byte 0x10
6369
+ .byte 0
6370
+ .uleb128 0xd
6371
+ .4byte .LASF405
6372
+ .byte 0x20
6373
+ .byte 0x1e
6374
+ .byte 0x61
6375
+ .4byte 0x1598
6376
+ .uleb128 0xe
6377
+ .4byte .LASF406
6378
+ .byte 0x1e
6379
+ .byte 0x6b
6380
+ .4byte 0x15bb
6381
+ .byte 0
6382
+ .uleb128 0xe
6383
+ .4byte .LASF407
6384
+ .byte 0x1e
6385
+ .byte 0x75
6386
+ .4byte 0x15df
6387
+ .byte 0x8
6388
+ .uleb128 0xe
6389
+ .4byte .LASF408
6390
+ .byte 0x1e
6391
+ .byte 0x7f
6392
+ .4byte 0x15fe
6393
+ .byte 0x10
6394
+ .uleb128 0xe
6395
+ .4byte .LASF409
6396
+ .byte 0x1e
6397
+ .byte 0x8c
6398
+ .4byte 0x162c
6399
+ .byte 0x18
6400
+ .byte 0
6401
+ .uleb128 0x7
6402
+ .4byte 0x155b
6403
+ .uleb128 0x12
6404
+ .4byte 0x54
6405
+ .4byte 0x15bb
6406
+ .uleb128 0x13
6407
+ .4byte 0x25f
6408
+ .uleb128 0x13
6409
+ .4byte 0x54
6410
+ .uleb128 0x13
6411
+ .4byte 0x137
6412
+ .uleb128 0x13
6413
+ .4byte 0x54
6414
+ .byte 0
6415
+ .uleb128 0x8
6416
+ .byte 0x8
6417
+ .4byte 0x159d
6418
+ .uleb128 0x12
6419
+ .4byte 0x54
6420
+ .4byte 0x15df
6421
+ .uleb128 0x13
6422
+ .4byte 0x25f
6423
+ .uleb128 0x13
6424
+ .4byte 0x54
6425
+ .uleb128 0x13
6426
+ .4byte 0x265
6427
+ .uleb128 0x13
6428
+ .4byte 0x54
6429
+ .byte 0
6430
+ .uleb128 0x8
6431
+ .byte 0x8
6432
+ .4byte 0x15c1
6433
+ .uleb128 0x12
6434
+ .4byte 0x54
6435
+ .4byte 0x15fe
6436
+ .uleb128 0x13
6437
+ .4byte 0x25f
6438
+ .uleb128 0x13
6439
+ .4byte 0x3b
6440
+ .uleb128 0x13
6441
+ .4byte 0x137
6442
+ .byte 0
6443
+ .uleb128 0x8
6444
+ .byte 0x8
6445
+ .4byte 0x15e5
6446
+ .uleb128 0x12
6447
+ .4byte 0x54
6448
+ .4byte 0x162c
6449
+ .uleb128 0x13
6450
+ .4byte 0x25f
6451
+ .uleb128 0x13
6452
+ .4byte 0x54
6453
+ .uleb128 0x13
6454
+ .4byte 0x137
6455
+ .uleb128 0x13
6456
+ .4byte 0x54
6457
+ .uleb128 0x13
6458
+ .4byte 0x137
6459
+ .uleb128 0x13
6460
+ .4byte 0x54
6461
+ .byte 0
6462
+ .uleb128 0x8
6463
+ .byte 0x8
6464
+ .4byte 0x1604
6465
+ .uleb128 0xd
6466
+ .4byte .LASF410
6467
+ .byte 0x20
6468
+ .byte 0x1f
6469
+ .byte 0x5e
6470
+ .4byte 0x166f
6471
+ .uleb128 0xe
6472
+ .4byte .LASF60
6473
+ .byte 0x1f
6474
+ .byte 0x5f
6475
+ .4byte 0x137
6476
+ .byte 0
6477
+ .uleb128 0xe
6478
+ .4byte .LASF411
6479
+ .byte 0x1f
6480
+ .byte 0x60
6481
+ .4byte 0x3b
6482
+ .byte 0x8
6483
+ .uleb128 0xe
6484
+ .4byte .LASF412
6485
+ .byte 0x1f
6486
+ .byte 0x61
6487
+ .4byte 0x3b
6488
+ .byte 0x10
6489
+ .uleb128 0xe
6490
+ .4byte .LASF413
6491
+ .byte 0x1f
6492
+ .byte 0x62
6493
+ .4byte 0x3b
6494
+ .byte 0x18
6495
+ .byte 0
6496
+ .uleb128 0xd
6497
+ .4byte .LASF414
6498
+ .byte 0x20
6499
+ .byte 0x1
6500
+ .byte 0xf
6501
+ .4byte 0x16ac
6502
+ .uleb128 0xe
6503
+ .4byte .LASF406
6504
+ .byte 0x1
6505
+ .byte 0x10
6506
+ .4byte 0x15bb
6507
+ .byte 0
6508
+ .uleb128 0xe
6509
+ .4byte .LASF407
6510
+ .byte 0x1
6511
+ .byte 0x11
6512
+ .4byte 0x15df
6513
+ .byte 0x8
6514
+ .uleb128 0xe
6515
+ .4byte .LASF415
6516
+ .byte 0x1
6517
+ .byte 0x12
6518
+ .4byte 0x16cb
6519
+ .byte 0x10
6520
+ .uleb128 0xe
6521
+ .4byte .LASF416
6522
+ .byte 0x1
6523
+ .byte 0x15
6524
+ .4byte 0x16cb
6525
+ .byte 0x18
6526
+ .byte 0
6527
+ .uleb128 0x7
6528
+ .4byte 0x166f
6529
+ .uleb128 0x2e
6530
+ .4byte 0x16cb
6531
+ .uleb128 0x13
6532
+ .4byte 0x11d8
6533
+ .uleb128 0x13
6534
+ .4byte 0x11d8
6535
+ .uleb128 0x13
6536
+ .4byte 0x3b
6537
+ .uleb128 0x13
6538
+ .4byte 0x54
6539
+ .byte 0
6540
+ .uleb128 0x8
6541
+ .byte 0x8
6542
+ .4byte 0x16b1
6543
+ .uleb128 0x2f
6544
+ .4byte .LASF417
6545
+ .byte 0x1
6546
+ .2byte 0x2c7
6547
+ .4byte 0x1598
6548
+ .uleb128 0x9
6549
+ .byte 0x3
6550
+ .8byte rockchip_secure_otp_ops
6551
+ .uleb128 0x2f
6552
+ .4byte .LASF418
6553
+ .byte 0x1
6554
+ .2byte 0x2dc
6555
+ .4byte 0x16ac
6556
+ .uleb128 0x9
6557
+ .byte 0x3
6558
+ .8byte rk3562_data
6559
+ .uleb128 0xa
6560
+ .4byte 0x1417
6561
+ .4byte 0x170d
6562
+ .uleb128 0x11
6563
+ .4byte 0xda
6564
+ .byte 0x1
6565
+ .byte 0
6566
+ .uleb128 0x7
6567
+ .4byte 0x16fd
6568
+ .uleb128 0x2f
6569
+ .4byte .LASF419
6570
+ .byte 0x1
6571
+ .2byte 0x2e3
6572
+ .4byte 0x170d
6573
+ .uleb128 0x9
6574
+ .byte 0x3
6575
+ .8byte rockchip_otp_ids
6576
+ .uleb128 0x30
6577
+ .4byte .LASF420
6578
+ .byte 0x1
6579
+ .2byte 0x2eb
6580
+ .4byte 0x11de
6581
+ .uleb128 0x9
6582
+ .byte 0x3
6583
+ .8byte _u_boot_list_2_driver_2_rockchip_secure_otp
6584
+ .uleb128 0x31
6585
+ .4byte .LASF421
6586
+ .byte 0x1
6587
+ .2byte 0x2cd
6588
+ .4byte 0x54
6589
+ .8byte .LFB277
6590
+ .8byte .LFE277-.LFB277
6591
+ .uleb128 0x1
6592
+ .byte 0x9c
6593
+ .4byte 0x182b
6594
+ .uleb128 0x32
6595
+ .string "dev"
6596
+ .byte 0x1
6597
+ .2byte 0x2cd
6598
+ .4byte 0x25f
6599
+ .4byte .LLST14
6600
+ .uleb128 0x33
6601
+ .string "otp"
6602
+ .byte 0x1
6603
+ .2byte 0x2cf
6604
+ .4byte 0x182b
6605
+ .4byte .LLST15
6606
+ .uleb128 0x34
6607
+ .8byte .LVL20
6608
+ .4byte 0x4289
6609
+ .4byte 0x1798
6610
+ .uleb128 0x35
6611
+ .uleb128 0x1
6612
+ .byte 0x50
6613
+ .uleb128 0x2
6614
+ .byte 0x84
6615
+ .sleb128 0
6616
+ .byte 0
6617
+ .uleb128 0x34
6618
+ .8byte .LVL23
6619
+ .4byte 0x4295
6620
+ .4byte 0x17b0
6621
+ .uleb128 0x35
6622
+ .uleb128 0x1
6623
+ .byte 0x50
6624
+ .uleb128 0x2
6625
+ .byte 0x84
6626
+ .sleb128 0
6627
+ .byte 0
6628
+ .uleb128 0x34
6629
+ .8byte .LVL24
6630
+ .4byte 0x42a0
6631
+ .4byte 0x17da
6632
+ .uleb128 0x35
6633
+ .uleb128 0x1
6634
+ .byte 0x50
6635
+ .uleb128 0x2
6636
+ .byte 0x84
6637
+ .sleb128 0
6638
+ .uleb128 0x35
6639
+ .uleb128 0x1
6640
+ .byte 0x51
6641
+ .uleb128 0x9
6642
+ .byte 0x3
6643
+ .8byte .LC0
6644
+ .uleb128 0x35
6645
+ .uleb128 0x1
6646
+ .byte 0x52
6647
+ .uleb128 0x1
6648
+ .byte 0x30
6649
+ .byte 0
6650
+ .uleb128 0x34
6651
+ .8byte .LVL25
6652
+ .4byte 0x42a0
6653
+ .4byte 0x1804
6654
+ .uleb128 0x35
6655
+ .uleb128 0x1
6656
+ .byte 0x50
6657
+ .uleb128 0x2
6658
+ .byte 0x84
6659
+ .sleb128 0
6660
+ .uleb128 0x35
6661
+ .uleb128 0x1
6662
+ .byte 0x51
6663
+ .uleb128 0x9
6664
+ .byte 0x3
6665
+ .8byte .LC1
6666
+ .uleb128 0x35
6667
+ .uleb128 0x1
6668
+ .byte 0x52
6669
+ .uleb128 0x1
6670
+ .byte 0x30
6671
+ .byte 0
6672
+ .uleb128 0x36
6673
+ .8byte .LVL26
6674
+ .4byte 0x42a0
6675
+ .uleb128 0x35
6676
+ .uleb128 0x1
6677
+ .byte 0x50
6678
+ .uleb128 0x2
6679
+ .byte 0x84
6680
+ .sleb128 0
6681
+ .uleb128 0x35
6682
+ .uleb128 0x1
6683
+ .byte 0x51
6684
+ .uleb128 0x9
6685
+ .byte 0x3
6686
+ .8byte .LC2
6687
+ .uleb128 0x35
6688
+ .uleb128 0x1
6689
+ .byte 0x52
6690
+ .uleb128 0x1
6691
+ .byte 0x30
6692
+ .byte 0
6693
+ .byte 0
6694
+ .uleb128 0x8
6695
+ .byte 0x8
6696
+ .4byte 0x1632
6697
+ .uleb128 0x31
6698
+ .4byte .LASF422
6699
+ .byte 0x1
6700
+ .2byte 0x2b6
6701
+ .4byte 0x54
6702
+ .8byte .LFB276
6703
+ .8byte .LFE276-.LFB276
6704
+ .uleb128 0x1
6705
+ .byte 0x9c
6706
+ .4byte 0x18b2
6707
+ .uleb128 0x32
6708
+ .string "dev"
6709
+ .byte 0x1
6710
+ .2byte 0x2b6
6711
+ .4byte 0x25f
6712
+ .4byte .LLST1
6713
+ .uleb128 0x37
6714
+ .4byte .LASF423
6715
+ .byte 0x1
6716
+ .2byte 0x2b7
6717
+ .4byte 0x3b
6718
+ .uleb128 0x1
6719
+ .byte 0x51
6720
+ .uleb128 0x38
6721
+ .string "buf"
6722
+ .byte 0x1
6723
+ .2byte 0x2b8
6724
+ .4byte 0x137
6725
+ .uleb128 0x1
6726
+ .byte 0x52
6727
+ .uleb128 0x33
6728
+ .string "ret"
6729
+ .byte 0x1
6730
+ .2byte 0x2ba
6731
+ .4byte 0x54
6732
+ .4byte .LLST2
6733
+ .uleb128 0x39
6734
+ .4byte 0x18b2
6735
+ .8byte .LBB23
6736
+ .8byte .LBE23-.LBB23
6737
+ .byte 0x1
6738
+ .2byte 0x2be
6739
+ .uleb128 0x3a
6740
+ .4byte 0x18c3
6741
+ .4byte .LLST3
6742
+ .byte 0
6743
+ .byte 0
6744
+ .uleb128 0x3b
6745
+ .4byte .LASF431
6746
+ .byte 0x1
6747
+ .2byte 0x2af
6748
+ .4byte 0x54
6749
+ .byte 0x1
6750
+ .4byte 0x18d0
6751
+ .uleb128 0x3c
6752
+ .string "buf"
6753
+ .byte 0x1
6754
+ .2byte 0x2af
6755
+ .4byte 0x11d8
6756
+ .byte 0
6757
+ .uleb128 0x31
6758
+ .4byte .LASF424
6759
+ .byte 0x1
6760
+ .2byte 0x2a7
6761
+ .4byte 0x54
6762
+ .8byte .LFB274
6763
+ .8byte .LFE274-.LFB274
6764
+ .uleb128 0x1
6765
+ .byte 0x9c
6766
+ .4byte 0x1981
6767
+ .uleb128 0x32
6768
+ .string "dev"
6769
+ .byte 0x1
6770
+ .2byte 0x2a7
6771
+ .4byte 0x25f
6772
+ .4byte .LLST4
6773
+ .uleb128 0x3d
6774
+ .4byte .LASF425
6775
+ .byte 0x1
6776
+ .2byte 0x2a7
6777
+ .4byte 0x54
6778
+ .4byte .LLST5
6779
+ .uleb128 0x32
6780
+ .string "buf"
6781
+ .byte 0x1
6782
+ .2byte 0x2a8
6783
+ .4byte 0x265
6784
+ .4byte .LLST6
6785
+ .uleb128 0x3d
6786
+ .4byte .LASF51
6787
+ .byte 0x1
6788
+ .2byte 0x2a8
6789
+ .4byte 0x54
6790
+ .4byte .LLST7
6791
+ .uleb128 0x3e
6792
+ .4byte .LASF426
6793
+ .byte 0x1
6794
+ .2byte 0x2aa
6795
+ .4byte 0x1981
6796
+ .4byte .LLST8
6797
+ .uleb128 0x34
6798
+ .8byte .LVL8
6799
+ .4byte 0x42ab
6800
+ .4byte 0x195a
6801
+ .uleb128 0x35
6802
+ .uleb128 0x1
6803
+ .byte 0x50
6804
+ .uleb128 0x2
6805
+ .byte 0x83
6806
+ .sleb128 0
6807
+ .byte 0
6808
+ .uleb128 0x3f
6809
+ .8byte .LVL12
6810
+ .uleb128 0x35
6811
+ .uleb128 0x1
6812
+ .byte 0x50
6813
+ .uleb128 0x3
6814
+ .byte 0xf3
6815
+ .uleb128 0x1
6816
+ .byte 0x50
6817
+ .uleb128 0x35
6818
+ .uleb128 0x1
6819
+ .byte 0x51
6820
+ .uleb128 0x3
6821
+ .byte 0xf3
6822
+ .uleb128 0x1
6823
+ .byte 0x51
6824
+ .uleb128 0x35
6825
+ .uleb128 0x1
6826
+ .byte 0x52
6827
+ .uleb128 0x3
6828
+ .byte 0xf3
6829
+ .uleb128 0x1
6830
+ .byte 0x52
6831
+ .uleb128 0x35
6832
+ .uleb128 0x1
6833
+ .byte 0x53
6834
+ .uleb128 0x3
6835
+ .byte 0xf3
6836
+ .uleb128 0x1
6837
+ .byte 0x53
6838
+ .byte 0
6839
+ .byte 0
6840
+ .uleb128 0x8
6841
+ .byte 0x8
6842
+ .4byte 0x166f
6843
+ .uleb128 0x31
6844
+ .4byte .LASF427
6845
+ .byte 0x1
6846
+ .2byte 0x29f
6847
+ .4byte 0x54
6848
+ .8byte .LFB273
6849
+ .8byte .LFE273-.LFB273
6850
+ .uleb128 0x1
6851
+ .byte 0x9c
6852
+ .4byte 0x1a38
6853
+ .uleb128 0x32
6854
+ .string "dev"
6855
+ .byte 0x1
6856
+ .2byte 0x29f
6857
+ .4byte 0x25f
6858
+ .4byte .LLST9
6859
+ .uleb128 0x3d
6860
+ .4byte .LASF425
6861
+ .byte 0x1
6862
+ .2byte 0x29f
6863
+ .4byte 0x54
6864
+ .4byte .LLST10
6865
+ .uleb128 0x32
6866
+ .string "buf"
6867
+ .byte 0x1
6868
+ .2byte 0x2a0
6869
+ .4byte 0x137
6870
+ .4byte .LLST11
6871
+ .uleb128 0x3d
6872
+ .4byte .LASF51
6873
+ .byte 0x1
6874
+ .2byte 0x2a0
6875
+ .4byte 0x54
6876
+ .4byte .LLST12
6877
+ .uleb128 0x3e
6878
+ .4byte .LASF426
6879
+ .byte 0x1
6880
+ .2byte 0x2a2
6881
+ .4byte 0x1981
6882
+ .4byte .LLST13
6883
+ .uleb128 0x34
6884
+ .8byte .LVL14
6885
+ .4byte 0x42ab
6886
+ .4byte 0x1a11
6887
+ .uleb128 0x35
6888
+ .uleb128 0x1
6889
+ .byte 0x50
6890
+ .uleb128 0x2
6891
+ .byte 0x83
6892
+ .sleb128 0
6893
+ .byte 0
6894
+ .uleb128 0x3f
6895
+ .8byte .LVL18
6896
+ .uleb128 0x35
6897
+ .uleb128 0x1
6898
+ .byte 0x50
6899
+ .uleb128 0x3
6900
+ .byte 0xf3
6901
+ .uleb128 0x1
6902
+ .byte 0x50
6903
+ .uleb128 0x35
6904
+ .uleb128 0x1
6905
+ .byte 0x51
6906
+ .uleb128 0x3
6907
+ .byte 0xf3
6908
+ .uleb128 0x1
6909
+ .byte 0x51
6910
+ .uleb128 0x35
6911
+ .uleb128 0x1
6912
+ .byte 0x52
6913
+ .uleb128 0x3
6914
+ .byte 0xf3
6915
+ .uleb128 0x1
6916
+ .byte 0x52
6917
+ .uleb128 0x35
6918
+ .uleb128 0x1
6919
+ .byte 0x53
6920
+ .uleb128 0x3
6921
+ .byte 0xf3
6922
+ .uleb128 0x1
6923
+ .byte 0x53
6924
+ .byte 0
6925
+ .byte 0
6926
+ .uleb128 0x31
6927
+ .4byte .LASF428
6928
+ .byte 0x1
6929
+ .2byte 0x26c
6930
+ .4byte 0x54
6931
+ .8byte .LFB272
6932
+ .8byte .LFE272-.LFB272
6933
+ .uleb128 0x1
6934
+ .byte 0x9c
6935
+ .4byte 0x2564
6936
+ .uleb128 0x32
6937
+ .string "dev"
6938
+ .byte 0x1
6939
+ .2byte 0x26c
6940
+ .4byte 0x25f
6941
+ .4byte .LLST69
6942
+ .uleb128 0x3d
6943
+ .4byte .LASF425
6944
+ .byte 0x1
6945
+ .2byte 0x26c
6946
+ .4byte 0x54
6947
+ .4byte .LLST70
6948
+ .uleb128 0x32
6949
+ .string "buf"
6950
+ .byte 0x1
6951
+ .2byte 0x26c
6952
+ .4byte 0x265
6953
+ .4byte .LLST71
6954
+ .uleb128 0x3d
6955
+ .4byte .LASF51
6956
+ .byte 0x1
6957
+ .2byte 0x26c
6958
+ .4byte 0x54
6959
+ .4byte .LLST72
6960
+ .uleb128 0x33
6961
+ .string "otp"
6962
+ .byte 0x1
6963
+ .2byte 0x26e
6964
+ .4byte 0x182b
6965
+ .4byte .LLST73
6966
+ .uleb128 0x3e
6967
+ .4byte .LASF387
6968
+ .byte 0x1
6969
+ .2byte 0x26f
6970
+ .4byte 0x11d2
6971
+ .4byte .LLST74
6972
+ .uleb128 0x3e
6973
+ .4byte .LASF429
6974
+ .byte 0x1
6975
+ .2byte 0x270
6976
+ .4byte 0xfa
6977
+ .4byte .LLST74
6978
+ .uleb128 0x3e
6979
+ .4byte .LASF430
6980
+ .byte 0x1
6981
+ .2byte 0x271
6982
+ .4byte 0xfa
6983
+ .4byte .LLST76
6984
+ .uleb128 0x33
6985
+ .string "i"
6986
+ .byte 0x1
6987
+ .2byte 0x272
6988
+ .4byte 0x54
6989
+ .4byte .LLST77
6990
+ .uleb128 0x33
6991
+ .string "ret"
6992
+ .byte 0x1
6993
+ .2byte 0x272
6994
+ .4byte 0x54
6995
+ .4byte .LLST78
6996
+ .uleb128 0x40
6997
+ .4byte 0x2564
6998
+ .8byte .LBB244
6999
+ .4byte .Ldebug_ranges0+0x3f0
7000
+ .byte 0x1
7001
+ .2byte 0x294
7002
+ .4byte 0x2436
7003
+ .uleb128 0x3a
7004
+ .4byte 0x2599
7005
+ .4byte .LLST79
7006
+ .uleb128 0x3a
7007
+ .4byte 0x258d
7008
+ .4byte .LLST80
7009
+ .uleb128 0x3a
7010
+ .4byte 0x2581
7011
+ .4byte .LLST81
7012
+ .uleb128 0x3a
7013
+ .4byte 0x2575
7014
+ .4byte .LLST82
7015
+ .uleb128 0x41
7016
+ .4byte .Ldebug_ranges0+0x3f0
7017
+ .uleb128 0x42
7018
+ .4byte 0x25a5
7019
+ .4byte .LLST83
7020
+ .uleb128 0x42
7021
+ .4byte 0x25b1
7022
+ .4byte .LLST84
7023
+ .uleb128 0x43
7024
+ .4byte 0x25ca
7025
+ .8byte .L88
7026
+ .uleb128 0x44
7027
+ .4byte 0x25bd
7028
+ .uleb128 0x45
7029
+ .8byte .LBB246
7030
+ .8byte .LBE246-.LBB246
7031
+ .4byte 0x1b7c
7032
+ .uleb128 0x42
7033
+ .4byte 0x25d7
7034
+ .4byte .LLST85
7035
+ .byte 0
7036
+ .uleb128 0x45
7037
+ .8byte .LBB247
7038
+ .8byte .LBE247-.LBB247
7039
+ .4byte 0x1b9b
7040
+ .uleb128 0x42
7041
+ .4byte 0x25e9
7042
+ .4byte .LLST86
7043
+ .byte 0
7044
+ .uleb128 0x45
7045
+ .8byte .LBB248
7046
+ .8byte .LBE248-.LBB248
7047
+ .4byte 0x1bba
7048
+ .uleb128 0x42
7049
+ .4byte 0x25fb
7050
+ .4byte .LLST87
7051
+ .byte 0
7052
+ .uleb128 0x45
7053
+ .8byte .LBB249
7054
+ .8byte .LBE249-.LBB249
7055
+ .4byte 0x1bd9
7056
+ .uleb128 0x42
7057
+ .4byte 0x260d
7058
+ .4byte .LLST88
7059
+ .byte 0
7060
+ .uleb128 0x45
7061
+ .8byte .LBB250
7062
+ .8byte .LBE250-.LBB250
7063
+ .4byte 0x1bf8
7064
+ .uleb128 0x42
7065
+ .4byte 0x261f
7066
+ .4byte .LLST89
7067
+ .byte 0
7068
+ .uleb128 0x45
7069
+ .8byte .LBB251
7070
+ .8byte .LBE251-.LBB251
7071
+ .4byte 0x1c17
7072
+ .uleb128 0x42
7073
+ .4byte 0x2631
7074
+ .4byte .LLST90
7075
+ .byte 0
7076
+ .uleb128 0x45
7077
+ .8byte .LBB252
7078
+ .8byte .LBE252-.LBB252
7079
+ .4byte 0x1c36
7080
+ .uleb128 0x42
7081
+ .4byte 0x2643
7082
+ .4byte .LLST91
7083
+ .byte 0
7084
+ .uleb128 0x45
7085
+ .8byte .LBB253
7086
+ .8byte .LBE253-.LBB253
7087
+ .4byte 0x1c55
7088
+ .uleb128 0x42
7089
+ .4byte 0x2655
7090
+ .4byte .LLST92
7091
+ .byte 0
7092
+ .uleb128 0x45
7093
+ .8byte .LBB254
7094
+ .8byte .LBE254-.LBB254
7095
+ .4byte 0x1c74
7096
+ .uleb128 0x42
7097
+ .4byte 0x2667
7098
+ .4byte .LLST93
7099
+ .byte 0
7100
+ .uleb128 0x45
7101
+ .8byte .LBB255
7102
+ .8byte .LBE255-.LBB255
7103
+ .4byte 0x1c93
7104
+ .uleb128 0x42
7105
+ .4byte 0x2679
7106
+ .4byte .LLST94
7107
+ .byte 0
7108
+ .uleb128 0x45
7109
+ .8byte .LBB256
7110
+ .8byte .LBE256-.LBB256
7111
+ .4byte 0x1cb2
7112
+ .uleb128 0x42
7113
+ .4byte 0x268b
7114
+ .4byte .LLST95
7115
+ .byte 0
7116
+ .uleb128 0x45
7117
+ .8byte .LBB257
7118
+ .8byte .LBE257-.LBB257
7119
+ .4byte 0x1cd1
7120
+ .uleb128 0x42
7121
+ .4byte 0x269d
7122
+ .4byte .LLST96
7123
+ .byte 0
7124
+ .uleb128 0x45
7125
+ .8byte .LBB258
7126
+ .8byte .LBE258-.LBB258
7127
+ .4byte 0x1cf0
7128
+ .uleb128 0x42
7129
+ .4byte 0x26af
7130
+ .4byte .LLST97
7131
+ .byte 0
7132
+ .uleb128 0x45
7133
+ .8byte .LBB259
7134
+ .8byte .LBE259-.LBB259
7135
+ .4byte 0x1d0f
7136
+ .uleb128 0x42
7137
+ .4byte 0x26c1
7138
+ .4byte .LLST98
7139
+ .byte 0
7140
+ .uleb128 0x45
7141
+ .8byte .LBB260
7142
+ .8byte .LBE260-.LBB260
7143
+ .4byte 0x1d2e
7144
+ .uleb128 0x42
7145
+ .4byte 0x26d3
7146
+ .4byte .LLST99
7147
+ .byte 0
7148
+ .uleb128 0x45
7149
+ .8byte .LBB261
7150
+ .8byte .LBE261-.LBB261
7151
+ .4byte 0x1d4d
7152
+ .uleb128 0x42
7153
+ .4byte 0x26e5
7154
+ .4byte .LLST100
7155
+ .byte 0
7156
+ .uleb128 0x45
7157
+ .8byte .LBB262
7158
+ .8byte .LBE262-.LBB262
7159
+ .4byte 0x1d6c
7160
+ .uleb128 0x42
7161
+ .4byte 0x26f7
7162
+ .4byte .LLST101
7163
+ .byte 0
7164
+ .uleb128 0x45
7165
+ .8byte .LBB263
7166
+ .8byte .LBE263-.LBB263
7167
+ .4byte 0x1d8b
7168
+ .uleb128 0x42
7169
+ .4byte 0x2709
7170
+ .4byte .LLST102
7171
+ .byte 0
7172
+ .uleb128 0x46
7173
+ .4byte .Ldebug_ranges0+0x450
7174
+ .4byte 0x1d9e
7175
+ .uleb128 0x42
7176
+ .4byte 0x271b
7177
+ .4byte .LLST103
7178
+ .byte 0
7179
+ .uleb128 0x46
7180
+ .4byte .Ldebug_ranges0+0x480
7181
+ .4byte 0x1db1
7182
+ .uleb128 0x42
7183
+ .4byte 0x272d
7184
+ .4byte .LLST104
7185
+ .byte 0
7186
+ .uleb128 0x46
7187
+ .4byte .Ldebug_ranges0+0x4b0
7188
+ .4byte 0x1dc4
7189
+ .uleb128 0x42
7190
+ .4byte 0x273f
7191
+ .4byte .LLST105
7192
+ .byte 0
7193
+ .uleb128 0x46
7194
+ .4byte .Ldebug_ranges0+0x4e0
7195
+ .4byte 0x1dd7
7196
+ .uleb128 0x42
7197
+ .4byte 0x2a2f
7198
+ .4byte .LLST106
7199
+ .byte 0
7200
+ .uleb128 0x45
7201
+ .8byte .LBB272
7202
+ .8byte .LBE272-.LBB272
7203
+ .4byte 0x1df6
7204
+ .uleb128 0x42
7205
+ .4byte 0x2751
7206
+ .4byte .LLST107
7207
+ .byte 0
7208
+ .uleb128 0x45
7209
+ .8byte .LBB273
7210
+ .8byte .LBE273-.LBB273
7211
+ .4byte 0x1e15
7212
+ .uleb128 0x42
7213
+ .4byte 0x2763
7214
+ .4byte .LLST108
7215
+ .byte 0
7216
+ .uleb128 0x45
7217
+ .8byte .LBB274
7218
+ .8byte .LBE274-.LBB274
7219
+ .4byte 0x1e34
7220
+ .uleb128 0x42
7221
+ .4byte 0x2775
7222
+ .4byte .LLST109
7223
+ .byte 0
7224
+ .uleb128 0x45
7225
+ .8byte .LBB275
7226
+ .8byte .LBE275-.LBB275
7227
+ .4byte 0x1e53
7228
+ .uleb128 0x42
7229
+ .4byte 0x2787
7230
+ .4byte .LLST110
7231
+ .byte 0
7232
+ .uleb128 0x45
7233
+ .8byte .LBB276
7234
+ .8byte .LBE276-.LBB276
7235
+ .4byte 0x1e72
7236
+ .uleb128 0x42
7237
+ .4byte 0x2799
7238
+ .4byte .LLST111
7239
+ .byte 0
7240
+ .uleb128 0x45
7241
+ .8byte .LBB277
7242
+ .8byte .LBE277-.LBB277
7243
+ .4byte 0x1e91
7244
+ .uleb128 0x42
7245
+ .4byte 0x27ab
7246
+ .4byte .LLST112
7247
+ .byte 0
7248
+ .uleb128 0x45
7249
+ .8byte .LBB278
7250
+ .8byte .LBE278-.LBB278
7251
+ .4byte 0x1eb0
7252
+ .uleb128 0x42
7253
+ .4byte 0x27bd
7254
+ .4byte .LLST113
7255
+ .byte 0
7256
+ .uleb128 0x45
7257
+ .8byte .LBB279
7258
+ .8byte .LBE279-.LBB279
7259
+ .4byte 0x1ecf
7260
+ .uleb128 0x42
7261
+ .4byte 0x27cf
7262
+ .4byte .LLST114
7263
+ .byte 0
7264
+ .uleb128 0x45
7265
+ .8byte .LBB280
7266
+ .8byte .LBE280-.LBB280
7267
+ .4byte 0x1eee
7268
+ .uleb128 0x42
7269
+ .4byte 0x27e1
7270
+ .4byte .LLST115
7271
+ .byte 0
7272
+ .uleb128 0x45
7273
+ .8byte .LBB281
7274
+ .8byte .LBE281-.LBB281
7275
+ .4byte 0x1f0d
7276
+ .uleb128 0x42
7277
+ .4byte 0x27f3
7278
+ .4byte .LLST116
7279
+ .byte 0
7280
+ .uleb128 0x45
7281
+ .8byte .LBB282
7282
+ .8byte .LBE282-.LBB282
7283
+ .4byte 0x1f2c
7284
+ .uleb128 0x42
7285
+ .4byte 0x2805
7286
+ .4byte .LLST117
7287
+ .byte 0
7288
+ .uleb128 0x45
7289
+ .8byte .LBB283
7290
+ .8byte .LBE283-.LBB283
7291
+ .4byte 0x1f4b
7292
+ .uleb128 0x42
7293
+ .4byte 0x2817
7294
+ .4byte .LLST118
7295
+ .byte 0
7296
+ .uleb128 0x45
7297
+ .8byte .LBB284
7298
+ .8byte .LBE284-.LBB284
7299
+ .4byte 0x1f6a
7300
+ .uleb128 0x42
7301
+ .4byte 0x2829
7302
+ .4byte .LLST119
7303
+ .byte 0
7304
+ .uleb128 0x45
7305
+ .8byte .LBB285
7306
+ .8byte .LBE285-.LBB285
7307
+ .4byte 0x1f89
7308
+ .uleb128 0x42
7309
+ .4byte 0x283b
7310
+ .4byte .LLST120
7311
+ .byte 0
7312
+ .uleb128 0x45
7313
+ .8byte .LBB286
7314
+ .8byte .LBE286-.LBB286
7315
+ .4byte 0x1fa8
7316
+ .uleb128 0x42
7317
+ .4byte 0x284d
7318
+ .4byte .LLST121
7319
+ .byte 0
7320
+ .uleb128 0x45
7321
+ .8byte .LBB287
7322
+ .8byte .LBE287-.LBB287
7323
+ .4byte 0x1fc7
7324
+ .uleb128 0x42
7325
+ .4byte 0x285f
7326
+ .4byte .LLST122
7327
+ .byte 0
7328
+ .uleb128 0x46
7329
+ .4byte .Ldebug_ranges0+0x510
7330
+ .4byte 0x1fda
7331
+ .uleb128 0x42
7332
+ .4byte 0x2871
7333
+ .4byte .LLST123
7334
+ .byte 0
7335
+ .uleb128 0x45
7336
+ .8byte .LBB290
7337
+ .8byte .LBE290-.LBB290
7338
+ .4byte 0x1ff9
7339
+ .uleb128 0x42
7340
+ .4byte 0x2883
7341
+ .4byte .LLST124
7342
+ .byte 0
7343
+ .uleb128 0x45
7344
+ .8byte .LBB291
7345
+ .8byte .LBE291-.LBB291
7346
+ .4byte 0x2018
7347
+ .uleb128 0x42
7348
+ .4byte 0x2895
7349
+ .4byte .LLST125
7350
+ .byte 0
7351
+ .uleb128 0x45
7352
+ .8byte .LBB292
7353
+ .8byte .LBE292-.LBB292
7354
+ .4byte 0x2037
7355
+ .uleb128 0x42
7356
+ .4byte 0x28a7
7357
+ .4byte .LLST126
7358
+ .byte 0
7359
+ .uleb128 0x45
7360
+ .8byte .LBB293
7361
+ .8byte .LBE293-.LBB293
7362
+ .4byte 0x2056
7363
+ .uleb128 0x42
7364
+ .4byte 0x28b9
7365
+ .4byte .LLST127
7366
+ .byte 0
7367
+ .uleb128 0x46
7368
+ .4byte .Ldebug_ranges0+0x540
7369
+ .4byte 0x2069
7370
+ .uleb128 0x42
7371
+ .4byte 0x28cb
7372
+ .4byte .LLST128
7373
+ .byte 0
7374
+ .uleb128 0x45
7375
+ .8byte .LBB296
7376
+ .8byte .LBE296-.LBB296
7377
+ .4byte 0x2088
7378
+ .uleb128 0x42
7379
+ .4byte 0x28dd
7380
+ .4byte .LLST129
7381
+ .byte 0
7382
+ .uleb128 0x45
7383
+ .8byte .LBB297
7384
+ .8byte .LBE297-.LBB297
7385
+ .4byte 0x20a7
7386
+ .uleb128 0x42
7387
+ .4byte 0x28ef
7388
+ .4byte .LLST130
7389
+ .byte 0
7390
+ .uleb128 0x46
7391
+ .4byte .Ldebug_ranges0+0x570
7392
+ .4byte 0x20ba
7393
+ .uleb128 0x42
7394
+ .4byte 0x2901
7395
+ .4byte .LLST131
7396
+ .byte 0
7397
+ .uleb128 0x46
7398
+ .4byte .Ldebug_ranges0+0x5a0
7399
+ .4byte 0x20cd
7400
+ .uleb128 0x42
7401
+ .4byte 0x2913
7402
+ .4byte .LLST132
7403
+ .byte 0
7404
+ .uleb128 0x46
7405
+ .4byte .Ldebug_ranges0+0x5d0
7406
+ .4byte 0x20e0
7407
+ .uleb128 0x42
7408
+ .4byte 0x2925
7409
+ .4byte .LLST133
7410
+ .byte 0
7411
+ .uleb128 0x45
7412
+ .8byte .LBB304
7413
+ .8byte .LBE304-.LBB304
7414
+ .4byte 0x20ff
7415
+ .uleb128 0x42
7416
+ .4byte 0x2937
7417
+ .4byte .LLST134
7418
+ .byte 0
7419
+ .uleb128 0x45
7420
+ .8byte .LBB305
7421
+ .8byte .LBE305-.LBB305
7422
+ .4byte 0x211e
7423
+ .uleb128 0x42
7424
+ .4byte 0x2949
7425
+ .4byte .LLST135
7426
+ .byte 0
7427
+ .uleb128 0x45
7428
+ .8byte .LBB306
7429
+ .8byte .LBE306-.LBB306
7430
+ .4byte 0x213d
7431
+ .uleb128 0x42
7432
+ .4byte 0x295b
7433
+ .4byte .LLST136
7434
+ .byte 0
7435
+ .uleb128 0x45
7436
+ .8byte .LBB307
7437
+ .8byte .LBE307-.LBB307
7438
+ .4byte 0x215c
7439
+ .uleb128 0x42
7440
+ .4byte 0x296d
7441
+ .4byte .LLST137
7442
+ .byte 0
7443
+ .uleb128 0x46
7444
+ .4byte .Ldebug_ranges0+0x600
7445
+ .4byte 0x216f
7446
+ .uleb128 0x42
7447
+ .4byte 0x297f
7448
+ .4byte .LLST138
7449
+ .byte 0
7450
+ .uleb128 0x45
7451
+ .8byte .LBB310
7452
+ .8byte .LBE310-.LBB310
7453
+ .4byte 0x218e
7454
+ .uleb128 0x42
7455
+ .4byte 0x2991
7456
+ .4byte .LLST139
7457
+ .byte 0
7458
+ .uleb128 0x45
7459
+ .8byte .LBB311
7460
+ .8byte .LBE311-.LBB311
7461
+ .4byte 0x21ad
7462
+ .uleb128 0x42
7463
+ .4byte 0x29a3
7464
+ .4byte .LLST140
7465
+ .byte 0
7466
+ .uleb128 0x45
7467
+ .8byte .LBB312
7468
+ .8byte .LBE312-.LBB312
7469
+ .4byte 0x21cc
7470
+ .uleb128 0x42
7471
+ .4byte 0x29b5
7472
+ .4byte .LLST141
7473
+ .byte 0
7474
+ .uleb128 0x45
7475
+ .8byte .LBB313
7476
+ .8byte .LBE313-.LBB313
7477
+ .4byte 0x21eb
7478
+ .uleb128 0x42
7479
+ .4byte 0x29c7
7480
+ .4byte .LLST142
7481
+ .byte 0
7482
+ .uleb128 0x46
7483
+ .4byte .Ldebug_ranges0+0x630
7484
+ .4byte 0x21fe
7485
+ .uleb128 0x42
7486
+ .4byte 0x29d9
7487
+ .4byte .LLST143
7488
+ .byte 0
7489
+ .uleb128 0x45
7490
+ .8byte .LBB316
7491
+ .8byte .LBE316-.LBB316
7492
+ .4byte 0x221d
7493
+ .uleb128 0x42
7494
+ .4byte 0x29eb
7495
+ .4byte .LLST144
7496
+ .byte 0
7497
+ .uleb128 0x45
7498
+ .8byte .LBB317
7499
+ .8byte .LBE317-.LBB317
7500
+ .4byte 0x223c
7501
+ .uleb128 0x42
7502
+ .4byte 0x29fd
7503
+ .4byte .LLST145
7504
+ .byte 0
7505
+ .uleb128 0x45
7506
+ .8byte .LBB318
7507
+ .8byte .LBE318-.LBB318
7508
+ .4byte 0x225b
7509
+ .uleb128 0x42
7510
+ .4byte 0x2a0f
7511
+ .4byte .LLST146
7512
+ .byte 0
7513
+ .uleb128 0x45
7514
+ .8byte .LBB319
7515
+ .8byte .LBE319-.LBB319
7516
+ .4byte 0x227a
7517
+ .uleb128 0x42
7518
+ .4byte 0x2a21
7519
+ .4byte .LLST147
7520
+ .byte 0
7521
+ .uleb128 0x34
7522
+ .8byte .LVL263
7523
+ .4byte 0x42ab
7524
+ .4byte 0x2292
7525
+ .uleb128 0x35
7526
+ .uleb128 0x1
7527
+ .byte 0x50
7528
+ .uleb128 0x2
7529
+ .byte 0x88
7530
+ .sleb128 0
7531
+ .byte 0
7532
+ .uleb128 0x34
7533
+ .8byte .LVL266
7534
+ .4byte 0x42b7
7535
+ .4byte 0x22ba
7536
+ .uleb128 0x35
7537
+ .uleb128 0x1
7538
+ .byte 0x50
7539
+ .uleb128 0x9
7540
+ .byte 0x3
7541
+ .8byte .LC4
7542
+ .uleb128 0x35
7543
+ .uleb128 0x1
7544
+ .byte 0x51
7545
+ .uleb128 0x5
7546
+ .byte 0x85
7547
+ .sleb128 0
7548
+ .byte 0x9
7549
+ .byte 0xfe
7550
+ .byte 0x1a
7551
+ .byte 0
7552
+ .uleb128 0x47
7553
+ .8byte .LVL289
7554
+ .4byte 0x22ce
7555
+ .uleb128 0x35
7556
+ .uleb128 0x1
7557
+ .byte 0x53
7558
+ .uleb128 0x2
7559
+ .byte 0x89
7560
+ .sleb128 0
7561
+ .byte 0
7562
+ .uleb128 0x34
7563
+ .8byte .LVL310
7564
+ .4byte 0x401e
7565
+ .4byte 0x22f3
7566
+ .uleb128 0x35
7567
+ .uleb128 0x1
7568
+ .byte 0x50
7569
+ .uleb128 0x2
7570
+ .byte 0x8c
7571
+ .sleb128 0
7572
+ .uleb128 0x35
7573
+ .uleb128 0x1
7574
+ .byte 0x51
7575
+ .uleb128 0x1
7576
+ .byte 0x32
7577
+ .uleb128 0x48
7578
+ .4byte 0x3d7a
7579
+ .uleb128 0x2
7580
+ .byte 0x8c
7581
+ .sleb128 0
7582
+ .byte 0
7583
+ .uleb128 0x49
7584
+ .8byte .LVL314
7585
+ .4byte 0x42b7
7586
+ .uleb128 0x47
7587
+ .8byte .LVL315
7588
+ .4byte 0x2314
7589
+ .uleb128 0x35
7590
+ .uleb128 0x1
7591
+ .byte 0x53
7592
+ .uleb128 0x2
7593
+ .byte 0x89
7594
+ .sleb128 0
7595
+ .byte 0
7596
+ .uleb128 0x34
7597
+ .8byte .LVL336
7598
+ .4byte 0x401e
7599
+ .4byte 0x233a
7600
+ .uleb128 0x35
7601
+ .uleb128 0x1
7602
+ .byte 0x50
7603
+ .uleb128 0x2
7604
+ .byte 0x8c
7605
+ .sleb128 0
7606
+ .uleb128 0x35
7607
+ .uleb128 0x1
7608
+ .byte 0x51
7609
+ .uleb128 0x2
7610
+ .byte 0x85
7611
+ .sleb128 0
7612
+ .uleb128 0x48
7613
+ .4byte 0x3d7a
7614
+ .uleb128 0x2
7615
+ .byte 0x8c
7616
+ .sleb128 0
7617
+ .byte 0
7618
+ .uleb128 0x34
7619
+ .8byte .LVL345
7620
+ .4byte 0x401e
7621
+ .4byte 0x2360
7622
+ .uleb128 0x35
7623
+ .uleb128 0x1
7624
+ .byte 0x50
7625
+ .uleb128 0x2
7626
+ .byte 0x8c
7627
+ .sleb128 0
7628
+ .uleb128 0x35
7629
+ .uleb128 0x1
7630
+ .byte 0x51
7631
+ .uleb128 0x2
7632
+ .byte 0x85
7633
+ .sleb128 0
7634
+ .uleb128 0x48
7635
+ .4byte 0x3d7a
7636
+ .uleb128 0x2
7637
+ .byte 0x8c
7638
+ .sleb128 0
7639
+ .byte 0
7640
+ .uleb128 0x34
7641
+ .8byte .LVL355
7642
+ .4byte 0x401e
7643
+ .4byte 0x2386
7644
+ .uleb128 0x35
7645
+ .uleb128 0x1
7646
+ .byte 0x50
7647
+ .uleb128 0x2
7648
+ .byte 0x8c
7649
+ .sleb128 0
7650
+ .uleb128 0x35
7651
+ .uleb128 0x1
7652
+ .byte 0x51
7653
+ .uleb128 0x2
7654
+ .byte 0x85
7655
+ .sleb128 0
7656
+ .uleb128 0x48
7657
+ .4byte 0x3d7a
7658
+ .uleb128 0x2
7659
+ .byte 0x8c
7660
+ .sleb128 0
7661
+ .byte 0
7662
+ .uleb128 0x34
7663
+ .8byte .LVL364
7664
+ .4byte 0x401e
7665
+ .4byte 0x23ac
7666
+ .uleb128 0x35
7667
+ .uleb128 0x1
7668
+ .byte 0x50
7669
+ .uleb128 0x2
7670
+ .byte 0x8c
7671
+ .sleb128 0
7672
+ .uleb128 0x35
7673
+ .uleb128 0x1
7674
+ .byte 0x51
7675
+ .uleb128 0x2
7676
+ .byte 0x85
7677
+ .sleb128 0
7678
+ .uleb128 0x48
7679
+ .4byte 0x3d7a
7680
+ .uleb128 0x2
7681
+ .byte 0x8c
7682
+ .sleb128 0
7683
+ .byte 0
7684
+ .uleb128 0x34
7685
+ .8byte .LVL373
7686
+ .4byte 0x401e
7687
+ .4byte 0x23d2
7688
+ .uleb128 0x35
7689
+ .uleb128 0x1
7690
+ .byte 0x50
7691
+ .uleb128 0x2
7692
+ .byte 0x8c
7693
+ .sleb128 0
7694
+ .uleb128 0x35
7695
+ .uleb128 0x1
7696
+ .byte 0x51
7697
+ .uleb128 0x2
7698
+ .byte 0x85
7699
+ .sleb128 0
7700
+ .uleb128 0x48
7701
+ .4byte 0x3d7a
7702
+ .uleb128 0x2
7703
+ .byte 0x8c
7704
+ .sleb128 0
7705
+ .byte 0
7706
+ .uleb128 0x34
7707
+ .8byte .LVL378
7708
+ .4byte 0x3f49
7709
+ .4byte 0x23f2
7710
+ .uleb128 0x35
7711
+ .uleb128 0x1
7712
+ .byte 0x50
7713
+ .uleb128 0x2
7714
+ .byte 0x8c
7715
+ .sleb128 0
7716
+ .uleb128 0x48
7717
+ .4byte 0x3ce6
7718
+ .uleb128 0x2
7719
+ .byte 0x8c
7720
+ .sleb128 0
7721
+ .byte 0
7722
+ .uleb128 0x34
7723
+ .8byte .LVL386
7724
+ .4byte 0x401e
7725
+ .4byte 0x2418
7726
+ .uleb128 0x35
7727
+ .uleb128 0x1
7728
+ .byte 0x50
7729
+ .uleb128 0x2
7730
+ .byte 0x8c
7731
+ .sleb128 0
7732
+ .uleb128 0x35
7733
+ .uleb128 0x1
7734
+ .byte 0x51
7735
+ .uleb128 0x2
7736
+ .byte 0x85
7737
+ .sleb128 0
7738
+ .uleb128 0x48
7739
+ .4byte 0x3d7a
7740
+ .uleb128 0x2
7741
+ .byte 0x8c
7742
+ .sleb128 0
7743
+ .byte 0
7744
+ .uleb128 0x36
7745
+ .8byte .LVL391
7746
+ .4byte 0x3fb3
7747
+ .uleb128 0x35
7748
+ .uleb128 0x1
7749
+ .byte 0x50
7750
+ .uleb128 0x2
7751
+ .byte 0x8c
7752
+ .sleb128 0
7753
+ .uleb128 0x48
7754
+ .4byte 0x3d30
7755
+ .uleb128 0x2
7756
+ .byte 0x8c
7757
+ .sleb128 0
7758
+ .byte 0
7759
+ .byte 0
7760
+ .byte 0
7761
+ .uleb128 0x40
7762
+ .4byte 0x2a52
7763
+ .8byte .LBB326
7764
+ .4byte .Ldebug_ranges0+0x660
7765
+ .byte 0x1
7766
+ .2byte 0x28c
7767
+ .4byte 0x24d7
7768
+ .uleb128 0x3a
7769
+ .4byte 0x2a87
7770
+ .4byte .LLST148
7771
+ .uleb128 0x3a
7772
+ .4byte 0x2a7b
7773
+ .4byte .LLST149
7774
+ .uleb128 0x3a
7775
+ .4byte 0x2a6f
7776
+ .4byte .LLST150
7777
+ .uleb128 0x3a
7778
+ .4byte 0x2a63
7779
+ .4byte .LLST151
7780
+ .uleb128 0x41
7781
+ .4byte .Ldebug_ranges0+0x660
7782
+ .uleb128 0x42
7783
+ .4byte 0x2a93
7784
+ .4byte .LLST152
7785
+ .uleb128 0x4a
7786
+ .4byte 0x2a9f
7787
+ .uleb128 0x2
7788
+ .byte 0x91
7789
+ .sleb128 -2
7790
+ .uleb128 0x42
7791
+ .4byte 0x2aab
7792
+ .4byte .LLST153
7793
+ .uleb128 0x34
7794
+ .8byte .LVL274
7795
+ .4byte 0x39d5
7796
+ .4byte 0x24bb
7797
+ .uleb128 0x35
7798
+ .uleb128 0x1
7799
+ .byte 0x50
7800
+ .uleb128 0x2
7801
+ .byte 0x88
7802
+ .sleb128 0
7803
+ .uleb128 0x35
7804
+ .uleb128 0x1
7805
+ .byte 0x51
7806
+ .uleb128 0x2
7807
+ .byte 0x86
7808
+ .sleb128 0
7809
+ .uleb128 0x35
7810
+ .uleb128 0x1
7811
+ .byte 0x52
7812
+ .uleb128 0x3
7813
+ .byte 0x8f
7814
+ .sleb128 254
7815
+ .uleb128 0x35
7816
+ .uleb128 0x1
7817
+ .byte 0x53
7818
+ .uleb128 0x1
7819
+ .byte 0x32
7820
+ .byte 0
7821
+ .uleb128 0x36
7822
+ .8byte .LVL279
7823
+ .4byte 0x2ab8
7824
+ .uleb128 0x35
7825
+ .uleb128 0x1
7826
+ .byte 0x50
7827
+ .uleb128 0x2
7828
+ .byte 0x88
7829
+ .sleb128 0
7830
+ .uleb128 0x35
7831
+ .uleb128 0x1
7832
+ .byte 0x51
7833
+ .uleb128 0x2
7834
+ .byte 0x8c
7835
+ .sleb128 0
7836
+ .byte 0
7837
+ .byte 0
7838
+ .byte 0
7839
+ .uleb128 0x34
7840
+ .8byte .LVL247
7841
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7842
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8463
+ .uleb128 0x11
8464
+ .4byte 0xda
8465
+ .byte 0x1f
8466
+ .byte 0
8467
+ .uleb128 0x7
8468
+ .4byte 0x2a3d
8469
+ .uleb128 0x3b
8470
+ .4byte .LASF434
8471
+ .byte 0x1
8472
+ .2byte 0x1c0
8473
+ .4byte 0x54
8474
+ .byte 0x1
8475
+ .4byte 0x2ab8
8476
+ .uleb128 0x3c
8477
+ .string "dev"
8478
+ .byte 0x1
8479
+ .2byte 0x1c0
8480
+ .4byte 0x25f
8481
+ .uleb128 0x3c
8482
+ .string "otp"
8483
+ .byte 0x1
8484
+ .2byte 0x1c1
8485
+ .4byte 0x182b
8486
+ .uleb128 0x4b
8487
+ .4byte .LASF425
8488
+ .byte 0x1
8489
+ .2byte 0x1c2
8490
+ .4byte 0x54
8491
+ .uleb128 0x4b
8492
+ .4byte .LASF387
8493
+ .byte 0x1
8494
+ .2byte 0x1c2
8495
+ .4byte 0x94
8496
+ .uleb128 0x4d
8497
+ .4byte .LASF435
8498
+ .byte 0x1
8499
+ .2byte 0x1c4
8500
+ .4byte 0xa3
8501
+ .uleb128 0x4d
8502
+ .4byte .LASF430
8503
+ .byte 0x1
8504
+ .2byte 0x1c4
8505
+ .4byte 0xa3
8506
+ .uleb128 0x4c
8507
+ .string "ret"
8508
+ .byte 0x1
8509
+ .2byte 0x1c5
8510
+ .4byte 0x54
8511
+ .byte 0
8512
+ .uleb128 0x52
8513
+ .4byte .LASF436
8514
+ .byte 0x1
8515
+ .byte 0xed
8516
+ .4byte 0x54
8517
+ .8byte .LFB269
8518
+ .8byte .LFE269-.LFB269
8519
+ .uleb128 0x1
8520
+ .byte 0x9c
8521
+ .4byte 0x39c0
8522
+ .uleb128 0x53
8523
+ .string "dev"
8524
+ .byte 0x1
8525
+ .byte 0xed
8526
+ .4byte 0x25f
8527
+ .4byte .LLST30
8528
+ .uleb128 0x53
8529
+ .string "otp"
8530
+ .byte 0x1
8531
+ .byte 0xee
8532
+ .4byte 0x182b
8533
+ .4byte .LLST31
8534
+ .uleb128 0x54
8535
+ .4byte .LASF425
8536
+ .byte 0x1
8537
+ .byte 0xef
8538
+ .4byte 0x54
8539
+ .4byte .LLST32
8540
+ .uleb128 0x54
8541
+ .4byte .LASF387
8542
+ .byte 0x1
8543
+ .byte 0xef
8544
+ .4byte 0xa3
8545
+ .4byte .LLST33
8546
+ .uleb128 0x55
8547
+ .string "ret"
8548
+ .byte 0x1
8549
+ .byte 0xf1
8550
+ .4byte 0x54
8551
+ .4byte .LLST34
8552
+ .uleb128 0x56
8553
+ .4byte .LASF426
8554
+ .byte 0x1
8555
+ .byte 0xf2
8556
+ .4byte 0x1981
8557
+ .4byte .LLST35
8558
+ .uleb128 0x57
8559
+ .4byte .LASF433
8560
+ .4byte 0x39d0
8561
+ .uleb128 0x9
8562
+ .byte 0x3
8563
+ .8byte __func__.7678
8564
+ .uleb128 0x58
8565
+ .4byte .LASF439
8566
+ .byte 0x1
8567
+ .2byte 0x1b9
8568
+ .8byte .L39
8569
+ .uleb128 0x45
8570
+ .8byte .LBB40
8571
+ .8byte .LBE40-.LBB40
8572
+ .4byte 0x2b7c
8573
+ .uleb128 0x33
8574
+ .string "__v"
8575
+ .byte 0x1
8576
+ .2byte 0x106
8577
+ .4byte 0xae
8578
+ .4byte .LLST36
8579
+ .byte 0
8580
+ .uleb128 0x45
8581
+ .8byte .LBB41
8582
+ .8byte .LBE41-.LBB41
8583
+ .4byte 0x2ba2
8584
+ .uleb128 0x33
8585
+ .string "__v"
8586
+ .byte 0x1
8587
+ .2byte 0x107
8588
+ .4byte 0xae
8589
+ .4byte .LLST37
8590
+ .byte 0
8591
+ .uleb128 0x45
8592
+ .8byte .LBB42
8593
+ .8byte .LBE42-.LBB42
8594
+ .4byte 0x2bc8
8595
+ .uleb128 0x33
8596
+ .string "__v"
8597
+ .byte 0x1
8598
+ .2byte 0x108
8599
+ .4byte 0xae
8600
+ .4byte .LLST38
8601
+ .byte 0
8602
+ .uleb128 0x45
8603
+ .8byte .LBB43
8604
+ .8byte .LBE43-.LBB43
8605
+ .4byte 0x2bee
8606
+ .uleb128 0x33
8607
+ .string "__v"
8608
+ .byte 0x1
8609
+ .2byte 0x109
8610
+ .4byte 0xae
8611
+ .4byte .LLST39
8612
+ .byte 0
8613
+ .uleb128 0x45
8614
+ .8byte .LBB44
8615
+ .8byte .LBE44-.LBB44
8616
+ .4byte 0x2c14
8617
+ .uleb128 0x33
8618
+ .string "__v"
8619
+ .byte 0x1
8620
+ .2byte 0x10a
8621
+ .4byte 0xae
8622
+ .4byte .LLST40
8623
+ .byte 0
8624
+ .uleb128 0x45
8625
+ .8byte .LBB45
8626
+ .8byte .LBE45-.LBB45
8627
+ .4byte 0x2c3a
8628
+ .uleb128 0x33
8629
+ .string "__v"
8630
+ .byte 0x1
8631
+ .2byte 0x10b
8632
+ .4byte 0xae
8633
+ .4byte .LLST41
8634
+ .byte 0
8635
+ .uleb128 0x45
8636
+ .8byte .LBB46
8637
+ .8byte .LBE46-.LBB46
8638
+ .4byte 0x2c60
8639
+ .uleb128 0x33
8640
+ .string "__v"
8641
+ .byte 0x1
8642
+ .2byte 0x10c
8643
+ .4byte 0xae
8644
+ .4byte .LLST42
8645
+ .byte 0
8646
+ .uleb128 0x45
8647
+ .8byte .LBB47
8648
+ .8byte .LBE47-.LBB47
8649
+ .4byte 0x2c86
8650
+ .uleb128 0x33
8651
+ .string "__v"
8652
+ .byte 0x1
8653
+ .2byte 0x10d
8654
+ .4byte 0xae
8655
+ .4byte .LLST43
8656
+ .byte 0
8657
+ .uleb128 0x46
8658
+ .4byte .Ldebug_ranges0+0
8659
+ .4byte 0x2ca0
8660
+ .uleb128 0x33
8661
+ .string "__v"
8662
+ .byte 0x1
8663
+ .2byte 0x10e
8664
+ .4byte 0xae
8665
+ .4byte .LLST44
8666
+ .byte 0
8667
+ .uleb128 0x45
8668
+ .8byte .LBB50
8669
+ .8byte .LBE50-.LBB50
8670
+ .4byte 0x2cc5
8671
+ .uleb128 0x59
8672
+ .string "__v"
8673
+ .byte 0x1
8674
+ .2byte 0x115
8675
+ .4byte 0xae
8676
+ .sleb128 -65522
8677
+ .byte 0
8678
+ .uleb128 0x45
8679
+ .8byte .LBB51
8680
+ .8byte .LBE51-.LBB51
8681
+ .4byte 0x2ce8
8682
+ .uleb128 0x5a
8683
+ .string "__v"
8684
+ .byte 0x1
8685
+ .2byte 0x116
8686
+ .4byte 0xae
8687
+ .byte 0xf0
8688
+ .byte 0
8689
+ .uleb128 0x45
8690
+ .8byte .LBB52
8691
+ .8byte .LBE52-.LBB52
8692
+ .4byte 0x2d0b
8693
+ .uleb128 0x5a
8694
+ .string "__v"
8695
+ .byte 0x1
8696
+ .2byte 0x117
8697
+ .4byte 0xae
8698
+ .byte 0x1
8699
+ .byte 0
8700
+ .uleb128 0x45
8701
+ .8byte .LBB53
8702
+ .8byte .LBE53-.LBB53
8703
+ .4byte 0x2d2e
8704
+ .uleb128 0x5a
8705
+ .string "__v"
8706
+ .byte 0x1
8707
+ .2byte 0x118
8708
+ .4byte 0xae
8709
+ .byte 0x7a
8710
+ .byte 0
8711
+ .uleb128 0x45
8712
+ .8byte .LBB54
8713
+ .8byte .LBE54-.LBB54
8714
+ .4byte 0x2d51
8715
+ .uleb128 0x5a
8716
+ .string "__v"
8717
+ .byte 0x1
8718
+ .2byte 0x119
8719
+ .4byte 0xae
8720
+ .byte 0x25
8721
+ .byte 0
8722
+ .uleb128 0x45
8723
+ .8byte .LBB55
8724
+ .8byte .LBE55-.LBB55
8725
+ .4byte 0x2d74
8726
+ .uleb128 0x5a
8727
+ .string "__v"
8728
+ .byte 0x1
8729
+ .2byte 0x11a
8730
+ .4byte 0xae
8731
+ .byte 0
8732
+ .byte 0
8733
+ .uleb128 0x45
8734
+ .8byte .LBB56
8735
+ .8byte .LBE56-.LBB56
8736
+ .4byte 0x2d97
8737
+ .uleb128 0x5a
8738
+ .string "__v"
8739
+ .byte 0x1
8740
+ .2byte 0x11b
8741
+ .4byte 0xae
8742
+ .byte 0
8743
+ .byte 0
8744
+ .uleb128 0x45
8745
+ .8byte .LBB57
8746
+ .8byte .LBE57-.LBB57
8747
+ .4byte 0x2dba
8748
+ .uleb128 0x5a
8749
+ .string "__v"
8750
+ .byte 0x1
8751
+ .2byte 0x11c
8752
+ .4byte 0xae
8753
+ .byte 0
8754
+ .byte 0
8755
+ .uleb128 0x45
8756
+ .8byte .LBB58
8757
+ .8byte .LBE58-.LBB58
8758
+ .4byte 0x2ddd
8759
+ .uleb128 0x5a
8760
+ .string "__v"
8761
+ .byte 0x1
8762
+ .2byte 0x11d
8763
+ .4byte 0xae
8764
+ .byte 0x1f
8765
+ .byte 0
8766
+ .uleb128 0x45
8767
+ .8byte .LBB59
8768
+ .8byte .LBE59-.LBB59
8769
+ .4byte 0x2e00
8770
+ .uleb128 0x5a
8771
+ .string "__v"
8772
+ .byte 0x1
8773
+ .2byte 0x11e
8774
+ .4byte 0xae
8775
+ .byte 0xb
8776
+ .byte 0
8777
+ .uleb128 0x45
8778
+ .8byte .LBB60
8779
+ .8byte .LBE60-.LBB60
8780
+ .4byte 0x2e23
8781
+ .uleb128 0x5a
8782
+ .string "__v"
8783
+ .byte 0x1
8784
+ .2byte 0x11f
8785
+ .4byte 0xae
8786
+ .byte 0x8
8787
+ .byte 0
8788
+ .uleb128 0x45
8789
+ .8byte .LBB61
8790
+ .8byte .LBE61-.LBB61
8791
+ .4byte 0x2e46
8792
+ .uleb128 0x5a
8793
+ .string "__v"
8794
+ .byte 0x1
8795
+ .2byte 0x120
8796
+ .4byte 0xae
8797
+ .byte 0
8798
+ .byte 0
8799
+ .uleb128 0x45
8800
+ .8byte .LBB62
8801
+ .8byte .LBE62-.LBB62
8802
+ .4byte 0x2e69
8803
+ .uleb128 0x5a
8804
+ .string "__v"
8805
+ .byte 0x1
8806
+ .2byte 0x121
8807
+ .4byte 0xae
8808
+ .byte 0
8809
+ .byte 0
8810
+ .uleb128 0x45
8811
+ .8byte .LBB63
8812
+ .8byte .LBE63-.LBB63
8813
+ .4byte 0x2e8c
8814
+ .uleb128 0x5a
8815
+ .string "__v"
8816
+ .byte 0x1
8817
+ .2byte 0x122
8818
+ .4byte 0xae
8819
+ .byte 0
8820
+ .byte 0
8821
+ .uleb128 0x46
8822
+ .4byte .Ldebug_ranges0+0x30
8823
+ .4byte 0x2ea4
8824
+ .uleb128 0x5b
8825
+ .string "__v"
8826
+ .byte 0x1
8827
+ .2byte 0x123
8828
+ .4byte 0xae
8829
+ .uleb128 0x1
8830
+ .byte 0x50
8831
+ .byte 0
8832
+ .uleb128 0x46
8833
+ .4byte .Ldebug_ranges0+0x60
8834
+ .4byte 0x2ebe
8835
+ .uleb128 0x33
8836
+ .string "__v"
8837
+ .byte 0x1
8838
+ .2byte 0x124
8839
+ .4byte 0xae
8840
+ .4byte .LLST45
8841
+ .byte 0
8842
+ .uleb128 0x46
8843
+ .4byte .Ldebug_ranges0+0x90
8844
+ .4byte 0x2ed8
8845
+ .uleb128 0x5c
8846
+ .string "__v"
8847
+ .byte 0x1
8848
+ .2byte 0x125
8849
+ .4byte 0xae
8850
+ .4byte 0x10001
8851
+ .byte 0
8852
+ .uleb128 0x45
8853
+ .8byte .LBB70
8854
+ .8byte .LBE70-.LBB70
8855
+ .4byte 0x2efd
8856
+ .uleb128 0x59
8857
+ .string "__v"
8858
+ .byte 0x1
8859
+ .2byte 0x12c
8860
+ .4byte 0xae
8861
+ .sleb128 -65535
8862
+ .byte 0
8863
+ .uleb128 0x45
8864
+ .8byte .LBB71
8865
+ .8byte .LBE71-.LBB71
8866
+ .4byte 0x2f20
8867
+ .uleb128 0x5a
8868
+ .string "__v"
8869
+ .byte 0x1
8870
+ .2byte 0x12d
8871
+ .4byte 0xae
8872
+ .byte 0xfa
8873
+ .byte 0
8874
+ .uleb128 0x45
8875
+ .8byte .LBB72
8876
+ .8byte .LBE72-.LBB72
8877
+ .4byte 0x2f43
8878
+ .uleb128 0x5a
8879
+ .string "__v"
8880
+ .byte 0x1
8881
+ .2byte 0x12e
8882
+ .4byte 0xae
8883
+ .byte 0x9
8884
+ .byte 0
8885
+ .uleb128 0x46
8886
+ .4byte .Ldebug_ranges0+0xc0
8887
+ .4byte 0x2f5d
8888
+ .uleb128 0x5c
8889
+ .string "__v"
8890
+ .byte 0x1
8891
+ .2byte 0x12f
8892
+ .4byte 0xae
8893
+ .4byte 0x10001
8894
+ .byte 0
8895
+ .uleb128 0x45
8896
+ .8byte .LBB75
8897
+ .8byte .LBE75-.LBB75
8898
+ .4byte 0x2f83
8899
+ .uleb128 0x59
8900
+ .string "__v"
8901
+ .byte 0x1
8902
+ .2byte 0x136
8903
+ .4byte 0xae
8904
+ .sleb128 -16762368
8905
+ .byte 0
8906
+ .uleb128 0x45
8907
+ .8byte .LBB76
8908
+ .8byte .LBE76-.LBB76
8909
+ .4byte 0x2fa8
8910
+ .uleb128 0x59
8911
+ .string "__v"
8912
+ .byte 0x1
8913
+ .2byte 0x137
8914
+ .4byte 0xae
8915
+ .sleb128 -65522
8916
+ .byte 0
8917
+ .uleb128 0x45
8918
+ .8byte .LBB77
8919
+ .8byte .LBE77-.LBB77
8920
+ .4byte 0x2fcb
8921
+ .uleb128 0x5a
8922
+ .string "__v"
8923
+ .byte 0x1
8924
+ .2byte 0x138
8925
+ .4byte 0xae
8926
+ .byte 0xf0
8927
+ .byte 0
8928
+ .uleb128 0x45
8929
+ .8byte .LBB78
8930
+ .8byte .LBE78-.LBB78
8931
+ .4byte 0x2fee
8932
+ .uleb128 0x5a
8933
+ .string "__v"
8934
+ .byte 0x1
8935
+ .2byte 0x139
8936
+ .4byte 0xae
8937
+ .byte 0x1
8938
+ .byte 0
8939
+ .uleb128 0x45
8940
+ .8byte .LBB79
8941
+ .8byte .LBE79-.LBB79
8942
+ .4byte 0x3011
8943
+ .uleb128 0x5a
8944
+ .string "__v"
8945
+ .byte 0x1
8946
+ .2byte 0x13a
8947
+ .4byte 0xae
8948
+ .byte 0x7a
8949
+ .byte 0
8950
+ .uleb128 0x45
8951
+ .8byte .LBB80
8952
+ .8byte .LBE80-.LBB80
8953
+ .4byte 0x3034
8954
+ .uleb128 0x5a
8955
+ .string "__v"
8956
+ .byte 0x1
8957
+ .2byte 0x13b
8958
+ .4byte 0xae
8959
+ .byte 0x15
8960
+ .byte 0
8961
+ .uleb128 0x45
8962
+ .8byte .LBB81
8963
+ .8byte .LBE81-.LBB81
8964
+ .4byte 0x3057
8965
+ .uleb128 0x5a
8966
+ .string "__v"
8967
+ .byte 0x1
8968
+ .2byte 0x13c
8969
+ .4byte 0xae
8970
+ .byte 0xdc
8971
+ .byte 0
8972
+ .uleb128 0x45
8973
+ .8byte .LBB82
8974
+ .8byte .LBE82-.LBB82
8975
+ .4byte 0x307a
8976
+ .uleb128 0x5a
8977
+ .string "__v"
8978
+ .byte 0x1
8979
+ .2byte 0x13d
8980
+ .4byte 0xae
8981
+ .byte 0x92
8982
+ .byte 0
8983
+ .uleb128 0x45
8984
+ .8byte .LBB83
8985
+ .8byte .LBE83-.LBB83
8986
+ .4byte 0x309d
8987
+ .uleb128 0x5a
8988
+ .string "__v"
8989
+ .byte 0x1
8990
+ .2byte 0x13e
8991
+ .4byte 0xae
8992
+ .byte 0x79
8993
+ .byte 0
8994
+ .uleb128 0x45
8995
+ .8byte .LBB84
8996
+ .8byte .LBE84-.LBB84
8997
+ .4byte 0x30c0
8998
+ .uleb128 0x5a
8999
+ .string "__v"
9000
+ .byte 0x1
9001
+ .2byte 0x13f
9002
+ .4byte 0xae
9003
+ .byte 0x81
9004
+ .byte 0
9005
+ .uleb128 0x45
9006
+ .8byte .LBB85
9007
+ .8byte .LBE85-.LBB85
9008
+ .4byte 0x30e3
9009
+ .uleb128 0x5a
9010
+ .string "__v"
9011
+ .byte 0x1
9012
+ .2byte 0x140
9013
+ .4byte 0xae
9014
+ .byte 0x7e
9015
+ .byte 0
9016
+ .uleb128 0x45
9017
+ .8byte .LBB86
9018
+ .8byte .LBE86-.LBB86
9019
+ .4byte 0x3106
9020
+ .uleb128 0x5a
9021
+ .string "__v"
9022
+ .byte 0x1
9023
+ .2byte 0x141
9024
+ .4byte 0xae
9025
+ .byte 0x21
9026
+ .byte 0
9027
+ .uleb128 0x45
9028
+ .8byte .LBB87
9029
+ .8byte .LBE87-.LBB87
9030
+ .4byte 0x3129
9031
+ .uleb128 0x5a
9032
+ .string "__v"
9033
+ .byte 0x1
9034
+ .2byte 0x142
9035
+ .4byte 0xae
9036
+ .byte 0x11
9037
+ .byte 0
9038
+ .uleb128 0x45
9039
+ .8byte .LBB88
9040
+ .8byte .LBE88-.LBB88
9041
+ .4byte 0x314c
9042
+ .uleb128 0x5a
9043
+ .string "__v"
9044
+ .byte 0x1
9045
+ .2byte 0x143
9046
+ .4byte 0xae
9047
+ .byte 0x9d
9048
+ .byte 0
9049
+ .uleb128 0x45
9050
+ .8byte .LBB89
9051
+ .8byte .LBE89-.LBB89
9052
+ .4byte 0x316f
9053
+ .uleb128 0x5a
9054
+ .string "__v"
9055
+ .byte 0x1
9056
+ .2byte 0x144
9057
+ .4byte 0xae
9058
+ .byte 0x2
9059
+ .byte 0
9060
+ .uleb128 0x45
9061
+ .8byte .LBB90
9062
+ .8byte .LBE90-.LBB90
9063
+ .4byte 0x3192
9064
+ .uleb128 0x5a
9065
+ .string "__v"
9066
+ .byte 0x1
9067
+ .2byte 0x145
9068
+ .4byte 0xae
9069
+ .byte 0
9070
+ .byte 0
9071
+ .uleb128 0x45
9072
+ .8byte .LBB91
9073
+ .8byte .LBE91-.LBB91
9074
+ .4byte 0x31b5
9075
+ .uleb128 0x5a
9076
+ .string "__v"
9077
+ .byte 0x1
9078
+ .2byte 0x146
9079
+ .4byte 0xae
9080
+ .byte 0x40
9081
+ .byte 0
9082
+ .uleb128 0x46
9083
+ .4byte .Ldebug_ranges0+0xf0
9084
+ .4byte 0x31cf
9085
+ .uleb128 0x5c
9086
+ .string "__v"
9087
+ .byte 0x1
9088
+ .2byte 0x147
9089
+ .4byte 0xae
9090
+ .4byte 0x10001
9091
+ .byte 0
9092
+ .uleb128 0x45
9093
+ .8byte .LBB94
9094
+ .8byte .LBE94-.LBB94
9095
+ .4byte 0x31f4
9096
+ .uleb128 0x59
9097
+ .string "__v"
9098
+ .byte 0x1
9099
+ .2byte 0x14e
9100
+ .4byte 0xae
9101
+ .sleb128 -65534
9102
+ .byte 0
9103
+ .uleb128 0x45
9104
+ .8byte .LBB95
9105
+ .8byte .LBE95-.LBB95
9106
+ .4byte 0x3217
9107
+ .uleb128 0x5a
9108
+ .string "__v"
9109
+ .byte 0x1
9110
+ .2byte 0x14f
9111
+ .4byte 0xae
9112
+ .byte 0xfc
9113
+ .byte 0
9114
+ .uleb128 0x45
9115
+ .8byte .LBB96
9116
+ .8byte .LBE96-.LBB96
9117
+ .4byte 0x323a
9118
+ .uleb128 0x5a
9119
+ .string "__v"
9120
+ .byte 0x1
9121
+ .2byte 0x150
9122
+ .4byte 0xae
9123
+ .byte 0xa
9124
+ .byte 0
9125
+ .uleb128 0x45
9126
+ .8byte .LBB97
9127
+ .8byte .LBE97-.LBB97
9128
+ .4byte 0x325d
9129
+ .uleb128 0x5a
9130
+ .string "__v"
9131
+ .byte 0x1
9132
+ .2byte 0x151
9133
+ .4byte 0xae
9134
+ .byte 0x70
9135
+ .byte 0
9136
+ .uleb128 0x46
9137
+ .4byte .Ldebug_ranges0+0x120
9138
+ .4byte 0x3277
9139
+ .uleb128 0x5c
9140
+ .string "__v"
9141
+ .byte 0x1
9142
+ .2byte 0x152
9143
+ .4byte 0xae
9144
+ .4byte 0x10001
9145
+ .byte 0
9146
+ .uleb128 0x45
9147
+ .8byte .LBB100
9148
+ .8byte .LBE100-.LBB100
9149
+ .4byte 0x329d
9150
+ .uleb128 0x59
9151
+ .string "__v"
9152
+ .byte 0x1
9153
+ .2byte 0x159
9154
+ .4byte 0xae
9155
+ .sleb128 -16776704
9156
+ .byte 0
9157
+ .uleb128 0x45
9158
+ .8byte .LBB101
9159
+ .8byte .LBE101-.LBB101
9160
+ .4byte 0x32c2
9161
+ .uleb128 0x59
9162
+ .string "__v"
9163
+ .byte 0x1
9164
+ .2byte 0x15a
9165
+ .4byte 0xae
9166
+ .sleb128 -65534
9167
+ .byte 0
9168
+ .uleb128 0x45
9169
+ .8byte .LBB102
9170
+ .8byte .LBE102-.LBB102
9171
+ .4byte 0x32e5
9172
+ .uleb128 0x5a
9173
+ .string "__v"
9174
+ .byte 0x1
9175
+ .2byte 0x15b
9176
+ .4byte 0xae
9177
+ .byte 0xc0
9178
+ .byte 0
9179
+ .uleb128 0x46
9180
+ .4byte .Ldebug_ranges0+0x150
9181
+ .4byte 0x32ff
9182
+ .uleb128 0x33
9183
+ .string "__v"
9184
+ .byte 0x1
9185
+ .2byte 0x15c
9186
+ .4byte 0xae
9187
+ .4byte .LLST46
9188
+ .byte 0
9189
+ .uleb128 0x46
9190
+ .4byte .Ldebug_ranges0+0x180
9191
+ .4byte 0x3319
9192
+ .uleb128 0x33
9193
+ .string "__v"
9194
+ .byte 0x1
9195
+ .2byte 0x15d
9196
+ .4byte 0xae
9197
+ .4byte .LLST47
9198
+ .byte 0
9199
+ .uleb128 0x46
9200
+ .4byte .Ldebug_ranges0+0x1b0
9201
+ .4byte 0x3333
9202
+ .uleb128 0x5c
9203
+ .string "__v"
9204
+ .byte 0x1
9205
+ .2byte 0x15e
9206
+ .4byte 0xae
9207
+ .4byte 0x10001
9208
+ .byte 0
9209
+ .uleb128 0x45
9210
+ .8byte .LBB109
9211
+ .8byte .LBE109-.LBB109
9212
+ .4byte 0x3358
9213
+ .uleb128 0x59
9214
+ .string "__v"
9215
+ .byte 0x1
9216
+ .2byte 0x165
9217
+ .4byte 0xae
9218
+ .sleb128 -65535
9219
+ .byte 0
9220
+ .uleb128 0x45
9221
+ .8byte .LBB110
9222
+ .8byte .LBE110-.LBB110
9223
+ .4byte 0x337b
9224
+ .uleb128 0x5a
9225
+ .string "__v"
9226
+ .byte 0x1
9227
+ .2byte 0x166
9228
+ .4byte 0xae
9229
+ .byte 0xe0
9230
+ .byte 0
9231
+ .uleb128 0x45
9232
+ .8byte .LBB111
9233
+ .8byte .LBE111-.LBB111
9234
+ .4byte 0x339e
9235
+ .uleb128 0x5a
9236
+ .string "__v"
9237
+ .byte 0x1
9238
+ .2byte 0x167
9239
+ .4byte 0xae
9240
+ .byte 0
9241
+ .byte 0
9242
+ .uleb128 0x46
9243
+ .4byte .Ldebug_ranges0+0x1e0
9244
+ .4byte 0x33b8
9245
+ .uleb128 0x5c
9246
+ .string "__v"
9247
+ .byte 0x1
9248
+ .2byte 0x168
9249
+ .4byte 0xae
9250
+ .4byte 0x10001
9251
+ .byte 0
9252
+ .uleb128 0x45
9253
+ .8byte .LBB114
9254
+ .8byte .LBE114-.LBB114
9255
+ .4byte 0x33dd
9256
+ .uleb128 0x59
9257
+ .string "__v"
9258
+ .byte 0x1
9259
+ .2byte 0x16f
9260
+ .4byte 0xae
9261
+ .sleb128 -65535
9262
+ .byte 0
9263
+ .uleb128 0x45
9264
+ .8byte .LBB115
9265
+ .8byte .LBE115-.LBB115
9266
+ .4byte 0x3403
9267
+ .uleb128 0x59
9268
+ .string "__v"
9269
+ .byte 0x1
9270
+ .2byte 0x170
9271
+ .4byte 0xae
9272
+ .sleb128 -16762368
9273
+ .byte 0
9274
+ .uleb128 0x45
9275
+ .8byte .LBB116
9276
+ .8byte .LBE116-.LBB116
9277
+ .4byte 0x3426
9278
+ .uleb128 0x5a
9279
+ .string "__v"
9280
+ .byte 0x1
9281
+ .2byte 0x171
9282
+ .4byte 0xae
9283
+ .byte 0xff
9284
+ .byte 0
9285
+ .uleb128 0x45
9286
+ .8byte .LBB117
9287
+ .8byte .LBE117-.LBB117
9288
+ .4byte 0x3449
9289
+ .uleb128 0x5a
9290
+ .string "__v"
9291
+ .byte 0x1
9292
+ .2byte 0x172
9293
+ .4byte 0xae
9294
+ .byte 0xa
9295
+ .byte 0
9296
+ .uleb128 0x46
9297
+ .4byte .Ldebug_ranges0+0x210
9298
+ .4byte 0x3463
9299
+ .uleb128 0x5c
9300
+ .string "__v"
9301
+ .byte 0x1
9302
+ .2byte 0x173
9303
+ .4byte 0xae
9304
+ .4byte 0x10001
9305
+ .byte 0
9306
+ .uleb128 0x45
9307
+ .8byte .LBB120
9308
+ .8byte .LBE120-.LBB120
9309
+ .4byte 0x3488
9310
+ .uleb128 0x59
9311
+ .string "__v"
9312
+ .byte 0x1
9313
+ .2byte 0x17a
9314
+ .4byte 0xae
9315
+ .sleb128 -65535
9316
+ .byte 0
9317
+ .uleb128 0x45
9318
+ .8byte .LBB121
9319
+ .8byte .LBE121-.LBB121
9320
+ .4byte 0x34ab
9321
+ .uleb128 0x5a
9322
+ .string "__v"
9323
+ .byte 0x1
9324
+ .2byte 0x17b
9325
+ .4byte 0xae
9326
+ .byte 0x1
9327
+ .byte 0
9328
+ .uleb128 0x45
9329
+ .8byte .LBB122
9330
+ .8byte .LBE122-.LBB122
9331
+ .4byte 0x34ce
9332
+ .uleb128 0x5a
9333
+ .string "__v"
9334
+ .byte 0x1
9335
+ .2byte 0x17c
9336
+ .4byte 0xae
9337
+ .byte 0xbf
9338
+ .byte 0
9339
+ .uleb128 0x46
9340
+ .4byte .Ldebug_ranges0+0x240
9341
+ .4byte 0x34e8
9342
+ .uleb128 0x5c
9343
+ .string "__v"
9344
+ .byte 0x1
9345
+ .2byte 0x17d
9346
+ .4byte 0xae
9347
+ .4byte 0x10001
9348
+ .byte 0
9349
+ .uleb128 0x45
9350
+ .8byte .LBB125
9351
+ .8byte .LBE125-.LBB125
9352
+ .4byte 0x350d
9353
+ .uleb128 0x59
9354
+ .string "__v"
9355
+ .byte 0x1
9356
+ .2byte 0x18a
9357
+ .4byte 0xae
9358
+ .sleb128 -65535
9359
+ .byte 0
9360
+ .uleb128 0x45
9361
+ .8byte .LBB126
9362
+ .8byte .LBE126-.LBB126
9363
+ .4byte 0x3530
9364
+ .uleb128 0x5a
9365
+ .string "__v"
9366
+ .byte 0x1
9367
+ .2byte 0x18b
9368
+ .4byte 0xae
9369
+ .byte 0x2
9370
+ .byte 0
9371
+ .uleb128 0x45
9372
+ .8byte .LBB127
9373
+ .8byte .LBE127-.LBB127
9374
+ .4byte 0x3553
9375
+ .uleb128 0x5a
9376
+ .string "__v"
9377
+ .byte 0x1
9378
+ .2byte 0x18c
9379
+ .4byte 0xae
9380
+ .byte 0xbf
9381
+ .byte 0
9382
+ .uleb128 0x46
9383
+ .4byte .Ldebug_ranges0+0x270
9384
+ .4byte 0x356d
9385
+ .uleb128 0x5c
9386
+ .string "__v"
9387
+ .byte 0x1
9388
+ .2byte 0x18d
9389
+ .4byte 0xae
9390
+ .4byte 0x10001
9391
+ .byte 0
9392
+ .uleb128 0x45
9393
+ .8byte .LBB130
9394
+ .8byte .LBE130-.LBB130
9395
+ .4byte 0x3592
9396
+ .uleb128 0x59
9397
+ .string "__v"
9398
+ .byte 0x1
9399
+ .2byte 0x19a
9400
+ .4byte 0xae
9401
+ .sleb128 -65533
9402
+ .byte 0
9403
+ .uleb128 0x45
9404
+ .8byte .LBB131
9405
+ .8byte .LBE131-.LBB131
9406
+ .4byte 0x35b8
9407
+ .uleb128 0x59
9408
+ .string "__v"
9409
+ .byte 0x1
9410
+ .2byte 0x19b
9411
+ .4byte 0xae
9412
+ .sleb128 -16776704
9413
+ .byte 0
9414
+ .uleb128 0x45
9415
+ .8byte .LBB132
9416
+ .8byte .LBE132-.LBB132
9417
+ .4byte 0x35dd
9418
+ .uleb128 0x59
9419
+ .string "__v"
9420
+ .byte 0x1
9421
+ .2byte 0x19c
9422
+ .4byte 0xae
9423
+ .sleb128 -65535
9424
+ .byte 0
9425
+ .uleb128 0x45
9426
+ .8byte .LBB133
9427
+ .8byte .LBE133-.LBB133
9428
+ .4byte 0x3600
9429
+ .uleb128 0x5a
9430
+ .string "__v"
9431
+ .byte 0x1
9432
+ .2byte 0x19d
9433
+ .4byte 0xae
9434
+ .byte 0x2
9435
+ .byte 0
9436
+ .uleb128 0x45
9437
+ .8byte .LBB134
9438
+ .8byte .LBE134-.LBB134
9439
+ .4byte 0x3623
9440
+ .uleb128 0x5a
9441
+ .string "__v"
9442
+ .byte 0x1
9443
+ .2byte 0x19e
9444
+ .4byte 0xae
9445
+ .byte 0x80
9446
+ .byte 0
9447
+ .uleb128 0x46
9448
+ .4byte .Ldebug_ranges0+0x2a0
9449
+ .4byte 0x363d
9450
+ .uleb128 0x5c
9451
+ .string "__v"
9452
+ .byte 0x1
9453
+ .2byte 0x19f
9454
+ .4byte 0xae
9455
+ .4byte 0x10001
9456
+ .byte 0
9457
+ .uleb128 0x45
9458
+ .8byte .LBB137
9459
+ .8byte .LBE137-.LBB137
9460
+ .4byte 0x3662
9461
+ .uleb128 0x59
9462
+ .string "__v"
9463
+ .byte 0x1
9464
+ .2byte 0x1a6
9465
+ .4byte 0xae
9466
+ .sleb128 -65535
9467
+ .byte 0
9468
+ .uleb128 0x45
9469
+ .8byte .LBB138
9470
+ .8byte .LBE138-.LBB138
9471
+ .4byte 0x3685
9472
+ .uleb128 0x5a
9473
+ .string "__v"
9474
+ .byte 0x1
9475
+ .2byte 0x1a7
9476
+ .4byte 0xae
9477
+ .byte 0xa0
9478
+ .byte 0
9479
+ .uleb128 0x45
9480
+ .8byte .LBB139
9481
+ .8byte .LBE139-.LBB139
9482
+ .4byte 0x36a8
9483
+ .uleb128 0x5a
9484
+ .string "__v"
9485
+ .byte 0x1
9486
+ .2byte 0x1a8
9487
+ .4byte 0xae
9488
+ .byte 0
9489
+ .byte 0
9490
+ .uleb128 0x46
9491
+ .4byte .Ldebug_ranges0+0x2d0
9492
+ .4byte 0x36c2
9493
+ .uleb128 0x5c
9494
+ .string "__v"
9495
+ .byte 0x1
9496
+ .2byte 0x1a9
9497
+ .4byte 0xae
9498
+ .4byte 0x10001
9499
+ .byte 0
9500
+ .uleb128 0x45
9501
+ .8byte .LBB142
9502
+ .8byte .LBE142-.LBB142
9503
+ .4byte 0x36e5
9504
+ .uleb128 0x5a
9505
+ .string "__v"
9506
+ .byte 0x1
9507
+ .2byte 0x1b0
9508
+ .4byte 0xae
9509
+ .byte 0xfa
9510
+ .byte 0
9511
+ .uleb128 0x45
9512
+ .8byte .LBB143
9513
+ .8byte .LBE143-.LBB143
9514
+ .4byte 0x3708
9515
+ .uleb128 0x5a
9516
+ .string "__v"
9517
+ .byte 0x1
9518
+ .2byte 0x1b1
9519
+ .4byte 0xae
9520
+ .byte 0x9
9521
+ .byte 0
9522
+ .uleb128 0x46
9523
+ .4byte .Ldebug_ranges0+0x300
9524
+ .4byte 0x3722
9525
+ .uleb128 0x5c
9526
+ .string "__v"
9527
+ .byte 0x1
9528
+ .2byte 0x1b2
9529
+ .4byte 0xae
9530
+ .4byte 0x10001
9531
+ .byte 0
9532
+ .uleb128 0x34
9533
+ .8byte .LVL67
9534
+ .4byte 0x42ab
9535
+ .4byte 0x373b
9536
+ .uleb128 0x35
9537
+ .uleb128 0x1
9538
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9539
+ .uleb128 0x3
9540
+ .byte 0xf3
9541
+ .uleb128 0x1
9542
+ .byte 0x50
9543
+ .byte 0
9544
+ .uleb128 0x34
9545
+ .8byte .LVL69
9546
+ .4byte 0x42b7
9547
+ .4byte 0x3763
9548
+ .uleb128 0x35
9549
+ .uleb128 0x1
9550
+ .byte 0x50
9551
+ .uleb128 0x9
9552
+ .byte 0x3
9553
+ .8byte .LC4
9554
+ .uleb128 0x35
9555
+ .uleb128 0x1
9556
+ .byte 0x51
9557
+ .uleb128 0x5
9558
+ .byte 0x88
9559
+ .sleb128 0
9560
+ .byte 0x9
9561
+ .byte 0xfe
9562
+ .byte 0x1a
9563
+ .byte 0
9564
+ .uleb128 0x47
9565
+ .8byte .LVL74
9566
+ .4byte 0x3777
9567
+ .uleb128 0x35
9568
+ .uleb128 0x1
9569
+ .byte 0x53
9570
+ .uleb128 0x2
9571
+ .byte 0x84
9572
+ .sleb128 0
9573
+ .byte 0
9574
+ .uleb128 0x34
9575
+ .8byte .LVL83
9576
+ .4byte 0x401e
9577
+ .4byte 0x379c
9578
+ .uleb128 0x35
9579
+ .uleb128 0x1
9580
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9581
+ .uleb128 0x2
9582
+ .byte 0x8a
9583
+ .sleb128 0
9584
+ .uleb128 0x35
9585
+ .uleb128 0x1
9586
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9587
+ .uleb128 0x1
9588
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9589
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9590
+ .4byte 0x3d7a
9591
+ .uleb128 0x2
9592
+ .byte 0x8a
9593
+ .sleb128 0
9594
+ .byte 0
9595
+ .uleb128 0x49
9596
+ .8byte .LVL85
9597
+ .4byte 0x42b7
9598
+ .uleb128 0x47
9599
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9600
+ .4byte 0x37bd
9601
+ .uleb128 0x35
9602
+ .uleb128 0x1
9603
+ .byte 0x53
9604
+ .uleb128 0x2
9605
+ .byte 0x84
9606
+ .sleb128 0
9607
+ .byte 0
9608
+ .uleb128 0x34
9609
+ .8byte .LVL104
9610
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9611
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9612
+ .uleb128 0x35
9613
+ .uleb128 0x1
9614
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9615
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9616
+ .byte 0x8a
9617
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9618
+ .uleb128 0x35
9619
+ .uleb128 0x1
9620
+ .byte 0x51
9621
+ .uleb128 0x1
9622
+ .byte 0x32
9623
+ .uleb128 0x48
9624
+ .4byte 0x3d7a
9625
+ .uleb128 0x2
9626
+ .byte 0x8a
9627
+ .sleb128 0
9628
+ .byte 0
9629
+ .uleb128 0x34
9630
+ .8byte .LVL110
9631
+ .4byte 0x401e
9632
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9633
+ .uleb128 0x35
9634
+ .uleb128 0x1
9635
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9636
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9637
+ .byte 0x8a
9638
+ .sleb128 0
9639
+ .uleb128 0x35
9640
+ .uleb128 0x1
9641
+ .byte 0x51
9642
+ .uleb128 0x1
9643
+ .byte 0x32
9644
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9645
+ .4byte 0x3d7a
9646
+ .uleb128 0x2
9647
+ .byte 0x8a
9648
+ .sleb128 0
9649
+ .byte 0
9650
+ .uleb128 0x34
9651
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9652
+ .4byte 0x401e
9653
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9654
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9655
+ .uleb128 0x1
9656
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9657
+ .uleb128 0x2
9658
+ .byte 0x8a
9659
+ .sleb128 0
9660
+ .uleb128 0x35
9661
+ .uleb128 0x1
9662
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9663
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9664
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9665
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9666
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9667
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9668
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9669
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9670
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9671
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9672
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9673
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9674
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9675
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9676
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9677
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9678
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9679
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9680
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9681
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9682
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9683
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9684
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9685
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9686
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9687
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9688
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9689
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9690
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9691
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9692
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9693
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9694
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9695
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9696
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9697
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9698
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9699
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9700
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9701
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9702
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9703
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9704
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9705
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9706
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9707
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9708
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9709
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9710
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9711
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9712
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9713
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9714
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9715
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9716
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9717
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9718
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9719
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9720
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9721
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9722
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9723
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9724
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9725
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9726
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9727
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9728
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9729
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9730
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9731
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9732
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9733
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9734
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9735
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9736
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9737
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9738
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9739
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9740
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9741
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9742
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9743
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9744
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9745
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9746
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9747
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9748
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9749
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9750
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9751
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9752
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9753
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9754
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9755
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9756
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9757
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9758
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9759
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9760
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9761
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9762
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9763
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9764
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9765
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9766
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9767
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9768
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9769
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9770
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9771
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9772
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9773
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9774
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9775
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9776
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9777
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9778
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9779
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9780
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9781
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9782
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9783
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9784
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9785
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9786
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9787
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9788
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9789
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9790
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9791
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9792
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9793
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9794
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9795
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9796
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9797
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9798
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9799
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9800
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9801
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9802
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9803
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9804
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9805
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9806
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9807
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9808
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9809
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9810
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9811
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9812
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9813
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9814
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9815
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9816
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9817
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9818
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9819
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9820
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9821
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9822
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9823
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9824
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9825
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9826
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9827
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9828
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9829
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9830
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9831
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9832
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9833
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9834
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9835
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9836
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9837
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9838
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9839
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9840
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9841
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9842
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9843
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9844
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9845
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9846
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9847
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9848
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9849
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9850
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9851
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9852
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9853
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9854
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9855
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9856
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9857
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9858
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9859
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9860
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9861
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9862
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9863
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9864
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9865
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9866
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9867
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9868
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9869
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9870
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9871
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9872
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9873
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9874
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9875
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9876
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9877
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9878
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9879
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9880
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9881
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9882
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9883
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9884
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9885
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9886
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9887
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9888
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9889
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9890
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9891
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9892
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9893
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9894
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9895
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9896
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9897
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9898
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9899
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9900
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9901
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9902
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9903
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9904
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9905
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9906
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9907
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9908
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9909
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9910
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9911
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9912
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9913
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9914
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9915
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9916
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9917
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9918
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9919
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9920
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9921
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9922
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9923
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9924
+ .byte 0xae
9925
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9926
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9927
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9928
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9929
+ .byte 0x1
9930
+ .byte 0xae
9931
+ .4byte 0x54
9932
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9933
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9934
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9935
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9936
+ .byte 0xaf
9937
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9938
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9939
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9940
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9941
+ .byte 0x1
9942
+ .byte 0xaf
9943
+ .4byte 0x54
9944
+ .4byte .LLST58
9945
+ .uleb128 0x55
9946
+ .string "otp"
9947
+ .byte 0x1
9948
+ .byte 0xb1
9949
+ .4byte 0x182b
9950
+ .4byte .LLST59
9951
+ .uleb128 0x56
9952
+ .4byte .LASF387
9953
+ .byte 0x1
9954
+ .byte 0xb2
9955
+ .4byte 0x1981
9956
+ .4byte .LLST60
9957
+ .uleb128 0x56
9958
+ .4byte .LASF438
9959
+ .byte 0x1
9960
+ .byte 0xb3
9961
+ .4byte 0x11cc
9962
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9963
+ .uleb128 0x56
9964
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9965
+ .byte 0x1
9966
+ .byte 0xb4
9967
+ .4byte 0xa3
9968
+ .4byte .LLST62
9969
+ .uleb128 0x55
9970
+ .string "ret"
9971
+ .byte 0x1
9972
+ .byte 0xb5
9973
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9974
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9975
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9976
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9977
+ .4byte 0x3c1b
9978
+ .uleb128 0x9
9979
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9980
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9981
+ .uleb128 0x5d
9982
+ .4byte .LASF440
9983
+ .byte 0x1
9984
+ .byte 0xe3
9985
+ .8byte .L60
9986
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9987
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9988
+ .4byte 0x3ab8
9989
+ .uleb128 0x55
9990
+ .string "__v"
9991
+ .byte 0x1
9992
+ .byte 0xc0
9993
+ .4byte 0xae
9994
+ .4byte .LLST64
9995
+ .byte 0
9996
+ .uleb128 0x46
9997
+ .4byte .Ldebug_ranges0+0x360
9998
+ .4byte 0x3ad1
9999
+ .uleb128 0x55
10000
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10001
+ .byte 0x1
10002
+ .byte 0xd0
10003
+ .4byte 0xae
10004
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10005
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10006
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10007
+ .4byte .Ldebug_ranges0+0x390
10008
+ .4byte 0x3aea
10009
+ .uleb128 0x55
10010
+ .string "__v"
10011
+ .byte 0x1
10012
+ .byte 0xd2
10013
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10014
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10015
+ .byte 0
10016
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10017
+ .8byte .LBB176
10018
+ .8byte .LBE176-.LBB176
10019
+ .4byte 0x3b0f
10020
+ .uleb128 0x55
10021
+ .string "__v"
10022
+ .byte 0x1
10023
+ .byte 0xda
10024
+ .4byte 0xa3
10025
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10026
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10027
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10028
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10029
+ .4byte 0x3b28
10030
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10031
+ .string "__v"
10032
+ .byte 0x1
10033
+ .byte 0xe4
10034
+ .4byte 0xae
10035
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10036
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10037
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10038
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10039
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10040
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10041
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10042
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10043
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10044
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10045
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10046
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10047
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10048
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10049
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10050
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10051
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10052
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10053
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10054
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10055
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10056
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10057
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10058
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10059
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10060
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10061
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10062
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10063
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10064
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10065
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10066
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10067
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10068
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10069
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10070
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10071
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10072
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10073
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10074
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10075
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10076
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10077
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10078
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10079
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10080
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10081
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10082
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10083
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10084
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10085
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10086
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10087
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10088
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10089
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10090
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10091
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10092
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10093
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10094
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10095
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10096
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10097
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10098
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10099
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10100
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10101
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10102
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10103
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10104
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10105
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10106
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10107
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10108
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10109
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10110
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10111
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10112
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10113
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10114
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10115
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10116
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10117
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10118
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10119
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10120
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10121
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10122
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10123
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10124
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10125
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10126
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10127
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10128
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10129
+ .byte 0x3
10130
+ .8byte .LANCHOR3
10131
+ .byte 0
10132
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10133
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10134
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10135
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10136
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10137
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10138
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10139
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10140
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10141
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10142
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10143
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10144
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10145
+ .uleb128 0x11
10146
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10147
+ .byte 0x16
10148
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10149
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10150
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10151
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10152
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10153
+ .byte 0x1
10154
+ .byte 0x98
10155
+ .4byte 0x54
10156
+ .byte 0x1
10157
+ .4byte 0x3cc1
10158
+ .uleb128 0x60
10159
+ .string "otp"
10160
+ .byte 0x1
10161
+ .byte 0x98
10162
+ .4byte 0x182b
10163
+ .uleb128 0x61
10164
+ .4byte .LASF269
10165
+ .byte 0x1
10166
+ .byte 0x99
10167
+ .4byte 0x144
10168
+ .uleb128 0x62
10169
+ .string "ret"
10170
+ .byte 0x1
10171
+ .byte 0x9b
10172
+ .4byte 0x54
10173
+ .uleb128 0x4e
10174
+ .4byte .LASF433
10175
+ .4byte 0x3cd1
10176
+ .4byte .LASF441
10177
+ .uleb128 0x50
10178
+ .4byte 0x3c6f
10179
+ .uleb128 0x62
10180
+ .string "__v"
10181
+ .byte 0x1
10182
+ .byte 0x9d
10183
+ .4byte 0xae
10184
+ .byte 0
10185
+ .uleb128 0x50
10186
+ .4byte 0x3c80
10187
+ .uleb128 0x62
10188
+ .string "__v"
10189
+ .byte 0x1
10190
+ .byte 0x9e
10191
+ .4byte 0xae
10192
+ .byte 0
10193
+ .uleb128 0x50
10194
+ .4byte 0x3c91
10195
+ .uleb128 0x62
10196
+ .string "__v"
10197
+ .byte 0x1
10198
+ .byte 0x9f
10199
+ .4byte 0xae
10200
+ .byte 0
10201
+ .uleb128 0x50
10202
+ .4byte 0x3ca2
10203
+ .uleb128 0x62
10204
+ .string "__v"
10205
+ .byte 0x1
10206
+ .byte 0xa1
10207
+ .4byte 0xae
10208
+ .byte 0
10209
+ .uleb128 0x50
10210
+ .4byte 0x3cb3
10211
+ .uleb128 0x62
10212
+ .string "__v"
10213
+ .byte 0x1
10214
+ .byte 0xa3
10215
+ .4byte 0xae
10216
+ .byte 0
10217
+ .uleb128 0x51
10218
+ .uleb128 0x62
10219
+ .string "__v"
10220
+ .byte 0x1
10221
+ .byte 0xa5
10222
+ .4byte 0xae
10223
+ .byte 0
10224
+ .byte 0
10225
+ .uleb128 0xa
10226
+ .4byte 0xee
10227
+ .4byte 0x3cd1
10228
+ .uleb128 0x11
10229
+ .4byte 0xda
10230
+ .byte 0x1e
10231
+ .byte 0
10232
+ .uleb128 0x7
10233
+ .4byte 0x3cc1
10234
+ .uleb128 0x5f
10235
+ .4byte .LASF442
10236
+ .byte 0x1
10237
+ .byte 0x81
10238
+ .4byte 0x54
10239
+ .byte 0x1
10240
+ .4byte 0x3d20
10241
+ .uleb128 0x60
10242
+ .string "otp"
10243
+ .byte 0x1
10244
+ .byte 0x81
10245
+ .4byte 0x182b
10246
+ .uleb128 0x63
10247
+ .4byte .LASF443
10248
+ .byte 0x1
10249
+ .byte 0x83
10250
+ .4byte 0x54
10251
+ .uleb128 0x63
10252
+ .4byte .LASF430
10253
+ .byte 0x1
10254
+ .byte 0x84
10255
+ .4byte 0x54
10256
+ .uleb128 0x62
10257
+ .string "ret"
10258
+ .byte 0x1
10259
+ .byte 0x85
10260
+ .4byte 0x54
10261
+ .uleb128 0x51
10262
+ .uleb128 0x62
10263
+ .string "__v"
10264
+ .byte 0x1
10265
+ .byte 0x88
10266
+ .4byte 0xae
10267
+ .byte 0
10268
+ .byte 0
10269
+ .uleb128 0x5f
10270
+ .4byte .LASF444
10271
+ .byte 0x1
10272
+ .byte 0x6a
10273
+ .4byte 0x54
10274
+ .byte 0x1
10275
+ .4byte 0x3d6a
10276
+ .uleb128 0x60
10277
+ .string "otp"
10278
+ .byte 0x1
10279
+ .byte 0x6a
10280
+ .4byte 0x182b
10281
+ .uleb128 0x63
10282
+ .4byte .LASF443
10283
+ .byte 0x1
10284
+ .byte 0x6c
10285
+ .4byte 0x54
10286
+ .uleb128 0x63
10287
+ .4byte .LASF430
10288
+ .byte 0x1
10289
+ .byte 0x6d
10290
+ .4byte 0x54
10291
+ .uleb128 0x62
10292
+ .string "ret"
10293
+ .byte 0x1
10294
+ .byte 0x6e
10295
+ .4byte 0x54
10296
+ .uleb128 0x51
10297
+ .uleb128 0x62
10298
+ .string "__v"
10299
+ .byte 0x1
10300
+ .byte 0x71
10301
+ .4byte 0xae
10302
+ .byte 0
10303
+ .byte 0
10304
+ .uleb128 0x5f
10305
+ .4byte .LASF445
10306
+ .byte 0x1
10307
+ .byte 0x56
10308
+ .4byte 0x54
10309
+ .byte 0x1
10310
+ .4byte 0x3dc7
10311
+ .uleb128 0x60
10312
+ .string "otp"
10313
+ .byte 0x1
10314
+ .byte 0x56
10315
+ .4byte 0x182b
10316
+ .uleb128 0x61
10317
+ .4byte .LASF446
10318
+ .byte 0x1
10319
+ .byte 0x57
10320
+ .4byte 0xae
10321
+ .uleb128 0x63
10322
+ .4byte .LASF443
10323
+ .byte 0x1
10324
+ .byte 0x59
10325
+ .4byte 0x54
10326
+ .uleb128 0x4e
10327
+ .4byte .LASF433
10328
+ .4byte 0x2a4d
10329
+ .4byte .LASF445
10330
+ .uleb128 0x50
10331
+ .4byte 0x3db9
10332
+ .uleb128 0x62
10333
+ .string "__v"
10334
+ .byte 0x1
10335
+ .byte 0x5b
10336
+ .4byte 0xae
10337
+ .byte 0
10338
+ .uleb128 0x51
10339
+ .uleb128 0x62
10340
+ .string "__v"
10341
+ .byte 0x1
10342
+ .byte 0x65
10343
+ .4byte 0xae
10344
+ .byte 0
10345
+ .byte 0
10346
+ .uleb128 0x64
10347
+ .4byte .LASF450
10348
+ .byte 0x1
10349
+ .byte 0x4e
10350
+ .8byte .LFB263
10351
+ .8byte .LFE263-.LFB263
10352
+ .uleb128 0x1
10353
+ .byte 0x9c
10354
+ .4byte 0x3e3c
10355
+ .uleb128 0x65
10356
+ .4byte .LASF447
10357
+ .byte 0x1
10358
+ .byte 0x4e
10359
+ .4byte 0x11d8
10360
+ .uleb128 0x1
10361
+ .byte 0x50
10362
+ .uleb128 0x54
10363
+ .4byte .LASF448
10364
+ .byte 0x1
10365
+ .byte 0x4f
10366
+ .4byte 0x11d8
10367
+ .4byte .LLST0
10368
+ .uleb128 0x65
10369
+ .4byte .LASF449
10370
+ .byte 0x1
10371
+ .byte 0x50
10372
+ .4byte 0x3b
10373
+ .uleb128 0x1
10374
+ .byte 0x52
10375
+ .uleb128 0x65
10376
+ .4byte .LASF425
10377
+ .byte 0x1
10378
+ .byte 0x50
10379
+ .4byte 0x54
10380
+ .uleb128 0x1
10381
+ .byte 0x53
10382
+ .uleb128 0x66
10383
+ .8byte .LBB22
10384
+ .8byte .LBE22-.LBB22
10385
+ .uleb128 0x67
10386
+ .string "__v"
10387
+ .byte 0x1
10388
+ .byte 0x52
10389
+ .4byte 0xae
10390
+ .4byte 0x80000
10391
+ .byte 0
10392
+ .byte 0
10393
+ .uleb128 0x64
10394
+ .4byte .LASF451
10395
+ .byte 0x1
10396
+ .byte 0x42
10397
+ .8byte .LFB262
10398
+ .8byte .LFE262-.LFB262
10399
+ .uleb128 0x1
10400
+ .byte 0x9c
10401
+ .4byte 0x3f2f
10402
+ .uleb128 0x54
10403
+ .4byte .LASF447
10404
+ .byte 0x1
10405
+ .byte 0x42
10406
+ .4byte 0x11d8
10407
+ .4byte .LLST16
10408
+ .uleb128 0x54
10409
+ .4byte .LASF448
10410
+ .byte 0x1
10411
+ .byte 0x43
10412
+ .4byte 0x11d8
10413
+ .4byte .LLST17
10414
+ .uleb128 0x54
10415
+ .4byte .LASF449
10416
+ .byte 0x1
10417
+ .byte 0x44
10418
+ .4byte 0x3b
10419
+ .4byte .LLST18
10420
+ .uleb128 0x54
10421
+ .4byte .LASF425
10422
+ .byte 0x1
10423
+ .byte 0x44
10424
+ .4byte 0x54
10425
+ .4byte .LLST19
10426
+ .uleb128 0x45
10427
+ .8byte .LBB25
10428
+ .8byte .LBE25-.LBB25
10429
+ .4byte 0x3eba
10430
+ .uleb128 0x67
10431
+ .string "__v"
10432
+ .byte 0x1
10433
+ .byte 0x47
10434
+ .4byte 0xae
10435
+ .4byte 0x80008
10436
+ .byte 0
10437
+ .uleb128 0x45
10438
+ .8byte .LBB26
10439
+ .8byte .LBE26-.LBB26
10440
+ .4byte 0x3edf
10441
+ .uleb128 0x67
10442
+ .string "__v"
10443
+ .byte 0x1
10444
+ .byte 0x48
10445
+ .4byte 0xae
10446
+ .4byte 0x100010
10447
+ .byte 0
10448
+ .uleb128 0x45
10449
+ .8byte .LBB27
10450
+ .8byte .LBE27-.LBB27
10451
+ .4byte 0x3f04
10452
+ .uleb128 0x67
10453
+ .string "__v"
10454
+ .byte 0x1
10455
+ .byte 0x4a
10456
+ .4byte 0xae
10457
+ .4byte 0x100000
10458
+ .byte 0
10459
+ .uleb128 0x34
10460
+ .8byte .LVL32
10461
+ .4byte 0x42ce
10462
+ .4byte 0x3f1b
10463
+ .uleb128 0x35
10464
+ .uleb128 0x1
10465
+ .byte 0x50
10466
+ .uleb128 0x1
10467
+ .byte 0x32
10468
+ .byte 0
10469
+ .uleb128 0x68
10470
+ .8byte .LVL34
10471
+ .4byte 0x42ce
10472
+ .uleb128 0x35
10473
+ .uleb128 0x1
10474
+ .byte 0x50
10475
+ .uleb128 0x1
10476
+ .byte 0x31
10477
+ .byte 0
10478
+ .byte 0
10479
+ .uleb128 0x69
10480
+ .4byte .LASF463
10481
+ .byte 0x1a
10482
+ .2byte 0x36f
10483
+ .byte 0x3
10484
+ .4byte 0x3f49
10485
+ .uleb128 0x3c
10486
+ .string "ptr"
10487
+ .byte 0x1a
10488
+ .2byte 0x36f
10489
+ .4byte 0x137
10490
+ .byte 0
10491
+ .uleb128 0x6a
10492
+ .4byte 0x3cd6
10493
+ .8byte .LFB278
10494
+ .8byte .LFE278-.LFB278
10495
+ .uleb128 0x1
10496
+ .byte 0x9c
10497
+ .4byte 0x3fb3
10498
+ .uleb128 0x6b
10499
+ .4byte 0x3ce6
10500
+ .uleb128 0x42
10501
+ .4byte 0x3cf1
10502
+ .4byte .LLST20
10503
+ .uleb128 0x42
10504
+ .4byte 0x3cfc
10505
+ .4byte .LLST21
10506
+ .uleb128 0x44
10507
+ .4byte 0x3d07
10508
+ .uleb128 0x45
10509
+ .8byte .LBB28
10510
+ .8byte .LBE28-.LBB28
10511
+ .4byte 0x3f9f
10512
+ .uleb128 0x42
10513
+ .4byte 0x3d13
10514
+ .4byte .LLST22
10515
+ .byte 0
10516
+ .uleb128 0x36
10517
+ .8byte .LVL40
10518
+ .4byte 0x42ce
10519
+ .uleb128 0x35
10520
+ .uleb128 0x1
10521
+ .byte 0x50
10522
+ .uleb128 0x1
10523
+ .byte 0x31
10524
+ .byte 0
10525
+ .byte 0
10526
+ .uleb128 0x6a
10527
+ .4byte 0x3d20
10528
+ .8byte .LFB279
10529
+ .8byte .LFE279-.LFB279
10530
+ .uleb128 0x1
10531
+ .byte 0x9c
10532
+ .4byte 0x401e
10533
+ .uleb128 0x6b
10534
+ .4byte 0x3d30
10535
+ .uleb128 0x42
10536
+ .4byte 0x3d3b
10537
+ .4byte .LLST23
10538
+ .uleb128 0x42
10539
+ .4byte 0x3d46
10540
+ .4byte .LLST24
10541
+ .uleb128 0x6c
10542
+ .4byte 0x3d51
10543
+ .sleb128 -1
10544
+ .uleb128 0x45
10545
+ .8byte .LBB29
10546
+ .8byte .LBE29-.LBB29
10547
+ .4byte 0x400a
10548
+ .uleb128 0x42
10549
+ .4byte 0x3d5d
10550
+ .4byte .LLST25
10551
+ .byte 0
10552
+ .uleb128 0x36
10553
+ .8byte .LVL48
10554
+ .4byte 0x42ce
10555
+ .uleb128 0x35
10556
+ .uleb128 0x1
10557
+ .byte 0x50
10558
+ .uleb128 0x1
10559
+ .byte 0x31
10560
+ .byte 0
10561
+ .byte 0
10562
+ .uleb128 0x6a
10563
+ .4byte 0x3d6a
10564
+ .8byte .LFB280
10565
+ .8byte .LFE280-.LFB280
10566
+ .uleb128 0x1
10567
+ .byte 0x9c
10568
+ .4byte 0x410b
10569
+ .uleb128 0x3a
10570
+ .4byte 0x3d85
10571
+ .4byte .LLST26
10572
+ .uleb128 0x6b
10573
+ .4byte 0x3d7a
10574
+ .uleb128 0x42
10575
+ .4byte 0x3d90
10576
+ .4byte .LLST27
10577
+ .uleb128 0x44
10578
+ .4byte 0x3d9b
10579
+ .uleb128 0x45
10580
+ .8byte .LBB36
10581
+ .8byte .LBE36-.LBB36
10582
+ .4byte 0x4074
10583
+ .uleb128 0x42
10584
+ .4byte 0x3dad
10585
+ .4byte .LLST28
10586
+ .byte 0
10587
+ .uleb128 0x45
10588
+ .8byte .LBB37
10589
+ .8byte .LBE37-.LBB37
10590
+ .4byte 0x4093
10591
+ .uleb128 0x42
10592
+ .4byte 0x3dba
10593
+ .4byte .LLST29
10594
+ .byte 0
10595
+ .uleb128 0x45
10596
+ .8byte .LBB38
10597
+ .8byte .LBE38-.LBB38
10598
+ .4byte 0x40f7
10599
+ .uleb128 0x6b
10600
+ .4byte 0x3d85
10601
+ .uleb128 0x6b
10602
+ .4byte 0x3d7a
10603
+ .uleb128 0x66
10604
+ .8byte .LBB39
10605
+ .8byte .LBE39-.LBB39
10606
+ .uleb128 0x44
10607
+ .4byte 0x3d90
10608
+ .uleb128 0x44
10609
+ .4byte 0x3d9b
10610
+ .uleb128 0x36
10611
+ .8byte .LVL63
10612
+ .4byte 0x42b7
10613
+ .uleb128 0x35
10614
+ .uleb128 0x1
10615
+ .byte 0x50
10616
+ .uleb128 0x9
10617
+ .byte 0x3
10618
+ .8byte .LC3
10619
+ .uleb128 0x35
10620
+ .uleb128 0x1
10621
+ .byte 0x51
10622
+ .uleb128 0x9
10623
+ .byte 0x3
10624
+ .8byte .LANCHOR0
10625
+ .byte 0
10626
+ .byte 0
10627
+ .byte 0
10628
+ .uleb128 0x36
10629
+ .8byte .LVL60
10630
+ .4byte 0x42ce
10631
+ .uleb128 0x35
10632
+ .uleb128 0x1
10633
+ .byte 0x50
10634
+ .uleb128 0x1
10635
+ .byte 0x31
10636
+ .byte 0
10637
+ .byte 0
10638
+ .uleb128 0x6a
10639
+ .4byte 0x3c20
10640
+ .8byte .LFB267
10641
+ .8byte .LFE267-.LFB267
10642
+ .uleb128 0x1
10643
+ .byte 0x9c
10644
+ .4byte 0x4289
10645
+ .uleb128 0x3a
10646
+ .4byte 0x3c30
10647
+ .4byte .LLST48
10648
+ .uleb128 0x3a
10649
+ .4byte 0x3c3b
10650
+ .4byte .LLST49
10651
+ .uleb128 0x42
10652
+ .4byte 0x3c46
10653
+ .4byte .LLST50
10654
+ .uleb128 0x44
10655
+ .4byte 0x3c51
10656
+ .uleb128 0x45
10657
+ .8byte .LBB160
10658
+ .8byte .LBE160-.LBB160
10659
+ .4byte 0x4165
10660
+ .uleb128 0x6c
10661
+ .4byte 0x3c63
10662
+ .sleb128 -16776704
10663
+ .byte 0
10664
+ .uleb128 0x45
10665
+ .8byte .LBB161
10666
+ .8byte .LBE161-.LBB161
10667
+ .4byte 0x4183
10668
+ .uleb128 0x6c
10669
+ .4byte 0x3c74
10670
+ .sleb128 -65535
10671
+ .byte 0
10672
+ .uleb128 0x45
10673
+ .8byte .LBB162
10674
+ .8byte .LBE162-.LBB162
10675
+ .4byte 0x419f
10676
+ .uleb128 0x6d
10677
+ .4byte 0x3c85
10678
+ .byte 0xfa
10679
+ .byte 0
10680
+ .uleb128 0x45
10681
+ .8byte .LBB163
10682
+ .8byte .LBE163-.LBB163
10683
+ .4byte 0x41be
10684
+ .uleb128 0x42
10685
+ .4byte 0x3c96
10686
+ .4byte .LLST51
10687
+ .byte 0
10688
+ .uleb128 0x45
10689
+ .8byte .LBB164
10690
+ .8byte .LBE164-.LBB164
10691
+ .4byte 0x41dd
10692
+ .uleb128 0x42
10693
+ .4byte 0x3cb4
10694
+ .4byte .LLST52
10695
+ .byte 0
10696
+ .uleb128 0x45
10697
+ .8byte .LBB165
10698
+ .8byte .LBE165-.LBB165
10699
+ .4byte 0x4249
10700
+ .uleb128 0x3a
10701
+ .4byte 0x3c30
10702
+ .4byte .LLST53
10703
+ .uleb128 0x3a
10704
+ .4byte 0x3c3b
10705
+ .4byte .LLST54
10706
+ .uleb128 0x66
10707
+ .8byte .LBB166
10708
+ .8byte .LBE166-.LBB166
10709
+ .uleb128 0x44
10710
+ .4byte 0x4138
10711
+ .uleb128 0x44
10712
+ .4byte 0x4141
10713
+ .uleb128 0x36
10714
+ .8byte .LVL209
10715
+ .4byte 0x42b7
10716
+ .uleb128 0x35
10717
+ .uleb128 0x1
10718
+ .byte 0x50
10719
+ .uleb128 0x9
10720
+ .byte 0x3
10721
+ .8byte .LC8
10722
+ .uleb128 0x35
10723
+ .uleb128 0x1
10724
+ .byte 0x51
10725
+ .uleb128 0x9
10726
+ .byte 0x3
10727
+ .8byte .LANCHOR2
10728
+ .byte 0
10729
+ .byte 0
10730
+ .byte 0
10731
+ .uleb128 0x45
10732
+ .8byte .LBB167
10733
+ .8byte .LBE167-.LBB167
10734
+ .4byte 0x4265
10735
+ .uleb128 0x6d
10736
+ .4byte 0x3ca7
10737
+ .byte 0x9
10738
+ .byte 0
10739
+ .uleb128 0x36
10740
+ .8byte .LVL205
10741
+ .4byte 0x401e
10742
+ .uleb128 0x35
10743
+ .uleb128 0x1
10744
+ .byte 0x50
10745
+ .uleb128 0x3
10746
+ .byte 0xf3
10747
+ .uleb128 0x1
10748
+ .byte 0x50
10749
+ .uleb128 0x35
10750
+ .uleb128 0x1
10751
+ .byte 0x51
10752
+ .uleb128 0x1
10753
+ .byte 0x32
10754
+ .uleb128 0x48
10755
+ .4byte 0x3d7a
10756
+ .uleb128 0x3
10757
+ .byte 0xf3
10758
+ .uleb128 0x1
10759
+ .byte 0x50
10760
+ .byte 0
10761
+ .byte 0
10762
+ .uleb128 0x6e
10763
+ .4byte .LASF452
10764
+ .4byte .LASF452
10765
+ .byte 0x8
10766
+ .2byte 0x115
10767
+ .uleb128 0x6f
10768
+ .4byte .LASF453
10769
+ .4byte .LASF453
10770
+ .byte 0x20
10771
+ .byte 0x85
10772
+ .uleb128 0x6f
10773
+ .4byte .LASF454
10774
+ .4byte .LASF454
10775
+ .byte 0x20
10776
+ .byte 0x38
10777
+ .uleb128 0x6e
10778
+ .4byte .LASF455
10779
+ .4byte .LASF455
10780
+ .byte 0x8
10781
+ .2byte 0x16e
10782
+ .uleb128 0x6f
10783
+ .4byte .LASF456
10784
+ .4byte .LASF456
10785
+ .byte 0x21
10786
+ .byte 0x13
10787
+ .uleb128 0x6e
10788
+ .4byte .LASF457
10789
+ .4byte .LASF457
10790
+ .byte 0x1a
10791
+ .2byte 0x393
10792
+ .uleb128 0x6f
10793
+ .4byte .LASF458
10794
+ .4byte .LASF458
10795
+ .byte 0x22
10796
+ .byte 0xb
10797
+ .byte 0
10798
+ .section .debug_abbrev,"",@progbits
10799
+.Ldebug_abbrev0:
10800
+ .uleb128 0x1
10801
+ .uleb128 0x11
10802
+ .byte 0x1
10803
+ .uleb128 0x25
10804
+ .uleb128 0xe
10805
+ .uleb128 0x13
10806
+ .uleb128 0xb
10807
+ .uleb128 0x3
10808
+ .uleb128 0xe
10809
+ .uleb128 0x1b
10810
+ .uleb128 0xe
10811
+ .uleb128 0x55
10812
+ .uleb128 0x17
10813
+ .uleb128 0x11
10814
+ .uleb128 0x1
10815
+ .uleb128 0x10
10816
+ .uleb128 0x17
10817
+ .byte 0
10818
+ .byte 0
10819
+ .uleb128 0x2
10820
+ .uleb128 0x16
10821
+ .byte 0
10822
+ .uleb128 0x3
10823
+ .uleb128 0xe
10824
+ .uleb128 0x3a
10825
+ .uleb128 0xb
10826
+ .uleb128 0x3b
10827
+ .uleb128 0xb
10828
+ .uleb128 0x49
10829
+ .uleb128 0x13
10830
+ .byte 0
10831
+ .byte 0
10832
+ .uleb128 0x3
10833
+ .uleb128 0x24
10834
+ .byte 0
10835
+ .uleb128 0xb
10836
+ .uleb128 0xb
10837
+ .uleb128 0x3e
10838
+ .uleb128 0xb
10839
+ .uleb128 0x3
10840
+ .uleb128 0xe
10841
+ .byte 0
10842
+ .byte 0
10843
+ .uleb128 0x4
10844
+ .uleb128 0x34
10845
+ .byte 0
10846
+ .uleb128 0x3
10847
+ .uleb128 0xe
10848
+ .uleb128 0x3a
10849
+ .uleb128 0xb
10850
+ .uleb128 0x3b
10851
+ .uleb128 0xb
10852
+ .uleb128 0x49
10853
+ .uleb128 0x13
10854
+ .uleb128 0x3f
10855
+ .uleb128 0x19
10856
+ .uleb128 0x3c
10857
+ .uleb128 0x19
10858
+ .byte 0
10859
+ .byte 0
10860
+ .uleb128 0x5
10861
+ .uleb128 0x24
10862
+ .byte 0
10863
+ .uleb128 0xb
10864
+ .uleb128 0xb
10865
+ .uleb128 0x3e
10866
+ .uleb128 0xb
10867
+ .uleb128 0x3
10868
+ .uleb128 0x8
10869
+ .byte 0
10870
+ .byte 0
10871
+ .uleb128 0x6
10872
+ .uleb128 0x16
10873
+ .byte 0
10874
+ .uleb128 0x3
10875
+ .uleb128 0x8
10876
+ .uleb128 0x3a
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+ .uleb128 0x68
12124
+ .uleb128 0x4109
12125
+ .byte 0x1
12126
+ .uleb128 0x11
12127
+ .uleb128 0x1
12128
+ .uleb128 0x2115
12129
+ .uleb128 0x19
12130
+ .uleb128 0x31
12131
+ .uleb128 0x13
12132
+ .byte 0
12133
+ .byte 0
12134
+ .uleb128 0x69
12135
+ .uleb128 0x2e
12136
+ .byte 0x1
12137
+ .uleb128 0x3
12138
+ .uleb128 0xe
12139
+ .uleb128 0x3a
12140
+ .uleb128 0xb
12141
+ .uleb128 0x3b
12142
+ .uleb128 0x5
12143
+ .uleb128 0x27
12144
+ .uleb128 0x19
12145
+ .uleb128 0x20
12146
+ .uleb128 0xb
12147
+ .uleb128 0x1
12148
+ .uleb128 0x13
12149
+ .byte 0
12150
+ .byte 0
12151
+ .uleb128 0x6a
12152
+ .uleb128 0x2e
12153
+ .byte 0x1
12154
+ .uleb128 0x31
12155
+ .uleb128 0x13
12156
+ .uleb128 0x11
12157
+ .uleb128 0x1
12158
+ .uleb128 0x12
12159
+ .uleb128 0x7
12160
+ .uleb128 0x40
12161
+ .uleb128 0x18
12162
+ .uleb128 0x2117
12163
+ .uleb128 0x19
12164
+ .uleb128 0x1
12165
+ .uleb128 0x13
12166
+ .byte 0
12167
+ .byte 0
12168
+ .uleb128 0x6b
12169
+ .uleb128 0x5
12170
+ .byte 0
12171
+ .uleb128 0x31
12172
+ .uleb128 0x13
12173
+ .byte 0
12174
+ .byte 0
12175
+ .uleb128 0x6c
12176
+ .uleb128 0x34
12177
+ .byte 0
12178
+ .uleb128 0x31
12179
+ .uleb128 0x13
12180
+ .uleb128 0x1c
12181
+ .uleb128 0xd
12182
+ .byte 0
12183
+ .byte 0
12184
+ .uleb128 0x6d
12185
+ .uleb128 0x34
12186
+ .byte 0
12187
+ .uleb128 0x31
12188
+ .uleb128 0x13
12189
+ .uleb128 0x1c
12190
+ .uleb128 0xb
12191
+ .byte 0
12192
+ .byte 0
12193
+ .uleb128 0x6e
12194
+ .uleb128 0x2e
12195
+ .byte 0
12196
+ .uleb128 0x3f
12197
+ .uleb128 0x19
12198
+ .uleb128 0x3c
12199
+ .uleb128 0x19
12200
+ .uleb128 0x6e
12201
+ .uleb128 0xe
12202
+ .uleb128 0x3
12203
+ .uleb128 0xe
12204
+ .uleb128 0x3a
12205
+ .uleb128 0xb
12206
+ .uleb128 0x3b
12207
+ .uleb128 0x5
12208
+ .byte 0
12209
+ .byte 0
12210
+ .uleb128 0x6f
12211
+ .uleb128 0x2e
12212
+ .byte 0
12213
+ .uleb128 0x3f
12214
+ .uleb128 0x19
12215
+ .uleb128 0x3c
12216
+ .uleb128 0x19
12217
+ .uleb128 0x6e
12218
+ .uleb128 0xe
12219
+ .uleb128 0x3
12220
+ .uleb128 0xe
12221
+ .uleb128 0x3a
12222
+ .uleb128 0xb
12223
+ .uleb128 0x3b
12224
+ .uleb128 0xb
12225
+ .byte 0
12226
+ .byte 0
12227
+ .byte 0
12228
+ .section .debug_loc,"",@progbits
12229
+.Ldebug_loc0:
12230
+.LLST14:
12231
+ .8byte .LVL19
12232
+ .8byte .LVL20-1
12233
+ .2byte 0x1
12234
+ .byte 0x50
12235
+ .8byte .LVL20-1
12236
+ .8byte .LVL27
12237
+ .2byte 0x1
12238
+ .byte 0x64
12239
+ .8byte .LVL27
12240
+ .8byte .LFE277
12241
+ .2byte 0x4
12242
+ .byte 0xf3
12243
+ .uleb128 0x1
12244
+ .byte 0x50
12245
+ .byte 0x9f
12246
+ .8byte 0
12247
+ .8byte 0
12248
+.LLST15:
12249
+ .8byte .LVL21
12250
+ .8byte .LVL22
12251
+ .2byte 0x1
12252
+ .byte 0x50
12253
+ .8byte .LVL22
12254
+ .8byte .LVL27
12255
+ .2byte 0x1
12256
+ .byte 0x63
12257
+ .8byte 0
12258
+ .8byte 0
12259
+.LLST1:
12260
+ .8byte .LVL2
12261
+ .8byte .LVL3
12262
+ .2byte 0x1
12263
+ .byte 0x50
12264
+ .8byte .LVL3
12265
+ .8byte .LFE276
12266
+ .2byte 0x4
12267
+ .byte 0xf3
12268
+ .uleb128 0x1
12269
+ .byte 0x50
12270
+ .byte 0x9f
12271
+ .8byte 0
12272
+ .8byte 0
12273
+.LLST2:
12274
+ .8byte .LVL2
12275
+ .8byte .LVL5
12276
+ .2byte 0x3
12277
+ .byte 0x9
12278
+ .byte 0xea
12279
+ .byte 0x9f
12280
+ .8byte .LVL6
12281
+ .8byte .LFE276
12282
+ .2byte 0x3
12283
+ .byte 0x9
12284
+ .byte 0xea
12285
+ .byte 0x9f
12286
+ .8byte 0
12287
+ .8byte 0
12288
+.LLST3:
12289
+ .8byte .LVL4
12290
+ .8byte .LVL5
12291
+ .2byte 0x1
12292
+ .byte 0x52
12293
+ .8byte 0
12294
+ .8byte 0
12295
+.LLST4:
12296
+ .8byte .LVL7
12297
+ .8byte .LVL8-1
12298
+ .2byte 0x1
12299
+ .byte 0x50
12300
+ .8byte .LVL8-1
12301
+ .8byte .LVL11
12302
+ .2byte 0x1
12303
+ .byte 0x63
12304
+ .8byte .LVL11
12305
+ .8byte .LVL12-1
12306
+ .2byte 0x1
12307
+ .byte 0x50
12308
+ .8byte .LVL12-1
12309
+ .8byte .LFE274
12310
+ .2byte 0x4
12311
+ .byte 0xf3
12312
+ .uleb128 0x1
12313
+ .byte 0x50
12314
+ .byte 0x9f
12315
+ .8byte 0
12316
+ .8byte 0
12317
+.LLST5:
12318
+ .8byte .LVL7
12319
+ .8byte .LVL8-1
12320
+ .2byte 0x1
12321
+ .byte 0x51
12322
+ .8byte .LVL8-1
12323
+ .8byte .LVL11
12324
+ .2byte 0x1
12325
+ .byte 0x64
12326
+ .8byte .LVL11
12327
+ .8byte .LVL12-1
12328
+ .2byte 0x1
12329
+ .byte 0x51
12330
+ .8byte .LVL12-1
12331
+ .8byte .LFE274
12332
+ .2byte 0x4
12333
+ .byte 0xf3
12334
+ .uleb128 0x1
12335
+ .byte 0x51
12336
+ .byte 0x9f
12337
+ .8byte 0
12338
+ .8byte 0
12339
+.LLST6:
12340
+ .8byte .LVL7
12341
+ .8byte .LVL8-1
12342
+ .2byte 0x1
12343
+ .byte 0x52
12344
+ .8byte .LVL8-1
12345
+ .8byte .LVL10
12346
+ .2byte 0x1
12347
+ .byte 0x65
12348
+ .8byte .LVL10
12349
+ .8byte .LVL12-1
12350
+ .2byte 0x1
12351
+ .byte 0x52
12352
+ .8byte .LVL12-1
12353
+ .8byte .LFE274
12354
+ .2byte 0x4
12355
+ .byte 0xf3
12356
+ .uleb128 0x1
12357
+ .byte 0x52
12358
+ .byte 0x9f
12359
+ .8byte 0
12360
+ .8byte 0
12361
+.LLST7:
12362
+ .8byte .LVL7
12363
+ .8byte .LVL8-1
12364
+ .2byte 0x1
12365
+ .byte 0x53
12366
+ .8byte .LVL8-1
12367
+ .8byte .LVL10
12368
+ .2byte 0x1
12369
+ .byte 0x66
12370
+ .8byte .LVL10
12371
+ .8byte .LVL12-1
12372
+ .2byte 0x1
12373
+ .byte 0x53
12374
+ .8byte .LVL12-1
12375
+ .8byte .LFE274
12376
+ .2byte 0x4
12377
+ .byte 0xf3
12378
+ .uleb128 0x1
12379
+ .byte 0x53
12380
+ .byte 0x9f
12381
+ .8byte 0
12382
+ .8byte 0
12383
+.LLST8:
12384
+ .8byte .LVL8
12385
+ .8byte .LVL9
12386
+ .2byte 0x1
12387
+ .byte 0x50
12388
+ .8byte 0
12389
+ .8byte 0
12390
+.LLST9:
12391
+ .8byte .LVL13
12392
+ .8byte .LVL14-1
12393
+ .2byte 0x1
12394
+ .byte 0x50
12395
+ .8byte .LVL14-1
12396
+ .8byte .LVL17
12397
+ .2byte 0x1
12398
+ .byte 0x63
12399
+ .8byte .LVL17
12400
+ .8byte .LVL18-1
12401
+ .2byte 0x1
12402
+ .byte 0x50
12403
+ .8byte .LVL18-1
12404
+ .8byte .LFE273
12405
+ .2byte 0x4
12406
+ .byte 0xf3
12407
+ .uleb128 0x1
12408
+ .byte 0x50
12409
+ .byte 0x9f
12410
+ .8byte 0
12411
+ .8byte 0
12412
+.LLST10:
12413
+ .8byte .LVL13
12414
+ .8byte .LVL14-1
12415
+ .2byte 0x1
12416
+ .byte 0x51
12417
+ .8byte .LVL14-1
12418
+ .8byte .LVL17
12419
+ .2byte 0x1
12420
+ .byte 0x64
12421
+ .8byte .LVL17
12422
+ .8byte .LVL18-1
12423
+ .2byte 0x1
12424
+ .byte 0x51
12425
+ .8byte .LVL18-1
12426
+ .8byte .LFE273
12427
+ .2byte 0x4
12428
+ .byte 0xf3
12429
+ .uleb128 0x1
12430
+ .byte 0x51
12431
+ .byte 0x9f
12432
+ .8byte 0
12433
+ .8byte 0
12434
+.LLST11:
12435
+ .8byte .LVL13
12436
+ .8byte .LVL14-1
12437
+ .2byte 0x1
12438
+ .byte 0x52
12439
+ .8byte .LVL14-1
12440
+ .8byte .LVL16
12441
+ .2byte 0x1
12442
+ .byte 0x65
12443
+ .8byte .LVL16
12444
+ .8byte .LVL18-1
12445
+ .2byte 0x1
12446
+ .byte 0x52
12447
+ .8byte .LVL18-1
12448
+ .8byte .LFE273
12449
+ .2byte 0x4
12450
+ .byte 0xf3
12451
+ .uleb128 0x1
12452
+ .byte 0x52
12453
+ .byte 0x9f
12454
+ .8byte 0
12455
+ .8byte 0
12456
+.LLST12:
12457
+ .8byte .LVL13
12458
+ .8byte .LVL14-1
12459
+ .2byte 0x1
12460
+ .byte 0x53
12461
+ .8byte .LVL14-1
12462
+ .8byte .LVL16
12463
+ .2byte 0x1
12464
+ .byte 0x66
12465
+ .8byte .LVL16
12466
+ .8byte .LVL18-1
12467
+ .2byte 0x1
12468
+ .byte 0x53
12469
+ .8byte .LVL18-1
12470
+ .8byte .LFE273
12471
+ .2byte 0x4
12472
+ .byte 0xf3
12473
+ .uleb128 0x1
12474
+ .byte 0x53
12475
+ .byte 0x9f
12476
+ .8byte 0
12477
+ .8byte 0
12478
+.LLST13:
12479
+ .8byte .LVL14
12480
+ .8byte .LVL15
12481
+ .2byte 0x1
12482
+ .byte 0x50
12483
+ .8byte 0
12484
+ .8byte 0
12485
+.LLST69:
12486
+ .8byte .LVL246
12487
+ .8byte .LVL247-1
12488
+ .2byte 0x1
12489
+ .byte 0x50
12490
+ .8byte .LVL247-1
12491
+ .8byte .LVL254
12492
+ .2byte 0x1
12493
+ .byte 0x68
12494
+ .8byte .LVL254
12495
+ .8byte .LVL257
12496
+ .2byte 0x4
12497
+ .byte 0xf3
12498
+ .uleb128 0x1
12499
+ .byte 0x50
12500
+ .byte 0x9f
12501
+ .8byte .LVL257
12502
+ .8byte .LFE272
12503
+ .2byte 0x1
12504
+ .byte 0x68
12505
+ .8byte 0
12506
+ .8byte 0
12507
+.LLST70:
12508
+ .8byte .LVL246
12509
+ .8byte .LVL247-1
12510
+ .2byte 0x1
12511
+ .byte 0x51
12512
+ .8byte .LVL247-1
12513
+ .8byte .LVL253
12514
+ .2byte 0x1
12515
+ .byte 0x64
12516
+ .8byte .LVL253
12517
+ .8byte .LVL257
12518
+ .2byte 0x4
12519
+ .byte 0xf3
12520
+ .uleb128 0x1
12521
+ .byte 0x51
12522
+ .byte 0x9f
12523
+ .8byte .LVL257
12524
+ .8byte .LFE272
12525
+ .2byte 0x1
12526
+ .byte 0x64
12527
+ .8byte 0
12528
+ .8byte 0
12529
+.LLST71:
12530
+ .8byte .LVL246
12531
+ .8byte .LVL247-1
12532
+ .2byte 0x1
12533
+ .byte 0x52
12534
+ .8byte .LVL247-1
12535
+ .8byte .LVL256
12536
+ .2byte 0x3
12537
+ .byte 0x8f
12538
+ .sleb128 224
12539
+ .8byte .LVL256
12540
+ .8byte .LVL257
12541
+ .2byte 0x3
12542
+ .byte 0x8f
12543
+ .sleb128 80
12544
+ .8byte .LVL257
12545
+ .8byte .LFE272
12546
+ .2byte 0x3
12547
+ .byte 0x8f
12548
+ .sleb128 224
12549
+ .8byte 0
12550
+ .8byte 0
12551
+.LLST72:
12552
+ .8byte .LVL246
12553
+ .8byte .LVL247-1
12554
+ .2byte 0x1
12555
+ .byte 0x53
12556
+ .8byte .LVL247-1
12557
+ .8byte .LVL252
12558
+ .2byte 0x1
12559
+ .byte 0x65
12560
+ .8byte .LVL252
12561
+ .8byte .LVL257
12562
+ .2byte 0x4
12563
+ .byte 0xf3
12564
+ .uleb128 0x1
12565
+ .byte 0x53
12566
+ .byte 0x9f
12567
+ .8byte .LVL257
12568
+ .8byte .LVL261
12569
+ .2byte 0x1
12570
+ .byte 0x65
12571
+ .8byte .LVL261
12572
+ .8byte .LVL267
12573
+ .2byte 0x4
12574
+ .byte 0xf3
12575
+ .uleb128 0x1
12576
+ .byte 0x53
12577
+ .byte 0x9f
12578
+ .8byte .LVL267
12579
+ .8byte .LVL281
12580
+ .2byte 0x1
12581
+ .byte 0x65
12582
+ .8byte .LVL281
12583
+ .8byte .LVL283
12584
+ .2byte 0x4
12585
+ .byte 0xf3
12586
+ .uleb128 0x1
12587
+ .byte 0x53
12588
+ .byte 0x9f
12589
+ .8byte .LVL283
12590
+ .8byte .LVL287
12591
+ .2byte 0x1
12592
+ .byte 0x65
12593
+ .8byte .LVL287
12594
+ .8byte .LVL396
12595
+ .2byte 0x4
12596
+ .byte 0xf3
12597
+ .uleb128 0x1
12598
+ .byte 0x53
12599
+ .byte 0x9f
12600
+ .8byte .LVL396
12601
+ .8byte .LFE272
12602
+ .2byte 0x1
12603
+ .byte 0x65
12604
+ .8byte 0
12605
+ .8byte 0
12606
+.LLST73:
12607
+ .8byte .LVL248
12608
+ .8byte .LVL249
12609
+ .2byte 0x1
12610
+ .byte 0x50
12611
+ .8byte .LVL249
12612
+ .8byte .LVL255
12613
+ .2byte 0x1
12614
+ .byte 0x6c
12615
+ .8byte .LVL257
12616
+ .8byte .LFE272
12617
+ .2byte 0x1
12618
+ .byte 0x6c
12619
+ .8byte 0
12620
+ .8byte 0
12621
+.LLST74:
12622
+ .8byte .LVL248
12623
+ .8byte .LVL256
12624
+ .2byte 0x3
12625
+ .byte 0x8f
12626
+ .sleb128 224
12627
+ .8byte .LVL256
12628
+ .8byte .LVL257
12629
+ .2byte 0x3
12630
+ .byte 0x8f
12631
+ .sleb128 80
12632
+ .8byte .LVL257
12633
+ .8byte .LFE272
12634
+ .2byte 0x3
12635
+ .byte 0x8f
12636
+ .sleb128 224
12637
+ .8byte 0
12638
+ .8byte 0
12639
+.LLST76:
12640
+ .8byte .LVL250
12641
+ .8byte .LVL251
12642
+ .2byte 0x1
12643
+ .byte 0x50
12644
+ .8byte .LVL257
12645
+ .8byte .LVL258
12646
+ .2byte 0x1
12647
+ .byte 0x50
12648
+ .8byte .LVL258
12649
+ .8byte .LVL260
12650
+ .2byte 0x1
12651
+ .byte 0x63
12652
+ .8byte .LVL267
12653
+ .8byte .LVL272
12654
+ .2byte 0x1
12655
+ .byte 0x63
12656
+ .8byte .LVL285
12657
+ .8byte .LVL286
12658
+ .2byte 0x1
12659
+ .byte 0x63
12660
+ .8byte 0
12661
+ .8byte 0
12662
+.LLST77:
12663
+ .8byte .LVL261
12664
+ .8byte .LVL267
12665
+ .2byte 0x1
12666
+ .byte 0x67
12667
+ .8byte .LVL269
12668
+ .8byte .LVL270
12669
+ .2byte 0x1
12670
+ .byte 0x50
12671
+ .8byte .LVL272
12672
+ .8byte .LVL278
12673
+ .2byte 0x1
12674
+ .byte 0x63
12675
+ .8byte .LVL283
12676
+ .8byte .LVL285
12677
+ .2byte 0x1
12678
+ .byte 0x63
12679
+ .8byte .LVL286
12680
+ .8byte .LVL287
12681
+ .2byte 0x1
12682
+ .byte 0x63
12683
+ .8byte .LVL288
12684
+ .8byte .LVL394
12685
+ .2byte 0x1
12686
+ .byte 0x67
12687
+ .8byte .LVL394
12688
+ .8byte .LVL395
12689
+ .2byte 0x3
12690
+ .byte 0x87
12691
+ .sleb128 1
12692
+ .byte 0x9f
12693
+ .8byte .LVL396
12694
+ .8byte .LFE272
12695
+ .2byte 0x1
12696
+ .byte 0x63
12697
+ .8byte 0
12698
+ .8byte 0
12699
+.LLST78:
12700
+ .8byte .LVL250
12701
+ .8byte .LVL251
12702
+ .2byte 0x2
12703
+ .byte 0x30
12704
+ .byte 0x9f
12705
+ .8byte .LVL257
12706
+ .8byte .LVL268
12707
+ .2byte 0x2
12708
+ .byte 0x30
12709
+ .byte 0x9f
12710
+ .8byte .LVL268
12711
+ .8byte .LVL269
12712
+ .2byte 0x1
12713
+ .byte 0x50
12714
+ .8byte .LVL272
12715
+ .8byte .LVL280
12716
+ .2byte 0x2
12717
+ .byte 0x30
12718
+ .byte 0x9f
12719
+ .8byte .LVL283
12720
+ .8byte .LVL315
12721
+ .2byte 0x2
12722
+ .byte 0x30
12723
+ .byte 0x9f
12724
+ .8byte .LVL317
12725
+ .8byte .LVL394
12726
+ .2byte 0x2
12727
+ .byte 0x30
12728
+ .byte 0x9f
12729
+ .8byte 0
12730
+ .8byte 0
12731
+.LLST79:
12732
+ .8byte .LVL262
12733
+ .8byte .LVL267
12734
+ .2byte 0x1
12735
+ .byte 0x6a
12736
+ .8byte .LVL288
12737
+ .8byte .LVL313
12738
+ .2byte 0x1
12739
+ .byte 0x6a
12740
+ .8byte .LVL317
12741
+ .8byte .LVL352
12742
+ .2byte 0x1
12743
+ .byte 0x6a
12744
+ .8byte 0
12745
+ .8byte 0
12746
+.LLST80:
12747
+ .8byte .LVL262
12748
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12749
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12750
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12751
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12752
+ .8byte .LVL267
12753
+ .2byte 0x1
12754
+ .byte 0x69
12755
+ .8byte .LVL288
12756
+ .8byte .LVL315
12757
+ .2byte 0x1
12758
+ .byte 0x69
12759
+ .8byte .LVL317
12760
+ .8byte .LVL394
12761
+ .2byte 0x1
12762
+ .byte 0x69
12763
+ .8byte 0
12764
+ .8byte 0
12765
+.LLST81:
12766
+ .8byte .LVL262
12767
+ .8byte .LVL267
12768
+ .2byte 0x1
12769
+ .byte 0x6c
12770
+ .8byte .LVL288
12771
+ .8byte .LVL315
12772
+ .2byte 0x1
12773
+ .byte 0x6c
12774
+ .8byte .LVL317
12775
+ .8byte .LVL394
12776
+ .2byte 0x1
12777
+ .byte 0x6c
12778
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12779
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12780
+.LLST82:
12781
+ .8byte .LVL262
12782
+ .8byte .LVL267
12783
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12784
+ .byte 0x68
12785
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12786
+ .8byte .LVL315
12787
+ .2byte 0x1
12788
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12789
+ .8byte .LVL317
12790
+ .8byte .LVL394
12791
+ .2byte 0x1
12792
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12793
+ .8byte 0
12794
+ .8byte 0
12795
+.LLST83:
12796
+ .8byte .LVL262
12797
+ .8byte .LVL267
12798
+ .2byte 0x2
12799
+ .byte 0x30
12800
+ .byte 0x9f
12801
+ .8byte .LVL288
12802
+ .8byte .LVL311
12803
+ .2byte 0x2
12804
+ .byte 0x30
12805
+ .byte 0x9f
12806
+ .8byte .LVL311
12807
+ .8byte .LVL312
12808
+ .2byte 0x1
12809
+ .byte 0x50
12810
+ .8byte .LVL312
12811
+ .8byte .LVL315
12812
+ .2byte 0x1
12813
+ .byte 0x6b
12814
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12815
+ .8byte .LVL318
12816
+ .2byte 0x1
12817
+ .byte 0x50
12818
+ .8byte .LVL318
12819
+ .8byte .LVL337
12820
+ .2byte 0x1
12821
+ .byte 0x6b
12822
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12823
+ .8byte .LVL338
12824
+ .2byte 0x1
12825
+ .byte 0x50
12826
+ .8byte .LVL338
12827
+ .8byte .LVL339
12828
+ .2byte 0x1
12829
+ .byte 0x6b
12830
+ .8byte .LVL339
12831
+ .8byte .LVL340
12832
+ .2byte 0x1
12833
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12834
+ .8byte .LVL340
12835
+ .8byte .LVL346
12836
+ .2byte 0x1
12837
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12838
+ .8byte .LVL346
12839
+ .8byte .LVL347
12840
+ .2byte 0x1
12841
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12842
+ .8byte .LVL347
12843
+ .8byte .LVL348
12844
+ .2byte 0x1
12845
+ .byte 0x6b
12846
+ .8byte .LVL348
12847
+ .8byte .LVL349
12848
+ .2byte 0x1
12849
+ .byte 0x50
12850
+ .8byte .LVL349
12851
+ .8byte .LVL356
12852
+ .2byte 0x1
12853
+ .byte 0x6b
12854
+ .8byte .LVL356
12855
+ .8byte .LVL357
12856
+ .2byte 0x1
12857
+ .byte 0x50
12858
+ .8byte .LVL357
12859
+ .8byte .LVL358
12860
+ .2byte 0x1
12861
+ .byte 0x6b
12862
+ .8byte .LVL358
12863
+ .8byte .LVL359
12864
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12865
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12866
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12867
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12868
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12869
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12870
+ .8byte .LVL365
12871
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12872
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12873
+ .byte 0x50
12874
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12875
+ .8byte .LVL367
12876
+ .2byte 0x1
12877
+ .byte 0x6b
12878
+ .8byte .LVL367
12879
+ .8byte .LVL368
12880
+ .2byte 0x1
12881
+ .byte 0x50
12882
+ .8byte .LVL368
12883
+ .8byte .LVL374
12884
+ .2byte 0x1
12885
+ .byte 0x6b
12886
+ .8byte .LVL374
12887
+ .8byte .LVL375
12888
+ .2byte 0x1
12889
+ .byte 0x50
12890
+ .8byte .LVL375
12891
+ .8byte .LVL376
12892
+ .2byte 0x1
12893
+ .byte 0x6b
12894
+ .8byte .LVL376
12895
+ .8byte .LVL377
12896
+ .2byte 0x1
12897
+ .byte 0x50
12898
+ .8byte .LVL377
12899
+ .8byte .LVL379
12900
+ .2byte 0x1
12901
+ .byte 0x6b
12902
+ .8byte .LVL379
12903
+ .8byte .LVL380
12904
+ .2byte 0x1
12905
+ .byte 0x50
12906
+ .8byte .LVL380
12907
+ .8byte .LVL381
12908
+ .2byte 0x1
12909
+ .byte 0x6b
12910
+ .8byte .LVL381
12911
+ .8byte .LVL382
12912
+ .2byte 0x1
12913
+ .byte 0x50
12914
+ .8byte .LVL382
12915
+ .8byte .LVL387
12916
+ .2byte 0x1
12917
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12918
+ .8byte .LVL387
12919
+ .8byte .LVL388
12920
+ .2byte 0x1
12921
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12922
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12923
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12924
+ .2byte 0x1
12925
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12926
+ .8byte .LVL389
12927
+ .8byte .LVL390
12928
+ .2byte 0x1
12929
+ .byte 0x50
12930
+ .8byte .LVL390
12931
+ .8byte .LVL392
12932
+ .2byte 0x1
12933
+ .byte 0x6b
12934
+ .8byte .LVL392
12935
+ .8byte .LVL393
12936
+ .2byte 0x1
12937
+ .byte 0x50
12938
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12939
+ .8byte .LVL394
12940
+ .2byte 0x1
12941
+ .byte 0x6b
12942
+ .8byte 0
12943
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12944
+.LLST84:
12945
+ .8byte .LVL264
12946
+ .8byte .LVL265
12947
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12948
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12949
+ .8byte .LVL265
12950
+ .8byte .LVL267
12951
+ .2byte 0x3
12952
+ .byte 0x8f
12953
+ .sleb128 232
12954
+ .8byte .LVL288
12955
+ .8byte .LVL315
12956
+ .2byte 0x3
12957
+ .byte 0x8f
12958
+ .sleb128 232
12959
+ .8byte .LVL317
12960
+ .8byte .LVL394
12961
+ .2byte 0x3
12962
+ .byte 0x8f
12963
+ .sleb128 232
12964
+ .8byte 0
12965
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12966
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12967
+ .8byte .LVL289
12968
+ .8byte .LVL316
12969
+ .2byte 0x4
12970
+ .byte 0x40
12971
+ .byte 0x3c
12972
+ .byte 0x24
12973
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12974
+ .8byte .LVL317
12975
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12976
+ .2byte 0x4
12977
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12978
+ .byte 0x3c
12979
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12980
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12981
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12982
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12983
+.LLST86:
12984
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12985
+ .8byte .LVL316
12986
+ .2byte 0x6
12987
+ .byte 0xc
12988
+ .4byte 0x40004
12989
+ .byte 0x9f
12990
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12991
+ .8byte .LVL394
12992
+ .2byte 0x6
12993
+ .byte 0xc
12994
+ .4byte 0x40004
12995
+ .byte 0x9f
12996
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12997
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12998
+.LLST87:
12999
+ .8byte .LVL291
13000
+ .8byte .LVL316
13001
+ .2byte 0x5
13002
+ .byte 0x11
13003
+ .sleb128 -65536
13004
+ .byte 0x9f
13005
+ .8byte .LVL317
13006
+ .8byte .LVL394
13007
+ .2byte 0x5
13008
+ .byte 0x11
13009
+ .sleb128 -65536
13010
+ .byte 0x9f
13011
+ .8byte 0
13012
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13013
+.LLST88:
13014
+ .8byte .LVL292
13015
+ .8byte .LVL316
13016
+ .2byte 0x6
13017
+ .byte 0x11
13018
+ .sleb128 -16776704
13019
+ .byte 0x9f
13020
+ .8byte .LVL317
13021
+ .8byte .LVL394
13022
+ .2byte 0x6
13023
+ .byte 0x11
13024
+ .sleb128 -16776704
13025
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13026
+ .8byte 0
13027
+ .8byte 0
13028
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13029
+ .8byte .LVL293
13030
+ .8byte .LVL316
13031
+ .2byte 0x5
13032
+ .byte 0x11
13033
+ .sleb128 -65522
13034
+ .byte 0x9f
13035
+ .8byte .LVL317
13036
+ .8byte .LVL394
13037
+ .2byte 0x5
13038
+ .byte 0x11
13039
+ .sleb128 -65522
13040
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13041
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13042
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13043
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13044
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13045
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13046
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13047
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13048
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13049
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13050
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13051
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13052
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13053
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13054
+ .byte 0xf0
13055
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13056
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13057
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13058
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13059
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13060
+ .8byte .LVL316
13061
+ .2byte 0x2
13062
+ .byte 0x31
13063
+ .byte 0x9f
13064
+ .8byte .LVL317
13065
+ .8byte .LVL394
13066
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13067
+ .byte 0x31
13068
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13069
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13070
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13071
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13072
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13073
+ .8byte .LVL316
13074
+ .2byte 0x3
13075
+ .byte 0x8
13076
+ .byte 0x7a
13077
+ .byte 0x9f
13078
+ .8byte .LVL317
13079
+ .8byte .LVL394
13080
+ .2byte 0x3
13081
+ .byte 0x8
13082
+ .byte 0x7a
13083
+ .byte 0x9f
13084
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13085
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13086
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13087
+ .8byte .LVL297
13088
+ .8byte .LVL316
13089
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13090
+ .byte 0x8
13091
+ .byte 0x25
13092
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13093
+ .8byte .LVL317
13094
+ .8byte .LVL394
13095
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13096
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13097
+ .byte 0x25
13098
+ .byte 0x9f
13099
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13100
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13101
+.LLST94:
13102
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13103
+ .8byte .LVL316
13104
+ .2byte 0x2
13105
+ .byte 0x30
13106
+ .byte 0x9f
13107
+ .8byte .LVL317
13108
+ .8byte .LVL394
13109
+ .2byte 0x2
13110
+ .byte 0x30
13111
+ .byte 0x9f
13112
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13113
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13114
+.LLST95:
13115
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13116
+ .8byte .LVL316
13117
+ .2byte 0x2
13118
+ .byte 0x30
13119
+ .byte 0x9f
13120
+ .8byte .LVL317
13121
+ .8byte .LVL394
13122
+ .2byte 0x2
13123
+ .byte 0x30
13124
+ .byte 0x9f
13125
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13126
+ .8byte 0
13127
+.LLST96:
13128
+ .8byte .LVL300
13129
+ .8byte .LVL316
13130
+ .2byte 0x2
13131
+ .byte 0x30
13132
+ .byte 0x9f
13133
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13134
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13135
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13136
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13137
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13138
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13139
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13140
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13141
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13142
+ .8byte .LVL316
13143
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13144
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13145
+ .byte 0x9f
13146
+ .8byte .LVL317
13147
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13148
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13149
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13150
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13151
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13152
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13153
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13154
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13155
+ .8byte .LVL316
13156
+ .2byte 0x2
13157
+ .byte 0x3b
13158
+ .byte 0x9f
13159
+ .8byte .LVL317
13160
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13161
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13162
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13163
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13164
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13165
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13166
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13167
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13168
+ .8byte .LVL316
13169
+ .2byte 0x2
13170
+ .byte 0x38
13171
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13172
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13173
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13174
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13175
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13176
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13177
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13178
+ .8byte 0
13179
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13180
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13181
+ .8byte .LVL316
13182
+ .2byte 0x2
13183
+ .byte 0x30
13184
+ .byte 0x9f
13185
+ .8byte .LVL317
13186
+ .8byte .LVL394
13187
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13188
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13189
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13190
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13191
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13192
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13193
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13194
+ .8byte .LVL316
13195
+ .2byte 0x2
13196
+ .byte 0x30
13197
+ .byte 0x9f
13198
+ .8byte .LVL317
13199
+ .8byte .LVL394
13200
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13201
+ .byte 0x30
13202
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13203
+ .8byte 0
13204
+ .8byte 0
13205
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13206
+ .8byte .LVL306
13207
+ .8byte .LVL316
13208
+ .2byte 0x2
13209
+ .byte 0x30
13210
+ .byte 0x9f
13211
+ .8byte .LVL317
13212
+ .8byte .LVL394
13213
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13214
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13215
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13216
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13217
+ .8byte 0
13218
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13219
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13220
+ .8byte .LVL315
13221
+ .2byte 0x1
13222
+ .byte 0x69
13223
+ .8byte .LVL317
13224
+ .8byte .LVL394
13225
+ .2byte 0x1
13226
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13227
+ .8byte 0
13228
+ .8byte 0
13229
+.LLST104:
13230
+ .8byte .LVL308
13231
+ .8byte .LVL313
13232
+ .2byte 0x1
13233
+ .byte 0x65
13234
+ .8byte .LVL317
13235
+ .8byte .LVL332
13236
+ .2byte 0x1
13237
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13238
+ .8byte 0
13239
+ .8byte 0
13240
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13241
+ .8byte .LVL309
13242
+ .8byte .LVL316
13243
+ .2byte 0x6
13244
+ .byte 0xc
13245
+ .4byte 0x10001
13246
+ .byte 0x9f
13247
+ .8byte .LVL317
13248
+ .8byte .LVL394
13249
+ .2byte 0x6
13250
+ .byte 0xc
13251
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13252
+ .byte 0x9f
13253
+ .8byte 0
13254
+ .8byte 0
13255
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13256
+ .8byte .LVL314
13257
+ .8byte .LVL316
13258
+ .2byte 0x5
13259
+ .byte 0x11
13260
+ .sleb128 -65533
13261
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13262
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13263
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13264
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13265
+ .8byte .LVL317
13266
+ .8byte .LVL394
13267
+ .2byte 0x6
13268
+ .byte 0x11
13269
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13270
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13271
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13272
+ .8byte 0
13273
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13274
+ .8byte .LVL319
13275
+ .8byte .LVL394
13276
+ .2byte 0x3
13277
+ .byte 0x8
13278
+ .byte 0xf0
13279
+ .byte 0x9f
13280
+ .8byte 0
13281
+ .8byte 0
13282
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13283
+ .8byte .LVL320
13284
+ .8byte .LVL394
13285
+ .2byte 0x2
13286
+ .byte 0x31
13287
+ .byte 0x9f
13288
+ .8byte 0
13289
+ .8byte 0
13290
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13291
+ .8byte .LVL321
13292
+ .8byte .LVL394
13293
+ .2byte 0x3
13294
+ .byte 0x8
13295
+ .byte 0x7a
13296
+ .byte 0x9f
13297
+ .8byte 0
13298
+ .8byte 0
13299
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13300
+ .8byte .LVL322
13301
+ .8byte .LVL394
13302
+ .2byte 0x2
13303
+ .byte 0x45
13304
+ .byte 0x9f
13305
+ .8byte 0
13306
+ .8byte 0
13307
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13308
+ .8byte .LVL323
13309
+ .8byte .LVL394
13310
+ .2byte 0x3
13311
+ .byte 0x8
13312
+ .byte 0xdc
13313
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13314
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13315
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13316
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13317
+ .8byte .LVL324
13318
+ .8byte .LVL394
13319
+ .2byte 0x3
13320
+ .byte 0x8
13321
+ .byte 0x92
13322
+ .byte 0x9f
13323
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13324
+ .8byte 0
13325
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13326
+ .8byte .LVL325
13327
+ .8byte .LVL394
13328
+ .2byte 0x3
13329
+ .byte 0x8
13330
+ .byte 0x79
13331
+ .byte 0x9f
13332
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13333
+ .8byte 0
13334
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13335
+ .8byte .LVL326
13336
+ .8byte .LVL394
13337
+ .2byte 0x3
13338
+ .byte 0x8
13339
+ .byte 0x81
13340
+ .byte 0x9f
13341
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13342
+ .8byte 0
13343
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13344
+ .8byte .LVL327
13345
+ .8byte .LVL394
13346
+ .2byte 0x3
13347
+ .byte 0x8
13348
+ .byte 0x7e
13349
+ .byte 0x9f
13350
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13351
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13352
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13353
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13354
+ .8byte .LVL394
13355
+ .2byte 0x3
13356
+ .byte 0x8
13357
+ .byte 0x21
13358
+ .byte 0x9f
13359
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13360
+ .8byte 0
13361
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13362
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13363
+ .8byte .LVL394
13364
+ .2byte 0x2
13365
+ .byte 0x41
13366
+ .byte 0x9f
13367
+ .8byte 0
13368
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13369
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13370
+ .8byte .LVL330
13371
+ .8byte .LVL394
13372
+ .2byte 0x3
13373
+ .byte 0x8
13374
+ .byte 0x9d
13375
+ .byte 0x9f
13376
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13377
+ .8byte 0
13378
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13379
+ .8byte .LVL331
13380
+ .8byte .LVL394
13381
+ .2byte 0x2
13382
+ .byte 0x32
13383
+ .byte 0x9f
13384
+ .8byte 0
13385
+ .8byte 0
13386
+.LLST121:
13387
+ .8byte .LVL333
13388
+ .8byte .LVL394
13389
+ .2byte 0x2
13390
+ .byte 0x30
13391
+ .byte 0x9f
13392
+ .8byte 0
13393
+ .8byte 0
13394
+.LLST122:
13395
+ .8byte .LVL334
13396
+ .8byte .LVL394
13397
+ .2byte 0x2
13398
+ .byte 0x30
13399
+ .byte 0x9f
13400
+ .8byte 0
13401
+ .8byte 0
13402
+.LLST123:
13403
+ .8byte .LVL335
13404
+ .8byte .LVL394
13405
+ .2byte 0x6
13406
+ .byte 0xc
13407
+ .4byte 0x10001
13408
+ .byte 0x9f
13409
+ .8byte 0
13410
+ .8byte 0
13411
+.LLST124:
13412
+ .8byte .LVL339
13413
+ .8byte .LVL394
13414
+ .2byte 0x6
13415
+ .byte 0x11
13416
+ .sleb128 -16776704
13417
+ .byte 0x9f
13418
+ .8byte 0
13419
+ .8byte 0
13420
+.LLST125:
13421
+ .8byte .LVL341
13422
+ .8byte .LVL394
13423
+ .2byte 0x5
13424
+ .byte 0x11
13425
+ .sleb128 -65535
13426
+ .byte 0x9f
13427
+ .8byte 0
13428
+ .8byte 0
13429
+.LLST126:
13430
+ .8byte .LVL342
13431
+ .8byte .LVL394
13432
+ .2byte 0x3
13433
+ .byte 0x8
13434
+ .byte 0xfb
13435
+ .byte 0x9f
13436
+ .8byte 0
13437
+ .8byte 0
13438
+.LLST127:
13439
+ .8byte .LVL343
13440
+ .8byte .LVL394
13441
+ .2byte 0x2
13442
+ .byte 0x30
13443
+ .byte 0x9f
13444
+ .8byte 0
13445
+ .8byte 0
13446
+.LLST128:
13447
+ .8byte .LVL344
13448
+ .8byte .LVL394
13449
+ .2byte 0x6
13450
+ .byte 0xc
13451
+ .4byte 0x10001
13452
+ .byte 0x9f
13453
+ .8byte 0
13454
+ .8byte 0
13455
+.LLST129:
13456
+ .8byte .LVL348
13457
+ .8byte .LVL394
13458
+ .2byte 0x5
13459
+ .byte 0x11
13460
+ .sleb128 -65534
13461
+ .byte 0x9f
13462
+ .8byte 0
13463
+ .8byte 0
13464
+.LLST130:
13465
+ .8byte .LVL350
13466
+ .8byte .LVL394
13467
+ .2byte 0x3
13468
+ .byte 0x8
13469
+ .byte 0xc0
13470
+ .byte 0x9f
13471
+ .8byte 0
13472
+ .8byte 0
13473
+.LLST131:
13474
+ .8byte .LVL351
13475
+ .8byte .LVL354
13476
+ .2byte 0x1
13477
+ .byte 0x51
13478
+ .8byte 0
13479
+ .8byte 0
13480
+.LLST132:
13481
+ .8byte .LVL352
13482
+ .8byte .LVL394
13483
+ .2byte 0x1
13484
+ .byte 0x6a
13485
+ .8byte 0
13486
+ .8byte 0
13487
+.LLST133:
13488
+ .8byte .LVL353
13489
+ .8byte .LVL394
13490
+ .2byte 0x6
13491
+ .byte 0xc
13492
+ .4byte 0x10001
13493
+ .byte 0x9f
13494
+ .8byte 0
13495
+ .8byte 0
13496
+.LLST134:
13497
+ .8byte .LVL358
13498
+ .8byte .LVL394
13499
+ .2byte 0x6
13500
+ .byte 0x11
13501
+ .sleb128 -16762368
13502
+ .byte 0x9f
13503
+ .8byte 0
13504
+ .8byte 0
13505
+.LLST135:
13506
+ .8byte .LVL360
13507
+ .8byte .LVL394
13508
+ .2byte 0x5
13509
+ .byte 0x11
13510
+ .sleb128 -65535
13511
+ .byte 0x9f
13512
+ .8byte 0
13513
+ .8byte 0
13514
+.LLST136:
13515
+ .8byte .LVL361
13516
+ .8byte .LVL394
13517
+ .2byte 0x3
13518
+ .byte 0x8
13519
+ .byte 0xff
13520
+ .byte 0x9f
13521
+ .8byte 0
13522
+ .8byte 0
13523
+.LLST137:
13524
+ .8byte .LVL362
13525
+ .8byte .LVL394
13526
+ .2byte 0x2
13527
+ .byte 0x3a
13528
+ .byte 0x9f
13529
+ .8byte 0
13530
+ .8byte 0
13531
+.LLST138:
13532
+ .8byte .LVL363
13533
+ .8byte .LVL394
13534
+ .2byte 0x6
13535
+ .byte 0xc
13536
+ .4byte 0x10001
13537
+ .byte 0x9f
13538
+ .8byte 0
13539
+ .8byte 0
13540
+.LLST139:
13541
+ .8byte .LVL367
13542
+ .8byte .LVL394
13543
+ .2byte 0x5
13544
+ .byte 0x11
13545
+ .sleb128 -65534
13546
+ .byte 0x9f
13547
+ .8byte 0
13548
+ .8byte 0
13549
+.LLST140:
13550
+ .8byte .LVL369
13551
+ .8byte .LVL394
13552
+ .2byte 0x2
13553
+ .byte 0x31
13554
+ .byte 0x9f
13555
+ .8byte 0
13556
+ .8byte 0
13557
+.LLST141:
13558
+ .8byte .LVL370
13559
+ .8byte .LVL394
13560
+ .2byte 0x3
13561
+ .byte 0x8
13562
+ .byte 0xbf
13563
+ .byte 0x9f
13564
+ .8byte 0
13565
+ .8byte 0
13566
+.LLST142:
13567
+ .8byte .LVL371
13568
+ .8byte .LVL394
13569
+ .2byte 0x2
13570
+ .byte 0x30
13571
+ .byte 0x9f
13572
+ .8byte 0
13573
+ .8byte 0
13574
+.LLST143:
13575
+ .8byte .LVL372
13576
+ .8byte .LVL394
13577
+ .2byte 0x6
13578
+ .byte 0xc
13579
+ .4byte 0x10001
13580
+ .byte 0x9f
13581
+ .8byte 0
13582
+ .8byte 0
13583
+.LLST144:
13584
+ .8byte .LVL381
13585
+ .8byte .LVL394
13586
+ .2byte 0x5
13587
+ .byte 0x11
13588
+ .sleb128 -65535
13589
+ .byte 0x9f
13590
+ .8byte 0
13591
+ .8byte 0
13592
+.LLST145:
13593
+ .8byte .LVL383
13594
+ .8byte .LVL394
13595
+ .2byte 0x2
13596
+ .byte 0x32
13597
+ .byte 0x9f
13598
+ .8byte 0
13599
+ .8byte 0
13600
+.LLST146:
13601
+ .8byte .LVL384
13602
+ .8byte .LVL394
13603
+ .2byte 0x3
13604
+ .byte 0x8
13605
+ .byte 0xbf
13606
+ .byte 0x9f
13607
+ .8byte 0
13608
+ .8byte 0
13609
+.LLST147:
13610
+ .8byte .LVL385
13611
+ .8byte .LVL394
13612
+ .2byte 0x6
13613
+ .byte 0xc
13614
+ .4byte 0x10001
13615
+ .byte 0x9f
13616
+ .8byte 0
13617
+ .8byte 0
13618
+.LLST148:
13619
+ .8byte .LVL273
13620
+ .8byte .LVL276
13621
+ .2byte 0x1
13622
+ .byte 0x67
13623
+ .8byte .LVL283
13624
+ .8byte .LVL284
13625
+ .2byte 0x1
13626
+ .byte 0x67
13627
+ .8byte 0
13628
+ .8byte 0
13629
+.LLST149:
13630
+ .8byte .LVL273
13631
+ .8byte .LVL280
13632
+ .2byte 0x1
13633
+ .byte 0x69
13634
+ .8byte .LVL283
13635
+ .8byte .LVL285
13636
+ .2byte 0x1
13637
+ .byte 0x69
13638
+ .8byte 0
13639
+ .8byte 0
13640
+.LLST150:
13641
+ .8byte .LVL273
13642
+ .8byte .LVL280
13643
+ .2byte 0x1
13644
+ .byte 0x6c
13645
+ .8byte .LVL283
13646
+ .8byte .LVL285
13647
+ .2byte 0x1
13648
+ .byte 0x6c
13649
+ .8byte 0
13650
+ .8byte 0
13651
+.LLST151:
13652
+ .8byte .LVL273
13653
+ .8byte .LVL280
13654
+ .2byte 0x1
13655
+ .byte 0x68
13656
+ .8byte .LVL283
13657
+ .8byte .LVL285
13658
+ .2byte 0x1
13659
+ .byte 0x68
13660
+ .8byte 0
13661
+ .8byte 0
13662
+.LLST152:
13663
+ .8byte .LVL275
13664
+ .8byte .LVL276
13665
+ .2byte 0xd
13666
+ .byte 0x8f
13667
+ .sleb128 254
13668
+ .byte 0x94
13669
+ .byte 0x2
13670
+ .byte 0x20
13671
+ .byte 0x87
13672
+ .sleb128 0
13673
+ .byte 0x8
13674
+ .byte 0xff
13675
+ .byte 0x1a
13676
+ .byte 0x1a
13677
+ .byte 0x9f
13678
+ .8byte .LVL283
13679
+ .8byte .LVL284
13680
+ .2byte 0xf
13681
+ .byte 0x8f
13682
+ .sleb128 254
13683
+ .byte 0x94
13684
+ .byte 0x2
13685
+ .byte 0x20
13686
+ .byte 0x87
13687
+ .sleb128 0
13688
+ .byte 0x8
13689
+ .byte 0xff
13690
+ .byte 0x1a
13691
+ .byte 0x38
13692
+ .byte 0x24
13693
+ .byte 0x1a
13694
+ .byte 0x9f
13695
+ .8byte 0
13696
+ .8byte 0
13697
+.LLST153:
13698
+ .8byte .LVL274
13699
+ .8byte .LVL277
13700
+ .2byte 0x1
13701
+ .byte 0x50
13702
+ .8byte .LVL283
13703
+ .8byte .LVL285
13704
+ .2byte 0x1
13705
+ .byte 0x50
13706
+ .8byte 0
13707
+ .8byte 0
13708
+.LLST30:
13709
+ .8byte .LVL66
13710
+ .8byte .LVL67-1
13711
+ .2byte 0x1
13712
+ .byte 0x50
13713
+ .8byte .LVL67-1
13714
+ .8byte .LFE269
13715
+ .2byte 0x4
13716
+ .byte 0xf3
13717
+ .uleb128 0x1
13718
+ .byte 0x50
13719
+ .byte 0x9f
13720
+ .8byte 0
13721
+ .8byte 0
13722
+.LLST31:
13723
+ .8byte .LVL66
13724
+ .8byte .LVL67-1
13725
+ .2byte 0x1
13726
+ .byte 0x51
13727
+ .8byte .LVL67-1
13728
+ .8byte .LVL72
13729
+ .2byte 0x1
13730
+ .byte 0x6a
13731
+ .8byte .LVL72
13732
+ .8byte .LVL73
13733
+ .2byte 0x4
13734
+ .byte 0xf3
13735
+ .uleb128 0x1
13736
+ .byte 0x51
13737
+ .byte 0x9f
13738
+ .8byte .LVL73
13739
+ .8byte .LFE269
13740
+ .2byte 0x1
13741
+ .byte 0x6a
13742
+ .8byte 0
13743
+ .8byte 0
13744
+.LLST32:
13745
+ .8byte .LVL66
13746
+ .8byte .LVL67-1
13747
+ .2byte 0x1
13748
+ .byte 0x52
13749
+ .8byte .LVL67-1
13750
+ .8byte .LVL67
13751
+ .2byte 0x1
13752
+ .byte 0x68
13753
+ .8byte .LVL67
13754
+ .8byte .LVL71
13755
+ .2byte 0x1
13756
+ .byte 0x64
13757
+ .8byte .LVL71
13758
+ .8byte .LVL73
13759
+ .2byte 0x6
13760
+ .byte 0xf3
13761
+ .uleb128 0x1
13762
+ .byte 0x52
13763
+ .byte 0x31
13764
+ .byte 0x26
13765
+ .byte 0x9f
13766
+ .8byte .LVL73
13767
+ .8byte .LFE269
13768
+ .2byte 0x1
13769
+ .byte 0x64
13770
+ .8byte 0
13771
+ .8byte 0
13772
+.LLST33:
13773
+ .8byte .LVL66
13774
+ .8byte .LVL67-1
13775
+ .2byte 0x1
13776
+ .byte 0x53
13777
+ .8byte .LVL67-1
13778
+ .8byte .LVL70
13779
+ .2byte 0x1
13780
+ .byte 0x65
13781
+ .8byte .LVL70
13782
+ .8byte .LFE269
13783
+ .2byte 0x4
13784
+ .byte 0xf3
13785
+ .uleb128 0x1
13786
+ .byte 0x53
13787
+ .byte 0x9f
13788
+ .8byte 0
13789
+ .8byte 0
13790
+.LLST34:
13791
+ .8byte .LVL66
13792
+ .8byte .LVL70
13793
+ .2byte 0x2
13794
+ .byte 0x30
13795
+ .byte 0x9f
13796
+ .8byte .LVL73
13797
+ .8byte .LVL83
13798
+ .2byte 0x2
13799
+ .byte 0x30
13800
+ .byte 0x9f
13801
+ .8byte .LVL83
13802
+ .8byte .LVL84
13803
+ .2byte 0x1
13804
+ .byte 0x50
13805
+ .8byte .LVL87
13806
+ .8byte .LVL88
13807
+ .2byte 0x1
13808
+ .byte 0x50
13809
+ .8byte .LVL104
13810
+ .8byte .LVL106
13811
+ .2byte 0x1
13812
+ .byte 0x50
13813
+ .8byte .LVL110
13814
+ .8byte .LVL112
13815
+ .2byte 0x1
13816
+ .byte 0x50
13817
+ .8byte .LVL130
13818
+ .8byte .LVL132
13819
+ .2byte 0x1
13820
+ .byte 0x50
13821
+ .8byte .LVL137
13822
+ .8byte .LVL139
13823
+ .2byte 0x1
13824
+ .byte 0x50
13825
+ .8byte .LVL146
13826
+ .8byte .LVL148
13827
+ .2byte 0x1
13828
+ .byte 0x50
13829
+ .8byte .LVL152
13830
+ .8byte .LVL154
13831
+ .2byte 0x1
13832
+ .byte 0x50
13833
+ .8byte .LVL160
13834
+ .8byte .LVL162
13835
+ .2byte 0x1
13836
+ .byte 0x50
13837
+ .8byte .LVL167
13838
+ .8byte .LVL168
13839
+ .2byte 0x1
13840
+ .byte 0x50
13841
+ .8byte .LVL169
13842
+ .8byte .LVL170
13843
+ .2byte 0x1
13844
+ .byte 0x50
13845
+ .8byte .LVL171
13846
+ .8byte .LVL172
13847
+ .2byte 0x1
13848
+ .byte 0x50
13849
+ .8byte .LVL176
13850
+ .8byte .LVL177
13851
+ .2byte 0x1
13852
+ .byte 0x50
13853
+ .8byte .LVL178
13854
+ .8byte .LVL179
13855
+ .2byte 0x1
13856
+ .byte 0x50
13857
+ .8byte .LVL180
13858
+ .8byte .LVL181
13859
+ .2byte 0x1
13860
+ .byte 0x50
13861
+ .8byte .LVL187
13862
+ .8byte .LVL189
13863
+ .2byte 0x1
13864
+ .byte 0x50
13865
+ .8byte .LVL193
13866
+ .8byte .LVL195
13867
+ .2byte 0x1
13868
+ .byte 0x50
13869
+ .8byte .LVL198
13870
+ .8byte .LFE269
13871
+ .2byte 0x1
13872
+ .byte 0x50
13873
+ .8byte 0
13874
+ .8byte 0
13875
+.LLST35:
13876
+ .8byte .LVL67
13877
+ .8byte .LVL68
13878
+ .2byte 0x1
13879
+ .byte 0x50
13880
+ .8byte .LVL68
13881
+ .8byte .LVL69
13882
+ .2byte 0x1
13883
+ .byte 0x67
13884
+ .8byte .LVL73
13885
+ .8byte .LFE269
13886
+ .2byte 0x1
13887
+ .byte 0x67
13888
+ .8byte 0
13889
+ .8byte 0
13890
+.LLST36:
13891
+ .8byte .LVL74
13892
+ .8byte .LVL86
13893
+ .2byte 0x4
13894
+ .byte 0x40
13895
+ .byte 0x3c
13896
+ .byte 0x24
13897
+ .byte 0x9f
13898
+ .8byte .LVL87
13899
+ .8byte .LFE269
13900
+ .2byte 0x4
13901
+ .byte 0x40
13902
+ .byte 0x3c
13903
+ .byte 0x24
13904
+ .byte 0x9f
13905
+ .8byte 0
13906
+ .8byte 0
13907
+.LLST37:
13908
+ .8byte .LVL75
13909
+ .8byte .LVL86
13910
+ .2byte 0x6
13911
+ .byte 0xc
13912
+ .4byte 0x40004
13913
+ .byte 0x9f
13914
+ .8byte .LVL87
13915
+ .8byte .LFE269
13916
+ .2byte 0x6
13917
+ .byte 0xc
13918
+ .4byte 0x40004
13919
+ .byte 0x9f
13920
+ .8byte 0
13921
+ .8byte 0
13922
+.LLST38:
13923
+ .8byte .LVL76
13924
+ .8byte .LVL86
13925
+ .2byte 0x5
13926
+ .byte 0x11
13927
+ .sleb128 -65536
13928
+ .byte 0x9f
13929
+ .8byte .LVL87
13930
+ .8byte .LFE269
13931
+ .2byte 0x5
13932
+ .byte 0x11
13933
+ .sleb128 -65536
13934
+ .byte 0x9f
13935
+ .8byte 0
13936
+ .8byte 0
13937
+.LLST39:
13938
+ .8byte .LVL77
13939
+ .8byte .LVL86
13940
+ .2byte 0x6
13941
+ .byte 0x11
13942
+ .sleb128 -16776704
13943
+ .byte 0x9f
13944
+ .8byte .LVL87
13945
+ .8byte .LFE269
13946
+ .2byte 0x6
13947
+ .byte 0x11
13948
+ .sleb128 -16776704
13949
+ .byte 0x9f
13950
+ .8byte 0
13951
+ .8byte 0
13952
+.LLST40:
13953
+ .8byte .LVL78
13954
+ .8byte .LVL86
13955
+ .2byte 0x5
13956
+ .byte 0x11
13957
+ .sleb128 -65534
13958
+ .byte 0x9f
13959
+ .8byte .LVL87
13960
+ .8byte .LFE269
13961
+ .2byte 0x5
13962
+ .byte 0x11
13963
+ .sleb128 -65534
13964
+ .byte 0x9f
13965
+ .8byte 0
13966
+ .8byte 0
13967
+.LLST41:
13968
+ .8byte .LVL79
13969
+ .8byte .LVL86
13970
+ .2byte 0x3
13971
+ .byte 0x8
13972
+ .byte 0xfc
13973
+ .byte 0x9f
13974
+ .8byte .LVL87
13975
+ .8byte .LFE269
13976
+ .2byte 0x3
13977
+ .byte 0x8
13978
+ .byte 0xfc
13979
+ .byte 0x9f
13980
+ .8byte 0
13981
+ .8byte 0
13982
+.LLST42:
13983
+ .8byte .LVL80
13984
+ .8byte .LVL86
13985
+ .2byte 0x2
13986
+ .byte 0x30
13987
+ .byte 0x9f
13988
+ .8byte .LVL87
13989
+ .8byte .LFE269
13990
+ .2byte 0x2
13991
+ .byte 0x30
13992
+ .byte 0x9f
13993
+ .8byte 0
13994
+ .8byte 0
13995
+.LLST43:
13996
+ .8byte .LVL81
13997
+ .8byte .LVL86
13998
+ .2byte 0x2
13999
+ .byte 0x30
14000
+ .byte 0x9f
14001
+ .8byte .LVL87
14002
+ .8byte .LFE269
14003
+ .2byte 0x2
14004
+ .byte 0x30
14005
+ .byte 0x9f
14006
+ .8byte 0
14007
+ .8byte 0
14008
+.LLST44:
14009
+ .8byte .LVL82
14010
+ .8byte .LVL86
14011
+ .2byte 0x6
14012
+ .byte 0xc
14013
+ .4byte 0x10001
14014
+ .byte 0x9f
14015
+ .8byte .LVL87
14016
+ .8byte .LFE269
14017
+ .2byte 0x6
14018
+ .byte 0xc
14019
+ .4byte 0x10001
14020
+ .byte 0x9f
14021
+ .8byte 0
14022
+ .8byte 0
14023
+.LLST45:
14024
+ .8byte .LVL102
14025
+ .8byte .LVL104-1
14026
+ .2byte 0x1
14027
+ .byte 0x55
14028
+ .8byte .LVL104-1
14029
+ .8byte .LVL165
14030
+ .2byte 0x6
14031
+ .byte 0x88
14032
+ .sleb128 0
14033
+ .byte 0x9
14034
+ .byte 0xf7
14035
+ .byte 0x24
14036
+ .byte 0x9f
14037
+ .8byte 0
14038
+ .8byte 0
14039
+.LLST46:
14040
+ .8byte .LVL142
14041
+ .8byte .LVL145
14042
+ .2byte 0x1
14043
+ .byte 0x51
14044
+ .8byte 0
14045
+ .8byte 0
14046
+.LLST47:
14047
+ .8byte .LVL143
14048
+ .8byte .LVL159
14049
+ .2byte 0x1
14050
+ .byte 0x65
14051
+ .8byte .LVL159
14052
+ .8byte .LFE269
14053
+ .2byte 0xa
14054
+ .byte 0xf3
14055
+ .uleb128 0x1
14056
+ .byte 0x53
14057
+ .byte 0xa
14058
+ .2byte 0xffff
14059
+ .byte 0x1a
14060
+ .byte 0x38
14061
+ .byte 0x25
14062
+ .byte 0x9f
14063
+ .8byte 0
14064
+ .8byte 0
14065
+.LLST55:
14066
+ .8byte .LVL212
14067
+ .8byte .LVL213-1
14068
+ .2byte 0x1
14069
+ .byte 0x50
14070
+ .8byte .LVL213-1
14071
+ .8byte .LVL221
14072
+ .2byte 0x1
14073
+ .byte 0x66
14074
+ .8byte .LVL221
14075
+ .8byte .LVL227
14076
+ .2byte 0x4
14077
+ .byte 0xf3
14078
+ .uleb128 0x1
14079
+ .byte 0x50
14080
+ .byte 0x9f
14081
+ .8byte .LVL227
14082
+ .8byte .LVL228
14083
+ .2byte 0x1
14084
+ .byte 0x66
14085
+ .8byte .LVL228
14086
+ .8byte .LFE268
14087
+ .2byte 0x4
14088
+ .byte 0xf3
14089
+ .uleb128 0x1
14090
+ .byte 0x50
14091
+ .byte 0x9f
14092
+ .8byte 0
14093
+ .8byte 0
14094
+.LLST56:
14095
+ .8byte .LVL212
14096
+ .8byte .LVL213-1
14097
+ .2byte 0x1
14098
+ .byte 0x51
14099
+ .8byte .LVL213-1
14100
+ .8byte .LVL217
14101
+ .2byte 0x4
14102
+ .byte 0xf3
14103
+ .uleb128 0x1
14104
+ .byte 0x51
14105
+ .byte 0x9f
14106
+ .8byte .LVL217
14107
+ .8byte .LVL225
14108
+ .2byte 0x1
14109
+ .byte 0x63
14110
+ .8byte .LVL227
14111
+ .8byte .LFE268
14112
+ .2byte 0x1
14113
+ .byte 0x63
14114
+ .8byte 0
14115
+ .8byte 0
14116
+.LLST57:
14117
+ .8byte .LVL212
14118
+ .8byte .LVL213-1
14119
+ .2byte 0x1
14120
+ .byte 0x52
14121
+ .8byte .LVL213-1
14122
+ .8byte .LVL222
14123
+ .2byte 0x1
14124
+ .byte 0x65
14125
+ .8byte .LVL222
14126
+ .8byte .LVL227
14127
+ .2byte 0x4
14128
+ .byte 0xf3
14129
+ .uleb128 0x1
14130
+ .byte 0x52
14131
+ .byte 0x9f
14132
+ .8byte .LVL227
14133
+ .8byte .LVL228
14134
+ .2byte 0x1
14135
+ .byte 0x65
14136
+ .8byte .LVL228
14137
+ .8byte .LFE268
14138
+ .2byte 0x4
14139
+ .byte 0xf3
14140
+ .uleb128 0x1
14141
+ .byte 0x52
14142
+ .byte 0x9f
14143
+ .8byte 0
14144
+ .8byte 0
14145
+.LLST58:
14146
+ .8byte .LVL212
14147
+ .8byte .LVL213-1
14148
+ .2byte 0x1
14149
+ .byte 0x53
14150
+ .8byte .LVL213-1
14151
+ .8byte .LVL222
14152
+ .2byte 0x1
14153
+ .byte 0x67
14154
+ .8byte .LVL222
14155
+ .8byte .LVL226
14156
+ .2byte 0x3
14157
+ .byte 0x87
14158
+ .sleb128 -1
14159
+ .byte 0x9f
14160
+ .8byte .LVL227
14161
+ .8byte .LVL228
14162
+ .2byte 0x1
14163
+ .byte 0x67
14164
+ .8byte .LVL228
14165
+ .8byte .LVL244
14166
+ .2byte 0x3
14167
+ .byte 0x87
14168
+ .sleb128 -1
14169
+ .byte 0x9f
14170
+ .8byte .LVL244
14171
+ .8byte .LFE268
14172
+ .2byte 0x1
14173
+ .byte 0x67
14174
+ .8byte 0
14175
+ .8byte 0
14176
+.LLST59:
14177
+ .8byte .LVL214
14178
+ .8byte .LVL215
14179
+ .2byte 0x1
14180
+ .byte 0x50
14181
+ .8byte .LVL215
14182
+ .8byte .LVL225
14183
+ .2byte 0x1
14184
+ .byte 0x64
14185
+ .8byte .LVL227
14186
+ .8byte .LFE268
14187
+ .2byte 0x1
14188
+ .byte 0x64
14189
+ .8byte 0
14190
+ .8byte 0
14191
+.LLST60:
14192
+ .8byte .LVL217
14193
+ .8byte .LVL218
14194
+ .2byte 0x1
14195
+ .byte 0x50
14196
+ .8byte .LVL218
14197
+ .8byte .LVL226
14198
+ .2byte 0x1
14199
+ .byte 0x68
14200
+ .8byte .LVL227
14201
+ .8byte .LFE268
14202
+ .2byte 0x1
14203
+ .byte 0x68
14204
+ .8byte 0
14205
+ .8byte 0
14206
+.LLST61:
14207
+ .8byte .LVL217
14208
+ .8byte .LVL224
14209
+ .2byte 0x1
14210
+ .byte 0x65
14211
+ .8byte .LVL227
14212
+ .8byte .LVL236
14213
+ .2byte 0x1
14214
+ .byte 0x65
14215
+ .8byte .LVL238
14216
+ .8byte .LVL241
14217
+ .2byte 0x1
14218
+ .byte 0x65
14219
+ .8byte .LVL241
14220
+ .8byte .LVL242
14221
+ .2byte 0x3
14222
+ .byte 0x85
14223
+ .sleb128 1
14224
+ .byte 0x9f
14225
+ .8byte .LVL242
14226
+ .8byte .LVL245
14227
+ .2byte 0x3
14228
+ .byte 0x85
14229
+ .sleb128 2
14230
+ .byte 0x9f
14231
+ .8byte .LVL245
14232
+ .8byte .LFE268
14233
+ .2byte 0x1
14234
+ .byte 0x65
14235
+ .8byte 0
14236
+ .8byte 0
14237
+.LLST62:
14238
+ .8byte .LVL241
14239
+ .8byte .LVL243
14240
+ .2byte 0x1
14241
+ .byte 0x50
14242
+ .8byte 0
14243
+ .8byte 0
14244
+.LLST63:
14245
+ .8byte .LVL217
14246
+ .8byte .LVL222
14247
+ .2byte 0x2
14248
+ .byte 0x30
14249
+ .byte 0x9f
14250
+ .8byte .LVL222
14251
+ .8byte .LVL223
14252
+ .2byte 0x1
14253
+ .byte 0x66
14254
+ .8byte .LVL227
14255
+ .8byte .LVL228
14256
+ .2byte 0x2
14257
+ .byte 0x30
14258
+ .byte 0x9f
14259
+ .8byte .LVL228
14260
+ .8byte .LVL234
14261
+ .2byte 0x1
14262
+ .byte 0x66
14263
+ .8byte .LVL234
14264
+ .8byte .LVL235
14265
+ .2byte 0x1
14266
+ .byte 0x50
14267
+ .8byte .LVL235
14268
+ .8byte .LVL238
14269
+ .2byte 0x1
14270
+ .byte 0x66
14271
+ .8byte .LVL238
14272
+ .8byte .LVL239
14273
+ .2byte 0x1
14274
+ .byte 0x50
14275
+ .8byte .LVL239
14276
+ .8byte .LFE268
14277
+ .2byte 0x1
14278
+ .byte 0x66
14279
+ .8byte 0
14280
+ .8byte 0
14281
+.LLST64:
14282
+ .8byte .LVL220
14283
+ .8byte .LVL227
14284
+ .2byte 0x6
14285
+ .byte 0xc
14286
+ .4byte 0x10001
14287
+ .byte 0x9f
14288
+ .8byte .LVL228
14289
+ .8byte .LFE268
14290
+ .2byte 0x6
14291
+ .byte 0xc
14292
+ .4byte 0x10001
14293
+ .byte 0x9f
14294
+ .8byte 0
14295
+ .8byte 0
14296
+.LLST65:
14297
+ .8byte .LVL229
14298
+ .8byte .LVL231
14299
+ .2byte 0x1
14300
+ .byte 0x51
14301
+ .8byte .LVL231
14302
+ .8byte .LVL232
14303
+ .2byte 0x6
14304
+ .byte 0x84
14305
+ .sleb128 0
14306
+ .byte 0x6
14307
+ .byte 0x23
14308
+ .uleb128 0x104
14309
+ .8byte .LVL232
14310
+ .8byte .LVL236
14311
+ .2byte 0x8
14312
+ .byte 0x83
14313
+ .sleb128 -1
14314
+ .byte 0x11
14315
+ .sleb128 -65536
14316
+ .byte 0x21
14317
+ .byte 0x9f
14318
+ .8byte .LVL238
14319
+ .8byte .LFE268
14320
+ .2byte 0x8
14321
+ .byte 0x83
14322
+ .sleb128 -1
14323
+ .byte 0x11
14324
+ .sleb128 -65536
14325
+ .byte 0x21
14326
+ .byte 0x9f
14327
+ .8byte 0
14328
+ .8byte 0
14329
+.LLST66:
14330
+ .8byte .LVL230
14331
+ .8byte .LVL236
14332
+ .2byte 0x6
14333
+ .byte 0xc
14334
+ .4byte 0x10001
14335
+ .byte 0x9f
14336
+ .8byte .LVL238
14337
+ .8byte .LFE268
14338
+ .2byte 0x6
14339
+ .byte 0xc
14340
+ .4byte 0x10001
14341
+ .byte 0x9f
14342
+ .8byte 0
14343
+ .8byte 0
14344
+.LLST68:
14345
+ .8byte .LVL240
14346
+ .8byte .LVL243
14347
+ .2byte 0x1
14348
+ .byte 0x50
14349
+ .8byte 0
14350
+ .8byte 0
14351
+.LLST67:
14352
+ .8byte .LVL236
14353
+ .8byte .LVL238
14354
+ .2byte 0x4
14355
+ .byte 0x40
14356
+ .byte 0x3c
14357
+ .byte 0x24
14358
+ .byte 0x9f
14359
+ .8byte 0
14360
+ .8byte 0
14361
+.LLST0:
14362
+ .8byte .LVL0
14363
+ .8byte .LVL1
14364
+ .2byte 0x1
14365
+ .byte 0x51
14366
+ .8byte .LVL1
14367
+ .8byte .LFE263
14368
+ .2byte 0x4
14369
+ .byte 0xf3
14370
+ .uleb128 0x1
14371
+ .byte 0x51
14372
+ .byte 0x9f
14373
+ .8byte 0
14374
+ .8byte 0
14375
+.LLST16:
14376
+ .8byte .LVL28
14377
+ .8byte .LVL31
14378
+ .2byte 0x1
14379
+ .byte 0x50
14380
+ .8byte .LVL31
14381
+ .8byte .LFE262
14382
+ .2byte 0x4
14383
+ .byte 0xf3
14384
+ .uleb128 0x1
14385
+ .byte 0x50
14386
+ .byte 0x9f
14387
+ .8byte 0
14388
+ .8byte 0
14389
+.LLST17:
14390
+ .8byte .LVL28
14391
+ .8byte .LVL29
14392
+ .2byte 0x1
14393
+ .byte 0x51
14394
+ .8byte .LVL29
14395
+ .8byte .LVL33
14396
+ .2byte 0x1
14397
+ .byte 0x63
14398
+ .8byte .LVL33
14399
+ .8byte .LFE262
14400
+ .2byte 0x4
14401
+ .byte 0xf3
14402
+ .uleb128 0x1
14403
+ .byte 0x51
14404
+ .byte 0x9f
14405
+ .8byte 0
14406
+ .8byte 0
14407
+.LLST18:
14408
+ .8byte .LVL28
14409
+ .8byte .LVL32-1
14410
+ .2byte 0x1
14411
+ .byte 0x52
14412
+ .8byte .LVL32-1
14413
+ .8byte .LFE262
14414
+ .2byte 0x4
14415
+ .byte 0xf3
14416
+ .uleb128 0x1
14417
+ .byte 0x52
14418
+ .byte 0x9f
14419
+ .8byte 0
14420
+ .8byte 0
14421
+.LLST19:
14422
+ .8byte .LVL28
14423
+ .8byte .LVL32-1
14424
+ .2byte 0x1
14425
+ .byte 0x53
14426
+ .8byte .LVL32-1
14427
+ .8byte .LFE262
14428
+ .2byte 0x4
14429
+ .byte 0xf3
14430
+ .uleb128 0x1
14431
+ .byte 0x53
14432
+ .byte 0x9f
14433
+ .8byte 0
14434
+ .8byte 0
14435
+.LLST20:
14436
+ .8byte .LVL35
14437
+ .8byte .LVL38
14438
+ .2byte 0x3
14439
+ .byte 0x83
14440
+ .sleb128 -1
14441
+ .byte 0x9f
14442
+ .8byte .LVL38
14443
+ .8byte .LVL39
14444
+ .2byte 0x1
14445
+ .byte 0x63
14446
+ .8byte .LVL39
14447
+ .8byte .LVL41
14448
+ .2byte 0x3
14449
+ .byte 0x83
14450
+ .sleb128 -1
14451
+ .byte 0x9f
14452
+ .8byte .LVL41
14453
+ .8byte .LVL42
14454
+ .2byte 0x1
14455
+ .byte 0x63
14456
+ .8byte 0
14457
+ .8byte 0
14458
+.LLST21:
14459
+ .8byte .LVL37
14460
+ .8byte .LVL40-1
14461
+ .2byte 0x1
14462
+ .byte 0x51
14463
+ .8byte .LVL41
14464
+ .8byte .LFE278
14465
+ .2byte 0x1
14466
+ .byte 0x51
14467
+ .8byte 0
14468
+ .8byte 0
14469
+.LLST22:
14470
+ .8byte .LVL36
14471
+ .8byte .LVL40-1
14472
+ .2byte 0x1
14473
+ .byte 0x51
14474
+ .8byte .LVL41
14475
+ .8byte .LFE278
14476
+ .2byte 0x1
14477
+ .byte 0x51
14478
+ .8byte 0
14479
+ .8byte 0
14480
+.LLST23:
14481
+ .8byte .LVL43
14482
+ .8byte .LVL46
14483
+ .2byte 0x3
14484
+ .byte 0x83
14485
+ .sleb128 -1
14486
+ .byte 0x9f
14487
+ .8byte .LVL46
14488
+ .8byte .LVL48
14489
+ .2byte 0x1
14490
+ .byte 0x63
14491
+ .8byte .LVL48
14492
+ .8byte .LVL50
14493
+ .2byte 0x3
14494
+ .byte 0x83
14495
+ .sleb128 -1
14496
+ .byte 0x9f
14497
+ .8byte .LVL51
14498
+ .8byte .LFE279
14499
+ .2byte 0x1
14500
+ .byte 0x63
14501
+ .8byte 0
14502
+ .8byte 0
14503
+.LLST24:
14504
+ .8byte .LVL45
14505
+ .8byte .LVL47
14506
+ .2byte 0x1
14507
+ .byte 0x50
14508
+ .8byte .LVL49
14509
+ .8byte .LVL50
14510
+ .2byte 0x1
14511
+ .byte 0x50
14512
+ .8byte .LVL51
14513
+ .8byte .LVL52
14514
+ .2byte 0x1
14515
+ .byte 0x50
14516
+ .8byte 0
14517
+ .8byte 0
14518
+.LLST25:
14519
+ .8byte .LVL44
14520
+ .8byte .LVL47
14521
+ .2byte 0x1
14522
+ .byte 0x50
14523
+ .8byte .LVL49
14524
+ .8byte .LVL50
14525
+ .2byte 0x1
14526
+ .byte 0x50
14527
+ .8byte .LVL51
14528
+ .8byte .LVL52
14529
+ .2byte 0x1
14530
+ .byte 0x50
14531
+ .8byte 0
14532
+ .8byte 0
14533
+.LLST26:
14534
+ .8byte .LVL53
14535
+ .8byte .LVL54
14536
+ .2byte 0x1
14537
+ .byte 0x51
14538
+ .8byte .LVL54
14539
+ .8byte .LVL56
14540
+ .2byte 0x1
14541
+ .byte 0x63
14542
+ .8byte .LVL56
14543
+ .8byte .LVL58
14544
+ .2byte 0x4
14545
+ .byte 0xf3
14546
+ .uleb128 0x1
14547
+ .byte 0x51
14548
+ .byte 0x9f
14549
+ .8byte .LVL58
14550
+ .8byte .LVL64
14551
+ .2byte 0x1
14552
+ .byte 0x63
14553
+ .8byte .LVL64
14554
+ .8byte .LFE280
14555
+ .2byte 0x4
14556
+ .byte 0xf3
14557
+ .uleb128 0x1
14558
+ .byte 0x51
14559
+ .byte 0x9f
14560
+ .8byte 0
14561
+ .8byte 0
14562
+.LLST27:
14563
+ .8byte .LVL54
14564
+ .8byte .LVL60
14565
+ .2byte 0x1
14566
+ .byte 0x64
14567
+ .8byte .LVL60
14568
+ .8byte .LVL61
14569
+ .2byte 0x3
14570
+ .byte 0x84
14571
+ .sleb128 -1
14572
+ .byte 0x9f
14573
+ .8byte .LVL61
14574
+ .8byte .LVL65
14575
+ .2byte 0x1
14576
+ .byte 0x64
14577
+ .8byte 0
14578
+ .8byte 0
14579
+.LLST28:
14580
+ .8byte .LVL55
14581
+ .8byte .LVL57
14582
+ .2byte 0x1
14583
+ .byte 0x50
14584
+ .8byte .LVL58
14585
+ .8byte .LVL59
14586
+ .2byte 0x1
14587
+ .byte 0x50
14588
+ .8byte 0
14589
+ .8byte 0
14590
+.LLST29:
14591
+ .8byte .LVL56
14592
+ .8byte .LVL58
14593
+ .2byte 0x1
14594
+ .byte 0x63
14595
+ .8byte 0
14596
+ .8byte 0
14597
+.LLST48:
14598
+ .8byte .LVL199
14599
+ .8byte .LVL205-1
14600
+ .2byte 0x1
14601
+ .byte 0x50
14602
+ .8byte .LVL205-1
14603
+ .8byte .LVL211
14604
+ .2byte 0x4
14605
+ .byte 0xf3
14606
+ .uleb128 0x1
14607
+ .byte 0x50
14608
+ .byte 0x9f
14609
+ .8byte .LVL211
14610
+ .8byte .LFE267
14611
+ .2byte 0x1
14612
+ .byte 0x50
14613
+ .8byte 0
14614
+ .8byte 0
14615
+.LLST49:
14616
+ .8byte .LVL199
14617
+ .8byte .LVL203
14618
+ .2byte 0x1
14619
+ .byte 0x51
14620
+ .8byte .LVL203
14621
+ .8byte .LFE267
14622
+ .2byte 0x4
14623
+ .byte 0xf3
14624
+ .uleb128 0x1
14625
+ .byte 0x51
14626
+ .byte 0x9f
14627
+ .8byte 0
14628
+ .8byte 0
14629
+.LLST50:
14630
+ .8byte .LVL199
14631
+ .8byte .LVL206
14632
+ .2byte 0x2
14633
+ .byte 0x30
14634
+ .byte 0x9f
14635
+ .8byte .LVL206
14636
+ .8byte .LVL208
14637
+ .2byte 0x1
14638
+ .byte 0x50
14639
+ .8byte .LVL208
14640
+ .8byte .LVL210
14641
+ .2byte 0x1
14642
+ .byte 0x63
14643
+ .8byte .LVL210
14644
+ .8byte .LVL211
14645
+ .2byte 0x1
14646
+ .byte 0x50
14647
+ .8byte .LVL211
14648
+ .8byte .LFE267
14649
+ .2byte 0x2
14650
+ .byte 0x30
14651
+ .byte 0x9f
14652
+ .8byte 0
14653
+ .8byte 0
14654
+.LLST51:
14655
+ .8byte .LVL202
14656
+ .8byte .LVL204
14657
+ .2byte 0x2
14658
+ .byte 0x30
14659
+ .byte 0x9f
14660
+ .8byte 0
14661
+ .8byte 0
14662
+.LLST52:
14663
+ .8byte .LVL204
14664
+ .8byte .LVL211
14665
+ .2byte 0x6
14666
+ .byte 0xc
14667
+ .4byte 0x10001
14668
+ .byte 0x9f
14669
+ .8byte 0
14670
+ .8byte 0
14671
+.LLST53:
14672
+ .8byte .LVL207
14673
+ .8byte .LVL209
14674
+ .2byte 0x4
14675
+ .byte 0xf3
14676
+ .uleb128 0x1
14677
+ .byte 0x50
14678
+ .byte 0x9f
14679
+ .8byte 0
14680
+ .8byte 0
14681
+.LLST54:
14682
+ .8byte .LVL207
14683
+ .8byte .LVL209
14684
+ .2byte 0x4
14685
+ .byte 0xf3
14686
+ .uleb128 0x1
14687
+ .byte 0x51
14688
+ .byte 0x9f
14689
+ .8byte 0
14690
+ .8byte 0
14691
+ .section .debug_aranges,"",@progbits
14692
+ .4byte 0xec
14693
+ .2byte 0x2
14694
+ .4byte .Ldebug_info0
14695
+ .byte 0x8
14696
+ .byte 0
14697
+ .2byte 0
14698
+ .2byte 0
14699
+ .8byte .LFB263
14700
+ .8byte .LFE263-.LFB263
14701
+ .8byte .LFB276
14702
+ .8byte .LFE276-.LFB276
14703
+ .8byte .LFB274
14704
+ .8byte .LFE274-.LFB274
14705
+ .8byte .LFB273
14706
+ .8byte .LFE273-.LFB273
14707
+ .8byte .LFB277
14708
+ .8byte .LFE277-.LFB277
14709
+ .8byte .LFB262
14710
+ .8byte .LFE262-.LFB262
14711
+ .8byte .LFB278
14712
+ .8byte .LFE278-.LFB278
14713
+ .8byte .LFB279
14714
+ .8byte .LFE279-.LFB279
14715
+ .8byte .LFB280
14716
+ .8byte .LFE280-.LFB280
14717
+ .8byte .LFB269
14718
+ .8byte .LFE269-.LFB269
14719
+ .8byte .LFB267
14720
+ .8byte .LFE267-.LFB267
14721
+ .8byte .LFB268
14722
+ .8byte .LFE268-.LFB268
14723
+ .8byte .LFB272
14724
+ .8byte .LFE272-.LFB272
14725
+ .8byte 0
14726
+ .8byte 0
14727
+ .section .debug_ranges,"",@progbits
14728
+.Ldebug_ranges0:
14729
+ .8byte .LBB48
14730
+ .8byte .LBE48
14731
+ .8byte .LBB49
14732
+ .8byte .LBE49
14733
+ .8byte 0
14734
+ .8byte 0
14735
+ .8byte .LBB64
14736
+ .8byte .LBE64
14737
+ .8byte .LBB66
14738
+ .8byte .LBE66
14739
+ .8byte 0
14740
+ .8byte 0
14741
+ .8byte .LBB65
14742
+ .8byte .LBE65
14743
+ .8byte .LBB67
14744
+ .8byte .LBE67
14745
+ .8byte 0
14746
+ .8byte 0
14747
+ .8byte .LBB68
14748
+ .8byte .LBE68
14749
+ .8byte .LBB69
14750
+ .8byte .LBE69
14751
+ .8byte 0
14752
+ .8byte 0
14753
+ .8byte .LBB73
14754
+ .8byte .LBE73
14755
+ .8byte .LBB74
14756
+ .8byte .LBE74
14757
+ .8byte 0
14758
+ .8byte 0
14759
+ .8byte .LBB92
14760
+ .8byte .LBE92
14761
+ .8byte .LBB93
14762
+ .8byte .LBE93
14763
+ .8byte 0
14764
+ .8byte 0
14765
+ .8byte .LBB98
14766
+ .8byte .LBE98
14767
+ .8byte .LBB99
14768
+ .8byte .LBE99
14769
+ .8byte 0
14770
+ .8byte 0
14771
+ .8byte .LBB103
14772
+ .8byte .LBE103
14773
+ .8byte .LBB105
14774
+ .8byte .LBE105
14775
+ .8byte 0
14776
+ .8byte 0
14777
+ .8byte .LBB104
14778
+ .8byte .LBE104
14779
+ .8byte .LBB106
14780
+ .8byte .LBE106
14781
+ .8byte 0
14782
+ .8byte 0
14783
+ .8byte .LBB107
14784
+ .8byte .LBE107
14785
+ .8byte .LBB108
14786
+ .8byte .LBE108
14787
+ .8byte 0
14788
+ .8byte 0
14789
+ .8byte .LBB112
14790
+ .8byte .LBE112
14791
+ .8byte .LBB113
14792
+ .8byte .LBE113
14793
+ .8byte 0
14794
+ .8byte 0
14795
+ .8byte .LBB118
14796
+ .8byte .LBE118
14797
+ .8byte .LBB119
14798
+ .8byte .LBE119
14799
+ .8byte 0
14800
+ .8byte 0
14801
+ .8byte .LBB123
14802
+ .8byte .LBE123
14803
+ .8byte .LBB124
14804
+ .8byte .LBE124
14805
+ .8byte 0
14806
+ .8byte 0
14807
+ .8byte .LBB128
14808
+ .8byte .LBE128
14809
+ .8byte .LBB129
14810
+ .8byte .LBE129
14811
+ .8byte 0
14812
+ .8byte 0
14813
+ .8byte .LBB135
14814
+ .8byte .LBE135
14815
+ .8byte .LBB136
14816
+ .8byte .LBE136
14817
+ .8byte 0
14818
+ .8byte 0
14819
+ .8byte .LBB140
14820
+ .8byte .LBE140
14821
+ .8byte .LBB141
14822
+ .8byte .LBE141
14823
+ .8byte 0
14824
+ .8byte 0
14825
+ .8byte .LBB144
14826
+ .8byte .LBE144
14827
+ .8byte .LBB145
14828
+ .8byte .LBE145
14829
+ .8byte 0
14830
+ .8byte 0
14831
+ .8byte .LBB168
14832
+ .8byte .LBE168
14833
+ .8byte .LBB169
14834
+ .8byte .LBE169
14835
+ .8byte 0
14836
+ .8byte 0
14837
+ .8byte .LBB170
14838
+ .8byte .LBE170
14839
+ .8byte .LBB171
14840
+ .8byte .LBE171
14841
+ .8byte 0
14842
+ .8byte 0
14843
+ .8byte .LBB172
14844
+ .8byte .LBE172
14845
+ .8byte .LBB173
14846
+ .8byte .LBE173
14847
+ .8byte 0
14848
+ .8byte 0
14849
+ .8byte .LBB174
14850
+ .8byte .LBE174
14851
+ .8byte .LBB175
14852
+ .8byte .LBE175
14853
+ .8byte 0
14854
+ .8byte 0
14855
+ .8byte .LBB244
14856
+ .8byte .LBE244
14857
+ .8byte .LBB324
14858
+ .8byte .LBE324
14859
+ .8byte .LBB325
14860
+ .8byte .LBE325
14861
+ .8byte .LBB335
14862
+ .8byte .LBE335
14863
+ .8byte .LBB336
14864
+ .8byte .LBE336
14865
+ .8byte 0
14866
+ .8byte 0
14867
+ .8byte .LBB264
14868
+ .8byte .LBE264
14869
+ .8byte .LBB266
14870
+ .8byte .LBE266
14871
+ .8byte 0
14872
+ .8byte 0
14873
+ .8byte .LBB265
14874
+ .8byte .LBE265
14875
+ .8byte .LBB267
14876
+ .8byte .LBE267
14877
+ .8byte 0
14878
+ .8byte 0
14879
+ .8byte .LBB268
14880
+ .8byte .LBE268
14881
+ .8byte .LBB269
14882
+ .8byte .LBE269
14883
+ .8byte 0
14884
+ .8byte 0
14885
+ .8byte .LBB270
14886
+ .8byte .LBE270
14887
+ .8byte .LBB271
14888
+ .8byte .LBE271
14889
+ .8byte 0
14890
+ .8byte 0
14891
+ .8byte .LBB288
14892
+ .8byte .LBE288
14893
+ .8byte .LBB289
14894
+ .8byte .LBE289
14895
+ .8byte 0
14896
+ .8byte 0
14897
+ .8byte .LBB294
14898
+ .8byte .LBE294
14899
+ .8byte .LBB295
14900
+ .8byte .LBE295
14901
+ .8byte 0
14902
+ .8byte 0
14903
+ .8byte .LBB298
14904
+ .8byte .LBE298
14905
+ .8byte .LBB300
14906
+ .8byte .LBE300
14907
+ .8byte 0
14908
+ .8byte 0
14909
+ .8byte .LBB299
14910
+ .8byte .LBE299
14911
+ .8byte .LBB301
14912
+ .8byte .LBE301
14913
+ .8byte 0
14914
+ .8byte 0
14915
+ .8byte .LBB302
14916
+ .8byte .LBE302
14917
+ .8byte .LBB303
14918
+ .8byte .LBE303
14919
+ .8byte 0
14920
+ .8byte 0
14921
+ .8byte .LBB308
14922
+ .8byte .LBE308
14923
+ .8byte .LBB309
14924
+ .8byte .LBE309
14925
+ .8byte 0
14926
+ .8byte 0
14927
+ .8byte .LBB314
14928
+ .8byte .LBE314
14929
+ .8byte .LBB315
14930
+ .8byte .LBE315
14931
+ .8byte 0
14932
+ .8byte 0
14933
+ .8byte .LBB326
14934
+ .8byte .LBE326
14935
+ .8byte .LBB332
14936
+ .8byte .LBE332
14937
+ .8byte .LBB333
14938
+ .8byte .LBE333
14939
+ .8byte .LBB334
14940
+ .8byte .LBE334
14941
+ .8byte .LBB337
14942
+ .8byte .LBE337
14943
+ .8byte 0
14944
+ .8byte 0
14945
+ .8byte .LFB263
14946
+ .8byte .LFE263
14947
+ .8byte .LFB276
14948
+ .8byte .LFE276
14949
+ .8byte .LFB274
14950
+ .8byte .LFE274
14951
+ .8byte .LFB273
14952
+ .8byte .LFE273
14953
+ .8byte .LFB277
14954
+ .8byte .LFE277
14955
+ .8byte .LFB262
14956
+ .8byte .LFE262
14957
+ .8byte .LFB278
14958
+ .8byte .LFE278
14959
+ .8byte .LFB279
14960
+ .8byte .LFE279
14961
+ .8byte .LFB280
14962
+ .8byte .LFE280
14963
+ .8byte .LFB269
14964
+ .8byte .LFE269
14965
+ .8byte .LFB267
14966
+ .8byte .LFE267
14967
+ .8byte .LFB268
14968
+ .8byte .LFE268
14969
+ .8byte .LFB272
14970
+ .8byte .LFE272
14971
+ .8byte 0
14972
+ .8byte 0
14973
+ .section .debug_line,"",@progbits
14974
+.Ldebug_line0:
14975
+ .section .debug_str,"MS",@progbits,1
14976
+.LASF222:
14977
+ .string "UCLASS_SERIAL"
14978
+.LASF320:
14979
+ .string "gd_t"
14980
+.LASF15:
14981
+ .string "long int"
14982
+.LASF39:
14983
+ .string "uclass_node"
14984
+.LASF423:
14985
+ .string "request"
14986
+.LASF313:
14987
+ .string "phandle"
14988
+.LASF53:
14989
+ .string "flash_id"
14990
+.LASF405:
14991
+ .string "misc_ops"
14992
+.LASF377:
14993
+ .string "mem_malloc_start"
14994
+.LASF428:
14995
+ .string "rk3562_secure_otp_write"
14996
+.LASF333:
14997
+ .string "net_hostname"
14998
+.LASF28:
14999
+ .string "name"
15000
+.LASF249:
15001
+ .string "UCLASS_ETH_PHY"
15002
+.LASF229:
15003
+ .string "UCLASS_THERMAL"
15004
+.LASF60:
15005
+ .string "base"
15006
+.LASF355:
15007
+ .string "NETLOOP_RESTART"
15008
+.LASF288:
15009
+ .string "new_gd"
15010
+.LASF349:
15011
+ .string "net_boot_file_size"
15012
+.LASF134:
15013
+ .string "fit_hdr_os"
15014
+.LASF181:
15015
+ .string "UCLASS_FIRMWARE"
15016
+.LASF458:
15017
+ .string "udelay"
15018
+.LASF142:
15019
+ .string "fit_noffset_fdt"
15020
+.LASF74:
15021
+ .string "bi_dsp_freq"
15022
+.LASF304:
15023
+ .string "malloc_ptr"
15024
+.LASF91:
15025
+ .string "_datarellocal_start_ofs"
15026
+.LASF94:
15027
+ .string "fdt32_t"
15028
+.LASF146:
15029
+ .string "rd_start"
15030
+.LASF372:
15031
+ .string "property"
15032
+.LASF266:
15033
+ .string "tlb_emerg"
15034
+.LASF78:
15035
+ .string "bi_enetaddr"
15036
+.LASF291:
15037
+ .string "uclass_root"
15038
+.LASF188:
15039
+ .string "UCLASS_IRQ"
15040
+.LASF421:
15041
+ .string "rockchip_secure_otp_ofdata_to_platdata"
15042
+.LASF438:
15043
+ .string "buffer"
15044
+.LASF235:
15045
+ .string "UCLASS_USB_HUB"
15046
+.LASF230:
15047
+ .string "UCLASS_TIMER"
15048
+.LASF42:
15049
+ .string "flags"
15050
+.LASF139:
15051
+ .string "fit_noffset_rd"
15052
+.LASF270:
15053
+ .string "baudrate"
15054
+.LASF335:
15055
+ .string "net_ethaddr"
15056
+.LASF301:
15057
+ .string "timebase_l"
15058
+.LASF21:
15059
+ .string "errno"
15060
+.LASF32:
15061
+ .string "node"
15062
+.LASF360:
15063
+ .string "bind"
15064
+.LASF456:
15065
+ .string "printf"
15066
+.LASF402:
15067
+ .string "DECOM_ZLIB"
15068
+.LASF8:
15069
+ .string "unsigned int"
15070
+.LASF47:
15071
+ .string "next"
15072
+.LASF101:
15073
+ .string "version"
15074
+.LASF397:
15075
+ .string "per_device_platdata_auto_alloc_size"
15076
+.LASF131:
15077
+ .string "legacy_hdr_os_copy"
15078
+.LASF195:
15079
+ .string "UCLASS_MMC"
15080
+.LASF290:
15081
+ .string "dm_root_f"
15082
+.LASF341:
15083
+ .string "net_rx_packet"
15084
+.LASF38:
15085
+ .string "parent_priv"
15086
+.LASF176:
15087
+ .string "UCLASS_CROS_EC"
15088
+.LASF311:
15089
+ .string "console_evt"
15090
+.LASF191:
15091
+ .string "UCLASS_LPC"
15092
+.LASF105:
15093
+ .string "size_dt_struct"
15094
+.LASF380:
15095
+ .string "p_current"
15096
+.LASF345:
15097
+ .string "net_our_vlan"
15098
+.LASF22:
15099
+ .string "___strtok"
15100
+.LASF67:
15101
+ .string "bi_memsize"
15102
+.LASF121:
15103
+ .string "image_info"
15104
+.LASF200:
15105
+ .string "UCLASS_NVME"
15106
+.LASF156:
15107
+ .string "bootm_headers_t"
15108
+.LASF253:
15109
+ .string "UCLASS_RNG"
15110
+.LASF250:
15111
+ .string "UCLASS_MDIO"
15112
+.LASF187:
15113
+ .string "UCLASS_IDE"
15114
+.LASF274:
15115
+ .string "bus_clk"
15116
+.LASF378:
15117
+ .string "mem_malloc_end"
15118
+.LASF225:
15119
+ .string "UCLASS_SPI_FLASH"
15120
+.LASF189:
15121
+ .string "UCLASS_KEYBOARD"
15122
+.LASF72:
15123
+ .string "bi_sramsize"
15124
+.LASF185:
15125
+ .string "UCLASS_I2C_MUX"
15126
+.LASF298:
15127
+ .string "fdt_blob_kern"
15128
+.LASF278:
15129
+ .string "env_addr"
15130
+.LASF48:
15131
+ .string "prev"
15132
+.LASF227:
15133
+ .string "UCLASS_SYSCON"
15134
+.LASF171:
15135
+ .string "UCLASS_BLK"
15136
+.LASF212:
15137
+ .string "UCLASS_PWRSEQ"
15138
+.LASF132:
15139
+ .string "legacy_hdr_valid"
15140
+.LASF265:
15141
+ .string "tlb_fillptr"
15142
+.LASF82:
15143
+ .string "bi_arch_number"
15144
+.LASF324:
15145
+ .string "load_addr"
15146
+.LASF292:
15147
+ .string "fdt_blob"
15148
+.LASF329:
15149
+ .string "net_gateway"
15150
+.LASF166:
15151
+ .string "UCLASS_PCI_EMUL"
15152
+.LASF425:
15153
+ .string "offset"
15154
+.LASF350:
15155
+ .string "net_boot_file_expected_size_in_blocks"
15156
+.LASF404:
15157
+ .string "OTP_NS"
15158
+.LASF415:
15159
+ .string "spl_rockchip_otp_start"
15160
+.LASF206:
15161
+ .string "UCLASS_PHY"
15162
+.LASF455:
15163
+ .string "dev_get_driver_data"
15164
+.LASF3:
15165
+ .string "signed char"
15166
+.LASF203:
15167
+ .string "UCLASS_PCH"
15168
+.LASF100:
15169
+ .string "off_mem_rsvmap"
15170
+.LASF163:
15171
+ .string "UCLASS_TEST_PROBE"
15172
+.LASF149:
15173
+ .string "ft_len"
15174
+.LASF19:
15175
+ .string "uint32_t"
15176
+.LASF385:
15177
+ .string "udevice_id"
15178
+.LASF326:
15179
+ .string "save_size"
15180
+.LASF440:
15181
+ .string "read_end"
15182
+.LASF379:
15183
+ .string "mem_malloc_brk"
15184
+.LASF436:
15185
+ .string "rk3562_secure_otp_write_2_bytes_noecc"
15186
+.LASF143:
15187
+ .string "fit_hdr_setup"
15188
+.LASF300:
15189
+ .string "timebase_h"
15190
+.LASF160:
15191
+ .string "UCLASS_TEST"
15192
+.LASF87:
15193
+ .string "IRQ_STACK_START"
15194
+.LASF420:
15195
+ .string "_u_boot_list_2_driver_2_rockchip_secure_otp"
15196
+.LASF70:
15197
+ .string "bi_flashoffset"
15198
+.LASF201:
15199
+ .string "UCLASS_PANEL"
15200
+.LASF267:
15201
+ .string "pre_serial"
15202
+.LASF431:
15203
+ .string "rockchip_secure_otp_capability"
15204
+.LASF36:
15205
+ .string "uclass"
15206
+.LASF162:
15207
+ .string "UCLASS_TEST_BUS"
15208
+.LASF461:
15209
+ .string "/home/lxh/uboot/u-boot"
15210
+.LASF239:
15211
+ .string "UCLASS_VIDEO_CONSOLE"
15212
+.LASF361:
15213
+ .string "probe"
15214
+.LASF10:
15215
+ .string "long long unsigned int"
15216
+.LASF261:
15217
+ .string "lastinc"
15218
+.LASF389:
15219
+ .string "post_bind"
15220
+.LASF285:
15221
+ .string "irq_sp"
15222
+.LASF327:
15223
+ .string "in_addr"
15224
+.LASF197:
15225
+ .string "UCLASS_MTD"
15226
+.LASF216:
15227
+ .string "UCLASS_RESET"
15228
+.LASF117:
15229
+ .string "ih_type"
15230
+.LASF80:
15231
+ .string "bi_intfreq"
15232
+.LASF172:
15233
+ .string "UCLASS_CLK"
15234
+.LASF351:
15235
+ .string "net_ping_ip"
15236
+.LASF79:
15237
+ .string "bi_ethspeed"
15238
+.LASF376:
15239
+ .string "ofnode"
15240
+.LASF231:
15241
+ .string "UCLASS_TPM"
15242
+.LASF316:
15243
+ .string "child"
15244
+.LASF444:
15245
+ .string "rockchip_secure_otp_wait_flag"
15246
+.LASF457:
15247
+ .string "malloc_simple"
15248
+.LASF59:
15249
+ .string "lmb_property"
15250
+.LASF269:
15251
+ .string "enable"
15252
+.LASF429:
15253
+ .string "data_byte"
15254
+.LASF263:
15255
+ .string "tlb_addr"
15256
+.LASF374:
15257
+ .string "value"
15258
+.LASF184:
15259
+ .string "UCLASS_I2C_GENERIC"
15260
+.LASF99:
15261
+ .string "off_dt_strings"
15262
+.LASF419:
15263
+ .string "rockchip_otp_ids"
15264
+.LASF103:
15265
+ .string "boot_cpuid_phys"
15266
+.LASF362:
15267
+ .string "remove"
15268
+.LASF133:
15269
+ .string "fit_uname_cfg"
15270
+.LASF106:
15271
+ .string "working_fdt"
15272
+.LASF317:
15273
+ .string "sibling"
15274
+.LASF460:
15275
+ .string "drivers/misc/rk3562-secure-otp.c"
15276
+.LASF118:
15277
+ .string "ih_comp"
15278
+.LASF202:
15279
+ .string "UCLASS_PANEL_BACKLIGHT"
15280
+.LASF81:
15281
+ .string "bi_busfreq"
15282
+.LASF297:
15283
+ .string "ufdt_blob"
15284
+.LASF280:
15285
+ .string "ram_top"
15286
+.LASF272:
15287
+ .string "global_data"
15288
+.LASF328:
15289
+ .string "s_addr"
15290
+.LASF127:
15291
+ .string "arch"
15292
+.LASF226:
15293
+ .string "UCLASS_SPI_GENERIC"
15294
+.LASF318:
15295
+ .string "mtd_info"
15296
+.LASF95:
15297
+ .string "fdt_header"
15298
+.LASF177:
15299
+ .string "UCLASS_DISPLAY"
15300
+.LASF391:
15301
+ .string "pre_probe"
15302
+.LASF353:
15303
+ .string "net_loop_state"
15304
+.LASF55:
15305
+ .string "protect"
15306
+.LASF347:
15307
+ .string "net_restart_wrap"
15308
+.LASF307:
15309
+ .string "video_bottom"
15310
+.LASF439:
15311
+ .string "write_end"
15312
+.LASF71:
15313
+ .string "bi_sramstart"
15314
+.LASF224:
15315
+ .string "UCLASS_SPMI"
15316
+.LASF220:
15317
+ .string "UCLASS_SCMI_AGENT"
15318
+.LASF23:
15319
+ .string "_Bool"
15320
+.LASF12:
15321
+ .string "phys_size_t"
15322
+.LASF45:
15323
+ .string "udevice"
15324
+.LASF37:
15325
+ .string "uclass_priv"
15326
+.LASF123:
15327
+ .string "image_len"
15328
+.LASF319:
15329
+ .string "jt_funcs"
15330
+.LASF409:
15331
+ .string "call"
15332
+.LASF331:
15333
+ .string "net_dns_server"
15334
+.LASF398:
15335
+ .string "__invalid_size_argument_for_IOC"
15336
+.LASF57:
15337
+ .string "flash_info"
15338
+.LASF463:
15339
+ .string "free"
15340
+.LASF289:
15341
+ .string "dm_root"
15342
+.LASF108:
15343
+ .string "ih_magic"
15344
+.LASF218:
15345
+ .string "UCLASS_RAMDISK"
15346
+.LASF124:
15347
+ .string "load"
15348
+.LASF26:
15349
+ .string "_binary_u_boot_bin_end"
15350
+.LASF141:
15351
+ .string "fit_uname_fdt"
15352
+.LASF190:
15353
+ .string "UCLASS_LED"
15354
+.LASF293:
15355
+ .string "new_fdt"
15356
+.LASF408:
15357
+ .string "ioctl"
15358
+.LASF434:
15359
+ .string "rk3562_secure_otp_write_byte_noecc"
15360
+.LASF170:
15361
+ .string "UCLASS_AHCI"
15362
+.LASF41:
15363
+ .string "sibling_node"
15364
+.LASF334:
15365
+ .string "net_root_path"
15366
+.LASF49:
15367
+ .string "block_drvr"
15368
+.LASF9:
15369
+ .string "long long int"
15370
+.LASF251:
15371
+ .string "UCLASS_EBC"
15372
+.LASF325:
15373
+ .string "save_addr"
15374
+.LASF35:
15375
+ .string "priv"
15376
+.LASF209:
15377
+ .string "UCLASS_PMIC"
15378
+.LASF303:
15379
+ .string "malloc_limit"
15380
+.LASF14:
15381
+ .string "char"
15382
+.LASF414:
15383
+ .string "secure_otp_data"
15384
+.LASF180:
15385
+ .string "UCLASS_GPIO"
15386
+.LASF44:
15387
+ .string "ide_bus_offset"
15388
+.LASF255:
15389
+ .string "UCLASS_PD"
15390
+.LASF52:
15391
+ .string "sector_count"
15392
+.LASF145:
15393
+ .string "fit_noffset_setup"
15394
+.LASF122:
15395
+ .string "image_start"
15396
+.LASF56:
15397
+ .string "flash_info_t"
15398
+.LASF228:
15399
+ .string "UCLASS_SYSRESET"
15400
+.LASF115:
15401
+ .string "ih_os"
15402
+.LASF31:
15403
+ .string "uclass_platdata"
15404
+.LASF337:
15405
+ .string "net_ip"
15406
+.LASF459:
15407
+ .ascii "GNU C11 6.3.1 201"
15408
+ .string "70404 -mstrict-align -march=armv8-a+nosimd -mlittle-endian -mabi=lp64 -g -Os -fno-builtin -ffreestanding -fshort-wchar -fno-stack-protector -fno-delete-null-pointer-checks -fstack-usage -ffunction-sections -fdata-sections -ffixed-r9 -fno-common -ffixed-x18"
15409
+.LASF306:
15410
+ .string "video_top"
15411
+.LASF258:
15412
+ .string "LOGF_MAX_CATEGORIES"
15413
+.LASF358:
15414
+ .string "net_state"
15415
+.LASF286:
15416
+ .string "start_addr_sp"
15417
+.LASF135:
15418
+ .string "fit_uname_os"
15419
+.LASF18:
15420
+ .string "uint8_t"
15421
+.LASF7:
15422
+ .string "__u32"
15423
+.LASF363:
15424
+ .string "unbind"
15425
+.LASF284:
15426
+ .string "mon_len"
15427
+.LASF357:
15428
+ .string "NETLOOP_FAIL"
15429
+.LASF418:
15430
+ .string "rk3562_data"
15431
+.LASF365:
15432
+ .string "child_post_bind"
15433
+.LASF314:
15434
+ .string "full_name"
15435
+.LASF214:
15436
+ .string "UCLASS_REGULATOR"
15437
+.LASF183:
15438
+ .string "UCLASS_I2C_EEPROM"
15439
+.LASF371:
15440
+ .string "per_child_platdata_auto_alloc_size"
15441
+.LASF445:
15442
+ .string "rockchip_secure_otp_wait_status"
15443
+.LASF129:
15444
+ .string "bootm_headers"
15445
+.LASF276:
15446
+ .string "mem_clk"
15447
+.LASF359:
15448
+ .string "of_match"
15449
+.LASF352:
15450
+ .string "uclass_id"
15451
+.LASF321:
15452
+ .string "monitor_flash_len"
15453
+.LASF367:
15454
+ .string "child_post_remove"
15455
+.LASF370:
15456
+ .string "per_child_auto_alloc_size"
15457
+.LASF213:
15458
+ .string "UCLASS_RAM"
15459
+.LASF451:
15460
+ .string "rk3562_spl_rockchip_otp_start"
15461
+.LASF364:
15462
+ .string "ofdata_to_platdata"
15463
+.LASF208:
15464
+ .string "UCLASS_PINCTRL"
15465
+.LASF29:
15466
+ .string "platdata"
15467
+.LASF260:
15468
+ .string "timer_rate_hz"
15469
+.LASF435:
15470
+ .string "data_2b"
15471
+.LASF90:
15472
+ .string "_datarelrolocal_start_ofs"
15473
+.LASF164:
15474
+ .string "UCLASS_SPI_EMUL"
15475
+.LASF196:
15476
+ .string "UCLASS_MOD_EXP"
15477
+.LASF97:
15478
+ .string "totalsize"
15479
+.LASF388:
15480
+ .string "uclass_driver"
15481
+.LASF73:
15482
+ .string "bi_arm_freq"
15483
+.LASF199:
15484
+ .string "UCLASS_NORTHBRIDGE"
15485
+.LASF236:
15486
+ .string "UCLASS_USB_GADGET_GENERIC"
15487
+.LASF120:
15488
+ .string "image_header_t"
15489
+.LASF68:
15490
+ .string "bi_flashstart"
15491
+.LASF92:
15492
+ .string "_datarelro_start_ofs"
15493
+.LASF13:
15494
+ .string "sizetype"
15495
+.LASF386:
15496
+ .string "compatible"
15497
+.LASF165:
15498
+ .string "UCLASS_I2C_EMUL"
15499
+.LASF275:
15500
+ .string "pci_clk"
15501
+.LASF173:
15502
+ .string "UCLASS_CPU"
15503
+.LASF344:
15504
+ .string "net_null_ethaddr"
15505
+.LASF86:
15506
+ .string "bd_t"
15507
+.LASF174:
15508
+ .string "UCLASS_AMP"
15509
+.LASF244:
15510
+ .string "UCLASS_RC"
15511
+.LASF454:
15512
+ .string "dev_read_u32_default"
15513
+.LASF338:
15514
+ .string "net_server_ip"
15515
+.LASF281:
15516
+ .string "ram_top_ext_size"
15517
+.LASF51:
15518
+ .string "size"
15519
+.LASF58:
15520
+ .string "long double"
15521
+.LASF76:
15522
+ .string "bi_bootflags"
15523
+.LASF83:
15524
+ .string "bi_boot_params"
15525
+.LASF442:
15526
+ .string "rockchip_secure_otp_check_flag"
15527
+.LASF449:
15528
+ .string "mask"
15529
+.LASF247:
15530
+ .string "UCLASS_IO_DOMAIN"
15531
+.LASF25:
15532
+ .string "_binary_u_boot_bin_start"
15533
+.LASF159:
15534
+ .string "UCLASS_DEMO"
15535
+.LASF107:
15536
+ .string "image_header"
15537
+.LASF102:
15538
+ .string "last_comp_version"
15539
+.LASF322:
15540
+ .string "__dtb_dt_begin"
15541
+.LASF252:
15542
+ .string "UCLASS_EINK_DISPLAY"
15543
+.LASF310:
15544
+ .string "sys_start_tick"
15545
+.LASF168:
15546
+ .string "UCLASS_SIMPLE_BUS"
15547
+.LASF179:
15548
+ .string "UCLASS_ETH"
15549
+.LASF153:
15550
+ .string "cmdline_end"
15551
+.LASF75:
15552
+ .string "bi_ddr_freq"
15553
+.LASF98:
15554
+ .string "off_dt_struct"
15555
+.LASF441:
15556
+ .string "rockchip_secure_otp_ecc_enable"
15557
+.LASF232:
15558
+ .string "UCLASS_UFS"
15559
+.LASF309:
15560
+ .string "serial"
15561
+.LASF387:
15562
+ .string "data"
15563
+.LASF330:
15564
+ .string "net_netmask"
15565
+.LASF323:
15566
+ .string "__dtb_dt_spl_begin"
15567
+.LASF65:
15568
+ .string "bd_info"
15569
+.LASF152:
15570
+ .string "cmdline_start"
15571
+.LASF157:
15572
+ .string "images"
15573
+.LASF268:
15574
+ .string "using_pre_serial"
15575
+.LASF130:
15576
+ .string "legacy_hdr_os"
15577
+.LASF426:
15578
+ .string "otp_data"
15579
+.LASF192:
15580
+ .string "UCLASS_MAILBOX"
15581
+.LASF217:
15582
+ .string "UCLASS_RKNAND"
15583
+.LASF138:
15584
+ .string "fit_uname_rd"
15585
+.LASF437:
15586
+ .string "rk3562_secure_otp_read"
15587
+.LASF77:
15588
+ .string "bi_ip_addr"
15589
+.LASF308:
15590
+ .string "pm_ctx_phys"
15591
+.LASF296:
15592
+ .string "of_root_f"
15593
+.LASF282:
15594
+ .string "relocaddr"
15595
+.LASF33:
15596
+ .string "driver_data"
15597
+.LASF0:
15598
+ .string "unsigned char"
15599
+.LASF11:
15600
+ .string "phys_addr_t"
15601
+.LASF390:
15602
+ .string "pre_unbind"
15603
+.LASF432:
15604
+ .string "rk3562_secure_otp_write_2_bytes"
15605
+.LASF339:
15606
+ .string "net_tx_packet"
15607
+.LASF396:
15608
+ .string "per_device_auto_alloc_size"
15609
+.LASF150:
15610
+ .string "initrd_start"
15611
+.LASF34:
15612
+ .string "parent"
15613
+.LASF381:
15614
+ .string "current"
15615
+.LASF6:
15616
+ .string "short int"
15617
+.LASF302:
15618
+ .string "malloc_base"
15619
+.LASF116:
15620
+ .string "ih_arch"
15621
+.LASF401:
15622
+ .string "DECOM_GZIP"
15623
+.LASF315:
15624
+ .string "properties"
15625
+.LASF241:
15626
+ .string "UCLASS_WDT"
15627
+.LASF443:
15628
+ .string "delay"
15629
+.LASF373:
15630
+ .string "length"
15631
+.LASF332:
15632
+ .string "net_nis_domain"
15633
+.LASF112:
15634
+ .string "ih_load"
15635
+.LASF299:
15636
+ .string "env_buf"
15637
+.LASF356:
15638
+ .string "NETLOOP_SUCCESS"
15639
+.LASF167:
15640
+ .string "UCLASS_USB_EMUL"
15641
+.LASF430:
15642
+ .string "temp"
15643
+.LASF161:
15644
+ .string "UCLASS_TEST_FDT"
15645
+.LASF294:
15646
+ .string "fdt_size"
15647
+.LASF416:
15648
+ .string "spl_rockchip_otp_stop"
15649
+.LASF446:
15650
+ .string "flag"
15651
+.LASF17:
15652
+ .string "ulong"
15653
+.LASF110:
15654
+ .string "ih_time"
15655
+.LASF111:
15656
+ .string "ih_size"
15657
+.LASF178:
15658
+ .string "UCLASS_DMA"
15659
+.LASF254:
15660
+ .string "UCLASS_DMC"
15661
+.LASF215:
15662
+ .string "UCLASS_REMOTEPROC"
15663
+.LASF354:
15664
+ .string "NETLOOP_CONTINUE"
15665
+.LASF219:
15666
+ .string "UCLASS_RTC"
15667
+.LASF262:
15668
+ .string "timer_reset_value"
15669
+.LASF295:
15670
+ .string "of_root"
15671
+.LASF340:
15672
+ .string "net_rx_packets"
15673
+.LASF194:
15674
+ .string "UCLASS_MISC"
15675
+.LASF62:
15676
+ .string "region"
15677
+.LASF148:
15678
+ .string "ft_addr"
15679
+.LASF417:
15680
+ .string "rockchip_secure_otp_ops"
15681
+.LASF406:
15682
+ .string "read"
15683
+.LASF54:
15684
+ .string "start"
15685
+.LASF144:
15686
+ .string "fit_uname_setup"
15687
+.LASF114:
15688
+ .string "ih_dcrc"
15689
+.LASF24:
15690
+ .string "image_base"
15691
+.LASF393:
15692
+ .string "pre_remove"
15693
+.LASF158:
15694
+ .string "UCLASS_ROOT"
15695
+.LASF96:
15696
+ .string "magic"
15697
+.LASF242:
15698
+ .string "UCLASS_FG"
15699
+.LASF137:
15700
+ .string "fit_hdr_rd"
15701
+.LASF140:
15702
+ .string "fit_hdr_fdt"
15703
+.LASF113:
15704
+ .string "ih_ep"
15705
+.LASF287:
15706
+ .string "reloc_off"
15707
+.LASF394:
15708
+ .string "init"
15709
+.LASF240:
15710
+ .string "UCLASS_VIDEO_CRTC"
15711
+.LASF237:
15712
+ .string "UCLASS_VIDEO"
15713
+.LASF447:
15714
+ .string "secure_conf"
15715
+.LASF205:
15716
+ .string "UCLASS_PCI_GENERIC"
15717
+.LASF1:
15718
+ .string "long unsigned int"
15719
+.LASF5:
15720
+ .string "__u8"
15721
+.LASF375:
15722
+ .string "of_offset"
15723
+.LASF259:
15724
+ .string "arch_global_data"
15725
+.LASF89:
15726
+ .string "_datarel_start_ofs"
15727
+.LASF312:
15728
+ .string "device_node"
15729
+.LASF264:
15730
+ .string "tlb_size"
15731
+.LASF66:
15732
+ .string "bi_memstart"
15733
+.LASF109:
15734
+ .string "ih_hcrc"
15735
+.LASF104:
15736
+ .string "size_dt_strings"
15737
+.LASF128:
15738
+ .string "image_info_t"
15739
+.LASF63:
15740
+ .string "memory"
15741
+.LASF27:
15742
+ .string "driver"
15743
+.LASF147:
15744
+ .string "rd_end"
15745
+.LASF193:
15746
+ .string "UCLASS_MASS_STORAGE"
15747
+.LASF450:
15748
+ .string "rk3562_spl_rockchip_otp_stop"
15749
+.LASF151:
15750
+ .string "initrd_end"
15751
+.LASF210:
15752
+ .string "UCLASS_PWM"
15753
+.LASF93:
15754
+ .string "IRQ_STACK_START_IN"
15755
+.LASF84:
15756
+ .string "bi_andr_version"
15757
+.LASF126:
15758
+ .string "type"
15759
+.LASF342:
15760
+ .string "net_rx_packet_len"
15761
+.LASF384:
15762
+ .string "u_boot_dev_head"
15763
+.LASF427:
15764
+ .string "secure_otp_read"
15765
+.LASF221:
15766
+ .string "UCLASS_SCSI"
15767
+.LASF16:
15768
+ .string "ushort"
15769
+.LASF204:
15770
+ .string "UCLASS_PCI"
15771
+.LASF198:
15772
+ .string "UCLASS_NOP"
15773
+.LASF395:
15774
+ .string "destroy"
15775
+.LASF448:
15776
+ .string "otp_cru_rst"
15777
+.LASF248:
15778
+ .string "UCLASS_CRYPTO"
15779
+.LASF453:
15780
+ .string "dev_read_addr_ptr"
15781
+.LASF277:
15782
+ .string "have_console"
15783
+.LASF400:
15784
+ .string "DECOM_LZ4"
15785
+.LASF175:
15786
+ .string "UCLASS_CODEC"
15787
+.LASF382:
15788
+ .string "uc_drv"
15789
+.LASF233:
15790
+ .string "UCLASS_USB"
15791
+.LASF305:
15792
+ .string "cur_serial_dev"
15793
+.LASF271:
15794
+ .string "addr"
15795
+.LASF46:
15796
+ .string "list_head"
15797
+.LASF155:
15798
+ .string "state"
15799
+.LASF20:
15800
+ .string "__be32"
15801
+.LASF207:
15802
+ .string "UCLASS_PINCONFIG"
15803
+.LASF234:
15804
+ .string "UCLASS_USB_DEV_GENERIC"
15805
+.LASF343:
15806
+ .string "net_bcast_ethaddr"
15807
+.LASF136:
15808
+ .string "fit_noffset_os"
15809
+.LASF223:
15810
+ .string "UCLASS_SPI"
15811
+.LASF336:
15812
+ .string "net_server_ethaddr"
15813
+.LASF256:
15814
+ .string "UCLASS_COUNT"
15815
+.LASF279:
15816
+ .string "env_valid"
15817
+.LASF246:
15818
+ .string "UCLASS_DVFS"
15819
+.LASF413:
15820
+ .string "otp_cru_rst_base"
15821
+.LASF40:
15822
+ .string "child_head"
15823
+.LASF50:
15824
+ .string "select_hwpart"
15825
+.LASF4:
15826
+ .string "uchar"
15827
+.LASF69:
15828
+ .string "bi_flashsize"
15829
+.LASF383:
15830
+ .string "dev_head"
15831
+.LASF410:
15832
+ .string "rockchip_otp_platdata"
15833
+.LASF2:
15834
+ .string "short unsigned int"
15835
+.LASF392:
15836
+ .string "post_probe"
15837
+.LASF366:
15838
+ .string "child_pre_probe"
15839
+.LASF422:
15840
+ .string "secure_otp_ioctl"
15841
+.LASF348:
15842
+ .string "net_boot_file_name"
15843
+.LASF407:
15844
+ .string "write"
15845
+.LASF245:
15846
+ .string "UCLASS_CHARGE_DISPLAY"
15847
+.LASF257:
15848
+ .string "UCLASS_INVALID"
15849
+.LASF403:
15850
+ .string "OTP_S"
15851
+.LASF433:
15852
+ .string "__func__"
15853
+.LASF64:
15854
+ .string "reserved"
15855
+.LASF182:
15856
+ .string "UCLASS_I2C"
15857
+.LASF119:
15858
+ .string "ih_name"
15859
+.LASF462:
15860
+ .string "ofnode_union"
15861
+.LASF412:
15862
+ .string "otp_mask_base"
15863
+.LASF169:
15864
+ .string "UCLASS_ADC"
15865
+.LASF43:
15866
+ .string "req_seq"
15867
+.LASF283:
15868
+ .string "ram_size"
15869
+.LASF452:
15870
+ .string "dev_get_platdata"
15871
+.LASF186:
15872
+ .string "UCLASS_I2S"
15873
+.LASF368:
15874
+ .string "priv_auto_alloc_size"
15875
+.LASF30:
15876
+ .string "parent_platdata"
15877
+.LASF411:
15878
+ .string "secure_conf_base"
15879
+.LASF154:
15880
+ .string "verify"
15881
+.LASF88:
15882
+ .string "FIQ_STACK_START"
15883
+.LASF85:
15884
+ .string "bi_dram"
15885
+.LASF125:
15886
+ .string "comp"
15887
+.LASF346:
15888
+ .string "net_native_vlan"
15889
+.LASF424:
15890
+ .string "secure_otp_write"
15891
+.LASF211:
15892
+ .string "UCLASS_POWER_DOMAIN"
15893
+.LASF399:
15894
+ .string "misc_mode"
15895
+.LASF273:
15896
+ .string "cpu_clk"
15897
+.LASF238:
15898
+ .string "UCLASS_VIDEO_BRIDGE"
15899
+.LASF369:
15900
+ .string "platdata_auto_alloc_size"
15901
+.LASF61:
15902
+ .string "lmb_region"
15903
+.LASF243:
15904
+ .string "UCLASS_KEY"
15905
+ .ident "GCC: (Linaro GCC 6.3-2017.05) 6.3.1 20170404"
15906
+ .section .note.GNU-stack,"",@progbits
u-boot/drivers/misc/rockchip-otp.c
....@@ -246,7 +246,7 @@
246246 if (!buffer)
247247 return -ENOMEM;
248248
249
- ret = rockchip_otp_ecc_enable(otp, false);
249
+ ret = rockchip_otp_ecc_enable(otp, true);
250250 if (ret < 0) {
251251 printf("%s rockchip_otp_ecc_enable err\n", __func__);
252252 return ret;
....@@ -460,6 +460,14 @@
460460 .data = (ulong)&rk3308bs_data,
461461 },
462462 {
463
+ .compatible = "rockchip,rk3528-otp",
464
+ .data = (ulong)&rk3568_data,
465
+ },
466
+ {
467
+ .compatible = "rockchip,rk3562-otp",
468
+ .data = (ulong)&rk3568_data,
469
+ },
470
+ {
463471 .compatible = "rockchip,rk3568-otp",
464472 .data = (ulong)&rk3568_data,
465473 },
u-boot/drivers/mmc/dw_mmc.c
....@@ -8,6 +8,7 @@
88
99 #include <common.h>
1010 #include <bouncebuf.h>
11
+#include <div64.h>
1112 #include <errno.h>
1213 #include <malloc.h>
1314 #include <memalign.h>
....@@ -19,6 +20,7 @@
1920 #endif
2021
2122 #define PAGE_SIZE 4096
23
+#define MSEC_PER_SEC 1000ULL
2224
2325 /*
2426 * Currently it supports read/write up to 8*8*4 Bytes per
....@@ -159,18 +161,62 @@
159161 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
160162 }
161163
162
-static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size)
164
+#ifdef CONFIG_SPL_BUILD
165
+static unsigned int dwmci_get_drto(struct dwmci_host *host,
166
+ const unsigned int size)
167
+{
168
+ unsigned int drto_clks;
169
+ unsigned int drto_div;
170
+ unsigned int drto_ms;
171
+
172
+ drto_clks = dwmci_readl(host, DWMCI_TMOUT) >> 8;
173
+ drto_div = (dwmci_readl(host, DWMCI_CLKDIV) & 0xff) * 2;
174
+ if (drto_div == 0)
175
+ drto_div = 1;
176
+
177
+ drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div,
178
+ host->mmc->clock);
179
+
180
+ /* add a bit spare time */
181
+ drto_ms += 10;
182
+
183
+ return drto_ms;
184
+}
185
+#else
186
+static unsigned int dwmci_get_drto(struct dwmci_host *host,
187
+ const unsigned int size)
163188 {
164189 unsigned int timeout;
165190
166191 timeout = size * 8; /* counting in bits */
167192 timeout *= 10; /* wait 10 times as long */
168
- timeout /= mmc->clock;
169
- timeout /= mmc->bus_width;
193
+ timeout /= host->mmc->clock;
194
+ timeout /= host->mmc->bus_width;
170195 timeout *= 1000; /* counting in msec */
171196 timeout = (timeout < 10000) ? 10000 : timeout;
172197
173198 return timeout;
199
+}
200
+#endif
201
+
202
+static unsigned int dwmci_get_cto(struct dwmci_host *host)
203
+{
204
+ unsigned int cto_clks;
205
+ unsigned int cto_div;
206
+ unsigned int cto_ms;
207
+
208
+ cto_clks = dwmci_readl(host, DWMCI_TMOUT) & 0xff;
209
+ cto_div = (dwmci_readl(host, DWMCI_CLKDIV) & 0xff) * 2;
210
+ if (cto_div == 0)
211
+ cto_div = 1;
212
+
213
+ cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div,
214
+ host->mmc->clock);
215
+
216
+ /* add a bit spare time */
217
+ cto_ms += 10;
218
+
219
+ return cto_ms;
174220 }
175221
176222 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
....@@ -192,7 +238,7 @@
192238 else
193239 buf = (unsigned int *)data->src;
194240
195
- timeout = dwmci_get_timeout(host->mmc, size);
241
+ timeout = dwmci_get_drto(host, size);
196242 size /= 4;
197243
198244 for (;;) {
....@@ -252,6 +298,7 @@
252298 }
253299 dwmci_writel(host, DWMCI_RINTSTS,
254300 DWMCI_INTMSK_RXDR);
301
+ start = get_timer(0);
255302 } else if (data->flags == MMC_DATA_WRITE &&
256303 (mask & DWMCI_INTMSK_TXDR)) {
257304 while (size) {
....@@ -281,6 +328,7 @@
281328 }
282329 dwmci_writel(host, DWMCI_RINTSTS,
283330 DWMCI_INTMSK_TXDR);
331
+ start = get_timer(0);
284332 }
285333 }
286334
....@@ -329,9 +377,8 @@
329377 struct dwmci_host *host = mmc->priv;
330378 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
331379 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
332
- int ret = 0, flags = 0, i;
380
+ int ret = 0, flags = 0;
333381 unsigned int timeout = 500;
334
- u32 retry = 100000;
335382 u32 mask, ctrl;
336383 ulong start = get_timer(0);
337384 struct bounce_buffer bbstate;
....@@ -400,16 +447,18 @@
400447
401448 dwmci_writel(host, DWMCI_CMD, flags);
402449
403
- for (i = 0; i < retry; i++) {
450
+ timeout = dwmci_get_cto(host);
451
+ start = get_timer(0);
452
+ do {
404453 mask = dwmci_readl(host, DWMCI_RINTSTS);
405454 if (mask & DWMCI_INTMSK_CDONE) {
406455 if (!data)
407456 dwmci_writel(host, DWMCI_RINTSTS, mask);
408457 break;
409458 }
410
- }
459
+ } while (!(get_timer(start) > timeout));
411460
412
- if (i == retry) {
461
+ if (get_timer(start) > timeout) {
413462 debug("%s: Timeout.\n", __func__);
414463 return -ETIMEDOUT;
415464 }
....@@ -470,9 +519,8 @@
470519 #endif
471520 struct dwmci_host *host = mmc->priv;
472521 struct dwmci_idmac *cur_idmac;
473
- int ret = 0, flags = 0, i;
522
+ int ret = 0, flags = 0;
474523 unsigned int timeout = 500;
475
- u32 retry = 100000;
476524 u32 mask;
477525 ulong start = get_timer(0);
478526 struct bounce_buffer bbstate;
....@@ -541,16 +589,18 @@
541589
542590 dwmci_writel(host, DWMCI_CMD, flags);
543591
544
- for (i = 0; i < retry; i++) {
592
+ timeout = dwmci_get_cto(host);
593
+ start = get_timer(0);
594
+ do {
545595 mask = dwmci_readl(host, DWMCI_RINTSTS);
546596 if (mask & DWMCI_INTMSK_CDONE) {
547597 if (!data)
548598 dwmci_writel(host, DWMCI_RINTSTS, mask);
549599 break;
550600 }
551
- }
601
+ } while (!(get_timer(start) > timeout));
552602
553
- if (i == retry) {
603
+ if (get_timer(start) > timeout) {
554604 debug("%s: Timeout.\n", __func__);
555605 return -ETIMEDOUT;
556606 }
u-boot/drivers/mmc/mmc-uclass.c
....@@ -143,6 +143,20 @@
143143 return dm_mmc_get_cd(mmc->dev);
144144 }
145145
146
+static int dm_mmc_set_enhanced_strobe(struct udevice *dev)
147
+{
148
+ struct dm_mmc_ops *ops = mmc_get_ops(dev);
149
+
150
+ if (ops->set_enhanced_strobe)
151
+ return ops->set_enhanced_strobe(dev);
152
+
153
+ return -ENOTSUPP;
154
+}
155
+
156
+int mmc_set_enhanced_strobe(struct mmc *mmc)
157
+{
158
+ return dm_mmc_set_enhanced_strobe(mmc->dev);
159
+}
146160 struct mmc *mmc_get_mmc_dev(struct udevice *dev)
147161 {
148162 struct mmc_uclass_priv *upriv;
u-boot/drivers/mmc/mmc.c
....@@ -1007,12 +1007,22 @@
10071007 return ret;
10081008 }
10091009
1010
+static int mmc_switch_to_hs400(struct mmc *mmc)
1011
+{
1012
+ u8 val, fixed_drv_type, card_drv_type, drive_strength;
1013
+
1014
+ fixed_drv_type = mmc->cfg->fixed_drv_type;
1015
+ card_drv_type = mmc->raw_driver_strength | mmc_driver_type_mask(0);
1016
+ drive_strength = (card_drv_type & mmc_driver_type_mask(fixed_drv_type))
1017
+ ? fixed_drv_type : 0;
1018
+ val = EXT_CSD_TIMING_HS400 | drive_strength << EXT_CSD_DRV_STR_SHIFT;
1019
+
1020
+ return __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, val, false);
1021
+}
1022
+
10101023 static int mmc_select_hs400(struct mmc *mmc)
10111024 {
10121025 int ret;
1013
-
1014
- /* Reduce frequency to HS frequency */
1015
- mmc_set_clock(mmc, MMC_HIGH_52_MAX_DTR);
10161026
10171027 /* Switch card to HS mode */
10181028 ret = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
....@@ -1022,6 +1032,9 @@
10221032
10231033 /* Set host controller to HS timing */
10241034 mmc_set_timing(mmc, MMC_TIMING_MMC_HS);
1035
+
1036
+ /* Reduce frequency to HS frequency */
1037
+ mmc_set_clock(mmc, MMC_HIGH_52_MAX_DTR);
10251038
10261039 ret = mmc_send_status(mmc, 1000);
10271040 if (ret)
....@@ -1035,8 +1048,7 @@
10351048 return ret;
10361049
10371050 /* Switch card to HS400 */
1038
- ret = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1039
- EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS400, false);
1051
+ ret = mmc_switch_to_hs400(mmc);
10401052 if (ret)
10411053 return ret;
10421054
....@@ -1045,9 +1057,48 @@
10451057
10461058 return ret;
10471059 }
1060
+
1061
+static int mmc_select_hs400es(struct mmc *mmc)
1062
+{
1063
+ int err;
1064
+
1065
+ /* Switch card to HS mode */
1066
+ err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1067
+ EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS, false);
1068
+ if (err)
1069
+ return err;
1070
+
1071
+ /* Set host controller to HS timing */
1072
+ mmc_set_timing(mmc, MMC_TIMING_MMC_HS);
1073
+
1074
+ err = mmc_send_status(mmc, 1000);
1075
+ if (err)
1076
+ return err;
1077
+
1078
+ mmc_set_clock(mmc, MMC_HIGH_52_MAX_DTR);
1079
+
1080
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1081
+ EXT_CSD_DDR_BUS_WIDTH_8 |
1082
+ EXT_CSD_BUS_WIDTH_STROBE);
1083
+ if (err) {
1084
+ printf("switch to bus width for hs400 failed\n");
1085
+ return err;
1086
+ }
1087
+
1088
+ /* Switch card to HS400 */
1089
+ err = mmc_switch_to_hs400(mmc);
1090
+ if (err)
1091
+ return err;
1092
+
1093
+ /* Set host controller to HS400 timing and frequency */
1094
+ mmc_set_timing(mmc, MMC_TIMING_MMC_HS400ES);
1095
+
1096
+ return mmc_set_enhanced_strobe(mmc);
1097
+}
10481098 #else
10491099 static int mmc_select_hs200(struct mmc *mmc) { return 0; }
10501100 static int mmc_select_hs400(struct mmc *mmc) { return 0; }
1101
+static int mmc_select_hs400es(struct mmc *mmc) { return 0; }
10511102 #endif
10521103
10531104 static u32 mmc_select_card_type(struct mmc *mmc, u8 *ext_csd)
....@@ -1139,6 +1190,16 @@
11391190 return err;
11401191
11411192 avail_type = mmc_select_card_type(mmc, ext_csd);
1193
+
1194
+ if (avail_type & EXT_CSD_CARD_TYPE_HS400ES) {
1195
+ err = mmc_select_bus_width(mmc);
1196
+ if (err > 0 && mmc->bus_width == MMC_BUS_WIDTH_8BIT) {
1197
+ err = mmc_select_hs400es(mmc);
1198
+ mmc_set_bus_speed(mmc, avail_type);
1199
+ if (!err)
1200
+ return err;
1201
+ }
1202
+ }
11421203
11431204 if (avail_type & EXT_CSD_CARD_TYPE_HS200)
11441205 err = mmc_select_hs200(mmc);
....@@ -1824,6 +1885,10 @@
18241885 mmc->erase_grp_size = 1;
18251886 mmc->part_config = MMCPART_NOAVAILABLE;
18261887 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1888
+ /* select high speed to reduce initialization time */
1889
+ mmc_select_hs(mmc);
1890
+ mmc_set_clock(mmc, MMC_HIGH_52_MAX_DTR);
1891
+
18271892 /* check ext_csd version and capacity */
18281893 err = mmc_send_ext_csd(mmc, ext_csd);
18291894 if (err)
....@@ -1973,6 +2038,8 @@
19732038 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
19742039
19752040 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2041
+
2042
+ mmc->raw_driver_strength = ext_csd[EXT_CSD_DRIVER_STRENGTH];
19762043 }
19772044
19782045 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
u-boot/drivers/mmc/rockchip_dw_mmc.c
....@@ -42,7 +42,7 @@
4242 {
4343 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
4444
45
- if (!priv || !&priv->clk)
45
+ if (!priv)
4646 return 0;
4747
4848 if (!memcmp(dev->name, "dwmmc", strlen("dwmmc")))
u-boot/drivers/mmc/rockchip_sdhci.c
....@@ -39,6 +39,12 @@
3939 ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
4040 PHYCTRL_DLLRDY_DONE)
4141
42
+#define ARASAN_VENDOR_REGISTER 0x78
43
+#define ARASAN_VENDOR_ENHANCED_STROBE BIT(0)
44
+
45
+/* DWC IP vendor area 1 pointer */
46
+#define DWCMSHC_P_VENDOR_AREA1 0xe8
47
+#define DWCMSHC_AREA1_MASK GENMASK(11, 0)
4248 /* Rockchip specific Registers */
4349 #define DWCMSHC_CTRL_HS400 0x7
4450 #define DWCMSHC_CARD_IS_EMMC BIT(0)
....@@ -46,6 +52,7 @@
4652
4753 #define DWCMSHC_HOST_CTRL3 0x508
4854 #define DWCMSHC_EMMC_CONTROL 0x52c
55
+#define DWCMSHC_EMMC_ATCTRL 0x540
4956 #define DWCMSHC_EMMC_DLL_CTRL 0x800
5057 #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
5158 #define DWCMSHC_EMMC_DLL_RXCLK 0x804
....@@ -55,25 +62,31 @@
5562 #define DWCMSHC_EMMC_DLL_STATUS0 0x840
5663 #define DWCMSHC_EMMC_DLL_STATUS1 0x844
5764 #define DWCMSHC_EMMC_DLL_START BIT(0)
58
-#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
5965 #define DWCMSHC_EMMC_DLL_START_POINT 16
6066 #define DWCMSHC_EMMC_DLL_START_DEFAULT 5
6167 #define DWCMSHC_EMMC_DLL_INC_VALUE 2
6268 #define DWCMSHC_EMMC_DLL_INC 8
69
+#define DWCMSHC_EMMC_DLL_BYPASS BIT(24)
6370 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
6471 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10
65
-#define DLL_TXCLK_TAPNUM_90_DEGREES 0x8
66
-#define DLL_STRBIN_TAPNUM_DEFAULT 0x3
72
+#define DLL_TXCLK_TAPNUM_90_DEGREES 0x9
73
+#define DLL_STRBIN_TAPNUM_DEFAULT 0x4
74
+#define DLL_STRBIN_DELAY_NUM_OFFSET 16
75
+#define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
76
+#define DLL_STRBIN_DELAY_NUM_SEL BIT(26)
6777 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
6878 #define DLL_TXCLK_NO_INVERTER BIT(29)
6979 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
7080 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
71
-#define DLL_RXCLK_NO_INVERTER 1
72
-#define DLL_RXCLK_INVERTER 0
81
+#define DLL_TAP_VALUE_SEL BIT(25)
82
+#define DLL_TAP_VALUE_OFFSET 8
83
+#define DLL_RXCLK_NO_INVERTER BIT(29)
84
+#define DLL_RXCLK_ORI_GATE BIT(31)
7385 #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
7486 #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
7587 #define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
7688 #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
89
+#define DLL_CMDOUT_BOTH_CLK_EDGE BIT(30)
7790
7891 #define DWCMSHC_ENHANCED_STROBE BIT(8)
7992 #define DLL_LOCK_WO_TMOUT(x) \
....@@ -106,10 +119,18 @@
106119 struct sdhci_data {
107120 int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock);
108121 void (*set_ios_post)(struct sdhci_host *host);
122
+ int (*set_enhanced_strobe)(struct sdhci_host *host);
109123 int (*get_phy)(struct udevice *dev);
110124 u32 flags;
111125 #define RK_DLL_CMD_OUT BIT(1)
112126 #define RK_RXCLK_NO_INVERTER BIT(2)
127
+#define RK_TAP_VALUE_SEL BIT(3)
128
+
129
+ u8 hs200_tx_tap;
130
+ u8 hs400_tx_tap;
131
+ u8 hs400_cmd_tap;
132
+ u8 hs400_strbin_tap;
133
+ u8 ddr50_strbin_delay_num;
113134 };
114135
115136 static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
....@@ -254,21 +275,7 @@
254275 clk |= SDHCI_CLOCK_INT_EN;
255276 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
256277
257
- /* Wait max 20 ms */
258
- timeout = 20;
259
- while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
260
- & SDHCI_CLOCK_INT_STABLE)) {
261
- if (timeout == 0) {
262
- printf("%s: Internal clock never stabilised.\n",
263
- __func__);
264
- return -EBUSY;
265
- }
266
- timeout--;
267
- udelay(1000);
268
- }
269
- clk |= SDHCI_CLOCK_CARD_EN;
270
- sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
271
- host->clock = clock;
278
+ sdhci_enable_clk(host, clk);
272279
273280 return 0;
274281 }
....@@ -323,16 +330,24 @@
323330 {
324331 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
325332 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
326
- u32 extra;
333
+ u32 txclk_tapnum, extra, dll_lock_value;
327334 int timeout = 500, ret;
328335
329336 ret = rockchip_emmc_set_clock(host, clock);
337
+
338
+ /* Disable output clock while config DLL */
339
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
330340
331341 if (clock >= 100 * MHz) {
332342 /* reset DLL */
333343 sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL);
334344 udelay(1);
335345 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
346
+
347
+ extra = 0x1 << 16 | /* tune clock stop en */
348
+ 0x2 << 17 | /* pre-change delay */
349
+ 0x3 << 19; /* post-change delay */
350
+ sdhci_writel(host, extra, DWCMSHC_EMMC_ATCTRL);
336351
337352 /* Init DLL settings */
338353 extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
....@@ -341,48 +356,106 @@
341356 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
342357
343358 while (1) {
344
- if (timeout < 0)
345
- return -ETIMEDOUT;
359
+ if (timeout < 0) {
360
+ ret = -ETIMEDOUT;
361
+ goto exit;
362
+ }
346363 if (DLL_LOCK_WO_TMOUT((sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0))))
347364 break;
348365 udelay(1);
349366 timeout--;
350367 }
351
- extra = DWCMSHC_EMMC_DLL_DLYENA;
368
+ dll_lock_value = ((sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0) & 0xFF) * 2 ) & 0xFF;
369
+ extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE;
352370 if (data->flags & RK_RXCLK_NO_INVERTER)
353
- extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
371
+ extra |= DLL_RXCLK_NO_INVERTER;
372
+ if (data->flags & RK_TAP_VALUE_SEL)
373
+ extra |= DLL_TAP_VALUE_SEL | (dll_lock_value << DLL_TAP_VALUE_OFFSET);
354374 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
375
+
376
+ txclk_tapnum = data->hs200_tx_tap;
377
+ if ((data->flags & RK_DLL_CMD_OUT) &&
378
+ (host->mmc->timing == MMC_TIMING_MMC_HS400 ||
379
+ host->mmc->timing == MMC_TIMING_MMC_HS400ES)) {
380
+ txclk_tapnum = data->hs400_tx_tap;
381
+
382
+ extra = DLL_CMDOUT_SRC_CLK_NEG |
383
+ DLL_CMDOUT_BOTH_CLK_EDGE |
384
+ DWCMSHC_EMMC_DLL_DLYENA |
385
+ data->hs400_cmd_tap |
386
+ DLL_CMDOUT_TAPNUM_FROM_SW;
387
+ if (data->flags & RK_TAP_VALUE_SEL)
388
+ extra |= DLL_TAP_VALUE_SEL | (dll_lock_value << DLL_TAP_VALUE_OFFSET);
389
+ sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
390
+ }
355391
356392 extra = DWCMSHC_EMMC_DLL_DLYENA |
357393 DLL_TXCLK_TAPNUM_FROM_SW |
358394 DLL_TXCLK_NO_INVERTER|
359
- DLL_TXCLK_TAPNUM_DEFAULT;
360
-
395
+ txclk_tapnum;
396
+ if (data->flags & RK_TAP_VALUE_SEL)
397
+ extra |= DLL_TAP_VALUE_SEL | (dll_lock_value << DLL_TAP_VALUE_OFFSET);
361398 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
362399
363400 extra = DWCMSHC_EMMC_DLL_DLYENA |
364
- DLL_STRBIN_TAPNUM_DEFAULT;
401
+ data->hs400_strbin_tap |
402
+ DLL_STRBIN_TAPNUM_FROM_SW;
403
+ if (data->flags & RK_TAP_VALUE_SEL)
404
+ extra |= DLL_TAP_VALUE_SEL | (dll_lock_value << DLL_TAP_VALUE_OFFSET);
365405 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
366406 } else {
407
+ /* disable dll */
408
+ sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
409
+
367410 /* Disable cmd conflict check */
368411 extra = sdhci_readl(host, DWCMSHC_HOST_CTRL3);
369412 extra &= ~BIT(0);
370413 sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3);
371414
372415 /* reset the clock phase when the frequency is lower than 100MHz */
373
- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
374
- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK);
416
+ sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
417
+ sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
375418 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
376
- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
377419 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
420
+ /*
421
+ * Before switching to hs400es mode, the driver will enable
422
+ * enhanced strobe first. PHY needs to configure the parameters
423
+ * of enhanced strobe first.
424
+ */
425
+ extra = DWCMSHC_EMMC_DLL_DLYENA |
426
+ DLL_STRBIN_DELAY_NUM_SEL |
427
+ data->ddr50_strbin_delay_num << DLL_STRBIN_DELAY_NUM_OFFSET;
428
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
378429 }
430
+
431
+exit:
432
+ /* enable output clock */
433
+ sdhci_enable_clk(host, 0);
434
+
379435 return ret;
436
+}
437
+
438
+static int dwcmshc_sdhci_set_enhanced_strobe(struct sdhci_host *host)
439
+{
440
+ struct mmc *mmc = host->mmc;
441
+ u32 vendor;
442
+
443
+ vendor = sdhci_readl(host, DWCMSHC_EMMC_CONTROL);
444
+ if (mmc->timing == MMC_TIMING_MMC_HS400ES)
445
+ vendor |= DWCMSHC_ENHANCED_STROBE;
446
+ else
447
+ vendor &= ~DWCMSHC_ENHANCED_STROBE;
448
+ sdhci_writel(host, vendor, DWCMSHC_EMMC_CONTROL);
449
+
450
+ /* some emmc device need a delay before send command */
451
+ udelay(100);
452
+
453
+ return 0;
380454 }
381455
382456 static void dwcmshc_sdhci_set_ios_post(struct sdhci_host *host)
383457 {
384458 u16 ctrl;
385
- u32 extra;
386459 u32 timing = host->mmc->timing;
387460
388461 if (timing == MMC_TIMING_MMC_HS400 || timing == MMC_TIMING_MMC_HS400ES) {
....@@ -395,16 +468,6 @@
395468 ctrl = sdhci_readw(host, DWCMSHC_EMMC_CONTROL);
396469 ctrl |= DWCMSHC_CARD_IS_EMMC;
397470 sdhci_writew(host, ctrl, DWCMSHC_EMMC_CONTROL);
398
-
399
- extra = DLL_CMDOUT_SRC_CLK_NEG |
400
- DLL_CMDOUT_EN_SRC_CLK_NEG;
401
- sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
402
-
403
- extra = DWCMSHC_EMMC_DLL_DLYENA |
404
- DLL_TXCLK_TAPNUM_FROM_SW |
405
- DLL_TXCLK_NO_INVERTER|
406
- DLL_TXCLK_TAPNUM_90_DEGREES;
407
- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
408471 }
409472 }
410473
....@@ -434,9 +497,21 @@
434497 data->set_ios_post(host);
435498 }
436499
500
+static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host)
501
+{
502
+ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
503
+ struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
504
+
505
+ if (data->set_enhanced_strobe)
506
+ return data->set_enhanced_strobe(host);
507
+
508
+ return -ENOTSUPP;
509
+}
510
+
437511 static struct sdhci_ops rockchip_sdhci_ops = {
438512 .set_clock = rockchip_sdhci_set_clock,
439513 .set_ios_post = rockchip_sdhci_set_ios_post,
514
+ .set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe,
440515 };
441516
442517 static int rockchip_sdhci_probe(struct udevice *dev)
....@@ -496,7 +571,13 @@
496571 host->host_caps |= MMC_MODE_HS200;
497572 else if (dev_read_bool(dev, "mmc-hs400-1_8v"))
498573 host->host_caps |= MMC_MODE_HS400;
574
+
575
+ if (data->set_enhanced_strobe && dev_read_bool(dev, "mmc-hs400-enhanced-strobe"))
576
+ host->host_caps |= MMC_MODE_HS400ES;
577
+
499578 ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
579
+
580
+ plat->cfg.fixed_drv_type = dev_read_u32_default(dev, "fixed-emmc-driver-type", 0);
500581
501582 host->mmc = &plat->mmc;
502583 if (ret)
....@@ -536,13 +617,50 @@
536617 .emmc_set_clock = dwcmshc_sdhci_emmc_set_clock,
537618 .get_phy = dwcmshc_emmc_get_phy,
538619 .flags = RK_RXCLK_NO_INVERTER,
620
+ .hs200_tx_tap = 16,
621
+ .hs400_tx_tap = 8,
622
+ .hs400_cmd_tap = 8,
623
+ .hs400_strbin_tap = 3,
624
+ .ddr50_strbin_delay_num = 16,
539625 };
540626
541627 static const struct sdhci_data rk3588_data = {
542628 .emmc_set_clock = dwcmshc_sdhci_emmc_set_clock,
543629 .get_phy = dwcmshc_emmc_get_phy,
544630 .set_ios_post = dwcmshc_sdhci_set_ios_post,
545
- .flags = RK_DLL_CMD_OUT | RK_RXCLK_NO_INVERTER,
631
+ .set_enhanced_strobe = dwcmshc_sdhci_set_enhanced_strobe,
632
+ .flags = RK_DLL_CMD_OUT,
633
+ .hs200_tx_tap = 16,
634
+ .hs400_tx_tap = 9,
635
+ .hs400_cmd_tap = 8,
636
+ .hs400_strbin_tap = 3,
637
+ .ddr50_strbin_delay_num = 16,
638
+};
639
+
640
+static const struct sdhci_data rk3528_data = {
641
+ .emmc_set_clock = dwcmshc_sdhci_emmc_set_clock,
642
+ .get_phy = dwcmshc_emmc_get_phy,
643
+ .set_ios_post = dwcmshc_sdhci_set_ios_post,
644
+ .set_enhanced_strobe = dwcmshc_sdhci_set_enhanced_strobe,
645
+ .flags = RK_DLL_CMD_OUT | RK_TAP_VALUE_SEL,
646
+ .hs200_tx_tap = 12,
647
+ .hs400_tx_tap = 6,
648
+ .hs400_cmd_tap = 6,
649
+ .hs400_strbin_tap = 3,
650
+ .ddr50_strbin_delay_num = 10,
651
+};
652
+
653
+static const struct sdhci_data rk3562_data = {
654
+ .emmc_set_clock = dwcmshc_sdhci_emmc_set_clock,
655
+ .get_phy = dwcmshc_emmc_get_phy,
656
+ .set_ios_post = dwcmshc_sdhci_set_ios_post,
657
+ .set_enhanced_strobe = dwcmshc_sdhci_set_enhanced_strobe,
658
+ .flags = RK_DLL_CMD_OUT | RK_TAP_VALUE_SEL,
659
+ .hs200_tx_tap = 12,
660
+ .hs400_tx_tap = 6,
661
+ .hs400_cmd_tap = 6,
662
+ .hs400_strbin_tap = 3,
663
+ .ddr50_strbin_delay_num = 10,
546664 };
547665
548666 static const struct udevice_id sdhci_ids[] = {
....@@ -555,6 +673,14 @@
555673 .data = (ulong)&rk3568_data,
556674 },
557675 {
676
+ .compatible = "rockchip,rk3528-dwcmshc",
677
+ .data = (ulong)&rk3528_data,
678
+ },
679
+ {
680
+ .compatible = "rockchip,rk3562-dwcmshc",
681
+ .data = (ulong)&rk3562_data,
682
+ },
683
+ {
558684 .compatible = "rockchip,rk3588-dwcmshc",
559685 .data = (ulong)&rk3588_data,
560686 },
u-boot/drivers/mmc/sdhci.c
....@@ -178,6 +178,7 @@
178178 } else {
179179 puts("timeout.\n");
180180 /* remove timeout return error and try to send command */
181
+ break;
181182 }
182183 }
183184 time++;
....@@ -313,6 +314,29 @@
313314 return -ECOMM;
314315 }
315316
317
+void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
318
+{
319
+ unsigned int timeout;
320
+
321
+ clk |= SDHCI_CLOCK_INT_EN;
322
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
323
+
324
+ /* Wait max 20 ms */
325
+ timeout = 20;
326
+ while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
327
+ & SDHCI_CLOCK_INT_STABLE)) {
328
+ if (timeout == 0) {
329
+ printf("%s: Internal clock never stabilised.\n",
330
+ __func__);
331
+ return;
332
+ }
333
+ timeout--;
334
+ udelay(1000);
335
+ }
336
+ clk |= SDHCI_CLOCK_CARD_EN;
337
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
338
+}
339
+
316340 int sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
317341 {
318342 unsigned int div, clk = 0, timeout;
....@@ -379,23 +403,8 @@
379403 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
380404 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
381405 << SDHCI_DIVIDER_HI_SHIFT;
382
- clk |= SDHCI_CLOCK_INT_EN;
383
- sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
384406
385
- /* Wait max 20 ms */
386
- timeout = 20;
387
- while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
388
- & SDHCI_CLOCK_INT_STABLE)) {
389
- if (timeout == 0) {
390
- printf("%s: Internal clock never stabilised.\n",
391
- __func__);
392
- return -EBUSY;
393
- }
394
- timeout--;
395
- udelay(1000);
396
- }
397
- clk |= SDHCI_CLOCK_CARD_EN;
398
- sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
407
+ sdhci_enable_clk(host, clk);
399408
400409 host->clock = clock;
401410 return 0;
....@@ -681,11 +690,23 @@
681690 return sdhci_init(mmc);
682691 }
683692
693
+static int sdhci_set_enhanced_strobe(struct udevice *dev)
694
+{
695
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
696
+ struct sdhci_host *host = mmc->priv;
697
+
698
+ if (host->ops && host->ops->set_enhanced_strobe)
699
+ return host->ops->set_enhanced_strobe(host);
700
+
701
+ return -ENOTSUPP;
702
+}
703
+
684704 const struct dm_mmc_ops sdhci_ops = {
685705 .card_busy = sdhci_card_busy,
686706 .send_cmd = sdhci_send_command,
687707 .set_ios = sdhci_set_ios,
688708 .execute_tuning = sdhci_execute_tuning,
709
+ .set_enhanced_strobe = sdhci_set_enhanced_strobe,
689710 };
690711 #else
691712 static const struct mmc_ops sdhci_ops = {
u-boot/drivers/mtd/mtd_blk.c
....@@ -22,9 +22,6 @@
2222 #endif
2323
2424 #define MTD_PART_NAND_HEAD "mtdparts="
25
-#define MTD_ROOT_PART_NUM "ubi.mtd="
26
-#define MTD_ROOT_PART_NAME_UBIFS "root=ubi0:rootfs"
27
-#define MTD_ROOT_PART_NAME_SQUASHFS "root=/dev/ubiblock0_0"
2825 #define MTD_PART_INFO_MAX_SIZE 512
2926 #define MTD_SINGLE_PART_INFO_MAX_SIZE 40
3027
....@@ -371,20 +368,7 @@
371368 mtd = (struct mtd_info *)dev_desc->bdev->priv;
372369 if (!mtd)
373370 return NULL;
374
-#ifndef CONFIG_SPL_BUILD
375
- char mtd_root_part_info[40] = {0};
376371
377
- p = part_get_info_by_name(dev_desc, PART_SYSTEM, &info);
378
- if (p > 0) {
379
- if (strstr(env_get("bootargs"), "rootfstype=squashfs"))
380
- snprintf(mtd_root_part_info, ARRAY_SIZE(mtd_root_part_info), "%s%d %s",
381
- MTD_ROOT_PART_NUM, p - 1, MTD_ROOT_PART_NAME_SQUASHFS);
382
- else
383
- snprintf(mtd_root_part_info, ARRAY_SIZE(mtd_root_part_info), "%s%d %s",
384
- MTD_ROOT_PART_NUM, p - 1, MTD_ROOT_PART_NAME_UBIFS);
385
- env_update("bootargs", mtd_root_part_info);
386
- }
387
-#endif
388372 mtd_part_info = (char *)calloc(MTD_PART_INFO_MAX_SIZE, sizeof(char));
389373 if (!mtd_part_info) {
390374 printf("%s: Fail to malloc!", __func__);
u-boot/drivers/mtd/nand/spi/Kconfig
....@@ -52,6 +52,12 @@
5252 help
5353 Add support for various ESMT SPI Nand flash chips
5454
55
+config SPI_NAND_XINCUN
56
+ bool "XINCUN SPI flash support"
57
+ default y
58
+ help
59
+ Add support for various XINCUN SPI Nand flash chips
60
+
5561 config SPI_NAND_XTX
5662 bool "XTX SPI flash support"
5763 default y
....@@ -112,4 +118,10 @@
112118 bool "SKYHIGH SPI flash support"
113119 help
114120 Add support for various SKYHIGH SPI Nand flash chips
121
+
122
+config SPI_NAND_GSTO
123
+ default y
124
+ bool "GSTO SPI flash support"
125
+ help
126
+ Add support for various GSTO SPI Nand flash chips
115127 endif
u-boot/drivers/mtd/nand/spi/Makefile
....@@ -8,6 +8,7 @@
88 obj-$(CONFIG_SPI_NAND_WINBOND) += winbond.o
99 obj-$(CONFIG_SPI_NAND_DOSILICON) += dosilicon.o
1010 obj-$(CONFIG_SPI_NAND_ESMT) += esmt.o
11
+obj-$(CONFIG_SPI_NAND_XINCUN) += xincun.o
1112 obj-$(CONFIG_SPI_NAND_XTX) += xtx.o
1213 obj-$(CONFIG_SPI_NAND_HYF) += hyf.o
1314 obj-$(CONFIG_SPI_NAND_FMSH) += fmsh.o
....@@ -18,4 +19,5 @@
1819 obj-$(CONFIG_SPI_NAND_SILICONGO) += silicongo.o
1920 obj-$(CONFIG_SPI_NAND_UNIM) += unim.o
2021 obj-$(CONFIG_SPI_NAND_SKYHIGH) += skyhigh.o
22
+obj-$(CONFIG_SPI_NAND_GSTO) += gsto.o
2123 obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
u-boot/drivers/mtd/nand/spi/core.c
....@@ -510,7 +510,7 @@
510510 const struct nand_page_io_req *req,
511511 bool ecc_enabled)
512512 {
513
- u8 status;
513
+ u8 status = 0;
514514 int ret;
515515
516516 ret = spinand_load_page_op(spinand, req);
....@@ -518,6 +518,12 @@
518518 return ret;
519519
520520 ret = spinand_wait(spinand, &status);
521
+ /*
522
+ * When there is data outside of OIP in the status, the status data is
523
+ * inaccurate and needs to be reconfirmed
524
+ */
525
+ if (spinand->id.data[0] == 0x01 && status && !ret)
526
+ ret = spinand_wait(spinand, &status);
521527 if (ret < 0)
522528 return ret;
523529
....@@ -837,6 +843,9 @@
837843 #ifdef CONFIG_SPI_NAND_ESMT
838844 &esmt_spinand_manufacturer,
839845 #endif
846
+#ifdef CONFIG_SPI_NAND_XINCUN
847
+ &xincun_spinand_manufacturer,
848
+#endif
840849 #ifdef CONFIG_SPI_NAND_XTX
841850 &xtx_spinand_manufacturer,
842851 #endif
....@@ -867,6 +876,9 @@
867876 #ifdef CONFIG_SPI_NAND_SKYHIGH
868877 &skyhigh_spinand_manufacturer,
869878 #endif
879
+#ifdef CONFIG_SPI_NAND_GSTO
880
+ &gsto_spinand_manufacturer,
881
+#endif
870882 };
871883
872884 static int spinand_manufacturer_match(struct spinand_device *spinand,
u-boot/drivers/mtd/nand/spi/dosilicon.c
....@@ -14,7 +14,7 @@
1414
1515 #define SPINAND_MFR_DOSILICON 0xE5
1616
17
-#define DOSICON_STATUS_ECC_MASK GENMASK(7, 4)
17
+#define DOSICON_STATUS_ECC_MASK GENMASK(6, 4)
1818 #define DOSICON_STATUS_ECC_NO_BITFLIPS (0 << 4)
1919 #define DOSICON_STATUS_ECC_1TO3_BITFLIPS (1 << 4)
2020 #define DOSICON_STATUS_ECC_4TO6_BITFLIPS (3 << 4)
....@@ -198,6 +198,26 @@
198198 SPINAND_HAS_QE_BIT,
199199 SPINAND_ECCINFO(&ds35xxgb_ooblayout,
200200 ds35xxgb_ecc_get_status)),
201
+ SPINAND_INFO("DS35Q12B",
202
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF5),
203
+ NAND_MEMORG(1, 2048, 128, 64, 512, 1, 1, 1),
204
+ NAND_ECCREQ(8, 512),
205
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
206
+ &write_cache_variants,
207
+ &update_cache_variants),
208
+ SPINAND_HAS_QE_BIT,
209
+ SPINAND_ECCINFO(&ds35xxgb_ooblayout,
210
+ ds35xxgb_ecc_get_status)),
211
+ SPINAND_INFO("DS35M12B",
212
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA5),
213
+ NAND_MEMORG(1, 2048, 128, 64, 512, 1, 1, 1),
214
+ NAND_ECCREQ(8, 512),
215
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
216
+ &write_cache_variants,
217
+ &update_cache_variants),
218
+ SPINAND_HAS_QE_BIT,
219
+ SPINAND_ECCINFO(&ds35xxgb_ooblayout,
220
+ ds35xxgb_ecc_get_status)),
201221 };
202222
203223 static const struct spinand_manufacturer_ops dosilicon_spinand_manuf_ops = {
u-boot/drivers/mtd/nand/spi/fmsh.c
....@@ -82,6 +82,31 @@
8282 .rfree = fm25s01_ooblayout_free,
8383 };
8484
85
+/*
86
+ * ecc bits: 0xC0[4,6]
87
+ * [0b000], No bit errors were detected;
88
+ * [0b001] and [0b011], 1~6 Bit errors were detected and corrected. Not
89
+ * reach Flipping Bits;
90
+ * [0b101], Bit error count equals the bit flip
91
+ * detection threshold
92
+ * [0b010], Multiple bit errors were detected and
93
+ * not corrected.
94
+ * others, Reserved.
95
+ */
96
+static int fm25s01bi3_ecc_ecc_get_status(struct spinand_device *spinand,
97
+ u8 status)
98
+{
99
+ struct nand_device *nand = spinand_to_nand(spinand);
100
+ u8 eccsr = (status & GENMASK(6, 4)) >> 4;
101
+
102
+ if (eccsr <= 1 || eccsr == 3)
103
+ return eccsr;
104
+ else if (eccsr == 5)
105
+ return nand->eccreq.strength;
106
+ else
107
+ return -EBADMSG;
108
+}
109
+
85110 static const struct spinand_info fmsh_spinand_table[] = {
86111 SPINAND_INFO("FM25S01A",
87112 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4),
....@@ -99,11 +124,11 @@
99124 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
100125 &write_cache_variants,
101126 &update_cache_variants),
102
- 1,
127
+ SPINAND_HAS_QE_BIT,
103128 SPINAND_ECCINFO(&fm25s01a_ooblayout, NULL)),
104129 SPINAND_INFO("FM25S01",
105130 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA1),
106
- NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
131
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
107132 NAND_ECCREQ(1, 512),
108133 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
109134 &write_cache_variants,
....@@ -112,13 +137,22 @@
112137 SPINAND_ECCINFO(&fm25s01_ooblayout, NULL)),
113138 SPINAND_INFO("FM25LS01",
114139 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA5),
115
- NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
140
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
116141 NAND_ECCREQ(1, 512),
117142 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
118143 &write_cache_variants,
119144 &update_cache_variants),
120145 0,
121146 SPINAND_ECCINFO(&fm25s01_ooblayout, NULL)),
147
+ SPINAND_INFO("FM25S01BI3",
148
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4),
149
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
150
+ NAND_ECCREQ(8, 512),
151
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
152
+ &write_cache_variants,
153
+ &update_cache_variants),
154
+ SPINAND_HAS_QE_BIT,
155
+ SPINAND_ECCINFO(&fm25s01_ooblayout, fm25s01bi3_ecc_ecc_get_status)),
122156 };
123157
124158 static const struct spinand_manufacturer_ops fmsh_spinand_manuf_ops = {
u-boot/drivers/mtd/nand/spi/foresee.c
....@@ -28,7 +28,7 @@
2828
2929 static SPINAND_OP_VARIANTS(update_cache_variants,
3030 SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
31
- SPINAND_PROG_LOAD(false, 0, NULL, 0));
31
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
3232
3333 static int fsxxndxxg_ooblayout_ecc(struct mtd_info *mtd, int section,
3434 struct mtd_oob_region *region)
....@@ -117,6 +117,24 @@
117117 &update_cache_variants),
118118 SPINAND_HAS_QE_BIT,
119119 SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)),
120
+ SPINAND_INFO("F35UQA002G-WWT",
121
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x62),
122
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
123
+ NAND_ECCREQ(1, 512),
124
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
125
+ &write_cache_variants,
126
+ &update_cache_variants),
127
+ SPINAND_HAS_QE_BIT,
128
+ SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)),
129
+ SPINAND_INFO("F35UQA001G-WWT",
130
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x61),
131
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
132
+ NAND_ECCREQ(1, 512),
133
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
134
+ &write_cache_variants,
135
+ &update_cache_variants),
136
+ SPINAND_HAS_QE_BIT,
137
+ SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)),
120138 };
121139
122140 static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = {
u-boot/drivers/mtd/nand/spi/gigadevice.c
....@@ -43,6 +43,22 @@
4343 SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
4444 SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
4545
46
+static SPINAND_OP_VARIANTS(read_cache_variants_1gq5,
47
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
48
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
49
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
50
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
51
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
52
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
53
+
54
+static SPINAND_OP_VARIANTS(read_cache_variants_2gq5,
55
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
56
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
57
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
58
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
59
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
60
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
61
+
4662 static SPINAND_OP_VARIANTS(write_cache_variants,
4763 SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
4864 SPINAND_PROG_LOAD(true, 0, NULL, 0));
....@@ -353,6 +369,36 @@
353369 SPINAND_HAS_QE_BIT,
354370 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
355371 gd5fxgq4uexxg_ecc_get_status)),
372
+ SPINAND_INFO("GD5F1GQ4RExxG",
373
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1),
374
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
375
+ NAND_ECCREQ(8, 512),
376
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
377
+ &write_cache_variants,
378
+ &update_cache_variants),
379
+ SPINAND_HAS_QE_BIT,
380
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
381
+ gd5fxgq4uexxg_ecc_get_status)),
382
+ SPINAND_INFO("GD5F2GQ4UExxG",
383
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),
384
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
385
+ NAND_ECCREQ(8, 512),
386
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
387
+ &write_cache_variants,
388
+ &update_cache_variants),
389
+ SPINAND_HAS_QE_BIT,
390
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
391
+ gd5fxgq4uexxg_ecc_get_status)),
392
+ SPINAND_INFO("GD5F2GQ4RExxG",
393
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2),
394
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
395
+ NAND_ECCREQ(8, 512),
396
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
397
+ &write_cache_variants,
398
+ &update_cache_variants),
399
+ SPINAND_HAS_QE_BIT,
400
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
401
+ gd5fxgq4uexxg_ecc_get_status)),
356402 SPINAND_INFO("GD5F1GQ4UFxxG",
357403 SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
358404 NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
....@@ -373,36 +419,116 @@
373419 SPINAND_HAS_QE_BIT,
374420 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
375421 gd5fxgq5xexxg_ecc_get_status)),
376
- SPINAND_INFO("GD5F2GQ5UExxG",
377
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52),
378
- NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
422
+ SPINAND_INFO("GD5F1GQ5RExxG",
423
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41),
424
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
379425 NAND_ECCREQ(4, 512),
380
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
426
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
381427 &write_cache_variants,
382428 &update_cache_variants),
383429 SPINAND_HAS_QE_BIT,
384430 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
385431 gd5fxgq5xexxg_ecc_get_status)),
386
- SPINAND_INFO("GD5F2GQ4UBxxG",
387
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),
432
+ SPINAND_INFO("GD5F2GQ5UExxG",
433
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
434
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
435
+ NAND_ECCREQ(4, 512),
436
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
437
+ &write_cache_variants,
438
+ &update_cache_variants),
439
+ SPINAND_HAS_QE_BIT,
440
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
441
+ gd5fxgq5xexxg_ecc_get_status)),
442
+ SPINAND_INFO("GD5F2GQ5RExxG",
443
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42),
444
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
445
+ NAND_ECCREQ(4, 512),
446
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
447
+ &write_cache_variants,
448
+ &update_cache_variants),
449
+ SPINAND_HAS_QE_BIT,
450
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
451
+ gd5fxgq5xexxg_ecc_get_status)),
452
+ SPINAND_INFO("GD5F4GQ6UExxG",
453
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55),
454
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 2, 1),
455
+ NAND_ECCREQ(4, 512),
456
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
457
+ &write_cache_variants,
458
+ &update_cache_variants),
459
+ SPINAND_HAS_QE_BIT,
460
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
461
+ gd5fxgq5xexxg_ecc_get_status)),
462
+ SPINAND_INFO("GD5F4GQ6RExxG",
463
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45),
464
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 2, 1),
465
+ NAND_ECCREQ(4, 512),
466
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
467
+ &write_cache_variants,
468
+ &update_cache_variants),
469
+ SPINAND_HAS_QE_BIT,
470
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
471
+ gd5fxgq5xexxg_ecc_get_status)),
472
+ SPINAND_INFO("GD5F1GM7UExxG",
473
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91),
474
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
475
+ NAND_ECCREQ(8, 512),
476
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
477
+ &write_cache_variants,
478
+ &update_cache_variants),
479
+ SPINAND_HAS_QE_BIT,
480
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
481
+ gd5fxgq4uexxg_ecc_get_status)),
482
+ SPINAND_INFO("GD5F1GM7RExxG",
483
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81),
484
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
485
+ NAND_ECCREQ(8, 512),
486
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
487
+ &write_cache_variants,
488
+ &update_cache_variants),
489
+ SPINAND_HAS_QE_BIT,
490
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
491
+ gd5fxgq4uexxg_ecc_get_status)),
492
+ SPINAND_INFO("GD5F2GM7UExxG",
493
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
388494 NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
389495 NAND_ECCREQ(8, 512),
390
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
496
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
391497 &write_cache_variants,
392498 &update_cache_variants),
393499 SPINAND_HAS_QE_BIT,
394500 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
395
- gd5fxgq4xa_ecc_get_status)),
396
- SPINAND_INFO("GD5F4GQ6UExxG",
397
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x55),
501
+ gd5fxgq4uexxg_ecc_get_status)),
502
+ SPINAND_INFO("GD5F2GM7RExxG",
503
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82),
504
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
505
+ NAND_ECCREQ(8, 512),
506
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
507
+ &write_cache_variants,
508
+ &update_cache_variants),
509
+ SPINAND_HAS_QE_BIT,
510
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
511
+ gd5fxgq4uexxg_ecc_get_status)),
512
+ SPINAND_INFO("GD5F4GM8UExxG",
513
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95),
398514 NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
399
- NAND_ECCREQ(4, 512),
400
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
515
+ NAND_ECCREQ(8, 512),
516
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
401517 &write_cache_variants,
402518 &update_cache_variants),
403519 SPINAND_HAS_QE_BIT,
404520 SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
405
- gd5fxgq5xexxg_ecc_get_status)),
521
+ gd5fxgq4uexxg_ecc_get_status)),
522
+ SPINAND_INFO("GD5F4GM8RExxG",
523
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85),
524
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
525
+ NAND_ECCREQ(8, 512),
526
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
527
+ &write_cache_variants,
528
+ &update_cache_variants),
529
+ SPINAND_HAS_QE_BIT,
530
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
531
+ gd5fxgq4uexxg_ecc_get_status)),
406532 SPINAND_INFO("GD5F1GQ4UExxH",
407533 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd9),
408534 NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
....@@ -412,56 +538,6 @@
412538 &update_cache_variants),
413539 SPINAND_HAS_QE_BIT,
414540 SPINAND_ECCINFO(&gd5fxgqx_variant3_ooblayout,
415
- gd5fxgq4xa_ecc_get_status)),
416
- SPINAND_INFO("GD5F1GQ5RExxG",
417
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x41),
418
- NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
419
- NAND_ECCREQ(4, 512),
420
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
421
- &write_cache_variants,
422
- &update_cache_variants),
423
- SPINAND_HAS_QE_BIT,
424
- SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
425
- gd5fxgq5xexxg_ecc_get_status)),
426
- SPINAND_INFO("GD5F2GQ5RExxG",
427
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x42),
428
- NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
429
- NAND_ECCREQ(4, 512),
430
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
431
- &write_cache_variants,
432
- &update_cache_variants),
433
- SPINAND_HAS_QE_BIT,
434
- SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
435
- gd5fxgq5xexxg_ecc_get_status)),
436
- SPINAND_INFO("GD5F2GM7RxG",
437
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x82),
438
- NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
439
- NAND_ECCREQ(8, 512),
440
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
441
- &write_cache_variants,
442
- &update_cache_variants),
443
- SPINAND_HAS_QE_BIT,
444
- SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
445
- gd5fxgq4xa_ecc_get_status)),
446
- SPINAND_INFO("GD5F1GM7UxG",
447
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x91),
448
- NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
449
- NAND_ECCREQ(8, 512),
450
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
451
- &write_cache_variants,
452
- &update_cache_variants),
453
- SPINAND_HAS_QE_BIT,
454
- SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
455
- gd5fxgq4xa_ecc_get_status)),
456
- SPINAND_INFO("GD5F2GM7UxG",
457
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x92),
458
- NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
459
- NAND_ECCREQ(8, 512),
460
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
461
- &write_cache_variants,
462
- &update_cache_variants),
463
- SPINAND_HAS_QE_BIT,
464
- SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
465541 gd5fxgq4xa_ecc_get_status)),
466542 };
467543
u-boot/drivers/mtd/nand/spi/gsto.c
....@@ -0,0 +1,92 @@
1
+// SPDX-License-Identifier: GPL-2.0
2
+/*
3
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd
4
+ *
5
+ * Authors:
6
+ * Dingqiang Lin <jon.lin@rock-chips.com>
7
+ */
8
+
9
+#ifndef __UBOOT__
10
+#include <linux/device.h>
11
+#include <linux/kernel.h>
12
+#endif
13
+#include <linux/mtd/spinand.h>
14
+
15
+#define SPINAND_MFR_GSTO 0x52
16
+
17
+static SPINAND_OP_VARIANTS(read_cache_variants,
18
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
19
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
20
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
21
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
22
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
23
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
24
+
25
+static SPINAND_OP_VARIANTS(write_cache_variants,
26
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
27
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
28
+
29
+static SPINAND_OP_VARIANTS(update_cache_variants,
30
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
31
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
32
+
33
+static int gss0xgsak1_ooblayout_ecc(struct mtd_info *mtd, int section,
34
+ struct mtd_oob_region *region)
35
+{
36
+ if (section)
37
+ return -ERANGE;
38
+
39
+ region->offset = 32;
40
+ region->length = 32;
41
+
42
+ return 0;
43
+}
44
+
45
+static int gss0xgsak1_ooblayout_free(struct mtd_info *mtd, int section,
46
+ struct mtd_oob_region *region)
47
+{
48
+ if (section)
49
+ return -ERANGE;
50
+
51
+ region->offset = 2;
52
+ region->length = 30;
53
+
54
+ return 0;
55
+}
56
+
57
+static const struct mtd_ooblayout_ops gss0xgsak1_ooblayout = {
58
+ .ecc = gss0xgsak1_ooblayout_ecc,
59
+ .rfree = gss0xgsak1_ooblayout_free,
60
+};
61
+
62
+static const struct spinand_info gsto_spinand_table[] = {
63
+ SPINAND_INFO("GSS01GSAK1",
64
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBA, 0x13),
65
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
66
+ NAND_ECCREQ(4, 512),
67
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
68
+ &write_cache_variants,
69
+ &update_cache_variants),
70
+ 0,
71
+ SPINAND_ECCINFO(&gss0xgsak1_ooblayout, NULL)),
72
+ SPINAND_INFO("GSS02GSAK1",
73
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBA, 0x23),
74
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
75
+ NAND_ECCREQ(4, 512),
76
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
77
+ &write_cache_variants,
78
+ &update_cache_variants),
79
+ 0,
80
+ SPINAND_ECCINFO(&gss0xgsak1_ooblayout, NULL)),
81
+};
82
+
83
+static const struct spinand_manufacturer_ops gsto_spinand_manuf_ops = {
84
+};
85
+
86
+const struct spinand_manufacturer gsto_spinand_manufacturer = {
87
+ .id = SPINAND_MFR_GSTO,
88
+ .name = "GSTO",
89
+ .chips = gsto_spinand_table,
90
+ .nchips = ARRAY_SIZE(gsto_spinand_table),
91
+ .ops = &gsto_spinand_manuf_ops,
92
+};
u-boot/drivers/mtd/nand/spi/hyf.c
....@@ -106,7 +106,7 @@
106106 if (section > 3)
107107 return -ERANGE;
108108
109
- region->offset = 16 * section;
109
+ region->offset = 32 * section;
110110 region->length = 8;
111111
112112 return 0;
....@@ -199,6 +199,26 @@
199199 SPINAND_HAS_QE_BIT,
200200 SPINAND_ECCINFO(&hyf2gq4uaacae_ooblayout,
201201 hyf1gq4udacae_ecc_get_status)),
202
+ SPINAND_INFO("HYF2GQ4IAACAE",
203
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x82),
204
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
205
+ NAND_ECCREQ(14, 512),
206
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
207
+ &write_cache_variants,
208
+ &update_cache_variants),
209
+ SPINAND_HAS_QE_BIT,
210
+ SPINAND_ECCINFO(&hyf2gq4uaacae_ooblayout,
211
+ hyf1gq4udacae_ecc_get_status)),
212
+ SPINAND_INFO("HYF1GQ4IDACAE",
213
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x81),
214
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
215
+ NAND_ECCREQ(4, 512),
216
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
217
+ &write_cache_variants,
218
+ &update_cache_variants),
219
+ SPINAND_HAS_QE_BIT,
220
+ SPINAND_ECCINFO(&hyf1gq4udacae_ooblayout,
221
+ hyf1gq4udacae_ecc_get_status)),
202222 };
203223
204224 static const struct spinand_manufacturer_ops hyf_spinand_manuf_ops = {
u-boot/drivers/mtd/nand/spi/jsc.c
....@@ -72,12 +72,13 @@
7272 static int js28u1gqscahg_ecc_get_status(struct spinand_device *spinand,
7373 u8 status)
7474 {
75
- u8 eccsr = (status & GENMASK(6, 4)) >> 2;
75
+ struct nand_device *nand = spinand_to_nand(spinand);
76
+ u8 eccsr = (status & GENMASK(6, 4)) >> 4;
7677
77
- if (eccsr <= 7)
78
+ if (eccsr < 4)
7879 return eccsr;
79
- else if (eccsr == 12)
80
- return 8;
80
+ else if (eccsr == 4)
81
+ return nand->eccreq.strength;
8182 else
8283 return -EBADMSG;
8384 }
u-boot/drivers/mtd/nand/spi/skyhigh.c
....@@ -14,6 +14,10 @@
1414
1515 #define SPINAND_MFR_SKYHIGH 0x01
1616
17
+#define SKYHIGH_STATUS_ECC_1_2_BITFLIPS (1 << 4)
18
+#define SKYHIGH_STATUS_ECC_3_4_BITFLIPS (2 << 4)
19
+#define SKYHIGH_STATUS_ECC_UNCOR_ERROR (3 << 4)
20
+
1721 static SPINAND_OP_VARIANTS(read_cache_variants,
1822 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
1923 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
....@@ -27,8 +31,8 @@
2731 SPINAND_PROG_LOAD(true, 0, NULL, 0));
2832
2933 static SPINAND_OP_VARIANTS(update_cache_variants,
30
- SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
31
- SPINAND_PROG_LOAD(false, 0, NULL, 0));
34
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
35
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
3236
3337 static int s35ml04g3_ooblayout_ecc(struct mtd_info *mtd, int section,
3438 struct mtd_oob_region *region)
....@@ -53,7 +57,48 @@
5357 .rfree = s35ml04g3_ooblayout_free,
5458 };
5559
60
+
61
+static int s35ml0xg3_ecc_get_status(struct spinand_device *spinand,
62
+ u8 status)
63
+{
64
+ struct nand_device *nand = spinand_to_nand(spinand);
65
+
66
+ switch (status & STATUS_ECC_MASK) {
67
+ case STATUS_ECC_NO_BITFLIPS:
68
+ return 0;
69
+
70
+ case SKYHIGH_STATUS_ECC_UNCOR_ERROR:
71
+ return -EBADMSG;
72
+
73
+ case SKYHIGH_STATUS_ECC_1_2_BITFLIPS:
74
+ return 2;
75
+
76
+ default:
77
+ return nand->eccreq.strength;
78
+ }
79
+
80
+ return -EINVAL;
81
+}
82
+
5683 static const struct spinand_info skyhigh_spinand_table[] = {
84
+ SPINAND_INFO("S35ML01G3",
85
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
86
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 2, 1, 1),
87
+ NAND_ECCREQ(4, 512),
88
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
89
+ &write_cache_variants,
90
+ &update_cache_variants),
91
+ SPINAND_HAS_QE_BIT,
92
+ SPINAND_ECCINFO(&s35ml04g3_ooblayout, s35ml0xg3_ecc_get_status)),
93
+ SPINAND_INFO("S35ML02G3",
94
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
95
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
96
+ NAND_ECCREQ(4, 512),
97
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
98
+ &write_cache_variants,
99
+ &update_cache_variants),
100
+ SPINAND_HAS_QE_BIT,
101
+ SPINAND_ECCINFO(&s35ml04g3_ooblayout, s35ml0xg3_ecc_get_status)),
57102 SPINAND_INFO("S35ML04G3",
58103 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
59104 NAND_MEMORG(1, 2048, 128, 64, 4096, 2, 1, 1),
....@@ -62,7 +107,7 @@
62107 &write_cache_variants,
63108 &update_cache_variants),
64109 SPINAND_HAS_QE_BIT,
65
- SPINAND_ECCINFO(&s35ml04g3_ooblayout, NULL)),
110
+ SPINAND_ECCINFO(&s35ml04g3_ooblayout, s35ml0xg3_ecc_get_status)),
66111 };
67112
68113 static const struct spinand_manufacturer_ops skyhigh_spinand_manuf_ops = {
u-boot/drivers/mtd/nand/spi/unim.c
....@@ -71,12 +71,13 @@
7171 static int tx25g01_ecc_get_status(struct spinand_device *spinand,
7272 u8 status)
7373 {
74
- u8 eccsr = (status & GENMASK(6, 4)) >> 2;
74
+ struct nand_device *nand = spinand_to_nand(spinand);
75
+ u8 eccsr = (status & GENMASK(6, 4)) >> 4;
7576
76
- if (eccsr <= 7)
77
+ if (eccsr < 4)
7778 return eccsr;
78
- else if (eccsr == 12)
79
- return 8;
79
+ else if (eccsr == 4)
80
+ return nand->eccreq.strength;
8081 else
8182 return -EBADMSG;
8283 }
u-boot/drivers/mtd/nand/spi/xincun.c
....@@ -0,0 +1,108 @@
1
+/* SPDX-License-Identifier: GPL-2.0 */
2
+/*
3
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd
4
+ *
5
+ * Authors:
6
+ * Dingqiang Lin <jon.lin@rock-chips.com>
7
+ */
8
+
9
+#ifndef __UBOOT__
10
+#include <linux/device.h>
11
+#include <linux/kernel.h>
12
+#endif
13
+#include <linux/mtd/spinand.h>
14
+
15
+#define SPINAND_MFR_XINCUN 0x8C
16
+#define XINCUN_STATUS_ECC_HAS_BITFLIPS_T (3 << 4)
17
+
18
+static SPINAND_OP_VARIANTS(read_cache_variants,
19
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
20
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
21
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
22
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
23
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
24
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
25
+
26
+static SPINAND_OP_VARIANTS(write_cache_variants,
27
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
28
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
29
+
30
+static SPINAND_OP_VARIANTS(update_cache_variants,
31
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
32
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
33
+
34
+static int xcsp2aapk_ooblayout_ecc(struct mtd_info *mtd, int section,
35
+ struct mtd_oob_region *region)
36
+{
37
+ if (section)
38
+ return -ERANGE;
39
+
40
+ region->offset = mtd->oobsize / 2;
41
+ region->length = mtd->oobsize / 2;
42
+
43
+ return 0;
44
+}
45
+
46
+static int xcsp2aapk_ooblayout_free(struct mtd_info *mtd, int section,
47
+ struct mtd_oob_region *region)
48
+{
49
+ if (section)
50
+ return -ERANGE;
51
+
52
+ /* Reserve 2 bytes for the BBM. */
53
+ region->offset = 2;
54
+ region->length = mtd->oobsize / 2 - 2;
55
+
56
+ return 0;
57
+}
58
+
59
+static const struct mtd_ooblayout_ops xcsp2aapk_ooblayout = {
60
+ .ecc = xcsp2aapk_ooblayout_ecc,
61
+ .rfree = xcsp2aapk_ooblayout_free,
62
+};
63
+
64
+static int xcsp2aapk_ecc_get_status(struct spinand_device *spinand,
65
+ u8 status)
66
+{
67
+ struct nand_device *nand = spinand_to_nand(spinand);
68
+
69
+ switch (status & STATUS_ECC_MASK) {
70
+ case STATUS_ECC_NO_BITFLIPS:
71
+ return 0;
72
+
73
+ case STATUS_ECC_UNCOR_ERROR:
74
+ return -EBADMSG;
75
+
76
+ case STATUS_ECC_HAS_BITFLIPS:
77
+ return 0;
78
+ case XINCUN_STATUS_ECC_HAS_BITFLIPS_T:
79
+ return nand->eccreq.strength;
80
+ default:
81
+ break;
82
+ }
83
+
84
+ return -EINVAL;
85
+}
86
+
87
+static const struct spinand_info xincun_spinand_table[] = {
88
+ SPINAND_INFO("XCSP2AAPK",
89
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xA1),
90
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
91
+ NAND_ECCREQ(8, 512),
92
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
93
+ &write_cache_variants,
94
+ &update_cache_variants),
95
+ SPINAND_HAS_QE_BIT,
96
+ SPINAND_ECCINFO(&xcsp2aapk_ooblayout, xcsp2aapk_ecc_get_status)),
97
+};
98
+
99
+static const struct spinand_manufacturer_ops xincun_spinand_manuf_ops = {
100
+};
101
+
102
+const struct spinand_manufacturer xincun_spinand_manufacturer = {
103
+ .id = SPINAND_MFR_XINCUN,
104
+ .name = "XINCUN",
105
+ .chips = xincun_spinand_table,
106
+ .nchips = ARRAY_SIZE(xincun_spinand_table),
107
+ .ops = &xincun_spinand_manuf_ops,
108
+};
u-boot/drivers/mtd/spi/sf_internal.h
....@@ -68,6 +68,7 @@
6868 #define USE_CLSR BIT(14) /* use CLSR command */
6969 #define SPI_NOR_HAS_SST26LOCK BIT(15) /* Flash supports lock/unlock via BPR */
7070 #define SPI_NOR_OCTAL_READ BIT(16) /* Flash supports Octal Read */
71
+#define SPI_NOR_OCTAL_DTR_READ BIT(17) /* Flash supports Octal DTR Read */
7172 };
7273
7374 extern const struct flash_info spi_nor_ids[];
u-boot/drivers/mtd/spi/spi-nor-ids.c
....@@ -85,6 +85,9 @@
8585 { INFO("en25qh64", 0x1c7017, 0, 64 * 1024, 128, SECT_4K) },
8686 { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, SECT_4K) },
8787 { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
88
+ { INFO("en25qh256a", 0x1c7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
89
+ { INFO("en25qx256a", 0x1c7119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
90
+ { INFO("en25qx128a", 0x1c7118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
8891 #endif
8992 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
9093 /* GigaDevice */
....@@ -118,28 +121,18 @@
118121 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
119122 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
120123 },
121
- {
122
- INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
123
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
124
- SPI_NOR_HAS_TB)
125
- },
126
- { INFO("gd25q256", 0xc84019, 0, 64 * 1024, 512,
127
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
128
- SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
129
- SPI_NOR_HAS_TB)
130
- },
131124 { INFO("gd25q512", 0xc84020, 0, 64 * 1024, 1024,
132125 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
133126 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
134127 SPI_NOR_HAS_TB)
135128 },
136129 {
137
- INFO("gd25lq255", 0xc86019, 0, 64 * 1024, 512,
130
+ INFO("gd25lb512m", 0xc8671a, 0, 64 * 1024, 1024,
138131 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
139132 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK)
140133 },
141134 {
142
- INFO("gd25lb512m", 0xc8671a, 0, 64 * 1024, 1024,
135
+ INFO("gd55lb01ge", 0xc8671b, 0, 64 * 1024, 2048,
143136 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
144137 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK)
145138 },
....@@ -148,17 +141,112 @@
148141 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
149142 SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK)
150143 },
144
+ {
145
+ INFO("gd55b01ge", 0xc8471b, 0, 64 * 1024, 2048,
146
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
147
+ SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK)
148
+ },
149
+ /* adding these 3V QSPI flash parts */
150
+ {INFO("gd25b256", 0xc84019, 0, 64 * 1024, 512, SECT_4K |
151
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES) },
152
+ {INFO("gd25b512", 0xc8471A, 0, 64 * 1024, 1024, SECT_4K |
153
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
154
+ {INFO("gd55b01g", 0xc8471B, 0, 64 * 1024, 2048, SECT_4K |
155
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
156
+ {INFO("gd55b02g", 0xc8471C, 0, 64 * 1024, 4096, SECT_4K |
157
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
158
+ {INFO("gd25f64", 0xc84317, 0, 64 * 1024, 128, SECT_4K |
159
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
160
+ {INFO("gd25f128", 0xc84318, 0, 64 * 1024, 256, SECT_4K |
161
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
162
+ {INFO("gd25f256", 0xc84319, 0, 64 * 1024, 512, SECT_4K |
163
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
164
+ {INFO("gd55f512", 0xc8431A, 0, 64 * 1024, 1024, SECT_4K |
165
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
166
+ {INFO("gd25t512", 0xc8461A, 0, 64 * 1024, 1024, SECT_4K |
167
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
168
+ {INFO("gd55t01g", 0xc8461B, 0, 64 * 1024, 2048, SECT_4K |
169
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
170
+ {INFO("gd55t02g", 0xc8461C, 0, 64 * 1024, 4096, SECT_4K |
171
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
172
+ /* adding these 3V OSPI flash parts */
173
+ {INFO("gd25x512", 0xc8481A, 0, 64 * 1024, 1024, SECT_4K |
174
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
175
+ {INFO("gd55x01g", 0xc8481B, 0, 64 * 1024, 2048, SECT_4K |
176
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
177
+ {INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K |
178
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
179
+ {
180
+ INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
181
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
182
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
183
+ },
184
+ {
185
+ INFO("gd25lq256d", 0xc86019, 0, 64 * 1024, 512,
186
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
187
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
188
+ },
189
+ /* adding these 1.8V QSPI flash parts */
190
+ {INFO("gd25lb256", 0xc86719, 0, 64 * 1024, 512, SECT_4K |
191
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
192
+ {INFO("gd25lb512", 0xc8671A, 0, 64 * 1024, 1024, SECT_4K |
193
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
194
+ {INFO("gd55lb01g", 0xc8671B, 0, 64 * 1024, 2048, SECT_4K |
195
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
196
+ {INFO("gd55lb02g", 0xc8671C, 0, 64 * 1024, 4096, SECT_4K |
197
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
198
+ {INFO("gd25lf80", 0xc86314, 0, 64 * 1024, 16, SECT_4K |
199
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
200
+ {INFO("gd25lf16", 0xc86315, 0, 64 * 1024, 32, SECT_4K |
201
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
202
+ {INFO("gd25lf32", 0xc86316, 0, 64 * 1024, 64, SECT_4K |
203
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
204
+ {INFO("gd25lf64", 0xc86317, 0, 64 * 1024, 128, SECT_4K |
205
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
206
+ {INFO("gd25lf128", 0xc86318, 0, 64 * 1024, 256, SECT_4K |
207
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
208
+ {INFO("gd25lf255", 0xc86319, 0, 64 * 1024, 512, SECT_4K |
209
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
210
+ {INFO("gd25lf511", 0xc8631A, 0, 64 * 1024, 1024, SECT_4K |
211
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
212
+ {INFO("gd25lt256", 0xc86619, 0, 64 * 1024, 512, SECT_4K |
213
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
214
+ {INFO("gd25lt512", 0xc8661A, 0, 64 * 1024, 1024, SECT_4K |
215
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
216
+ {INFO("gd55lt01g", 0xc8661B, 0, 64 * 1024, 2048, SECT_4K |
217
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
218
+ {INFO("gd55lt02g", 0xc8661C, 0, 64 * 1024, 4096, SECT_4K |
219
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
220
+ {
221
+ INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
222
+ SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
223
+ },
224
+ /* adding these 1.8V OSPI flash parts */
225
+ {INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024, SECT_4K |
226
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
227
+ {INFO("gd55lx01g", 0xc8681B, 0, 64 * 1024, 2048, SECT_4K |
228
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
229
+ {INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096, SECT_4K |
230
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
151231 #endif
152232 #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
153233 /* ISSI */
154234 { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8,
155235 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
236
+ { INFO("is25lp008", 0x9d6014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) },
237
+ { INFO("is25lp016", 0x9d6015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) },
156238 { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) },
157239 { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) },
158240 { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256,
159241 SECT_4K | SPI_NOR_DUAL_READ) },
160242 { INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512,
161243 SECT_4K | SPI_NOR_DUAL_READ) },
244
+ { INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024,
245
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
246
+ { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048,
247
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
248
+ { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) },
249
+ { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) },
162250 { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64,
163251 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
164252 { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128,
....@@ -168,6 +256,12 @@
168256 { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512,
169257 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
170258 SPI_NOR_4B_OPCODES) },
259
+ { INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024,
260
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
261
+ { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048,
262
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
263
+ { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256,
264
+ SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
171265 #endif
172266 #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
173267 /* Macronix */
....@@ -183,17 +277,41 @@
183277 { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
184278 { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
185279 { INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
280
+ { INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
281
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
186282 { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
187283 { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
188284 { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
285
+ { INFO("mx25v8035f", 0xc22314, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
286
+ { INFO("mx25r1635f", 0xc22815, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
189287 { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
190288 { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
191289 { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
290
+ { INFO("mx25u51245f", 0xc2953a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
291
+ { INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
192292 { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
193293 { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
294
+ { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
194295 { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
195296 { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) },
196
- { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
297
+ { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
298
+ { INFO("mx66lm1g45g", 0xc2853b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
299
+ { INFO("mx25lm51245g", 0xc2853a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
300
+ { INFO("mx25lw51245g", 0xc2863a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
301
+ { INFO("mx25lm25645g", 0xc28539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
302
+ { INFO("mx66uw2g345g", 0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
303
+ { INFO("mx66um1g45g", 0xc2803b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
304
+ { INFO("mx66uw1g45g", 0xc2813b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
305
+ { INFO("mx25uw51245g", 0xc2813a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
306
+ { INFO("mx25uw51345g", 0xc2843a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
307
+ { INFO("mx25um25645g", 0xc28039, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
308
+ { INFO("mx25uw25645g", 0xc28139, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
309
+ { INFO("mx25um25345g", 0xc28339, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
310
+ { INFO("mx25uw25345g", 0xc28439, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
311
+ { INFO("mx25uw12845g", 0xc28138, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
312
+ { INFO("mx25uw12345g", 0xc28438, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
313
+ { INFO("mx25uw6445g", 0xc28137, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
314
+ { INFO("mx25uw6345g", 0xc28437, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
197315 #endif
198316
199317 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
....@@ -210,7 +328,7 @@
210328 { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
211329 { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) },
212330 { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024,
213
- SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
331
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
214332 USE_FSR) },
215333 { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
216334 { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
....@@ -219,7 +337,12 @@
219337 { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
220338 { INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
221339 { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
222
- { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
340
+ { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) },
341
+#ifdef CONFIG_SPI_FLASH_MT35XU
342
+ { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
343
+ { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
344
+#endif /* CONFIG_SPI_FLASH_MT35XU */
345
+ { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
223346 { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
224347 #endif
225348 #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
....@@ -235,6 +358,7 @@
235358 { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
236359 { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
237360 { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
361
+ { INFO("s70fs01gs_256k", 0x010221, 0x4d00, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
238362 { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) },
239363 { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) },
240364 { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
....@@ -347,6 +471,31 @@
347471 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
348472 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
349473 },
474
+ {
475
+ INFO("w25q512jv", 0xef7119, 0, 64 * 1024, 512,
476
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
477
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
478
+ },
479
+ {
480
+ INFO("w25q512nwq", 0xef6020, 0, 64 * 1024, 1024,
481
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
482
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
483
+ },
484
+ {
485
+ INFO("w25q512nwm", 0xef8020, 0, 64 * 1024, 1024,
486
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
487
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
488
+ },
489
+ {
490
+ INFO("w25q512jvq", 0xef4020, 0, 64 * 1024, 1024,
491
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
492
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
493
+ },
494
+ {
495
+ INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048,
496
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
497
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
498
+ },
350499 { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) },
351500 { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
352501 { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
....@@ -358,6 +507,7 @@
358507 { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
359508 { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
360509 { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
510
+ { INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
361511 #endif
362512 #ifdef CONFIG_SPI_FLASH_XMC
363513 /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
....@@ -376,17 +526,23 @@
376526 /* XTX Technology (Shenzhen) Limited */
377527 { INFO("xt25f64f", 0x0b4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
378528 { INFO("xt25f128b", 0x0b4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
529
+ { INFO("xt25f256b", 0x0b4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
530
+ { INFO("xt25q64d", 0x0b6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
531
+ { INFO("xt25q128d", 0x0b6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
379532 #endif
380533 #ifdef CONFIG_SPI_FLASH_PUYA
381534 /* PUYA Semiconductor (Shanghai) Co., Ltd. */
382535 { INFO("P25Q64H", 0x856017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
383536 { INFO("P25Q128H", 0x856018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
537
+ { INFO("PY25Q64HA", 0x852017, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
384538 { INFO("PY25Q128HA", 0x852018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
539
+ { INFO("PY25Q256HB", 0x852019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
385540 #endif
386541 #ifdef CONFIG_SPI_FLASH_FMSH
387542 /* FUDAN MICRO (Shanghai) Co., Ltd. */
388543 { INFO("FM25Q128A", 0xA14018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
389544 { INFO("FM25Q64", 0xA14017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
545
+ { INFO("FM25Q256I3", 0xA14019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
390546 #endif
391547 #ifdef CONFIG_SPI_FLASH_DOSILICON
392548 /* Dosilicon Co., Ltd. */
u-boot/drivers/mtd/ubi/debug.h
....@@ -28,13 +28,8 @@
2828 } \
2929 } while (0)
3030 #else
31
-#define ubi_assert(expr) do { \
32
- if (unlikely(!(expr))) { \
33
- pr_debug("UBI assert failed in %s at %u\n", \
34
- __func__, __LINE__); \
35
- dump_stack(); \
36
- } \
37
-} while (0)
31
+#include <log.h>
32
+#define ubi_assert(expr) assert(expr)
3833 #endif
3934
4035 #define ubi_dbg_print_hex_dump(ps, pt, r, g, b, len, a) \
u-boot/drivers/net/gmac_rockchip.c
....@@ -18,6 +18,9 @@
1818 #include <asm/arch/clock.h>
1919 #include <asm/arch/hardware.h>
2020 #ifdef CONFIG_DWC_ETH_QOS
21
+#include <asm/arch/grf_rk3528.h>
22
+#include <asm/arch/grf_rk3562.h>
23
+#include <asm/arch/ioc_rk3562.h>
2124 #include <asm/arch/grf_rk3568.h>
2225 #include <asm/arch/grf_rk3588.h>
2326 #include <asm/arch/grf_rv1106.h>
....@@ -516,6 +519,147 @@
516519 return 0;
517520 }
518521 #else
522
+static int rk3528_set_rgmii_speed(struct gmac_rockchip_platdata *pdata,
523
+ struct rockchip_eth_dev *dev)
524
+{
525
+ struct eqos_priv *priv = &dev->eqos;
526
+ struct rk3528_grf *grf;
527
+ unsigned int div;
528
+
529
+ enum {
530
+ RK3528_GMAC0_CLK_RMII_DIV_SHIFT = 3,
531
+ RK3528_GMAC0_CLK_RMII_DIV_MASK = GENMASK(4, 3),
532
+ RK3528_GMAC0_CLK_RMII_DIV2 = BIT(3),
533
+ RK3528_GMAC0_CLK_RMII_DIV20 = 0,
534
+ };
535
+
536
+ enum {
537
+ RK3528_GMAC1_CLK_RGMII_DIV_SHIFT = 10,
538
+ RK3528_GMAC1_CLK_RGMII_DIV_MASK = GENMASK(11, 10),
539
+ RK3528_GMAC1_CLK_RGMII_DIV1 = 0,
540
+ RK3528_GMAC1_CLK_RGMII_DIV5 = GENMASK(11, 10),
541
+ RK3528_GMAC1_CLK_RGMII_DIV50 = BIT(11),
542
+ RK3528_GMAC1_CLK_RMII_DIV2 = BIT(11),
543
+ RK3528_GMAC1_CLK_RMII_DIV20 = 0,
544
+ };
545
+
546
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
547
+
548
+ switch (priv->phy->speed) {
549
+ case 10:
550
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
551
+ div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV20 :
552
+ RK3528_GMAC0_CLK_RMII_DIV20;
553
+ else
554
+ div = RK3528_GMAC1_CLK_RGMII_DIV50;
555
+ break;
556
+ case 100:
557
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
558
+ div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV2 :
559
+ RK3528_GMAC0_CLK_RMII_DIV2;
560
+ else
561
+ div = RK3528_GMAC1_CLK_RGMII_DIV5;
562
+ break;
563
+ case 1000:
564
+ if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
565
+ div = RK3528_GMAC1_CLK_RGMII_DIV1;
566
+ else
567
+ return -EINVAL;
568
+ break;
569
+ default:
570
+ debug("Unknown phy speed: %d\n", priv->phy->speed);
571
+ return -EINVAL;
572
+ }
573
+
574
+ if (pdata->bus_id)
575
+ rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_RGMII_DIV_MASK, div);
576
+ else
577
+ rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_DIV_MASK, div);
578
+
579
+ return 0;
580
+}
581
+
582
+static int rk3562_set_gmac_speed(struct gmac_rockchip_platdata *pdata,
583
+ struct rockchip_eth_dev *dev)
584
+{
585
+ struct eqos_priv *priv = &dev->eqos;
586
+ struct rk3562_grf *grf;
587
+ unsigned int div;
588
+
589
+ enum {
590
+ RK3562_GMAC0_CLK_RGMII_DIV_SHIFT = 7,
591
+ RK3562_GMAC0_CLK_RGMII_DIV_MASK = GENMASK(8, 7),
592
+ RK3562_GMAC0_CLK_RGMII_DIV1 = 0,
593
+ RK3562_GMAC0_CLK_RGMII_DIV5 = GENMASK(8, 7),
594
+ RK3562_GMAC0_CLK_RGMII_DIV50 = BIT(8),
595
+ RK3562_GMAC0_CLK_RMII_DIV2 = BIT(7),
596
+ RK3562_GMAC0_CLK_RMII_DIV20 = 0,
597
+ };
598
+
599
+ enum {
600
+ RK3562_GMAC1_SPEED_SHIFT = 0x0,
601
+ RK3562_GMAC1_SPEED_MASK = BIT(0),
602
+ RK3562_GMAC1_SPEED_10M = 0,
603
+ RK3562_GMAC1_SPEED_100M = BIT(0),
604
+ };
605
+
606
+ enum {
607
+ RK3562_GMAC1_CLK_RMII_DIV_SHIFT = 13,
608
+ RK3562_GMAC1_CLK_RMII_DIV_MASK = BIT(13),
609
+ RK3562_GMAC1_CLK_RMII_DIV2 = BIT(13),
610
+ RK3562_GMAC1_CLK_RMII_DIV20 = 0,
611
+ };
612
+
613
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
614
+
615
+ switch (priv->phy->speed) {
616
+ case 10:
617
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) {
618
+ if (pdata->bus_id > 0) {
619
+ div = RK3562_GMAC1_CLK_RMII_DIV20;
620
+ rk_clrsetreg(&grf->soc_con[0],
621
+ RK3562_GMAC1_SPEED_MASK,
622
+ RK3562_GMAC1_SPEED_10M);
623
+ } else {
624
+ div = RK3562_GMAC0_CLK_RMII_DIV20;
625
+ }
626
+ } else {
627
+ div = RK3562_GMAC0_CLK_RGMII_DIV50;
628
+ }
629
+ break;
630
+ case 100:
631
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) {
632
+ if (pdata->bus_id > 0) {
633
+ div = RK3562_GMAC1_CLK_RMII_DIV2;
634
+ rk_clrsetreg(&grf->soc_con[0],
635
+ RK3562_GMAC1_SPEED_MASK,
636
+ RK3562_GMAC1_SPEED_100M);
637
+ } else {
638
+ div = RK3562_GMAC0_CLK_RMII_DIV2;
639
+ }
640
+ } else {
641
+ div = RK3562_GMAC0_CLK_RGMII_DIV5;
642
+ }
643
+ break;
644
+ case 1000:
645
+ if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
646
+ div = RK3562_GMAC0_CLK_RGMII_DIV1;
647
+ else
648
+ return -EINVAL;
649
+ break;
650
+ default:
651
+ debug("Unknown phy speed: %d\n", priv->phy->speed);
652
+ return -EINVAL;
653
+ }
654
+
655
+ if (pdata->bus_id)
656
+ rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_RMII_DIV_MASK, div);
657
+ else
658
+ rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_RGMII_DIV_MASK, div);
659
+
660
+ return 0;
661
+}
662
+
519663 static int rk3588_set_rgmii_speed(struct gmac_rockchip_platdata *pdata,
520664 struct rockchip_eth_dev *dev)
521665 {
....@@ -1064,6 +1208,251 @@
10641208 }
10651209
10661210 #else
1211
+static void rk3528_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata)
1212
+{
1213
+ struct rk3528_grf *grf;
1214
+ unsigned char bgs[1] = {0};
1215
+
1216
+ enum {
1217
+ RK3528_MACPHY_ENABLE_MASK = BIT(1),
1218
+ RK3528_MACPHY_DISENABLE = BIT(1),
1219
+ RK3528_MACPHY_ENABLE = 0,
1220
+ RK3528_MACPHY_XMII_SEL_MASK = GENMASK(6, 5),
1221
+ RK3528_MACPHY_XMII_SEL = BIT(6),
1222
+ RK3528_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7),
1223
+ RK3528_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)),
1224
+ RK3528_MACPHY_PHY_ID_MASK = GENMASK(14, 10),
1225
+ RK3528_MACPHY_PHY_ID = BIT(11),
1226
+ };
1227
+
1228
+ enum {
1229
+ RK3528_MACPHY_BGS_MASK = GENMASK(3, 0),
1230
+ };
1231
+
1232
+#if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP)
1233
+ struct udevice *dev;
1234
+ u32 regs[2] = {0};
1235
+ ofnode node;
1236
+ int ret = 0;
1237
+
1238
+ /* retrieve the device */
1239
+ if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE))
1240
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
1241
+ DM_GET_DRIVER(rockchip_efuse),
1242
+ &dev);
1243
+ else
1244
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
1245
+ DM_GET_DRIVER(rockchip_otp),
1246
+ &dev);
1247
+ if (!ret) {
1248
+ node = dev_read_subnode(dev, "macphy-bgs");
1249
+ if (ofnode_valid(node)) {
1250
+ if (!ofnode_read_u32_array(node, "reg", regs, 2)) {
1251
+ /* read the bgs from the efuses */
1252
+ ret = misc_read(dev, regs[0], &bgs, 1);
1253
+ if (ret) {
1254
+ printf("read bgs from efuse/otp failed, ret=%d\n",
1255
+ ret);
1256
+ bgs[0] = 0;
1257
+ }
1258
+ }
1259
+ }
1260
+ }
1261
+#endif
1262
+
1263
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1264
+
1265
+ reset_assert(&pdata->phy_reset);
1266
+ udelay(20);
1267
+ rk_clrsetreg(&grf->macphy_con0,
1268
+ RK3528_MACPHY_ENABLE_MASK |
1269
+ RK3528_MACPHY_XMII_SEL_MASK |
1270
+ RK3528_MACPHY_24M_CLK_SEL_MASK |
1271
+ RK3528_MACPHY_PHY_ID_MASK,
1272
+ RK3528_MACPHY_ENABLE |
1273
+ RK3528_MACPHY_XMII_SEL |
1274
+ RK3528_MACPHY_24M_CLK_SEL_24M |
1275
+ RK3528_MACPHY_PHY_ID);
1276
+
1277
+ rk_clrsetreg(&grf->macphy_con1,
1278
+ RK3528_MACPHY_BGS_MASK,
1279
+ bgs[0]);
1280
+ udelay(20);
1281
+ reset_deassert(&pdata->phy_reset);
1282
+ udelay(30 * 1000);
1283
+}
1284
+
1285
+static void rk3528_set_to_rmii(struct gmac_rockchip_platdata *pdata)
1286
+{
1287
+ unsigned int clk_mode;
1288
+ struct rk3528_grf *grf;
1289
+
1290
+ enum {
1291
+ RK3528_GMAC0_CLK_RMII_MODE_SHIFT = 0x1,
1292
+ RK3528_GMAC0_CLK_RMII_MODE_MASK = BIT(1),
1293
+ RK3528_GMAC0_CLK_RMII_MODE = 0x1,
1294
+ };
1295
+
1296
+ enum {
1297
+ RK3528_GMAC1_CLK_RMII_MODE_SHIFT = 0x8,
1298
+ RK3528_GMAC1_CLK_RMII_MODE_MASK = BIT(8),
1299
+ RK3528_GMAC1_CLK_RMII_MODE = 0x1,
1300
+ };
1301
+
1302
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1303
+
1304
+ if (pdata->bus_id == 1) {
1305
+ clk_mode = RK3528_GMAC1_CLK_RMII_MODE << RK3528_GMAC1_CLK_RMII_MODE_SHIFT;
1306
+ rk_clrsetreg(&grf->gmac1_con1, RK3528_GMAC1_CLK_RMII_MODE_MASK, clk_mode);
1307
+ } else {
1308
+ clk_mode = RK3528_GMAC0_CLK_RMII_MODE << RK3528_GMAC0_CLK_RMII_MODE_SHIFT;
1309
+ rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_MODE_MASK, clk_mode);
1310
+ }
1311
+}
1312
+
1313
+static void rk3528_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
1314
+{
1315
+ unsigned int rx_enable;
1316
+ unsigned int rx_delay;
1317
+ struct rk3528_grf *grf;
1318
+
1319
+ enum {
1320
+ RK3528_GMAC1_RGMII_MODE_SHIFT = 0x8,
1321
+ RK3528_GMAC1_RGMII_MODE_MASK = BIT(8),
1322
+ RK3528_GMAC1_RGMII_MODE = 0x0,
1323
+
1324
+ RK3528_GMAC1_TXCLK_DLY_ENA_MASK = BIT(14),
1325
+ RK3528_GMAC1_TXCLK_DLY_ENA_DISABLE = 0,
1326
+ RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE = BIT(14),
1327
+
1328
+ RK3528_GMAC1_RXCLK_DLY_ENA_MASK = BIT(15),
1329
+ RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE = 0,
1330
+ RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE = BIT(15),
1331
+ };
1332
+
1333
+ enum {
1334
+ RK3528_GMAC1_RX_DL_CFG_SHIFT = 0x8,
1335
+ RK3528_GMAC1_RX_DL_CFG_MASK = GENMASK(15, 8),
1336
+
1337
+ RK3528_GMAC1_TX_DL_CFG_SHIFT = 0x0,
1338
+ RK3528_GMAC1_TX_DL_CFG_MASK = GENMASK(7, 0),
1339
+ };
1340
+
1341
+ if (!pdata->bus_id)
1342
+ return;
1343
+
1344
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1345
+
1346
+ if (pdata->rx_delay < 0) {
1347
+ rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE;
1348
+ rx_delay = 0;
1349
+ } else {
1350
+ rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE;
1351
+ rx_delay = pdata->rx_delay << RK3528_GMAC1_RX_DL_CFG_SHIFT;
1352
+ }
1353
+
1354
+ rk_clrsetreg(&grf->gmac1_con0,
1355
+ RK3528_GMAC1_TXCLK_DLY_ENA_MASK |
1356
+ RK3528_GMAC1_RXCLK_DLY_ENA_MASK |
1357
+ RK3528_GMAC1_RGMII_MODE_MASK,
1358
+ rx_enable | RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE |
1359
+ (RK3528_GMAC1_RGMII_MODE << RK3528_GMAC1_RGMII_MODE_SHIFT));
1360
+
1361
+ rk_clrsetreg(&grf->gmac1_con1,
1362
+ RK3528_GMAC1_RX_DL_CFG_MASK |
1363
+ RK3528_GMAC1_TX_DL_CFG_MASK,
1364
+ (pdata->tx_delay << RK3528_GMAC1_TX_DL_CFG_SHIFT) |
1365
+ rx_delay);
1366
+}
1367
+
1368
+static void rk3562_set_to_rmii(struct gmac_rockchip_platdata *pdata)
1369
+{
1370
+ struct rk3562_grf *grf;
1371
+ unsigned int mode;
1372
+
1373
+ enum {
1374
+ RK3562_GMAC0_RMII_MODE_SHIFT = 0x5,
1375
+ RK3562_GMAC0_RMII_MODE_MASK = BIT(5),
1376
+ RK3562_GMAC0_RMII_MODE = 0x1,
1377
+ };
1378
+
1379
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1380
+
1381
+ if (!pdata->bus_id) {
1382
+ mode = RK3562_GMAC0_RMII_MODE << RK3562_GMAC0_RMII_MODE_SHIFT;
1383
+ rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RMII_MODE_MASK, mode);
1384
+ }
1385
+}
1386
+
1387
+static void rk3562_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
1388
+{
1389
+ struct rk3562_grf *grf;
1390
+ struct rk3562_ioc *ioc;
1391
+ unsigned int rx_enable;
1392
+ unsigned int rx_delay;
1393
+
1394
+ enum {
1395
+ RK3562_GMAC0_RGMII_MODE_SHIFT = 0x5,
1396
+ RK3562_GMAC0_RGMII_MODE_MASK = BIT(5),
1397
+ RK3562_GMAC0_RGMII_MODE = 0x0,
1398
+
1399
+ RK3562_GMAC0_TXCLK_DLY_ENA_MASK = BIT(0),
1400
+ RK3562_GMAC0_TXCLK_DLY_ENA_DISABLE = 0,
1401
+ RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE = BIT(0),
1402
+
1403
+ RK3562_GMAC0_RXCLK_DLY_ENA_MASK = BIT(1),
1404
+ RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE = 0,
1405
+ RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE = BIT(1),
1406
+ };
1407
+
1408
+ enum {
1409
+ RK3562_GMAC0_RX_DL_CFG_SHIFT = 0x8,
1410
+ RK3562_GMAC0_RX_DL_CFG_MASK = GENMASK(15, 8),
1411
+
1412
+ RK3562_GMAC0_TX_DL_CFG_SHIFT = 0x0,
1413
+ RK3562_GMAC0_TX_DL_CFG_MASK = GENMASK(7, 0),
1414
+ };
1415
+
1416
+ if (pdata->bus_id)
1417
+ return;
1418
+
1419
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1420
+ ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC);
1421
+
1422
+ rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RGMII_MODE_MASK,
1423
+ RK3562_GMAC0_RGMII_MODE << RK3562_GMAC0_RGMII_MODE_SHIFT);
1424
+
1425
+ if (pdata->rx_delay < 0) {
1426
+ rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE;
1427
+ rx_delay = 0;
1428
+ } else {
1429
+ rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE;
1430
+ rx_delay = pdata->rx_delay << RK3562_GMAC0_RX_DL_CFG_SHIFT;
1431
+ }
1432
+
1433
+ rk_clrsetreg(&ioc->mac0_io_con1,
1434
+ RK3562_GMAC0_TXCLK_DLY_ENA_MASK |
1435
+ RK3562_GMAC0_RXCLK_DLY_ENA_MASK,
1436
+ rx_enable | RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE);
1437
+
1438
+ rk_clrsetreg(&ioc->mac0_io_con0,
1439
+ RK3562_GMAC0_RX_DL_CFG_MASK |
1440
+ RK3562_GMAC0_TX_DL_CFG_MASK,
1441
+ (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) |
1442
+ rx_delay);
1443
+
1444
+ rk_clrsetreg(&ioc->mac1_io_con1,
1445
+ RK3562_GMAC0_TXCLK_DLY_ENA_MASK |
1446
+ RK3562_GMAC0_RXCLK_DLY_ENA_MASK,
1447
+ rx_enable | RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE);
1448
+
1449
+ rk_clrsetreg(&ioc->mac1_io_con0,
1450
+ RK3562_GMAC0_RX_DL_CFG_MASK |
1451
+ RK3562_GMAC0_TX_DL_CFG_MASK,
1452
+ (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) |
1453
+ rx_delay);
1454
+}
1455
+
10671456 static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata)
10681457 {
10691458 struct rk3568_grf *grf;
....@@ -1438,6 +1827,86 @@
14381827 #endif
14391828
14401829 #ifdef CONFIG_DWC_ETH_QOS
1830
+static void rk3528_set_clock_selection(struct gmac_rockchip_platdata *pdata)
1831
+{
1832
+ struct rk3528_grf *grf;
1833
+ unsigned int val;
1834
+
1835
+ enum {
1836
+ RK3528_GMAC1_CLK_SELET_SHIFT = 0x12,
1837
+ RK3528_GMAC1_CLK_SELET_MASK = BIT(12),
1838
+ RK3528_GMAC1_CLK_SELET_CRU = 0,
1839
+ RK3528_GMAC1_CLK_SELET_IO = BIT(12),
1840
+ };
1841
+
1842
+ if (!pdata->bus_id)
1843
+ return;
1844
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1845
+
1846
+ val = pdata->clock_input ? RK3528_GMAC1_CLK_SELET_IO :
1847
+ RK3528_GMAC1_CLK_SELET_CRU;
1848
+ rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_SELET_MASK, val);
1849
+}
1850
+
1851
+static void rk3562_set_clock_selection(struct gmac_rockchip_platdata *pdata)
1852
+{
1853
+ struct rk3562_grf *grf;
1854
+ struct rk3562_ioc *ioc;
1855
+ unsigned int val;
1856
+
1857
+ enum {
1858
+ RK3562_GMAC0_CLK_SELET_SHIFT = 0x9,
1859
+ RK3562_GMAC0_CLK_SELET_MASK = BIT(9),
1860
+ RK3562_GMAC0_CLK_SELET_CRU = 0,
1861
+ RK3562_GMAC0_CLK_SELET_IO = BIT(9),
1862
+ };
1863
+
1864
+ enum {
1865
+ RK3562_GMAC1_CLK_SELET_SHIFT = 15,
1866
+ RK3562_GMAC1_CLK_SELET_MASK = BIT(15),
1867
+ RK3562_GMAC1_CLK_SELET_CRU = 0,
1868
+ RK3562_GMAC1_CLK_SELET_IO = BIT(15),
1869
+ };
1870
+
1871
+ enum {
1872
+ RK3562_GMAC0_IO_EXTCLK_SELET_SHIFT = 0x2,
1873
+ RK3562_GMAC0_IO_EXTCLK_SELET_MASK = BIT(2),
1874
+ RK3562_GMAC0_IO_EXTCLK_SELET_CRU = 0,
1875
+ RK3562_GMAC0_IO_EXTCLK_SELET_IO = BIT(2),
1876
+ };
1877
+
1878
+ enum {
1879
+ RK3562_GMAC1_IO_EXTCLK_SELET_SHIFT = 0x3,
1880
+ RK3562_GMAC1_IO_EXTCLK_SELET_MASK = BIT(3),
1881
+ RK3562_GMAC1_IO_EXTCLK_SELET_CRU = 0,
1882
+ RK3562_GMAC1_IO_EXTCLK_SELET_IO = BIT(3),
1883
+ };
1884
+
1885
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1886
+ ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC);
1887
+
1888
+ if (!pdata->bus_id) {
1889
+ val = pdata->clock_input ? RK3562_GMAC0_CLK_SELET_IO :
1890
+ RK3562_GMAC0_CLK_SELET_CRU;
1891
+ rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_SELET_MASK, val);
1892
+ val = pdata->clock_input ? RK3562_GMAC0_IO_EXTCLK_SELET_IO :
1893
+ RK3562_GMAC0_IO_EXTCLK_SELET_CRU;
1894
+ rk_clrsetreg(&ioc->mac1_io_con1,
1895
+ RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val);
1896
+ rk_clrsetreg(&ioc->mac0_io_con1,
1897
+ RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val);
1898
+
1899
+ } else {
1900
+ val = pdata->clock_input ? RK3562_GMAC1_CLK_SELET_IO :
1901
+ RK3562_GMAC1_CLK_SELET_CRU;
1902
+ rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_SELET_MASK, val);
1903
+ val = pdata->clock_input ? RK3562_GMAC1_IO_EXTCLK_SELET_IO :
1904
+ RK3562_GMAC1_IO_EXTCLK_SELET_CRU;
1905
+ rk_clrsetreg(&ioc->mac1_io_con1,
1906
+ RK3562_GMAC1_IO_EXTCLK_SELET_MASK, val);
1907
+ }
1908
+}
1909
+
14411910 static void rk3588_set_clock_selection(struct gmac_rockchip_platdata *pdata)
14421911 {
14431912 struct rk3588_php_grf *php_grf;
....@@ -1701,6 +2170,21 @@
17012170 .set_to_rmii = rv1108_gmac_set_to_rmii,
17022171 };
17032172 #else
2173
+const struct rk_gmac_ops rk3528_gmac_ops = {
2174
+ .fix_mac_speed = rk3528_set_rgmii_speed,
2175
+ .set_to_rgmii = rk3528_set_to_rgmii,
2176
+ .set_to_rmii = rk3528_set_to_rmii,
2177
+ .set_clock_selection = rk3528_set_clock_selection,
2178
+ .integrated_phy_powerup = rk3528_gmac_integrated_phy_powerup,
2179
+};
2180
+
2181
+const struct rk_gmac_ops rk3562_gmac_ops = {
2182
+ .fix_mac_speed = rk3562_set_gmac_speed,
2183
+ .set_to_rgmii = rk3562_set_to_rgmii,
2184
+ .set_to_rmii = rk3562_set_to_rmii,
2185
+ .set_clock_selection = rk3562_set_clock_selection,
2186
+};
2187
+
17042188 const struct rk_gmac_ops rk3568_gmac_ops = {
17052189 .fix_mac_speed = rv1126_set_rgmii_speed,
17062190 .set_to_rgmii = rk3568_set_to_rgmii,
....@@ -1774,6 +2258,16 @@
17742258 .data = (ulong)&rv1108_gmac_ops },
17752259 #endif
17762260 #else
2261
+#ifdef CONFIG_ROCKCHIP_RK3528
2262
+ { .compatible = "rockchip,rk3528-gmac",
2263
+ .data = (ulong)&rk3528_gmac_ops },
2264
+#endif
2265
+
2266
+#ifdef CONFIG_ROCKCHIP_RK3562
2267
+ { .compatible = "rockchip,rk3562-gmac",
2268
+ .data = (ulong)&rk3562_gmac_ops },
2269
+#endif
2270
+
17772271 #ifdef CONFIG_ROCKCHIP_RK3568
17782272 { .compatible = "rockchip,rk3568-gmac",
17792273 .data = (ulong)&rk3568_gmac_ops },
u-boot/drivers/net/phy/rk630phy.c
....@@ -50,6 +50,7 @@
5050 #define REG_PAGE6_CP_CURRENT 0x17
5151 #define REG_PAGE6_ADC_OP_BIAS 0x18
5252 #define REG_PAGE6_RX_DECTOR 0x19
53
+#define REG_PAGE6_TX_MOS_DRV 0x1B
5354 #define REG_PAGE6_AFE_PDCW 0x1c
5455
5556 /* PAGE 8 */
....@@ -201,6 +202,8 @@
201202 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_RX_DECTOR, 0x0408);
202203 /* PHYAFE PDCW optimization */
203204 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_AFE_PDCW, 0x8880);
205
+ /* Add PHY Tx mos drive, reduce power noise/jitter */
206
+ phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_TX_MOS_DRV, 0x888e);
204207
205208 /* Switch to page 8 */
206209 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0800);
u-boot/drivers/nvme/nvme.c
....@@ -6,6 +6,7 @@
66 */
77
88 #include <common.h>
9
+#include <bouncebuf.h>
910 #include <dm.h>
1011 #include <errno.h>
1112 #include <memalign.h>
....@@ -740,13 +741,25 @@
740741 u64 prp2;
741742 u64 total_len = blkcnt << desc->log2blksz;
742743 u64 temp_len = total_len;
744
+ uintptr_t temp_buffer;
743745
744746 u64 slba = blknr;
745747 u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);
746748 u64 total_lbas = blkcnt;
747749
748
- flush_dcache_range((unsigned long)buffer,
749
- (unsigned long)buffer + total_len);
750
+ struct bounce_buffer bb;
751
+ unsigned int bb_flags;
752
+ int ret;
753
+
754
+ if (read)
755
+ bb_flags = GEN_BB_WRITE;
756
+ else
757
+ bb_flags = GEN_BB_READ;
758
+
759
+ ret = bounce_buffer_start(&bb, buffer, total_len, bb_flags);
760
+ if (ret)
761
+ return -ENOMEM;
762
+ temp_buffer = (unsigned long)bb.bounce_buffer;
750763
751764 c.rw.opcode = read ? nvme_cmd_read : nvme_cmd_write;
752765 c.rw.flags = 0;
....@@ -771,24 +784,22 @@
771784 }
772785
773786 if (nvme_setup_prps(dev, &prp2,
774
- lbas << ns->lba_shift, (ulong)buffer))
787
+ lbas << ns->lba_shift, temp_buffer))
775788 return -EIO;
776789 c.rw.slba = cpu_to_le64(slba);
777790 slba += lbas;
778791 c.rw.length = cpu_to_le16(lbas - 1);
779
- c.rw.prp1 = cpu_to_le64((ulong)buffer);
792
+ c.rw.prp1 = cpu_to_le64(temp_buffer);
780793 c.rw.prp2 = cpu_to_le64(prp2);
781794 status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q],
782795 &c, NULL, IO_TIMEOUT);
783796 if (status)
784797 break;
785798 temp_len -= (u32)lbas << ns->lba_shift;
786
- buffer += lbas << ns->lba_shift;
799
+ temp_buffer += lbas << ns->lba_shift;
787800 }
788801
789
- if (read)
790
- invalidate_dcache_range((unsigned long)buffer,
791
- (unsigned long)buffer + total_len);
802
+ bounce_buffer_stop(&bb);
792803
793804 return (total_len - temp_len) >> desc->log2blksz;
794805 }
u-boot/drivers/pci/pcie_dw_rockchip.c
....@@ -18,8 +18,41 @@
1818 #include <asm-generic/gpio.h>
1919 #include <asm/arch-rockchip/clock.h>
2020 #include <linux/iopoll.h>
21
+#include <linux/ioport.h>
2122
2223 DECLARE_GLOBAL_DATA_PTR;
24
+
25
+#define RK_PCIE_DBG 0
26
+
27
+#define __pcie_dev_print_emit(fmt, ...) \
28
+({ \
29
+ printf(fmt, ##__VA_ARGS__); \
30
+})
31
+
32
+#ifdef dev_err
33
+#undef dev_err
34
+#define dev_err(dev, fmt, ...) \
35
+({ \
36
+ if (dev) \
37
+ __pcie_dev_print_emit("%s: " fmt, dev->name, \
38
+ ##__VA_ARGS__); \
39
+})
40
+#endif
41
+
42
+#ifdef dev_info
43
+#undef dev_info
44
+#define dev_info dev_err
45
+#endif
46
+
47
+#ifdef DEBUG
48
+#define dev_dbg dev_err
49
+#else
50
+#define dev_dbg(dev, fmt, ...) \
51
+({ \
52
+ if (0) \
53
+ __dev_printk(7, dev, fmt, ##__VA_ARGS__); \
54
+})
55
+#endif
2356
2457 struct rk_pcie {
2558 struct udevice *dev;
....@@ -62,7 +95,6 @@
6295 #define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
6396 #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
6497 #define PCIE_CLIENT_DBF_EN 0xffff0003
65
-#define RK_PCIE_DBG 0
6698
6799 /* PCI DBICS registers */
68100 #define PCIE_LINK_STATUS_REG 0x80
....@@ -119,6 +151,8 @@
119151 #define LINK_WAIT_MAX_IATU_RETRIES 5
120152 #define LINK_WAIT_IATU 10000
121153
154
+#define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000
155
+
122156 static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
123157 {
124158 if ((uintptr_t)addr & (size - 1)) {
....@@ -165,7 +199,7 @@
165199
166200 ret = rk_pcie_read(base + reg, size, &val);
167201 if (ret)
168
- dev_err(rk_pcie->pci->dev, "Read APB address failed\n");
202
+ dev_err(rk_pcie->dev, "Read APB address failed\n");
169203
170204 return val;
171205 }
....@@ -177,7 +211,7 @@
177211
178212 ret = rk_pcie_write(base + reg, size, val);
179213 if (ret)
180
- dev_err(rk_pcie->pci->dev, "Write APB address failed\n");
214
+ dev_err(rk_pcie->dev, "Write APB address failed\n");
181215 }
182216
183217 static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg)
....@@ -272,6 +306,10 @@
272306 val = readl(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
273307 val |= PORT_LOGIC_SPEED_CHANGE;
274308 writel(val, rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
309
+
310
+ /* Disable BAR0 BAR1 */
311
+ writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 0 * 4);
312
+ writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 1 * 4);
275313
276314 rk_pcie_dbi_write_enable(rk_pcie, false);
277315 }
....@@ -469,10 +507,10 @@
469507 #if RK_PCIE_DBG
470508 u32 loop;
471509
472
- dev_info(rk_pcie->dev, "ltssm = 0x%x\n",
510
+ dev_err(rk_pcie->dev, "ltssm = 0x%x\n",
473511 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
474512 for (loop = 0; loop < 64; loop++)
475
- dev_info(rk_pcie->dev, "fifo_status = 0x%x\n",
513
+ dev_err(rk_pcie->dev, "fifo_status = 0x%x\n",
476514 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS));
477515 #endif
478516 }
....@@ -641,17 +679,18 @@
641679 struct rk_pcie *priv = dev_get_priv(dev);
642680 u32 max_link_speed;
643681 int ret;
682
+ struct resource res;
644683
645
- priv->dbi_base = (void *)dev_read_addr_index(dev, 0);
646
- if (!priv->dbi_base)
684
+ ret = dev_read_resource_byname(dev, "pcie-dbi", &res);
685
+ if (ret)
647686 return -ENODEV;
648
-
687
+ priv->dbi_base = (void *)(res.start);
649688 dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base);
650689
651
- priv->apb_base = (void *)dev_read_addr_index(dev, 1);
652
- if (!priv->apb_base)
690
+ ret = dev_read_resource_byname(dev, "pcie-apb", &res);
691
+ if (ret)
653692 return -ENODEV;
654
-
693
+ priv->apb_base = (void *)(res.start);
655694 dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base);
656695
657696 ret = gpio_request_by_name(dev, "reset-gpios", 0,
....@@ -771,6 +810,8 @@
771810 };
772811
773812 static const struct udevice_id rockchip_pcie_ids[] = {
813
+ { .compatible = "rockchip,rk3528-pcie" },
814
+ { .compatible = "rockchip,rk3562-pcie" },
774815 { .compatible = "rockchip,rk3568-pcie" },
775816 { .compatible = "rockchip,rk3588-pcie" },
776817 { }
u-boot/drivers/phy/Makefile
....@@ -18,3 +18,5 @@
1818 obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
1919 obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
2020 obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o
21
+
22
+CFLAGS_phy-rockchip-inno-usb2.o := -Wno-error=unused-function -Wno-error=unused-const-variable -Wunused-const-variable=0
u-boot/drivers/phy/phy-rockchip-inno-usb2.c
....@@ -149,6 +149,7 @@
149149 * primary stage.
150150 * @grf: General Register Files register base.
151151 * @usbgrf_base : USB General Register Files register base.
152
+ * @phy_base: the base address of USB PHY.
152153 * @phy_rst: phy reset control.
153154 * @phy_cfg: phy register configuration, assigned by driver data.
154155 */
....@@ -157,6 +158,7 @@
157158 u8 primary_retries;
158159 struct regmap *grf_base;
159160 struct regmap *usbgrf_base;
161
+ void __iomem *phy_base;
160162 struct udevice *vbus_supply[USB2PHY_NUM_PORTS];
161163 struct reset_ctl phy_rst;
162164 const struct rockchip_usb2phy_cfg *phy_cfg;
....@@ -282,6 +284,11 @@
282284 return POWER_SUPPLY_TYPE_UNKNOWN;
283285 }
284286
287
+#ifdef CONFIG_ROCKCHIP_RK3036
288
+ chg_type = POWER_SUPPLY_TYPE_USB;
289
+ goto out;
290
+#endif
291
+
285292 /* Suspend USB-PHY and put the controller in non-driving mode */
286293 property_enable(base, &port_cfg->phy_sus, true);
287294 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
....@@ -388,36 +395,14 @@
388395 port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
389396
390397 /* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */
391
- property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
398
+ if(rphy->phy_cfg->clkout_ctl.disable)
399
+ property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
392400
393401 /* Reset USB-PHY */
394402 property_enable(base, &port_cfg->phy_sus, true);
395403 udelay(20);
396404 property_enable(base, &port_cfg->phy_sus, false);
397405 mdelay(2);
398
-}
399
-
400
-static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy)
401
-{
402
- struct udevice *parent = phy->dev->parent;
403
- struct rockchip_usb2phy *rphy = dev_get_priv(parent);
404
- const struct rockchip_usb2phy_port_cfg *port_cfg;
405
- struct regmap *base = get_reg_base(rphy);
406
- struct udevice *vbus = NULL;
407
- bool iddig = true;
408
-
409
- if (phy->id == USB2PHY_PORT_HOST) {
410
- vbus = rphy->vbus_supply[USB2PHY_PORT_HOST];
411
- } else if (phy->id == USB2PHY_PORT_OTG) {
412
- port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
413
- if (port_cfg->utmi_iddig.offset) {
414
- iddig = property_enabled(base, &port_cfg->utmi_iddig);
415
- if (!iddig)
416
- vbus = rphy->vbus_supply[USB2PHY_PORT_OTG];
417
- }
418
- }
419
-
420
- return vbus;
421406 }
422407
423408 static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy)
....@@ -492,10 +477,11 @@
492477
493478 static int rockchip_usb2phy_power_on(struct phy *phy)
494479 {
495
- struct udevice *vbus = NULL;
480
+ struct udevice *parent = phy->dev->parent;
481
+ struct rockchip_usb2phy *rphy = dev_get_priv(parent);
482
+ struct udevice *vbus = rphy->vbus_supply[phy->id];
496483 int ret;
497484
498
- vbus = rockchip_usb2phy_check_vbus(phy);
499485 if (vbus) {
500486 ret = regulator_set_enable(vbus, true);
501487 if (ret) {
....@@ -509,10 +495,11 @@
509495
510496 static int rockchip_usb2phy_power_off(struct phy *phy)
511497 {
512
- struct udevice *vbus = NULL;
498
+ struct udevice *parent = phy->dev->parent;
499
+ struct rockchip_usb2phy *rphy = dev_get_priv(parent);
500
+ struct udevice *vbus = rphy->vbus_supply[phy->id];
513501 int ret;
514502
515
- vbus = rockchip_usb2phy_check_vbus(phy);
516503 if (vbus) {
517504 ret = regulator_set_enable(vbus, false);
518505 if (ret) {
....@@ -587,6 +574,11 @@
587574 struct resource res;
588575 u32 reg, index;
589576 int ret;
577
+
578
+ rphy->phy_base = (void __iomem *)dev_read_addr(dev);
579
+ if (IS_ERR(rphy->phy_base)) {
580
+ dev_err(dev, "get the base address of usb phy failed\n");
581
+ }
590582
591583 if (!strncmp(parent->name, "root_driver", 11) &&
592584 dev_read_bool(dev, "rockchip,grf")) {
....@@ -818,6 +810,102 @@
818810 return 0;
819811 }
820812
813
+static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy)
814
+{
815
+ u32 reg;
816
+
817
+ /* Set HS disconnect detect mode to single ended detect mode */
818
+ reg = readl(rphy->phy_base + 0x70);
819
+ writel(reg | BIT(2), rphy->phy_base + 0x70);
820
+
821
+ return 0;
822
+}
823
+
824
+static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy)
825
+{
826
+ u32 reg;
827
+ int ret = 0;
828
+
829
+ if (IS_ERR(rphy->phy_base)) {
830
+ return PTR_ERR(rphy->phy_base);
831
+ }
832
+
833
+ /* Turn off otg port differential receiver in suspend mode */
834
+ reg = readl(rphy->phy_base + 0x30);
835
+ writel(reg & ~BIT(2), rphy->phy_base + 0x30);
836
+
837
+ /* Turn off host port differential receiver in suspend mode */
838
+ reg = readl(rphy->phy_base + 0x0430);
839
+ writel(reg & ~BIT(2), rphy->phy_base + 0x0430);
840
+
841
+ /* Set otg port HS eye height to 400mv(default is 450mv) */
842
+ reg = readl(rphy->phy_base + 0x30);
843
+ reg &= ~GENMASK(6, 4);
844
+ reg |= (0x00 << 4);
845
+ writel(reg, rphy->phy_base + 0x30);
846
+
847
+ /* Set host port HS eye height to 400mv(default is 450mv) */
848
+ reg = readl(rphy->phy_base + 0x430);
849
+ reg &= ~GENMASK(6, 4);
850
+ reg |= (0x00 << 4);
851
+ writel(reg, rphy->phy_base + 0x430);
852
+
853
+ /* Choose the Tx fs/ls data as linestate from TX driver for otg port */
854
+ reg = readl(rphy->phy_base + 0x94);
855
+ reg &= ~GENMASK(6, 3);
856
+ reg |= (0x03 << 3);
857
+ writel(reg, rphy->phy_base + 0x94);
858
+
859
+ /* Turn on output clk of phy*/
860
+ reg = readl(rphy->phy_base + 0x41c);
861
+ reg &= ~GENMASK(7, 2);
862
+ reg |= (0x27 << 2);
863
+ writel(reg, rphy->phy_base + 0x41c);
864
+
865
+ return ret;
866
+}
867
+
868
+static int rk3562_usb2phy_tuning(struct rockchip_usb2phy *rphy)
869
+{
870
+ u32 reg;
871
+ int ret = 0;
872
+
873
+ if (IS_ERR(rphy->phy_base)) {
874
+ return PTR_ERR(rphy->phy_base);
875
+ }
876
+
877
+ /* Turn off differential receiver by default to save power */
878
+ reg = readl(rphy->phy_base + 0x30);
879
+ writel(reg & ~BIT(2), rphy->phy_base + 0x30);
880
+
881
+ reg = readl(rphy->phy_base + 0x0430);
882
+ writel(reg & ~BIT(2), rphy->phy_base + 0x0430);
883
+
884
+ /* Enable pre-emphasis during non-chirp phase */
885
+ reg = readl(rphy->phy_base);
886
+ reg &= ~GENMASK(2, 0);
887
+ reg |= 0x04;
888
+ writel(reg, rphy->phy_base);
889
+
890
+ reg = readl(rphy->phy_base + 0x0400);
891
+ reg &= ~GENMASK(2, 0);
892
+ reg |= 0x04;
893
+ writel(reg, rphy->phy_base + 0x0400);
894
+
895
+ /* Set HS eye height to 425mv(default is 400mv) */
896
+ reg = readl(rphy->phy_base + 0x0030);
897
+ reg &= ~GENMASK(6, 4);
898
+ reg |= (0x05 << 4);
899
+ writel(reg, rphy->phy_base + 0x0030);
900
+
901
+ reg = readl(rphy->phy_base + 0x0430);
902
+ reg &= ~GENMASK(6, 4);
903
+ reg |= (0x05 << 4);
904
+ writel(reg, rphy->phy_base + 0x0430);
905
+
906
+ return ret;
907
+}
908
+
821909 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
822910 {
823911 struct regmap *base = get_reg_base(rphy);
....@@ -902,6 +990,43 @@
902990 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
903991 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
904992 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
993
+ },
994
+ },
995
+ { /* sentinel */ }
996
+};
997
+
998
+static const struct rockchip_usb2phy_cfg rk3036_phy_cfgs[] = {
999
+ {
1000
+ .reg = 0x17c,
1001
+ .num_ports = 2,
1002
+ .clkout_ctl = { 0x017c, 11, 11, 1, 0 },
1003
+ .port_cfgs = {
1004
+ [USB2PHY_PORT_OTG] = {
1005
+ .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 },
1006
+ .bvalid_det_en = { 0x017c, 14, 14, 0, 1 },
1007
+ .bvalid_det_st = { 0x017c, 15, 15, 0, 1 },
1008
+ .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 },
1009
+ .iddig_output = { 0x017c, 10, 10, 0, 1 },
1010
+ .iddig_en = { 0x017c, 9, 9, 0, 1 },
1011
+ .idfall_det_en = { 0x01a0, 2, 2, 0, 1 },
1012
+ .idfall_det_st = { 0x01a0, 3, 3, 0, 1 },
1013
+ .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 },
1014
+ .idrise_det_en = { 0x01a0, 0, 0, 0, 1 },
1015
+ .idrise_det_st = { 0x01a0, 1, 1, 0, 1 },
1016
+ .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 },
1017
+ .ls_det_en = { 0x017c, 12, 12, 0, 1 },
1018
+ .ls_det_st = { 0x017c, 13, 13, 0, 1 },
1019
+ .ls_det_clr = { 0x017c, 13, 13, 0, 1 },
1020
+ .utmi_bvalid = { 0x014c, 5, 5, 0, 1 },
1021
+ .utmi_iddig = { 0x014c, 8, 8, 0, 1 },
1022
+ .utmi_ls = { 0x014c, 7, 6, 0, 1 },
1023
+ },
1024
+ [USB2PHY_PORT_HOST] = {
1025
+ .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 },
1026
+ .ls_det_en = { 0x0194, 14, 14, 0, 1 },
1027
+ .ls_det_st = { 0x0194, 15, 15, 0, 1 },
1028
+ .ls_det_clr = { 0x0194, 15, 15, 0, 1 }
1029
+ }
9051030 },
9061031 },
9071032 { /* sentinel */ }
....@@ -1272,6 +1397,51 @@
12721397 { /* sentinel */ }
12731398 };
12741399
1400
+static const struct rockchip_usb2phy_cfg rv1106_phy_cfgs[] = {
1401
+ {
1402
+ .reg = 0xff3e0000,
1403
+ .num_ports = 1,
1404
+ .phy_tuning = rv1106_usb2phy_tuning,
1405
+ .clkout_ctl = { 0x0058, 4, 4, 1, 0 },
1406
+ .port_cfgs = {
1407
+ [USB2PHY_PORT_OTG] = {
1408
+ .phy_sus = { 0x0050, 8, 0, 0, 0x1d1 },
1409
+ .bvalid_det_en = { 0x0100, 2, 2, 0, 1 },
1410
+ .bvalid_det_st = { 0x0104, 2, 2, 0, 1 },
1411
+ .bvalid_det_clr = { 0x0108, 2, 2, 0, 1 },
1412
+ .iddig_output = { 0x0050, 10, 10, 0, 1 },
1413
+ .iddig_en = { 0x0050, 9, 9, 0, 1 },
1414
+ .idfall_det_en = { 0x0100, 5, 5, 0, 1 },
1415
+ .idfall_det_st = { 0x0104, 5, 5, 0, 1 },
1416
+ .idfall_det_clr = { 0x0108, 5, 5, 0, 1 },
1417
+ .idrise_det_en = { 0x0100, 4, 4, 0, 1 },
1418
+ .idrise_det_st = { 0x0104, 4, 4, 0, 1 },
1419
+ .idrise_det_clr = { 0x0108, 4, 4, 0, 1 },
1420
+ .ls_det_en = { 0x0100, 0, 0, 0, 1 },
1421
+ .ls_det_st = { 0x0104, 0, 0, 0, 1 },
1422
+ .ls_det_clr = { 0x0108, 0, 0, 0, 1 },
1423
+ .utmi_avalid = { 0x0060, 10, 10, 0, 1 },
1424
+ .utmi_bvalid = { 0x0060, 9, 9, 0, 1 },
1425
+ .utmi_iddig = { 0x0060, 6, 6, 0, 1 },
1426
+ .utmi_ls = { 0x0060, 5, 4, 0, 1 },
1427
+ },
1428
+ },
1429
+ .chg_det = {
1430
+ .opmode = { 0x0050, 3, 0, 5, 1 },
1431
+ .cp_det = { 0x0060, 13, 13, 0, 1 },
1432
+ .dcp_det = { 0x0060, 12, 12, 0, 1 },
1433
+ .dp_det = { 0x0060, 14, 14, 0, 1 },
1434
+ .idm_sink_en = { 0x0058, 8, 8, 0, 1 },
1435
+ .idp_sink_en = { 0x0058, 7, 7, 0, 1 },
1436
+ .idp_src_en = { 0x0058, 9, 9, 0, 1 },
1437
+ .rdm_pdwn_en = { 0x0058, 10, 10, 0, 1 },
1438
+ .vdm_src_en = { 0x0058, 12, 12, 0, 1 },
1439
+ .vdp_src_en = { 0x0058, 11, 11, 0, 1 },
1440
+ },
1441
+ },
1442
+ { /* sentinel */ }
1443
+};
1444
+
12751445 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
12761446 {
12771447 .reg = 0x100,
....@@ -1309,6 +1479,110 @@
13091479 .rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 },
13101480 .vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 },
13111481 .vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 },
1482
+ },
1483
+ },
1484
+ { /* sentinel */ }
1485
+};
1486
+
1487
+static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
1488
+ {
1489
+ .reg = 0xffdf0000,
1490
+ .num_ports = 2,
1491
+ .phy_tuning = rk3528_usb2phy_tuning,
1492
+ .port_cfgs = {
1493
+ [USB2PHY_PORT_OTG] = {
1494
+ .phy_sus = { 0x6004c, 8, 0, 0, 0x1d1 },
1495
+ .bvalid_det_en = { 0x60074, 2, 2, 0, 1 },
1496
+ .bvalid_det_st = { 0x60078, 2, 2, 0, 1 },
1497
+ .bvalid_det_clr = { 0x6007c, 2, 2, 0, 1 },
1498
+ .iddig_output = { 0x6004c, 10, 10, 0, 1 },
1499
+ .iddig_en = { 0x6004c, 9, 9, 0, 1 },
1500
+ .idfall_det_en = { 0x60074, 5, 5, 0, 1 },
1501
+ .idfall_det_st = { 0x60078, 5, 5, 0, 1 },
1502
+ .idfall_det_clr = { 0x6007c, 5, 5, 0, 1 },
1503
+ .idrise_det_en = { 0x60074, 4, 4, 0, 1 },
1504
+ .idrise_det_st = { 0x60078, 4, 4, 0, 1 },
1505
+ .idrise_det_clr = { 0x6007c, 4, 4, 0, 1 },
1506
+ .ls_det_en = { 0x60074, 0, 0, 0, 1 },
1507
+ .ls_det_st = { 0x60078, 0, 0, 0, 1 },
1508
+ .ls_det_clr = { 0x6007c, 0, 0, 0, 1 },
1509
+ .utmi_avalid = { 0x6006c, 1, 1, 0, 1 },
1510
+ .utmi_bvalid = { 0x6006c, 0, 0, 0, 1 },
1511
+ .utmi_iddig = { 0x6006c, 6, 6, 0, 1 },
1512
+ .utmi_ls = { 0x6006c, 5, 4, 0, 1 },
1513
+ },
1514
+ [USB2PHY_PORT_HOST] = {
1515
+ .phy_sus = { 0x6005c, 8, 0, 0x1d2, 0x1d1 },
1516
+ .ls_det_en = { 0x60090, 0, 0, 0, 1 },
1517
+ .ls_det_st = { 0x60094, 0, 0, 0, 1 },
1518
+ .ls_det_clr = { 0x60098, 0, 0, 0, 1 },
1519
+ .utmi_ls = { 0x6006c, 13, 12, 0, 1 },
1520
+ .utmi_hstdet = { 0x6006c, 15, 15, 0, 1 }
1521
+ }
1522
+ },
1523
+ .chg_det = {
1524
+ .opmode = { 0x6004c, 3, 0, 5, 1 },
1525
+ .cp_det = { 0x6006c, 19, 19, 0, 1 },
1526
+ .dcp_det = { 0x6006c, 18, 18, 0, 1 },
1527
+ .dp_det = { 0x6006c, 20, 20, 0, 1 },
1528
+ .idm_sink_en = { 0x60058, 1, 1, 0, 1 },
1529
+ .idp_sink_en = { 0x60058, 0, 0, 0, 1 },
1530
+ .idp_src_en = { 0x60058, 2, 2, 0, 1 },
1531
+ .rdm_pdwn_en = { 0x60058, 3, 3, 0, 1 },
1532
+ .vdm_src_en = { 0x60058, 5, 5, 0, 1 },
1533
+ .vdp_src_en = { 0x60058, 4, 4, 0, 1 },
1534
+ },
1535
+ }
1536
+};
1537
+
1538
+static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = {
1539
+ {
1540
+ .reg = 0xff740000,
1541
+ .num_ports = 2,
1542
+ .phy_tuning = rk3562_usb2phy_tuning,
1543
+ .clkout_ctl = { 0x0108, 4, 4, 1, 0 },
1544
+ .port_cfgs = {
1545
+ [USB2PHY_PORT_OTG] = {
1546
+ .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
1547
+ .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
1548
+ .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
1549
+ .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
1550
+ .iddig_output = { 0x0100, 10, 10, 0, 1 },
1551
+ .iddig_en = { 0x0100, 9, 9, 0, 1 },
1552
+ .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
1553
+ .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
1554
+ .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
1555
+ .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
1556
+ .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
1557
+ .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
1558
+ .ls_det_en = { 0x0110, 0, 0, 0, 1 },
1559
+ .ls_det_st = { 0x0114, 0, 0, 0, 1 },
1560
+ .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
1561
+ .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1562
+ .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1563
+ .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
1564
+ .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1565
+ },
1566
+ [USB2PHY_PORT_HOST] = {
1567
+ .phy_sus = { 0x0104, 8, 0, 0x1d2, 0x1d1 },
1568
+ .ls_det_en = { 0x0110, 1, 1, 0, 1 },
1569
+ .ls_det_st = { 0x0114, 1, 1, 0, 1 },
1570
+ .ls_det_clr = { 0x0118, 1, 1, 0, 1 },
1571
+ .utmi_ls = { 0x0120, 17, 16, 0, 1 },
1572
+ .utmi_hstdet = { 0x0120, 19, 19, 0, 1 }
1573
+ }
1574
+ },
1575
+ .chg_det = {
1576
+ .opmode = { 0x0100, 3, 0, 5, 1 },
1577
+ .cp_det = { 0x0120, 24, 24, 0, 1 },
1578
+ .dcp_det = { 0x0120, 23, 23, 0, 1 },
1579
+ .dp_det = { 0x0120, 25, 25, 0, 1 },
1580
+ .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1581
+ .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1582
+ .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1583
+ .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1584
+ .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1585
+ .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
13121586 },
13131587 },
13141588 { /* sentinel */ }
....@@ -1401,6 +1675,8 @@
14011675 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
14021676 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
14031677 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
1678
+ .utmi_avalid = { 0x00c0, 7, 7, 0, 1 },
1679
+ .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 },
14041680 .utmi_iddig = { 0x00c0, 5, 5, 0, 1 },
14051681 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
14061682 }
....@@ -1468,16 +1744,48 @@
14681744 };
14691745
14701746 static const struct udevice_id rockchip_usb2phy_ids[] = {
1747
+#ifdef CONFIG_ROCKCHIP_RK1808
14711748 { .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs },
1749
+#endif
1750
+#ifdef CONFIG_ROCKCHIP_RK3036
1751
+ { .compatible = "rockchip,rk3036-usb2phy", .data = (ulong)&rk3036_phy_cfgs },
1752
+#endif
1753
+#if defined CONFIG_ROCKCHIP_RK3128 || defined CONFIG_ROCKCHIP_RK3126
14721754 { .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs },
1755
+#endif
1756
+#ifdef CONFIG_ROCKCHIP_RK322X
14731757 { .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs },
1758
+#endif
1759
+#ifdef CONFIG_ROCKCHIP_RK3308
14741760 { .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs },
1761
+#endif
1762
+#if defined CONFIG_ROCKCHIP_RK3328 || defined CONFIG_ROCKCHIP_PX30
14751763 { .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs },
1764
+#endif
1765
+#ifdef CONFIG_ROCKCHIP_RK3368
14761766 { .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs },
1767
+#endif
1768
+#ifdef CONFIG_ROCKCHIP_RK3399
14771769 { .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs },
1770
+#endif
1771
+#ifdef CONFIG_ROCKCHIP_RK3528
1772
+ { .compatible = "rockchip,rk3528-usb2phy", .data = (ulong)&rk3528_phy_cfgs },
1773
+#endif
1774
+#ifdef CONFIG_ROCKCHIP_RK3562
1775
+ { .compatible = "rockchip,rk3562-usb2phy", .data = (ulong)&rk3562_phy_cfgs },
1776
+#endif
1777
+#ifdef CONFIG_ROCKCHIP_RK3568
14781778 { .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs },
1779
+#endif
1780
+#ifdef CONFIG_ROCKCHIP_RK3588
14791781 { .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs },
1782
+#endif
1783
+#ifdef CONFIG_ROCKCHIP_RV1106
1784
+ { .compatible = "rockchip,rv1106-usb2phy", .data = (ulong)&rv1106_phy_cfgs },
1785
+#endif
1786
+#ifdef CONFIG_ROCKCHIP_RV1108
14801787 { .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs },
1788
+#endif
14811789 { }
14821790 };
14831791
u-boot/drivers/phy/phy-rockchip-naneng-combphy.c
....@@ -22,7 +22,7 @@
2222 struct rockchip_combphy_priv;
2323
2424 struct combphy_reg {
25
- u16 offset;
25
+ u32 offset;
2626 u16 bitend;
2727 u16 bitstart;
2828 u16 disable;
....@@ -37,6 +37,7 @@
3737 struct combphy_reg pipe_rxterm_set;
3838 struct combphy_reg pipe_txelec_set;
3939 struct combphy_reg pipe_txcomp_set;
40
+ struct combphy_reg pipe_clk_24m;
4041 struct combphy_reg pipe_clk_25m;
4142 struct combphy_reg pipe_clk_100m;
4243 struct combphy_reg pipe_phymode_sel;
....@@ -62,6 +63,7 @@
6263 struct combphy_reg pipe_xpcs_phy_ready;
6364 struct combphy_reg u3otg0_port_en;
6465 struct combphy_reg u3otg1_port_en;
66
+ struct combphy_reg pipe_phy_grf_reset;
6567 };
6668
6769 struct rockchip_combphy_cfg {
....@@ -179,6 +181,7 @@
179181 static int rockchip_combphy_init(struct phy *phy)
180182 {
181183 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
184
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
182185 int ret;
183186
184187 ret = clk_enable(&priv->ref_clk);
....@@ -191,6 +194,9 @@
191194
192195 reset_deassert(&priv->phy_rst);
193196
197
+ if (cfg->pipe_phy_grf_reset.enable)
198
+ param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false);
199
+
194200 return 0;
195201
196202 err_clk:
....@@ -202,9 +208,13 @@
202208 static int rockchip_combphy_exit(struct phy *phy)
203209 {
204210 struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
211
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
205212
206
- clk_disable(&priv->ref_clk);
213
+ if (cfg->pipe_phy_grf_reset.enable)
214
+ param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true);
215
+
207216 reset_assert(&priv->phy_rst);
217
+ clk_disable(&priv->ref_clk);
208218
209219 return 0;
210220 }
....@@ -291,6 +301,215 @@
291301
292302 return rockchip_combphy_parse_dt(udev, priv);
293303 }
304
+
305
+static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
306
+{
307
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
308
+ u32 val;
309
+
310
+ switch (priv->mode) {
311
+ case PHY_TYPE_PCIE:
312
+ /* Set SSC downward spread spectrum */
313
+ val = readl(priv->mmio + 0x18);
314
+ val &= ~GENMASK(5, 4);
315
+ val |= 0x01 << 4;
316
+ writel(val, priv->mmio + 0x18);
317
+
318
+ param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
319
+ param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
320
+ param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
321
+ param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
322
+ break;
323
+ case PHY_TYPE_USB3:
324
+ /* Set SSC downward spread spectrum */
325
+ val = readl(priv->mmio + 0x18);
326
+ val &= ~GENMASK(5, 4);
327
+ val |= 0x01 << 4;
328
+ writel(val, priv->mmio + 0x18);
329
+
330
+ /* Enable adaptive CTLE for USB3.0 Rx */
331
+ val = readl(priv->mmio + 0x200);
332
+ val &= ~GENMASK(17, 17);
333
+ val |= 0x01;
334
+ writel(val, priv->mmio + 0x200);
335
+
336
+ param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
337
+ param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
338
+ param_write(priv->phy_grf, &cfg->usb_mode_set, true);
339
+ break;
340
+ default:
341
+ dev_err(priv->dev, "incompatible PHY type\n");
342
+ return -EINVAL;
343
+ }
344
+
345
+ param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
346
+ if (priv->mode == PHY_TYPE_PCIE) {
347
+ /* PLL KVCO tuning fine */
348
+ val = readl(priv->mmio + 0x18);
349
+ val &= ~(0x7 << 10);
350
+ val |= 0x2 << 10;
351
+ writel(val, priv->mmio + 0x18);
352
+
353
+ /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */
354
+ val = readl(priv->mmio + 0x108);
355
+ val &= ~(0x7f7);
356
+ val |= 0x4f0;
357
+ writel(val, priv->mmio + 0x108);
358
+ }
359
+
360
+ return 0;
361
+}
362
+
363
+static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
364
+ /* pipe-phy-grf */
365
+ .pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 },
366
+ .usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 },
367
+ .pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 },
368
+ .pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 },
369
+ .pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 },
370
+ .pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 },
371
+ .pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 },
372
+ .pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 },
373
+ .pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 },
374
+ .pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 },
375
+ .pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 },
376
+ .pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 },
377
+ .con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 },
378
+ .con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 },
379
+ .con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 },
380
+ .con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 },
381
+ /* pipe-grf */
382
+ .u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 },
383
+};
384
+
385
+static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
386
+ .grfcfg = &rk3528_combphy_grfcfgs,
387
+ .combphy_cfg = rk3528_combphy_cfg,
388
+};
389
+
390
+static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
391
+{
392
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
393
+ u32 val;
394
+
395
+ switch (priv->mode) {
396
+ case PHY_TYPE_PCIE:
397
+ /* Set SSC downward spread spectrum */
398
+ val = readl(priv->mmio + (0x1f << 2));
399
+ val &= ~GENMASK(5, 4);
400
+ val |= 0x01 << 4;
401
+ writel(val, priv->mmio + 0x7c);
402
+
403
+ param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
404
+ param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
405
+ param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
406
+ param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
407
+ break;
408
+ case PHY_TYPE_USB3:
409
+ /* Set SSC downward spread spectrum */
410
+ val = readl(priv->mmio + (0x1f << 2));
411
+ val &= ~GENMASK(5, 4);
412
+ val |= 0x01 << 4;
413
+ writel(val, priv->mmio + 0x7c);
414
+
415
+ /* Enable adaptive CTLE for USB3.0 Rx */
416
+ val = readl(priv->mmio + (0x0e << 2));
417
+ val &= ~GENMASK(0, 0);
418
+ val |= 0x01;
419
+ writel(val, priv->mmio + (0x0e << 2));
420
+
421
+ /* Set PLL KVCO fine tuning signals */
422
+ val = readl(priv->mmio + (0x20 << 2));
423
+ val &= ~(0x7 << 2);
424
+ val |= 0x2 << 2;
425
+ writel(val, priv->mmio + (0x20 << 2));
426
+
427
+ /* Set PLL LPF R1 to su_trim[10:7]=1001 */
428
+ writel(0x4, priv->mmio + (0xb << 2));
429
+
430
+ /* Set PLL input clock divider 1/2 */
431
+ val = readl(priv->mmio + (0x5 << 2));
432
+ val &= ~(0x3 << 6);
433
+ val |= 0x1 << 6;
434
+ writel(val, priv->mmio + (0x5 << 2));
435
+
436
+ /* Set PLL loop divider */
437
+ writel(0x32, priv->mmio + (0x11 << 2));
438
+
439
+ /* Set PLL KVCO to min and set PLL charge pump current to max */
440
+ writel(0xf0, priv->mmio + (0xa << 2));
441
+
442
+ param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
443
+ param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
444
+ param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
445
+ param_write(priv->phy_grf, &cfg->usb_mode_set, true);
446
+ break;
447
+ default:
448
+ pr_err("%s, phy-type %d\n", __func__, priv->mode);
449
+ return -EINVAL;
450
+ }
451
+
452
+ clk_set_rate(&priv->ref_clk, 100000000);
453
+ param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
454
+
455
+ if (priv->mode == PHY_TYPE_PCIE) {
456
+ /* PLL KVCO tuning fine */
457
+ val = readl(priv->mmio + (0x20 << 2));
458
+ val &= ~(0x7 << 2);
459
+ val |= 0x2 << 2;
460
+ writel(val, priv->mmio + (0x20 << 2));
461
+
462
+ /* Enable controlling random jitter, aka RMJ */
463
+ writel(0x4, priv->mmio + (0xb << 2));
464
+
465
+ val = readl(priv->mmio + (0x5 << 2));
466
+ val &= ~(0x3 << 6);
467
+ val |= 0x1 << 6;
468
+ writel(val, priv->mmio + (0x5 << 2));
469
+
470
+ writel(0x32, priv->mmio + (0x11 << 2));
471
+ writel(0xf0, priv->mmio + (0xa << 2));
472
+ }
473
+
474
+ if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) {
475
+ val = readl(priv->mmio + (0x7 << 2));
476
+ val |= BIT(4);
477
+ writel(val, priv->mmio + (0x7 << 2));
478
+ }
479
+
480
+ return 0;
481
+}
482
+
483
+static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = {
484
+ /* pipe-phy-grf */
485
+ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
486
+ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
487
+ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
488
+ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
489
+ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
490
+ .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
491
+ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
492
+ .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
493
+ .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
494
+ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
495
+ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
496
+ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
497
+ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
498
+ .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
499
+ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
500
+ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
501
+ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
502
+ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
503
+ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
504
+ .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 },
505
+ /* pipe-grf */
506
+ .u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 },
507
+};
508
+
509
+static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = {
510
+ .grfcfg = &rk3562_combphy_grfcfgs,
511
+ .combphy_cfg = rk3562_combphy_cfg,
512
+};
294513
295514 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
296515 {
....@@ -565,6 +784,14 @@
565784
566785 static const struct udevice_id rockchip_combphy_ids[] = {
567786 {
787
+ .compatible = "rockchip,rk3528-naneng-combphy",
788
+ .data = (ulong)&rk3528_combphy_cfgs
789
+ },
790
+ {
791
+ .compatible = "rockchip,rk3562-naneng-combphy",
792
+ .data = (ulong)&rk3562_combphy_cfgs
793
+ },
794
+ {
568795 .compatible = "rockchip,rk3568-naneng-combphy",
569796 .data = (ulong)&rk3568_combphy_cfgs
570797 },
u-boot/drivers/phy/phy-rockchip-samsung-hdptx.c
....@@ -592,9 +592,21 @@
592592 struct phy_configure_opts_dp *dp)
593593 {
594594 u8 lane;
595
+ u32 status;
596
+ int ret;
595597
596598 for (lane = 0; lane < dp->lanes; lane++)
597599 rockchip_hdptx_phy_set_voltage(hdptx, dp, lane);
600
+
601
+ reset_deassert(&hdptx->lane_reset);
602
+
603
+ ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
604
+ status, FIELD_GET(PHY_RDY, status),
605
+ 50, 5000);
606
+ if (ret) {
607
+ dev_err(hdptx->dev, "timeout waiting for phy_rdy\n");
608
+ return ret;
609
+ }
598610
599611 return 0;
600612 }
....@@ -676,17 +688,6 @@
676688
677689 regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN,
678690 FIELD_PREP(LANE_EN, GENMASK(dp->lanes - 1, 0)));
679
-
680
- reset_deassert(&hdptx->lane_reset);
681
- udelay(10);
682
-
683
- ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
684
- status, FIELD_GET(PHY_RDY, status),
685
- 50, 1000);
686
- if (ret) {
687
- dev_err(hdptx->dev, "timeout waiting for phy_rdy\n");
688
- return ret;
689
- }
690691
691692 return 0;
692693 }
u-boot/drivers/phy/phy-rockchip-usbdp.c
....@@ -549,14 +549,15 @@
549549 return 0;
550550 }
551551
552
-static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, const struct device_node *np)
552
+static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct udevice *dev)
553553 {
554
+ const struct device_node *np = ofnode_to_np(dev->node);
554555 struct property *prop;
555556 int ret, i, len, num_lanes;
556557
557558 prop = of_find_property(np, "rockchip,dp-lane-mux", &len);
558559 if (!prop) {
559
- dev_dbg(udphy->dev, "failed to find dp lane mux, following dp alt mode\n");
560
+ dev_dbg(dev, "failed to find dp lane mux, following dp alt mode\n");
560561 udphy->mode = UDPHY_MODE_USB;
561562 return 0;
562563 }
....@@ -564,13 +565,13 @@
564565 num_lanes = len / sizeof(u32);
565566
566567 if (num_lanes != 2 && num_lanes != 4) {
567
- dev_err(udphy->dev, "invalid number of lane mux\n");
568
+ dev_err(dev, "invalid number of lane mux\n");
568569 return -EINVAL;
569570 }
570571
571572 ret = of_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes);
572573 if (ret) {
573
- dev_err(udphy->dev, "get dp lane mux failed\n");
574
+ dev_err(dev, "get dp lane mux failed\n");
574575 return -EINVAL;
575576 }
576577
....@@ -578,7 +579,7 @@
578579 int j;
579580
580581 if (udphy->dp_lane_sel[i] > 3) {
581
- dev_err(udphy->dev, "lane mux between 0 and 3, exceeding the range\n");
582
+ dev_err(dev, "lane mux between 0 and 3, exceeding the range\n");
582583 return -EINVAL;
583584 }
584585
....@@ -586,22 +587,23 @@
586587
587588 for (j = i + 1; j < num_lanes; j++) {
588589 if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {
589
- dev_err(udphy->dev, "set repeat lane mux value\n");
590
+ dev_err(dev, "set repeat lane mux value\n");
590591 return -EINVAL;
591592 }
592593 }
593594 }
594595
595596 udphy->mode = UDPHY_MODE_DP;
596
- if (num_lanes == 2)
597
+ if (num_lanes == 2) {
597598 udphy->mode |= UDPHY_MODE_USB;
599
+ udphy->flip = udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP ? true : false;
600
+ }
598601
599602 return 0;
600603 }
601604
602605 static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev)
603606 {
604
- const struct device_node *np = ofnode_to_np(dev->node);
605607 enum usb_device_speed maximum_speed;
606608 int ret;
607609
....@@ -645,7 +647,7 @@
645647 }
646648 }
647649
648
- ret = udphy_parse_lane_mux_data(udphy, np);
650
+ ret = udphy_parse_lane_mux_data(udphy, dev);
649651 if (ret)
650652 return ret;
651653
....@@ -947,7 +949,7 @@
947949
948950 dev_for_each_subnode(subnode, parent) {
949951 if (!ofnode_valid(subnode)) {
950
- printf("%s: no subnode for %s", __func__, parent->name);
952
+ printf("%s: no subnode for %s\n", __func__, parent->name);
951953 return -ENXIO;
952954 }
953955
....@@ -1014,14 +1016,14 @@
10141016 val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
10151017 200, 100);
10161018 if (ret)
1017
- dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
1019
+ dev_notice(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
10181020 } else {
10191021 ret = regmap_read_poll_timeout(udphy->pma_regmap,
10201022 TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val,
10211023 val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
10221024 200, 100);
10231025 if (ret)
1024
- dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
1026
+ dev_notice(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
10251027 }
10261028 }
10271029
u-boot/drivers/pinctrl/Kconfig
....@@ -145,14 +145,6 @@
145145 This option is to enable the pinctrl driver for Maxim
146146 MAX96745.
147147
148
-config PINCTRL_MAX96752F
149
- bool "Maxim MAX96752F pinctrl driver"
150
- depends on DM && I2C_MUX_MAX96752F
151
- select PINCONF
152
- help
153
- This option is to enable the pinctrl driver for Maxim
154
- MAX96752F.
155
-
156148 config PINCTRL_MAX96755F
157149 bool "Maxim MAX96755F pinctrl driver"
158150 depends on DM && I2C_MUX_MAX96755F
u-boot/drivers/pinctrl/Makefile
....@@ -24,6 +24,5 @@
2424 obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o
2525 ifndef CONFIG_SPL_BUILD
2626 obj-$(CONFIG_PINCTRL_MAX96745) += pinctrl-max96745.o
27
-obj-$(CONFIG_PINCTRL_MAX96752F) += pinctrl-max96752f.o
2827 obj-$(CONFIG_PINCTRL_MAX96755F) += pinctrl-max96755f.o
2928 endif
u-boot/drivers/pinctrl/pinctrl-max96752f.c
deleted file mode 100644
....@@ -1,491 +0,0 @@
1
-// SPDX-License-Identifier: GPL-2.0+
2
-/*
3
- * (C) Copyright 2022 Rockchip Electronics Co., Ltd
4
- */
5
-
6
-#include <common.h>
7
-#include <dm.h>
8
-#include <dm/pinctrl.h>
9
-#include <errno.h>
10
-#include <i2c.h>
11
-#include <max96752f.h>
12
-
13
-struct config_desc {
14
- u16 reg;
15
- u8 mask;
16
- u8 val;
17
-};
18
-
19
-struct function_desc {
20
- const char *name;
21
- const char **group_names;
22
- int num_group_names;
23
-
24
- u8 gpio_out_dis:1;
25
- u8 gpio_tx_en:1;
26
- u8 gpio_rx_en:1;
27
- u8 oldi:1;
28
- u8 gpio_tx_id;
29
- u8 gpio_rx_id;
30
-};
31
-
32
-struct group_desc {
33
- const char *name;
34
- int *pins;
35
- int num_pins;
36
-
37
- const struct config_desc *configs;
38
- int num_configs;
39
-};
40
-
41
-struct pin_desc {
42
- unsigned number;
43
- const char *name;
44
-};
45
-
46
-static const struct pin_desc max96752f_pins[] = {
47
- {0, "oldi"},
48
- {1, "gpio1"},
49
- {2, "gpio2"},
50
- {3, "gpio3"},
51
- {4, "gpio4"},
52
- {5, "gpio5"},
53
- {6, "gpio6"},
54
- {7, "gpio7"},
55
- {8, "gpio8"},
56
- {9, "gpio9"},
57
- {10, "gpio10"},
58
- {11, "gpio11"},
59
- {12, "gpio12"},
60
- {13, "gpio13"},
61
- {14, "gpio14"},
62
- {15, "gpio15"},
63
-};
64
-
65
-static int oldi_pins[] = {0};
66
-static int gpio1_pins[] = {1};
67
-static int gpio2_pins[] = {2};
68
-static int gpio3_pins[] = {3};
69
-static int gpio4_pins[] = {4};
70
-static int gpio5_pins[] = {5};
71
-static int gpio6_pins[] = {6};
72
-static int gpio7_pins[] = {7};
73
-static int gpio8_pins[] = {8};
74
-static int gpio9_pins[] = {9};
75
-static int gpio10_pins[] = {10};
76
-static int gpio11_pins[] = {11};
77
-static int gpio12_pins[] = {12};
78
-static int gpio13_pins[] = {13};
79
-static int gpio14_pins[] = {14};
80
-static int gpio15_pins[] = {15};
81
-
82
-#define GROUP_DESC(nm) \
83
-{ \
84
- .name = #nm, \
85
- .pins = nm ## _pins, \
86
- .num_pins = ARRAY_SIZE(nm ## _pins), \
87
-}
88
-
89
-#define GROUP_DESC_CONFIG(nm) \
90
-{ \
91
- .name = #nm, \
92
- .pins = nm ## _pins, \
93
- .num_pins = ARRAY_SIZE(nm ## _pins), \
94
- .configs = nm ## _configs, \
95
- .num_configs = ARRAY_SIZE(nm ## _configs), \
96
-}
97
-
98
-static const struct config_desc gpio6_configs[] = {
99
- { 0x0002, AUD_TX_EN, 0 },
100
-};
101
-
102
-static const struct config_desc gpio7_configs[] = {
103
- { 0x0002, AUD_TX_EN, 0 },
104
-};
105
-
106
-static const struct config_desc gpio8_configs[] = {
107
- { 0x0002, AUD_TX_EN, 0 },
108
-};
109
-
110
-static const struct config_desc gpio11_configs[] = {
111
- { 0x0140, AUD_RX_EN, 0 },
112
-};
113
-
114
-static const struct config_desc gpio12_configs[] = {
115
- { 0x0140, AUD_RX_EN, 0 },
116
-};
117
-
118
-static const struct config_desc gpio13_configs[] = {
119
- { 0x0140, AUD_RX_EN, 0 },
120
-};
121
-
122
-static const struct group_desc max96752f_groups[] = {
123
- GROUP_DESC(oldi),
124
- GROUP_DESC(gpio1),
125
- GROUP_DESC(gpio2),
126
- GROUP_DESC(gpio3),
127
- GROUP_DESC(gpio4),
128
- GROUP_DESC(gpio5),
129
- GROUP_DESC_CONFIG(gpio6),
130
- GROUP_DESC_CONFIG(gpio7),
131
- GROUP_DESC_CONFIG(gpio8),
132
- GROUP_DESC(gpio9),
133
- GROUP_DESC(gpio10),
134
- GROUP_DESC_CONFIG(gpio11),
135
- GROUP_DESC_CONFIG(gpio12),
136
- GROUP_DESC_CONFIG(gpio13),
137
- GROUP_DESC(gpio14),
138
- GROUP_DESC(gpio15),
139
-};
140
-
141
-static const char *gpio_groups[] = {
142
- "reserved", "gpio1", "gpio2", "gpio3", "gpio4",
143
- "gpio5", "gpio6", "gpio7", "gpio8", "gpio9",
144
- "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
145
- "gpio15",
146
-};
147
-
148
-static const char *oldi_groups[] = { "oldi" };
149
-
150
-#define FUNCTION_DESC_GPIO_RX(id) \
151
-{ \
152
- .name = "GPIO_RX_"#id, \
153
- .group_names = gpio_groups, \
154
- .num_group_names = ARRAY_SIZE(gpio_groups), \
155
- .gpio_rx_en = 1, \
156
- .gpio_rx_id = id, \
157
-} \
158
-
159
-#define FUNCTION_DESC_GPIO_TX(id) \
160
-{ \
161
- .name = "GPIO_TX_"#id, \
162
- .group_names = gpio_groups, \
163
- .num_group_names = ARRAY_SIZE(gpio_groups), \
164
- .gpio_out_dis = 1, \
165
- .gpio_tx_en = 1, \
166
- .gpio_tx_id = id \
167
-} \
168
-
169
-#define FUNCTION_DESC_GPIO() \
170
-{ \
171
- .name = "GPIO", \
172
- .group_names = gpio_groups, \
173
- .num_group_names = ARRAY_SIZE(gpio_groups), \
174
-} \
175
-
176
-#define FUNCTION_DESC_OLDI() \
177
-{ \
178
- .name = "OLDI", \
179
- .group_names = oldi_groups, \
180
- .num_group_names = ARRAY_SIZE(oldi_groups), \
181
- .oldi = 1, \
182
-} \
183
-
184
-static const struct function_desc max96752f_functions[] = {
185
- FUNCTION_DESC_GPIO_TX(0),
186
- FUNCTION_DESC_GPIO_TX(1),
187
- FUNCTION_DESC_GPIO_TX(2),
188
- FUNCTION_DESC_GPIO_TX(3),
189
- FUNCTION_DESC_GPIO_TX(4),
190
- FUNCTION_DESC_GPIO_TX(5),
191
- FUNCTION_DESC_GPIO_TX(6),
192
- FUNCTION_DESC_GPIO_TX(7),
193
- FUNCTION_DESC_GPIO_TX(8),
194
- FUNCTION_DESC_GPIO_TX(9),
195
- FUNCTION_DESC_GPIO_TX(10),
196
- FUNCTION_DESC_GPIO_TX(11),
197
- FUNCTION_DESC_GPIO_TX(12),
198
- FUNCTION_DESC_GPIO_TX(13),
199
- FUNCTION_DESC_GPIO_TX(14),
200
- FUNCTION_DESC_GPIO_TX(15),
201
- FUNCTION_DESC_GPIO_TX(16),
202
- FUNCTION_DESC_GPIO_TX(17),
203
- FUNCTION_DESC_GPIO_TX(18),
204
- FUNCTION_DESC_GPIO_TX(19),
205
- FUNCTION_DESC_GPIO_TX(20),
206
- FUNCTION_DESC_GPIO_TX(21),
207
- FUNCTION_DESC_GPIO_TX(22),
208
- FUNCTION_DESC_GPIO_TX(23),
209
- FUNCTION_DESC_GPIO_TX(24),
210
- FUNCTION_DESC_GPIO_TX(25),
211
- FUNCTION_DESC_GPIO_TX(26),
212
- FUNCTION_DESC_GPIO_TX(27),
213
- FUNCTION_DESC_GPIO_TX(28),
214
- FUNCTION_DESC_GPIO_TX(29),
215
- FUNCTION_DESC_GPIO_TX(30),
216
- FUNCTION_DESC_GPIO_TX(31),
217
- FUNCTION_DESC_GPIO_RX(0),
218
- FUNCTION_DESC_GPIO_RX(1),
219
- FUNCTION_DESC_GPIO_RX(2),
220
- FUNCTION_DESC_GPIO_RX(3),
221
- FUNCTION_DESC_GPIO_RX(4),
222
- FUNCTION_DESC_GPIO_RX(5),
223
- FUNCTION_DESC_GPIO_RX(6),
224
- FUNCTION_DESC_GPIO_RX(7),
225
- FUNCTION_DESC_GPIO_RX(8),
226
- FUNCTION_DESC_GPIO_RX(9),
227
- FUNCTION_DESC_GPIO_RX(10),
228
- FUNCTION_DESC_GPIO_RX(11),
229
- FUNCTION_DESC_GPIO_RX(12),
230
- FUNCTION_DESC_GPIO_RX(13),
231
- FUNCTION_DESC_GPIO_RX(14),
232
- FUNCTION_DESC_GPIO_RX(15),
233
- FUNCTION_DESC_GPIO_RX(16),
234
- FUNCTION_DESC_GPIO_RX(17),
235
- FUNCTION_DESC_GPIO_RX(18),
236
- FUNCTION_DESC_GPIO_RX(19),
237
- FUNCTION_DESC_GPIO_RX(20),
238
- FUNCTION_DESC_GPIO_RX(21),
239
- FUNCTION_DESC_GPIO_RX(22),
240
- FUNCTION_DESC_GPIO_RX(23),
241
- FUNCTION_DESC_GPIO_RX(24),
242
- FUNCTION_DESC_GPIO_RX(25),
243
- FUNCTION_DESC_GPIO_RX(26),
244
- FUNCTION_DESC_GPIO_RX(27),
245
- FUNCTION_DESC_GPIO_RX(28),
246
- FUNCTION_DESC_GPIO_RX(29),
247
- FUNCTION_DESC_GPIO_RX(30),
248
- FUNCTION_DESC_GPIO_RX(31),
249
- FUNCTION_DESC_GPIO(),
250
- FUNCTION_DESC_OLDI(),
251
-};
252
-
253
-static int max96752f_get_pins_count(struct udevice *dev)
254
-{
255
- return ARRAY_SIZE(max96752f_pins);
256
-}
257
-
258
-static const char *max96752f_get_pin_name(struct udevice *dev,
259
- unsigned selector)
260
-{
261
- return max96752f_pins[selector].name;
262
-}
263
-
264
-static int max96752f_pinctrl_get_groups_count(struct udevice *dev)
265
-{
266
- return ARRAY_SIZE(max96752f_groups);
267
-}
268
-
269
-static const char *max96752f_pinctrl_get_group_name(struct udevice *dev,
270
- unsigned selector)
271
-{
272
- return max96752f_groups[selector].name;
273
-}
274
-
275
-static int max96752f_pinctrl_get_functions_count(struct udevice *dev)
276
-{
277
- return ARRAY_SIZE(max96752f_functions);
278
-}
279
-
280
-static const char *max96752f_pinctrl_get_function_name(struct udevice *dev,
281
- unsigned selector)
282
-{
283
- return max96752f_functions[selector].name;
284
-}
285
-
286
-static int max96752f_pinmux_set(struct udevice *dev, unsigned group_selector,
287
- unsigned func_selector)
288
-{
289
- const struct group_desc *grp = &max96752f_groups[group_selector];
290
- const struct function_desc *func = &max96752f_functions[func_selector];
291
- int i, ret;
292
-
293
- if (func->oldi)
294
- return 0;
295
-
296
- for (i = 0; i < grp->num_configs; i++) {
297
- const struct config_desc *config = &grp->configs[i];
298
-
299
- ret = dm_i2c_reg_clrset(dev->parent, config->reg, config->mask,
300
- config->val);
301
- if (ret < 0)
302
- return ret;
303
- }
304
-
305
- for (i = 0; i < grp->num_pins; i++) {
306
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(grp->pins[i]),
307
- GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN,
308
- FIELD_PREP(GPIO_OUT_DIS, func->gpio_out_dis) |
309
- FIELD_PREP(GPIO_RX_EN, func->gpio_rx_en) |
310
- FIELD_PREP(GPIO_TX_EN, func->gpio_tx_en));
311
- if (ret < 0)
312
- return ret;
313
-
314
- if (func->gpio_tx_en) {
315
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_B_REG(grp->pins[i]),
316
- GPIO_TX_ID,
317
- FIELD_PREP(GPIO_TX_ID, func->gpio_tx_id));
318
- if (ret < 0)
319
- return ret;
320
- }
321
-
322
- if (func->gpio_rx_en) {
323
- ret = dm_i2c_reg_clrset(dev->parent,
324
- GPIO_C_REG(grp->pins[i]),
325
- GPIO_RX_ID,
326
- FIELD_PREP(GPIO_RX_ID, func->gpio_rx_id));
327
- if (ret < 0)
328
- return ret;
329
- }
330
- }
331
-
332
- return 0;
333
-}
334
-
335
-#define PIN_CONFIG_OLDI_SPL_EN (PIN_CONFIG_END + 1)
336
-#define PIN_CONFIG_OLDI_SWAP_AB (PIN_CONFIG_END + 2)
337
-
338
-static const struct pinconf_param max96752f_pinconf_params[] = {
339
- { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
340
- { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 },
341
- { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
342
- { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 40000 },
343
- { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 40000 },
344
- { "output-low", PIN_CONFIG_OUTPUT, 0 },
345
- { "output-high", PIN_CONFIG_OUTPUT, 1 },
346
- { "oldi-spl-en", PIN_CONFIG_OLDI_SPL_EN, 0 },
347
- { "oldi-swap-ab", PIN_CONFIG_OLDI_SWAP_AB, 0 },
348
-};
349
-
350
-static int max96752f_pinconf_set(struct udevice *dev, unsigned int pin,
351
- unsigned int param, unsigned int arg)
352
-{
353
- u8 res_cfg;
354
- int ret;
355
-
356
- switch (param) {
357
- case PIN_CONFIG_DRIVE_OPEN_DRAIN:
358
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_B_REG(pin), OUT_TYPE,
359
- FIELD_PREP(OUT_TYPE, 0));
360
- if (ret < 0)
361
- return ret;
362
-
363
- break;
364
- case PIN_CONFIG_DRIVE_PUSH_PULL:
365
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_B_REG(pin), OUT_TYPE,
366
- FIELD_PREP(OUT_TYPE, 1));
367
- if (ret < 0)
368
- return ret;
369
-
370
- break;
371
- case PIN_CONFIG_BIAS_DISABLE:
372
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_C_REG(pin),
373
- PULL_UPDN_SEL,
374
- FIELD_PREP(PULL_UPDN_SEL, 0));
375
- if (ret < 0)
376
- return ret;
377
-
378
- break;
379
- case PIN_CONFIG_BIAS_PULL_UP:
380
- switch (arg) {
381
- case 40000:
382
- res_cfg = 0;
383
- break;
384
- case 1000000:
385
- res_cfg = 1;
386
- break;
387
- default:
388
- return -EINVAL;
389
- }
390
-
391
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(pin), RES_CFG,
392
- FIELD_PREP(RES_CFG, res_cfg));
393
- if (ret < 0)
394
- return ret;
395
-
396
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_C_REG(pin),
397
- PULL_UPDN_SEL,
398
- FIELD_PREP(PULL_UPDN_SEL, 1));
399
- if (ret < 0)
400
- return ret;
401
-
402
- break;
403
- case PIN_CONFIG_BIAS_PULL_DOWN:
404
- switch (arg) {
405
- case 40000:
406
- res_cfg = 0;
407
- break;
408
- case 1000000:
409
- res_cfg = 1;
410
- break;
411
- default:
412
- return -EINVAL;
413
- }
414
-
415
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(pin), RES_CFG,
416
- FIELD_PREP(RES_CFG, res_cfg));
417
- if (ret < 0)
418
- return ret;
419
-
420
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_C_REG(pin),
421
- PULL_UPDN_SEL,
422
- FIELD_PREP(PULL_UPDN_SEL, 2));
423
- if (ret < 0)
424
- return ret;
425
-
426
- break;
427
- case PIN_CONFIG_OUTPUT:
428
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(pin),
429
- GPIO_OUT_DIS | GPIO_OUT,
430
- FIELD_PREP(GPIO_OUT_DIS, 0) |
431
- FIELD_PREP(GPIO_OUT, arg));
432
- if (ret < 0)
433
- return ret;
434
-
435
- break;
436
- case PIN_CONFIG_OLDI_SPL_EN:
437
- if (pin > 0)
438
- return -EINVAL;
439
-
440
- ret = dm_i2c_reg_clrset(dev->parent, OLDI_REG(1),
441
- OLDI_SPL_EN | OLDI_SPL_POL,
442
- FIELD_PREP(OLDI_SPL_EN, 1) |
443
- FIELD_PREP(OLDI_SPL_POL, 0));
444
- if (ret < 0)
445
- return ret;
446
-
447
- break;
448
- case PIN_CONFIG_OLDI_SWAP_AB:
449
- if (pin > 0)
450
- return -EINVAL;
451
-
452
- ret = dm_i2c_reg_clrset(dev->parent, OLDI_REG(1), OLDI_SWAP_AB,
453
- FIELD_PREP(OLDI_SWAP_AB, 1));
454
- if (ret < 0)
455
- return ret;
456
-
457
- break;
458
- default:
459
- dev_err(dev, "unsupported configuration parameter %u\n", param);
460
- return -ENOTSUPP;
461
- }
462
-
463
- return 0;
464
-}
465
-
466
-static const struct pinctrl_ops max96752f_pinctrl_ops = {
467
- .get_pins_count = max96752f_get_pins_count,
468
- .get_pin_name = max96752f_get_pin_name,
469
- .get_groups_count = max96752f_pinctrl_get_groups_count,
470
- .get_group_name = max96752f_pinctrl_get_group_name,
471
- .get_functions_count = max96752f_pinctrl_get_functions_count,
472
- .get_function_name = max96752f_pinctrl_get_function_name,
473
- .set_state = pinctrl_generic_set_state,
474
- .pinmux_set = max96752f_pinmux_set,
475
- .pinmux_group_set = max96752f_pinmux_set,
476
- .pinconf_num_params = ARRAY_SIZE(max96752f_pinconf_params),
477
- .pinconf_params = max96752f_pinconf_params,
478
- .pinconf_set = max96752f_pinconf_set,
479
-};
480
-
481
-static const struct udevice_id max96752f_pinctrl_of_match[] = {
482
- { .compatible = "maxim,max96752f-pinctrl" },
483
- { }
484
-};
485
-
486
-U_BOOT_DRIVER(max96752f_pinctrl) = {
487
- .name = "pinctrl-max96752f",
488
- .id = UCLASS_PINCTRL,
489
- .of_match = max96752f_pinctrl_of_match,
490
- .ops = &max96752f_pinctrl_ops,
491
-};
u-boot/drivers/pinctrl/rockchip/Makefile
....@@ -12,6 +12,8 @@
1212 #obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
1313 #obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
1414 #obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
15
+obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o
16
+obj-$(CONFIG_ROCKCHIP_RK3562) += pinctrl-rk3562.o
1517 obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
1618 obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o
1719 obj-$(CONFIG_ROCKCHIP_RV1106) += pinctrl-rv1106.o
u-boot/drivers/pinctrl/rockchip/pinctrl-rk3528.c
....@@ -0,0 +1,313 @@
1
+// SPDX-License-Identifier: GPL-2.0+
2
+/*
3
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
4
+ */
5
+
6
+#include <common.h>
7
+#include <dm.h>
8
+#include <dm/pinctrl.h>
9
+#include <regmap.h>
10
+#include <syscon.h>
11
+
12
+#include "pinctrl-rockchip.h"
13
+
14
+static int rk3528_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
15
+{
16
+ struct rockchip_pinctrl_priv *priv = bank->priv;
17
+ int iomux_num = (pin / 8);
18
+ struct regmap *regmap;
19
+ int reg, ret, mask;
20
+ u8 bit;
21
+ u32 data;
22
+
23
+ debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
24
+
25
+ regmap = priv->regmap_base;
26
+ reg = bank->iomux[iomux_num].offset;
27
+ if ((pin % 8) >= 4)
28
+ reg += 0x4;
29
+ bit = (pin % 4) * 4;
30
+ mask = 0xf;
31
+
32
+ data = (mask << (bit + 16));
33
+ data |= (mux & mask) << bit;
34
+
35
+ debug("iomux write reg = %x data = %x\n", reg, data);
36
+
37
+ ret = regmap_write(regmap, reg, data);
38
+
39
+ return ret;
40
+}
41
+
42
+#define RK3528_DRV_BITS_PER_PIN 8
43
+#define RK3528_DRV_PINS_PER_REG 2
44
+#define RK3528_DRV_GPIO0_OFFSET 0x100
45
+#define RK3528_DRV_GPIO1_OFFSET 0x20120
46
+#define RK3528_DRV_GPIO2_OFFSET 0x30160
47
+#define RK3528_DRV_GPIO3_OFFSET 0x20190
48
+#define RK3528_DRV_GPIO4_OFFSET 0x101C0
49
+
50
+static void rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
51
+ int pin_num, struct regmap **regmap,
52
+ int *reg, u8 *bit)
53
+{
54
+ struct rockchip_pinctrl_priv *priv = bank->priv;
55
+
56
+ *regmap = priv->regmap_base;
57
+ switch (bank->bank_num) {
58
+ case 0:
59
+ *reg = RK3528_DRV_GPIO0_OFFSET;
60
+ break;
61
+
62
+ case 1:
63
+ *reg = RK3528_DRV_GPIO1_OFFSET;
64
+ break;
65
+
66
+ case 2:
67
+ *reg = RK3528_DRV_GPIO2_OFFSET;
68
+ break;
69
+
70
+ case 3:
71
+ *reg = RK3528_DRV_GPIO3_OFFSET;
72
+ break;
73
+
74
+ case 4:
75
+ *reg = RK3528_DRV_GPIO4_OFFSET;
76
+ break;
77
+
78
+ default:
79
+ *reg = 0;
80
+ dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
81
+ break;
82
+ }
83
+
84
+ *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
85
+ *bit = pin_num % RK3528_DRV_PINS_PER_REG;
86
+ *bit *= RK3528_DRV_BITS_PER_PIN;
87
+}
88
+
89
+static int rk3528_set_drive(struct rockchip_pin_bank *bank,
90
+ int pin_num, int strength)
91
+{
92
+ struct regmap *regmap;
93
+ int reg, ret;
94
+ u32 data;
95
+ u8 bit;
96
+ int drv = (1 << (strength + 1)) - 1;
97
+
98
+ rk3528_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
99
+
100
+ /* enable the write to the equivalent lower bits */
101
+ data = ((1 << RK3528_DRV_BITS_PER_PIN) - 1) << (bit + 16);
102
+ data |= (drv << bit);
103
+ ret = regmap_write(regmap, reg, data);
104
+
105
+ return ret;
106
+}
107
+
108
+#define RK3528_PULL_BITS_PER_PIN 2
109
+#define RK3528_PULL_PINS_PER_REG 8
110
+#define RK3528_PULL_GPIO0_OFFSET 0x200
111
+#define RK3528_PULL_GPIO1_OFFSET 0x20210
112
+#define RK3528_PULL_GPIO2_OFFSET 0x30220
113
+#define RK3528_PULL_GPIO3_OFFSET 0x20230
114
+#define RK3528_PULL_GPIO4_OFFSET 0x10240
115
+
116
+static void rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
117
+ int pin_num, struct regmap **regmap,
118
+ int *reg, u8 *bit)
119
+{
120
+ struct rockchip_pinctrl_priv *priv = bank->priv;
121
+
122
+ *regmap = priv->regmap_base;
123
+ switch (bank->bank_num) {
124
+ case 0:
125
+ *reg = RK3528_PULL_GPIO0_OFFSET;
126
+ break;
127
+
128
+ case 1:
129
+ *reg = RK3528_PULL_GPIO1_OFFSET;
130
+ break;
131
+
132
+ case 2:
133
+ *reg = RK3528_PULL_GPIO2_OFFSET;
134
+ break;
135
+
136
+ case 3:
137
+ *reg = RK3528_PULL_GPIO3_OFFSET;
138
+ break;
139
+
140
+ case 4:
141
+ *reg = RK3528_PULL_GPIO4_OFFSET;
142
+ break;
143
+
144
+ default:
145
+ *reg = 0;
146
+ dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
147
+ break;
148
+ }
149
+
150
+ *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
151
+ *bit = pin_num % RK3528_PULL_PINS_PER_REG;
152
+ *bit *= RK3528_PULL_BITS_PER_PIN;
153
+}
154
+
155
+static int rk3528_set_pull(struct rockchip_pin_bank *bank,
156
+ int pin_num, int pull)
157
+{
158
+ struct regmap *regmap;
159
+ int reg, ret;
160
+ u8 bit, type;
161
+ u32 data;
162
+
163
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
164
+ return -ENOTSUPP;
165
+
166
+ rk3528_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
167
+ type = bank->pull_type[pin_num / 8];
168
+ ret = rockchip_translate_pull_value(type, pull);
169
+ if (ret < 0) {
170
+ debug("unsupported pull setting %d\n", pull);
171
+ return ret;
172
+ }
173
+
174
+ /* enable the write to the equivalent lower bits */
175
+ data = ((1 << RK3528_PULL_BITS_PER_PIN) - 1) << (bit + 16);
176
+
177
+ data |= (ret << bit);
178
+ ret = regmap_write(regmap, reg, data);
179
+
180
+ return ret;
181
+}
182
+
183
+#define RK3528_SMT_BITS_PER_PIN 1
184
+#define RK3528_SMT_PINS_PER_REG 8
185
+#define RK3528_SMT_GPIO0_OFFSET 0x400
186
+#define RK3528_SMT_GPIO1_OFFSET 0x20410
187
+#define RK3528_SMT_GPIO2_OFFSET 0x30420
188
+#define RK3528_SMT_GPIO3_OFFSET 0x20430
189
+#define RK3528_SMT_GPIO4_OFFSET 0x10440
190
+
191
+static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
192
+ int pin_num,
193
+ struct regmap **regmap,
194
+ int *reg, u8 *bit)
195
+{
196
+ struct rockchip_pinctrl_priv *priv = bank->priv;
197
+
198
+ *regmap = priv->regmap_base;
199
+ switch (bank->bank_num) {
200
+ case 0:
201
+ *reg = RK3528_SMT_GPIO0_OFFSET;
202
+ break;
203
+
204
+ case 1:
205
+ *reg = RK3528_SMT_GPIO1_OFFSET;
206
+ break;
207
+
208
+ case 2:
209
+ *reg = RK3528_SMT_GPIO2_OFFSET;
210
+ break;
211
+
212
+ case 3:
213
+ *reg = RK3528_SMT_GPIO3_OFFSET;
214
+ break;
215
+
216
+ case 4:
217
+ *reg = RK3528_SMT_GPIO4_OFFSET;
218
+ break;
219
+
220
+ default:
221
+ *reg = 0;
222
+ dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
223
+ break;
224
+ }
225
+
226
+ *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
227
+ *bit = pin_num % RK3528_SMT_PINS_PER_REG;
228
+ *bit *= RK3528_SMT_BITS_PER_PIN;
229
+ return 0;
230
+}
231
+
232
+static int rk3528_set_schmitt(struct rockchip_pin_bank *bank,
233
+ int pin_num, int enable)
234
+{
235
+ struct regmap *regmap;
236
+ int reg, ret;
237
+ u32 data;
238
+ u8 bit;
239
+
240
+ rk3528_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
241
+
242
+ /* enable the write to the equivalent lower bits */
243
+ data = ((1 << RK3528_SMT_BITS_PER_PIN) - 1) << (bit + 16);
244
+ data |= (enable << bit);
245
+ ret = regmap_write(regmap, reg, data);
246
+
247
+ return ret;
248
+}
249
+
250
+static struct rockchip_pin_bank rk3528_pin_banks[] = {
251
+ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
252
+ IOMUX_WIDTH_4BIT,
253
+ IOMUX_WIDTH_4BIT,
254
+ IOMUX_WIDTH_4BIT,
255
+ IOMUX_WIDTH_4BIT,
256
+ 0, 0, 0, 0),
257
+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
258
+ IOMUX_WIDTH_4BIT,
259
+ IOMUX_WIDTH_4BIT,
260
+ IOMUX_WIDTH_4BIT,
261
+ IOMUX_WIDTH_4BIT,
262
+ 0x20020, 0x20028, 0x20030, 0x20038),
263
+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
264
+ IOMUX_WIDTH_4BIT,
265
+ IOMUX_WIDTH_4BIT,
266
+ IOMUX_WIDTH_4BIT,
267
+ IOMUX_WIDTH_4BIT,
268
+ 0x30040, 0, 0, 0),
269
+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
270
+ IOMUX_WIDTH_4BIT,
271
+ IOMUX_WIDTH_4BIT,
272
+ IOMUX_WIDTH_4BIT,
273
+ IOMUX_WIDTH_4BIT,
274
+ 0x20060, 0x20068, 0x20070, 0),
275
+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
276
+ IOMUX_WIDTH_4BIT,
277
+ IOMUX_WIDTH_4BIT,
278
+ IOMUX_WIDTH_4BIT,
279
+ IOMUX_WIDTH_4BIT,
280
+ 0x10080, 0x10088, 0x10090, 0x10098),
281
+};
282
+
283
+static const struct rockchip_pin_ctrl rk3528_pin_ctrl = {
284
+ .pin_banks = rk3528_pin_banks,
285
+ .nr_banks = ARRAY_SIZE(rk3528_pin_banks),
286
+ .nr_pins = 160,
287
+ .grf_mux_offset = 0x0,
288
+ .set_mux = rk3528_set_mux,
289
+ .set_pull = rk3528_set_pull,
290
+ .set_drive = rk3528_set_drive,
291
+ .set_schmitt = rk3528_set_schmitt,
292
+};
293
+
294
+static const struct udevice_id rk3528_pinctrl_ids[] = {
295
+ {
296
+ .compatible = "rockchip,rk3528-pinctrl",
297
+ .data = (ulong)&rk3528_pin_ctrl
298
+ },
299
+ { }
300
+};
301
+
302
+U_BOOT_DRIVER(pinctrl_rk3528) = {
303
+ .name = "rockchip_rk3528_pinctrl",
304
+ .id = UCLASS_PINCTRL,
305
+ .of_match = rk3528_pinctrl_ids,
306
+ .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
307
+ .ops = &rockchip_pinctrl_ops,
308
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
309
+ .bind = dm_scan_fdt_dev,
310
+#endif
311
+ .probe = rockchip_pinctrl_probe,
312
+};
313
+
u-boot/drivers/pinctrl/rockchip/pinctrl-rk3562.c
....@@ -0,0 +1,324 @@
1
+// SPDX-License-Identifier: GPL-2.0+
2
+/*
3
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
4
+ */
5
+
6
+#include <common.h>
7
+#include <dm.h>
8
+#include <dm/pinctrl.h>
9
+#include <regmap.h>
10
+#include <syscon.h>
11
+
12
+#include "pinctrl-rockchip.h"
13
+
14
+static int rk3562_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
15
+{
16
+ struct rockchip_pinctrl_priv *priv = bank->priv;
17
+ int iomux_num = (pin / 8);
18
+ struct regmap *regmap;
19
+ int reg, ret, mask;
20
+ u8 bit;
21
+ u32 data;
22
+
23
+ debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
24
+
25
+ regmap = priv->regmap_base;
26
+ reg = bank->iomux[iomux_num].offset;
27
+ if ((pin % 8) >= 4)
28
+ reg += 0x4;
29
+ bit = (pin % 4) * 4;
30
+ mask = 0xf;
31
+
32
+ data = (mask << (bit + 16));
33
+ data |= (mux & mask) << bit;
34
+
35
+ /* force jtag m1 */
36
+ if (bank->bank_num == 1) {
37
+ if ((pin == 13) || (pin == 14)) {
38
+ if (mux == 1) {
39
+ regmap_write(regmap, 0x504, 0x10001);
40
+ } else {
41
+ regmap_write(regmap, 0x504, 0x10000);
42
+ }
43
+ }
44
+ }
45
+
46
+ debug("iomux write reg = %x data = %x\n", reg, data);
47
+
48
+ ret = regmap_write(regmap, reg, data);
49
+
50
+ return ret;
51
+}
52
+
53
+#define RK3562_DRV_BITS_PER_PIN 8
54
+#define RK3562_DRV_PINS_PER_REG 2
55
+#define RK3562_DRV_GPIO0_OFFSET 0x20070
56
+#define RK3562_DRV_GPIO1_OFFSET 0x200
57
+#define RK3562_DRV_GPIO2_OFFSET 0x240
58
+#define RK3562_DRV_GPIO3_OFFSET 0x10280
59
+#define RK3562_DRV_GPIO4_OFFSET 0x102C0
60
+
61
+static void rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
62
+ int pin_num, struct regmap **regmap,
63
+ int *reg, u8 *bit)
64
+{
65
+ struct rockchip_pinctrl_priv *priv = bank->priv;
66
+
67
+ *regmap = priv->regmap_base;
68
+ switch (bank->bank_num) {
69
+ case 0:
70
+ *reg = RK3562_DRV_GPIO0_OFFSET;
71
+ break;
72
+
73
+ case 1:
74
+ *reg = RK3562_DRV_GPIO1_OFFSET;
75
+ break;
76
+
77
+ case 2:
78
+ *reg = RK3562_DRV_GPIO2_OFFSET;
79
+ break;
80
+
81
+ case 3:
82
+ *reg = RK3562_DRV_GPIO3_OFFSET;
83
+ break;
84
+
85
+ case 4:
86
+ *reg = RK3562_DRV_GPIO4_OFFSET;
87
+ break;
88
+
89
+ default:
90
+ *reg = 0;
91
+ dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
92
+ break;
93
+ }
94
+
95
+ *reg += ((pin_num / RK3562_DRV_PINS_PER_REG) * 4);
96
+ *bit = pin_num % RK3562_DRV_PINS_PER_REG;
97
+ *bit *= RK3562_DRV_BITS_PER_PIN;
98
+}
99
+
100
+static int rk3562_set_drive(struct rockchip_pin_bank *bank,
101
+ int pin_num, int strength)
102
+{
103
+ struct regmap *regmap;
104
+ int reg, ret;
105
+ u32 data;
106
+ u8 bit;
107
+ int drv = (1 << (strength + 1)) - 1;
108
+
109
+ rk3562_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
110
+
111
+ /* enable the write to the equivalent lower bits */
112
+ data = ((1 << RK3562_DRV_BITS_PER_PIN) - 1) << (bit + 16);
113
+ data |= (drv << bit);
114
+ ret = regmap_write(regmap, reg, data);
115
+
116
+ return ret;
117
+}
118
+
119
+#define RK3562_PULL_BITS_PER_PIN 2
120
+#define RK3562_PULL_PINS_PER_REG 8
121
+#define RK3562_PULL_GPIO0_OFFSET 0x20020
122
+#define RK3562_PULL_GPIO1_OFFSET 0x80
123
+#define RK3562_PULL_GPIO2_OFFSET 0x90
124
+#define RK3562_PULL_GPIO3_OFFSET 0x100A0
125
+#define RK3562_PULL_GPIO4_OFFSET 0x100B0
126
+
127
+static void rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
128
+ int pin_num, struct regmap **regmap,
129
+ int *reg, u8 *bit)
130
+{
131
+ struct rockchip_pinctrl_priv *priv = bank->priv;
132
+
133
+ *regmap = priv->regmap_base;
134
+ switch (bank->bank_num) {
135
+ case 0:
136
+ *reg = RK3562_PULL_GPIO0_OFFSET;
137
+ break;
138
+
139
+ case 1:
140
+ *reg = RK3562_PULL_GPIO1_OFFSET;
141
+ break;
142
+
143
+ case 2:
144
+ *reg = RK3562_PULL_GPIO2_OFFSET;
145
+ break;
146
+
147
+ case 3:
148
+ *reg = RK3562_PULL_GPIO3_OFFSET;
149
+ break;
150
+
151
+ case 4:
152
+ *reg = RK3562_PULL_GPIO4_OFFSET;
153
+ break;
154
+
155
+ default:
156
+ *reg = 0;
157
+ dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
158
+ break;
159
+ }
160
+
161
+ *reg += ((pin_num / RK3562_PULL_PINS_PER_REG) * 4);
162
+ *bit = pin_num % RK3562_PULL_PINS_PER_REG;
163
+ *bit *= RK3562_PULL_BITS_PER_PIN;
164
+}
165
+
166
+static int rk3562_set_pull(struct rockchip_pin_bank *bank,
167
+ int pin_num, int pull)
168
+{
169
+ struct regmap *regmap;
170
+ int reg, ret;
171
+ u8 bit, type;
172
+ u32 data;
173
+
174
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
175
+ return -ENOTSUPP;
176
+
177
+ rk3562_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
178
+ type = bank->pull_type[pin_num / 8];
179
+ ret = rockchip_translate_pull_value(type, pull);
180
+ if (ret < 0) {
181
+ debug("unsupported pull setting %d\n", pull);
182
+ return ret;
183
+ }
184
+
185
+ /* enable the write to the equivalent lower bits */
186
+ data = ((1 << RK3562_PULL_BITS_PER_PIN) - 1) << (bit + 16);
187
+
188
+ data |= (ret << bit);
189
+ ret = regmap_write(regmap, reg, data);
190
+
191
+ return ret;
192
+}
193
+
194
+#define RK3562_SMT_BITS_PER_PIN 2
195
+#define RK3562_SMT_PINS_PER_REG 8
196
+#define RK3562_SMT_GPIO0_OFFSET 0x20030
197
+#define RK3562_SMT_GPIO1_OFFSET 0xC0
198
+#define RK3562_SMT_GPIO2_OFFSET 0xD0
199
+#define RK3562_SMT_GPIO3_OFFSET 0x100E0
200
+#define RK3562_SMT_GPIO4_OFFSET 0x100F0
201
+
202
+static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
203
+ int pin_num,
204
+ struct regmap **regmap,
205
+ int *reg, u8 *bit)
206
+{
207
+ struct rockchip_pinctrl_priv *priv = bank->priv;
208
+
209
+ *regmap = priv->regmap_base;
210
+ switch (bank->bank_num) {
211
+ case 0:
212
+ *reg = RK3562_SMT_GPIO0_OFFSET;
213
+ break;
214
+
215
+ case 1:
216
+ *reg = RK3562_SMT_GPIO1_OFFSET;
217
+ break;
218
+
219
+ case 2:
220
+ *reg = RK3562_SMT_GPIO2_OFFSET;
221
+ break;
222
+
223
+ case 3:
224
+ *reg = RK3562_SMT_GPIO3_OFFSET;
225
+ break;
226
+
227
+ case 4:
228
+ *reg = RK3562_SMT_GPIO4_OFFSET;
229
+ break;
230
+
231
+ default:
232
+ *reg = 0;
233
+ dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
234
+ break;
235
+ }
236
+
237
+ *reg += ((pin_num / RK3562_SMT_PINS_PER_REG) * 4);
238
+ *bit = pin_num % RK3562_SMT_PINS_PER_REG;
239
+ *bit *= RK3562_SMT_BITS_PER_PIN;
240
+
241
+ return 0;
242
+}
243
+
244
+static int rk3562_set_schmitt(struct rockchip_pin_bank *bank,
245
+ int pin_num, int enable)
246
+{
247
+ struct regmap *regmap;
248
+ int reg, ret;
249
+ u32 data;
250
+ u8 bit;
251
+
252
+ rk3562_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
253
+
254
+ /* enable the write to the equivalent lower bits */
255
+ data = ((1 << RK3562_SMT_BITS_PER_PIN) - 1) << (bit + 16);
256
+ data |= (enable << bit);
257
+ ret = regmap_write(regmap, reg, data);
258
+
259
+ return ret;
260
+}
261
+
262
+static struct rockchip_pin_bank rk3562_pin_banks[] = {
263
+ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
264
+ IOMUX_WIDTH_4BIT,
265
+ IOMUX_WIDTH_4BIT,
266
+ IOMUX_WIDTH_4BIT,
267
+ IOMUX_WIDTH_4BIT,
268
+ 0x20000, 0x20008, 0x20010, 0x20018),
269
+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
270
+ IOMUX_WIDTH_4BIT,
271
+ IOMUX_WIDTH_4BIT,
272
+ IOMUX_WIDTH_4BIT,
273
+ IOMUX_WIDTH_4BIT,
274
+ 0, 0x08, 0x10, 0x18),
275
+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
276
+ IOMUX_WIDTH_4BIT,
277
+ IOMUX_WIDTH_4BIT,
278
+ IOMUX_WIDTH_4BIT,
279
+ IOMUX_WIDTH_4BIT,
280
+ 0x20, 0, 0, 0),
281
+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
282
+ IOMUX_WIDTH_4BIT,
283
+ IOMUX_WIDTH_4BIT,
284
+ IOMUX_WIDTH_4BIT,
285
+ IOMUX_WIDTH_4BIT,
286
+ 0x10040, 0x10048, 0x10050, 0x10058),
287
+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4",
288
+ IOMUX_WIDTH_4BIT,
289
+ IOMUX_WIDTH_4BIT,
290
+ 0,
291
+ 0,
292
+ 0x10060, 0x10068, 0, 0),
293
+};
294
+
295
+static const struct rockchip_pin_ctrl rk3562_pin_ctrl = {
296
+ .pin_banks = rk3562_pin_banks,
297
+ .nr_banks = ARRAY_SIZE(rk3562_pin_banks),
298
+ .nr_pins = 144,
299
+ .grf_mux_offset = 0x0,
300
+ .set_mux = rk3562_set_mux,
301
+ .set_pull = rk3562_set_pull,
302
+ .set_drive = rk3562_set_drive,
303
+ .set_schmitt = rk3562_set_schmitt,
304
+};
305
+
306
+static const struct udevice_id rk3562_pinctrl_ids[] = {
307
+ {
308
+ .compatible = "rockchip,rk3562-pinctrl",
309
+ .data = (ulong)&rk3562_pin_ctrl
310
+ },
311
+ { }
312
+};
313
+
314
+U_BOOT_DRIVER(pinctrl_rk3562) = {
315
+ .name = "rockchip_rk3562_pinctrl",
316
+ .id = UCLASS_PINCTRL,
317
+ .of_match = rk3562_pinctrl_ids,
318
+ .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
319
+ .ops = &rockchip_pinctrl_ops,
320
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
321
+ .bind = dm_scan_fdt_dev,
322
+#endif
323
+ .probe = rockchip_pinctrl_probe,
324
+};
u-boot/drivers/power/charge_animation.c
....@@ -499,6 +499,7 @@
499499 struct charge_animation_priv *priv = dev_get_priv(dev);
500500 struct udevice *fg = priv->fg;
501501 int voltage, soc, charging = 1;
502
+ int first_poll_fg = 1;
502503 static int timer_initialized;
503504
504505 voltage = fuel_gauge_get_voltage(fg);
....@@ -506,6 +507,11 @@
506507 return -EINVAL;
507508
508509 while (voltage < pdata->low_power_voltage + 50) {
510
+ if (!first_poll_fg)
511
+ mdelay(FUEL_GAUGE_POLL_MS);
512
+
513
+ first_poll_fg = 0;
514
+
509515 /* Check charger online */
510516 charging = fg_charger_get_chrg_online(dev);
511517 if (charging <= 0) {
u-boot/drivers/power/pmic/rk8xx.c
....@@ -152,7 +152,8 @@
152152 { RK817_PMIC_SYS_CFG1, 0x20, 0x70},
153153 /* Set pmic_sleep as none function */
154154 { RK817_PMIC_SYS_CFG3, 0x00, 0x18 },
155
-
155
+ /* GATE pin function: gate function */
156
+ { RK817_GPIO_INT_CFG, 0x00, 0x20 },
156157 #ifdef CONFIG_DM_CHARGE_DISPLAY
157158 /* Set pmic_int active low */
158159 { RK817_GPIO_INT_CFG, 0x00, 0x02 },
....@@ -408,6 +409,9 @@
408409 val = dev_read_u32_default(dev, "not-save-power-en", 0);
409410 rk8xx->not_save_power_en = val;
410411
412
+ val = dev_read_bool(dev, "vsys-off-shutdown");
413
+ rk8xx->sys_can_sd = val;
414
+
411415 return 0;
412416 }
413417
....@@ -534,6 +538,16 @@
534538 break;
535539 case RK809_ID:
536540 case RK817_ID:
541
+ if (device_is_compatible(dev, "rockchip,rk809") && (priv->variant != RK809_ID)) {
542
+ dev_err(dev, "the dts is RK809, the hardware is RK817\n");
543
+ run_command("download", 0);
544
+ }
545
+
546
+ if (device_is_compatible(dev, "rockchip,rk817") && (priv->variant != RK817_ID)) {
547
+ dev_err(dev, "the dts is RK817, the hardware is RK809\n");
548
+ run_command("download", 0);
549
+ }
550
+
537551 on_source = RK817_ON_SOURCE;
538552 off_source = RK817_OFF_SOURCE;
539553 pwron_key = RK817_PWRON_KEY;
....@@ -541,27 +555,46 @@
541555 lp_act_msk = RK8XX_LP_ACTION_MSK;
542556 init_data = rk817_init_reg;
543557 init_data_num = ARRAY_SIZE(rk817_init_reg);
558
+
559
+ /* whether the system voltage can be shutdown in PWR_off mode */
560
+ if (priv->sys_can_sd) {
561
+ ret = rk8xx_read(dev, RK817_PMIC_CHRG_TERM, &value, 1);
562
+ if (ret)
563
+ return ret;
564
+ value |= 0x80;
565
+ ret = rk8xx_write(dev, RK817_PMIC_CHRG_TERM, &value, 1);
566
+ if (ret)
567
+ return ret;
568
+ } else {
569
+ ret = rk8xx_read(dev, RK817_PMIC_CHRG_TERM, &value, 1);
570
+ if (ret)
571
+ return ret;
572
+ value &= 0x7f;
573
+ ret = rk8xx_write(dev, RK817_PMIC_CHRG_TERM, &value, 1);
574
+ if (ret)
575
+ return ret;
576
+ }
577
+
544578 /* judge whether save the PMIC_POWER_EN register */
545
- if (priv->not_save_power_en)
546
- break;
579
+ if (!priv->not_save_power_en) {
580
+ ret = rk8xx_read(dev, RK817_POWER_EN0, &power_en0, 1);
581
+ if (ret)
582
+ return ret;
583
+ ret = rk8xx_read(dev, RK817_POWER_EN1, &power_en1, 1);
584
+ if (ret)
585
+ return ret;
586
+ ret = rk8xx_read(dev, RK817_POWER_EN2, &power_en2, 1);
587
+ if (ret)
588
+ return ret;
589
+ ret = rk8xx_read(dev, RK817_POWER_EN3, &power_en3, 1);
590
+ if (ret)
591
+ return ret;
547592
548
- ret = rk8xx_read(dev, RK817_POWER_EN0, &power_en0, 1);
549
- if (ret)
550
- return ret;
551
- ret = rk8xx_read(dev, RK817_POWER_EN1, &power_en1, 1);
552
- if (ret)
553
- return ret;
554
- ret = rk8xx_read(dev, RK817_POWER_EN2, &power_en2, 1);
555
- if (ret)
556
- return ret;
557
- ret = rk8xx_read(dev, RK817_POWER_EN3, &power_en3, 1);
558
- if (ret)
559
- return ret;
560
-
561
- value = (power_en0 & 0x0f) | ((power_en1 & 0x0f) << 4);
562
- rk8xx_write(dev, RK817_POWER_EN_SAVE0, &value, 1);
563
- value = (power_en2 & 0x0f) | ((power_en3 & 0x0f) << 4);
564
- rk8xx_write(dev, RK817_POWER_EN_SAVE1, &value, 1);
593
+ value = (power_en0 & 0x0f) | ((power_en1 & 0x0f) << 4);
594
+ rk8xx_write(dev, RK817_POWER_EN_SAVE0, &value, 1);
595
+ value = (power_en2 & 0x0f) | ((power_en3 & 0x0f) << 4);
596
+ rk8xx_write(dev, RK817_POWER_EN_SAVE1, &value, 1);
597
+ }
565598 break;
566599 default:
567600 printf("Unknown PMIC: RK%x!!\n", priv->variant);
u-boot/drivers/power/regulator/fixed.c
....@@ -45,10 +45,12 @@
4545 gpio = &dev_pdata->gpio;
4646 ret = gpio_request_by_name(dev, "gpio", 0, gpio, flags);
4747 if (ret) {
48
- debug("Fixed regulator optional enable GPIO - not found! Error: %d\n",
49
- ret);
50
- if (ret != -ENOENT)
51
- return ret;
48
+ ret = gpio_request_by_name(dev, "gpios", 0, gpio, flags);
49
+ if (ret) {
50
+ debug("Fixed regulator optional enable GPIO - not found! Error: %d\n", ret);
51
+ if (ret != -ENOENT)
52
+ return ret;
53
+ }
5254 }
5355
5456 /* Get optional ramp up delay */
u-boot/drivers/power/regulator/regulator-uclass.c
....@@ -8,7 +8,6 @@
88 #include <common.h>
99 #include <errno.h>
1010 #include <dm.h>
11
-#include <dm/device-internal.h>
1211 #include <dm/uclass-internal.h>
1312 #include <power/pmic.h>
1413 #include <power/regulator.h>
....@@ -413,16 +412,10 @@
413412 if (regulator_name_is_unique(dev, uc_pdata->name))
414413 return 0;
415414
416
-#ifdef CONFIG_USING_KERNEL_DTB
417
- printf("Pre-reloc: %s\n", uc_pdata->name);
418
-
419
- return 0;
420
-#else
421415 debug("'%s' of dev: '%s', has nonunique value: '%s\n",
422416 property, dev->name, uc_pdata->name);
423417
424418 return -EINVAL;
425
-#endif
426419 }
427420
428421 static int regulator_pre_probe(struct udevice *dev)
....@@ -505,90 +498,6 @@
505498 return ret;
506499 }
507500
508
-#ifdef CONFIG_USING_KERNEL_DTB
509
-/*
510
- * Skip probed pre-reloc regulators.
511
- *
512
- * Some regulator like fixed/gpio regultor applies a default output state
513
- * when probed. It maybe reverse the state which was set by the pre-reloc
514
- * regulator. Example: vcc3v3_pcie.
515
- */
516
-int regulators_enable_boot_on(bool verbose)
517
-{
518
- struct dm_regulator_uclass_platdata *uc_pdata;
519
- struct udevice *dev;
520
- struct uclass *uc;
521
- char **pre_probed = NULL;
522
- int i = 0, num = 0;
523
- int ret;
524
- bool skip;
525
-
526
- ret = uclass_get(UCLASS_REGULATOR, &uc);
527
- if (ret)
528
- return ret;
529
-
530
- /* find probed pre-reloc regulators */
531
- for (uclass_find_first_device(UCLASS_REGULATOR, &dev);
532
- dev;
533
- uclass_find_next_device(&dev)) {
534
- if (!(dev->flags & DM_FLAG_KNRL_DTB) &&
535
- (dev->flags & DM_FLAG_ACTIVATED))
536
- num++;
537
- }
538
- if (num) {
539
- pre_probed = calloc(num, sizeof(char *));
540
- if (!pre_probed)
541
- return -ENOMEM;
542
-
543
- for (uclass_find_first_device(UCLASS_REGULATOR, &dev);
544
- dev;
545
- uclass_find_next_device(&dev)) {
546
- if (!(dev->flags & DM_FLAG_KNRL_DTB) &&
547
- (dev->flags & DM_FLAG_ACTIVATED)) {
548
- uc_pdata = dev_get_uclass_platdata(dev);
549
- pre_probed[i++] = (char *)uc_pdata->name;
550
- }
551
- }
552
- }
553
-
554
- /* Skip kernel regulators whose name matches probed pre-reloc regulators */
555
- for (uclass_find_first_device(UCLASS_REGULATOR, &dev);
556
- dev;
557
- uclass_find_next_device(&dev)) {
558
- uc_pdata = dev_get_uclass_platdata(dev);
559
- debug("%s: %s%s\n", __func__, uc_pdata->name,
560
- dev->flags & DM_FLAG_KNRL_DTB ? "" : "*");
561
- if (dev->flags & DM_FLAG_KNRL_DTB) {
562
- for (i = 0, skip = false; i < num; i++) {
563
- if (!strcmp(pre_probed[i], uc_pdata->name)) {
564
- skip = true;
565
- break;
566
- }
567
- }
568
- if (skip)
569
- continue;
570
- }
571
-
572
- /* Probe and init */
573
- ret = device_probe(dev);
574
- if (ret)
575
- continue;
576
- ret = regulator_autoset(dev);
577
- if (ret == -EMEDIUMTYPE)
578
- ret = 0;
579
- if (verbose)
580
- regulator_show(dev, ret);
581
- if (ret == -ENOSYS)
582
- ret = 0;
583
- }
584
-
585
- if (pre_probed)
586
- free(pre_probed);
587
-
588
- return ret;
589
-}
590
-
591
-#else
592501 int regulators_enable_boot_on(bool verbose)
593502 {
594503 struct udevice *dev;
....@@ -613,7 +522,6 @@
613522
614523 return ret;
615524 }
616
-#endif
617525
618526 UCLASS_DRIVER(regulator) = {
619527 .id = UCLASS_REGULATOR,
u-boot/drivers/ram/rockchip/Makefile
....@@ -16,6 +16,8 @@
1616 obj-$(CONFIG_ROCKCHIP_RK3308) += sdram_rv1108_pctl_phy.o sdram_rk3308.o
1717 obj-$(CONFIG_ROCKCHIP_RK3328) += sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
1818 obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
19
+obj-$(CONFIG_ROCKCHIP_RK3528) += sdram_rk3528.o
20
+obj-$(CONFIG_ROCKCHIP_RK3562) += sdram_rk3562.o
1921 obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o
2022 obj-$(CONFIG_ROCKCHIP_RK3588) += sdram_rk3588.o
2123 obj-$(CONFIG_ROCKCHIP_PX30) += sdram_px30.o sdram_pctl_px30.o sdram_phy_px30.o
u-boot/drivers/ram/rockchip/sdram_rk3528.c
....@@ -0,0 +1,21 @@
1
+// SPDX-License-Identifier: GPL-2.0
2
+/*
3
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd.
4
+ */
5
+
6
+#include <common.h>
7
+
8
+#ifdef CONFIG_TPL_BUILD
9
+#ifndef CONFIG_TPL_TINY_FRAMEWORK
10
+#error please defined CONFIG_TPL_TINY_FRAMEWORK for RK3528 !!!
11
+#endif
12
+#endif
13
+
14
+#ifdef CONFIG_TPL_BUILD
15
+
16
+/* return: 0 = success, other = fail */
17
+int sdram_init(void)
18
+{
19
+ return (-1);
20
+}
21
+#endif /* CONFIG_TPL_BUILD */
u-boot/drivers/ram/rockchip/sdram_rk3562.c
....@@ -0,0 +1,31 @@
1
+// SPDX-License-Identifier: GPL-2.0
2
+/*
3
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd.
4
+ */
5
+
6
+#include <common.h>
7
+#include <debug_uart.h>
8
+#include <dm.h>
9
+#include <ram.h>
10
+#include <syscon.h>
11
+#include <asm/io.h>
12
+#include <asm/arch/clock.h>
13
+#include <asm/arch/hardware.h>
14
+#include <asm/arch/rk_atags.h>
15
+#include <asm/arch/cru_rk3562.h>
16
+#include <asm/arch/grf_rk3562.h>
17
+
18
+#ifdef CONFIG_TPL_BUILD
19
+#ifndef CONFIG_TPL_TINY_FRAMEWORK
20
+#error please defined CONFIG_TPL_TINY_FRAMEWORK for RK3562 !!!
21
+#endif
22
+#endif
23
+
24
+#ifdef CONFIG_TPL_BUILD
25
+
26
+/* return: 0 = success, other = fail */
27
+int sdram_init(void)
28
+{
29
+ return (-1);
30
+}
31
+#endif /* CONFIG_TPL_BUILD */
u-boot/drivers/ram/rockchip/sdram_rv1126.c
....@@ -374,6 +374,8 @@
374374 break;
375375 delay--;
376376 }
377
+ if (delay <= 0)
378
+ printascii("ERROR: DPLL lock timeout!\n");
377379
378380 writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode);
379381 }
....@@ -557,11 +559,18 @@
557559 {
558560 void __iomem *phy_base = dram->phy;
559561 u32 fbdiv, prediv, postdiv, postdiv_en;
562
+ int delay = 1000;
560563
561564 if (wait) {
562565 clrbits_le32(PHY_REG(phy_base, 0x53), PHY_PD_DISB);
563
- while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK))
564
- continue;
566
+ while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK)) {
567
+ udelay(1);
568
+ if (delay-- <= 0) {
569
+ printascii("ERROR: phy pll lock timeout!\n");
570
+ while (1)
571
+ ;
572
+ }
573
+ }
565574 } else {
566575 freq /= MHz;
567576 prediv = 1;
....@@ -2484,13 +2493,13 @@
24842493 return 0;
24852494 }
24862495
2487
-static int sdram_init_(struct dram_info *dram,
2488
- struct rv1126_sdram_params *sdram_params, u32 post_init)
2496
+int sdram_init_(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 post_init)
24892497 {
24902498 void __iomem *pctl_base = dram->pctl;
24912499 void __iomem *phy_base = dram->phy;
24922500 u32 ddr4_vref;
24932501 u32 mr_tmp, tmp;
2502
+ int delay = 1000;
24942503
24952504 rkclk_configure_ddr(dram, sdram_params);
24962505
....@@ -2538,8 +2547,14 @@
25382547
25392548 rkclk_ddr_reset(dram, 0, 0, 0, 0);
25402549
2541
- while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0)
2542
- continue;
2550
+ while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0) {
2551
+ udelay(1);
2552
+ if (delay-- <= 0) {
2553
+ printascii("ERROR: Cannot wait dfi_init_done!\n");
2554
+ while (1)
2555
+ ;
2556
+ }
2557
+ }
25432558
25442559 if (sdram_params->base.dramtype == LPDDR3) {
25452560 pctl_write_mr(dram->pctl, 3, 11, lp3_odt_value, LPDDR3);
....@@ -3300,6 +3315,7 @@
33003315 struct rv1126_sdram_params *sdram_params_new;
33013316 void __iomem *pctl_base = dram->pctl;
33023317 void __iomem *phy_base = dram->phy;
3318
+ int delay = 1000;
33033319
33043320 lp_stat = low_power_update(dram, 0);
33053321 sdram_params_new = get_default_sdram_config(freq);
....@@ -3388,8 +3404,14 @@
33883404 (0x0 << ACLK_DDR_UPCTL_EN_SHIFT),
33893405 BUS_SGRF_BASE_ADDR + SGRF_SOC_CON12);
33903406 while ((readl(pctl_base + DDR_PCTL2_DFISTAT) &
3391
- PCTL2_DFI_INIT_COMPLETE) != PCTL2_DFI_INIT_COMPLETE)
3392
- continue;
3407
+ PCTL2_DFI_INIT_COMPLETE) != PCTL2_DFI_INIT_COMPLETE) {
3408
+ udelay(1);
3409
+ if (delay-- <= 0) {
3410
+ printascii("ERROR: Cannot wait DFI_INIT_COMPLETE\n");
3411
+ while (1)
3412
+ ;
3413
+ }
3414
+ }
33933415
33943416 sw_set_req(dram);
33953417 setbits_le32(pctl_base + DDR_PCTL2_MSTR, 0x1 << 29);
u-boot/drivers/rkflash/sfc_nand.c
....@@ -49,6 +49,12 @@
4949 { 0xC2, 0x92, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
5050 /* MX35UF2GE4AC */
5151 { 0xC2, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
52
+ /* MX35UF1GE4AD */
53
+ { 0xC2, 0x96, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
54
+ /* MX35UF2GE4AD */
55
+ { 0xC2, 0xA6, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
56
+ /* MX35UF4GE4AD */
57
+ { 0xC2, 0xB7, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 },
5258
5359 /* GD5F1GQ4UAYIG */
5460 { 0xC8, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
....@@ -93,6 +99,8 @@
9399 { 0xEF, 0xBA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 },
94100 /* W25N512GVEIG */
95101 { 0xEF, 0xAA, 0x20, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 },
102
+ /* W25N01KV */
103
+ { 0xEF, 0xAE, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
96104
97105 /* HYF2GQ4UAACAE */
98106 { 0xC9, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
....@@ -105,7 +113,11 @@
105113 /* HYF2GQ4UHCCAE */
106114 { 0xC9, 0x5A, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
107115 /* HYF4GQ4UAACBE */
108
- { 0xC9, 0xD4, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x4, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 },
116
+ { 0xC9, 0xD4, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0xE, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 },
117
+ /* HYF2GQ4IAACAE */
118
+ { 0xC9, 0x82, 0x00, 4, 0x40, 1, 2048, 0x4C, 20, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
119
+ /* HYF1GQ4IDACAE */
120
+ { 0xC9, 0x81, 0x00, 4, 0x40, 1, 1024, 0x4C, 20, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
109121
110122 /* FS35ND01G-S1 */
111123 { 0xCD, 0xB1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 },
....@@ -124,7 +136,7 @@
124136 /* F35SQA512M */
125137 { 0xCD, 0x70, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
126138 /* F35UQA512M */
127
- { 0xCD, 0x70, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
139
+ { 0xCD, 0x60, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
128140
129141 /* DS35Q1GA-IB */
130142 { 0xE5, 0x71, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
....@@ -142,6 +154,10 @@
142154 { 0xE5, 0xF4, 0x00, 4, 0x40, 2, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 },
143155 /* DS35M1GB-IB */
144156 { 0xE5, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 },
157
+ /* DS35Q12B-IB */
158
+ { 0xE5, 0xF5, 0x00, 4, 0x40, 1, 512, 0x0C, 17, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 },
159
+ /* DS35M12B-IB */
160
+ { 0xE5, 0xA5, 0x00, 4, 0x40, 1, 512, 0x0C, 17, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 },
145161
146162 /* EM73C044VCC-H */
147163 { 0xD5, 0x22, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
....@@ -199,8 +215,16 @@
199215 { 0xEA, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
200216 /* TX25G01 */
201217 { 0xA1, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 },
218
+ /* ANV1GCP0CLG, HYF1GQ4UTXCAE */
219
+ { 0x01, 0x15, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status9 },
220
+ /* S35ML02G3, ANV1GCP0CLG */
221
+ { 0x01, 0x25, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 },
202222 /* S35ML04G3 */
203
- { 0x01, 0x35, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 },
223
+ { 0x01, 0x35, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 },
224
+ /* GSS01GSAK1 */
225
+ { 0x52, 0xBA, 0x13, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
226
+ /* GSS02GSAK1 */
227
+ { 0x52, 0xBA, 0x23, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
204228 };
205229
206230 static struct nand_info *p_nand_info;
u-boot/drivers/rkflash/sfc_nor.c
....@@ -32,10 +32,14 @@
3232 { 0xc86016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 },
3333 /* GD25B512MEYIG */
3434 { 0xc8471A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 },
35
+ /* GD55B01GE */
36
+ { 0xc8471B, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 18, 0, 0 },
3537 /* GD25LQ255E and GD25LQ256C */
3638 { 0xc86019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1D, 16, 9, 0 },
3739 /* GD25LB512MEYIG */
3840 { 0xc8671A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 },
41
+ /* GD55LB01GEFIRR */
42
+ { 0xc8671B, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 18, 0, 0 },
3943
4044 /* W25Q32JV */
4145 { 0xef4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
....@@ -112,6 +116,10 @@
112116 { 0x0b4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 },
113117 /* XT25F16BS */
114118 { 0x0b4015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 },
119
+ /* XT25Q64D */
120
+ { 0x0b6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
121
+ /* XT25Q128D */
122
+ { 0x0b6018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
115123
116124 /* EN25QH64A */
117125 { 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 },
....@@ -124,7 +132,11 @@
124132 /* EN25S64A */
125133 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 },
126134 /* EN25QH256A */
127
- { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 },
135
+ { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 0, 0 },
136
+ /* EN25QX256A */
137
+ { 0x1c7119, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
138
+ /* EN25QX128A */
139
+ { 0x1c7118, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
128140
129141 /* P25Q64H */
130142 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
....@@ -134,8 +146,12 @@
134146 { 0x856015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 },
135147 /* P25Q32SL P25Q32SH-SSH-IT */
136148 { 0x856016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
149
+ /* PY25Q64HA */
150
+ { 0x852017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
137151 /* PY25Q128H */
138152 { 0x852018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
153
+ /* PY25Q256H */
154
+ { 0x852019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
139155
140156 /* ZB25VQ64 */
141157 { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
....@@ -153,6 +169,8 @@
153169 { 0xA14018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
154170 /* FM25Q64-SOB-T-G */
155171 { 0xA14017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
172
+ /* FM25Q256I3 */
173
+ { 0xA14019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
156174
157175 /* FM25Q64A */
158176 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
....@@ -174,6 +192,9 @@
174192
175193 /* BY25Q256FSEIG */
176194 { 0x684919, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
195
+
196
+ /* NM25Q128EVB */
197
+ { 0x522118, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 10, 0 },
177198 };
178199
179200 static int snor_write_en(void)
u-boot/drivers/rng/rockchip_rng.c
....@@ -2,13 +2,14 @@
22 /*
33 * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
44 */
5
+#include <common.h>
6
+#include <clk-uclass.h>
7
+#include <dm.h>
8
+#include <rng.h>
59 #include <asm/arch-rockchip/hardware.h>
610 #include <asm/io.h>
7
-#include <common.h>
8
-#include <dm.h>
911 #include <linux/iopoll.h>
1012 #include <linux/string.h>
11
-#include <rng.h>
1213
1314 #define RK_HW_RNG_MAX 32
1415
....@@ -70,6 +71,27 @@
7071 #define TRNG_v1_VERSION_CODE 0x46BC
7172 /* end of TRNG V1 register define */
7273
74
+/* start of RKRNG register define */
75
+#define RKRNG_CTRL 0x0010
76
+#define RKRNG_CTRL_INST_REQ BIT(0)
77
+#define RKRNG_CTRL_RESEED_REQ BIT(1)
78
+#define RKRNG_CTRL_TEST_REQ BIT(2)
79
+#define RKRNG_CTRL_SW_DRNG_REQ BIT(3)
80
+#define RKRNG_CTRL_SW_TRNG_REQ BIT(4)
81
+
82
+#define RKRNG_STATE 0x0014
83
+#define RKRNG_STATE_INST_ACK BIT(0)
84
+#define RKRNG_STATE_RESEED_ACK BIT(1)
85
+#define RKRNG_STATE_TEST_ACK BIT(2)
86
+#define RKRNG_STATE_SW_DRNG_ACK BIT(3)
87
+#define RKRNG_STATE_SW_TRNG_ACK BIT(4)
88
+
89
+/* DRNG_DATA_0 ~ DNG_DATA_7 */
90
+#define RKRNG_DRNG_DATA_0 0x0070
91
+#define RKRNG_DRNG_DATA_7 0x008C
92
+
93
+/* end of RKRNG register define */
94
+
7395 #define RK_RNG_TIME_OUT 50000 /* max 50ms */
7496
7597 #define trng_write(pdata, pos, val) writel(val, (pdata)->base + (pos))
....@@ -83,7 +105,36 @@
83105 struct rk_rng_platdata {
84106 fdt_addr_t base;
85107 struct rk_rng_soc_data *soc_data;
108
+ struct clk hclk;
86109 };
110
+
111
+static int rk_rng_do_enable_clk(struct udevice *dev, int enable)
112
+{
113
+ struct rk_rng_platdata *pdata = dev_get_priv(dev);
114
+ int ret;
115
+
116
+ if (!pdata->hclk.dev)
117
+ return 0;
118
+
119
+ ret = enable ? clk_enable(&pdata->hclk) : clk_disable(&pdata->hclk);
120
+ if (ret == -ENOSYS || !ret)
121
+ return 0;
122
+
123
+ printf("rk rng: failed to %s clk, ret=%d\n",
124
+ enable ? "enable" : "disable", ret);
125
+
126
+ return ret;
127
+}
128
+
129
+static int rk_rng_enable_clk(struct udevice *dev)
130
+{
131
+ return rk_rng_do_enable_clk(dev, 1);
132
+}
133
+
134
+static int rk_rng_disable_clk(struct udevice *dev)
135
+{
136
+ return rk_rng_do_enable_clk(dev, 0);
137
+}
87138
88139 static int rk_rng_read_regs(fdt_addr_t addr, void *buf, size_t size)
89140 {
....@@ -106,7 +157,7 @@
106157 return 0;
107158 }
108159
109
-static int rk_cryptov1_rng_read(struct udevice *dev, void *data, size_t len)
160
+static int cryptov1_rng_read(struct udevice *dev, void *data, size_t len)
110161 {
111162 struct rk_rng_platdata *pdata = dev_get_priv(dev);
112163 u32 reg = 0;
....@@ -137,7 +188,7 @@
137188 return 0;
138189 }
139190
140
-static int rk_cryptov2_rng_read(struct udevice *dev, void *data, size_t len)
191
+static int cryptov2_rng_read(struct udevice *dev, void *data, size_t len)
141192 {
142193 struct rk_rng_platdata *pdata = dev_get_priv(dev);
143194 u32 reg = 0;
....@@ -171,7 +222,7 @@
171222 return retval;
172223 }
173224
174
-static int rk_trngv1_init(struct udevice *dev)
225
+static int trngv1_init(struct udevice *dev)
175226 {
176227 u32 status, version;
177228 u32 auto_reseed_cnt = 1000;
....@@ -198,7 +249,7 @@
198249 return 0;
199250 }
200251
201
-static int rk_trngv1_rng_read(struct udevice *dev, void *data, size_t len)
252
+static int trngv1_rng_read(struct udevice *dev, void *data, size_t len)
202253 {
203254 struct rk_rng_platdata *pdata = dev_get_priv(dev);
204255 u32 reg = 0;
....@@ -224,6 +275,53 @@
224275 exit:
225276 /* close TRNG */
226277 trng_write(pdata, TRNG_V1_CTRL, TRNG_V1_CTRL_NOP);
278
+
279
+ return retval;
280
+}
281
+
282
+static int rkrng_init(struct udevice *dev)
283
+{
284
+ struct rk_rng_platdata *pdata = dev_get_priv(dev);
285
+ u32 reg = 0;
286
+
287
+ rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff);
288
+
289
+ reg = trng_read(pdata, RKRNG_STATE);
290
+ trng_write(pdata, RKRNG_STATE, reg);
291
+
292
+ return 0;
293
+}
294
+
295
+static int rkrng_rng_read(struct udevice *dev, void *data, size_t len)
296
+{
297
+ struct rk_rng_platdata *pdata = dev_get_priv(dev);
298
+ u32 reg = 0;
299
+ int retval;
300
+
301
+ if (len > RK_HW_RNG_MAX)
302
+ return -EINVAL;
303
+
304
+ rk_rng_enable_clk(dev);
305
+
306
+ reg = RKRNG_CTRL_SW_DRNG_REQ;
307
+
308
+ rk_clrsetreg(pdata->base + RKRNG_CTRL, 0xffff, reg);
309
+
310
+ retval = readl_poll_timeout(pdata->base + RKRNG_STATE, reg,
311
+ (reg & RKRNG_STATE_SW_DRNG_ACK),
312
+ RK_RNG_TIME_OUT);
313
+ if (retval)
314
+ goto exit;
315
+
316
+ trng_write(pdata, RKRNG_STATE, reg);
317
+
318
+ rk_rng_read_regs(pdata->base + RKRNG_DRNG_DATA_0, data, len);
319
+
320
+exit:
321
+ /* close TRNG */
322
+ rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff);
323
+
324
+ rk_rng_disable_clk(dev);
227325
228326 return retval;
229327 }
....@@ -266,6 +364,8 @@
266364 if (!pdata->base)
267365 return -ENOMEM;
268366
367
+ clk_get_by_index(dev, 0, &pdata->hclk);
368
+
269369 return 0;
270370 }
271371
....@@ -282,17 +382,22 @@
282382 return ret;
283383 }
284384
285
-static const struct rk_rng_soc_data rk_cryptov1_soc_data = {
286
- .rk_rng_read = rk_cryptov1_rng_read,
385
+static const struct rk_rng_soc_data cryptov1_soc_data = {
386
+ .rk_rng_read = cryptov1_rng_read,
287387 };
288388
289
-static const struct rk_rng_soc_data rk_cryptov2_soc_data = {
290
- .rk_rng_read = rk_cryptov2_rng_read,
389
+static const struct rk_rng_soc_data cryptov2_soc_data = {
390
+ .rk_rng_read = cryptov2_rng_read,
291391 };
292392
293
-static const struct rk_rng_soc_data rk_trngv1_soc_data = {
294
- .rk_rng_init = rk_trngv1_init,
295
- .rk_rng_read = rk_trngv1_rng_read,
393
+static const struct rk_rng_soc_data trngv1_soc_data = {
394
+ .rk_rng_init = trngv1_init,
395
+ .rk_rng_read = trngv1_rng_read,
396
+};
397
+
398
+static const struct rk_rng_soc_data rkrng_soc_data = {
399
+ .rk_rng_init = rkrng_init,
400
+ .rk_rng_read = rkrng_rng_read,
296401 };
297402
298403 static const struct dm_rng_ops rockchip_rng_ops = {
....@@ -302,15 +407,19 @@
302407 static const struct udevice_id rockchip_rng_match[] = {
303408 {
304409 .compatible = "rockchip,cryptov1-rng",
305
- .data = (ulong)&rk_cryptov1_soc_data,
410
+ .data = (ulong)&cryptov1_soc_data,
306411 },
307412 {
308413 .compatible = "rockchip,cryptov2-rng",
309
- .data = (ulong)&rk_cryptov2_soc_data,
414
+ .data = (ulong)&cryptov2_soc_data,
310415 },
311416 {
312417 .compatible = "rockchip,trngv1",
313
- .data = (ulong)&rk_trngv1_soc_data,
418
+ .data = (ulong)&trngv1_soc_data,
419
+ },
420
+ {
421
+ .compatible = "rockchip,rkrng",
422
+ .data = (ulong)&rkrng_soc_data,
314423 },
315424 {},
316425 };
u-boot/drivers/scsi/scsi.c
....@@ -172,6 +172,7 @@
172172 block_dev->devnum, start, blks, (unsigned long)buffer);
173173 do {
174174 pccb->pdata = (unsigned char *)buf_addr;
175
+ pccb->dma_dir = DMA_FROM_DEVICE;
175176 #ifdef CONFIG_SYS_64BIT_LBA
176177 if (start > SCSI_LBA48_READ) {
177178 unsigned long blocks;
....@@ -247,6 +248,7 @@
247248 __func__, block_dev->devnum, start, blks, (unsigned long)buffer);
248249 do {
249250 pccb->pdata = (unsigned char *)buf_addr;
251
+ pccb->dma_dir = DMA_TO_DEVICE;
250252 if (blks > SCSI_MAX_WRITE_BLK) {
251253 pccb->datalen = (block_dev->blksz *
252254 SCSI_MAX_WRITE_BLK);
....@@ -395,6 +397,7 @@
395397 pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
396398
397399 pccb->datalen = 16;
400
+ pccb->dma_dir = DMA_FROM_DEVICE;
398401 if (scsi_exec(dev, pccb))
399402 return 1;
400403
....@@ -500,6 +503,7 @@
500503 pccb->lun = lun;
501504 pccb->pdata = (unsigned char *)&tempbuff;
502505 pccb->datalen = 512;
506
+ pccb->dma_dir = DMA_FROM_DEVICE;
503507 scsi_setup_inquiry(pccb);
504508 if (scsi_exec(dev, pccb)) {
505509 if (pccb->contr_stat == SCSI_SEL_TIME_OUT) {
u-boot/drivers/spi/rockchip_sfc.c
....@@ -108,6 +108,7 @@
108108 #define SFC_VER_4 0x4
109109 #define SFC_VER_5 0x5
110110 #define SFC_VER_6 0x6
111
+#define SFC_VER_8 0x8
111112
112113 /* Delay line controller resiter */
113114 #define SFC_DLL_CTRL0 0x3C
....@@ -225,6 +226,7 @@
225226 static u32 rockchip_sfc_get_max_dll_cells(struct rockchip_sfc *sfc)
226227 {
227228 switch (rockchip_sfc_get_version(sfc)) {
229
+ case SFC_VER_8:
228230 case SFC_VER_6:
229231 case SFC_VER_5:
230232 return SFC_DLL_CTRL0_DLL_MAX_VER5;
u-boot/drivers/spi/soft_spi.c
....@@ -201,10 +201,8 @@
201201 static int soft_spi_ofdata_to_platdata(struct udevice *dev)
202202 {
203203 struct soft_spi_platdata *plat = dev->platdata;
204
- const void *blob = gd->fdt_blob;
205
- int node = dev_of_offset(dev);
206204
207
- plat->spi_delay_us = fdtdec_get_int(blob, node, "spi-delay-us", 0);
205
+ plat->spi_delay_us = dev_read_u32_default(dev, "spi-delay-us", 0);
208206
209207 return 0;
210208 }
....@@ -216,24 +214,34 @@
216214 int cs_flags, clk_flags;
217215 int ret;
218216
219
- cs_flags = (slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW;
220
- clk_flags = (slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0;
217
+ if (slave) {
218
+ cs_flags = (slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW;
219
+ clk_flags = (slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0;
220
+ } else {
221
+ cs_flags = GPIOD_ACTIVE_LOW;
222
+ clk_flags = 0;
223
+ }
221224
222
- if (gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs,
223
- GPIOD_IS_OUT | cs_flags) ||
224
- gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk,
225
- GPIOD_IS_OUT | clk_flags))
225
+ if (gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs, GPIOD_IS_OUT | cs_flags) ||
226
+ (gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk, GPIOD_IS_OUT | clk_flags) &&
227
+ gpio_request_by_name(dev, "sck-gpios", 0, &plat->sclk, GPIOD_IS_OUT | clk_flags)))
226228 return -EINVAL;
227229
228230 ret = gpio_request_by_name(dev, "gpio-mosi", 0, &plat->mosi,
229231 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
230
- if (ret)
231
- plat->flags |= SPI_MASTER_NO_TX;
232
+ if (ret) {
233
+ if (gpio_request_by_name(dev, "mosi-gpios", 0, &plat->mosi,
234
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE))
235
+ plat->flags |= SPI_MASTER_NO_TX;
236
+ }
232237
233238 ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso,
234239 GPIOD_IS_IN);
235
- if (ret)
236
- plat->flags |= SPI_MASTER_NO_RX;
240
+ if (ret) {
241
+ if (gpio_request_by_name(dev, "miso-gpios", 0, &plat->miso,
242
+ GPIOD_IS_IN))
243
+ plat->flags |= SPI_MASTER_NO_RX;
244
+ }
237245
238246 if ((plat->flags & (SPI_MASTER_NO_RX | SPI_MASTER_NO_TX)) ==
239247 (SPI_MASTER_NO_RX | SPI_MASTER_NO_TX))
u-boot/drivers/thermal/rockchip_thermal.c
....@@ -78,6 +78,7 @@
7878 #define TSADCV2_AUTO_PERIOD_HT 0x6c
7979 #define TSADCV3_AUTO_PERIOD 0x154
8080 #define TSADCV3_AUTO_PERIOD_HT 0x158
81
+#define TSADCV3_Q_MAX 0x210
8182
8283 #define TSADCV2_AUTO_EN BIT(0)
8384 #define TSADCV2_AUTO_EN_MASK BIT(16)
....@@ -88,6 +89,7 @@
8889 #define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
8990
9091 #define TSADCV3_AUTO_Q_SEL_EN BIT(1)
92
+#define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17)
9193
9294 #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
9395 #define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
....@@ -101,6 +103,7 @@
101103 #define TSADCV2_DATA_MASK 0xfff
102104 #define TSADCV3_DATA_MASK 0x3ff
103105 #define TSADCV4_DATA_MASK 0x1ff
106
+#define TSADCV5_DATA_MASK 0x7ff
104107
105108 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
106109 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
....@@ -112,6 +115,14 @@
112115 #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
113116 #define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
114117 #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
118
+#define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */
119
+#define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
120
+#define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */
121
+#define TSADCV12_AUTO_PERIOD_TIME 3000 /* 2.5ms */
122
+#define TSADCV12_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
123
+#define TSADCV12_Q_MAX_VAL 0xfff /* 12bit 4095 */
124
+#define TSADCV9_Q_MAX 0x210
125
+#define TSADCV9_Q_MAX_VAL (0xffff0400 << 0)
115126
116127 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
117128 #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
....@@ -123,7 +134,10 @@
123134 #define PX30_GRF_SOC_CON0 0x0400
124135 #define PX30_GRF_SOC_CON2 0x0408
125136
137
+#define RK3562_GRF_TSADC_CON 0x0580
138
+
126139 #define RK3568_GRF_TSADC_CON 0x0600
140
+#define RK3528_GRF_TSADC_CON 0x40030
127141 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
128142 #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
129143 #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
....@@ -137,9 +151,10 @@
137151 #define GRF_CON_TSADC_CH_INV (0x10001 << 1)
138152 #define PX30S_TSADC_TDC_MODE (0x10001 << 4)
139153
140
-#define MIN_TEMP (-40000)
154
+/* -40 to 125 is reliable, outside the range existed unreliability */
155
+#define MIN_TEMP (-60000)
141156 #define LOWEST_TEMP (-273000)
142
-#define MAX_TEMP (125000)
157
+#define MAX_TEMP (180000)
143158 #define MAX_ENV_TEMP (85000)
144159
145160 #define BASE (1024)
....@@ -208,7 +223,8 @@
208223 };
209224
210225 static const struct tsadc_table rk1808_code_table[] = {
211
- {0, -40000},
226
+ {0, MIN_TEMP},
227
+ {3423, MIN_TEMP},
212228 {3455, -40000},
213229 {3463, -35000},
214230 {3471, -30000},
....@@ -243,11 +259,13 @@
243259 {3709, 115000},
244260 {3718, 120000},
245261 {3726, 125000},
246
- {TSADCV2_DATA_MASK, 125000},
262
+ {3820, MAX_TEMP},
263
+ {TSADCV2_DATA_MASK, MAX_TEMP},
247264 };
248265
249266 static const struct tsadc_table rk3228_code_table[] = {
250
- {0, -40000},
267
+ {0, MIN_TEMP},
268
+ {568, MIN_TEMP},
251269 {588, -40000},
252270 {593, -35000},
253271 {598, -30000},
....@@ -282,11 +300,13 @@
282300 {749, 115000},
283301 {754, 120000},
284302 {760, 125000},
285
- {TSADCV2_DATA_MASK, 125000},
303
+ {821, MAX_TEMP},
304
+ {TSADCV2_DATA_MASK, MAX_TEMP},
286305 };
287306
288307 static const struct tsadc_table rk3288_code_table[] = {
289
- {TSADCV2_DATA_MASK, -40000},
308
+ {TSADCV2_DATA_MASK, MIN_TEMP},
309
+ {3833, MIN_TEMP},
290310 {3800, -40000},
291311 {3792, -35000},
292312 {3783, -30000},
....@@ -321,10 +341,15 @@
321341 {3452, 115000},
322342 {3437, 120000},
323343 {3421, 125000},
344
+ {3350, 145000},
345
+ {3270, 165000},
346
+ {3195, MAX_TEMP},
347
+ {0, MAX_TEMP},
324348 };
325349
326350 static const struct tsadc_table rk3328_code_table[] = {
327
- {0, -40000},
351
+ {0, MIN_TEMP},
352
+ {261, MIN_TEMP},
328353 {296, -40000},
329354 {304, -35000},
330355 {313, -30000},
....@@ -358,11 +383,15 @@
358383 {644, 115000},
359384 {659, 120000},
360385 {675, 125000},
361
- {TSADCV2_DATA_MASK, 125000},
386
+ {745, 145000},
387
+ {825, 165000},
388
+ {900, MAX_TEMP},
389
+ {TSADCV2_DATA_MASK, MAX_TEMP},
362390 };
363391
364392 static const struct tsadc_table rk3368_code_table[] = {
365
- {0, -40000},
393
+ {0, MIN_TEMP},
394
+ {98, MIN_TEMP},
366395 {106, -40000},
367396 {108, -35000},
368397 {110, -30000},
....@@ -397,11 +426,13 @@
397426 {167, 115000},
398427 {169, 120000},
399428 {171, 125000},
400
- {TSADCV3_DATA_MASK, 125000},
429
+ {193, MAX_TEMP},
430
+ {TSADCV3_DATA_MASK, MAX_TEMP},
401431 };
402432
403433 static const struct tsadc_table rk3399_code_table[] = {
404
- {0, -40000},
434
+ {0, MIN_TEMP},
435
+ {368, MIN_TEMP},
405436 {402, -40000},
406437 {410, -35000},
407438 {419, -30000},
....@@ -436,11 +467,95 @@
436467 {668, 115000},
437468 {677, 120000},
438469 {685, 125000},
439
- {TSADCV3_DATA_MASK, 125000},
470
+ {782, MAX_TEMP},
471
+ {TSADCV3_DATA_MASK, MAX_TEMP},
472
+};
473
+
474
+static const struct tsadc_table rk3528_code_table[] = {
475
+ {0, MIN_TEMP},
476
+ {1386, MIN_TEMP},
477
+ {1419, -40000},
478
+ {1427, -35000},
479
+ {1435, -30000},
480
+ {1443, -25000},
481
+ {1452, -20000},
482
+ {1460, -15000},
483
+ {1468, -10000},
484
+ {1477, -5000},
485
+ {1486, 0},
486
+ {1494, 5000},
487
+ {1502, 10000},
488
+ {1510, 15000},
489
+ {1519, 20000},
490
+ {1527, 25000},
491
+ {1535, 30000},
492
+ {1544, 35000},
493
+ {1552, 40000},
494
+ {1561, 45000},
495
+ {1569, 50000},
496
+ {1578, 55000},
497
+ {1586, 60000},
498
+ {1594, 65000},
499
+ {1603, 70000},
500
+ {1612, 75000},
501
+ {1620, 80000},
502
+ {1628, 85000},
503
+ {1637, 90000},
504
+ {1646, 95000},
505
+ {1654, 100000},
506
+ {1662, 105000},
507
+ {1671, 110000},
508
+ {1679, 115000},
509
+ {1688, 120000},
510
+ {1696, 125000},
511
+ {1790, MAX_TEMP},
512
+ {TSADCV5_DATA_MASK, MAX_TEMP},
513
+};
514
+
515
+static const struct tsadc_table rk3562_code_table[] = {
516
+ {0, MIN_TEMP},
517
+ {1385, MIN_TEMP},
518
+ {1419, -40000},
519
+ {1428, -35000},
520
+ {1436, -30000},
521
+ {1445, -25000},
522
+ {1453, -20000},
523
+ {1462, -15000},
524
+ {1470, -10000},
525
+ {1479, -5000},
526
+ {1487, 0},
527
+ {1496, 5000},
528
+ {1504, 10000},
529
+ {1512, 15000},
530
+ {1521, 20000},
531
+ {1529, 25000},
532
+ {1538, 30000},
533
+ {1546, 35000},
534
+ {1555, 40000},
535
+ {1563, 45000},
536
+ {1572, 50000},
537
+ {1580, 55000},
538
+ {1589, 60000},
539
+ {1598, 65000},
540
+ {1606, 70000},
541
+ {1615, 75000},
542
+ {1623, 80000},
543
+ {1632, 85000},
544
+ {1640, 90000},
545
+ {1648, 95000},
546
+ {1657, 100000},
547
+ {1666, 105000},
548
+ {1674, 110000},
549
+ {1682, 115000},
550
+ {1691, 120000},
551
+ {1699, 125000},
552
+ {1793, MAX_TEMP},
553
+ {TSADCV2_DATA_MASK, MAX_TEMP},
440554 };
441555
442556 static const struct tsadc_table rk3568_code_table[] = {
443
- {0, -40000},
557
+ {0, MIN_TEMP},
558
+ {1448, MIN_TEMP},
444559 {1584, -40000},
445560 {1620, -35000},
446561 {1652, -30000},
....@@ -475,16 +590,19 @@
475590 {2636, 115000},
476591 {2672, 120000},
477592 {2704, 125000},
478
- {TSADCV2_DATA_MASK, 125000},
593
+ {3076, MAX_TEMP},
594
+ {TSADCV2_DATA_MASK, MAX_TEMP},
479595 };
480596
481597 static const struct tsadc_table rk3588_code_table[] = {
482
- {0, -40000},
598
+ {0, MIN_TEMP},
599
+ {194, MIN_TEMP},
483600 {215, -40000},
484601 {285, 25000},
485602 {350, 85000},
486603 {395, 125000},
487
- {TSADCV4_DATA_MASK, 125000},
604
+ {455, MAX_TEMP},
605
+ {TSADCV4_DATA_MASK, MAX_TEMP},
488606 };
489607
490608 /*
....@@ -806,6 +924,81 @@
806924 tsadc_init_v2(dev);
807925 if (!IS_ERR(priv->grf))
808926 writel(PX30S_TSADC_TDC_MODE, priv->grf + PX30_GRF_SOC_CON0);
927
+}
928
+
929
+static void tsadc_init_v11(struct udevice *dev)
930
+{
931
+ struct rockchip_thermal_priv *priv = dev_get_priv(dev);
932
+
933
+ writel(TSADCV7_AUTO_PERIOD_TIME, priv->base + TSADCV3_AUTO_PERIOD);
934
+ writel(TSADCV7_AUTO_PERIOD_HT_TIME,
935
+ priv->base + TSADCV3_AUTO_PERIOD_HT);
936
+ writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
937
+ priv->base + TSADCV3_HIGHT_INT_DEBOUNCE);
938
+ writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
939
+ priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
940
+ writel(TSADCV3_Q_MAX_VAL, priv->base + TSADCV3_Q_MAX);
941
+ writel(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
942
+ priv->base + TSADCV2_AUTO_CON);
943
+
944
+ if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
945
+ writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
946
+ TSADCV2_AUTO_TSHUT_POLARITY_MASK,
947
+ priv->base + TSADCV2_AUTO_CON);
948
+ else
949
+ writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
950
+ priv->base + TSADCV2_AUTO_CON);
951
+
952
+ if (!IS_ERR(priv->grf)) {
953
+ writel(RK3568_GRF_TSADC_TSEN,
954
+ priv->grf + RK3528_GRF_TSADC_CON);
955
+ udelay(15);
956
+ writel(RK3568_GRF_TSADC_ANA_REG0,
957
+ priv->grf + RK3528_GRF_TSADC_CON);
958
+ writel(RK3568_GRF_TSADC_ANA_REG1,
959
+ priv->grf + RK3528_GRF_TSADC_CON);
960
+ writel(RK3568_GRF_TSADC_ANA_REG2,
961
+ priv->grf + RK3528_GRF_TSADC_CON);
962
+ udelay(200);
963
+ }
964
+}
965
+
966
+static void tsadc_init_v12(struct udevice *dev)
967
+{
968
+ struct rockchip_thermal_priv *priv = dev_get_priv(dev);
969
+
970
+ writel(TSADCV12_AUTO_PERIOD_TIME,
971
+ priv->base + TSADCV3_AUTO_PERIOD);
972
+ writel(TSADCV12_AUTO_PERIOD_HT_TIME,
973
+ priv->base + TSADCV3_AUTO_PERIOD_HT);
974
+ writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
975
+ priv->base + TSADCV3_HIGHT_INT_DEBOUNCE);
976
+ writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
977
+ priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
978
+ writel(TSADCV12_Q_MAX_VAL,
979
+ priv->base + TSADCV9_Q_MAX);
980
+ writel(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
981
+ priv->base + TSADCV2_AUTO_CON);
982
+ if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
983
+ writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
984
+ TSADCV2_AUTO_TSHUT_POLARITY_MASK,
985
+ priv->base + TSADCV2_AUTO_CON);
986
+ else
987
+ writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
988
+ priv->base + TSADCV2_AUTO_CON);
989
+
990
+ if (!IS_ERR(priv->grf)) {
991
+ writel(RK3568_GRF_TSADC_TSEN,
992
+ priv->grf + RK3562_GRF_TSADC_CON);
993
+ udelay(15);
994
+ writel(RK3568_GRF_TSADC_ANA_REG0,
995
+ priv->grf + RK3562_GRF_TSADC_CON);
996
+ writel(RK3568_GRF_TSADC_ANA_REG1,
997
+ priv->grf + RK3562_GRF_TSADC_CON);
998
+ writel(RK3568_GRF_TSADC_ANA_REG2,
999
+ priv->grf + RK3562_GRF_TSADC_CON);
1000
+ udelay(200);
1001
+ }
8091002 }
8101003
8111004 static int tsadc_get_temp_v2(struct udevice *dev,
....@@ -1381,6 +1574,54 @@
13811574 },
13821575 };
13831576
1577
+static const struct rockchip_tsadc_chip rk3528_tsadc_data = {
1578
+ .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1579
+ .chn_num = 1, /* one channels for tsadc */
1580
+
1581
+ .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via GPIO give PMIC */
1582
+ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1583
+ .tshut_temp = 95000,
1584
+
1585
+ .tsadc_init = tsadc_init_v11,
1586
+ .tsadc_control = tsadc_control_v4,
1587
+ .tsadc_get_temp = tsadc_get_temp_v4,
1588
+ .irq_ack = tsadc_irq_ack_v4,
1589
+ .set_alarm_temp = tsadc_alarm_temp_v3,
1590
+ .set_tshut_temp = tsadc_tshut_temp_v3,
1591
+ .set_tshut_mode = tsadc_tshut_mode_v4,
1592
+
1593
+ .table = {
1594
+ .id = rk3528_code_table,
1595
+ .length = ARRAY_SIZE(rk3528_code_table),
1596
+ .data_mask = TSADCV2_DATA_MASK,
1597
+ .mode = ADC_INCREMENT,
1598
+ },
1599
+};
1600
+
1601
+static const struct rockchip_tsadc_chip rk3562_tsadc_data = {
1602
+ .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1603
+ .chn_num = 1, /* one channels for tsadc */
1604
+
1605
+ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1606
+ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1607
+ .tshut_temp = 95000,
1608
+
1609
+ .tsadc_init = tsadc_init_v12,
1610
+ .tsadc_control = tsadc_control_v4,
1611
+ .tsadc_get_temp = tsadc_get_temp_v4,
1612
+ .irq_ack = tsadc_irq_ack_v4,
1613
+ .set_alarm_temp = tsadc_alarm_temp_v3,
1614
+ .set_tshut_temp = tsadc_tshut_temp_v3,
1615
+ .set_tshut_mode = tsadc_tshut_mode_v4,
1616
+
1617
+ .table = {
1618
+ .id = rk3562_code_table,
1619
+ .length = ARRAY_SIZE(rk3562_code_table),
1620
+ .data_mask = TSADCV2_DATA_MASK,
1621
+ .mode = ADC_INCREMENT,
1622
+ },
1623
+};
1624
+
13841625 static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
13851626 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
13861627 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
....@@ -1477,6 +1718,14 @@
14771718 .data = (ulong)&rk3399_tsadc_data,
14781719 },
14791720 {
1721
+ .compatible = "rockchip,rk3528-tsadc",
1722
+ .data = (ulong)&rk3528_tsadc_data,
1723
+ },
1724
+ {
1725
+ .compatible = "rockchip,rk3562-tsadc",
1726
+ .data = (ulong)&rk3562_tsadc_data,
1727
+ },
1728
+ {
14801729 .compatible = "rockchip,rk3568-tsadc",
14811730 .data = (ulong)&rk3568_tsadc_data,
14821731 },
u-boot/drivers/ufs/Kconfig
....@@ -0,0 +1,24 @@
1
+menu "UFS Host Controller Support"
2
+
3
+config UFS
4
+ bool "Support UFS controllers"
5
+ depends on DM_SCSI
6
+ select CHARSET
7
+ help
8
+ This selects support for Universal Flash Subsystem (UFS).
9
+ Say Y here if you want UFS Support.
10
+
11
+config CADENCE_UFS
12
+ bool "Cadence platform driver for UFS"
13
+ depends on UFS
14
+ help
15
+ This selects the platform driver for the Cadence UFS host
16
+ controller present on present TI's J721e devices.
17
+
18
+config TI_J721E_UFS
19
+ bool "Glue Layer driver for UFS on TI J721E devices"
20
+ help
21
+ This selects the glue layer driver for Cadence controller
22
+ present on TI's J721E devices.
23
+
24
+endmenu
u-boot/drivers/ufs/Makefile
....@@ -0,0 +1,8 @@
1
+# SPDX-License-Identifier: GPL-2.0
2
+#
3
+# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
4
+#
5
+
6
+obj-$(CONFIG_UFS) += ufs.o ufs-uclass.o
7
+obj-$(CONFIG_CADENCE_UFS) += cdns-platform.o
8
+obj-$(CONFIG_TI_J721E_UFS) += ti-j721e-ufs.o
u-boot/drivers/ufs/cdns-platform.c
....@@ -0,0 +1,125 @@
1
+// SPDX-License-Identifier: GPL-2.0+
2
+/**
3
+ * cdns-platform.c - Platform driver for Cadence UFSHCI device
4
+ *
5
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
6
+ */
7
+
8
+#include <clk.h>
9
+#include <common.h>
10
+#include <dm.h>
11
+#include <ufs.h>
12
+#include <asm/io.h>
13
+#include <linux/bitops.h>
14
+#include <linux/err.h>
15
+
16
+#include "ufs.h"
17
+
18
+#define USEC_PER_SEC 1000000L
19
+
20
+#define CDNS_UFS_REG_HCLKDIV 0xFC
21
+#define CDNS_UFS_REG_PHY_XCFGD1 0x113C
22
+
23
+static int cdns_ufs_link_startup_notify(struct ufs_hba *hba,
24
+ enum ufs_notify_change_status status)
25
+{
26
+ hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
27
+ switch (status) {
28
+ case PRE_CHANGE:
29
+ return ufshcd_dme_set(hba,
30
+ UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
31
+ 0);
32
+ case POST_CHANGE:
33
+ ;
34
+ }
35
+
36
+ return 0;
37
+}
38
+
39
+static int cdns_ufs_set_hclkdiv(struct ufs_hba *hba)
40
+{
41
+ struct clk clk;
42
+ unsigned long core_clk_rate = 0;
43
+ u32 core_clk_div = 0;
44
+ int ret;
45
+
46
+ ret = clk_get_by_name(hba->dev, "core_clk", &clk);
47
+ if (ret) {
48
+ dev_err(hba->dev, "failed to get core_clk clock\n");
49
+ return ret;
50
+ }
51
+
52
+ core_clk_rate = clk_get_rate(&clk);
53
+ if (IS_ERR_VALUE(core_clk_rate)) {
54
+ dev_err(hba->dev, "%s: unable to find core_clk rate\n",
55
+ __func__);
56
+ return core_clk_rate;
57
+ }
58
+
59
+ core_clk_div = core_clk_rate / USEC_PER_SEC;
60
+ ufshcd_writel(hba, core_clk_div, CDNS_UFS_REG_HCLKDIV);
61
+
62
+ return 0;
63
+}
64
+
65
+static int cdns_ufs_hce_enable_notify(struct ufs_hba *hba,
66
+ enum ufs_notify_change_status status)
67
+{
68
+ switch (status) {
69
+ case PRE_CHANGE:
70
+ return cdns_ufs_set_hclkdiv(hba);
71
+ case POST_CHANGE:
72
+ ;
73
+ }
74
+
75
+ return 0;
76
+}
77
+
78
+static int cdns_ufs_init(struct ufs_hba *hba)
79
+{
80
+ u32 data;
81
+
82
+ /* Increase RX_Advanced_Min_ActivateTime_Capability */
83
+ data = ufshcd_readl(hba, CDNS_UFS_REG_PHY_XCFGD1);
84
+ data |= BIT(24);
85
+ ufshcd_writel(hba, data, CDNS_UFS_REG_PHY_XCFGD1);
86
+
87
+ return 0;
88
+}
89
+
90
+static struct ufs_hba_ops cdns_pltfm_hba_ops = {
91
+ .init = cdns_ufs_init,
92
+ .hce_enable_notify = cdns_ufs_hce_enable_notify,
93
+ .link_startup_notify = cdns_ufs_link_startup_notify,
94
+};
95
+
96
+static int cdns_ufs_pltfm_probe(struct udevice *dev)
97
+{
98
+ int err = ufshcd_probe(dev, &cdns_pltfm_hba_ops);
99
+ if (err)
100
+ dev_err(dev, "ufshcd_probe() failed %d\n", err);
101
+
102
+ return err;
103
+}
104
+
105
+static int cdns_ufs_pltfm_bind(struct udevice *dev)
106
+{
107
+ struct udevice *scsi_dev;
108
+
109
+ return ufs_scsi_bind(dev, &scsi_dev);
110
+}
111
+
112
+static const struct udevice_id cdns_ufs_pltfm_ids[] = {
113
+ {
114
+ .compatible = "cdns,ufshc-m31-16nm",
115
+ },
116
+ {},
117
+};
118
+
119
+U_BOOT_DRIVER(cdns_ufs_pltfm) = {
120
+ .name = "cdns-ufs-pltfm",
121
+ .id = UCLASS_UFS,
122
+ .of_match = cdns_ufs_pltfm_ids,
123
+ .probe = cdns_ufs_pltfm_probe,
124
+ .bind = cdns_ufs_pltfm_bind,
125
+};
u-boot/drivers/ufs/ti-j721e-ufs.c
....@@ -0,0 +1,74 @@
1
+// SPDX-License-Identifier: GPL-2.0+
2
+/*
3
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4
+ */
5
+
6
+#include <asm/io.h>
7
+#include <clk.h>
8
+#include <common.h>
9
+#include <dm.h>
10
+//#include <dm/device_compat.h>
11
+#include <linux/bitops.h>
12
+#include <linux/err.h>
13
+
14
+#define UFS_SS_CTRL 0x4
15
+#define UFS_SS_RST_N_PCS BIT(0)
16
+#define UFS_SS_CLK_26MHZ BIT(4)
17
+
18
+static int ti_j721e_ufs_probe(struct udevice *dev)
19
+{
20
+ void __iomem *base;
21
+ unsigned int clock;
22
+ struct clk clk;
23
+ u32 reg = 0;
24
+ int ret;
25
+
26
+ ret = clk_get_by_index(dev, 0, &clk);
27
+ if (ret) {
28
+ dev_err(dev, "failed to get M-PHY clock\n");
29
+ return ret;
30
+ }
31
+
32
+ clock = clk_get_rate(&clk);
33
+ if (IS_ERR_VALUE(clock)) {
34
+ dev_err(dev, "failed to get rate\n");
35
+ return ret;
36
+ }
37
+
38
+ base = dev_remap_addr_index(dev, 0);
39
+
40
+ if (clock == 26000000)
41
+ reg |= UFS_SS_CLK_26MHZ;
42
+ /* Take UFS slave device out of reset */
43
+ reg |= UFS_SS_RST_N_PCS;
44
+ writel(reg, base + UFS_SS_CTRL);
45
+
46
+ return 0;
47
+}
48
+
49
+static int ti_j721e_ufs_remove(struct udevice *dev)
50
+{
51
+ void __iomem *base = dev_remap_addr_index(dev, 0);
52
+ u32 reg = readl(base + UFS_SS_CTRL);
53
+
54
+ reg &= ~UFS_SS_RST_N_PCS;
55
+ writel(reg, base + UFS_SS_CTRL);
56
+
57
+ return 0;
58
+}
59
+
60
+static const struct udevice_id ti_j721e_ufs_ids[] = {
61
+ {
62
+ .compatible = "ti,j721e-ufs",
63
+ },
64
+ {},
65
+};
66
+
67
+U_BOOT_DRIVER(ti_j721e_ufs) = {
68
+ .name = "ti-j721e-ufs",
69
+ .id = UCLASS_MISC,
70
+ .of_match = ti_j721e_ufs_ids,
71
+ .probe = ti_j721e_ufs_probe,
72
+ .remove = ti_j721e_ufs_remove,
73
+ .flags = DM_FLAG_OS_PREPARE,
74
+};
u-boot/drivers/ufs/ufs-uclass.c
....@@ -0,0 +1,18 @@
1
+// SPDX-License-Identifier: GPL-2.0
2
+/**
3
+ * ufs-uclass.c - Universal Flash Subsystem (UFS) Uclass driver
4
+ *
5
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
6
+ */
7
+
8
+#define LOG_CATEGORY UCLASS_UFS
9
+
10
+#include <common.h>
11
+#include "ufs.h"
12
+#include <dm.h>
13
+
14
+UCLASS_DRIVER(ufs) = {
15
+ .id = UCLASS_UFS,
16
+ .name = "ufs",
17
+ .per_device_auto_alloc_size = sizeof(struct ufs_hba),
18
+};
u-boot/drivers/ufs/ufs.c
....@@ -0,0 +1,1970 @@
1
+// SPDX-License-Identifier: GPL-2.0+
2
+/**
3
+ * ufs.c - Universal Flash Subsystem (UFS) driver
4
+ *
5
+ * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported
6
+ * to u-boot.
7
+ *
8
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
9
+ */
10
+#include <charset.h>
11
+#include <common.h>
12
+#include <dm.h>
13
+#include <log.h>
14
+#include <dm/lists.h>
15
+#include <dm/device-internal.h>
16
+#include <malloc.h>
17
+#include <hexdump.h>
18
+#include <scsi.h>
19
+#include <asm/io.h>
20
+#include <asm/dma-mapping.h>
21
+#include <linux/bitops.h>
22
+#include <linux/delay.h>
23
+
24
+#include "ufs.h"
25
+
26
+#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
27
+ UTP_TASK_REQ_COMPL |\
28
+ UFSHCD_ERROR_MASK)
29
+/* maximum number of link-startup retries */
30
+#define DME_LINKSTARTUP_RETRIES 3
31
+
32
+/* maximum number of retries for a general UIC command */
33
+#define UFS_UIC_COMMAND_RETRIES 3
34
+
35
+/* Query request retries */
36
+#define QUERY_REQ_RETRIES 3
37
+/* Query request timeout */
38
+#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
39
+
40
+/* maximum timeout in ms for a general UIC command */
41
+#define UFS_UIC_CMD_TIMEOUT 1000
42
+/* NOP OUT retries waiting for NOP IN response */
43
+#define NOP_OUT_RETRIES 10
44
+/* Timeout after 30 msecs if NOP OUT hangs without response */
45
+#define NOP_OUT_TIMEOUT 30 /* msecs */
46
+
47
+/* Only use one Task Tag for all requests */
48
+#define TASK_TAG 0
49
+
50
+/* Expose the flag value from utp_upiu_query.value */
51
+#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
52
+
53
+#define MAX_PRDT_ENTRY 262144
54
+
55
+/* maximum bytes per request */
56
+#define UFS_MAX_BYTES (128 * 256 * 1024)
57
+
58
+static inline bool ufshcd_is_hba_active(struct ufs_hba *hba);
59
+static inline void ufshcd_hba_stop(struct ufs_hba *hba);
60
+static int ufshcd_hba_enable(struct ufs_hba *hba);
61
+
62
+/*
63
+ * ufshcd_wait_for_register - wait for register value to change
64
+ */
65
+static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
66
+ u32 val, unsigned long timeout_ms)
67
+{
68
+ int err = 0;
69
+ unsigned long start = get_timer(0);
70
+
71
+ /* ignore bits that we don't intend to wait on */
72
+ val = val & mask;
73
+
74
+ while ((ufshcd_readl(hba, reg) & mask) != val) {
75
+ if (get_timer(start) > timeout_ms) {
76
+ if ((ufshcd_readl(hba, reg) & mask) != val)
77
+ err = -ETIMEDOUT;
78
+ break;
79
+ }
80
+ }
81
+
82
+ return err;
83
+}
84
+
85
+/**
86
+ * ufshcd_init_pwr_info - setting the POR (power on reset)
87
+ * values in hba power info
88
+ */
89
+static void ufshcd_init_pwr_info(struct ufs_hba *hba)
90
+{
91
+ hba->pwr_info.gear_rx = UFS_PWM_G1;
92
+ hba->pwr_info.gear_tx = UFS_PWM_G1;
93
+ hba->pwr_info.lane_rx = 1;
94
+ hba->pwr_info.lane_tx = 1;
95
+ hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
96
+ hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
97
+ hba->pwr_info.hs_rate = 0;
98
+}
99
+
100
+/**
101
+ * ufshcd_print_pwr_info - print power params as saved in hba
102
+ * power info
103
+ */
104
+static void ufshcd_print_pwr_info(struct ufs_hba *hba)
105
+{
106
+ static const char * const names[] = {
107
+ "INVALID MODE",
108
+ "FAST MODE",
109
+ "SLOW_MODE",
110
+ "INVALID MODE",
111
+ "FASTAUTO_MODE",
112
+ "SLOWAUTO_MODE",
113
+ "INVALID MODE",
114
+ };
115
+
116
+ dev_err(hba->dev, "[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
117
+ hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
118
+ hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
119
+ names[hba->pwr_info.pwr_rx],
120
+ names[hba->pwr_info.pwr_tx],
121
+ hba->pwr_info.hs_rate);
122
+}
123
+
124
+/**
125
+ * ufshcd_ready_for_uic_cmd - Check if controller is ready
126
+ * to accept UIC commands
127
+ */
128
+static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
129
+{
130
+ if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
131
+ return true;
132
+ else
133
+ return false;
134
+}
135
+
136
+/**
137
+ * ufshcd_get_uic_cmd_result - Get the UIC command result
138
+ */
139
+static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
140
+{
141
+ return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
142
+ MASK_UIC_COMMAND_RESULT;
143
+}
144
+
145
+/**
146
+ * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
147
+ */
148
+static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
149
+{
150
+ return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
151
+}
152
+
153
+/**
154
+ * ufshcd_is_device_present - Check if any device connected to
155
+ * the host controller
156
+ */
157
+static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
158
+{
159
+ return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
160
+ DEVICE_PRESENT) ? true : false;
161
+}
162
+
163
+/**
164
+ * ufshcd_send_uic_cmd - UFS Interconnect layer command API
165
+ *
166
+ */
167
+static int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
168
+{
169
+ unsigned long start = 0;
170
+ u32 intr_status;
171
+ u32 enabled_intr_status;
172
+
173
+ if (!ufshcd_ready_for_uic_cmd(hba)) {
174
+ dev_err(hba->dev,
175
+ "Controller not ready to accept UIC commands\n");
176
+ return -EIO;
177
+ }
178
+
179
+ debug("sending uic command:%d\n", uic_cmd->command);
180
+
181
+ /* Write Args */
182
+ ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
183
+ ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
184
+ ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
185
+
186
+ /* Write UIC Cmd */
187
+ ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
188
+ REG_UIC_COMMAND);
189
+
190
+ start = get_timer(0);
191
+ do {
192
+ intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
193
+ enabled_intr_status = intr_status & hba->intr_mask;
194
+ ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
195
+
196
+ if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) {
197
+ dev_err(hba->dev,
198
+ "Timedout waiting for UIC response\n");
199
+
200
+ return -ETIMEDOUT;
201
+ }
202
+
203
+ if (enabled_intr_status & UFSHCD_ERROR_MASK) {
204
+ dev_err(hba->dev, "Error in status:%08x\n",
205
+ enabled_intr_status);
206
+
207
+ return -1;
208
+ }
209
+ } while (!(enabled_intr_status & UFSHCD_UIC_MASK));
210
+
211
+ uic_cmd->argument2 = ufshcd_get_uic_cmd_result(hba);
212
+ uic_cmd->argument3 = ufshcd_get_dme_attr_val(hba);
213
+
214
+ debug("Sent successfully\n");
215
+
216
+ return 0;
217
+}
218
+
219
+/**
220
+ * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
221
+ *
222
+ */
223
+int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, u8 attr_set,
224
+ u32 mib_val, u8 peer)
225
+{
226
+ struct uic_command uic_cmd = {0};
227
+ static const char *const action[] = {
228
+ "dme-set",
229
+ "dme-peer-set"
230
+ };
231
+ const char *set = action[!!peer];
232
+ int ret;
233
+ int retries = UFS_UIC_COMMAND_RETRIES;
234
+
235
+ uic_cmd.command = peer ?
236
+ UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
237
+ uic_cmd.argument1 = attr_sel;
238
+ uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
239
+ uic_cmd.argument3 = mib_val;
240
+
241
+ do {
242
+ /* for peer attributes we retry upon failure */
243
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
244
+ if (ret)
245
+ dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
246
+ set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
247
+ } while (ret && peer && --retries);
248
+
249
+ if (ret)
250
+ dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
251
+ set, UIC_GET_ATTR_ID(attr_sel), mib_val,
252
+ UFS_UIC_COMMAND_RETRIES - retries);
253
+
254
+ return ret;
255
+}
256
+
257
+/**
258
+ * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
259
+ *
260
+ */
261
+int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
262
+ u32 *mib_val, u8 peer)
263
+{
264
+ struct uic_command uic_cmd = {0};
265
+ static const char *const action[] = {
266
+ "dme-get",
267
+ "dme-peer-get"
268
+ };
269
+ const char *get = action[!!peer];
270
+ int ret;
271
+ int retries = UFS_UIC_COMMAND_RETRIES;
272
+
273
+ uic_cmd.command = peer ?
274
+ UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
275
+ uic_cmd.argument1 = attr_sel;
276
+
277
+ do {
278
+ /* for peer attributes we retry upon failure */
279
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
280
+ if (ret)
281
+ dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
282
+ get, UIC_GET_ATTR_ID(attr_sel), ret);
283
+ } while (ret && peer && --retries);
284
+
285
+ if (ret)
286
+ dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
287
+ get, UIC_GET_ATTR_ID(attr_sel),
288
+ UFS_UIC_COMMAND_RETRIES - retries);
289
+
290
+ if (mib_val && !ret)
291
+ *mib_val = uic_cmd.argument3;
292
+
293
+ return ret;
294
+}
295
+
296
+static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
297
+{
298
+ u32 tx_lanes, i, err = 0;
299
+
300
+ if (!peer)
301
+ ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
302
+ &tx_lanes);
303
+ else
304
+ ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
305
+ &tx_lanes);
306
+ for (i = 0; i < tx_lanes; i++) {
307
+ if (!peer)
308
+ err = ufshcd_dme_set(hba,
309
+ UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
310
+ UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
311
+ 0);
312
+ else
313
+ err = ufshcd_dme_peer_set(hba,
314
+ UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
315
+ UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
316
+ 0);
317
+ if (err) {
318
+ dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
319
+ __func__, peer, i, err);
320
+ break;
321
+ }
322
+ }
323
+
324
+ return err;
325
+}
326
+
327
+static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
328
+{
329
+ return ufshcd_disable_tx_lcc(hba, true);
330
+}
331
+
332
+/**
333
+ * ufshcd_dme_link_startup - Notify Unipro to perform link startup
334
+ *
335
+ */
336
+static int ufshcd_dme_link_startup(struct ufs_hba *hba)
337
+{
338
+ struct uic_command uic_cmd = {0};
339
+ int ret;
340
+
341
+ uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
342
+
343
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
344
+ if (ret)
345
+ dev_dbg(hba->dev,
346
+ "dme-link-startup: error code %d\n", ret);
347
+ return ret;
348
+}
349
+
350
+/**
351
+ * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
352
+ *
353
+ */
354
+static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
355
+{
356
+ ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
357
+}
358
+
359
+/**
360
+ * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
361
+ */
362
+static inline int ufshcd_get_lists_status(u32 reg)
363
+{
364
+ return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
365
+}
366
+
367
+/**
368
+ * ufshcd_enable_run_stop_reg - Enable run-stop registers,
369
+ * When run-stop registers are set to 1, it indicates the
370
+ * host controller that it can process the requests
371
+ */
372
+static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
373
+{
374
+ ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
375
+ REG_UTP_TASK_REQ_LIST_RUN_STOP);
376
+ ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
377
+ REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
378
+}
379
+
380
+/**
381
+ * ufshcd_enable_intr - enable interrupts
382
+ */
383
+static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
384
+{
385
+ u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
386
+ u32 rw;
387
+
388
+ if (hba->version == UFSHCI_VERSION_10) {
389
+ rw = set & INTERRUPT_MASK_RW_VER_10;
390
+ set = rw | ((set ^ intrs) & intrs);
391
+ } else {
392
+ set |= intrs;
393
+ }
394
+
395
+ ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
396
+
397
+ hba->intr_mask = set;
398
+}
399
+
400
+/**
401
+ * ufshcd_make_hba_operational - Make UFS controller operational
402
+ *
403
+ * To bring UFS host controller to operational state,
404
+ * 1. Enable required interrupts
405
+ * 2. Configure interrupt aggregation
406
+ * 3. Program UTRL and UTMRL base address
407
+ * 4. Configure run-stop-registers
408
+ *
409
+ */
410
+static int ufshcd_make_hba_operational(struct ufs_hba *hba)
411
+{
412
+ int err = 0;
413
+ u32 reg;
414
+
415
+ /* Enable required interrupts */
416
+ ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
417
+
418
+ /* Disable interrupt aggregation */
419
+ ufshcd_disable_intr_aggr(hba);
420
+
421
+ /* Configure UTRL and UTMRL base address registers */
422
+ ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utrdl),
423
+ REG_UTP_TRANSFER_REQ_LIST_BASE_L);
424
+ ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utrdl),
425
+ REG_UTP_TRANSFER_REQ_LIST_BASE_H);
426
+ ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utmrdl),
427
+ REG_UTP_TASK_REQ_LIST_BASE_L);
428
+ ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl),
429
+ REG_UTP_TASK_REQ_LIST_BASE_H);
430
+
431
+ /*
432
+ * UCRDY, UTMRLDY and UTRLRDY bits must be 1
433
+ */
434
+ reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
435
+ if (!(ufshcd_get_lists_status(reg))) {
436
+ ufshcd_enable_run_stop_reg(hba);
437
+ } else {
438
+ dev_err(hba->dev,
439
+ "Host controller not ready to process requests");
440
+ err = -EIO;
441
+ goto out;
442
+ }
443
+
444
+out:
445
+ return err;
446
+}
447
+
448
+/**
449
+ * ufshcd_link_startup - Initialize unipro link startup
450
+ */
451
+static int ufshcd_link_startup(struct ufs_hba *hba)
452
+{
453
+ int ret;
454
+ int retries = DME_LINKSTARTUP_RETRIES;
455
+ bool link_startup_again = true;
456
+
457
+link_startup:
458
+ do {
459
+ ufshcd_ops_link_startup_notify(hba, PRE_CHANGE);
460
+
461
+ ret = ufshcd_dme_link_startup(hba);
462
+
463
+ /* check if device is detected by inter-connect layer */
464
+ if (!ret && !ufshcd_is_device_present(hba)) {
465
+ dev_err(hba->dev, "%s: Device not present\n", __func__);
466
+ ret = -ENXIO;
467
+ goto out;
468
+ }
469
+
470
+ /*
471
+ * DME link lost indication is only received when link is up,
472
+ * but we can't be sure if the link is up until link startup
473
+ * succeeds. So reset the local Uni-Pro and try again.
474
+ */
475
+ if (ret && ufshcd_hba_enable(hba))
476
+ goto out;
477
+ } while (ret && retries--);
478
+
479
+ if (ret)
480
+ /* failed to get the link up... retire */
481
+ goto out;
482
+
483
+ if (link_startup_again) {
484
+ link_startup_again = false;
485
+ retries = DME_LINKSTARTUP_RETRIES;
486
+ goto link_startup;
487
+ }
488
+
489
+ /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
490
+ ufshcd_init_pwr_info(hba);
491
+
492
+ if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
493
+ ret = ufshcd_disable_device_tx_lcc(hba);
494
+ if (ret)
495
+ goto out;
496
+ }
497
+
498
+ /* Include any host controller configuration via UIC commands */
499
+ ret = ufshcd_ops_link_startup_notify(hba, POST_CHANGE);
500
+ if (ret)
501
+ goto out;
502
+
503
+ ret = ufshcd_make_hba_operational(hba);
504
+out:
505
+ if (ret)
506
+ dev_err(hba->dev, "link startup failed %d\n", ret);
507
+
508
+ return ret;
509
+}
510
+
511
+/**
512
+ * ufshcd_hba_stop - Send controller to reset state
513
+ */
514
+static inline void ufshcd_hba_stop(struct ufs_hba *hba)
515
+{
516
+ int err;
517
+
518
+ ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
519
+ err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
520
+ CONTROLLER_ENABLE, CONTROLLER_DISABLE,
521
+ 10);
522
+ if (err)
523
+ dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
524
+}
525
+
526
+/**
527
+ * ufshcd_is_hba_active - Get controller state
528
+ */
529
+static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
530
+{
531
+ return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
532
+ ? false : true;
533
+}
534
+
535
+/**
536
+ * ufshcd_hba_start - Start controller initialization sequence
537
+ */
538
+static inline void ufshcd_hba_start(struct ufs_hba *hba)
539
+{
540
+ ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
541
+}
542
+
543
+/**
544
+ * ufshcd_hba_enable - initialize the controller
545
+ */
546
+static int ufshcd_hba_enable(struct ufs_hba *hba)
547
+{
548
+ int retry;
549
+
550
+ if (!ufshcd_is_hba_active(hba))
551
+ /* change controller state to "reset state" */
552
+ ufshcd_hba_stop(hba);
553
+
554
+ ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE);
555
+
556
+ /* start controller initialization sequence */
557
+ ufshcd_hba_start(hba);
558
+
559
+ /*
560
+ * To initialize a UFS host controller HCE bit must be set to 1.
561
+ * During initialization the HCE bit value changes from 1->0->1.
562
+ * When the host controller completes initialization sequence
563
+ * it sets the value of HCE bit to 1. The same HCE bit is read back
564
+ * to check if the controller has completed initialization sequence.
565
+ * So without this delay the value HCE = 1, set in the previous
566
+ * instruction might be read back.
567
+ * This delay can be changed based on the controller.
568
+ */
569
+ mdelay(1);
570
+
571
+ /* wait for the host controller to complete initialization */
572
+ retry = 10;
573
+ while (ufshcd_is_hba_active(hba)) {
574
+ if (retry) {
575
+ retry--;
576
+ } else {
577
+ dev_err(hba->dev, "Controller enable failed\n");
578
+ return -EIO;
579
+ }
580
+ mdelay(5);
581
+ }
582
+
583
+ /* enable UIC related interrupts */
584
+ ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
585
+
586
+ ufshcd_ops_hce_enable_notify(hba, POST_CHANGE);
587
+
588
+ return 0;
589
+}
590
+
591
+/**
592
+ * ufshcd_host_memory_configure - configure local reference block with
593
+ * memory offsets
594
+ */
595
+static void ufshcd_host_memory_configure(struct ufs_hba *hba)
596
+{
597
+ struct utp_transfer_req_desc *utrdlp;
598
+ dma_addr_t cmd_desc_dma_addr;
599
+ u16 response_offset;
600
+ u16 prdt_offset;
601
+
602
+ utrdlp = hba->utrdl;
603
+ cmd_desc_dma_addr = (dma_addr_t)hba->ucdl;
604
+
605
+ utrdlp->command_desc_base_addr_lo =
606
+ cpu_to_le32(lower_32_bits(cmd_desc_dma_addr));
607
+ utrdlp->command_desc_base_addr_hi =
608
+ cpu_to_le32(upper_32_bits(cmd_desc_dma_addr));
609
+
610
+ response_offset = offsetof(struct utp_transfer_cmd_desc, response_upiu);
611
+ prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
612
+
613
+ utrdlp->response_upiu_offset = cpu_to_le16(response_offset >> 2);
614
+ utrdlp->prd_table_offset = cpu_to_le16(prdt_offset >> 2);
615
+ utrdlp->response_upiu_length = cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
616
+
617
+ hba->ucd_req_ptr = (struct utp_upiu_req *)hba->ucdl;
618
+ hba->ucd_rsp_ptr =
619
+ (struct utp_upiu_rsp *)&hba->ucdl->response_upiu;
620
+ hba->ucd_prdt_ptr =
621
+ (struct ufshcd_sg_entry *)&hba->ucdl->prd_table;
622
+}
623
+
624
+/**
625
+ * ufshcd_memory_alloc - allocate memory for host memory space data structures
626
+ */
627
+static int ufshcd_memory_alloc(struct ufs_hba *hba)
628
+{
629
+ /* Allocate one Transfer Request Descriptor
630
+ * Should be aligned to 1k boundary.
631
+ */
632
+ hba->utrdl = memalign(1024, sizeof(struct utp_transfer_req_desc));
633
+ if (!hba->utrdl) {
634
+ dev_err(hba->dev, "Transfer Descriptor memory allocation failed\n");
635
+ return -ENOMEM;
636
+ }
637
+
638
+ /* Allocate one Command Descriptor
639
+ * Should be aligned to 1k boundary.
640
+ */
641
+ hba->ucdl = memalign(1024, sizeof(struct utp_transfer_cmd_desc));
642
+ if (!hba->ucdl) {
643
+ dev_err(hba->dev, "Command descriptor memory allocation failed\n");
644
+ return -ENOMEM;
645
+ }
646
+
647
+ return 0;
648
+}
649
+
650
+/**
651
+ * ufshcd_get_intr_mask - Get the interrupt bit mask
652
+ */
653
+static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
654
+{
655
+ u32 intr_mask = 0;
656
+
657
+ switch (hba->version) {
658
+ case UFSHCI_VERSION_10:
659
+ intr_mask = INTERRUPT_MASK_ALL_VER_10;
660
+ break;
661
+ case UFSHCI_VERSION_11:
662
+ case UFSHCI_VERSION_20:
663
+ intr_mask = INTERRUPT_MASK_ALL_VER_11;
664
+ break;
665
+ case UFSHCI_VERSION_21:
666
+ default:
667
+ intr_mask = INTERRUPT_MASK_ALL_VER_21;
668
+ break;
669
+ }
670
+
671
+ return intr_mask;
672
+}
673
+
674
+/**
675
+ * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
676
+ */
677
+static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
678
+{
679
+ return ufshcd_readl(hba, REG_UFS_VERSION);
680
+}
681
+
682
+/**
683
+ * ufshcd_get_upmcrs - Get the power mode change request status
684
+ */
685
+static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
686
+{
687
+ return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
688
+}
689
+
690
+/**
691
+ * ufshcd_prepare_req_desc_hdr() - Fills the requests header
692
+ * descriptor according to request
693
+ */
694
+static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc,
695
+ u32 *upiu_flags,
696
+ enum dma_data_direction cmd_dir)
697
+{
698
+ u32 data_direction;
699
+ u32 dword_0;
700
+
701
+ if (cmd_dir == DMA_FROM_DEVICE) {
702
+ data_direction = UTP_DEVICE_TO_HOST;
703
+ *upiu_flags = UPIU_CMD_FLAGS_READ;
704
+ } else if (cmd_dir == DMA_TO_DEVICE) {
705
+ data_direction = UTP_HOST_TO_DEVICE;
706
+ *upiu_flags = UPIU_CMD_FLAGS_WRITE;
707
+ } else {
708
+ data_direction = UTP_NO_DATA_TRANSFER;
709
+ *upiu_flags = UPIU_CMD_FLAGS_NONE;
710
+ }
711
+
712
+ dword_0 = data_direction | (0x1 << UPIU_COMMAND_TYPE_OFFSET);
713
+
714
+ /* Enable Interrupt for command */
715
+ dword_0 |= UTP_REQ_DESC_INT_CMD;
716
+
717
+ /* Transfer request descriptor header fields */
718
+ req_desc->header.dword_0 = cpu_to_le32(dword_0);
719
+ /* dword_1 is reserved, hence it is set to 0 */
720
+ req_desc->header.dword_1 = 0;
721
+ /*
722
+ * assigning invalid value for command status. Controller
723
+ * updates OCS on command completion, with the command
724
+ * status
725
+ */
726
+ req_desc->header.dword_2 =
727
+ cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
728
+ /* dword_3 is reserved, hence it is set to 0 */
729
+ req_desc->header.dword_3 = 0;
730
+
731
+ req_desc->prd_table_length = 0;
732
+}
733
+
734
+static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
735
+ u32 upiu_flags)
736
+{
737
+ struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
738
+ struct ufs_query *query = &hba->dev_cmd.query;
739
+ u16 len = be16_to_cpu(query->request.upiu_req.length);
740
+
741
+ /* Query request header */
742
+ ucd_req_ptr->header.dword_0 =
743
+ UPIU_HEADER_DWORD(UPIU_TRANSACTION_QUERY_REQ,
744
+ upiu_flags, 0, TASK_TAG);
745
+ ucd_req_ptr->header.dword_1 =
746
+ UPIU_HEADER_DWORD(0, query->request.query_func,
747
+ 0, 0);
748
+
749
+ /* Data segment length only need for WRITE_DESC */
750
+ if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
751
+ ucd_req_ptr->header.dword_2 =
752
+ UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
753
+ else
754
+ ucd_req_ptr->header.dword_2 = 0;
755
+
756
+ /* Copy the Query Request buffer as is */
757
+ memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, QUERY_OSF_SIZE);
758
+
759
+ /* Copy the Descriptor */
760
+ if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
761
+ memcpy(ucd_req_ptr + 1, query->descriptor, len);
762
+
763
+ memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
764
+}
765
+
766
+static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba)
767
+{
768
+ struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
769
+
770
+ memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
771
+
772
+ /* command descriptor fields */
773
+ ucd_req_ptr->header.dword_0 =
774
+ UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT, 0, 0, TASK_TAG);
775
+ /* clear rest of the fields of basic header */
776
+ ucd_req_ptr->header.dword_1 = 0;
777
+ ucd_req_ptr->header.dword_2 = 0;
778
+
779
+ memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
780
+}
781
+
782
+/**
783
+ * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
784
+ * for Device Management Purposes
785
+ */
786
+static int ufshcd_comp_devman_upiu(struct ufs_hba *hba,
787
+ enum dev_cmd_type cmd_type)
788
+{
789
+ u32 upiu_flags;
790
+ int ret = 0;
791
+ struct utp_transfer_req_desc *req_desc = hba->utrdl;
792
+
793
+ hba->dev_cmd.type = cmd_type;
794
+
795
+ ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, DMA_NONE);
796
+ switch (cmd_type) {
797
+ case DEV_CMD_TYPE_QUERY:
798
+ ufshcd_prepare_utp_query_req_upiu(hba, upiu_flags);
799
+ break;
800
+ case DEV_CMD_TYPE_NOP:
801
+ ufshcd_prepare_utp_nop_upiu(hba);
802
+ break;
803
+ default:
804
+ ret = -EINVAL;
805
+ }
806
+
807
+ return ret;
808
+}
809
+
810
+static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
811
+{
812
+ unsigned long start;
813
+ u32 intr_status;
814
+ u32 enabled_intr_status;
815
+
816
+ ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
817
+
818
+ start = get_timer(0);
819
+ do {
820
+ intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
821
+ enabled_intr_status = intr_status & hba->intr_mask;
822
+ ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
823
+
824
+ if (get_timer(start) > QUERY_REQ_TIMEOUT) {
825
+ dev_err(hba->dev,
826
+ "Timedout waiting for UTP response\n");
827
+
828
+ return -ETIMEDOUT;
829
+ }
830
+
831
+ if (enabled_intr_status & UFSHCD_ERROR_MASK) {
832
+ dev_err(hba->dev, "Error in status:%08x\n",
833
+ enabled_intr_status);
834
+
835
+ return -1;
836
+ }
837
+ } while (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL));
838
+
839
+ return 0;
840
+}
841
+
842
+/**
843
+ * ufshcd_get_req_rsp - returns the TR response transaction type
844
+ */
845
+static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
846
+{
847
+ return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
848
+}
849
+
850
+/**
851
+ * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
852
+ *
853
+ */
854
+static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba)
855
+{
856
+ return le32_to_cpu(hba->utrdl->header.dword_2) & MASK_OCS;
857
+}
858
+
859
+static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
860
+{
861
+ return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
862
+}
863
+
864
+static int ufshcd_check_query_response(struct ufs_hba *hba)
865
+{
866
+ struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
867
+
868
+ /* Get the UPIU response */
869
+ query_res->response = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr) >>
870
+ UPIU_RSP_CODE_OFFSET;
871
+ return query_res->response;
872
+}
873
+
874
+/**
875
+ * ufshcd_copy_query_response() - Copy the Query Response and the data
876
+ * descriptor
877
+ */
878
+static int ufshcd_copy_query_response(struct ufs_hba *hba)
879
+{
880
+ struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
881
+
882
+ memcpy(&query_res->upiu_res, &hba->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
883
+
884
+ /* Get the descriptor */
885
+ if (hba->dev_cmd.query.descriptor &&
886
+ hba->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
887
+ u8 *descp = (u8 *)hba->ucd_rsp_ptr +
888
+ GENERAL_UPIU_REQUEST_SIZE;
889
+ u16 resp_len;
890
+ u16 buf_len;
891
+
892
+ /* data segment length */
893
+ resp_len = be32_to_cpu(hba->ucd_rsp_ptr->header.dword_2) &
894
+ MASK_QUERY_DATA_SEG_LEN;
895
+ buf_len =
896
+ be16_to_cpu(hba->dev_cmd.query.request.upiu_req.length);
897
+ if (likely(buf_len >= resp_len)) {
898
+ memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
899
+ } else {
900
+ dev_warn(hba->dev,
901
+ "%s: Response size is bigger than buffer",
902
+ __func__);
903
+ return -EINVAL;
904
+ }
905
+ }
906
+
907
+ return 0;
908
+}
909
+
910
+/**
911
+ * ufshcd_exec_dev_cmd - API for sending device management requests
912
+ */
913
+static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, enum dev_cmd_type cmd_type,
914
+ int timeout)
915
+{
916
+ int err;
917
+ int resp;
918
+
919
+ err = ufshcd_comp_devman_upiu(hba, cmd_type);
920
+ if (err)
921
+ return err;
922
+
923
+ err = ufshcd_send_command(hba, TASK_TAG);
924
+ if (err)
925
+ return err;
926
+
927
+ err = ufshcd_get_tr_ocs(hba);
928
+ if (err) {
929
+ dev_err(hba->dev, "Error in OCS:%d\n", err);
930
+ return -EINVAL;
931
+ }
932
+
933
+ resp = ufshcd_get_req_rsp(hba->ucd_rsp_ptr);
934
+ switch (resp) {
935
+ case UPIU_TRANSACTION_NOP_IN:
936
+ break;
937
+ case UPIU_TRANSACTION_QUERY_RSP:
938
+ err = ufshcd_check_query_response(hba);
939
+ if (!err)
940
+ err = ufshcd_copy_query_response(hba);
941
+ break;
942
+ case UPIU_TRANSACTION_REJECT_UPIU:
943
+ /* TODO: handle Reject UPIU Response */
944
+ err = -EPERM;
945
+ dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
946
+ __func__);
947
+ break;
948
+ default:
949
+ err = -EINVAL;
950
+ dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
951
+ __func__, resp);
952
+ }
953
+
954
+ return err;
955
+}
956
+
957
+/**
958
+ * ufshcd_init_query() - init the query response and request parameters
959
+ */
960
+static inline void ufshcd_init_query(struct ufs_hba *hba,
961
+ struct ufs_query_req **request,
962
+ struct ufs_query_res **response,
963
+ enum query_opcode opcode,
964
+ u8 idn, u8 index, u8 selector)
965
+{
966
+ *request = &hba->dev_cmd.query.request;
967
+ *response = &hba->dev_cmd.query.response;
968
+ memset(*request, 0, sizeof(struct ufs_query_req));
969
+ memset(*response, 0, sizeof(struct ufs_query_res));
970
+ (*request)->upiu_req.opcode = opcode;
971
+ (*request)->upiu_req.idn = idn;
972
+ (*request)->upiu_req.index = index;
973
+ (*request)->upiu_req.selector = selector;
974
+}
975
+
976
+/**
977
+ * ufshcd_query_flag() - API function for sending flag query requests
978
+ */
979
+int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
980
+ enum flag_idn idn, bool *flag_res)
981
+{
982
+ struct ufs_query_req *request = NULL;
983
+ struct ufs_query_res *response = NULL;
984
+ int err, index = 0, selector = 0;
985
+ int timeout = QUERY_REQ_TIMEOUT;
986
+
987
+ ufshcd_init_query(hba, &request, &response, opcode, idn, index,
988
+ selector);
989
+
990
+ switch (opcode) {
991
+ case UPIU_QUERY_OPCODE_SET_FLAG:
992
+ case UPIU_QUERY_OPCODE_CLEAR_FLAG:
993
+ case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
994
+ request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
995
+ break;
996
+ case UPIU_QUERY_OPCODE_READ_FLAG:
997
+ request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
998
+ if (!flag_res) {
999
+ /* No dummy reads */
1000
+ dev_err(hba->dev, "%s: Invalid argument for read request\n",
1001
+ __func__);
1002
+ err = -EINVAL;
1003
+ goto out;
1004
+ }
1005
+ break;
1006
+ default:
1007
+ dev_err(hba->dev,
1008
+ "%s: Expected query flag opcode but got = %d\n",
1009
+ __func__, opcode);
1010
+ err = -EINVAL;
1011
+ goto out;
1012
+ }
1013
+
1014
+ err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
1015
+
1016
+ if (err) {
1017
+ dev_err(hba->dev,
1018
+ "%s: Sending flag query for idn %d failed, err = %d\n",
1019
+ __func__, idn, err);
1020
+ goto out;
1021
+ }
1022
+
1023
+ if (flag_res)
1024
+ *flag_res = (be32_to_cpu(response->upiu_res.value) &
1025
+ MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
1026
+
1027
+out:
1028
+ return err;
1029
+}
1030
+
1031
+static int ufshcd_query_flag_retry(struct ufs_hba *hba,
1032
+ enum query_opcode opcode,
1033
+ enum flag_idn idn, bool *flag_res)
1034
+{
1035
+ int ret;
1036
+ int retries;
1037
+
1038
+ for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
1039
+ ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
1040
+ if (ret)
1041
+ dev_dbg(hba->dev,
1042
+ "%s: failed with error %d, retries %d\n",
1043
+ __func__, ret, retries);
1044
+ else
1045
+ break;
1046
+ }
1047
+
1048
+ if (ret)
1049
+ dev_err(hba->dev,
1050
+ "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
1051
+ __func__, opcode, idn, ret, retries);
1052
+ return ret;
1053
+}
1054
+
1055
+static int __ufshcd_query_descriptor(struct ufs_hba *hba,
1056
+ enum query_opcode opcode,
1057
+ enum desc_idn idn, u8 index, u8 selector,
1058
+ u8 *desc_buf, int *buf_len)
1059
+{
1060
+ struct ufs_query_req *request = NULL;
1061
+ struct ufs_query_res *response = NULL;
1062
+ int err;
1063
+
1064
+ if (!desc_buf) {
1065
+ dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
1066
+ __func__, opcode);
1067
+ err = -EINVAL;
1068
+ goto out;
1069
+ }
1070
+
1071
+ if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
1072
+ dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
1073
+ __func__, *buf_len);
1074
+ err = -EINVAL;
1075
+ goto out;
1076
+ }
1077
+
1078
+ ufshcd_init_query(hba, &request, &response, opcode, idn, index,
1079
+ selector);
1080
+ hba->dev_cmd.query.descriptor = desc_buf;
1081
+ request->upiu_req.length = cpu_to_be16(*buf_len);
1082
+
1083
+ switch (opcode) {
1084
+ case UPIU_QUERY_OPCODE_WRITE_DESC:
1085
+ request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
1086
+ break;
1087
+ case UPIU_QUERY_OPCODE_READ_DESC:
1088
+ request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
1089
+ break;
1090
+ default:
1091
+ dev_err(hba->dev, "%s: Expected query descriptor opcode but got = 0x%.2x\n",
1092
+ __func__, opcode);
1093
+ err = -EINVAL;
1094
+ goto out;
1095
+ }
1096
+
1097
+ err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
1098
+
1099
+ if (err) {
1100
+ dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
1101
+ __func__, opcode, idn, index, err);
1102
+ goto out;
1103
+ }
1104
+
1105
+ hba->dev_cmd.query.descriptor = NULL;
1106
+ *buf_len = be16_to_cpu(response->upiu_res.length);
1107
+
1108
+out:
1109
+ return err;
1110
+}
1111
+
1112
+/**
1113
+ * ufshcd_query_descriptor_retry - API function for sending descriptor requests
1114
+ */
1115
+int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode,
1116
+ enum desc_idn idn, u8 index, u8 selector,
1117
+ u8 *desc_buf, int *buf_len)
1118
+{
1119
+ int err;
1120
+ int retries;
1121
+
1122
+ for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
1123
+ err = __ufshcd_query_descriptor(hba, opcode, idn, index,
1124
+ selector, desc_buf, buf_len);
1125
+ if (!err || err == -EINVAL)
1126
+ break;
1127
+ }
1128
+
1129
+ return err;
1130
+}
1131
+
1132
+/**
1133
+ * ufshcd_read_desc_length - read the specified descriptor length from header
1134
+ */
1135
+static int ufshcd_read_desc_length(struct ufs_hba *hba, enum desc_idn desc_id,
1136
+ int desc_index, int *desc_length)
1137
+{
1138
+ int ret;
1139
+ u8 header[QUERY_DESC_HDR_SIZE];
1140
+ int header_len = QUERY_DESC_HDR_SIZE;
1141
+
1142
+ if (desc_id >= QUERY_DESC_IDN_MAX)
1143
+ return -EINVAL;
1144
+
1145
+ ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
1146
+ desc_id, desc_index, 0, header,
1147
+ &header_len);
1148
+
1149
+ if (ret) {
1150
+ dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
1151
+ __func__, desc_id);
1152
+ return ret;
1153
+ } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
1154
+ dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
1155
+ __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
1156
+ desc_id);
1157
+ ret = -EINVAL;
1158
+ }
1159
+
1160
+ *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
1161
+
1162
+ return ret;
1163
+}
1164
+
1165
+static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
1166
+{
1167
+ int err;
1168
+
1169
+ err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
1170
+ &hba->desc_size.dev_desc);
1171
+ if (err)
1172
+ hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
1173
+
1174
+ err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
1175
+ &hba->desc_size.pwr_desc);
1176
+ if (err)
1177
+ hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
1178
+
1179
+ err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
1180
+ &hba->desc_size.interc_desc);
1181
+ if (err)
1182
+ hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
1183
+
1184
+ err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
1185
+ &hba->desc_size.conf_desc);
1186
+ if (err)
1187
+ hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
1188
+
1189
+ err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
1190
+ &hba->desc_size.unit_desc);
1191
+ if (err)
1192
+ hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
1193
+
1194
+ err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
1195
+ &hba->desc_size.geom_desc);
1196
+ if (err)
1197
+ hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
1198
+
1199
+ err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
1200
+ &hba->desc_size.hlth_desc);
1201
+ if (err)
1202
+ hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
1203
+}
1204
+
1205
+/**
1206
+ * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
1207
+ *
1208
+ */
1209
+int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
1210
+ int *desc_len)
1211
+{
1212
+ switch (desc_id) {
1213
+ case QUERY_DESC_IDN_DEVICE:
1214
+ *desc_len = hba->desc_size.dev_desc;
1215
+ break;
1216
+ case QUERY_DESC_IDN_POWER:
1217
+ *desc_len = hba->desc_size.pwr_desc;
1218
+ break;
1219
+ case QUERY_DESC_IDN_GEOMETRY:
1220
+ *desc_len = hba->desc_size.geom_desc;
1221
+ break;
1222
+ case QUERY_DESC_IDN_CONFIGURATION:
1223
+ *desc_len = hba->desc_size.conf_desc;
1224
+ break;
1225
+ case QUERY_DESC_IDN_UNIT:
1226
+ *desc_len = hba->desc_size.unit_desc;
1227
+ break;
1228
+ case QUERY_DESC_IDN_INTERCONNECT:
1229
+ *desc_len = hba->desc_size.interc_desc;
1230
+ break;
1231
+ case QUERY_DESC_IDN_STRING:
1232
+ *desc_len = QUERY_DESC_MAX_SIZE;
1233
+ break;
1234
+ case QUERY_DESC_IDN_HEALTH:
1235
+ *desc_len = hba->desc_size.hlth_desc;
1236
+ break;
1237
+ case QUERY_DESC_IDN_RFU_0:
1238
+ case QUERY_DESC_IDN_RFU_1:
1239
+ *desc_len = 0;
1240
+ break;
1241
+ default:
1242
+ *desc_len = 0;
1243
+ return -EINVAL;
1244
+ }
1245
+ return 0;
1246
+}
1247
+EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
1248
+
1249
+/**
1250
+ * ufshcd_read_desc_param - read the specified descriptor parameter
1251
+ *
1252
+ */
1253
+int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id,
1254
+ int desc_index, u8 param_offset, u8 *param_read_buf,
1255
+ u8 param_size)
1256
+{
1257
+ int ret;
1258
+ u8 *desc_buf;
1259
+ int buff_len;
1260
+ bool is_kmalloc = true;
1261
+
1262
+ /* Safety check */
1263
+ if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
1264
+ return -EINVAL;
1265
+
1266
+ /* Get the max length of descriptor from structure filled up at probe
1267
+ * time.
1268
+ */
1269
+ ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
1270
+
1271
+ /* Sanity checks */
1272
+ if (ret || !buff_len) {
1273
+ dev_err(hba->dev, "%s: Failed to get full descriptor length",
1274
+ __func__);
1275
+ return ret;
1276
+ }
1277
+
1278
+ /* Check whether we need temp memory */
1279
+ if (param_offset != 0 || param_size < buff_len) {
1280
+ desc_buf = kmalloc(buff_len, GFP_KERNEL);
1281
+ if (!desc_buf)
1282
+ return -ENOMEM;
1283
+ } else {
1284
+ desc_buf = param_read_buf;
1285
+ is_kmalloc = false;
1286
+ }
1287
+
1288
+ /* Request for full descriptor */
1289
+ ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
1290
+ desc_id, desc_index, 0, desc_buf,
1291
+ &buff_len);
1292
+
1293
+ if (ret) {
1294
+ dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
1295
+ __func__, desc_id, desc_index, param_offset, ret);
1296
+ goto out;
1297
+ }
1298
+
1299
+ /* Sanity check */
1300
+ if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
1301
+ dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
1302
+ __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
1303
+ ret = -EINVAL;
1304
+ goto out;
1305
+ }
1306
+
1307
+ /* Check wherher we will not copy more data, than available */
1308
+ if (is_kmalloc && param_size > buff_len)
1309
+ param_size = buff_len;
1310
+
1311
+ if (is_kmalloc)
1312
+ memcpy(param_read_buf, &desc_buf[param_offset], param_size);
1313
+out:
1314
+ if (is_kmalloc)
1315
+ kfree(desc_buf);
1316
+ return ret;
1317
+}
1318
+
1319
+/* replace non-printable or non-ASCII characters with spaces */
1320
+static inline void ufshcd_remove_non_printable(uint8_t *val)
1321
+{
1322
+ if (!val)
1323
+ return;
1324
+
1325
+ if (*val < 0x20 || *val > 0x7e)
1326
+ *val = ' ';
1327
+}
1328
+
1329
+/**
1330
+ * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
1331
+ * state) and waits for it to take effect.
1332
+ *
1333
+ */
1334
+static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
1335
+{
1336
+ unsigned long start = 0;
1337
+ u8 status;
1338
+ int ret;
1339
+
1340
+ ret = ufshcd_send_uic_cmd(hba, cmd);
1341
+ if (ret) {
1342
+ dev_err(hba->dev,
1343
+ "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
1344
+ cmd->command, cmd->argument3, ret);
1345
+
1346
+ return ret;
1347
+ }
1348
+
1349
+ start = get_timer(0);
1350
+ do {
1351
+ status = ufshcd_get_upmcrs(hba);
1352
+ if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) {
1353
+ dev_err(hba->dev,
1354
+ "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
1355
+ cmd->command, status);
1356
+ ret = (status != PWR_OK) ? status : -1;
1357
+ break;
1358
+ }
1359
+ } while (status != PWR_LOCAL);
1360
+
1361
+ return ret;
1362
+}
1363
+
1364
+/**
1365
+ * ufshcd_uic_change_pwr_mode - Perform the UIC power mode change
1366
+ * using DME_SET primitives.
1367
+ */
1368
+static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
1369
+{
1370
+ struct uic_command uic_cmd = {0};
1371
+ int ret;
1372
+
1373
+ uic_cmd.command = UIC_CMD_DME_SET;
1374
+ uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
1375
+ uic_cmd.argument3 = mode;
1376
+ ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
1377
+
1378
+ return ret;
1379
+}
1380
+
1381
+static
1382
+void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba,
1383
+ struct scsi_cmd *pccb, u32 upiu_flags)
1384
+{
1385
+ struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
1386
+ unsigned int cdb_len;
1387
+
1388
+ /* command descriptor fields */
1389
+ ucd_req_ptr->header.dword_0 =
1390
+ UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND, upiu_flags,
1391
+ pccb->lun, TASK_TAG);
1392
+ ucd_req_ptr->header.dword_1 =
1393
+ UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
1394
+
1395
+ /* Total EHS length and Data segment length will be zero */
1396
+ ucd_req_ptr->header.dword_2 = 0;
1397
+
1398
+ ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(pccb->datalen);
1399
+
1400
+ cdb_len = min_t(unsigned short, pccb->cmdlen, UFS_CDB_SIZE);
1401
+ memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
1402
+ memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len);
1403
+
1404
+ memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
1405
+}
1406
+
1407
+static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry,
1408
+ unsigned char *buf, ulong len)
1409
+{
1410
+ entry->size = cpu_to_le32(len) | GENMASK(1, 0);
1411
+ entry->base_addr = cpu_to_le32(lower_32_bits((unsigned long)buf));
1412
+ entry->upper_addr = cpu_to_le32(upper_32_bits((unsigned long)buf));
1413
+}
1414
+
1415
+static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb)
1416
+{
1417
+ struct utp_transfer_req_desc *req_desc = hba->utrdl;
1418
+ struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr;
1419
+ ulong datalen = pccb->datalen;
1420
+ int table_length;
1421
+ u8 *buf;
1422
+ int i;
1423
+
1424
+ if (!datalen) {
1425
+ req_desc->prd_table_length = 0;
1426
+ return;
1427
+ }
1428
+
1429
+ table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY);
1430
+ buf = pccb->pdata;
1431
+ i = table_length;
1432
+ while (--i) {
1433
+ prepare_prdt_desc(&prd_table[table_length - i - 1], buf,
1434
+ MAX_PRDT_ENTRY - 1);
1435
+ buf += MAX_PRDT_ENTRY;
1436
+ datalen -= MAX_PRDT_ENTRY;
1437
+ }
1438
+
1439
+ prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1);
1440
+
1441
+ req_desc->prd_table_length = table_length;
1442
+}
1443
+
1444
+static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb)
1445
+{
1446
+ struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent);
1447
+ struct utp_transfer_req_desc *req_desc = hba->utrdl;
1448
+ u32 upiu_flags;
1449
+ int ocs, result = 0;
1450
+ u8 scsi_status;
1451
+
1452
+ ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, pccb->dma_dir);
1453
+ ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags);
1454
+ prepare_prdt_table(hba, pccb);
1455
+
1456
+ ufshcd_send_command(hba, TASK_TAG);
1457
+
1458
+ ocs = ufshcd_get_tr_ocs(hba);
1459
+ switch (ocs) {
1460
+ case OCS_SUCCESS:
1461
+ result = ufshcd_get_req_rsp(hba->ucd_rsp_ptr);
1462
+ switch (result) {
1463
+ case UPIU_TRANSACTION_RESPONSE:
1464
+ result = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr);
1465
+
1466
+ scsi_status = result & MASK_SCSI_STATUS;
1467
+ if (scsi_status)
1468
+ return -EINVAL;
1469
+
1470
+ break;
1471
+ case UPIU_TRANSACTION_REJECT_UPIU:
1472
+ /* TODO: handle Reject UPIU Response */
1473
+ dev_err(hba->dev,
1474
+ "Reject UPIU not fully implemented\n");
1475
+ return -EINVAL;
1476
+ default:
1477
+ dev_err(hba->dev,
1478
+ "Unexpected request response code = %x\n",
1479
+ result);
1480
+ return -EINVAL;
1481
+ }
1482
+ break;
1483
+ default:
1484
+ dev_err(hba->dev, "OCS error from controller = %x\n", ocs);
1485
+ return -EINVAL;
1486
+ }
1487
+
1488
+ return 0;
1489
+}
1490
+
1491
+static inline int ufshcd_read_desc(struct ufs_hba *hba, enum desc_idn desc_id,
1492
+ int desc_index, u8 *buf, u32 size)
1493
+{
1494
+ return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
1495
+}
1496
+
1497
+static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
1498
+{
1499
+ return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
1500
+}
1501
+
1502
+/**
1503
+ * ufshcd_read_string_desc - read string descriptor
1504
+ *
1505
+ */
1506
+int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
1507
+ u8 *buf, u32 size, bool ascii)
1508
+{
1509
+ int err = 0;
1510
+
1511
+ err = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING, desc_index, buf,
1512
+ size);
1513
+
1514
+ if (err) {
1515
+ dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
1516
+ __func__, QUERY_REQ_RETRIES, err);
1517
+ goto out;
1518
+ }
1519
+
1520
+ if (ascii) {
1521
+ int desc_len;
1522
+ int ascii_len;
1523
+ int i;
1524
+ u8 *buff_ascii;
1525
+
1526
+ desc_len = buf[0];
1527
+ /* remove header and divide by 2 to move from UTF16 to UTF8 */
1528
+ ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
1529
+ if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
1530
+ dev_err(hba->dev, "%s: buffer allocated size is too small\n",
1531
+ __func__);
1532
+ err = -ENOMEM;
1533
+ goto out;
1534
+ }
1535
+
1536
+ buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
1537
+ if (!buff_ascii) {
1538
+ err = -ENOMEM;
1539
+ goto out;
1540
+ }
1541
+
1542
+ /*
1543
+ * the descriptor contains string in UTF16 format
1544
+ * we need to convert to utf-8 so it can be displayed
1545
+ */
1546
+ utf16_to_utf8(buff_ascii,
1547
+ (uint16_t *)&buf[QUERY_DESC_HDR_SIZE], ascii_len);
1548
+
1549
+ /* replace non-printable or non-ASCII characters with spaces */
1550
+ for (i = 0; i < ascii_len; i++)
1551
+ ufshcd_remove_non_printable(&buff_ascii[i]);
1552
+
1553
+ memset(buf + QUERY_DESC_HDR_SIZE, 0,
1554
+ size - QUERY_DESC_HDR_SIZE);
1555
+ memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
1556
+ buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
1557
+ kfree(buff_ascii);
1558
+ }
1559
+out:
1560
+ return err;
1561
+}
1562
+
1563
+static int ufs_get_device_desc(struct ufs_hba *hba,
1564
+ struct ufs_dev_desc *dev_desc)
1565
+{
1566
+ int err;
1567
+ size_t buff_len;
1568
+ u8 model_index;
1569
+ u8 *desc_buf;
1570
+
1571
+ buff_len = max_t(size_t, hba->desc_size.dev_desc,
1572
+ QUERY_DESC_MAX_SIZE + 1);
1573
+ desc_buf = kmalloc(buff_len, GFP_KERNEL);
1574
+ if (!desc_buf) {
1575
+ err = -ENOMEM;
1576
+ goto out;
1577
+ }
1578
+
1579
+ err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
1580
+ if (err) {
1581
+ dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
1582
+ __func__, err);
1583
+ goto out;
1584
+ }
1585
+
1586
+ /*
1587
+ * getting vendor (manufacturerID) and Bank Index in big endian
1588
+ * format
1589
+ */
1590
+ dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
1591
+ desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
1592
+
1593
+ model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
1594
+
1595
+ /* Zero-pad entire buffer for string termination. */
1596
+ memset(desc_buf, 0, buff_len);
1597
+
1598
+ err = ufshcd_read_string_desc(hba, model_index, desc_buf,
1599
+ QUERY_DESC_MAX_SIZE, true/*ASCII*/);
1600
+ if (err) {
1601
+ dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
1602
+ __func__, err);
1603
+ goto out;
1604
+ }
1605
+
1606
+ desc_buf[QUERY_DESC_MAX_SIZE] = '\0';
1607
+ strlcpy(dev_desc->model, (char *)(desc_buf + QUERY_DESC_HDR_SIZE),
1608
+ min_t(u8, desc_buf[QUERY_DESC_LENGTH_OFFSET],
1609
+ MAX_MODEL_LEN));
1610
+
1611
+ /* Null terminate the model string */
1612
+ dev_desc->model[MAX_MODEL_LEN] = '\0';
1613
+
1614
+out:
1615
+ kfree(desc_buf);
1616
+ return err;
1617
+}
1618
+
1619
+/**
1620
+ * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
1621
+ */
1622
+static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
1623
+{
1624
+ struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
1625
+
1626
+ if (hba->max_pwr_info.is_valid)
1627
+ return 0;
1628
+
1629
+ pwr_info->pwr_tx = FAST_MODE;
1630
+ pwr_info->pwr_rx = FAST_MODE;
1631
+ pwr_info->hs_rate = PA_HS_MODE_B;
1632
+
1633
+ /* Get the connected lane count */
1634
+ ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
1635
+ &pwr_info->lane_rx);
1636
+ ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
1637
+ &pwr_info->lane_tx);
1638
+
1639
+ if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
1640
+ dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
1641
+ __func__, pwr_info->lane_rx, pwr_info->lane_tx);
1642
+ return -EINVAL;
1643
+ }
1644
+
1645
+ /*
1646
+ * First, get the maximum gears of HS speed.
1647
+ * If a zero value, it means there is no HSGEAR capability.
1648
+ * Then, get the maximum gears of PWM speed.
1649
+ */
1650
+ ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
1651
+ if (!pwr_info->gear_rx) {
1652
+ ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
1653
+ &pwr_info->gear_rx);
1654
+ if (!pwr_info->gear_rx) {
1655
+ dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
1656
+ __func__, pwr_info->gear_rx);
1657
+ return -EINVAL;
1658
+ }
1659
+ pwr_info->pwr_rx = SLOW_MODE;
1660
+ }
1661
+
1662
+ ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
1663
+ &pwr_info->gear_tx);
1664
+ if (!pwr_info->gear_tx) {
1665
+ ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
1666
+ &pwr_info->gear_tx);
1667
+ if (!pwr_info->gear_tx) {
1668
+ dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
1669
+ __func__, pwr_info->gear_tx);
1670
+ return -EINVAL;
1671
+ }
1672
+ pwr_info->pwr_tx = SLOW_MODE;
1673
+ }
1674
+
1675
+ hba->max_pwr_info.is_valid = true;
1676
+ return 0;
1677
+}
1678
+
1679
+static int ufshcd_change_power_mode(struct ufs_hba *hba,
1680
+ struct ufs_pa_layer_attr *pwr_mode)
1681
+{
1682
+ int ret;
1683
+
1684
+ /* if already configured to the requested pwr_mode */
1685
+ if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
1686
+ pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
1687
+ pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
1688
+ pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
1689
+ pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
1690
+ pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
1691
+ pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
1692
+ dev_dbg(hba->dev, "%s: power already configured\n", __func__);
1693
+ return 0;
1694
+ }
1695
+
1696
+ /*
1697
+ * Configure attributes for power mode change with below.
1698
+ * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
1699
+ * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
1700
+ * - PA_HSSERIES
1701
+ */
1702
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
1703
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
1704
+ pwr_mode->lane_rx);
1705
+ if (pwr_mode->pwr_rx == FASTAUTO_MODE || pwr_mode->pwr_rx == FAST_MODE)
1706
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
1707
+ else
1708
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
1709
+
1710
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
1711
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
1712
+ pwr_mode->lane_tx);
1713
+ if (pwr_mode->pwr_tx == FASTAUTO_MODE || pwr_mode->pwr_tx == FAST_MODE)
1714
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
1715
+ else
1716
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
1717
+
1718
+ if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
1719
+ pwr_mode->pwr_tx == FASTAUTO_MODE ||
1720
+ pwr_mode->pwr_rx == FAST_MODE ||
1721
+ pwr_mode->pwr_tx == FAST_MODE)
1722
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
1723
+ pwr_mode->hs_rate);
1724
+
1725
+ ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 |
1726
+ pwr_mode->pwr_tx);
1727
+
1728
+ if (ret) {
1729
+ dev_err(hba->dev,
1730
+ "%s: power mode change failed %d\n", __func__, ret);
1731
+
1732
+ return ret;
1733
+ }
1734
+
1735
+ /* Copy new Power Mode to power info */
1736
+ memcpy(&hba->pwr_info, pwr_mode, sizeof(struct ufs_pa_layer_attr));
1737
+
1738
+ return ret;
1739
+}
1740
+
1741
+/**
1742
+ * ufshcd_verify_dev_init() - Verify device initialization
1743
+ *
1744
+ */
1745
+static int ufshcd_verify_dev_init(struct ufs_hba *hba)
1746
+{
1747
+ int retries;
1748
+ int err;
1749
+
1750
+ for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
1751
+ err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
1752
+ NOP_OUT_TIMEOUT);
1753
+ if (!err || err == -ETIMEDOUT)
1754
+ break;
1755
+
1756
+ dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
1757
+ }
1758
+
1759
+ if (err)
1760
+ dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
1761
+
1762
+ return err;
1763
+}
1764
+
1765
+/**
1766
+ * ufshcd_complete_dev_init() - checks device readiness
1767
+ */
1768
+static int ufshcd_complete_dev_init(struct ufs_hba *hba)
1769
+{
1770
+ int i;
1771
+ int err;
1772
+ bool flag_res = 1;
1773
+
1774
+ err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
1775
+ QUERY_FLAG_IDN_FDEVICEINIT, NULL);
1776
+ if (err) {
1777
+ dev_err(hba->dev,
1778
+ "%s setting fDeviceInit flag failed with error %d\n",
1779
+ __func__, err);
1780
+ goto out;
1781
+ }
1782
+
1783
+ /* poll for max. 1000 iterations for fDeviceInit flag to clear */
1784
+ for (i = 0; i < 1000 && !err && flag_res; i++)
1785
+ err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
1786
+ QUERY_FLAG_IDN_FDEVICEINIT,
1787
+ &flag_res);
1788
+
1789
+ if (err)
1790
+ dev_err(hba->dev,
1791
+ "%s reading fDeviceInit flag failed with error %d\n",
1792
+ __func__, err);
1793
+ else if (flag_res)
1794
+ dev_err(hba->dev,
1795
+ "%s fDeviceInit was not cleared by the device\n",
1796
+ __func__);
1797
+
1798
+out:
1799
+ return err;
1800
+}
1801
+
1802
+static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
1803
+{
1804
+ hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
1805
+ hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
1806
+ hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
1807
+ hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
1808
+ hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
1809
+ hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
1810
+ hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
1811
+}
1812
+
1813
+int ufs_start(struct ufs_hba *hba)
1814
+{
1815
+ struct ufs_dev_desc card = {0};
1816
+ int ret;
1817
+
1818
+ ret = ufshcd_link_startup(hba);
1819
+ if (ret)
1820
+ return ret;
1821
+
1822
+ ret = ufshcd_verify_dev_init(hba);
1823
+ if (ret)
1824
+ return ret;
1825
+
1826
+ ret = ufshcd_complete_dev_init(hba);
1827
+ if (ret)
1828
+ return ret;
1829
+
1830
+ /* Init check for device descriptor sizes */
1831
+ ufshcd_init_desc_sizes(hba);
1832
+
1833
+ ret = ufs_get_device_desc(hba, &card);
1834
+ if (ret) {
1835
+ dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
1836
+ __func__, ret);
1837
+
1838
+ return ret;
1839
+ }
1840
+
1841
+ if (ufshcd_get_max_pwr_mode(hba)) {
1842
+ dev_err(hba->dev,
1843
+ "%s: Failed getting max supported power mode\n",
1844
+ __func__);
1845
+ } else {
1846
+ ret = ufshcd_change_power_mode(hba, &hba->max_pwr_info.info);
1847
+ if (ret) {
1848
+ dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
1849
+ __func__, ret);
1850
+
1851
+ return ret;
1852
+ }
1853
+
1854
+ printf("Device at %s up at:", hba->dev->name);
1855
+ ufshcd_print_pwr_info(hba);
1856
+ }
1857
+
1858
+ return 0;
1859
+}
1860
+
1861
+int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
1862
+{
1863
+ struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev);
1864
+ struct scsi_platdata *scsi_plat;
1865
+ struct udevice *scsi_dev;
1866
+ int err;
1867
+
1868
+ device_find_first_child(ufs_dev, &scsi_dev);
1869
+ if (!scsi_dev)
1870
+ return -ENODEV;
1871
+
1872
+ scsi_plat = dev_get_uclass_platdata(scsi_dev);
1873
+ scsi_plat->max_id = UFSHCD_MAX_ID;
1874
+ scsi_plat->max_lun = UFS_MAX_LUNS;
1875
+ //scsi_plat->max_bytes_per_req = UFS_MAX_BYTES;
1876
+
1877
+ hba->dev = ufs_dev;
1878
+ hba->ops = hba_ops;
1879
+ hba->mmio_base = (void *)dev_read_addr(ufs_dev);
1880
+
1881
+ /* Set descriptor lengths to specification defaults */
1882
+ ufshcd_def_desc_sizes(hba);
1883
+
1884
+ ufshcd_ops_init(hba);
1885
+
1886
+ /* Read capabilties registers */
1887
+ hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
1888
+
1889
+ /* Get UFS version supported by the controller */
1890
+ hba->version = ufshcd_get_ufs_version(hba);
1891
+ if (hba->version != UFSHCI_VERSION_10 &&
1892
+ hba->version != UFSHCI_VERSION_11 &&
1893
+ hba->version != UFSHCI_VERSION_20 &&
1894
+ hba->version != UFSHCI_VERSION_21)
1895
+ dev_err(hba->dev, "invalid UFS version 0x%x\n",
1896
+ hba->version);
1897
+
1898
+ /* Get Interrupt bit mask per version */
1899
+ hba->intr_mask = ufshcd_get_intr_mask(hba);
1900
+
1901
+ /* Allocate memory for host memory space */
1902
+ err = ufshcd_memory_alloc(hba);
1903
+ if (err) {
1904
+ dev_err(hba->dev, "Memory allocation failed\n");
1905
+ return err;
1906
+ }
1907
+
1908
+ /* Configure Local data structures */
1909
+ ufshcd_host_memory_configure(hba);
1910
+
1911
+ /*
1912
+ * In order to avoid any spurious interrupt immediately after
1913
+ * registering UFS controller interrupt handler, clear any pending UFS
1914
+ * interrupt status and disable all the UFS interrupts.
1915
+ */
1916
+ ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
1917
+ REG_INTERRUPT_STATUS);
1918
+ ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
1919
+
1920
+ err = ufshcd_hba_enable(hba);
1921
+ if (err) {
1922
+ dev_err(hba->dev, "Host controller enable failed\n");
1923
+ return err;
1924
+ }
1925
+
1926
+ err = ufs_start(hba);
1927
+ if (err)
1928
+ return err;
1929
+
1930
+ return 0;
1931
+}
1932
+
1933
+int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp)
1934
+{
1935
+ int ret = device_bind_driver(ufs_dev, "ufs_scsi", "ufs_scsi",
1936
+ scsi_devp);
1937
+
1938
+ return ret;
1939
+}
1940
+
1941
+static struct scsi_ops ufs_ops = {
1942
+ .exec = ufs_scsi_exec,
1943
+};
1944
+
1945
+int ufs_probe_dev(int index)
1946
+{
1947
+ struct udevice *dev;
1948
+
1949
+ return uclass_get_device(UCLASS_UFS, index, &dev);
1950
+}
1951
+
1952
+int ufs_probe(void)
1953
+{
1954
+ struct udevice *dev;
1955
+ int ret, i;
1956
+
1957
+ for (i = 0;; i++) {
1958
+ ret = uclass_get_device(UCLASS_UFS, i, &dev);
1959
+ if (ret == -ENODEV)
1960
+ break;
1961
+ }
1962
+
1963
+ return 0;
1964
+}
1965
+
1966
+U_BOOT_DRIVER(ufs_scsi) = {
1967
+ .id = UCLASS_SCSI,
1968
+ .name = "ufs_scsi",
1969
+ .ops = &ufs_ops,
1970
+};
u-boot/drivers/ufs/ufs.h
....@@ -0,0 +1,917 @@
1
+/* SPDX-License-Identifier: GPL-2.0+ */
2
+#ifndef __UFS_H
3
+#define __UFS_H
4
+
5
+#include "unipro.h"
6
+
7
+struct udevice;
8
+
9
+#define UFS_CDB_SIZE 16
10
+#define UPIU_TRANSACTION_UIC_CMD 0x1F
11
+#define UIC_CMD_SIZE (sizeof(u32) * 4)
12
+#define RESPONSE_UPIU_SENSE_DATA_LENGTH 18
13
+#define UFS_MAX_LUNS 0x7F
14
+
15
+enum {
16
+ TASK_REQ_UPIU_SIZE_DWORDS = 8,
17
+ TASK_RSP_UPIU_SIZE_DWORDS = 8,
18
+ ALIGNED_UPIU_SIZE = 512,
19
+};
20
+
21
+/* UFS device power modes */
22
+enum ufs_dev_pwr_mode {
23
+ UFS_ACTIVE_PWR_MODE = 1,
24
+ UFS_SLEEP_PWR_MODE = 2,
25
+ UFS_POWERDOWN_PWR_MODE = 3,
26
+};
27
+
28
+enum ufs_notify_change_status {
29
+ PRE_CHANGE,
30
+ POST_CHANGE,
31
+};
32
+
33
+struct ufs_pa_layer_attr {
34
+ u32 gear_rx;
35
+ u32 gear_tx;
36
+ u32 lane_rx;
37
+ u32 lane_tx;
38
+ u32 pwr_rx;
39
+ u32 pwr_tx;
40
+ u32 hs_rate;
41
+};
42
+
43
+struct ufs_pwr_mode_info {
44
+ bool is_valid;
45
+ struct ufs_pa_layer_attr info;
46
+};
47
+
48
+enum ufs_desc_def_size {
49
+ QUERY_DESC_DEVICE_DEF_SIZE = 0x40,
50
+ QUERY_DESC_CONFIGURATION_DEF_SIZE = 0x90,
51
+ QUERY_DESC_UNIT_DEF_SIZE = 0x23,
52
+ QUERY_DESC_INTERCONNECT_DEF_SIZE = 0x06,
53
+ QUERY_DESC_GEOMETRY_DEF_SIZE = 0x48,
54
+ QUERY_DESC_POWER_DEF_SIZE = 0x62,
55
+ QUERY_DESC_HEALTH_DEF_SIZE = 0x25,
56
+};
57
+
58
+struct ufs_desc_size {
59
+ int dev_desc;
60
+ int pwr_desc;
61
+ int geom_desc;
62
+ int interc_desc;
63
+ int unit_desc;
64
+ int conf_desc;
65
+ int hlth_desc;
66
+};
67
+
68
+/*
69
+ * Request Descriptor Definitions
70
+ */
71
+
72
+/* Transfer request command type */
73
+enum {
74
+ UTP_CMD_TYPE_SCSI = 0x0,
75
+ UTP_CMD_TYPE_UFS = 0x1,
76
+ UTP_CMD_TYPE_DEV_MANAGE = 0x2,
77
+};
78
+
79
+/* UTP Transfer Request Command Offset */
80
+#define UPIU_COMMAND_TYPE_OFFSET 28
81
+
82
+/* Offset of the response code in the UPIU header */
83
+#define UPIU_RSP_CODE_OFFSET 8
84
+
85
+/* To accommodate UFS2.0 required Command type */
86
+enum {
87
+ UTP_CMD_TYPE_UFS_STORAGE = 0x1,
88
+};
89
+
90
+enum {
91
+ UTP_SCSI_COMMAND = 0x00000000,
92
+ UTP_NATIVE_UFS_COMMAND = 0x10000000,
93
+ UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
94
+ UTP_REQ_DESC_INT_CMD = 0x01000000,
95
+};
96
+
97
+/* UTP Transfer Request Data Direction (DD) */
98
+enum {
99
+ UTP_NO_DATA_TRANSFER = 0x00000000,
100
+ UTP_HOST_TO_DEVICE = 0x02000000,
101
+ UTP_DEVICE_TO_HOST = 0x04000000,
102
+};
103
+
104
+/* Overall command status values */
105
+enum {
106
+ OCS_SUCCESS = 0x0,
107
+ OCS_INVALID_CMD_TABLE_ATTR = 0x1,
108
+ OCS_INVALID_PRDT_ATTR = 0x2,
109
+ OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
110
+ OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
111
+ OCS_PEER_COMM_FAILURE = 0x5,
112
+ OCS_ABORTED = 0x6,
113
+ OCS_FATAL_ERROR = 0x7,
114
+ OCS_INVALID_COMMAND_STATUS = 0x0F,
115
+ MASK_OCS = 0x0F,
116
+};
117
+
118
+/* The maximum length of the data byte count field in the PRDT is 256KB */
119
+#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
120
+/* The granularity of the data byte count field in the PRDT is 32-bit */
121
+#define PRDT_DATA_BYTE_COUNT_PAD 4
122
+
123
+#define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
124
+#define QUERY_DESC_MAX_SIZE 255
125
+#define QUERY_DESC_MIN_SIZE 2
126
+#define QUERY_DESC_HDR_SIZE 2
127
+#define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \
128
+ (sizeof(struct utp_upiu_header)))
129
+#define RESPONSE_UPIU_SENSE_DATA_LENGTH 18
130
+#define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
131
+ cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
132
+ (byte1 << 8) | (byte0))
133
+/*
134
+ * UFS Protocol Information Unit related definitions
135
+ */
136
+
137
+/* Task management functions */
138
+enum {
139
+ UFS_ABORT_TASK = 0x01,
140
+ UFS_ABORT_TASK_SET = 0x02,
141
+ UFS_CLEAR_TASK_SET = 0x04,
142
+ UFS_LOGICAL_RESET = 0x08,
143
+ UFS_QUERY_TASK = 0x80,
144
+ UFS_QUERY_TASK_SET = 0x81,
145
+};
146
+
147
+/* UTP UPIU Transaction Codes Initiator to Target */
148
+enum {
149
+ UPIU_TRANSACTION_NOP_OUT = 0x00,
150
+ UPIU_TRANSACTION_COMMAND = 0x01,
151
+ UPIU_TRANSACTION_DATA_OUT = 0x02,
152
+ UPIU_TRANSACTION_TASK_REQ = 0x04,
153
+ UPIU_TRANSACTION_QUERY_REQ = 0x16,
154
+};
155
+
156
+/* UTP UPIU Transaction Codes Target to Initiator */
157
+enum {
158
+ UPIU_TRANSACTION_NOP_IN = 0x20,
159
+ UPIU_TRANSACTION_RESPONSE = 0x21,
160
+ UPIU_TRANSACTION_DATA_IN = 0x22,
161
+ UPIU_TRANSACTION_TASK_RSP = 0x24,
162
+ UPIU_TRANSACTION_READY_XFER = 0x31,
163
+ UPIU_TRANSACTION_QUERY_RSP = 0x36,
164
+ UPIU_TRANSACTION_REJECT_UPIU = 0x3F,
165
+};
166
+
167
+/* UPIU Read/Write flags */
168
+enum {
169
+ UPIU_CMD_FLAGS_NONE = 0x00,
170
+ UPIU_CMD_FLAGS_WRITE = 0x20,
171
+ UPIU_CMD_FLAGS_READ = 0x40,
172
+};
173
+
174
+/* UPIU Task Attributes */
175
+enum {
176
+ UPIU_TASK_ATTR_SIMPLE = 0x00,
177
+ UPIU_TASK_ATTR_ORDERED = 0x01,
178
+ UPIU_TASK_ATTR_HEADQ = 0x02,
179
+ UPIU_TASK_ATTR_ACA = 0x03,
180
+};
181
+
182
+/* UPIU Query request function */
183
+enum {
184
+ UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01,
185
+ UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81,
186
+};
187
+
188
+/* Offset of the response code in the UPIU header */
189
+#define UPIU_RSP_CODE_OFFSET 8
190
+
191
+enum {
192
+ MASK_SCSI_STATUS = 0xFF,
193
+ MASK_TASK_RESPONSE = 0xFF00,
194
+ MASK_RSP_UPIU_RESULT = 0xFFFF,
195
+ MASK_QUERY_DATA_SEG_LEN = 0xFFFF,
196
+ MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF,
197
+ MASK_RSP_EXCEPTION_EVENT = 0x10000,
198
+ MASK_TM_SERVICE_RESP = 0xFF,
199
+ MASK_TM_FUNC = 0xFF,
200
+};
201
+
202
+/* UTP QUERY Transaction Specific Fields OpCode */
203
+enum query_opcode {
204
+ UPIU_QUERY_OPCODE_NOP = 0x0,
205
+ UPIU_QUERY_OPCODE_READ_DESC = 0x1,
206
+ UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
207
+ UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
208
+ UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
209
+ UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
210
+ UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
211
+ UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
212
+ UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
213
+};
214
+
215
+/* Query response result code */
216
+enum {
217
+ QUERY_RESULT_SUCCESS = 0x00,
218
+ QUERY_RESULT_NOT_READABLE = 0xF6,
219
+ QUERY_RESULT_NOT_WRITEABLE = 0xF7,
220
+ QUERY_RESULT_ALREADY_WRITTEN = 0xF8,
221
+ QUERY_RESULT_INVALID_LENGTH = 0xF9,
222
+ QUERY_RESULT_INVALID_VALUE = 0xFA,
223
+ QUERY_RESULT_INVALID_SELECTOR = 0xFB,
224
+ QUERY_RESULT_INVALID_INDEX = 0xFC,
225
+ QUERY_RESULT_INVALID_IDN = 0xFD,
226
+ QUERY_RESULT_INVALID_OPCODE = 0xFE,
227
+ QUERY_RESULT_GENERAL_FAILURE = 0xFF,
228
+};
229
+
230
+enum {
231
+ UPIU_COMMAND_SET_TYPE_SCSI = 0x0,
232
+ UPIU_COMMAND_SET_TYPE_UFS = 0x1,
233
+ UPIU_COMMAND_SET_TYPE_QUERY = 0x2,
234
+};
235
+
236
+/* Flag idn for Query Requests*/
237
+enum flag_idn {
238
+ QUERY_FLAG_IDN_FDEVICEINIT = 0x01,
239
+ QUERY_FLAG_IDN_PERMANENT_WPE = 0x02,
240
+ QUERY_FLAG_IDN_PWR_ON_WPE = 0x03,
241
+ QUERY_FLAG_IDN_BKOPS_EN = 0x04,
242
+ QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05,
243
+ QUERY_FLAG_IDN_PURGE_ENABLE = 0x06,
244
+ QUERY_FLAG_IDN_RESERVED2 = 0x07,
245
+ QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08,
246
+ QUERY_FLAG_IDN_BUSY_RTC = 0x09,
247
+ QUERY_FLAG_IDN_RESERVED3 = 0x0A,
248
+ QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B,
249
+};
250
+
251
+/* Attribute idn for Query requests */
252
+enum attr_idn {
253
+ QUERY_ATTR_IDN_BOOT_LU_EN = 0x00,
254
+ QUERY_ATTR_IDN_RESERVED = 0x01,
255
+ QUERY_ATTR_IDN_POWER_MODE = 0x02,
256
+ QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03,
257
+ QUERY_ATTR_IDN_OOO_DATA_EN = 0x04,
258
+ QUERY_ATTR_IDN_BKOPS_STATUS = 0x05,
259
+ QUERY_ATTR_IDN_PURGE_STATUS = 0x06,
260
+ QUERY_ATTR_IDN_MAX_DATA_IN = 0x07,
261
+ QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08,
262
+ QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09,
263
+ QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A,
264
+ QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B,
265
+ QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C,
266
+ QUERY_ATTR_IDN_EE_CONTROL = 0x0D,
267
+ QUERY_ATTR_IDN_EE_STATUS = 0x0E,
268
+ QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F,
269
+ QUERY_ATTR_IDN_CNTX_CONF = 0x10,
270
+ QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11,
271
+ QUERY_ATTR_IDN_RESERVED2 = 0x12,
272
+ QUERY_ATTR_IDN_RESERVED3 = 0x13,
273
+ QUERY_ATTR_IDN_FFU_STATUS = 0x14,
274
+ QUERY_ATTR_IDN_PSA_STATE = 0x15,
275
+ QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16,
276
+};
277
+
278
+/* Descriptor idn for Query requests */
279
+enum desc_idn {
280
+ QUERY_DESC_IDN_DEVICE = 0x0,
281
+ QUERY_DESC_IDN_CONFIGURATION = 0x1,
282
+ QUERY_DESC_IDN_UNIT = 0x2,
283
+ QUERY_DESC_IDN_RFU_0 = 0x3,
284
+ QUERY_DESC_IDN_INTERCONNECT = 0x4,
285
+ QUERY_DESC_IDN_STRING = 0x5,
286
+ QUERY_DESC_IDN_RFU_1 = 0x6,
287
+ QUERY_DESC_IDN_GEOMETRY = 0x7,
288
+ QUERY_DESC_IDN_POWER = 0x8,
289
+ QUERY_DESC_IDN_HEALTH = 0x9,
290
+ QUERY_DESC_IDN_MAX,
291
+};
292
+
293
+enum desc_header_offset {
294
+ QUERY_DESC_LENGTH_OFFSET = 0x00,
295
+ QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
296
+};
297
+
298
+struct ufshcd_sg_entry {
299
+ __le32 base_addr;
300
+ __le32 upper_addr;
301
+ __le32 reserved;
302
+ __le32 size;
303
+};
304
+
305
+#define MAX_BUFF 128
306
+/**
307
+ * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
308
+ * @command_upiu: Command UPIU Frame address
309
+ * @response_upiu: Response UPIU Frame address
310
+ * @prd_table: Physical Region Descriptor
311
+ */
312
+struct utp_transfer_cmd_desc {
313
+ u8 command_upiu[ALIGNED_UPIU_SIZE];
314
+ u8 response_upiu[ALIGNED_UPIU_SIZE];
315
+ struct ufshcd_sg_entry prd_table[MAX_BUFF];
316
+};
317
+
318
+/**
319
+ * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
320
+ * @dword0: Descriptor Header DW0
321
+ * @dword1: Descriptor Header DW1
322
+ * @dword2: Descriptor Header DW2
323
+ * @dword3: Descriptor Header DW3
324
+ */
325
+struct request_desc_header {
326
+ __le32 dword_0;
327
+ __le32 dword_1;
328
+ __le32 dword_2;
329
+ __le32 dword_3;
330
+};
331
+
332
+/**
333
+ * struct utp_transfer_req_desc - UTRD structure
334
+ * @header: UTRD header DW-0 to DW-3
335
+ * @command_desc_base_addr_lo: UCD base address low DW-4
336
+ * @command_desc_base_addr_hi: UCD base address high DW-5
337
+ * @response_upiu_length: response UPIU length DW-6
338
+ * @response_upiu_offset: response UPIU offset DW-6
339
+ * @prd_table_length: Physical region descriptor length DW-7
340
+ * @prd_table_offset: Physical region descriptor offset DW-7
341
+ */
342
+struct utp_transfer_req_desc {
343
+ /* DW 0-3 */
344
+ struct request_desc_header header;
345
+
346
+ /* DW 4-5*/
347
+ __le32 command_desc_base_addr_lo;
348
+ __le32 command_desc_base_addr_hi;
349
+
350
+ /* DW 6 */
351
+ __le16 response_upiu_length;
352
+ __le16 response_upiu_offset;
353
+
354
+ /* DW 7 */
355
+ __le16 prd_table_length;
356
+ __le16 prd_table_offset;
357
+};
358
+
359
+/**
360
+ * struct utp_upiu_header - UPIU header structure
361
+ * @dword_0: UPIU header DW-0
362
+ * @dword_1: UPIU header DW-1
363
+ * @dword_2: UPIU header DW-2
364
+ */
365
+struct utp_upiu_header {
366
+ __be32 dword_0;
367
+ __be32 dword_1;
368
+ __be32 dword_2;
369
+};
370
+
371
+/**
372
+ * struct utp_upiu_query - upiu request buffer structure for
373
+ * query request.
374
+ * @opcode: command to perform B-0
375
+ * @idn: a value that indicates the particular type of data B-1
376
+ * @index: Index to further identify data B-2
377
+ * @selector: Index to further identify data B-3
378
+ * @reserved_osf: spec reserved field B-4,5
379
+ * @length: number of descriptor bytes to read/write B-6,7
380
+ * @value: Attribute value to be written DW-5
381
+ * @reserved: spec reserved DW-6,7
382
+ */
383
+struct utp_upiu_query {
384
+ __u8 opcode;
385
+ __u8 idn;
386
+ __u8 index;
387
+ __u8 selector;
388
+ __be16 reserved_osf;
389
+ __be16 length;
390
+ __be32 value;
391
+ __be32 reserved[2];
392
+};
393
+
394
+/**
395
+ * struct utp_upiu_cmd - Command UPIU structure
396
+ * @data_transfer_len: Data Transfer Length DW-3
397
+ * @cdb: Command Descriptor Block CDB DW-4 to DW-7
398
+ */
399
+struct utp_upiu_cmd {
400
+ __be32 exp_data_transfer_len;
401
+ u8 cdb[UFS_CDB_SIZE];
402
+};
403
+
404
+/*
405
+ * UTMRD structure.
406
+ */
407
+struct utp_task_req_desc {
408
+ /* DW 0-3 */
409
+ struct request_desc_header header;
410
+
411
+ /* DW 4-11 - Task request UPIU structure */
412
+ struct utp_upiu_header req_header;
413
+ __be32 input_param1;
414
+ __be32 input_param2;
415
+ __be32 input_param3;
416
+ __be32 __reserved1[2];
417
+
418
+ /* DW 12-19 - Task Management Response UPIU structure */
419
+ struct utp_upiu_header rsp_header;
420
+ __be32 output_param1;
421
+ __be32 output_param2;
422
+ __be32 __reserved2[3];
423
+};
424
+
425
+/**
426
+ * struct utp_upiu_req - general upiu request structure
427
+ * @header:UPIU header structure DW-0 to DW-2
428
+ * @sc: fields structure for scsi command DW-3 to DW-7
429
+ * @qr: fields structure for query request DW-3 to DW-7
430
+ */
431
+struct utp_upiu_req {
432
+ struct utp_upiu_header header;
433
+ union {
434
+ struct utp_upiu_cmd sc;
435
+ struct utp_upiu_query qr;
436
+ struct utp_upiu_query tr;
437
+ /* use utp_upiu_query to host the 4 dwords of uic command */
438
+ struct utp_upiu_query uc;
439
+ };
440
+};
441
+
442
+/**
443
+ * struct utp_cmd_rsp - Response UPIU structure
444
+ * @residual_transfer_count: Residual transfer count DW-3
445
+ * @reserved: Reserved double words DW-4 to DW-7
446
+ * @sense_data_len: Sense data length DW-8 U16
447
+ * @sense_data: Sense data field DW-8 to DW-12
448
+ */
449
+struct utp_cmd_rsp {
450
+ __be32 residual_transfer_count;
451
+ __be32 reserved[4];
452
+ __be16 sense_data_len;
453
+ u8 sense_data[RESPONSE_UPIU_SENSE_DATA_LENGTH];
454
+};
455
+
456
+/**
457
+ * struct utp_upiu_rsp - general upiu response structure
458
+ * @header: UPIU header structure DW-0 to DW-2
459
+ * @sr: fields structure for scsi command DW-3 to DW-12
460
+ * @qr: fields structure for query request DW-3 to DW-7
461
+ */
462
+struct utp_upiu_rsp {
463
+ struct utp_upiu_header header;
464
+ union {
465
+ struct utp_cmd_rsp sr;
466
+ struct utp_upiu_query qr;
467
+ };
468
+};
469
+
470
+#define MAX_MODEL_LEN 16
471
+/**
472
+ * ufs_dev_desc - ufs device details from the device descriptor
473
+ *
474
+ * @wmanufacturerid: card details
475
+ * @model: card model
476
+ */
477
+struct ufs_dev_desc {
478
+ u16 wmanufacturerid;
479
+ char model[MAX_MODEL_LEN + 1];
480
+};
481
+
482
+/* Device descriptor parameters offsets in bytes*/
483
+enum device_desc_param {
484
+ DEVICE_DESC_PARAM_LEN = 0x0,
485
+ DEVICE_DESC_PARAM_TYPE = 0x1,
486
+ DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2,
487
+ DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3,
488
+ DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4,
489
+ DEVICE_DESC_PARAM_PRTCL = 0x5,
490
+ DEVICE_DESC_PARAM_NUM_LU = 0x6,
491
+ DEVICE_DESC_PARAM_NUM_WLU = 0x7,
492
+ DEVICE_DESC_PARAM_BOOT_ENBL = 0x8,
493
+ DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9,
494
+ DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA,
495
+ DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB,
496
+ DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC,
497
+ DEVICE_DESC_PARAM_SEC_LU = 0xD,
498
+ DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE,
499
+ DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF,
500
+ DEVICE_DESC_PARAM_SPEC_VER = 0x10,
501
+ DEVICE_DESC_PARAM_MANF_DATE = 0x12,
502
+ DEVICE_DESC_PARAM_MANF_NAME = 0x14,
503
+ DEVICE_DESC_PARAM_PRDCT_NAME = 0x15,
504
+ DEVICE_DESC_PARAM_SN = 0x16,
505
+ DEVICE_DESC_PARAM_OEM_ID = 0x17,
506
+ DEVICE_DESC_PARAM_MANF_ID = 0x18,
507
+ DEVICE_DESC_PARAM_UD_OFFSET = 0x1A,
508
+ DEVICE_DESC_PARAM_UD_LEN = 0x1B,
509
+ DEVICE_DESC_PARAM_RTT_CAP = 0x1C,
510
+ DEVICE_DESC_PARAM_FRQ_RTC = 0x1D,
511
+ DEVICE_DESC_PARAM_UFS_FEAT = 0x1F,
512
+ DEVICE_DESC_PARAM_FFU_TMT = 0x20,
513
+ DEVICE_DESC_PARAM_Q_DPTH = 0x21,
514
+ DEVICE_DESC_PARAM_DEV_VER = 0x22,
515
+ DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24,
516
+ DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25,
517
+ DEVICE_DESC_PARAM_PSA_TMT = 0x29,
518
+ DEVICE_DESC_PARAM_PRDCT_REV = 0x2A,
519
+};
520
+
521
+struct ufs_hba;
522
+
523
+enum {
524
+ UFSHCD_MAX_CHANNEL = 0,
525
+ UFSHCD_MAX_ID = 1,
526
+};
527
+
528
+enum dev_cmd_type {
529
+ DEV_CMD_TYPE_NOP = 0x0,
530
+ DEV_CMD_TYPE_QUERY = 0x1,
531
+};
532
+
533
+/**
534
+ * struct uic_command - UIC command structure
535
+ * @command: UIC command
536
+ * @argument1: UIC command argument 1
537
+ * @argument2: UIC command argument 2
538
+ * @argument3: UIC command argument 3
539
+ * @cmd_active: Indicate if UIC command is outstanding
540
+ * @result: UIC command result
541
+ * @done: UIC command completion
542
+ */
543
+struct uic_command {
544
+ u32 command;
545
+ u32 argument1;
546
+ u32 argument2;
547
+ u32 argument3;
548
+ int cmd_active;
549
+ int result;
550
+};
551
+
552
+/* GenSelectorIndex calculation macros for M-PHY attributes */
553
+#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
554
+#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
555
+
556
+#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
557
+ ((sel) & 0xFFFF))
558
+#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
559
+#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
560
+#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
561
+
562
+/* Link Status*/
563
+enum link_status {
564
+ UFSHCD_LINK_IS_DOWN = 1,
565
+ UFSHCD_LINK_IS_UP = 2,
566
+};
567
+
568
+#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
569
+ ((sel) & 0xFFFF))
570
+#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
571
+#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
572
+#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
573
+
574
+/* UIC Commands */
575
+enum uic_cmd_dme {
576
+ UIC_CMD_DME_GET = 0x01,
577
+ UIC_CMD_DME_SET = 0x02,
578
+ UIC_CMD_DME_PEER_GET = 0x03,
579
+ UIC_CMD_DME_PEER_SET = 0x04,
580
+ UIC_CMD_DME_POWERON = 0x10,
581
+ UIC_CMD_DME_POWEROFF = 0x11,
582
+ UIC_CMD_DME_ENABLE = 0x12,
583
+ UIC_CMD_DME_RESET = 0x14,
584
+ UIC_CMD_DME_END_PT_RST = 0x15,
585
+ UIC_CMD_DME_LINK_STARTUP = 0x16,
586
+ UIC_CMD_DME_HIBER_ENTER = 0x17,
587
+ UIC_CMD_DME_HIBER_EXIT = 0x18,
588
+ UIC_CMD_DME_TEST_MODE = 0x1A,
589
+};
590
+
591
+/* UIC Config result code / Generic error code */
592
+enum {
593
+ UIC_CMD_RESULT_SUCCESS = 0x00,
594
+ UIC_CMD_RESULT_INVALID_ATTR = 0x01,
595
+ UIC_CMD_RESULT_FAILURE = 0x01,
596
+ UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
597
+ UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
598
+ UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
599
+ UIC_CMD_RESULT_BAD_INDEX = 0x05,
600
+ UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
601
+ UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
602
+ UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
603
+ UIC_CMD_RESULT_BUSY = 0x09,
604
+ UIC_CMD_RESULT_DME_FAILURE = 0x0A,
605
+};
606
+
607
+#define MASK_UIC_COMMAND_RESULT 0xFF
608
+
609
+/* Host <-> Device UniPro Link state */
610
+enum uic_link_state {
611
+ UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
612
+ UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
613
+ UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
614
+};
615
+
616
+/* UIC command interfaces for DME primitives */
617
+#define DME_LOCAL 0
618
+#define DME_PEER 1
619
+#define ATTR_SET_NOR 0 /* NORMAL */
620
+#define ATTR_SET_ST 1 /* STATIC */
621
+
622
+int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
623
+ u8 attr_set, u32 mib_val, u8 peer);
624
+int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
625
+ u32 *mib_val, u8 peer);
626
+
627
+static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
628
+ u32 mib_val)
629
+{
630
+ return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
631
+ mib_val, DME_LOCAL);
632
+}
633
+
634
+static inline int ufshcd_dme_get(struct ufs_hba *hba,
635
+ u32 attr_sel, u32 *mib_val)
636
+{
637
+ return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
638
+}
639
+
640
+static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
641
+ u32 attr_sel, u32 *mib_val)
642
+{
643
+ return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
644
+}
645
+
646
+static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
647
+ u32 mib_val)
648
+{
649
+ return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
650
+ mib_val, DME_PEER);
651
+}
652
+
653
+/**
654
+ * struct ufs_query_req - parameters for building a query request
655
+ * @query_func: UPIU header query function
656
+ * @upiu_req: the query request data
657
+ */
658
+struct ufs_query_req {
659
+ u8 query_func;
660
+ struct utp_upiu_query upiu_req;
661
+};
662
+
663
+/**
664
+ * struct ufs_query_resp - UPIU QUERY
665
+ * @response: device response code
666
+ * @upiu_res: query response data
667
+ */
668
+struct ufs_query_res {
669
+ u8 response;
670
+ struct utp_upiu_query upiu_res;
671
+};
672
+
673
+/**
674
+ * struct ufs_query - holds relevant data structures for query request
675
+ * @request: request upiu and function
676
+ * @descriptor: buffer for sending/receiving descriptor
677
+ * @response: response upiu and response
678
+ */
679
+struct ufs_query {
680
+ struct ufs_query_req request;
681
+ u8 *descriptor;
682
+ struct ufs_query_res response;
683
+};
684
+
685
+/**
686
+ * struct ufs_dev_cmd - all assosiated fields with device management commands
687
+ * @type: device management command type - Query, NOP OUT
688
+ * @tag_wq: wait queue until free command slot is available
689
+ */
690
+struct ufs_dev_cmd {
691
+ enum dev_cmd_type type;
692
+ struct ufs_query query;
693
+};
694
+
695
+struct ufs_hba_ops {
696
+ int (*init)(struct ufs_hba *hba);
697
+ int (*hce_enable_notify)(struct ufs_hba *hba,
698
+ enum ufs_notify_change_status);
699
+ int (*link_startup_notify)(struct ufs_hba *hba,
700
+ enum ufs_notify_change_status);
701
+ int (*phy_initialization)(struct ufs_hba *hba);
702
+};
703
+
704
+struct ufs_hba {
705
+ struct udevice *dev;
706
+ void __iomem *mmio_base;
707
+ struct ufs_hba_ops *ops;
708
+ struct ufs_desc_size desc_size;
709
+ u32 capabilities;
710
+ u32 version;
711
+ u32 intr_mask;
712
+ u32 quirks;
713
+/*
714
+ * If UFS host controller is having issue in processing LCC (Line
715
+ * Control Command) coming from device then enable this quirk.
716
+ * When this quirk is enabled, host controller driver should disable
717
+ * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
718
+ * attribute of device to 0).
719
+ */
720
+#define UFSHCD_QUIRK_BROKEN_LCC 0x1
721
+
722
+ /* Virtual memory reference */
723
+ struct utp_transfer_cmd_desc *ucdl;
724
+ struct utp_transfer_req_desc *utrdl;
725
+ /* TODO: Add Task Manegement Support */
726
+ struct utp_task_req_desc *utmrdl;
727
+
728
+ struct utp_upiu_req *ucd_req_ptr;
729
+ struct utp_upiu_rsp *ucd_rsp_ptr;
730
+ struct ufshcd_sg_entry *ucd_prdt_ptr;
731
+
732
+ /* Power Mode information */
733
+ enum ufs_dev_pwr_mode curr_dev_pwr_mode;
734
+ struct ufs_pa_layer_attr pwr_info;
735
+ struct ufs_pwr_mode_info max_pwr_info;
736
+
737
+ struct ufs_dev_cmd dev_cmd;
738
+};
739
+
740
+static inline int ufshcd_ops_init(struct ufs_hba *hba)
741
+{
742
+ if (hba->ops && hba->ops->init)
743
+ return hba->ops->init(hba);
744
+
745
+ return 0;
746
+}
747
+
748
+static inline int ufshcd_ops_hce_enable_notify(struct ufs_hba *hba,
749
+ bool status)
750
+{
751
+ if (hba->ops && hba->ops->hce_enable_notify)
752
+ return hba->ops->hce_enable_notify(hba, status);
753
+
754
+ return 0;
755
+}
756
+
757
+static inline int ufshcd_ops_link_startup_notify(struct ufs_hba *hba,
758
+ bool status)
759
+{
760
+ if (hba->ops && hba->ops->link_startup_notify)
761
+ return hba->ops->link_startup_notify(hba, status);
762
+
763
+ return 0;
764
+}
765
+
766
+/* Controller UFSHCI version */
767
+enum {
768
+ UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
769
+ UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
770
+ UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
771
+ UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
772
+};
773
+
774
+/* Interrupt disable masks */
775
+enum {
776
+ /* Interrupt disable mask for UFSHCI v1.0 */
777
+ INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
778
+ INTERRUPT_MASK_RW_VER_10 = 0x30000,
779
+
780
+ /* Interrupt disable mask for UFSHCI v1.1 */
781
+ INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
782
+
783
+ /* Interrupt disable mask for UFSHCI v2.1 */
784
+ INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
785
+};
786
+
787
+/* UFSHCI Registers */
788
+enum {
789
+ REG_CONTROLLER_CAPABILITIES = 0x00,
790
+ REG_UFS_VERSION = 0x08,
791
+ REG_CONTROLLER_DEV_ID = 0x10,
792
+ REG_CONTROLLER_PROD_ID = 0x14,
793
+ REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
794
+ REG_INTERRUPT_STATUS = 0x20,
795
+ REG_INTERRUPT_ENABLE = 0x24,
796
+ REG_CONTROLLER_STATUS = 0x30,
797
+ REG_CONTROLLER_ENABLE = 0x34,
798
+ REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
799
+ REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
800
+ REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
801
+ REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
802
+ REG_UIC_ERROR_CODE_DME = 0x48,
803
+ REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
804
+ REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
805
+ REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
806
+ REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
807
+ REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
808
+ REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
809
+ REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
810
+ REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
811
+ REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
812
+ REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
813
+ REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
814
+ REG_UIC_COMMAND = 0x90,
815
+ REG_UIC_COMMAND_ARG_1 = 0x94,
816
+ REG_UIC_COMMAND_ARG_2 = 0x98,
817
+ REG_UIC_COMMAND_ARG_3 = 0x9C,
818
+
819
+ UFSHCI_REG_SPACE_SIZE = 0xA0,
820
+
821
+ REG_UFS_CCAP = 0x100,
822
+ REG_UFS_CRYPTOCAP = 0x104,
823
+
824
+ UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
825
+};
826
+
827
+/* Controller capability masks */
828
+enum {
829
+ MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
830
+ MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
831
+ MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
832
+ MASK_64_ADDRESSING_SUPPORT = 0x01000000,
833
+ MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
834
+ MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
835
+};
836
+
837
+/* Interrupt Status 20h */
838
+#define UTP_TRANSFER_REQ_COMPL 0x1
839
+#define UIC_DME_END_PT_RESET 0x2
840
+#define UIC_ERROR 0x4
841
+#define UIC_TEST_MODE 0x8
842
+#define UIC_POWER_MODE 0x10
843
+#define UIC_HIBERNATE_EXIT 0x20
844
+#define UIC_HIBERNATE_ENTER 0x40
845
+#define UIC_LINK_LOST 0x80
846
+#define UIC_LINK_STARTUP 0x100
847
+#define UTP_TASK_REQ_COMPL 0x200
848
+#define UIC_COMMAND_COMPL 0x400
849
+#define DEVICE_FATAL_ERROR 0x800
850
+#define CONTROLLER_FATAL_ERROR 0x10000
851
+#define SYSTEM_BUS_FATAL_ERROR 0x20000
852
+
853
+#define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\
854
+ UIC_HIBERNATE_EXIT |\
855
+ UIC_POWER_MODE)
856
+
857
+#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UIC_POWER_MODE)
858
+
859
+#define UFSHCD_ERROR_MASK (UIC_ERROR |\
860
+ DEVICE_FATAL_ERROR |\
861
+ CONTROLLER_FATAL_ERROR |\
862
+ SYSTEM_BUS_FATAL_ERROR)
863
+
864
+#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
865
+ CONTROLLER_FATAL_ERROR |\
866
+ SYSTEM_BUS_FATAL_ERROR)
867
+
868
+/* Host Controller Enable 0x34h */
869
+#define CONTROLLER_ENABLE 0x1
870
+#define CONTROLLER_DISABLE 0x0
871
+/* HCS - Host Controller Status 30h */
872
+#define DEVICE_PRESENT 0x1
873
+#define UTP_TRANSFER_REQ_LIST_READY 0x2
874
+#define UTP_TASK_REQ_LIST_READY 0x4
875
+#define UIC_COMMAND_READY 0x8
876
+#define HOST_ERROR_INDICATOR 0x10
877
+#define DEVICE_ERROR_INDICATOR 0x20
878
+#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
879
+
880
+#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
881
+ UTP_TASK_REQ_LIST_READY |\
882
+ UIC_COMMAND_READY)
883
+
884
+enum {
885
+ PWR_OK = 0x0,
886
+ PWR_LOCAL = 0x01,
887
+ PWR_REMOTE = 0x02,
888
+ PWR_BUSY = 0x03,
889
+ PWR_ERROR_CAP = 0x04,
890
+ PWR_FATAL_ERROR = 0x05,
891
+};
892
+
893
+/* UICCMD - UIC Command */
894
+#define COMMAND_OPCODE_MASK 0xFF
895
+#define GEN_SELECTOR_INDEX_MASK 0xFFFF
896
+
897
+#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
898
+#define RESET_LEVEL 0xFF
899
+
900
+#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
901
+#define CFG_RESULT_CODE_MASK 0xFF
902
+#define GENERIC_ERROR_CODE_MASK 0xFF
903
+
904
+#define ufshcd_writel(hba, val, reg) \
905
+ writel((val), (hba)->mmio_base + (reg))
906
+#define ufshcd_readl(hba, reg) \
907
+ readl((hba)->mmio_base + (reg))
908
+
909
+/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
910
+#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
911
+
912
+/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
913
+#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
914
+
915
+int ufshcd_probe(struct udevice *dev, struct ufs_hba_ops *hba_ops);
916
+
917
+#endif
u-boot/drivers/ufs/ufshcd-dwc.c
....@@ -0,0 +1,149 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
2
+/*
3
+ * UFS Host driver for Synopsys Designware Core
4
+ *
5
+ * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
6
+ *
7
+ * Authors: Joao Pinto <jpinto@synopsys.com>
8
+ */
9
+
10
+#include "ufs.h"
11
+#include "unipro.h"
12
+
13
+#include "ufshcd-dwc.h"
14
+#include "ufshci-dwc.h"
15
+
16
+int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba,
17
+ const struct ufshcd_dme_attr_val *v, int n)
18
+{
19
+ int ret = 0;
20
+ int attr_node = 0;
21
+
22
+ for (attr_node = 0; attr_node < n; attr_node++) {
23
+ ret = ufshcd_dme_set_attr(hba, v[attr_node].attr_sel,
24
+ ATTR_SET_NOR, v[attr_node].mib_val, v[attr_node].peer);
25
+
26
+ if (ret)
27
+ return ret;
28
+ }
29
+
30
+ return 0;
31
+}
32
+EXPORT_SYMBOL(ufshcd_dwc_dme_set_attrs);
33
+
34
+/**
35
+ * ufshcd_dwc_program_clk_div()
36
+ * This function programs the clk divider value. This value is needed to
37
+ * provide 1 microsecond tick to unipro layer.
38
+ * @hba: Private Structure pointer
39
+ * @divider_val: clock divider value to be programmed
40
+ *
41
+ */
42
+static void ufshcd_dwc_program_clk_div(struct ufs_hba *hba, u32 divider_val)
43
+{
44
+ ufshcd_writel(hba, divider_val, DWC_UFS_REG_HCLKDIV);
45
+}
46
+
47
+/**
48
+ * ufshcd_dwc_link_is_up()
49
+ * Check if link is up
50
+ * @hba: private structure pointer
51
+ *
52
+ * Returns 0 on success, non-zero value on failure
53
+ */
54
+static int ufshcd_dwc_link_is_up(struct ufs_hba *hba)
55
+{
56
+ int dme_result = 0;
57
+
58
+ ufshcd_dme_get(hba, UIC_ARG_MIB(VS_POWERSTATE), &dme_result);
59
+
60
+ if (dme_result == UFSHCD_LINK_IS_UP)
61
+ return 0;
62
+
63
+ return 1;
64
+}
65
+
66
+/**
67
+ * ufshcd_dwc_connection_setup()
68
+ * This function configures both the local side (host) and the peer side
69
+ * (device) unipro attributes to establish the connection to application/
70
+ * cport.
71
+ * This function is not required if the hardware is properly configured to
72
+ * have this connection setup on reset. But invoking this function does no
73
+ * harm and should be fine even working with any ufs device.
74
+ *
75
+ * @hba: pointer to drivers private data
76
+ *
77
+ * Returns 0 on success non-zero value on failure
78
+ */
79
+static int ufshcd_dwc_connection_setup(struct ufs_hba *hba)
80
+{
81
+ static const struct ufshcd_dme_attr_val setup_attrs[] = {
82
+ { UIC_ARG_MIB(T_CONNECTIONSTATE), 0, DME_LOCAL },
83
+ { UIC_ARG_MIB(N_DEVICEID), 0, DME_LOCAL },
84
+ { UIC_ARG_MIB(N_DEVICEID_VALID), 0, DME_LOCAL },
85
+ { UIC_ARG_MIB(T_PEERDEVICEID), 1, DME_LOCAL },
86
+ { UIC_ARG_MIB(T_PEERCPORTID), 0, DME_LOCAL },
87
+ { UIC_ARG_MIB(T_TRAFFICCLASS), 0, DME_LOCAL },
88
+ { UIC_ARG_MIB(T_CPORTFLAGS), 0x6, DME_LOCAL },
89
+ { UIC_ARG_MIB(T_CPORTMODE), 1, DME_LOCAL },
90
+ { UIC_ARG_MIB(T_CONNECTIONSTATE), 1, DME_LOCAL },
91
+ { UIC_ARG_MIB(T_CONNECTIONSTATE), 0, DME_PEER },
92
+ { UIC_ARG_MIB(N_DEVICEID), 1, DME_PEER },
93
+ { UIC_ARG_MIB(N_DEVICEID_VALID), 1, DME_PEER },
94
+ { UIC_ARG_MIB(T_PEERDEVICEID), 1, DME_PEER },
95
+ { UIC_ARG_MIB(T_PEERCPORTID), 0, DME_PEER },
96
+ { UIC_ARG_MIB(T_TRAFFICCLASS), 0, DME_PEER },
97
+ { UIC_ARG_MIB(T_CPORTFLAGS), 0x6, DME_PEER },
98
+ { UIC_ARG_MIB(T_CPORTMODE), 1, DME_PEER },
99
+ { UIC_ARG_MIB(T_CONNECTIONSTATE), 1, DME_PEER }
100
+ };
101
+
102
+ return ufshcd_dwc_dme_set_attrs(hba, setup_attrs, ARRAY_SIZE(setup_attrs));
103
+}
104
+
105
+/**
106
+ * ufshcd_dwc_link_startup_notify()
107
+ * UFS Host DWC specific link startup sequence
108
+ * @hba: private structure pointer
109
+ * @status: Callback notify status
110
+ *
111
+ * Returns 0 on success, non-zero value on failure
112
+ */
113
+int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba,
114
+ enum ufs_notify_change_status status)
115
+{
116
+ int err = 0;
117
+
118
+ if (status == PRE_CHANGE) {
119
+ ufshcd_dwc_program_clk_div(hba, DWC_UFS_REG_HCLKDIV_DIV_125);
120
+
121
+ if (hba->ops->phy_initialization) {
122
+ err = hba->ops->phy_initialization(hba);
123
+ if (err) {
124
+ dev_err(hba->dev, "Phy setup failed (%d)\n",
125
+ err);
126
+ goto out;
127
+ }
128
+ }
129
+ } else { /* POST_CHANGE */
130
+ err = ufshcd_dwc_link_is_up(hba);
131
+ if (err) {
132
+ dev_err(hba->dev, "Link is not up\n");
133
+ goto out;
134
+ }
135
+
136
+ err = ufshcd_dwc_connection_setup(hba);
137
+ if (err)
138
+ dev_err(hba->dev, "Connection setup failed (%d)\n",
139
+ err);
140
+ }
141
+
142
+out:
143
+ return err;
144
+}
145
+EXPORT_SYMBOL(ufshcd_dwc_link_startup_notify);
146
+
147
+MODULE_AUTHOR("Joao Pinto <Joao.Pinto@synopsys.com>");
148
+MODULE_DESCRIPTION("UFS Host driver for Synopsys Designware Core");
149
+MODULE_LICENSE("Dual BSD/GPL");
u-boot/drivers/ufs/ufshcd-dwc.h
....@@ -0,0 +1,23 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
2
+/*
3
+ * UFS Host driver for Synopsys Designware Core
4
+ *
5
+ * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
6
+ *
7
+ * Authors: Joao Pinto <jpinto@synopsys.com>
8
+ */
9
+
10
+#ifndef _UFSHCD_DWC_H
11
+#define _UFSHCD_DWC_H
12
+
13
+struct ufshcd_dme_attr_val {
14
+ u32 attr_sel;
15
+ u32 mib_val;
16
+ u8 peer;
17
+};
18
+
19
+int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba,
20
+ enum ufs_notify_change_status status);
21
+int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba,
22
+ const struct ufshcd_dme_attr_val *v, int n);
23
+#endif /* End of Header */
u-boot/drivers/ufs/ufshci-dwc.h
....@@ -0,0 +1,33 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
2
+/*
3
+ * UFS Host driver for Synopsys Designware Core
4
+ *
5
+ * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
6
+ *
7
+ * Authors: Joao Pinto <jpinto@synopsys.com>
8
+ */
9
+
10
+#ifndef _UFSHCI_DWC_H
11
+#define _UFSHCI_DWC_H
12
+
13
+/* DWC HC UFSHCI specific Registers */
14
+enum dwc_specific_registers {
15
+ DWC_UFS_REG_HCLKDIV = 0xFC,
16
+};
17
+
18
+/* Clock Divider Values: Hex equivalent of frequency in MHz */
19
+enum clk_div_values {
20
+ DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e,
21
+ DWC_UFS_REG_HCLKDIV_DIV_125 = 0x7d,
22
+ DWC_UFS_REG_HCLKDIV_DIV_200 = 0xc8,
23
+};
24
+
25
+/* Selector Index */
26
+enum selector_index {
27
+ SELIND_LN0_TX = 0x00,
28
+ SELIND_LN1_TX = 0x01,
29
+ SELIND_LN0_RX = 0x04,
30
+ SELIND_LN1_RX = 0x05,
31
+};
32
+
33
+#endif /* End of Header */
u-boot/drivers/ufs/unipro.h
....@@ -0,0 +1,270 @@
1
+/* SPDX-License-Identifier: GPL-2.0+ */
2
+#ifndef _UNIPRO_H_
3
+#define _UNIPRO_H_
4
+
5
+/*
6
+ * M-TX Configuration Attributes
7
+ */
8
+#define TX_HIBERN8TIME_CAPABILITY 0x000F
9
+#define TX_MODE 0x0021
10
+#define TX_HSRATE_SERIES 0x0022
11
+#define TX_HSGEAR 0x0023
12
+#define TX_PWMGEAR 0x0024
13
+#define TX_AMPLITUDE 0x0025
14
+#define TX_HS_SLEWRATE 0x0026
15
+#define TX_SYNC_SOURCE 0x0027
16
+#define TX_HS_SYNC_LENGTH 0x0028
17
+#define TX_HS_PREPARE_LENGTH 0x0029
18
+#define TX_LS_PREPARE_LENGTH 0x002A
19
+#define TX_HIBERN8_CONTROL 0x002B
20
+#define TX_LCC_ENABLE 0x002C
21
+#define TX_PWM_BURST_CLOSURE_EXTENSION 0x002D
22
+#define TX_BYPASS_8B10B_ENABLE 0x002E
23
+#define TX_DRIVER_POLARITY 0x002F
24
+#define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE 0x0030
25
+#define TX_LS_TERMINATED_LINE_DRIVE_ENABLE 0x0031
26
+#define TX_LCC_SEQUENCER 0x0032
27
+#define TX_MIN_ACTIVATETIME 0x0033
28
+#define TX_PWM_G6_G7_SYNC_LENGTH 0x0034
29
+#define TX_REFCLKFREQ 0x00EB
30
+#define TX_CFGCLKFREQVAL 0x00EC
31
+#define CFGEXTRATTR 0x00F0
32
+#define DITHERCTRL2 0x00F1
33
+
34
+/*
35
+ * M-RX Configuration Attributes
36
+ */
37
+#define RX_MODE 0x00A1
38
+#define RX_HSRATE_SERIES 0x00A2
39
+#define RX_HSGEAR 0x00A3
40
+#define RX_PWMGEAR 0x00A4
41
+#define RX_LS_TERMINATED_ENABLE 0x00A5
42
+#define RX_HS_UNTERMINATED_ENABLE 0x00A6
43
+#define RX_ENTER_HIBERN8 0x00A7
44
+#define RX_BYPASS_8B10B_ENABLE 0x00A8
45
+#define RX_TERMINATION_FORCE_ENABLE 0x0089
46
+#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F
47
+#define RX_HIBERN8TIME_CAPABILITY 0x0092
48
+#define RX_REFCLKFREQ 0x00EB
49
+#define RX_CFGCLKFREQVAL 0x00EC
50
+#define CFGWIDEINLN 0x00F0
51
+#define CFGRXCDR8 0x00BA
52
+#define ENARXDIRECTCFG4 0x00F2
53
+#define CFGRXOVR8 0x00BD
54
+#define RXDIRECTCTRL2 0x00C7
55
+#define ENARXDIRECTCFG3 0x00F3
56
+#define RXCALCTRL 0x00B4
57
+#define ENARXDIRECTCFG2 0x00F4
58
+#define CFGRXOVR4 0x00E9
59
+#define RXSQCTRL 0x00B5
60
+#define CFGRXOVR6 0x00BF
61
+
62
+#define is_mphy_tx_attr(attr) (attr < RX_MODE)
63
+#define RX_MIN_ACTIVATETIME_UNIT_US 100
64
+#define HIBERN8TIME_UNIT_US 100
65
+
66
+/*
67
+ * Common Block Attributes
68
+ */
69
+#define TX_GLOBALHIBERNATE UNIPRO_CB_OFFSET(0x002B)
70
+#define REFCLKMODE UNIPRO_CB_OFFSET(0x00BF)
71
+#define DIRECTCTRL19 UNIPRO_CB_OFFSET(0x00CD)
72
+#define DIRECTCTRL10 UNIPRO_CB_OFFSET(0x00E6)
73
+#define CDIRECTCTRL6 UNIPRO_CB_OFFSET(0x00EA)
74
+#define RTOBSERVESELECT UNIPRO_CB_OFFSET(0x00F0)
75
+#define CBDIVFACTOR UNIPRO_CB_OFFSET(0x00F1)
76
+#define CBDCOCTRL5 UNIPRO_CB_OFFSET(0x00F3)
77
+#define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8)
78
+#define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB)
79
+
80
+#define UNIPRO_CB_OFFSET(x) (0x8000 | x)
81
+
82
+/*
83
+ * PHY Adpater attributes
84
+ */
85
+#define PA_ACTIVETXDATALANES 0x1560
86
+#define PA_ACTIVERXDATALANES 0x1580
87
+#define PA_TXTRAILINGCLOCKS 0x1564
88
+#define PA_PHY_TYPE 0x1500
89
+#define PA_AVAILTXDATALANES 0x1520
90
+#define PA_AVAILRXDATALANES 0x1540
91
+#define PA_MINRXTRAILINGCLOCKS 0x1543
92
+#define PA_TXPWRSTATUS 0x1567
93
+#define PA_RXPWRSTATUS 0x1582
94
+#define PA_TXFORCECLOCK 0x1562
95
+#define PA_TXPWRMODE 0x1563
96
+#define PA_LEGACYDPHYESCDL 0x1570
97
+#define PA_MAXTXSPEEDFAST 0x1521
98
+#define PA_MAXTXSPEEDSLOW 0x1522
99
+#define PA_MAXRXSPEEDFAST 0x1541
100
+#define PA_MAXRXSPEEDSLOW 0x1542
101
+#define PA_TXLINKSTARTUPHS 0x1544
102
+#define PA_LOCAL_TX_LCC_ENABLE 0x155E
103
+#define PA_TXSPEEDFAST 0x1565
104
+#define PA_TXSPEEDSLOW 0x1566
105
+#define PA_REMOTEVERINFO 0x15A0
106
+#define PA_TXGEAR 0x1568
107
+#define PA_TXTERMINATION 0x1569
108
+#define PA_HSSERIES 0x156A
109
+#define PA_PWRMODE 0x1571
110
+#define PA_RXGEAR 0x1583
111
+#define PA_RXTERMINATION 0x1584
112
+#define PA_MAXRXPWMGEAR 0x1586
113
+#define PA_MAXRXHSGEAR 0x1587
114
+#define PA_RXHSUNTERMCAP 0x15A5
115
+#define PA_RXLSTERMCAP 0x15A6
116
+#define PA_GRANULARITY 0x15AA
117
+#define PA_PACPREQTIMEOUT 0x1590
118
+#define PA_PACPREQEOBTIMEOUT 0x1591
119
+#define PA_HIBERN8TIME 0x15A7
120
+#define PA_LOCALVERINFO 0x15A9
121
+#define PA_TACTIVATE 0x15A8
122
+#define PA_PACPFRAMECOUNT 0x15C0
123
+#define PA_PACPERRORCOUNT 0x15C1
124
+#define PA_PHYTESTCONTROL 0x15C2
125
+#define PA_PWRMODEUSERDATA0 0x15B0
126
+#define PA_PWRMODEUSERDATA1 0x15B1
127
+#define PA_PWRMODEUSERDATA2 0x15B2
128
+#define PA_PWRMODEUSERDATA3 0x15B3
129
+#define PA_PWRMODEUSERDATA4 0x15B4
130
+#define PA_PWRMODEUSERDATA5 0x15B5
131
+#define PA_PWRMODEUSERDATA6 0x15B6
132
+#define PA_PWRMODEUSERDATA7 0x15B7
133
+#define PA_PWRMODEUSERDATA8 0x15B8
134
+#define PA_PWRMODEUSERDATA9 0x15B9
135
+#define PA_PWRMODEUSERDATA10 0x15BA
136
+#define PA_PWRMODEUSERDATA11 0x15BB
137
+#define PA_CONNECTEDTXDATALANES 0x1561
138
+#define PA_CONNECTEDRXDATALANES 0x1581
139
+#define PA_LOGICALLANEMAP 0x15A1
140
+#define PA_SLEEPNOCONFIGTIME 0x15A2
141
+#define PA_STALLNOCONFIGTIME 0x15A3
142
+#define PA_SAVECONFIGTIME 0x15A4
143
+
144
+#define PA_TACTIVATE_TIME_UNIT_US 10
145
+#define PA_HIBERN8_TIME_UNIT_US 100
146
+
147
+/*Other attributes*/
148
+#define VS_MPHYCFGUPDT 0xD085
149
+#define VS_DEBUGOMC 0xD09E
150
+#define VS_POWERSTATE 0xD083
151
+
152
+#define PA_GRANULARITY_MIN_VAL 1
153
+#define PA_GRANULARITY_MAX_VAL 6
154
+
155
+/* PHY Adapter Protocol Constants */
156
+#define PA_MAXDATALANES 4
157
+
158
+/* PA power modes */
159
+enum {
160
+ FAST_MODE = 1,
161
+ SLOW_MODE = 2,
162
+ FASTAUTO_MODE = 4,
163
+ SLOWAUTO_MODE = 5,
164
+ UNCHANGED = 7,
165
+};
166
+
167
+/* PA TX/RX Frequency Series */
168
+enum {
169
+ PA_HS_MODE_A = 1,
170
+ PA_HS_MODE_B = 2,
171
+};
172
+
173
+enum ufs_pwm_gear_tag {
174
+ UFS_PWM_DONT_CHANGE, /* Don't change Gear */
175
+ UFS_PWM_G1, /* PWM Gear 1 (default for reset) */
176
+ UFS_PWM_G2, /* PWM Gear 2 */
177
+ UFS_PWM_G3, /* PWM Gear 3 */
178
+ UFS_PWM_G4, /* PWM Gear 4 */
179
+ UFS_PWM_G5, /* PWM Gear 5 */
180
+ UFS_PWM_G6, /* PWM Gear 6 */
181
+ UFS_PWM_G7, /* PWM Gear 7 */
182
+};
183
+
184
+enum ufs_hs_gear_tag {
185
+ UFS_HS_DONT_CHANGE, /* Don't change Gear */
186
+ UFS_HS_G1, /* HS Gear 1 (default for reset) */
187
+ UFS_HS_G2, /* HS Gear 2 */
188
+ UFS_HS_G3, /* HS Gear 3 */
189
+};
190
+
191
+enum ufs_unipro_ver {
192
+ UFS_UNIPRO_VER_RESERVED = 0,
193
+ UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */
194
+ UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */
195
+ UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */
196
+ UFS_UNIPRO_VER_MAX = 4, /* UniPro unsupported version */
197
+ /* UniPro version field mask in PA_LOCALVERINFO */
198
+ UFS_UNIPRO_VER_MASK = 0xF,
199
+};
200
+
201
+/*
202
+ * Data Link Layer Attributes
203
+ */
204
+#define DL_TC0TXFCTHRESHOLD 0x2040
205
+#define DL_FC0PROTTIMEOUTVAL 0x2041
206
+#define DL_TC0REPLAYTIMEOUTVAL 0x2042
207
+#define DL_AFC0REQTIMEOUTVAL 0x2043
208
+#define DL_AFC0CREDITTHRESHOLD 0x2044
209
+#define DL_TC0OUTACKTHRESHOLD 0x2045
210
+#define DL_TC1TXFCTHRESHOLD 0x2060
211
+#define DL_FC1PROTTIMEOUTVAL 0x2061
212
+#define DL_TC1REPLAYTIMEOUTVAL 0x2062
213
+#define DL_AFC1REQTIMEOUTVAL 0x2063
214
+#define DL_AFC1CREDITTHRESHOLD 0x2064
215
+#define DL_TC1OUTACKTHRESHOLD 0x2065
216
+#define DL_TXPREEMPTIONCAP 0x2000
217
+#define DL_TC0TXMAXSDUSIZE 0x2001
218
+#define DL_TC0RXINITCREDITVAL 0x2002
219
+#define DL_TC0TXBUFFERSIZE 0x2005
220
+#define DL_PEERTC0PRESENT 0x2046
221
+#define DL_PEERTC0RXINITCREVAL 0x2047
222
+#define DL_TC1TXMAXSDUSIZE 0x2003
223
+#define DL_TC1RXINITCREDITVAL 0x2004
224
+#define DL_TC1TXBUFFERSIZE 0x2006
225
+#define DL_PEERTC1PRESENT 0x2066
226
+#define DL_PEERTC1RXINITCREVAL 0x2067
227
+
228
+/*
229
+ * Network Layer Attributes
230
+ */
231
+#define N_DEVICEID 0x3000
232
+#define N_DEVICEID_VALID 0x3001
233
+#define N_TC0TXMAXSDUSIZE 0x3020
234
+#define N_TC1TXMAXSDUSIZE 0x3021
235
+
236
+/*
237
+ * Transport Layer Attributes
238
+ */
239
+#define T_NUMCPORTS 0x4000
240
+#define T_NUMTESTFEATURES 0x4001
241
+#define T_CONNECTIONSTATE 0x4020
242
+#define T_PEERDEVICEID 0x4021
243
+#define T_PEERCPORTID 0x4022
244
+#define T_TRAFFICCLASS 0x4023
245
+#define T_PROTOCOLID 0x4024
246
+#define T_CPORTFLAGS 0x4025
247
+#define T_TXTOKENVALUE 0x4026
248
+#define T_RXTOKENVALUE 0x4027
249
+#define T_LOCALBUFFERSPACE 0x4028
250
+#define T_PEERBUFFERSPACE 0x4029
251
+#define T_CREDITSTOSEND 0x402A
252
+#define T_CPORTMODE 0x402B
253
+#define T_TC0TXMAXSDUSIZE 0x4060
254
+#define T_TC1TXMAXSDUSIZE 0x4061
255
+
256
+#ifdef FALSE
257
+#undef FALSE
258
+#endif
259
+
260
+#ifdef TRUE
261
+#undef TRUE
262
+#endif
263
+
264
+/* Boolean attribute values */
265
+enum {
266
+ FALSE = 0,
267
+ TRUE,
268
+};
269
+
270
+#endif /* _UNIPRO_H_ */
u-boot/drivers/usb/dwc3/gadget.c
....@@ -2482,7 +2482,6 @@
24822482 while (left > 0) {
24832483 union dwc3_event event;
24842484
2485
- invalidate_dcache_range((uintptr_t)evt->buf, evt->length);
24862485 event.raw = *(u32 *) (evt->buf + evt->lpos);
24872486
24882487 dwc3_process_event_entry(dwc, &event);
....@@ -2538,6 +2537,7 @@
25382537 u32 reg;
25392538
25402539 evt = dwc->ev_buffs[buf];
2540
+ dwc3_invalidate_cache((uintptr_t)evt->buf, evt->length);
25412541
25422542 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
25432543 count &= DWC3_GEVNTCOUNT_MASK;
u-boot/drivers/usb/dwc3/io.h
....@@ -48,6 +48,11 @@
4848 writel(value, base + offs);
4949 }
5050
51
+static inline void dwc3_invalidate_cache(uintptr_t addr, int length)
52
+{
53
+ invalidate_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
54
+}
55
+
5156 static inline void dwc3_flush_cache(uintptr_t addr, int length)
5257 {
5358 flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
u-boot/drivers/video/Kconfig
....@@ -14,6 +14,21 @@
1414 option compiles in the video uclass and routes all LCD/video access
1515 through this.
1616
17
+config SPL_DM_VIDEO
18
+ bool "Enable driver model support for LCD/video in SPL"
19
+ depends on DM_VIDEO && SPL
20
+ help
21
+ This enables driver model for LCD and video devices in SPL. These support
22
+ a bitmap display of various sizes and depths which can be drawn on
23
+ to display a command-line console or splash screen. Enabling this
24
+ option compiles in the video uclass and routes all LCD/video access
25
+ through this.
26
+
27
+config SPL_VIDEO_BUF
28
+ hex "SPL video memory buffer for any use"
29
+ depends on SPL_DM_VIDEO
30
+ default 0xa200000
31
+
1732 config BACKLIGHT_PWM
1833 bool "Generic PWM based Backlight Driver"
1934 depends on DM_VIDEO && DM_PWM
....@@ -390,6 +405,12 @@
390405 help
391406 This enables library for accessing EDID data from an LCD panel.
392407
408
+config SPL_I2C_EDID
409
+ bool "Enable EDID library in SPL"
410
+ depends on DM_I2C && SPL_DM_VIDEO
411
+ help
412
+ This enables library in SPL for accessing EDID data from an LCD panel.
413
+
393414 config DISPLAY
394415 bool "Enable Display support"
395416 depends on DM
u-boot/drivers/video/Makefile
....@@ -5,6 +5,7 @@
55 # SPDX-License-Identifier: GPL-2.0+
66 #
77
8
+ifndef CONFIG_SPL_BUILD
89 ifdef CONFIG_DM
910 obj-$(CONFIG_DISPLAY) += display-uclass.o
1011 obj-$(CONFIG_DM_VIDEO) += backlight-uclass.o
....@@ -56,8 +57,11 @@
5657 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
5758 obj-${CONFIG_EXYNOS_FB} += exynos/
5859 obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
59
-obj-${CONFIG_DRM_ROCKCHIP} += drm/
6060 obj-${CONFIG_ROCKCHIP_EINK} += rk_eink/
6161
6262 obj-y += bridge/
6363 obj-y += sunxi/
64
+endif
65
+
66
+obj-${CONFIG_DRM_ROCKCHIP} += drm/
67
+
u-boot/drivers/video/drm/Kconfig
....@@ -28,15 +28,6 @@
2828 help
2929 Driver for Maxim MAX96745 GMSL2 Serializer with eDP1.4a/DP1.4 Input.
3030
31
-config DRM_MAXIM_MAX96752F
32
- bool "Maxim max96752F GMSL2 Deserializer"
33
- depends on DRM_ROCKCHIP
34
- select I2C_MUX_MAX96752F
35
- select PINCTRL_MAX96752F
36
- select GPIO_MAX96752F
37
- help
38
- Driver for Maxim MAX96752F GMSL2 Deserializer with Dual LVDS Output.
39
-
4031 config DRM_MAXIM_MAX96755F
4132 bool "Maxim max96755F GMSL2 Serializer"
4233 depends on DRM_ROCKCHIP
....@@ -45,11 +36,19 @@
4536 help
4637 Driver for Maxim MAX96755F GMSL2 Serializer with MIPI-DSI Input.
4738
48
-config DRM_PANEL_MAXIM_DESERIALIZER
49
- bool "Maxim deserializer panel driver"
39
+config DRM_PANEL_ROHM_BU18RL82
40
+ bool "Rohm BU18RL82-based panels"
5041 depends on DRM_ROCKCHIP
5142 help
52
- Driver for Maxim deserializer panels.
43
+ Say Y if you want to enable support for panels based on the
44
+ Rohm BU18RL82.
45
+
46
+config DRM_PANEL_MAXIM_MAX96752F
47
+ bool "Maxim MAX96752F-based panels"
48
+ depends on DRM_ROCKCHIP
49
+ help
50
+ Say Y if you want to enable support for panels based on the
51
+ Maxim MAX96752F.
5352
5453 config DRM_ROCKCHIP_PANEL
5554 bool "Rockchip Panel Support"
....@@ -216,13 +215,12 @@
216215 Support for Rockchip HDMI/DP Combo PHY HDMI with Samsung
217216 IP block.
218217
219
-config ROCKCHIP_DRM_TVE
218
+config DRM_ROCKCHIP_TVE
220219 bool "Rockchip TVE Support"
221220 depends on DRM_ROCKCHIP
222221 help
223222 Choose this option to enable support for Rockchip TVE.
224
- Rockchip rk322x and rk322xh SoC has TVE can be used, and
225
- say Y to enable TVE driver.
223
+ Say Y to enable TVE driver.
226224
227225 config ROCKCHIP_CUBIC_LUT_SIZE
228226 int "Rockchip cubic lut size"
u-boot/drivers/video/drm/Makefile
....@@ -6,17 +6,18 @@
66
77 obj-y += drm_modes.o
88
9
-obj-y += rockchip_display.o rockchip_crtc.o rockchip_phy.o rockchip_bridge.o \
9
+ifndef CONFIG_SPL_BUILD
10
+obj-y += rockchip_display.o rockchip_display_helper.o rockchip_crtc.o rockchip_phy.o rockchip_bridge.o \
1011 rockchip_vop.o rockchip_vop_reg.o rockchip_vop2.o bmp_helper.o \
11
- rockchip_connector.o
12
+ rockchip_connector.o rockchip_post_csc.o
1213
1314 obj-$(CONFIG_DRM_MIPI_DSI) += drm_mipi_dsi.o
1415 obj-$(CONFIG_DRM_DP_HELPER) += drm_dp_helper.o
1516 obj-$(CONFIG_DRM_DSC) += drm_dsc.o
1617 obj-$(CONFIG_DRM_MAXIM_MAX96745) += max96745.o
17
-obj-$(CONFIG_DRM_MAXIM_MAX96752F) += max96752f.o
1818 obj-$(CONFIG_DRM_MAXIM_MAX96755F) += max96755f.o
19
-obj-$(CONFIG_DRM_PANEL_MAXIM_DESERIALIZER) += panel-maxim-deserializer.o
19
+obj-$(CONFIG_DRM_PANEL_ROHM_BU18RL82) += panel-rohm-bu18rl82.o
20
+obj-$(CONFIG_DRM_PANEL_MAXIM_MAX96752F) += panel-maxim-max96752f.o
2021 obj-$(CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI) += dw_mipi_dsi.o
2122 obj-$(CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2) += dw_mipi_dsi2.o
2223 obj-$(CONFIG_DRM_ROCKCHIP_DW_HDMI) += rockchip_dw_hdmi.o dw_hdmi.o
....@@ -27,7 +28,7 @@
2728 obj-$(CONFIG_DRM_ROCKCHIP_INNO_VIDEO_PHY) += inno_video_phy.o
2829 obj-$(CONFIG_DRM_ROCKCHIP_INNO_VIDEO_COMBO_PHY) += inno_video_combo_phy.o
2930 obj-$(CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI) += phy-rockchip-samsung-hdptx-hdmi.o
30
-obj-$(CONFIG_ROCKCHIP_DRM_TVE) += rockchip_drm_tve.o
31
+obj-$(CONFIG_DRM_ROCKCHIP_TVE) += rockchip_tve.o
3132 obj-$(CONFIG_DRM_ROCKCHIP_ANALOGIX_DP) += analogix_dp.o analogix_dp_reg.o
3233 obj-$(CONFIG_DRM_ROCKCHIP_DW_DP) += dw-dp.o
3334 obj-$(CONFIG_DRM_ROCKCHIP_LVDS) += rockchip_lvds.o
....@@ -37,3 +38,7 @@
3738 obj-$(CONFIG_DRM_ROCKCHIP_RK618) += rk618.o rk618_lvds.o rk618_dsi.o
3839 obj-$(CONFIG_DRM_ROCKCHIP_RK1000) += rk1000.o rk1000_tve.o
3940 obj-$(CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY) += samsung_mipi_dcphy.o
41
+else
42
+obj-y += rockchip_spl_display.o rockchip_display_helper.o rockchip_crtc.o rockchip_connector.o rockchip_post_csc.o rockchip_vop2.o rockchip_phy.o rockchip-inno-hdmi-phy.o rockchip_dw_hdmi.o dw_hdmi.o
43
+endif
44
+
u-boot/drivers/video/drm/analogix_dp.c
....@@ -943,6 +943,37 @@
943943 .detect = analogix_dp_connector_detect,
944944 };
945945
946
+static u32 analogix_dp_parse_link_frequencies(struct analogix_dp_device *dp)
947
+{
948
+ struct udevice *dev = dp->dev;
949
+ const struct device_node *endpoint;
950
+ u64 frequency = 0;
951
+
952
+ endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0);
953
+ if (!endpoint)
954
+ return 0;
955
+
956
+ if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0)
957
+ return 0;
958
+
959
+ if (!frequency)
960
+ return 0;
961
+
962
+ do_div(frequency, 10 * 1000); /* symbol rate kbytes */
963
+
964
+ switch (frequency) {
965
+ case 162000:
966
+ case 270000:
967
+ case 540000:
968
+ break;
969
+ default:
970
+ dev_err(dev, "invalid link frequency value: %llu\n", frequency);
971
+ return 0;
972
+ }
973
+
974
+ return frequency;
975
+}
976
+
946977 static int analogix_dp_parse_dt(struct analogix_dp_device *dp)
947978 {
948979 struct udevice *dev = dp->dev;
....@@ -956,21 +987,9 @@
956987 dp->video_info.force_stream_valid =
957988 dev_read_bool(dev, "analogix,force-stream-valid");
958989
959
- max_link_rate = dev_read_u32_default(dev, "max-link-rate", 0);
960
- if (max_link_rate) {
961
- switch (max_link_rate) {
962
- case 1620:
963
- case 2700:
964
- case 5400:
965
- dp->video_info.max_link_rate =
966
- min_t(u8, dp->video_info.max_link_rate,
967
- drm_dp_link_rate_to_bw_code(max_link_rate * 100));
968
- break;
969
- default:
970
- dev_err(dev, "invalid max-link-rate %d\n", max_link_rate);
971
- break;
972
- }
973
- }
990
+ max_link_rate = analogix_dp_parse_link_frequencies(dp);
991
+ if (max_link_rate && max_link_rate < drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate))
992
+ dp->video_info.max_link_rate = drm_dp_link_rate_to_bw_code(max_link_rate);
974993
975994 if (dev_read_prop(dev, "data-lanes", &len)) {
976995 num_lanes = len / sizeof(u32);
....@@ -1075,8 +1094,9 @@
10751094 .lcdsel_big = 0 | BIT(21),
10761095 .lcdsel_lit = BIT(5) | BIT(21),
10771096 .chip_type = RK3399_EDP,
1097
+ .ssc = true,
10781098
1079
- .max_link_rate = DP_LINK_BW_2_7,
1099
+ .max_link_rate = DP_LINK_BW_5_4,
10801100 .max_lane_count = 4,
10811101 };
10821102
u-boot/drivers/video/drm/drm_modes.c
....@@ -60,6 +60,19 @@
6060 }
6161
6262 /**
63
+ * drm_mode_copy - copy the mode
64
+ * @dst: mode to overwrite
65
+ * @src: mode to copy
66
+ *
67
+ * Copy an existing mode into another mode, preserving the object id and
68
+ * list head of the destination mode.
69
+ */
70
+void drm_mode_copy(struct drm_display_mode *dst, const struct drm_display_mode *src)
71
+{
72
+ *dst = *src;
73
+}
74
+
75
+/**
6376 * drm_mode_destroy - remove a mode
6477 * @mode: mode to remove
6578 */
....@@ -185,6 +198,45 @@
185198 }
186199
187200 /**
201
+ * drm_display_mode_from_videomode - fill in @dmode using @vm,
202
+ * @vm: videomode structure to use as source
203
+ * @dmode: drm_display_mode structure to use as destination
204
+ *
205
+ * Fills out @dmode using the display mode specified in @vm.
206
+ */
207
+void drm_display_mode_from_videomode(const struct videomode *vm,
208
+ struct drm_display_mode *dmode)
209
+{
210
+ dmode->hdisplay = vm->hactive;
211
+ dmode->hsync_start = dmode->hdisplay + vm->hfront_porch;
212
+ dmode->hsync_end = dmode->hsync_start + vm->hsync_len;
213
+ dmode->htotal = dmode->hsync_end + vm->hback_porch;
214
+
215
+ dmode->vdisplay = vm->vactive;
216
+ dmode->vsync_start = dmode->vdisplay + vm->vfront_porch;
217
+ dmode->vsync_end = dmode->vsync_start + vm->vsync_len;
218
+ dmode->vtotal = dmode->vsync_end + vm->vback_porch;
219
+
220
+ dmode->clock = vm->pixelclock / 1000;
221
+
222
+ dmode->flags = 0;
223
+ if (vm->flags & DISPLAY_FLAGS_HSYNC_HIGH)
224
+ dmode->flags |= DRM_MODE_FLAG_PHSYNC;
225
+ else if (vm->flags & DISPLAY_FLAGS_HSYNC_LOW)
226
+ dmode->flags |= DRM_MODE_FLAG_NHSYNC;
227
+ if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH)
228
+ dmode->flags |= DRM_MODE_FLAG_PVSYNC;
229
+ else if (vm->flags & DISPLAY_FLAGS_VSYNC_LOW)
230
+ dmode->flags |= DRM_MODE_FLAG_NVSYNC;
231
+ if (vm->flags & DISPLAY_FLAGS_INTERLACED)
232
+ dmode->flags |= DRM_MODE_FLAG_INTERLACE;
233
+ if (vm->flags & DISPLAY_FLAGS_DOUBLESCAN)
234
+ dmode->flags |= DRM_MODE_FLAG_DBLSCAN;
235
+ if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
236
+ dmode->flags |= DRM_MODE_FLAG_DBLCLK;
237
+}
238
+
239
+/**
188240 * drm_display_mode_to_videomode - fill in @vm using @dmode,
189241 * @dmode: drm_display_mode structure to use as source
190242 * @vm: videomode structure to use as destination
u-boot/drivers/video/drm/dw-dp.c
....@@ -231,6 +231,7 @@
231231
232232 bool force_hpd;
233233 bool force_output;
234
+ u32 max_link_rate;
234235 };
235236
236237 enum {
....@@ -562,7 +563,7 @@
562563 !!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED);
563564
564565 link->revision = link->dpcd[DP_DPCD_REV];
565
- link->rate = min_t(u32, dp->phy.attrs.max_link_rate * 100,
566
+ link->rate = min_t(u32, min(dp->max_link_rate, dp->phy.attrs.max_link_rate * 100),
566567 drm_dp_max_link_rate(link->dpcd));
567568 link->lanes = min_t(u8, dp->phy.attrs.bus_width,
568569 drm_dp_max_lane_count(link->dpcd));
....@@ -1704,6 +1705,49 @@
17041705 return 0;
17051706 }
17061707
1708
+static u32 dw_dp_parse_link_frequencies(struct dw_dp *dp)
1709
+{
1710
+ struct udevice *dev = dp->dev;
1711
+ const struct device_node *endpoint;
1712
+ u64 frequency = 0;
1713
+
1714
+ endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0);
1715
+ if (!endpoint)
1716
+ return 0;
1717
+
1718
+ if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0)
1719
+ return 0;
1720
+
1721
+ if (!frequency)
1722
+ return 0;
1723
+
1724
+ do_div(frequency, 10 * 1000); /* symbol rate kbytes */
1725
+
1726
+ switch (frequency) {
1727
+ case 162000:
1728
+ case 270000:
1729
+ case 540000:
1730
+ case 810000:
1731
+ break;
1732
+ default:
1733
+ dev_err(dev, "invalid link frequency value: %llu\n", frequency);
1734
+ return 0;
1735
+ }
1736
+
1737
+ return frequency;
1738
+}
1739
+
1740
+static int dw_dp_parse_dt(struct dw_dp *dp)
1741
+{
1742
+ dp->force_hpd = dev_read_bool(dp->dev, "force-hpd");
1743
+
1744
+ dp->max_link_rate = dw_dp_parse_link_frequencies(dp);
1745
+ if (!dp->max_link_rate)
1746
+ dp->max_link_rate = 810000;
1747
+
1748
+ return 0;
1749
+}
1750
+
17071751 static int dw_dp_probe(struct udevice *dev)
17081752 {
17091753 struct dw_dp *dp = dev_get_priv(dev);
....@@ -1723,8 +1767,6 @@
17231767 return ret;
17241768 }
17251769
1726
- dp->force_hpd = dev_read_bool(dev, "force-hpd");
1727
-
17281770 ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio,
17291771 GPIOD_IS_IN);
17301772 if (ret && ret != -ENOENT) {
....@@ -1736,6 +1778,12 @@
17361778
17371779 dp->dev = dev;
17381780
1781
+ ret = dw_dp_parse_dt(dp);
1782
+ if (ret) {
1783
+ dev_err(dev, "failed to parse DT\n");
1784
+ return ret;
1785
+ }
1786
+
17391787 dw_dp_ddc_init(dp);
17401788
17411789 rockchip_connector_bind(&dp->connector, dev, dp->id, &dw_dp_connector_funcs, NULL,
u-boot/drivers/video/drm/dw_hdmi.c
....@@ -7,6 +7,7 @@
77 #include <common.h>
88 #include <malloc.h>
99 #include <syscon.h>
10
+#include <asm/gpio.h>
1011 #include <asm/arch-rockchip/clock.h>
1112 #include <asm/arch/vendor.h>
1213 #include <edid.h>
....@@ -27,6 +28,7 @@
2728 #define HDCP_PRIVATE_KEY_SIZE 280
2829 #define HDCP_KEY_SHA_SIZE 20
2930 #define HDMI_HDCP1X_ID 5
31
+#define HDMI_EDID_BLOCK_LEN 128
3032 /*
3133 * Unless otherwise noted, entries in this table are 100% optimization.
3234 * Values can be obtained from hdmi_compute_n() but that function is
....@@ -181,6 +183,7 @@
181183 bool sink_has_audio;
182184 void *regs;
183185 void *grf;
186
+ void *gpio_base;
184187 struct dw_hdmi_i2c *i2c;
185188
186189 struct {
....@@ -203,6 +206,8 @@
203206
204207 bool hdcp1x_enable;
205208 bool output_bus_format_rgb;
209
+
210
+ struct gpio_desc hpd_gpiod;
206211 };
207212
208213 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
....@@ -409,6 +414,7 @@
409414 {
410415 struct dw_hdmi_i2c *i2c = hdmi->i2c;
411416 int interrupt = 0, i = 20;
417
+ bool read_edid = false;
412418
413419 if (!i2c->is_regaddr) {
414420 printf("set read register address to 0\n");
....@@ -416,14 +422,36 @@
416422 i2c->is_regaddr = true;
417423 }
418424
419
- while (length--) {
420
- hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
421
- if (i2c->is_segment)
422
- hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
423
- HDMI_I2CM_OPERATION);
424
- else
425
- hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
426
- HDMI_I2CM_OPERATION);
425
+ /* edid reads are in 128 bytes. scdc reads are in 1 byte */
426
+ if (length == HDMI_EDID_BLOCK_LEN)
427
+ read_edid = true;
428
+
429
+ while (length > 0) {
430
+ hdmi_writeb(hdmi, i2c->slave_reg, HDMI_I2CM_ADDRESS);
431
+
432
+ if (read_edid) {
433
+ i2c->slave_reg += 8;
434
+ length -= 8;
435
+ } else {
436
+ i2c->slave_reg++;
437
+ length--;
438
+ }
439
+
440
+ if (i2c->is_segment) {
441
+ if (read_edid)
442
+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ8_EXT,
443
+ HDMI_I2CM_OPERATION);
444
+ else
445
+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
446
+ HDMI_I2CM_OPERATION);
447
+ } else {
448
+ if (read_edid)
449
+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ8,
450
+ HDMI_I2CM_OPERATION);
451
+ else
452
+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
453
+ HDMI_I2CM_OPERATION);
454
+ }
427455
428456 while (i--) {
429457 udelay(1000);
....@@ -439,6 +467,10 @@
439467 if (!interrupt) {
440468 printf("[%s] i2c read reg[0x%02x] no interrupt\n",
441469 __func__, i2c->slave_reg);
470
+ hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
471
+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
472
+ HDMI_I2CM_OPERATION);
473
+ udelay(1000);
442474 return -EAGAIN;
443475 }
444476
....@@ -446,11 +478,19 @@
446478 if (interrupt & HDMI_IH_I2CM_STAT0_ERROR) {
447479 printf("[%s] read reg[0x%02x] data error:0x%02x\n",
448480 __func__, i2c->slave_reg, interrupt);
481
+ hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
482
+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
483
+ HDMI_I2CM_OPERATION);
484
+ udelay(1000);
449485 return -EIO;
450486 }
451487
452488 i = 20;
453
- *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
489
+ if (read_edid)
490
+ for (i = 0; i < 8; i++)
491
+ *buf++ = hdmi_readb(hdmi, HDMI_I2CM_READ_BUFF0 + i);
492
+ else
493
+ *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
454494 }
455495 i2c->is_segment = false;
456496
....@@ -490,8 +530,22 @@
490530 break;
491531 }
492532
533
+ if (!interrupt) {
534
+ printf("[%s] i2c write reg[0x%02x] no interrupt\n",
535
+ __func__, i2c->slave_reg);
536
+ hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
537
+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
538
+ HDMI_I2CM_OPERATION);
539
+ udelay(1000);
540
+ return -EAGAIN;
541
+ }
542
+
493543 if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
494544 printf("[%s] write data error\n", __func__);
545
+ hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
546
+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
547
+ HDMI_I2CM_OPERATION);
548
+ udelay(1000);
495549 return -EIO;
496550 } else if (interrupt & m_I2CM_DONE) {
497551 printf("[%s] write offset %02x success\n",
....@@ -959,6 +1013,7 @@
9591013 * but it has a vedor phy.
9601014 */
9611015 if (phy_type == DW_HDMI_PHY_VENDOR_PHY ||
1016
+ hdmi->dev_type == RK3528_HDMI ||
9621017 hdmi->dev_type == RK3328_HDMI ||
9631018 hdmi->dev_type == RK3228_HDMI) {
9641019 /* Vendor PHYs require support from the glue layer. */
....@@ -1042,14 +1097,11 @@
10421097 vmode->mpixelclock, vmode->mtmdsclock);
10431098
10441099 /* Set up HDMI_FC_INVIDCONF
1045
- * fc_invidconf.HDCP_keepout must be set (1'b1)
1046
- * when activate the scrambler feature.
1100
+ * Some display equipments require that the interval
1101
+ * between Video Data and Data island must be at least 58 pixels,
1102
+ * and fc_invidconf.HDCP_keepout set (1'b1) can meet the requirement.
10471103 */
1048
- inv_val = (vmode->mtmdsclock > 340000000 ||
1049
- (hdmi_info->scdc.scrambling.low_rates &&
1050
- hdmi->scramble_low_rates) ?
1051
- HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1052
- HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1104
+ inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE;
10531105
10541106 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
10551107 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
....@@ -1418,13 +1470,8 @@
14181470 HDMI_VP_CONF_PR_EN_MASK |
14191471 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
14201472
1421
- if ((color_depth == 5 && hdmi->previous_mode.htotal % 4) ||
1422
- (color_depth == 6 && hdmi->previous_mode.htotal % 2))
1423
- hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
1424
- HDMI_VP_STUFF);
1425
- else
1426
- hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1427
- HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1473
+ hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
1474
+ HDMI_VP_STUFF);
14281475
14291476 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
14301477
....@@ -1887,6 +1934,7 @@
18871934 hdmi->sample_rate);
18881935 }
18891936
1937
+#ifndef CONFIG_SPL_BUILD
18901938 static int dw_hdmi_hdcp_load_key(struct dw_hdmi *hdmi)
18911939 {
18921940 int i, j, ret, val;
....@@ -1952,6 +2000,7 @@
19522000 free(hdcp_keys);
19532001 return 0;
19542002 }
2003
+#endif
19552004
19562005 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi,
19572006 const struct drm_display_mode *mode)
....@@ -1981,8 +2030,10 @@
19812030 hdmi_modb(hdmi, hdmi_dvi, HDMI_A_HDCPCFG0_HDMIDVI_MASK,
19822031 HDMI_A_HDCPCFG0);
19832032
2033
+#ifndef CONFIG_SPL_BUILD
19842034 if (!(hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS) & 0x3f))
19852035 dw_hdmi_hdcp_load_key(hdmi);
2036
+#endif
19862037
19872038 hdmi_modb(hdmi, HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE,
19882039 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK,
....@@ -2269,13 +2320,18 @@
22692320 {
22702321 struct connector_state *conn_state = &state->conn_state;
22712322 const struct dw_hdmi_plat_data *pdata =
2323
+#ifdef CONFIG_SPL_BUILD
2324
+ (const struct dw_hdmi_plat_data *)conn->data;
2325
+#else
22722326 (const struct dw_hdmi_plat_data *)dev_get_driver_data(conn->dev);
2327
+ ofnode hdmi_node = conn->dev->node;
2328
+ struct device_node *ddc_node;
2329
+ int ret;
2330
+#endif
22732331 struct crtc_state *crtc_state = &state->crtc_state;
22742332 struct dw_hdmi *hdmi;
22752333 struct drm_display_mode *mode_buf;
2276
- ofnode hdmi_node = conn->dev->node;
22772334 u32 val;
2278
- struct device_node *ddc_node;
22792335
22802336 hdmi = malloc(sizeof(struct dw_hdmi));
22812337 if (!hdmi)
....@@ -2285,13 +2341,28 @@
22852341 mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode));
22862342 if (!mode_buf)
22872343 return -ENOMEM;
2344
+
2345
+#ifdef CONFIG_SPL_BUILD
2346
+ hdmi->id = 0;
2347
+ hdmi->regs = (void *)RK3528_HDMI_BASE;
2348
+ hdmi->io_width = 4;
2349
+ hdmi->scramble_low_rates = false;
2350
+ hdmi->hdcp1x_enable = false;
2351
+ hdmi->output_bus_format_rgb = false;
2352
+ conn_state->type = DRM_MODE_CONNECTOR_HDMIA;
2353
+#else
22882354 hdmi->id = of_alias_get_id(ofnode_to_np(hdmi_node), "hdmi");
22892355 if (hdmi->id < 0)
22902356 hdmi->id = 0;
2291
- conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id);
2357
+ conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id);
2358
+#endif
22922359
22932360 memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode));
22942361
2362
+ hdmi->dev_type = pdata->dev_type;
2363
+ hdmi->plat_data = pdata;
2364
+
2365
+#ifndef CONFIG_SPL_BUILD
22952366 hdmi->regs = dev_read_addr_ptr(conn->dev);
22962367 hdmi->io_width = ofnode_read_s32_default(hdmi_node, "reg-io-width", -1);
22972368
....@@ -2309,6 +2380,24 @@
23092380 else
23102381 hdmi->output_bus_format_rgb = false;
23112382
2383
+ ret = dev_read_size(conn->dev, "rockchip,phy-table");
2384
+ if (ret > 0 && hdmi->plat_data->phy_config) {
2385
+ u32 phy_config[ret / 4];
2386
+ int i;
2387
+
2388
+ dev_read_u32_array(conn->dev, "rockchip,phy-table", phy_config, ret / 4);
2389
+
2390
+ for (i = 0; i < ret / 16; i++) {
2391
+ if (phy_config[i * 4] != 0)
2392
+ hdmi->plat_data->phy_config[i].mpixelclock = (u64)phy_config[i * 4];
2393
+ else
2394
+ hdmi->plat_data->phy_config[i].mpixelclock = ~0UL;
2395
+ hdmi->plat_data->phy_config[i].sym_ctr = (u16)phy_config[i * 4 + 1];
2396
+ hdmi->plat_data->phy_config[i].term = (u16)phy_config[i * 4 + 2];
2397
+ hdmi->plat_data->phy_config[i].vlev_ctr = (u16)phy_config[i * 4 + 3];
2398
+ }
2399
+ }
2400
+
23122401 ddc_node = of_parse_phandle(ofnode_to_np(hdmi_node), "ddc-i2c-bus", 0);
23132402 if (ddc_node) {
23142403 uclass_get_device_by_ofnode(UCLASS_I2C, np_to_ofnode(ddc_node),
....@@ -2316,6 +2405,7 @@
23162405 if (hdmi->adap.i2c_bus)
23172406 hdmi->adap.ops = i2c_get_ops(hdmi->adap.i2c_bus);
23182407 }
2408
+#endif
23192409
23202410 hdmi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
23212411 if (hdmi->grf <= 0) {
....@@ -2323,6 +2413,20 @@
23232413 __func__, hdmi->grf);
23242414 return -ENXIO;
23252415 }
2416
+
2417
+#ifdef CONFIG_SPL_BUILD
2418
+ hdmi->gpio_base = (void *)RK3528_GPIO_BASE;
2419
+#else
2420
+ ret = gpio_request_by_name(conn->dev, "hpd-gpios", 0,
2421
+ &hdmi->hpd_gpiod, GPIOD_IS_IN);
2422
+ if (ret && ret != -ENOENT) {
2423
+ printf("%s: Cannot get HPD GPIO: %d\n", __func__, ret);
2424
+ return ret;
2425
+ }
2426
+ hdmi->gpio_base = (void *)dev_read_addr_index(conn->dev, 1);
2427
+#endif
2428
+ if (!hdmi->gpio_base)
2429
+ return -ENODEV;
23262430
23272431 dw_hdmi_set_reg_wr(hdmi);
23282432
....@@ -2345,24 +2449,28 @@
23452449 * Read high and low time from device tree. If not available use
23462450 * the default timing scl clock rate is about 99.6KHz.
23472451 */
2452
+#ifdef CONFIG_SPL_BUILD
2453
+ hdmi->i2c->scl_high_ns = 9625;
2454
+ hdmi->i2c->scl_low_ns = 10000;
2455
+#else
23482456 hdmi->i2c->scl_high_ns =
23492457 ofnode_read_s32_default(hdmi_node,
23502458 "ddc-i2c-scl-high-time-ns", 4708);
23512459 hdmi->i2c->scl_low_ns =
23522460 ofnode_read_s32_default(hdmi_node,
23532461 "ddc-i2c-scl-low-time-ns", 4916);
2462
+#endif
23542463
23552464 dw_hdmi_i2c_init(hdmi);
23562465 conn_state->output_if |= VOP_OUTPUT_IF_HDMI0;
23572466 conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA;
23582467
2359
- hdmi->dev_type = pdata->dev_type;
2360
- hdmi->plat_data = pdata;
23612468 hdmi->edid_data.mode_buf = mode_buf;
23622469 hdmi->sample_rate = 48000;
23632470
23642471 conn->data = hdmi;
2365
- dw_hdmi_set_iomux(hdmi->grf, hdmi->dev_type);
2472
+ dw_hdmi_set_iomux(hdmi->grf, hdmi->gpio_base,
2473
+ &hdmi->hpd_gpiod, hdmi->dev_type);
23662474 dw_hdmi_detect_phy(hdmi);
23672475 dw_hdmi_dev_init(hdmi);
23682476
....@@ -2413,7 +2521,7 @@
24132521
24142522 int rockchip_dw_hdmi_get_timing(struct rockchip_connector *conn, struct display_state *state)
24152523 {
2416
- int ret, i;
2524
+ int ret, i, vic;
24172525 struct connector_state *conn_state = &state->conn_state;
24182526 struct drm_display_mode *mode = &conn_state->mode;
24192527 struct dw_hdmi *hdmi = conn->data;
....@@ -2439,9 +2547,13 @@
24392547 hdmi->sink_has_audio = true;
24402548 do_cea_modes(&hdmi->edid_data, def_modes_vic,
24412549 sizeof(def_modes_vic));
2550
+ hdmi->edid_data.mode_buf[0].type |= DRM_MODE_TYPE_PREFERRED;
24422551 hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0];
24432552 printf("failed to get edid\n");
24442553 }
2554
+#ifdef CONFIG_SPL_BUILD
2555
+ conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id);
2556
+#endif
24452557 drm_rk_filter_whitelist(&hdmi->edid_data);
24462558 if (hdmi->phy.ops->mode_valid)
24472559 hdmi->phy.ops->mode_valid(conn, hdmi, state);
....@@ -2452,9 +2564,20 @@
24522564 return -EINVAL;
24532565 }
24542566
2455
- for (i = 0; i < hdmi->edid_data.modes; i++)
2567
+ for (i = 0; i < hdmi->edid_data.modes; i++) {
24562568 hdmi->edid_data.mode_buf[i].vrefresh =
24572569 drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]);
2570
+
2571
+ vic = drm_match_cea_mode(&hdmi->edid_data.mode_buf[i]);
2572
+ if (hdmi->edid_data.mode_buf[i].picture_aspect_ratio == HDMI_PICTURE_ASPECT_NONE) {
2573
+ if (vic >= 93 && vic <= 95)
2574
+ hdmi->edid_data.mode_buf[i].picture_aspect_ratio =
2575
+ HDMI_PICTURE_ASPECT_16_9;
2576
+ else if (vic == 98)
2577
+ hdmi->edid_data.mode_buf[i].picture_aspect_ratio =
2578
+ HDMI_PICTURE_ASPECT_256_135;
2579
+ }
2580
+ }
24582581
24592582 drm_mode_sort(&hdmi->edid_data);
24602583 drm_rk_selete_output(&hdmi->edid_data, conn_state, &bus_format,
....@@ -2463,7 +2586,6 @@
24632586 *mode = *hdmi->edid_data.preferred_mode;
24642587 hdmi->vic = drm_match_cea_mode(mode);
24652588
2466
- printf("mode:%dx%d\n", mode->hdisplay, mode->vdisplay);
24672589 if (state->force_output)
24682590 bus_format = state->force_bus_format;
24692591 conn_state->bus_format = bus_format;
u-boot/drivers/video/drm/dw_hdmi.h
....@@ -1194,6 +1194,7 @@
11941194 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
11951195
11961196 /* I2CM_OPERATION field values */
1197
+ HDMI_I2CM_OPERATION_BUS_CLEAR = 0x20,
11971198 HDMI_I2CM_OPERATION_WRITE = 0x10,
11981199 HDMI_I2CM_OPERATION_READ8_EXT = 0x8,
11991200 HDMI_I2CM_OPERATION_READ8 = 0x4,
....@@ -1411,6 +1412,7 @@
14111412 enum dw_hdmi_devtype dev_type,
14121413 bool output_bus_format_rgb);
14131414 void inno_dw_hdmi_set_domain(void *grf, int status);
1414
-void dw_hdmi_set_iomux(void *grf, int dev_type);
1415
+void dw_hdmi_set_iomux(void *grf, void *gpio_base, struct gpio_desc *hpd_gpiod,
1416
+ int dev_type);
14151417
14161418 #endif /* _ROCKCHIP_HDMI_H_ */
u-boot/drivers/video/drm/dw_hdmi_qp.c
....@@ -175,6 +175,9 @@
175175 case MEDIA_BUS_FMT_UYVY8_1X16:
176176 case MEDIA_BUS_FMT_UYVY10_1X20:
177177 case MEDIA_BUS_FMT_UYVY12_1X24:
178
+ case MEDIA_BUS_FMT_YUYV8_1X16:
179
+ case MEDIA_BUS_FMT_YUYV10_1X20:
180
+ case MEDIA_BUS_FMT_YUYV12_1X24:
178181 return true;
179182
180183 default:
....@@ -1047,6 +1050,9 @@
10471050 /* HDMI Initialization Step B.2 */
10481051 hdmi->phy.ops->set_pll(conn, hdmi->rk_hdmi, state);
10491052
1053
+ /* Mark yuv422 10bit */
1054
+ if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_YUYV10_1X20)
1055
+ hdmi_writel(hdmi, BIT(20), VIDEO_INTERFACE_CONFIG0);
10501056 rk3588_set_grf_cfg(hdmi->rk_hdmi);
10511057 link_cfg = dw_hdmi_rockchip_get_link_cfg(hdmi->rk_hdmi);
10521058
....@@ -1094,6 +1100,9 @@
10941100 hdmi->phy.enabled = true;
10951101 printf("%s DVI mode\n", __func__);
10961102 }
1103
+
1104
+ /* Mark uboot hdmi is enabled */
1105
+ hdmi_writel(hdmi, BIT(21), VIDEO_INTERFACE_CONFIG0);
10971106
10981107 return 0;
10991108 }
....@@ -1239,9 +1248,23 @@
12391248 return 0;
12401249 }
12411250
1242
-int rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector *conn, struct display_state *state)
1251
+static void rockchip_dw_hdmi_qp_mode_valid(struct dw_hdmi_qp *hdmi)
12431252 {
1244
- int ret, i;
1253
+ struct hdmi_edid_data *edid_data = &hdmi->edid_data;
1254
+ int i;
1255
+
1256
+ for (i = 0; i < edid_data->modes; i++) {
1257
+ if (edid_data->mode_buf[i].invalid)
1258
+ continue;
1259
+ if (edid_data->mode_buf[i].clock <= 25000)
1260
+ edid_data->mode_buf[i].invalid = true;
1261
+ }
1262
+}
1263
+
1264
+static int _rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector *conn,
1265
+ struct display_state *state, int edid_status)
1266
+{
1267
+ int i;
12451268 struct connector_state *conn_state = &state->conn_state;
12461269 struct drm_display_mode *mode = &conn_state->mode;
12471270 struct dw_hdmi_qp *hdmi = conn->data;
....@@ -1254,14 +1277,13 @@
12541277 if (!hdmi)
12551278 return -EFAULT;
12561279
1257
- ret = drm_do_get_edid(&hdmi->adap, conn_state->edid);
1258
- if (!ret) {
1280
+ if (!edid_status) {
12591281 hdmi->sink_is_hdmi =
12601282 drm_detect_hdmi_monitor(edid);
12611283 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1262
- ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid);
1284
+ edid_status = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid);
12631285 }
1264
- if (ret < 0) {
1286
+ if (edid_status < 0) {
12651287 hdmi->sink_is_hdmi = true;
12661288 hdmi->sink_has_audio = true;
12671289 do_cea_modes(&hdmi->edid_data, def_modes_vic,
....@@ -1270,8 +1292,7 @@
12701292 printf("failed to get edid\n");
12711293 }
12721294 drm_rk_filter_whitelist(&hdmi->edid_data);
1273
- if (hdmi->phy.ops->mode_valid)
1274
- hdmi->phy.ops->mode_valid(hdmi->rk_hdmi, state);
1295
+ rockchip_dw_hdmi_qp_mode_valid(hdmi);
12751296 drm_mode_max_resolution_filter(&hdmi->edid_data,
12761297 &state->crtc_state.max_output);
12771298 if (!drm_mode_prune_invalid(&hdmi->edid_data)) {
....@@ -1298,15 +1319,17 @@
12981319 hdmi->hdmi_data.enc_out_bus_format = bus_format;
12991320
13001321 switch (bus_format) {
1301
- case MEDIA_BUS_FMT_UYVY10_1X20:
1302
- conn_state->bus_format = MEDIA_BUS_FMT_YUV10_1X30;
1322
+ case MEDIA_BUS_FMT_YUYV10_1X20:
1323
+ conn_state->bus_format = MEDIA_BUS_FMT_YUYV10_1X20;
13031324 hdmi->hdmi_data.enc_in_bus_format =
1304
- MEDIA_BUS_FMT_YUV10_1X30;
1325
+ MEDIA_BUS_FMT_YUYV10_1X20;
1326
+ conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV422;
13051327 break;
1306
- case MEDIA_BUS_FMT_UYVY8_1X16:
1307
- conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24;
1328
+ case MEDIA_BUS_FMT_YUYV8_1X16:
1329
+ conn_state->bus_format = MEDIA_BUS_FMT_YUYV8_1X16;
13081330 hdmi->hdmi_data.enc_in_bus_format =
1309
- MEDIA_BUS_FMT_YUV8_1X24;
1331
+ MEDIA_BUS_FMT_YUYV8_1X16;
1332
+ conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV422;
13101333 break;
13111334 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
13121335 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
....@@ -1334,6 +1357,21 @@
13341357 return 0;
13351358 }
13361359
1360
+int rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector *conn, struct display_state *state)
1361
+{
1362
+ struct connector_state *conn_state = &state->conn_state;
1363
+ struct dw_hdmi_qp *hdmi = conn->data;
1364
+ int ret;
1365
+
1366
+ ret = drm_do_get_edid(&hdmi->adap, conn_state->edid);
1367
+
1368
+ if (conn_state->secondary)
1369
+ _rockchip_dw_hdmi_qp_get_timing(conn_state->secondary, state, ret);
1370
+
1371
+ return _rockchip_dw_hdmi_qp_get_timing(conn, state, ret);
1372
+}
1373
+
1374
+
13371375 int rockchip_dw_hdmi_qp_detect(struct rockchip_connector *conn, struct display_state *state)
13381376 {
13391377 int ret;
u-boot/drivers/video/drm/dw_mipi_dsi.c
....@@ -1489,6 +1489,21 @@
14891489 .max_bit_rate_per_lane = 1500000000UL,
14901490 };
14911491
1492
+static const u32 rk3562_dsi_grf_reg_fields[MAX_FIELDS] = {
1493
+ [DPIUPDATECFG] = GRF_REG_FIELD(0x05d0, 2, 2),
1494
+ [DPICOLORM] = GRF_REG_FIELD(0x05d0, 1, 1),
1495
+ [DPISHUTDN] = GRF_REG_FIELD(0x05d0, 0, 0),
1496
+ [SKEWCALHS] = GRF_REG_FIELD(0x05d4, 11, 15),
1497
+ [FORCETXSTOPMODE] = GRF_REG_FIELD(0x05d4, 4, 7),
1498
+ [TURNDISABLE] = GRF_REG_FIELD(0x05d4, 2, 2),
1499
+ [FORCERXMODE] = GRF_REG_FIELD(0x05d4, 0, 0),
1500
+};
1501
+
1502
+static const struct dw_mipi_dsi_plat_data rk3562_mipi_dsi_plat_data = {
1503
+ .dsi0_grf_reg_fields = rk3562_dsi_grf_reg_fields,
1504
+ .max_bit_rate_per_lane = 1200000000UL,
1505
+};
1506
+
14921507 static const u32 rk3568_dsi0_grf_reg_fields[MAX_FIELDS] = {
14931508 [DPIUPDATECFG] = GRF_REG_FIELD(0x0360, 2, 2),
14941509 [DPICOLORM] = GRF_REG_FIELD(0x0360, 1, 1),
....@@ -1573,6 +1588,10 @@
15731588 .data = (ulong)&rk3399_mipi_dsi_plat_data,
15741589 },
15751590 {
1591
+ .compatible = "rockchip,rk3562-mipi-dsi",
1592
+ .data = (ulong)&rk3562_mipi_dsi_plat_data,
1593
+ },
1594
+ {
15761595 .compatible = "rockchip,rk3568-mipi-dsi",
15771596 .data = (ulong)&rk3568_mipi_dsi_plat_data,
15781597 },
u-boot/drivers/video/drm/dw_mipi_dsi2.c
....@@ -12,6 +12,7 @@
1212 #include <common.h>
1313 #include <errno.h>
1414 #include <asm/unaligned.h>
15
+#include <asm/gpio.h>
1516 #include <asm/io.h>
1617 #include <asm/hardware.h>
1718 #include <dm/device.h>
....@@ -22,7 +23,6 @@
2223 #include <asm/arch-rockchip/clock.h>
2324 #include <linux/iopoll.h>
2425
25
-#include "rockchip_bridge.h"
2626 #include "rockchip_display.h"
2727 #include "rockchip_crtc.h"
2828 #include "rockchip_connector.h"
....@@ -289,6 +289,7 @@
289289 struct drm_display_mode mode;
290290 bool data_swap;
291291
292
+ struct gpio_desc te_gpio;
292293 struct mipi_dsi_device *device;
293294 struct mipi_dphy_configure mipi_dphy_cfg;
294295 const struct dw_mipi_dsi2_plat_data *pdata;
....@@ -693,42 +694,79 @@
693694 static int dw_mipi_dsi2_connector_pre_init(struct rockchip_connector *conn,
694695 struct display_state *state)
695696 {
697
+ struct connector_state *conn_state = &state->conn_state;
696698 struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev);
697699 struct mipi_dsi_host *host = dev_get_platdata(dsi2->dev);
698700 struct mipi_dsi_device *device;
699701 char name[20];
700
- struct udevice *dev;
701702
702
- device = calloc(1, sizeof(struct dw_mipi_dsi2));
703
- if (!device)
704
- return -ENOMEM;
703
+ conn_state->type = DRM_MODE_CONNECTOR_DSI;
705704
706
- if (conn->bridge)
707
- dev = conn->bridge->dev;
708
- else if (conn->panel)
709
- dev = conn->panel->dev;
710
- else
711
- return -ENODEV;
705
+ if (conn->bridge) {
706
+ device = dev_get_platdata(conn->bridge->dev);
707
+ if (!device)
708
+ return -ENODEV;
712709
713
- device->dev = dev;
714
- device->host = host;
715
- device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4);
716
- device->channel = dev_read_u32_default(dev, "reg", 0);
717
- device->format = dev_read_u32_default(dev, "dsi,format",
718
- MIPI_DSI_FMT_RGB888);
719
- device->mode_flags = dev_read_u32_default(dev, "dsi,flags",
720
- MIPI_DSI_MODE_VIDEO |
721
- MIPI_DSI_MODE_VIDEO_BURST |
722
- MIPI_DSI_MODE_VIDEO_HBP |
723
- MIPI_DSI_MODE_LPM |
724
- MIPI_DSI_MODE_EOT_PACKET);
710
+ device->host = host;
711
+ sprintf(name, "%s.%d", host->dev->name, device->channel);
712
+ device_set_name(conn->bridge->dev, name);
713
+ mipi_dsi_attach(device);
714
+ }
725715
726
- sprintf(name, "%s.%d", host->dev->name, device->channel);
727
- device_set_name(dev, name);
728
- dsi2->device = device;
729
- dev->parent_platdata = device;
716
+ return 0;
717
+}
730718
731
- mipi_dsi_attach(dsi2->device);
719
+static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2)
720
+{
721
+ struct udevice *dev = dsi2->device->dev;
722
+ struct rockchip_cmd_header *header;
723
+ struct drm_dsc_picture_parameter_set *pps = NULL;
724
+ u8 *dsc_packed_pps;
725
+ const void *data;
726
+ int len;
727
+
728
+ dsi2->c_option = dev_read_bool(dev, "phy-c-option");
729
+ dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable");
730
+ dsi2->dsc_enable = dev_read_bool(dev, "compressed-data");
731
+
732
+ if (dsi2->slave) {
733
+ dsi2->slave->c_option = dsi2->c_option;
734
+ dsi2->slave->scrambling_en = dsi2->scrambling_en;
735
+ dsi2->slave->dsc_enable = dsi2->dsc_enable;
736
+ }
737
+
738
+ dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0);
739
+ dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0);
740
+ dsi2->version_major = dev_read_u32_default(dev, "version-major", 0);
741
+ dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0);
742
+
743
+ data = dev_read_prop(dev, "panel-init-sequence", &len);
744
+ if (!data)
745
+ return -EINVAL;
746
+
747
+ while (len > sizeof(*header)) {
748
+ header = (struct rockchip_cmd_header *)data;
749
+ data += sizeof(*header);
750
+ len -= sizeof(*header);
751
+
752
+ if (header->payload_length > len)
753
+ return -EINVAL;
754
+
755
+ if (header->data_type == MIPI_DSI_PICTURE_PARAMETER_SET) {
756
+ dsc_packed_pps = calloc(1, header->payload_length);
757
+ if (!dsc_packed_pps)
758
+ return -ENOMEM;
759
+
760
+ memcpy(dsc_packed_pps, data, header->payload_length);
761
+ pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps;
762
+ break;
763
+ }
764
+
765
+ data += header->payload_length;
766
+ len -= header->payload_length;
767
+ }
768
+
769
+ dsi2->pps = pps;
732770
733771 return 0;
734772 }
....@@ -792,6 +830,13 @@
792830 dsi2->slave->dcphy.phy = phy;
793831 if (phy->funcs && phy->funcs->init)
794832 return phy->funcs->init(phy);
833
+ }
834
+
835
+ dw_mipi_dsi2_get_dsc_params_from_sink(dsi2);
836
+
837
+ if (dm_gpio_is_valid(&dsi2->te_gpio)) {
838
+ cstate->soft_te = true;
839
+ conn_state->te_gpio = &dsi2->te_gpio;
795840 }
796841
797842 if (dsi2->dsc_enable) {
....@@ -905,7 +950,7 @@
905950
906951 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2)
907952 {
908
- u32 sys_clk = SYS_CLK / MSEC_PER_SEC;
953
+ u32 sys_clk = SYS_CLK / USEC_PER_SEC;
909954 u32 esc_clk_div;
910955 u32 val = 0;
911956
....@@ -913,7 +958,7 @@
913958 val |= NON_CONTINUOUS_CLK;
914959
915960 /* The Escape clock ranges from 1MHz to 20MHz. */
916
- esc_clk_div = DIV_ROUND_UP(sys_clk, 10 * 2);
961
+ esc_clk_div = DIV_ROUND_UP(sys_clk, 20 * 2);
917962 val |= PHY_LPTX_CLK_DIV(esc_clk_div);
918963
919964 dsi_write(dsi2, DSI2_PHY_CLK_CFG, val);
....@@ -1102,6 +1147,41 @@
11021147 return 0;
11031148 }
11041149
1150
+static int dw_mipi_dsi2_connector_mode_valid(struct rockchip_connector *conn,
1151
+ struct display_state *state)
1152
+{
1153
+ struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev);
1154
+ struct connector_state *conn_state = &state->conn_state;
1155
+ u8 min_pixels = dsi2->slave ? 8 : 4;
1156
+ struct videomode vm;
1157
+
1158
+ drm_display_mode_to_videomode(&conn_state->mode, &vm);
1159
+
1160
+ /*
1161
+ * the minimum region size (HSA,HBP,HACT,HFP) is 4 pixels
1162
+ * which is the ip known issues and limitations.
1163
+ */
1164
+ if (!(vm.hsync_len < min_pixels || vm.hback_porch < min_pixels ||
1165
+ vm.hfront_porch < min_pixels || vm.hactive < min_pixels))
1166
+ return MODE_OK;
1167
+
1168
+ if (vm.hsync_len < min_pixels)
1169
+ vm.hsync_len = min_pixels;
1170
+
1171
+ if (vm.hback_porch < min_pixels)
1172
+ vm.hback_porch = min_pixels;
1173
+
1174
+ if (vm.hfront_porch < min_pixels)
1175
+ vm.hfront_porch = min_pixels;
1176
+
1177
+ if (vm.hactive < min_pixels)
1178
+ vm.hactive = min_pixels;
1179
+
1180
+ drm_display_mode_from_videomode(&vm, &conn_state->mode);
1181
+
1182
+ return MODE_OK;
1183
+}
1184
+
11051185 static const struct rockchip_connector_funcs dw_mipi_dsi2_connector_funcs = {
11061186 .pre_init = dw_mipi_dsi2_connector_pre_init,
11071187 .init = dw_mipi_dsi2_connector_init,
....@@ -1109,6 +1189,7 @@
11091189 .unprepare = dw_mipi_dsi2_connector_unprepare,
11101190 .enable = dw_mipi_dsi2_connector_enable,
11111191 .disable = dw_mipi_dsi2_connector_disable,
1192
+ .mode_valid = dw_mipi_dsi2_connector_mode_valid,
11121193 };
11131194
11141195 static int dw_mipi_dsi2_probe(struct udevice *dev)
....@@ -1132,6 +1213,13 @@
11321213 id = of_alias_get_id(ofnode_to_np(dev->node), "dsi");
11331214 if (id < 0)
11341215 id = 0;
1216
+
1217
+ ret = gpio_request_by_name(dev, "te-gpios", 0,
1218
+ &dsi2->te_gpio, GPIOD_IS_IN);
1219
+ if (ret && ret != -ENOENT) {
1220
+ printf("%s: Cannot get TE GPIO: %d\n", __func__, ret);
1221
+ return ret;
1222
+ }
11351223
11361224 dsi2->dev = dev;
11371225 dsi2->pdata = pdata;
....@@ -1185,61 +1273,6 @@
11851273 return dw_mipi_dsi2_transfer(dsi2, msg);
11861274 }
11871275
1188
-static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2)
1189
-{
1190
- struct udevice *dev = dsi2->device->dev;
1191
- struct rockchip_cmd_header *header;
1192
- struct drm_dsc_picture_parameter_set *pps = NULL;
1193
- u8 *dsc_packed_pps;
1194
- const void *data;
1195
- int len;
1196
-
1197
- dsi2->c_option = dev_read_bool(dev, "phy-c-option");
1198
- dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable");
1199
- dsi2->dsc_enable = dev_read_bool(dev, "compressed-data");
1200
-
1201
- if (dsi2->slave) {
1202
- dsi2->slave->c_option = dsi2->c_option;
1203
- dsi2->slave->scrambling_en = dsi2->scrambling_en;
1204
- dsi2->slave->dsc_enable = dsi2->dsc_enable;
1205
- }
1206
-
1207
- dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0);
1208
- dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0);
1209
- dsi2->version_major = dev_read_u32_default(dev, "version-major", 0);
1210
- dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0);
1211
-
1212
- data = dev_read_prop(dev, "panel-init-sequence", &len);
1213
- if (!data)
1214
- return -EINVAL;
1215
-
1216
- while (len > sizeof(*header)) {
1217
- header = (struct rockchip_cmd_header *)data;
1218
- data += sizeof(*header);
1219
- len -= sizeof(*header);
1220
-
1221
- if (header->payload_length > len)
1222
- return -EINVAL;
1223
-
1224
- if (header->data_type == MIPI_DSI_PICTURE_PARAMETER_SET) {
1225
- dsc_packed_pps = calloc(1, header->payload_length);
1226
- if (!dsc_packed_pps)
1227
- return -ENOMEM;
1228
-
1229
- memcpy(dsc_packed_pps, data, header->payload_length);
1230
- pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps;
1231
- break;
1232
- }
1233
-
1234
- data += header->payload_length;
1235
- len -= header->payload_length;
1236
- }
1237
-
1238
- dsi2->pps = pps;
1239
-
1240
- return 0;
1241
-}
1242
-
12431276 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host,
12441277 struct mipi_dsi_device *device)
12451278 {
....@@ -1252,8 +1285,7 @@
12521285 dsi2->channel = device->channel;
12531286 dsi2->format = device->format;
12541287 dsi2->mode_flags = device->mode_flags;
1255
-
1256
- dw_mipi_dsi2_get_dsc_params_from_sink(dsi2);
1288
+ dsi2->device = device;
12571289
12581290 return 0;
12591291 }
....@@ -1273,6 +1305,45 @@
12731305 return dm_scan_fdt_dev(dev);
12741306 }
12751307
1308
+static int dw_mipi_dsi2_child_post_bind(struct udevice *dev)
1309
+{
1310
+ struct mipi_dsi_host *host = dev_get_platdata(dev->parent);
1311
+ struct mipi_dsi_device *device = dev_get_parent_platdata(dev);
1312
+ char name[20];
1313
+
1314
+ sprintf(name, "%s.%d", host->dev->name, device->channel);
1315
+ device_set_name(dev, name);
1316
+
1317
+ device->dev = dev;
1318
+ device->host = host;
1319
+ device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4);
1320
+ device->format = dev_read_u32_default(dev, "dsi,format",
1321
+ MIPI_DSI_FMT_RGB888);
1322
+ device->mode_flags = dev_read_u32_default(dev, "dsi,flags",
1323
+ MIPI_DSI_MODE_VIDEO |
1324
+ MIPI_DSI_MODE_VIDEO_BURST |
1325
+ MIPI_DSI_MODE_VIDEO_HBP |
1326
+ MIPI_DSI_MODE_LPM |
1327
+ MIPI_DSI_MODE_EOT_PACKET);
1328
+ device->channel = dev_read_u32_default(dev, "reg", 0);
1329
+
1330
+ return 0;
1331
+}
1332
+
1333
+static int dw_mipi_dsi2_child_pre_probe(struct udevice *dev)
1334
+{
1335
+ struct mipi_dsi_device *device = dev_get_parent_platdata(dev);
1336
+ int ret;
1337
+
1338
+ ret = mipi_dsi_attach(device);
1339
+ if (ret) {
1340
+ dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
1341
+ return ret;
1342
+ }
1343
+
1344
+ return 0;
1345
+}
1346
+
12761347 U_BOOT_DRIVER(dw_mipi_dsi2) = {
12771348 .name = "dw_mipi_dsi2",
12781349 .id = UCLASS_DISPLAY,
....@@ -1280,5 +1351,8 @@
12801351 .probe = dw_mipi_dsi2_probe,
12811352 .bind = dw_mipi_dsi2_bind,
12821353 .priv_auto_alloc_size = sizeof(struct dw_mipi_dsi2),
1354
+ .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device),
12831355 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_host),
1356
+ .child_post_bind = dw_mipi_dsi2_child_post_bind,
1357
+ .child_pre_probe = dw_mipi_dsi2_child_pre_probe,
12841358 };
u-boot/drivers/video/drm/max96745.c
....@@ -9,41 +9,111 @@
99 #include <i2c.h>
1010 #include <max96745.h>
1111 #include <video_bridge.h>
12
+#include <linux/iopoll.h>
1213
1314 #include "rockchip_bridge.h"
1415 #include "rockchip_display.h"
1516 #include "rockchip_panel.h"
1617
17
-struct max96745_bridge_priv {
18
- struct gpio_desc lock_gpio;
19
-};
20
-
21
-static bool max96745_bridge_detect(struct rockchip_bridge *bridge)
18
+static bool max96745_bridge_link_locked(struct udevice *dev)
2219 {
23
- struct max96745_bridge_priv *priv = dev_get_priv(bridge->dev);
20
+ int ret;
2421
25
- if (!dm_gpio_get_value(&priv->lock_gpio))
22
+ ret = dm_i2c_reg_read(dev->parent, 0x002a);
23
+ if (ret < 0)
24
+ return false;
25
+
26
+ if (!FIELD_GET(LINK_LOCKED, ret))
2627 return false;
2728
2829 return true;
2930 }
3031
32
+static bool max96745_bridge_detect(struct rockchip_bridge *bridge)
33
+{
34
+ return max96745_bridge_link_locked(bridge->dev);
35
+}
36
+
37
+static void max96745_bridge_enable(struct rockchip_bridge *bridge)
38
+{
39
+ struct udevice *dev = bridge->dev;
40
+ struct drm_display_mode *mode = &bridge->state->conn_state.mode;
41
+ u8 cxtp, tx_rate;
42
+ int ret;
43
+
44
+ ret = dm_i2c_reg_read(dev->parent, 0x0011);
45
+ if (ret < 0)
46
+ return;
47
+
48
+ cxtp = FIELD_GET(CXTP_A, ret);
49
+
50
+ ret = dm_i2c_reg_read(dev->parent, 0x0028);
51
+ if (ret < 0)
52
+ return;
53
+
54
+ tx_rate = FIELD_GET(TX_RATE, ret);
55
+
56
+ if (!cxtp && mode->clock > 95000 && tx_rate == 1) {
57
+ ret = dm_i2c_reg_clrset(dev->parent, 0x0028, TX_RATE,
58
+ FIELD_PREP(TX_RATE, 2));
59
+ if (ret < 0)
60
+ return;
61
+
62
+ ret = dm_i2c_reg_clrset(dev->parent, 0x0029, RESET_ONESHOT,
63
+ FIELD_PREP(RESET_ONESHOT, 1));
64
+ if (ret < 0)
65
+ return;
66
+
67
+ if (readx_poll_timeout(max96745_bridge_link_locked, dev, ret,
68
+ ret, 200000))
69
+ dev_err(dev, "%s: GMSL link not locked\n", __func__);
70
+ }
71
+}
72
+
73
+static void max96745_bridge_post_disable(struct rockchip_bridge *bridge)
74
+{
75
+ struct udevice *dev = bridge->dev;
76
+ u8 cxtp, tx_rate;
77
+ int ret;
78
+
79
+ ret = dm_i2c_reg_read(dev->parent, 0x0011);
80
+ if (ret < 0)
81
+ return;
82
+
83
+ cxtp = FIELD_GET(CXTP_A, ret);
84
+
85
+ ret = dm_i2c_reg_read(dev->parent, 0x0028);
86
+ if (ret < 0)
87
+ return;
88
+
89
+ tx_rate = FIELD_GET(TX_RATE, ret);
90
+
91
+ if (!cxtp && tx_rate == 2) {
92
+ ret = dm_i2c_reg_clrset(dev->parent, 0x0028, TX_RATE,
93
+ FIELD_PREP(TX_RATE, 1));
94
+ if (ret < 0)
95
+ return;
96
+
97
+ ret = dm_i2c_reg_clrset(dev->parent, 0x0029, RESET_ONESHOT,
98
+ FIELD_PREP(RESET_ONESHOT, 1));
99
+ if (ret < 0)
100
+ return;
101
+
102
+ if (readx_poll_timeout(max96745_bridge_link_locked, dev, ret,
103
+ ret, 200000))
104
+ dev_err(dev, "%s: GMSL link not locked\n", __func__);
105
+ }
106
+}
107
+
31108 static const struct rockchip_bridge_funcs max96745_bridge_funcs = {
32
- .detect = max96745_bridge_detect,
109
+ .detect = max96745_bridge_detect,
110
+ .enable = max96745_bridge_enable,
111
+ .post_disable = max96745_bridge_post_disable,
33112 };
34113
35114 static int max96745_bridge_probe(struct udevice *dev)
36115 {
37
- struct max96745_bridge_priv *priv = dev_get_priv(dev);
38116 struct rockchip_bridge *bridge;
39
- int ret;
40
-
41
- ret = gpio_request_by_name(dev, "lock-gpios", 0, &priv->lock_gpio,
42
- GPIOD_IS_IN);
43
- if (ret) {
44
- dev_err(dev, "failed to get lock GPIO: %d\n", ret);
45
- return ret;
46
- }
47117
48118 bridge = calloc(1, sizeof(*bridge));
49119 if (!bridge)
....@@ -66,5 +136,4 @@
66136 .id = UCLASS_VIDEO_BRIDGE,
67137 .of_match = max96745_bridge_of_match,
68138 .probe = max96745_bridge_probe,
69
- .priv_auto_alloc_size = sizeof(struct max96745_bridge_priv),
70139 };
u-boot/drivers/video/drm/max96752f.c
deleted file mode 100644
....@@ -1,79 +0,0 @@
1
-// SPDX-License-Identifier: GPL-2.0+
2
-/*
3
- * (C) Copyright 2022 Rockchip Electronics Co., Ltd
4
- */
5
-
6
-#include <common.h>
7
-#include <dm.h>
8
-#include <errno.h>
9
-#include <i2c.h>
10
-#include <linux/media-bus-format.h>
11
-#include <max96752f.h>
12
-#include <video_bridge.h>
13
-
14
-#include "rockchip_bridge.h"
15
-#include "rockchip_display.h"
16
-#include "rockchip_panel.h"
17
-
18
-static void max96752f_bridge_pre_enable(struct rockchip_bridge *bridge)
19
-{
20
- struct udevice *dev = bridge->dev;
21
- struct connector_state *conn_state = &bridge->state->conn_state;
22
- bool oldi_format, oldi_4th_lane;
23
-
24
- max96752f_init(dev->parent);
25
-
26
- switch (conn_state->bus_format) {
27
- case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
28
- oldi_4th_lane = false;
29
- oldi_format = 0x0;
30
- break;
31
- case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
32
- oldi_4th_lane = true;
33
- oldi_format = 0x0;
34
- break;
35
- case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
36
- oldi_4th_lane = false;
37
- oldi_format = 0x1;
38
- break;
39
- default:
40
- oldi_4th_lane = false;
41
- oldi_format = 0x1;
42
- break;
43
- }
44
-
45
- dm_i2c_reg_clrset(dev->parent, 0x01ce, OLDI_FORMAT | OLDI_4TH_LANE,
46
- FIELD_PREP(OLDI_4TH_LANE, oldi_4th_lane) |
47
- FIELD_PREP(OLDI_FORMAT, oldi_format));
48
-}
49
-
50
-static const struct rockchip_bridge_funcs max96752f_bridge_funcs = {
51
- .pre_enable = max96752f_bridge_pre_enable,
52
-};
53
-
54
-static int max96752f_bridge_probe(struct udevice *dev)
55
-{
56
- struct rockchip_bridge *bridge;
57
-
58
- bridge = calloc(1, sizeof(*bridge));
59
- if (!bridge)
60
- return -ENOMEM;
61
-
62
- dev->driver_data = (ulong)bridge;
63
- bridge->dev = dev;
64
- bridge->funcs = &max96752f_bridge_funcs;
65
-
66
- return 0;
67
-}
68
-
69
-static const struct udevice_id max96752f_bridge_of_match[] = {
70
- { .compatible = "maxim,max96752f-bridge", },
71
- { }
72
-};
73
-
74
-U_BOOT_DRIVER(max96752f_bridge) = {
75
- .name = "max96752f_bridge",
76
- .id = UCLASS_VIDEO_BRIDGE,
77
- .of_match = max96752f_bridge_of_match,
78
- .probe = max96752f_bridge_probe,
79
-};
u-boot/drivers/video/drm/max96755f.c
....@@ -9,6 +9,7 @@
99 #include <i2c.h>
1010 #include <max96755f.h>
1111 #include <video_bridge.h>
12
+#include <drm/drm_mipi_dsi.h>
1213 #include <dm/of_access.h>
1314 #include <linux/media-bus-format.h>
1415
....@@ -21,9 +22,18 @@
2122 struct drm_display_mode *mode = &priv->mode;
2223 u32 hfp, hsa, hbp, hact;
2324 u32 vact, vsa, vfp, vbp;
25
+ u8 lane_map;
2426
2527 dm_i2c_reg_clrset(priv->dev, 0x0331, NUM_LANES,
2628 FIELD_PREP(NUM_LANES, priv->num_lanes - 1));
29
+
30
+ lane_map = (priv->dsi_lane_map[0] & 0xff) << 4 |
31
+ (priv->dsi_lane_map[1] & 0xff) << 6 |
32
+ (priv->dsi_lane_map[2] & 0xff) << 0 |
33
+ (priv->dsi_lane_map[3] & 0xff) << 2;
34
+
35
+ dm_i2c_reg_write(priv->dev, 0x0332, lane_map);
36
+
2737 if (!priv->dpi_deskew_en)
2838 return;
2939
....@@ -148,11 +158,26 @@
148158 .detect = max96755f_bridge_detect,
149159 };
150160
161
+static int max96755f_bridge_bind(struct udevice *dev)
162
+{
163
+ struct mipi_dsi_device *device = dev_get_platdata(dev);
164
+
165
+ device->dev = dev;
166
+ device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4);
167
+ device->format = dev_read_u32_default(dev, "dsi,format",
168
+ MIPI_DSI_FMT_RGB888);
169
+ device->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
170
+ device->channel = dev_read_u32_default(dev, "reg", 0);
171
+
172
+ return 0;
173
+}
174
+
151175 static int max96755f_bridge_probe(struct udevice *dev)
152176 {
153177 struct rockchip_bridge *bridge;
154178 struct max96755f_priv *priv = dev_get_priv(dev->parent);
155
- int ret;
179
+ const struct device_node *np = ofnode_to_np(dev->node);
180
+ int i, len, ret;
156181
157182 bridge = calloc(1, sizeof(*bridge));
158183 if (!bridge)
....@@ -165,6 +190,24 @@
165190 priv->num_lanes = dev_read_u32_default(dev, "dsi,lanes", 4);
166191 priv->dv_swp_ab = dev_read_bool(dev, "vd-swap-ab");
167192 priv->dpi_deskew_en = dev_read_bool(dev, "dpi-deskew-en");
193
+
194
+ for ( i = 0; i < priv->num_lanes; i++)
195
+ priv->dsi_lane_map[i] = i;
196
+
197
+ if (of_find_property(np, "maxim,dsi-lane-map", &len)) {
198
+ len /= sizeof(u32);
199
+ if (priv->num_lanes != len) {
200
+ printf("invalid number of lane map\n");
201
+ return -EINVAL;
202
+ }
203
+ }
204
+
205
+ ret = of_read_u32_array(np, "maxim,dsi-lane-map",
206
+ priv->dsi_lane_map, priv->num_lanes);
207
+ if (ret) {
208
+ printf("get dsi lane map failed\n");
209
+ return -EINVAL;
210
+ }
168211
169212 ret = gpio_request_by_name(dev, "lock-gpios", 0, &priv->lock_gpio,
170213 GPIOD_IS_IN);
....@@ -186,4 +229,6 @@
186229 .id = UCLASS_VIDEO_BRIDGE,
187230 .of_match = max96755f_bridge_of_match,
188231 .probe = max96755f_bridge_probe,
232
+ .bind = max96755f_bridge_bind,
233
+ .platdata_auto_alloc_size = sizeof(struct mipi_dsi_device),
189234 };
u-boot/drivers/video/drm/panel-maxim-deserializer.c
deleted file mode 100644
....@@ -1,300 +0,0 @@
1
-// SPDX-License-Identifier: GPL-2.0+
2
-/*
3
- * (C) Copyright 2022 Rockchip Electronics Co., Ltd
4
- */
5
-
6
-#include <config.h>
7
-#include <common.h>
8
-#include <backlight.h>
9
-#include <errno.h>
10
-#include <malloc.h>
11
-#include <video.h>
12
-
13
-#include <asm/gpio.h>
14
-#include <dm/device.h>
15
-#include <dm/read.h>
16
-#include <dm/pinctrl.h>
17
-#include <dm/uclass-id.h>
18
-#include <linux/media-bus-format.h>
19
-
20
-#include "rockchip_display.h"
21
-#include "rockchip_panel.h"
22
-
23
-struct maxim_deserializer_panel;
24
-
25
-struct maxim_deserializer_panel_desc {
26
- const char *name;
27
- u16 id;
28
- struct drm_display_mode mode;
29
- u32 width_mm;
30
- u32 height_mm;
31
-
32
- struct {
33
- const char *name;
34
- u8 addr;
35
- u8 dev_id;
36
- } deserializer;
37
-
38
- void (*prepare)(struct maxim_deserializer_panel *p);
39
- void (*unprepare)(struct maxim_deserializer_panel *p);
40
- void (*enable)(struct maxim_deserializer_panel *p);
41
- void (*disable)(struct maxim_deserializer_panel *p);
42
-};
43
-
44
-struct maxim_deserializer_panel {
45
- struct udevice *dev;
46
- struct udevice *backlight;
47
- struct gpio_desc enable_gpio;
48
-
49
- /* the panel desc as detected */
50
- const struct maxim_deserializer_panel_desc *desc;
51
-};
52
-
53
-static void maxim_max96752f_panel_prepare(struct maxim_deserializer_panel *p)
54
-{
55
- pinctrl_select_state(p->dev, p->desc->name ?
56
- p->desc->name : p->desc->deserializer.name);
57
-
58
- dm_i2c_reg_write(p->dev, 0x0002, 0x43);
59
- dm_i2c_reg_write(p->dev, 0x0140, 0x20);
60
-
61
- dm_i2c_reg_write(p->dev, 0x01ce, 0x5e); /* oldi */
62
- dm_i2c_reg_write(p->dev, 0x020c, 0x84); /* bl_pwm */
63
- dm_i2c_reg_write(p->dev, 0x0206, 0x83); /* tp_int */
64
-
65
- dm_i2c_reg_write(p->dev, 0x0215, 0x90); /* lcd_en */
66
- mdelay(20);
67
-}
68
-
69
-static void maxim_max96752f_panel_unprepare(struct maxim_deserializer_panel *p)
70
-{
71
- dm_i2c_reg_write(p->dev, 0x0215, 0x80); /* lcd_en */
72
-}
73
-
74
-static void maxim_max96752f_panel_enable(struct maxim_deserializer_panel *p)
75
-{
76
- dm_i2c_reg_write(p->dev, 0x0227, 0x90); /* lcd_rst */
77
- mdelay(20);
78
- dm_i2c_reg_write(p->dev, 0x020f, 0x90); /* tp_rst */
79
- mdelay(100);
80
- dm_i2c_reg_write(p->dev, 0x0221, 0x90); /* lcd_stb */
81
- mdelay(60);
82
- dm_i2c_reg_write(p->dev, 0x0212, 0x90); /* bl_current_ctl */
83
- dm_i2c_reg_write(p->dev, 0x0209, 0x90); /* bl_en */
84
-}
85
-
86
-static void maxim_max96752f_panel_disable(struct maxim_deserializer_panel *p)
87
-{
88
- dm_i2c_reg_write(p->dev, 0x0209, 0x80); /* bl_en */
89
- dm_i2c_reg_write(p->dev, 0x0212, 0x80); /* bl_current_ctl */
90
- dm_i2c_reg_write(p->dev, 0x0221, 0x80); /* lcd_stb */
91
- dm_i2c_reg_write(p->dev, 0x020f, 0x80); /* tp_rst */
92
- dm_i2c_reg_write(p->dev, 0x0227, 0x80); /* lcd_rst */
93
-}
94
-
95
-static const struct maxim_deserializer_panel_desc maxim_deserializer_default_panels[] = {
96
- {
97
- .deserializer = {
98
- .name = "max96752f",
99
- .addr = 0x48,
100
- .dev_id = 0x82,
101
- },
102
-
103
- .mode = {
104
- .clock = 148500,
105
- .hdisplay = 1920,
106
- .hsync_start = 1920 + 20,
107
- .hsync_end = 1920 + 20 + 20,
108
- .htotal = 1920 + 20 + 20 + 20,
109
- .vdisplay = 1080,
110
- .vsync_start = 1080 + 250,
111
- .vsync_end = 1080 + 250 + 2,
112
- .vtotal = 1080 + 250 + 2 + 8,
113
- .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
114
- },
115
-
116
- .prepare = maxim_max96752f_panel_prepare,
117
- .enable = maxim_max96752f_panel_enable,
118
- .disable = maxim_max96752f_panel_disable,
119
- .unprepare = maxim_max96752f_panel_unprepare,
120
- },
121
-};
122
-
123
-static void maxim_deserializer_panel_prepare(struct rockchip_panel *panel)
124
-{
125
- struct maxim_deserializer_panel *p = dev_get_priv(panel->dev);
126
-
127
- if (!p->desc)
128
- return;
129
-
130
- if (p->desc->prepare)
131
- p->desc->prepare(p);
132
-}
133
-
134
-static void maxim_deserializer_panel_unprepare(struct rockchip_panel *panel)
135
-{
136
- struct maxim_deserializer_panel *p = dev_get_priv(panel->dev);
137
-
138
- if (!p->desc)
139
- return;
140
-
141
- if (p->desc->unprepare)
142
- p->desc->unprepare(p);
143
-}
144
-
145
-static void maxim_deserializer_panel_enable(struct rockchip_panel *panel)
146
-{
147
- struct maxim_deserializer_panel *p = dev_get_priv(panel->dev);
148
-
149
- if (!p->desc)
150
- return;
151
-
152
- if (p->desc->enable)
153
- p->desc->enable(p);
154
-
155
- if (p->backlight)
156
- backlight_enable(p->backlight);
157
-}
158
-
159
-static void maxim_deserializer_panel_disable(struct rockchip_panel *panel)
160
-{
161
- struct maxim_deserializer_panel *p = dev_get_priv(panel->dev);
162
-
163
- if (!p->desc)
164
- return;
165
-
166
- if (p->backlight)
167
- backlight_disable(p->backlight);
168
-
169
- if (p->desc->disable)
170
- p->desc->disable(p);
171
-}
172
-
173
-static u16 maxim_deserializer_panel_get_id(struct maxim_deserializer_panel *p)
174
-{
175
- /* TODO */
176
- return 0;
177
-}
178
-
179
-static int maxim_deserializer_panel_detect(struct maxim_deserializer_panel *p)
180
-{
181
- const struct maxim_deserializer_panel_desc *desc = NULL;
182
- struct udevice *dev = p->dev;
183
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
184
- u16 id = maxim_deserializer_panel_get_id(p);
185
- unsigned int i, ret;
186
-
187
- if (id) {
188
- /* TODO */
189
- } else {
190
- u8 dev_id;
191
-
192
- for (i = 0; i < ARRAY_SIZE(maxim_deserializer_default_panels); i++) {
193
- chip->chip_addr = maxim_deserializer_default_panels[i].deserializer.addr;
194
-
195
- ret = dm_i2c_reg_read(dev, 0x000d);
196
- if (ret < 0)
197
- continue;
198
-
199
- dev_id = ret;
200
-
201
- if (maxim_deserializer_default_panels[i].deserializer.dev_id == dev_id) {
202
- desc = &maxim_deserializer_default_panels[i];
203
- break;
204
- }
205
- }
206
- }
207
-
208
- if (!desc)
209
- return -ENODEV;
210
-
211
- p->desc = desc;
212
- chip->chip_addr = desc->deserializer.addr;
213
-
214
- return 0;
215
-}
216
-
217
-static int maxim_deserializer_panel_get_mode(struct rockchip_panel *panel,
218
- struct drm_display_mode *mode)
219
-{
220
- struct maxim_deserializer_panel *p = dev_get_priv(panel->dev);
221
- int ret;
222
-
223
- ret = maxim_deserializer_panel_detect(p);
224
- if (ret)
225
- return ret;
226
-
227
- memcpy(mode, &p->desc->mode, sizeof(struct drm_display_mode));
228
- mode->vrefresh = drm_mode_vrefresh(mode);
229
-
230
- return 0;
231
-}
232
-
233
-static const struct rockchip_panel_funcs maxim_deserializer_panel_funcs = {
234
- .prepare = maxim_deserializer_panel_prepare,
235
- .unprepare = maxim_deserializer_panel_unprepare,
236
- .enable = maxim_deserializer_panel_enable,
237
- .disable = maxim_deserializer_panel_disable,
238
- .get_mode = maxim_deserializer_panel_get_mode,
239
-};
240
-
241
-static void maxim_deserializer_panel_power_on(struct maxim_deserializer_panel *p)
242
-{
243
- if (dm_gpio_is_valid(&p->enable_gpio)) {
244
- dm_gpio_set_value(&p->enable_gpio, 1);
245
- mdelay(500);
246
- }
247
-}
248
-
249
-static int maxim_deserializer_panel_probe(struct udevice *dev)
250
-{
251
- struct maxim_deserializer_panel *p = dev_get_priv(dev);
252
- struct rockchip_panel *panel;
253
- int ret;
254
-
255
- ret = i2c_set_chip_offset_len(dev, 2);
256
- if (ret)
257
- return ret;
258
-
259
- p->dev = dev;
260
-
261
- ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
262
- "backlight", &p->backlight);
263
- if (ret && ret != -ENOENT) {
264
- dev_err(dev, "%s: Cannot get backlight: %d\n", __func__, ret);
265
- return ret;
266
- }
267
-
268
- ret = gpio_request_by_name(dev, "enable-gpios", 0,
269
- &p->enable_gpio, GPIOD_IS_OUT);
270
- if (ret && ret != -ENOENT) {
271
- dev_err(dev, "%s: Cannot get enable GPIO: %d\n", __func__, ret);
272
- return ret;
273
- }
274
-
275
- maxim_deserializer_panel_power_on(p);
276
-
277
- panel = calloc(1, sizeof(*panel));
278
- if (!panel)
279
- return -ENOMEM;
280
-
281
- dev->driver_data = (ulong)panel;
282
- panel->dev = dev;
283
- panel->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
284
- panel->funcs = &maxim_deserializer_panel_funcs;
285
-
286
- return 0;
287
-}
288
-
289
-static const struct udevice_id maxim_deserializer_panel_of_match[] = {
290
- { .compatible = "maxim,deserializer-panel", },
291
- {}
292
-};
293
-
294
-U_BOOT_DRIVER(maxim_deserializer_panel) = {
295
- .name = "maxim_deserializer_panel",
296
- .id = UCLASS_PANEL,
297
- .of_match = maxim_deserializer_panel_of_match,
298
- .probe = maxim_deserializer_panel_probe,
299
- .priv_auto_alloc_size = sizeof(struct maxim_deserializer_panel),
300
-};
u-boot/drivers/video/drm/panel-maxim-max96752f.c
....@@ -0,0 +1,303 @@
1
+// SPDX-License-Identifier: GPL-2.0+
2
+/*
3
+ * Maxim MAX96752F GMSL2 Deserializer
4
+ *
5
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
6
+ */
7
+
8
+#include <config.h>
9
+#include <common.h>
10
+#include <backlight.h>
11
+#include <errno.h>
12
+#include <malloc.h>
13
+#include <video.h>
14
+
15
+#include <asm/gpio.h>
16
+#include <dm/device.h>
17
+#include <dm/read.h>
18
+#include <dm/pinctrl.h>
19
+#include <dm/uclass-id.h>
20
+#include <linux/media-bus-format.h>
21
+
22
+#include "rockchip_display.h"
23
+#include "rockchip_panel.h"
24
+
25
+struct max96752f;
26
+
27
+struct panel_desc {
28
+ const char *name;
29
+ int (*prepare)(struct max96752f *max96752f);
30
+ int (*unprepare)(struct max96752f *max96752f);
31
+ int (*enable)(struct max96752f *max96752f);
32
+ int (*disable)(struct max96752f *max96752f);
33
+ int (*backlight_enable)(struct max96752f *max96752f);
34
+ int (*backlight_disable)(struct max96752f *max96752f);
35
+};
36
+
37
+struct max96752f {
38
+ struct udevice *dev;
39
+ struct udevice *serializer;
40
+ struct udevice *backlight;
41
+
42
+ const struct panel_desc *desc;
43
+};
44
+
45
+static void max96752f_panel_prepare(struct rockchip_panel *panel)
46
+{
47
+ struct max96752f *max96752f = dev_get_priv(panel->dev);
48
+ const struct panel_desc *desc = max96752f->desc;
49
+
50
+ if (desc->prepare)
51
+ desc->prepare(max96752f);
52
+}
53
+
54
+static void max96752f_panel_unprepare(struct rockchip_panel *panel)
55
+{
56
+ struct max96752f *max96752f = dev_get_priv(panel->dev);
57
+ const struct panel_desc *desc = max96752f->desc;
58
+
59
+ if (desc->unprepare)
60
+ desc->unprepare(max96752f);
61
+}
62
+
63
+static void max96752f_panel_enable(struct rockchip_panel *panel)
64
+{
65
+ struct max96752f *max96752f = dev_get_priv(panel->dev);
66
+ const struct panel_desc *desc = max96752f->desc;
67
+
68
+ if (desc->enable)
69
+ desc->enable(max96752f);
70
+
71
+ if (max96752f->backlight)
72
+ backlight_enable(max96752f->backlight);
73
+
74
+ if (desc->backlight_enable)
75
+ desc->backlight_enable(max96752f);
76
+}
77
+
78
+static void max96752f_panel_disable(struct rockchip_panel *panel)
79
+{
80
+ struct max96752f *max96752f = dev_get_priv(panel->dev);
81
+ const struct panel_desc *desc = max96752f->desc;
82
+
83
+ if (desc->backlight_disable)
84
+ desc->backlight_disable(max96752f);
85
+
86
+ if (max96752f->backlight)
87
+ backlight_disable(max96752f->backlight);
88
+
89
+ if (desc->disable)
90
+ desc->disable(max96752f);
91
+}
92
+
93
+static const struct rockchip_panel_funcs max96752f_panel_funcs = {
94
+ .prepare = max96752f_panel_prepare,
95
+ .unprepare = max96752f_panel_unprepare,
96
+ .enable = max96752f_panel_enable,
97
+ .disable = max96752f_panel_disable,
98
+};
99
+
100
+static int max96752f_probe(struct udevice *dev)
101
+{
102
+ struct max96752f *max96752f = dev_get_priv(dev);
103
+ struct rockchip_panel *panel;
104
+ int ret;
105
+
106
+ ret = i2c_set_chip_offset_len(dev, 2);
107
+ if (ret)
108
+ return ret;
109
+
110
+ max96752f->dev = dev;
111
+ max96752f->serializer = dev->parent->parent;
112
+ max96752f->desc = (const struct panel_desc *)dev_get_driver_data(dev);
113
+
114
+ ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
115
+ "backlight", &max96752f->backlight);
116
+ if (ret && ret != -ENOENT) {
117
+ dev_err(dev, "%s: Cannot get backlight: %d\n", __func__, ret);
118
+ return ret;
119
+ }
120
+
121
+ panel = calloc(1, sizeof(*panel));
122
+ if (!panel)
123
+ return -ENOMEM;
124
+
125
+ dev->driver_data = (ulong)panel;
126
+ panel->dev = dev;
127
+ panel->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
128
+ panel->funcs = &max96752f_panel_funcs;
129
+
130
+ return 0;
131
+}
132
+
133
+#define maxim_serializer_write(max96752f, reg, val) do { \
134
+ int ret; \
135
+ ret = dm_i2c_reg_write(max96752f->serializer, \
136
+ reg, val); \
137
+ if (ret) \
138
+ return ret; \
139
+ } while (0)
140
+
141
+#define maxim_deserializer_write(max96752f, reg, val) do { \
142
+ int ret; \
143
+ ret = dm_i2c_reg_write(max96752f->dev, \
144
+ reg, val); \
145
+ if (ret) \
146
+ return ret; \
147
+ } while (0)
148
+
149
+static int boe_av156fht_l83_panel_prepare(struct max96752f *max96752f)
150
+{
151
+ maxim_deserializer_write(max96752f, 0x0002, 0x43);
152
+ maxim_deserializer_write(max96752f, 0x0140, 0x20);
153
+
154
+ maxim_deserializer_write(max96752f, 0x01ce, 0x5e); /* oldi */
155
+ maxim_deserializer_write(max96752f, 0x020c, 0x84); /* bl_pwm */
156
+ maxim_deserializer_write(max96752f, 0x0206, 0x83); /* tp_int */
157
+
158
+ maxim_deserializer_write(max96752f, 0x0215, 0x90); /* lcd_en */
159
+ mdelay(20);
160
+
161
+ return 0;
162
+}
163
+
164
+static int boe_av156fht_l83_panel_unprepare(struct max96752f *max96752f)
165
+{
166
+ maxim_deserializer_write(max96752f, 0x0215, 0x80); /* lcd_en */
167
+
168
+ return 0;
169
+}
170
+
171
+static int boe_av156fht_l83_panel_enable(struct max96752f *max96752f)
172
+{
173
+ maxim_deserializer_write(max96752f, 0x0227, 0x90); /* lcd_rst */
174
+ mdelay(20);
175
+ maxim_deserializer_write(max96752f, 0x020f, 0x90); /* tp_rst */
176
+ mdelay(100);
177
+ maxim_deserializer_write(max96752f, 0x0221, 0x90); /* lcd_stb */
178
+ mdelay(60);
179
+ maxim_deserializer_write(max96752f, 0x0212, 0x90); /* bl_current_ctl */
180
+ maxim_deserializer_write(max96752f, 0x0209, 0x90); /* bl_en */
181
+
182
+ return 0;
183
+}
184
+
185
+static int boe_av156fht_l83_panel_disable(struct max96752f *max96752f)
186
+{
187
+ maxim_deserializer_write(max96752f, 0x0209, 0x80); /* bl_en */
188
+ maxim_deserializer_write(max96752f, 0x0212, 0x80); /* bl_current_ctl */
189
+ maxim_deserializer_write(max96752f, 0x0221, 0x80); /* lcd_stb */
190
+ maxim_deserializer_write(max96752f, 0x020f, 0x80); /* tp_rst */
191
+ maxim_deserializer_write(max96752f, 0x0227, 0x80); /* lcd_rst */
192
+
193
+ return 0;
194
+}
195
+
196
+static int boe_av156fht_l83_panel_backlight_enable(struct max96752f *max96752f)
197
+{
198
+ maxim_deserializer_write(max96752f, 0x0212, 0x90); /* bl_current_ctl */
199
+ maxim_deserializer_write(max96752f, 0x0209, 0x90); /* bl_en */
200
+
201
+ return 0;
202
+}
203
+
204
+static int boe_av156fht_l83_panel_backlight_disable(struct max96752f *max96752f)
205
+{
206
+ maxim_deserializer_write(max96752f, 0x0209, 0x80); /* bl_en */
207
+ maxim_deserializer_write(max96752f, 0x0212, 0x80); /* bl_current_ctl */
208
+
209
+ return 0;
210
+}
211
+
212
+static const struct panel_desc boe_av156fht_l83 = {
213
+ .name = "boe-av156fht-l83",
214
+ .prepare = boe_av156fht_l83_panel_prepare,
215
+ .unprepare = boe_av156fht_l83_panel_unprepare,
216
+ .enable = boe_av156fht_l83_panel_enable,
217
+ .disable = boe_av156fht_l83_panel_disable,
218
+ .backlight_enable = boe_av156fht_l83_panel_backlight_enable,
219
+ .backlight_disable = boe_av156fht_l83_panel_backlight_disable,
220
+};
221
+
222
+static int hannstar_hsd123jpw3_a15_prepare(struct max96752f *max96752f)
223
+{
224
+ maxim_deserializer_write(max96752f, 0x0002, 0x43);
225
+ maxim_deserializer_write(max96752f, 0x0140, 0x20);
226
+ maxim_deserializer_write(max96752f, 0x01ce, 0x5e);
227
+
228
+ maxim_deserializer_write(max96752f, 0x0203, 0x83); /* GPIO1 <- TP_INT */
229
+ maxim_deserializer_write(max96752f, 0x0206, 0x84); /* GPIO2 -> TP_RST */
230
+ maxim_deserializer_write(max96752f, 0x0224, 0x84); /* GPIO12 -> LCD_BL_PWM */
231
+
232
+ return 0;
233
+}
234
+
235
+static int hannstar_hsd123jpw3_a15_unprepare(struct max96752f *max96752f)
236
+{
237
+ return 0;
238
+}
239
+
240
+static int hannstar_hsd123jpw3_a15_enable(struct max96752f *max96752f)
241
+{
242
+ maxim_deserializer_write(max96752f, 0x0221, 0x10); /* GPIO11 -> LCD_RESET */
243
+ mdelay(20);
244
+
245
+ return 0;
246
+}
247
+
248
+static int hannstar_hsd123jpw3_a15_disable(struct max96752f *max96752f)
249
+{
250
+ maxim_deserializer_write(max96752f, 0x0221, 0x00); /* GPIO11 -> LCD_RESET */
251
+ mdelay(20);
252
+
253
+ return 0;
254
+}
255
+
256
+static const struct panel_desc hannstar_hsd123jpw3_a15 = {
257
+ .name = "hannstar,hsd123jpw3-a15",
258
+ .prepare = hannstar_hsd123jpw3_a15_prepare,
259
+ .unprepare = hannstar_hsd123jpw3_a15_unprepare,
260
+ .enable = hannstar_hsd123jpw3_a15_enable,
261
+ .disable = hannstar_hsd123jpw3_a15_disable,
262
+};
263
+
264
+static int ogm_101fhbllm01_prepare(struct max96752f *max96752f)
265
+{
266
+ maxim_deserializer_write(max96752f, 0x01ce, 0x5e);
267
+
268
+ maxim_deserializer_write(max96752f, 0x0203, 0x84); /* GPIO1 -> BL_PWM */
269
+ maxim_deserializer_write(max96752f, 0x0206, 0x84); /* GPIO2 -> TP_RST */
270
+ maxim_deserializer_write(max96752f, 0x0209, 0x83); /* GPIO3 <- TP_INT */
271
+
272
+ maxim_deserializer_write(max96752f, 0x0001, 0x02);
273
+
274
+ return 0;
275
+}
276
+
277
+static int ogm_101fhbllm01_unprepare(struct max96752f *max96752f)
278
+{
279
+ maxim_deserializer_write(max96752f, 0x0001, 0x01);
280
+
281
+ return 0;
282
+}
283
+
284
+static const struct panel_desc ogm_101fhbllm01 = {
285
+ .name = "ogm,101fhbllm01",
286
+ .prepare = ogm_101fhbllm01_prepare,
287
+ .unprepare = ogm_101fhbllm01_unprepare,
288
+};
289
+
290
+static const struct udevice_id max96752f_of_match[] = {
291
+ { .compatible = "boe,av156fht-l83", .data = (ulong)&boe_av156fht_l83 },
292
+ { .compatible = "hannstar,hsd123jpw3-a15", .data = (ulong)&hannstar_hsd123jpw3_a15 },
293
+ { .compatible = "ogm,101fhbllm01", .data = (ulong)&ogm_101fhbllm01 },
294
+ {}
295
+};
296
+
297
+U_BOOT_DRIVER(max96752f) = {
298
+ .name = "max96752f",
299
+ .id = UCLASS_PANEL,
300
+ .of_match = max96752f_of_match,
301
+ .probe = max96752f_probe,
302
+ .priv_auto_alloc_size = sizeof(struct max96752f),
303
+};
u-boot/drivers/video/drm/panel-rohm-bu18rl82.c
....@@ -0,0 +1,349 @@
1
+// SPDX-License-Identifier: GPL-2.0+
2
+/*
3
+ * Rohm BU18RL82-based panel driver
4
+ *
5
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
6
+ */
7
+
8
+#include <config.h>
9
+#include <common.h>
10
+#include <backlight.h>
11
+#include <errno.h>
12
+#include <malloc.h>
13
+#include <video.h>
14
+
15
+#include <asm/gpio.h>
16
+#include <dm/device.h>
17
+#include <dm/read.h>
18
+#include <dm/pinctrl.h>
19
+#include <dm/uclass-id.h>
20
+#include <linux/media-bus-format.h>
21
+
22
+#include "rockchip_display.h"
23
+#include "rockchip_panel.h"
24
+
25
+struct bu18rl82;
26
+
27
+struct panel_desc {
28
+ const char *name;
29
+ int (*prepare)(struct bu18rl82 *rl82);
30
+ int (*unprepare)(struct bu18rl82 *rl82);
31
+ int (*enable)(struct bu18rl82 *rl82);
32
+ int (*disable)(struct bu18rl82 *rl82);
33
+ int (*backlight_enable)(struct bu18rl82 *rl82);
34
+ int (*backlight_disable)(struct bu18rl82 *rl82);
35
+};
36
+
37
+struct bu18rl82 {
38
+ struct udevice *dev;
39
+ struct udevice *backlight;
40
+ const struct panel_desc *desc;
41
+};
42
+
43
+static void bu18rl82_panel_prepare(struct rockchip_panel *panel)
44
+{
45
+ struct bu18rl82 *rl82 = dev_get_priv(panel->dev);
46
+ const struct panel_desc *desc = rl82->desc;
47
+
48
+ if (desc->prepare)
49
+ desc->prepare(rl82);
50
+}
51
+
52
+static void bu18rl82_panel_unprepare(struct rockchip_panel *panel)
53
+{
54
+ struct bu18rl82 *rl82 = dev_get_priv(panel->dev);
55
+ const struct panel_desc *desc = rl82->desc;
56
+
57
+ if (desc->unprepare)
58
+ desc->unprepare(rl82);
59
+}
60
+
61
+static void bu18rl82_panel_enable(struct rockchip_panel *panel)
62
+{
63
+ struct bu18rl82 *rl82 = dev_get_priv(panel->dev);
64
+ const struct panel_desc *desc = rl82->desc;
65
+
66
+ if (desc->enable)
67
+ desc->enable(rl82);
68
+
69
+ if (rl82->backlight)
70
+ backlight_enable(rl82->backlight);
71
+
72
+ if (desc->backlight_enable)
73
+ desc->backlight_enable(rl82);
74
+}
75
+
76
+static void bu18rl82_panel_disable(struct rockchip_panel *panel)
77
+{
78
+ struct bu18rl82 *rl82 = dev_get_priv(panel->dev);
79
+ const struct panel_desc *desc = rl82->desc;
80
+
81
+ if (desc->backlight_disable)
82
+ desc->backlight_disable(rl82);
83
+
84
+ if (rl82->backlight)
85
+ backlight_disable(rl82->backlight);
86
+
87
+ if (desc->disable)
88
+ desc->disable(rl82);
89
+}
90
+
91
+static const struct rockchip_panel_funcs bu18rl82_panel_funcs = {
92
+ .prepare = bu18rl82_panel_prepare,
93
+ .unprepare = bu18rl82_panel_unprepare,
94
+ .enable = bu18rl82_panel_enable,
95
+ .disable = bu18rl82_panel_disable,
96
+};
97
+
98
+static int bu18rl82_probe(struct udevice *dev)
99
+{
100
+ struct bu18rl82 *rl82 = dev_get_priv(dev);
101
+ struct rockchip_panel *panel;
102
+ int ret;
103
+
104
+ ret = i2c_set_chip_offset_len(dev, 2);
105
+ if (ret)
106
+ return ret;
107
+
108
+ rl82->dev = dev;
109
+ rl82->desc = (const struct panel_desc *)dev_get_driver_data(dev);
110
+
111
+ ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
112
+ "backlight", &rl82->backlight);
113
+ if (ret && ret != -ENOENT) {
114
+ dev_err(dev, "%s: Cannot get backlight: %d\n", __func__, ret);
115
+ return ret;
116
+ }
117
+
118
+ panel = calloc(1, sizeof(*panel));
119
+ if (!panel)
120
+ return -ENOMEM;
121
+
122
+ dev->driver_data = (ulong)panel;
123
+ panel->dev = dev;
124
+ panel->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
125
+ panel->funcs = &bu18rl82_panel_funcs;
126
+
127
+ return 0;
128
+}
129
+
130
+#define rohm_deserializer_write(rl82, reg, val) do { \
131
+ int ret; \
132
+ ret = dm_i2c_reg_write(rl82->dev, reg, val); \
133
+ if (ret) { \
134
+ dev_err(rl82->dev, \
135
+ "failed to set register 0x%04x\n", \
136
+ reg); \
137
+ return ret; \
138
+ } \
139
+ } while (0)
140
+
141
+static int csot_mg1561b01_prepare(struct bu18rl82 *rl82)
142
+{
143
+ const struct reg_sequence {
144
+ u16 reg;
145
+ u8 def;
146
+ } regs[] = {
147
+ { 0x0011, 0x03 }, { 0x0012, 0x03 },
148
+ { 0x001f, 0x02 }, { 0x0020, 0x02 },
149
+ { 0x0031, 0x41 }, { 0x0032, 0x41 },
150
+ { 0x0073, 0x80 }, { 0x0074, 0x07 },
151
+ { 0x007b, 0x38 }, { 0x007c, 0x04 },
152
+ { 0x0079, 0x0a },
153
+ { 0x0429, 0x0a }, { 0x045d, 0x01 },
154
+ { 0x0529, 0x0a }, { 0x055d, 0x01 },
155
+ { 0x060a, 0xb0 }, { 0x060b, 0xff }, { 0x060c, 0xff },
156
+ { 0x0644, 0x18 }, { 0x0645, 0x01 }, { 0x0646, 0x2d },
157
+ };
158
+ int i;
159
+
160
+ for (i = 0; i < ARRAY_SIZE(regs); i++)
161
+ rohm_deserializer_write(rl82, regs[i].reg, regs[i].def);
162
+
163
+ /* BL_PWM - GPIO0 */
164
+ rohm_deserializer_write(rl82, 0x0057, 0x00);
165
+ rohm_deserializer_write(rl82, 0x0058, 0x02);
166
+
167
+ /* TP_INT - GPIO3 */
168
+ rohm_deserializer_write(rl82, 0x0060, 0x08);
169
+ rohm_deserializer_write(rl82, 0x042e, 0x05);
170
+
171
+ /* TP_RST - GPIO4 */
172
+ rohm_deserializer_write(rl82, 0x0063, 0x00);
173
+ rohm_deserializer_write(rl82, 0x0064, 0x01);
174
+
175
+ return 0;
176
+}
177
+
178
+static int csot_mg1561b01_unprepare(struct bu18rl82 *rl82)
179
+{
180
+ /* TP_RST - GPIO4 */
181
+ rohm_deserializer_write(rl82, 0x0064, 0x00);
182
+
183
+ return 0;
184
+}
185
+
186
+static int csot_mg1561b01_enable(struct bu18rl82 *rl82)
187
+{
188
+ rohm_deserializer_write(rl82, 0x0091, 0x03);
189
+ rohm_deserializer_write(rl82, 0x0090, 0x01);
190
+
191
+ return 0;
192
+}
193
+
194
+static int csot_mg1561b01_disable(struct bu18rl82 *rl82)
195
+{
196
+ rohm_deserializer_write(rl82, 0x0090, 0x00);
197
+ rohm_deserializer_write(rl82, 0x0091, 0x00);
198
+
199
+ return 0;
200
+}
201
+
202
+static int csot_mg1561b01_backlight_enable(struct bu18rl82 *rl82)
203
+{
204
+ /* BL_EN - GPIO1 */
205
+ rohm_deserializer_write(rl82, 0x005a, 0x00);
206
+ rohm_deserializer_write(rl82, 0x005b, 0x01);
207
+
208
+ return 0;
209
+}
210
+
211
+static int csot_mg1561b01_backlight_disable(struct bu18rl82 *rl82)
212
+{
213
+ /* BL_EN - GPIO1 */
214
+ rohm_deserializer_write(rl82, 0x005b, 0x00);
215
+
216
+ return 0;
217
+}
218
+
219
+static const struct panel_desc csot_mg1561b01 = {
220
+ .name = "csot,mg1561b01",
221
+ .prepare = csot_mg1561b01_prepare,
222
+ .unprepare = csot_mg1561b01_unprepare,
223
+ .enable = csot_mg1561b01_enable,
224
+ .disable = csot_mg1561b01_disable,
225
+ .backlight_enable = csot_mg1561b01_backlight_enable,
226
+ .backlight_disable = csot_mg1561b01_backlight_disable,
227
+};
228
+
229
+static int touch_china_v123awf3_r1_prepare(struct bu18rl82 *rl82)
230
+{
231
+ const struct reg_sequence {
232
+ u16 reg;
233
+ u8 def;
234
+ } regs[] = {
235
+ { 0x0011, 0x03 }, { 0x0012, 0x03 },
236
+ { 0x001f, 0x02 }, { 0x0020, 0x02 },
237
+ { 0x0031, 0x48 }, { 0x0032, 0x48 },
238
+ { 0x0073, 0x80 }, { 0x0074, 0x07 },
239
+ { 0x007b, 0xd0 }, { 0x007c, 0x02 },
240
+ { 0x0079, 0x0a },
241
+ { 0x0429, 0x0a }, { 0x045d, 0x01 },
242
+ { 0x0529, 0x0a }, { 0x055d, 0x01 },
243
+ { 0x060a, 0xb0 }, { 0x060b, 0xff }, { 0x060c, 0xff },
244
+ { 0x0644, 0x90 }, { 0x0646, 0xd2 },
245
+ };
246
+ int i;
247
+
248
+ for (i = 0; i < ARRAY_SIZE(regs); i++)
249
+ rohm_deserializer_write(rl82, regs[i].reg, regs[i].def);
250
+
251
+ /* TP_INT - GPIO4 */
252
+ rohm_deserializer_write(rl82, 0x0063, 0x08);
253
+ rohm_deserializer_write(rl82, 0x042f, 0x06);
254
+
255
+ /* TP_RST - GPIO3 */
256
+ rohm_deserializer_write(rl82, 0x0060, 0x00);
257
+ rohm_deserializer_write(rl82, 0x0061, 0x00);
258
+
259
+ /* LCD_BIAS_EN - GPIO2 */
260
+ rohm_deserializer_write(rl82, 0x005d, 0x00);
261
+ rohm_deserializer_write(rl82, 0x005e, 0x01);
262
+ mdelay(6);
263
+
264
+ return 0;
265
+}
266
+
267
+static int touch_china_v123awf3_r1_unprepare(struct bu18rl82 *rl82)
268
+{
269
+ /* LCD_BIAS_EN - GPIO2 */
270
+ rohm_deserializer_write(rl82, 0x005e, 0x00);
271
+
272
+ return 0;
273
+}
274
+
275
+static int touch_china_v123awf3_r1_enable(struct bu18rl82 *rl82)
276
+{
277
+ rohm_deserializer_write(rl82, 0x0091, 0x03);
278
+ rohm_deserializer_write(rl82, 0x0090, 0x01);
279
+
280
+ /* RSEX - GPIO5 */
281
+ rohm_deserializer_write(rl82, 0x0066, 0x00);
282
+ rohm_deserializer_write(rl82, 0x0067, 0x01);
283
+ /* TP_RST - GPIO3 */
284
+ rohm_deserializer_write(rl82, 0x0060, 0x00);
285
+ rohm_deserializer_write(rl82, 0x0061, 0x01);
286
+ mdelay(20);
287
+ /* LCD_PON - GPIO1 */
288
+ rohm_deserializer_write(rl82, 0x005a, 0x00);
289
+ rohm_deserializer_write(rl82, 0x005b, 0x01);
290
+
291
+ return 0;
292
+}
293
+
294
+static int touch_china_v123awf3_r1_disable(struct bu18rl82 *rl82)
295
+{
296
+ rohm_deserializer_write(rl82, 0x0090, 0x00);
297
+ rohm_deserializer_write(rl82, 0x0091, 0x00);
298
+
299
+ /* LCD_PON - GPIO1 */
300
+ rohm_deserializer_write(rl82, 0x005b, 0x00);
301
+ mdelay(100);
302
+ /* TP_RST - GPIO3 */
303
+ rohm_deserializer_write(rl82, 0x0061, 0x00);
304
+ /* RSEX - GPIO5 */
305
+ rohm_deserializer_write(rl82, 0x0067, 0x00);
306
+
307
+ return 0;
308
+}
309
+
310
+static int touch_china_v123awf3_r1_backlight_enable(struct bu18rl82 *rl82)
311
+{
312
+ /* BL_PWM - GPIO0 */
313
+ rohm_deserializer_write(rl82, 0x0057, 0x00);
314
+ rohm_deserializer_write(rl82, 0x0058, 0x02);
315
+
316
+ return 0;
317
+}
318
+
319
+static int touch_china_v123awf3_r1_backlight_disable(struct bu18rl82 *rl82)
320
+{
321
+ /* BL_PWM - GPIO0 */
322
+ rohm_deserializer_write(rl82, 0x0058, 0x00);
323
+
324
+ return 0;
325
+}
326
+
327
+static const struct panel_desc touch_china_v123awf3_r1 = {
328
+ .name = "touch-china,v123awf3-r1",
329
+ .prepare = touch_china_v123awf3_r1_prepare,
330
+ .unprepare = touch_china_v123awf3_r1_unprepare,
331
+ .enable = touch_china_v123awf3_r1_enable,
332
+ .disable = touch_china_v123awf3_r1_disable,
333
+ .backlight_enable = touch_china_v123awf3_r1_backlight_enable,
334
+ .backlight_disable = touch_china_v123awf3_r1_backlight_disable,
335
+};
336
+
337
+static const struct udevice_id bu18rl82_of_match[] = {
338
+ { .compatible = "csot,mg1561b01", .data = (ulong)&csot_mg1561b01 },
339
+ { .compatible = "touch-china,v123awf3-r1", .data = (ulong)&touch_china_v123awf3_r1 },
340
+ {}
341
+};
342
+
343
+U_BOOT_DRIVER(panel_rohm_bu18rl82) = {
344
+ .name = "panel-rohm-bu18rl82",
345
+ .id = UCLASS_PANEL,
346
+ .of_match = bu18rl82_of_match,
347
+ .probe = bu18rl82_probe,
348
+ .priv_auto_alloc_size = sizeof(struct bu18rl82),
349
+};
u-boot/drivers/video/drm/phy-rockchip-samsung-hdptx-hdmi.c
....@@ -1278,9 +1278,9 @@
12781278 hdptx_write(hdptx, CMN_REG0043, 0x00);
12791279 hdptx_write(hdptx, CMN_REG0044, 0x46);
12801280 hdptx_write(hdptx, CMN_REG0045, 0x24);
1281
- hdptx_write(hdptx, CMN_REG0046, 0xff);
1281
+ hdptx_write(hdptx, CMN_REG0046, 0xdd);
12821282 hdptx_write(hdptx, CMN_REG0047, 0x00);
1283
- hdptx_write(hdptx, CMN_REG0048, 0x44);
1283
+ hdptx_write(hdptx, CMN_REG0048, 0x11);
12841284 hdptx_write(hdptx, CMN_REG0049, 0xfa);
12851285 hdptx_write(hdptx, CMN_REG004A, 0x08);
12861286 hdptx_write(hdptx, CMN_REG004B, 0x00);
....@@ -1457,6 +1457,13 @@
14571457 hdptx_write(hdptx, LANE_REG0616, 0x02);
14581458 hdptx_write(hdptx, LANE_REG061B, 0x01);
14591459 hdptx_write(hdptx, LANE_REG061E, 0x08);
1460
+
1461
+ /* fix Inter-Pair Skew exceed the limits */
1462
+ hdptx_write(hdptx, LANE_REG031E, 0x02);
1463
+ hdptx_write(hdptx, LANE_REG041E, 0x02);
1464
+ hdptx_write(hdptx, LANE_REG051E, 0x02);
1465
+ hdptx_write(hdptx, LANE_REG061E, 0x0a);
1466
+
14601467 hdptx_write(hdptx, LANE_REG061F, 0x15);
14611468 hdptx_write(hdptx, LANE_REG0620, 0xa0);
14621469
....@@ -1705,6 +1712,33 @@
17051712 hdptx_write(hdptx, LANE_REG061F, 0x15);
17061713 hdptx_write(hdptx, LANE_REG0620, 0xa0);
17071714
1715
+ hdptx_write(hdptx, LANE_REG031E, 0x02);
1716
+ hdptx_write(hdptx, LANE_REG041E, 0x02);
1717
+ hdptx_write(hdptx, LANE_REG051E, 0x02);
1718
+ hdptx_write(hdptx, LANE_REG061E, 0x02);
1719
+
1720
+ hdptx_write(hdptx, LANE_REG0303, 0x2f);
1721
+ hdptx_write(hdptx, LANE_REG0403, 0x2f);
1722
+ hdptx_write(hdptx, LANE_REG0503, 0x2f);
1723
+ hdptx_write(hdptx, LANE_REG0603, 0x2f);
1724
+ hdptx_write(hdptx, LANE_REG0305, 0x03);
1725
+ hdptx_write(hdptx, LANE_REG0405, 0x03);
1726
+ hdptx_write(hdptx, LANE_REG0505, 0x03);
1727
+ hdptx_write(hdptx, LANE_REG0605, 0x03);
1728
+ hdptx_write(hdptx, LANE_REG0306, 0xfc);
1729
+ hdptx_write(hdptx, LANE_REG0406, 0xfc);
1730
+ hdptx_write(hdptx, LANE_REG0506, 0xfc);
1731
+ hdptx_write(hdptx, LANE_REG0606, 0xfc);
1732
+
1733
+ hdptx_write(hdptx, LANE_REG0305, 0x4f);
1734
+ hdptx_write(hdptx, LANE_REG0405, 0x4f);
1735
+ hdptx_write(hdptx, LANE_REG0505, 0x4f);
1736
+ hdptx_write(hdptx, LANE_REG0605, 0x4f);
1737
+ hdptx_write(hdptx, LANE_REG0304, 0x14);
1738
+ hdptx_write(hdptx, LANE_REG0404, 0x14);
1739
+ hdptx_write(hdptx, LANE_REG0504, 0x14);
1740
+ hdptx_write(hdptx, LANE_REG0604, 0x14);
1741
+
17081742 return hdptx_post_enable_lane(hdptx);
17091743 }
17101744
....@@ -1774,6 +1808,33 @@
17741808 hdptx_write(hdptx, LANE_REG061B, 0x01);
17751809 hdptx_write(hdptx, LANE_REG061F, 0x15);
17761810 hdptx_write(hdptx, LANE_REG0620, 0xa0);
1811
+
1812
+ hdptx_write(hdptx, LANE_REG031E, 0x02);
1813
+ hdptx_write(hdptx, LANE_REG041E, 0x02);
1814
+ hdptx_write(hdptx, LANE_REG051E, 0x02);
1815
+ hdptx_write(hdptx, LANE_REG061E, 0x02);
1816
+
1817
+ hdptx_write(hdptx, LANE_REG0303, 0x2f);
1818
+ hdptx_write(hdptx, LANE_REG0403, 0x2f);
1819
+ hdptx_write(hdptx, LANE_REG0503, 0x2f);
1820
+ hdptx_write(hdptx, LANE_REG0603, 0x2f);
1821
+ hdptx_write(hdptx, LANE_REG0305, 0x03);
1822
+ hdptx_write(hdptx, LANE_REG0405, 0x03);
1823
+ hdptx_write(hdptx, LANE_REG0505, 0x03);
1824
+ hdptx_write(hdptx, LANE_REG0605, 0x03);
1825
+ hdptx_write(hdptx, LANE_REG0306, 0xfc);
1826
+ hdptx_write(hdptx, LANE_REG0406, 0xfc);
1827
+ hdptx_write(hdptx, LANE_REG0506, 0xfc);
1828
+ hdptx_write(hdptx, LANE_REG0606, 0xfc);
1829
+
1830
+ hdptx_write(hdptx, LANE_REG0305, 0x4f);
1831
+ hdptx_write(hdptx, LANE_REG0405, 0x4f);
1832
+ hdptx_write(hdptx, LANE_REG0505, 0x4f);
1833
+ hdptx_write(hdptx, LANE_REG0605, 0x4f);
1834
+ hdptx_write(hdptx, LANE_REG0304, 0x14);
1835
+ hdptx_write(hdptx, LANE_REG0404, 0x14);
1836
+ hdptx_write(hdptx, LANE_REG0504, 0x14);
1837
+ hdptx_write(hdptx, LANE_REG0604, 0x14);
17771838
17781839 return hdptx_post_enable_lane(hdptx);
17791840 }
....@@ -1951,12 +2012,14 @@
19512012
19522013 subnode = ofnode_find_subnode(parent->node, "clk-port");
19532014 if (!ofnode_valid(subnode)) {
1954
- printf("%s: no subnode for %s", __func__, parent->name);
2015
+ free(str);
2016
+ printf("%s: no subnode for %s\n", __func__, parent->name);
19552017 return -ENXIO;
19562018 }
19572019
19582020 ret = device_bind_driver_to_node(parent, "clk_hdptx", str, subnode, &child);
19592021 if (ret) {
2022
+ free(str);
19602023 printf("%s: clk-port cannot bind its driver\n", __func__);
19612024 return ret;
19622025 }
....@@ -2019,18 +2082,6 @@
20192082 new_rate = rate;
20202083 priv->rate = rate;
20212084 }
2022
- }
2023
- } else {
2024
- if (!hdptx_ropll_cmn_config(hdptx, rate)) {
2025
- new_rate = rate;
2026
- priv->rate = rate;
2027
- }
2028
- }
2029
-
2030
- if (rate > (HDMI20_MAX_RATE / 100)) {
2031
- if (!hdptx_lcpll_cmn_config(hdptx, rate)) {
2032
- new_rate = rate;
2033
- priv->rate = rate;
20342085 }
20352086 } else {
20362087 if (!hdptx_ropll_cmn_config(hdptx, rate)) {
u-boot/drivers/video/drm/rockchip-inno-hdmi-phy.c
....@@ -3,6 +3,7 @@
33 * (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd
44 */
55
6
+#include <clk-uclass.h>
67 #include <config.h>
78 #include <common.h>
89 #include <errno.h>
....@@ -11,7 +12,9 @@
1112 #include <fdtdec.h>
1213 #include <fdt_support.h>
1314 #include <asm/unaligned.h>
15
+#include <asm/arch/clock.h>
1416 #include <dm/device.h>
17
+#include <dm/lists.h>
1518 #include <dm/read.h>
1619 #include <asm/io.h>
1720 #include <linux/list.h>
....@@ -20,6 +23,7 @@
2023
2124 #include "rockchip_display.h"
2225 #include "rockchip_crtc.h"
26
+#include "rockchip_connector.h"
2327 #include "rockchip_phy.h"
2428
2529 #define INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT 1000
....@@ -145,7 +149,8 @@
145149
146150 enum inno_hdmi_phy_type {
147151 INNO_HDMI_PHY_RK3228,
148
- INNO_HDMI_PHY_RK3328
152
+ INNO_HDMI_PHY_RK3328,
153
+ INNO_HDMI_PHY_RK3528
149154 };
150155
151156 struct inno_hdmi_phy_drv_data;
....@@ -214,6 +219,14 @@
214219 const void *data;
215220 };
216221
222
+struct clk_inno_hdmi {
223
+ struct udevice *dev;
224
+ ulong rate;
225
+};
226
+
227
+/* global variables are used to pass reource from phy drivers to clk driver */
228
+static struct inno_hdmi_phy *g_inno;
229
+
217230 static const struct pre_pll_config pre_pll_cfg_table[] = {
218231 { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
219232 { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
....@@ -249,9 +262,13 @@
249262 {33750000, 1, 10, 2, 4},
250263 {74250000, 1, 40, 8, 1},
251264 {74250000, 18, 80, 8, 2},
265
+ {74250000, 1, 20, 4, 8},
252266 {148500000, 2, 40, 4, 3},
267
+ {148500000, 1, 10, 2, 8},
253268 {297000000, 4, 40, 2, 3},
269
+ {297000000, 2, 20, 2, 8},
254270 {594000000, 8, 40, 1, 3},
271
+ {594000000, 4, 20, 1, 8},
255272 { ~0UL, 0, 0, 0, 0}
256273 };
257274
....@@ -292,6 +309,30 @@
292309 594000000, {
293310 0x10, 0x1a, 0x1a, 0x1a, 0x07, 0x15, 0x08, 0x08, 0x08,
294311 0x00, 0xac, 0xcc, 0xcc, 0xcc,
312
+ },
313
+ }, {
314
+ ~0UL, {
315
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
316
+ 0x00, 0x00, 0x00, 0x00, 0x00,
317
+ },
318
+ }
319
+};
320
+
321
+static const struct phy_config rk3528_phy_cfg[] = {
322
+ /* tmdsclk bias-clk bias-data voltage-clk voltage-data pre-emphasis-data */
323
+ { 165000000, {
324
+ 0x03, 0x04, 0x0c, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00,
325
+ 0x00, 0x00, 0x00, 0x00, 0x00,
326
+ },
327
+ }, {
328
+ 340000000, {
329
+ 0x03, 0x04, 0x0c, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00,
330
+ 0x00, 0x00, 0x00, 0x00, 0x00,
331
+ },
332
+ }, {
333
+ 594000000, {
334
+ 0x02, 0x08, 0x0d, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
335
+ 0x00, 0x00, 0x00, 0x00, 0x00,
295336 },
296337 }, {
297338 ~0UL, {
....@@ -398,7 +439,11 @@
398439
399440 static int inno_hdmi_phy_power_on(struct rockchip_phy *phy)
400441 {
442
+#ifdef CONFIG_SPL_BUILD
443
+ struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;
444
+#else
401445 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);
446
+#endif
402447 const struct post_pll_config *cfg = post_pll_cfg_table;
403448 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;
404449 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock);
....@@ -420,6 +465,8 @@
420465 else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 &&
421466 tmdsclock <= 33750000)
422467 chipversion = 4;
468
+ else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3528)
469
+ chipversion = 8;
423470
424471 printf("tmdsclock = %d; chipversion = %d\n", tmdsclock, chipversion);
425472
....@@ -444,7 +491,11 @@
444491
445492 static int inno_hdmi_phy_power_off(struct rockchip_phy *phy)
446493 {
494
+#ifdef CONFIG_SPL_BUILD
495
+ struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;
496
+#else
447497 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);
498
+#endif
448499
449500 if (inno->plat_data->ops->power_off)
450501 inno->plat_data->ops->power_off(inno);
....@@ -858,6 +909,229 @@
858909 return rate;
859910 }
860911
912
+static int
913
+inno_hdmi_phy_rk3528_power_on(struct inno_hdmi_phy *inno,
914
+ const struct post_pll_config *cfg,
915
+ const struct phy_config *phy_cfg)
916
+{
917
+ u32 val;
918
+ u64 temp;
919
+ u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock);
920
+
921
+ /* Power off post PLL */
922
+ inno_update_bits(inno, 0xaa, 1, 0);
923
+
924
+ val = cfg->prediv;
925
+ inno_write(inno, 0xab, val);
926
+
927
+ if (cfg->postdiv == 1) {
928
+ inno_write(inno, 0xad, 0x8);
929
+ inno_write(inno, 0xaa, 2);
930
+ } else {
931
+ val = (cfg->postdiv / 2) - 1;
932
+ inno_write(inno, 0xad, val);
933
+ inno_write(inno, 0xaa, 0x0e);
934
+ }
935
+
936
+ val = cfg->fbdiv & 0xff;
937
+ inno_write(inno, 0xac, val);
938
+ val = (cfg->fbdiv >> 8) & BIT(0);
939
+ inno_update_bits(inno, 0xad, BIT(4), val);
940
+
941
+ /* current bias clk/data 2 */
942
+ val = phy_cfg->regs[0] << 4 | phy_cfg->regs[1];
943
+ inno_write(inno, 0xbf, val);
944
+
945
+ /* current bias data 1/0 */
946
+ val = phy_cfg->regs[1] << 4 | phy_cfg->regs[1];
947
+ inno_write(inno, 0xc0, val);
948
+
949
+ /* output voltage */
950
+ inno_write(inno, 0xb5, phy_cfg->regs[2]);
951
+ inno_write(inno, 0xb6, phy_cfg->regs[3]);
952
+ inno_write(inno, 0xb7, phy_cfg->regs[3]);
953
+ inno_write(inno, 0xb8, phy_cfg->regs[3]);
954
+
955
+ /* pre-emphasis */
956
+ inno_write(inno, 0xbb, phy_cfg->regs[4]);
957
+ inno_write(inno, 0xbc, phy_cfg->regs[4]);
958
+ inno_write(inno, 0xbd, phy_cfg->regs[4]);
959
+
960
+ /* enable LDO */
961
+ inno_write(inno, 0xb4, 0x7);
962
+
963
+ /* enable serializer */
964
+ inno_write(inno, 0xbe, 0x70);
965
+
966
+ inno_write(inno, 0xb2, 0x0f);
967
+
968
+ for (val = 0; val < 5; val++) {
969
+ if (inno_read(inno, 0xaf) & 1)
970
+ break;
971
+ udelay(1000);
972
+ }
973
+ if (!(inno_read(inno, 0xaf) & 1)) {
974
+ dev_err(inno->dev, "HDMI PHY Post PLL unlock\n");
975
+ return -ETIMEDOUT;
976
+ }
977
+
978
+ /* set termination resistance */
979
+ if (phy_cfg->tmdsclock > 340000000) {
980
+ inno_write(inno, 0xc7, 0x76);
981
+ inno_write(inno, 0xc5, 0x83);
982
+ inno_write(inno, 0xc8, 0x00);
983
+ inno_write(inno, 0xc9, 0x2f);
984
+ inno_write(inno, 0xca, 0x2f);
985
+ inno_write(inno, 0xcb, 0x2f);
986
+ } else {
987
+ inno_write(inno, 0xc7, 0x76);
988
+ inno_write(inno, 0xc5, 0x83);
989
+ inno_write(inno, 0xc8, 0x00);
990
+ inno_write(inno, 0xc9, 0x0f);
991
+ inno_write(inno, 0xca, 0x0f);
992
+ inno_write(inno, 0xcb, 0x0f);
993
+ }
994
+
995
+
996
+ /* set TMDS sync detection counter length */
997
+ temp = 47520000000UL / tmdsclock;
998
+ inno_write(inno, 0xd8, (temp >> 8) & 0xff);
999
+ inno_write(inno, 0xd9, temp & 0xff);
1000
+
1001
+ if (phy_cfg->tmdsclock > 340000000)
1002
+ mdelay(100);
1003
+ /* set pdata_en to 0/1 */
1004
+ inno_update_bits(inno, 0x02, 1, 0);
1005
+ inno_update_bits(inno, 0x02, 1, 1);
1006
+
1007
+ /* Enable PHY IRQ */
1008
+ inno_write(inno, 0x05, 0x22);
1009
+ inno_write(inno, 0x07, 0x22);
1010
+ inno_write(inno, 0xcc, 0x0f);
1011
+
1012
+ return 0;
1013
+}
1014
+
1015
+static void inno_hdmi_phy_rk3528_power_off(struct inno_hdmi_phy *inno)
1016
+{
1017
+ /* Power off driver */
1018
+ inno_write(inno, 0xb2, 0);
1019
+ /* Power off band gap */
1020
+ inno_update_bits(inno, 0xb0, 4, 0);
1021
+ /* Power off post pll */
1022
+ inno_update_bits(inno, 0xaa, 1, 1);
1023
+
1024
+ /* Disable PHY IRQ */
1025
+ inno_write(inno, 0x05, 0);
1026
+ inno_write(inno, 0x07, 0);
1027
+}
1028
+
1029
+static void inno_hdmi_phy_rk3528_init(struct inno_hdmi_phy *inno)
1030
+{
1031
+ /*
1032
+ * Use phy internal register control
1033
+ * rxsense/poweron/pllpd/pdataen signal.
1034
+ */
1035
+ inno_write(inno, 0x02, 0x81);
1036
+}
1037
+
1038
+static int
1039
+inno_hdmi_phy_rk3528_pre_pll_update(struct inno_hdmi_phy *inno,
1040
+ const struct pre_pll_config *cfg)
1041
+{
1042
+ u32 val;
1043
+
1044
+ inno_update_bits(inno, 0xb0, 4, 4);
1045
+ inno_write(inno, 0xcc, 0x0f);
1046
+
1047
+ /* Power on PLL */
1048
+ inno_update_bits(inno, 0xa0, 1, 0);
1049
+ /* Configure pre-pll */
1050
+ inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1);
1051
+ inno_write(inno, 0xa1, cfg->prediv);
1052
+ if (cfg->fracdiv)
1053
+ val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0;
1054
+ else
1055
+ val = ((cfg->fbdiv >> 8) & 0x0f) | 0xf0;
1056
+ inno_write(inno, 0xa2, val);
1057
+ inno_write(inno, 0xa3, cfg->fbdiv & 0xff);
1058
+ val = (cfg->pclk_div_a & 0x1f) |
1059
+ ((cfg->pclk_div_b & 3) << 5);
1060
+ inno_write(inno, 0xa5, val);
1061
+ val = (cfg->pclk_div_d & 0x1f) |
1062
+ ((cfg->pclk_div_c & 3) << 5);
1063
+ inno_write(inno, 0xa6, val);
1064
+ val = ((cfg->tmds_div_a & 3) << 4) |
1065
+ ((cfg->tmds_div_b & 3) << 2) |
1066
+ (cfg->tmds_div_c & 3);
1067
+ inno_write(inno, 0xa4, val);
1068
+
1069
+ if (cfg->fracdiv) {
1070
+ val = cfg->fracdiv & 0xff;
1071
+ inno_write(inno, 0xd3, val);
1072
+ val = (cfg->fracdiv >> 8) & 0xff;
1073
+ inno_write(inno, 0xd2, val);
1074
+ val = (cfg->fracdiv >> 16) & 0xff;
1075
+ inno_write(inno, 0xd1, val);
1076
+ } else {
1077
+ inno_write(inno, 0xd3, 0);
1078
+ inno_write(inno, 0xd2, 0);
1079
+ inno_write(inno, 0xd1, 0);
1080
+ }
1081
+
1082
+ /* Wait for PLL lock */
1083
+ for (val = 0; val < 5; val++) {
1084
+ if (inno_read(inno, 0xa9) & 1)
1085
+ break;
1086
+ udelay(1000);
1087
+ }
1088
+ if (val == 5) {
1089
+ dev_err(inno->dev, "Pre-PLL unlock\n");
1090
+ return -ETIMEDOUT;
1091
+ }
1092
+
1093
+ return 0;
1094
+}
1095
+
1096
+static unsigned long
1097
+inno_hdmi_rk3528_phy_pll_recalc_rate(struct inno_hdmi_phy *inno,
1098
+ unsigned long parent_rate)
1099
+{
1100
+ unsigned long frac;
1101
+ u8 nd, no_a, no_b, no_d;
1102
+ u16 nf;
1103
+ u64 vco = parent_rate;
1104
+
1105
+ nd = inno_read(inno, 0xa1) & 0x3f;
1106
+ nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3);
1107
+ vco *= nf;
1108
+ if ((inno_read(inno, 0xa2) & 0x30) == 0) {
1109
+ frac = inno_read(inno, 0xd3) |
1110
+ (inno_read(inno, 0xd2) << 8) |
1111
+ (inno_read(inno, 0xd1) << 16);
1112
+ vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24));
1113
+ }
1114
+ if (inno_read(inno, 0xa0) & 2) {
1115
+ do_div(vco, nd * 5);
1116
+ } else {
1117
+ no_a = inno_read(inno, 0xa5) & 0x1f;
1118
+ no_b = ((inno_read(inno, 0xa5) >> 5) & 7) + 2;
1119
+ no_d = inno_read(inno, 0xa6) & 0x1f;
1120
+ if (no_a == 1)
1121
+ do_div(vco, nd * no_b * no_d * 2);
1122
+ else
1123
+ do_div(vco, nd * no_a * no_d * 2);
1124
+ }
1125
+
1126
+ frac = vco;
1127
+ inno->pixclock = DIV_ROUND_CLOSEST(frac, 1000) * 1000;
1128
+
1129
+ dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
1130
+
1131
+ return frac;
1132
+}
1133
+
1134
+#ifndef CONFIG_SPL_BUILD
8611135 #define PHY_TAB_LEN 60
8621136
8631137 static
....@@ -889,6 +1163,7 @@
8891163
8901164 return 0;
8911165 }
1166
+#endif
8921167
8931168 static const struct inno_hdmi_phy_ops rk3228_hdmi_phy_ops = {
8941169 .init = inno_hdmi_phy_rk3228_init,
....@@ -905,6 +1180,14 @@
9051180 .recalc_rate = inno_hdmi_3328_phy_pll_recalc_rate,
9061181 };
9071182
1183
+static const struct inno_hdmi_phy_ops rk3528_hdmi_phy_ops = {
1184
+ .init = inno_hdmi_phy_rk3528_init,
1185
+ .power_on = inno_hdmi_phy_rk3528_power_on,
1186
+ .power_off = inno_hdmi_phy_rk3528_power_off,
1187
+ .pre_pll_update = inno_hdmi_phy_rk3528_pre_pll_update,
1188
+ .recalc_rate = inno_hdmi_rk3528_phy_pll_recalc_rate,
1189
+};
1190
+
9081191 static const struct inno_hdmi_phy_drv_data rk3228_hdmi_phy_drv_data = {
9091192 .dev_type = INNO_HDMI_PHY_RK3228,
9101193 .ops = &rk3228_hdmi_phy_ops,
....@@ -917,6 +1200,12 @@
9171200 .phy_cfg_table = rk3328_phy_cfg,
9181201 };
9191202
1203
+static const struct inno_hdmi_phy_drv_data rk3528_hdmi_phy_drv_data = {
1204
+ .dev_type = INNO_HDMI_PHY_RK3528,
1205
+ .ops = &rk3528_hdmi_phy_ops,
1206
+ .phy_cfg_table = rk3528_phy_cfg,
1207
+};
1208
+
9201209 static const struct rockchip_inno_data inno_hdmi_phy_of_match[] = {
9211210 { .compatible = "rockchip,rk3228-hdmi-phy",
9221211 .data = &rk3228_hdmi_phy_drv_data
....@@ -924,26 +1213,41 @@
9241213 { .compatible = "rockchip,rk3328-hdmi-phy",
9251214 .data = &rk3328_hdmi_phy_drv_data
9261215 },
1216
+ { .compatible = "rockchip,rk3528-hdmi-phy",
1217
+ .data = &rk3528_hdmi_phy_drv_data
1218
+ },
9271219 {}
9281220 };
9291221
9301222 static int inno_hdmi_phy_init(struct rockchip_phy *phy)
9311223 {
1224
+#ifdef CONFIG_SPL_BUILD
1225
+ struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;
1226
+#else
9321227 struct udevice *dev = phy->dev;
9331228 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);
934
- int i, val, phy_table_size, ret;
935
- const char *name;
1229
+ int val, phy_table_size, ret;
9361230 u32 *phy_config;
1231
+#endif
1232
+ int i;
1233
+ const char *name;
9371234
938
- inno->node = dev->node;
939
-
1235
+#ifdef CONFIG_SPL_BUILD
1236
+ inno->regs = (void *)RK3528_HDMIPHY_BASE;
1237
+#else
9401238 inno->regs = dev_read_addr_ptr(dev);
1239
+ inno->node = dev->node;
1240
+#endif
9411241 if (!inno->regs) {
9421242 printf("%s: failed to get phy address\n", __func__);
9431243 return -ENOMEM;
9441244 }
9451245
1246
+#ifdef CONFIG_SPL_BUILD
1247
+ name = "rockchip,rk3528-hdmi-phy";
1248
+#else
9461249 name = dev_read_string(dev, "compatible");
1250
+#endif
9471251 for (i = 0; i < ARRAY_SIZE(inno_hdmi_phy_of_match); i++) {
9481252 if (!strcmp(name, inno_hdmi_phy_of_match[i].compatible)) {
9491253 inno->plat_data = inno_hdmi_phy_of_match[i].data;
....@@ -951,6 +1255,7 @@
9511255 }
9521256 }
9531257
1258
+#ifndef CONFIG_SPL_BUILD
9541259 dev_read_prop(dev, "rockchip,phy-table", &val);
9551260
9561261 if (val >= 0) {
....@@ -986,6 +1291,7 @@
9861291 } else {
9871292 printf("use default hdmi phy table\n");
9881293 }
1294
+#endif
9891295
9901296 if (i >= ARRAY_SIZE(inno_hdmi_phy_of_match))
9911297 return 0;
....@@ -1002,8 +1308,16 @@
10021308 static unsigned long inno_hdmi_phy_set_pll(struct rockchip_phy *phy,
10031309 unsigned long rate)
10041310 {
1311
+#ifdef CONFIG_SPL_BUILD
1312
+ struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;
1313
+#else
10051314 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);
1315
+#endif
10061316
1317
+#ifdef CONFIG_SPL_BUILD
1318
+ if (!inno)
1319
+ inno = g_inno;
1320
+#endif
10071321 inno_hdmi_phy_clk_prepare(inno);
10081322 inno_hdmi_phy_clk_is_prepared(inno);
10091323 inno_hdmi_phy_clk_set_rate(inno, rate);
....@@ -1013,7 +1327,11 @@
10131327 static int
10141328 inno_hdmi_phy_set_bus_width(struct rockchip_phy *phy, u32 bus_width)
10151329 {
1330
+#ifdef CONFIG_SPL_BUILD
1331
+ struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;
1332
+#else
10161333 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);
1334
+#endif
10171335
10181336 inno->bus_width = bus_width;
10191337
....@@ -1023,7 +1341,11 @@
10231341 static long
10241342 inno_hdmi_phy_clk_round_rate(struct rockchip_phy *phy, unsigned long rate)
10251343 {
1344
+#ifdef CONFIG_SPL_BUILD
1345
+ struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;
1346
+#else
10261347 struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);
1348
+#endif
10271349 int i;
10281350 const struct pre_pll_config *cfg = pre_pll_cfg_table;
10291351 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
....@@ -1082,9 +1404,26 @@
10821404 .compatible = "rockchip,rk3228-hdmi-phy",
10831405 .data = (ulong)&inno_hdmi_phy_driver_data,
10841406 },
1407
+ {
1408
+ .compatible = "rockchip,rk3528-hdmi-phy",
1409
+ .data = (ulong)&inno_hdmi_phy_driver_data,
1410
+ },
10851411 {}
10861412 };
10871413
1414
+#ifdef CONFIG_SPL_BUILD
1415
+int inno_spl_hdmi_phy_probe(struct display_state *state)
1416
+{
1417
+ struct inno_hdmi_phy *inno = malloc(sizeof(struct inno_hdmi_phy));
1418
+
1419
+ memset(inno, 0, sizeof(*inno));
1420
+ g_inno = inno;
1421
+
1422
+ state->conn_state.connector->phy = &inno_hdmi_phy_driver_data;
1423
+ state->conn_state.connector->phy->data = (void *)inno;
1424
+ return 0;
1425
+}
1426
+#else
10881427 static int inno_hdmi_phy_probe(struct udevice *dev)
10891428 {
10901429 struct inno_hdmi_phy *inno = dev_get_priv(dev);
....@@ -1094,6 +1433,32 @@
10941433 inno->dev = dev;
10951434 phy->dev = dev;
10961435
1436
+ g_inno = inno;
1437
+ dev->driver_data = (ulong)&inno_hdmi_phy_driver_data;
1438
+ phy = &inno_hdmi_phy_driver_data;
1439
+
1440
+ return 0;
1441
+}
1442
+#endif
1443
+
1444
+static int rockchip_inno_phy_hdmi_bind(struct udevice *parent)
1445
+{
1446
+ struct udevice *child;
1447
+ ofnode subnode;
1448
+ int ret;
1449
+
1450
+ subnode = ofnode_find_subnode(parent->node, "clk-port");
1451
+ if (!ofnode_valid(subnode)) {
1452
+ printf("%s: no subnode for %s\n", __func__, parent->name);
1453
+ return -ENXIO;
1454
+ }
1455
+
1456
+ ret = device_bind_driver_to_node(parent, "clk_inno_hdmi", "inno_hdmi_pll_clk", subnode, &child);
1457
+ if (ret) {
1458
+ printf("%s: clk-port cannot bind its driver\n", __func__);
1459
+ return ret;
1460
+ }
1461
+
10971462 return 0;
10981463 }
10991464
....@@ -1101,6 +1466,57 @@
11011466 .name = "inno_hdmi_phy",
11021467 .id = UCLASS_PHY,
11031468 .of_match = inno_hdmi_phy_ids,
1469
+#ifndef CONFIG_SPL_BUILD
11041470 .probe = inno_hdmi_phy_probe,
1471
+#endif
1472
+ .bind = rockchip_inno_phy_hdmi_bind,
11051473 .priv_auto_alloc_size = sizeof(struct inno_hdmi_phy),
11061474 };
1475
+
1476
+
1477
+static ulong inno_hdmi_clk_get_rate(struct clk *clk)
1478
+{
1479
+ struct clk_inno_hdmi *priv = dev_get_priv(clk->dev);
1480
+
1481
+ return priv->rate;
1482
+}
1483
+
1484
+static ulong inno_hdmi_clk_set_rate(struct clk *clk, ulong rate)
1485
+{
1486
+ struct clk_inno_hdmi *priv = dev_get_priv(clk->dev);
1487
+ int ret;
1488
+
1489
+ inno_hdmi_phy_clk_prepare(g_inno);
1490
+ inno_hdmi_phy_clk_is_prepared(g_inno);
1491
+ ret = inno_hdmi_phy_clk_set_rate(g_inno, rate);
1492
+ if (ret < 0) {
1493
+ printf("inno hdmi set rate failed ret:%d\n", ret);
1494
+ return ret;
1495
+ }
1496
+
1497
+ priv->rate = g_inno->pixclock;
1498
+
1499
+ return priv->rate;
1500
+}
1501
+
1502
+static const struct clk_ops inno_hdmi_clk_ops = {
1503
+ .get_rate = inno_hdmi_clk_get_rate,
1504
+ .set_rate = inno_hdmi_clk_set_rate,
1505
+};
1506
+
1507
+static int inno_hdmi_clk_probe(struct udevice *dev)
1508
+{
1509
+ return 0;
1510
+}
1511
+
1512
+/*
1513
+ * In order for other display interfaces to use hdmiphy as source
1514
+ * for dclk, hdmiphy must register a virtual clock driver
1515
+ */
1516
+U_BOOT_DRIVER(clk_inno_hdmi) = {
1517
+ .name = "clk_inno_hdmi",
1518
+ .id = UCLASS_CLK,
1519
+ .priv_auto_alloc_size = sizeof(struct clk_inno_hdmi),
1520
+ .ops = &inno_hdmi_clk_ops,
1521
+ .probe = inno_hdmi_clk_probe,
1522
+};
u-boot/drivers/video/drm/rockchip_connector.c
....@@ -15,6 +15,19 @@
1515 #include "rockchip_connector.h"
1616 #include "rockchip_phy.h"
1717
18
+#ifdef CONFIG_SPL_BUILD
19
+int rockchip_connector_bind(struct rockchip_connector *conn, struct udevice *dev, int id,
20
+ const struct rockchip_connector_funcs *funcs, void *data, int type)
21
+{
22
+ conn->id = id;
23
+ conn->funcs = funcs;
24
+ conn->data = data;
25
+ conn->type = type;
26
+
27
+ return 0;
28
+}
29
+
30
+#else
1831 static LIST_HEAD(rockchip_connector_list);
1932
2033 int rockchip_connector_bind(struct rockchip_connector *conn, struct udevice *dev, int id,
....@@ -105,21 +118,6 @@
105118 return ret;
106119 }
107120
108
-int rockchip_connector_deinit(struct display_state *state)
109
-{
110
- struct rockchip_connector *conn;
111
-
112
- conn = state->conn_state.connector;
113
- if (conn->funcs->deinit) {
114
- conn->funcs->deinit(conn, state);
115
- if (state->conn_state.secondary) {
116
- conn = state->conn_state.secondary;
117
- conn->funcs->deinit(conn, state);
118
- }
119
- }
120
-
121
- return 0;
122
-}
123121
124122 static bool rockchip_connector_path_detect(struct rockchip_connector *conn,
125123 struct display_state *state)
....@@ -322,3 +320,20 @@
322320
323321 return 0;
324322 }
323
+#endif
324
+
325
+int rockchip_connector_deinit(struct display_state *state)
326
+{
327
+ struct rockchip_connector *conn;
328
+
329
+ conn = state->conn_state.connector;
330
+ if (conn->funcs->deinit) {
331
+ conn->funcs->deinit(conn, state);
332
+ if (state->conn_state.secondary) {
333
+ conn = state->conn_state.secondary;
334
+ conn->funcs->deinit(conn, state);
335
+ }
336
+ }
337
+
338
+ return 0;
339
+}
u-boot/drivers/video/drm/rockchip_connector.h
....@@ -7,6 +7,17 @@
77 #ifndef _ROCKCHIP_CONNECTOR_H_
88 #define _ROCKCHIP_CONNECTOR_H_
99
10
+#ifdef CONFIG_SPL_BUILD
11
+struct rockchip_connector {
12
+ struct rockchip_phy *phy;
13
+ int id;
14
+ int type;
15
+ bool hpd;
16
+
17
+ const struct rockchip_connector_funcs *funcs;
18
+ void *data;
19
+};
20
+#else
1021 #include "rockchip_bridge.h"
1122 #include "rockchip_panel.h"
1223
....@@ -18,10 +29,123 @@
1829 struct list_head head;
1930 int id;
2031 int type;
32
+ bool hpd;
2133
2234 const struct rockchip_connector_funcs *funcs;
2335 void *data;
2436 };
37
+#endif
38
+
39
+/**
40
+ * enum drm_bus_flags - bus_flags info for &drm_display_info
41
+ *
42
+ * This enum defines signal polarities and clock edge information for signals on
43
+ * a bus as bitmask flags.
44
+ *
45
+ * The clock edge information is conveyed by two sets of symbols,
46
+ * DRM_BUS_FLAGS_*_DRIVE_\* and DRM_BUS_FLAGS_*_SAMPLE_\*. When this enum is
47
+ * used to describe a bus from the point of view of the transmitter, the
48
+ * \*_DRIVE_\* flags should be used. When used from the point of view of the
49
+ * receiver, the \*_SAMPLE_\* flags should be used. The \*_DRIVE_\* and
50
+ * \*_SAMPLE_\* flags alias each other, with the \*_SAMPLE_POSEDGE and
51
+ * \*_SAMPLE_NEGEDGE flags being equal to \*_DRIVE_NEGEDGE and \*_DRIVE_POSEDGE
52
+ * respectively. This simplifies code as signals are usually sampled on the
53
+ * opposite edge of the driving edge. Transmitters and receivers may however
54
+ * need to take other signal timings into account to convert between driving
55
+ * and sample edges.
56
+ */
57
+enum drm_bus_flags {
58
+ /**
59
+ * @DRM_BUS_FLAG_DE_LOW:
60
+ *
61
+ * The Data Enable signal is active low
62
+ */
63
+ DRM_BUS_FLAG_DE_LOW = BIT(0),
64
+
65
+ /**
66
+ * @DRM_BUS_FLAG_DE_HIGH:
67
+ *
68
+ * The Data Enable signal is active high
69
+ */
70
+ DRM_BUS_FLAG_DE_HIGH = BIT(1),
71
+
72
+ /**
73
+ * @DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE:
74
+ *
75
+ * Data is driven on the rising edge of the pixel clock
76
+ */
77
+ DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE = BIT(2),
78
+
79
+ /**
80
+ * @DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE:
81
+ *
82
+ * Data is driven on the falling edge of the pixel clock
83
+ */
84
+ DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE = BIT(3),
85
+
86
+ /**
87
+ * @DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE:
88
+ *
89
+ * Data is sampled on the rising edge of the pixel clock
90
+ */
91
+ DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE = DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
92
+
93
+ /**
94
+ * @DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE:
95
+ *
96
+ * Data is sampled on the falling edge of the pixel clock
97
+ */
98
+ DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
99
+
100
+ /**
101
+ * @DRM_BUS_FLAG_DATA_MSB_TO_LSB:
102
+ *
103
+ * Data is transmitted MSB to LSB on the bus
104
+ */
105
+ DRM_BUS_FLAG_DATA_MSB_TO_LSB = BIT(4),
106
+
107
+ /**
108
+ * @DRM_BUS_FLAG_DATA_LSB_TO_MSB:
109
+ *
110
+ * Data is transmitted LSB to MSB on the bus
111
+ */
112
+ DRM_BUS_FLAG_DATA_LSB_TO_MSB = BIT(5),
113
+
114
+ /**
115
+ * @DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE:
116
+ *
117
+ * Sync signals are driven on the rising edge of the pixel clock
118
+ */
119
+ DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE = BIT(6),
120
+
121
+ /**
122
+ * @DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE:
123
+ *
124
+ * Sync signals are driven on the falling edge of the pixel clock
125
+ */
126
+ DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE = BIT(7),
127
+
128
+ /**
129
+ * @DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE:
130
+ *
131
+ * Sync signals are sampled on the rising edge of the pixel clock
132
+ */
133
+ DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
134
+
135
+ /**
136
+ * @DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE:
137
+ *
138
+ * Sync signals are sampled on the falling edge of the pixel clock
139
+ */
140
+ DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE = DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
141
+
142
+ /**
143
+ * @DRM_BUS_FLAG_SHARP_SIGNALS:
144
+ *
145
+ * Set if the Sharp-specific signals (SPL, CLS, PS, REV) must be used
146
+ */
147
+ DRM_BUS_FLAG_SHARP_SIGNALS = BIT(8),
148
+};
25149
26150 struct rockchip_connector_funcs {
27151 /*
u-boot/drivers/video/drm/rockchip_crtc.c
....@@ -20,6 +20,7 @@
2020 #include "rockchip_crtc.h"
2121 #include "rockchip_connector.h"
2222
23
+#ifndef CONFIG_SPL_BUILD
2324 static const struct udevice_id rockchip_vp_ids[] = {
2425 { .compatible = "rockchip-vp" },
2526 { }
....@@ -111,6 +112,16 @@
111112 .data = &rk3328_vop,
112113 };
113114
115
+static const struct rockchip_crtc rk3528_vop_data = {
116
+ .funcs = &rockchip_vop2_funcs,
117
+ .data = &rk3528_vop,
118
+};
119
+
120
+static const struct rockchip_crtc rk3562_vop_data = {
121
+ .funcs = &rockchip_vop2_funcs,
122
+ .data = &rk3562_vop,
123
+};
124
+
114125 static const struct rockchip_crtc rk3568_vop_data = {
115126 .funcs = &rockchip_vop2_funcs,
116127 .data = &rk3568_vop,
....@@ -174,6 +185,12 @@
174185 .compatible = "rockchip,rk3328-vop",
175186 .data = (ulong)&rk3328_vop_data,
176187 }, {
188
+ .compatible = "rockchip,rk3528-vop",
189
+ .data = (ulong)&rk3528_vop_data,
190
+ }, {
191
+ .compatible = "rockchip,rk3562-vop",
192
+ .data = (ulong)&rk3562_vop_data,
193
+ }, {
177194 .compatible = "rockchip,rk3568-vop",
178195 .data = (ulong)&rk3568_vop_data,
179196 }, {
....@@ -186,6 +203,13 @@
186203 {
187204 struct udevice *child;
188205 int ret;
206
+
207
+ /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
208
+ ret = clk_set_defaults(dev);
209
+ if (ret) {
210
+ dev_err(dev, "%s clk_set_defaults failed %d\n", __func__, ret);
211
+ return ret;
212
+ }
189213
190214 for (device_find_first_child(dev, &child);
191215 child;
....@@ -237,3 +261,19 @@
237261 .id = UCLASS_VIDEO_CRTC,
238262 .name = "CRTC",
239263 };
264
+
265
+#else
266
+static struct rockchip_crtc rk3528_vop_data = {
267
+ .funcs = &rockchip_vop2_funcs,
268
+ .data = &rk3528_vop,
269
+};
270
+
271
+int rockchip_spl_vop_probe(struct crtc_state *crtc_state)
272
+{
273
+
274
+ crtc_state->crtc = &rk3528_vop_data;
275
+
276
+ return 0;
277
+}
278
+#endif
279
+
u-boot/drivers/video/drm/rockchip_crtc.h
....@@ -44,7 +44,11 @@
4444 int (*send_mcu_cmd)(struct display_state *state, u32 type, u32 value);
4545 int (*check)(struct display_state *state);
4646 int (*mode_valid)(struct display_state *state);
47
+ int (*mode_fixup)(struct display_state *state);
4748 int (*plane_check)(struct display_state *state);
49
+ int (*regs_dump)(struct display_state *state);
50
+ int (*active_regs_dump)(struct display_state *state);
51
+ int (*apply_soft_te)(struct display_state *state);
4852 };
4953
5054 struct vop_data;
....@@ -67,6 +71,8 @@
6771 extern const struct vop_data rv1106_vop;
6872 extern const struct vop_data rv1108_vop;
6973 extern const struct vop_data rv1126_vop;
74
+extern const struct vop2_data rk3528_vop;
75
+extern const struct vop2_data rk3562_vop;
7076 extern const struct vop2_data rk3568_vop;
7177 extern const struct vop2_data rk3588_vop;
7278 #endif
u-boot/drivers/video/drm/rockchip_display.c
....@@ -57,7 +57,7 @@
5757 static unsigned long cubic_lut_memory_start;
5858 static unsigned long memory_end;
5959 static struct base2_info base_parameter;
60
-static uint32_t crc32_table[256];
60
+static u32 align_size = PAGE_SIZE;
6161
6262 /*
6363 * the phy types are used by different connectors in public.
....@@ -75,41 +75,6 @@
7575 int public_phy_type;
7676 bool phy_init;
7777 };
78
-
79
-void rockchip_display_make_crc32_table(void)
80
-{
81
- uint32_t c;
82
- int n, k;
83
- unsigned long poly; /* polynomial exclusive-or pattern */
84
- /* terms of polynomial defining this crc (except x^32): */
85
- static const char p[] = {0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26};
86
-
87
- /* make exclusive-or pattern from polynomial (0xedb88320L) */
88
- poly = 0L;
89
- for (n = 0; n < sizeof(p) / sizeof(char); n++)
90
- poly |= 1L << (31 - p[n]);
91
-
92
- for (n = 0; n < 256; n++) {
93
- c = (unsigned long)n;
94
- for (k = 0; k < 8; k++)
95
- c = c & 1 ? poly ^ (c >> 1) : c >> 1;
96
- crc32_table[n] = cpu_to_le32(c);
97
- }
98
-}
99
-
100
-uint32_t rockchip_display_crc32c_cal(unsigned char *data, int length)
101
-{
102
- int i;
103
- uint32_t crc;
104
- crc = 0xFFFFFFFF;
105
-
106
- for (i = 0; i < length; i++) {
107
- crc = crc32_table[(crc ^ *data) & 0xff] ^ (crc >> 8);
108
- data++;
109
- }
110
-
111
- return crc ^ 0xffffffff;
112
-}
11378
11479 int rockchip_get_baseparameter(void)
11580 {
....@@ -152,6 +117,7 @@
152117 struct base2_disp_header *disp_header;
153118 int i = 0, offset = -1;
154119 u32 crc_val;
120
+ u32 base2_length;
155121 void *base_parameter_addr = (void *)&base_parameter;
156122
157123 for (i = 0; i < 8; i++) {
....@@ -178,11 +144,23 @@
178144 if (strncasecmp(disp_info->disp_head_flag, "DISP", 4))
179145 return NULL;
180146
181
- crc_val = rockchip_display_crc32c_cal((unsigned char *)disp_info, sizeof(struct base2_disp_info) - 4);
182
-
183
- if (crc_val != disp_info->crc) {
184
- printf("error: connector type[%d], id[%d] disp info crc check error\n", type, id);
185
- return NULL;
147
+ if (base_parameter.major_version == 3 && base_parameter.minor_version == 0) {
148
+ crc_val = rockchip_display_crc32c_cal((unsigned char *)disp_info,
149
+ sizeof(struct base2_disp_info) - 4);
150
+ if (crc_val != disp_info->crc2) {
151
+ printf("error: connector type[%d], id[%d] disp info crc2 check error\n",
152
+ type, id);
153
+ return NULL;
154
+ }
155
+ } else {
156
+ base2_length = sizeof(struct base2_disp_info) - sizeof(struct csc_info) -
157
+ sizeof(struct acm_data) - 10 * 1024 - 4;
158
+ crc_val = rockchip_display_crc32c_cal((unsigned char *)disp_info, base2_length - 4);
159
+ if (crc_val != disp_info->crc) {
160
+ printf("error: connector type[%d], id[%d] disp info crc check error\n",
161
+ type, id);
162
+ return NULL;
163
+ }
186164 }
187165
188166 return disp_info;
....@@ -253,9 +231,9 @@
253231
254232 static void init_display_buffer(ulong base)
255233 {
256
- memory_start = base + DRM_ROCKCHIP_FB_SIZE;
234
+ memory_start = ALIGN(base + DRM_ROCKCHIP_FB_SIZE, align_size);
257235 memory_end = memory_start;
258
- cubic_lut_memory_start = memory_start + MEMORY_POOL_SIZE;
236
+ cubic_lut_memory_start = ALIGN(memory_start + MEMORY_POOL_SIZE, align_size);
259237 }
260238
261239 void *get_display_buffer(int size)
....@@ -340,38 +318,15 @@
340318 return 0;
341319 }
342320
343
-int drm_mode_vrefresh(const struct drm_display_mode *mode)
344
-{
345
- int refresh = 0;
346
- unsigned int calc_val;
347
-
348
- if (mode->vrefresh > 0) {
349
- refresh = mode->vrefresh;
350
- } else if (mode->htotal > 0 && mode->vtotal > 0) {
351
- int vtotal;
352
-
353
- vtotal = mode->vtotal;
354
- /* work out vrefresh the value will be x1000 */
355
- calc_val = (mode->clock * 1000);
356
- calc_val /= mode->htotal;
357
- refresh = (calc_val + vtotal / 2) / vtotal;
358
-
359
- if (mode->flags & DRM_MODE_FLAG_INTERLACE)
360
- refresh *= 2;
361
- if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
362
- refresh /= 2;
363
- if (mode->vscan > 1)
364
- refresh /= mode->vscan;
365
- }
366
- return refresh;
367
-}
368
-
369
-int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode)
321
+int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode, u32 *bus_flags)
370322 {
371323 int hactive, vactive, pixelclock;
372324 int hfront_porch, hback_porch, hsync_len;
373325 int vfront_porch, vback_porch, vsync_len;
374326 int val, flags = 0;
327
+
328
+#define FDT_GET_BOOL(val, name) \
329
+ val = ofnode_read_bool(node, name);
375330
376331 #define FDT_GET_INT(val, name) \
377332 val = ofnode_read_s32_default(node, name, -1); \
....@@ -396,8 +351,18 @@
396351 flags |= val ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
397352 FDT_GET_INT(val, "vsync-active");
398353 flags |= val ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
354
+
355
+ FDT_GET_BOOL(val, "interlaced");
356
+ flags |= val ? DRM_MODE_FLAG_INTERLACE : 0;
357
+ FDT_GET_BOOL(val, "doublescan");
358
+ flags |= val ? DRM_MODE_FLAG_DBLSCAN : 0;
359
+ FDT_GET_BOOL(val, "doubleclk");
360
+ flags |= val ? DISPLAY_FLAGS_DOUBLECLK : 0;
361
+
362
+ FDT_GET_INT(val, "de-active");
363
+ *bus_flags |= val ? DRM_BUS_FLAG_DE_HIGH : DRM_BUS_FLAG_DE_LOW;
399364 FDT_GET_INT(val, "pixelclk-active");
400
- flags |= val ? DRM_MODE_FLAG_PPIXDATA : 0;
365
+ *bus_flags |= val ? DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE : DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE;
401366
402367 FDT_GET_INT_DEFAULT(val, "screen-rotate", 0);
403368 if (val == DRM_MODE_FLAG_XMIRROR) {
....@@ -425,11 +390,13 @@
425390 return 0;
426391 }
427392
428
-static int display_get_force_timing_from_dts(ofnode node, struct drm_display_mode *mode)
393
+static int display_get_force_timing_from_dts(ofnode node,
394
+ struct drm_display_mode *mode,
395
+ u32 *bus_flags)
429396 {
430397 int ret = 0;
431398
432
- ret = rockchip_ofnode_get_display_mode(node, mode);
399
+ ret = rockchip_ofnode_get_display_mode(node, mode, bus_flags);
433400
434401 if (ret) {
435402 mode->clock = 74250;
....@@ -456,14 +423,24 @@
456423 }
457424
458425 static int display_get_timing_from_dts(struct rockchip_panel *panel,
459
- struct drm_display_mode *mode)
426
+ struct drm_display_mode *mode,
427
+ u32 *bus_flags)
460428 {
461429 struct ofnode_phandle_args args;
462
- ofnode dt, timing;
430
+ ofnode dt, timing, mcu_panel;
463431 int ret;
464432
433
+ mcu_panel = dev_read_subnode(panel->dev, "mcu-panel");
465434 dt = dev_read_subnode(panel->dev, "display-timings");
466435 if (ofnode_valid(dt)) {
436
+ ret = ofnode_parse_phandle_with_args(dt, "native-mode", NULL,
437
+ 0, 0, &args);
438
+ if (ret)
439
+ return ret;
440
+
441
+ timing = args.node;
442
+ } else if (ofnode_valid(mcu_panel)) {
443
+ dt = ofnode_find_subnode(mcu_panel, "display-timings");
467444 ret = ofnode_parse_phandle_with_args(dt, "native-mode", NULL,
468445 0, 0, &args);
469446 if (ret)
....@@ -479,163 +456,26 @@
479456 return -ENXIO;
480457 }
481458
482
- rockchip_ofnode_get_display_mode(timing, mode);
459
+ rockchip_ofnode_get_display_mode(timing, mode, bus_flags);
460
+
461
+ if (IS_ENABLED(CONFIG_ROCKCHIP_RK3568) || IS_ENABLED(CONFIG_ROCKCHIP_RK3588)) {
462
+ if (mode->hdisplay % 4) {
463
+ int old_hdisplay = mode->hdisplay;
464
+ int align = 4 - (mode->hdisplay % 4);
465
+
466
+ mode->hdisplay += align;
467
+ mode->hsync_start += align;
468
+ mode->hsync_end += align;
469
+ mode->htotal += align;
470
+
471
+ ofnode_write_u32_array(timing, "hactive", (u32 *)&mode->hdisplay, 1);
472
+
473
+ printf("WARN: hactive need to be aligned with 4-pixel, %d -> %d\n",
474
+ old_hdisplay, mode->hdisplay);
475
+ }
476
+ }
483477
484478 return 0;
485
-}
486
-
487
-/**
488
- * drm_mode_max_resolution_filter - mark modes out of vop max resolution
489
- * @edid_data: structure store mode list
490
- * @max_output: vop max output resolution
491
- */
492
-void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data,
493
- struct vop_rect *max_output)
494
-{
495
- int i;
496
-
497
- for (i = 0; i < edid_data->modes; i++) {
498
- if (edid_data->mode_buf[i].hdisplay > max_output->width ||
499
- edid_data->mode_buf[i].vdisplay > max_output->height)
500
- edid_data->mode_buf[i].invalid = true;
501
- }
502
-}
503
-
504
-/**
505
- * drm_mode_set_crtcinfo - set CRTC modesetting timing parameters
506
- * @p: mode
507
- * @adjust_flags: a combination of adjustment flags
508
- *
509
- * Setup the CRTC modesetting timing parameters for @p, adjusting if necessary.
510
- *
511
- * - The CRTC_INTERLACE_HALVE_V flag can be used to halve vertical timings of
512
- * interlaced modes.
513
- * - The CRTC_STEREO_DOUBLE flag can be used to compute the timings for
514
- * buffers containing two eyes (only adjust the timings when needed, eg. for
515
- * "frame packing" or "side by side full").
516
- * - The CRTC_NO_DBLSCAN and CRTC_NO_VSCAN flags request that adjustment *not*
517
- * be performed for doublescan and vscan > 1 modes respectively.
518
- */
519
-void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags)
520
-{
521
- if ((p == NULL) || ((p->type & DRM_MODE_TYPE_CRTC_C) == DRM_MODE_TYPE_BUILTIN))
522
- return;
523
-
524
- if (p->flags & DRM_MODE_FLAG_DBLCLK)
525
- p->crtc_clock = 2 * p->clock;
526
- else
527
- p->crtc_clock = p->clock;
528
- p->crtc_hdisplay = p->hdisplay;
529
- p->crtc_hsync_start = p->hsync_start;
530
- p->crtc_hsync_end = p->hsync_end;
531
- p->crtc_htotal = p->htotal;
532
- p->crtc_hskew = p->hskew;
533
- p->crtc_vdisplay = p->vdisplay;
534
- p->crtc_vsync_start = p->vsync_start;
535
- p->crtc_vsync_end = p->vsync_end;
536
- p->crtc_vtotal = p->vtotal;
537
-
538
- if (p->flags & DRM_MODE_FLAG_INTERLACE) {
539
- if (adjust_flags & CRTC_INTERLACE_HALVE_V) {
540
- p->crtc_vdisplay /= 2;
541
- p->crtc_vsync_start /= 2;
542
- p->crtc_vsync_end /= 2;
543
- p->crtc_vtotal /= 2;
544
- }
545
- }
546
-
547
- if (!(adjust_flags & CRTC_NO_DBLSCAN)) {
548
- if (p->flags & DRM_MODE_FLAG_DBLSCAN) {
549
- p->crtc_vdisplay *= 2;
550
- p->crtc_vsync_start *= 2;
551
- p->crtc_vsync_end *= 2;
552
- p->crtc_vtotal *= 2;
553
- }
554
- }
555
-
556
- if (!(adjust_flags & CRTC_NO_VSCAN)) {
557
- if (p->vscan > 1) {
558
- p->crtc_vdisplay *= p->vscan;
559
- p->crtc_vsync_start *= p->vscan;
560
- p->crtc_vsync_end *= p->vscan;
561
- p->crtc_vtotal *= p->vscan;
562
- }
563
- }
564
-
565
- if (adjust_flags & CRTC_STEREO_DOUBLE) {
566
- unsigned int layout = p->flags & DRM_MODE_FLAG_3D_MASK;
567
-
568
- switch (layout) {
569
- case DRM_MODE_FLAG_3D_FRAME_PACKING:
570
- p->crtc_clock *= 2;
571
- p->crtc_vdisplay += p->crtc_vtotal;
572
- p->crtc_vsync_start += p->crtc_vtotal;
573
- p->crtc_vsync_end += p->crtc_vtotal;
574
- p->crtc_vtotal += p->crtc_vtotal;
575
- break;
576
- }
577
- }
578
-
579
- p->crtc_vblank_start = min(p->crtc_vsync_start, p->crtc_vdisplay);
580
- p->crtc_vblank_end = max(p->crtc_vsync_end, p->crtc_vtotal);
581
- p->crtc_hblank_start = min(p->crtc_hsync_start, p->crtc_hdisplay);
582
- p->crtc_hblank_end = max(p->crtc_hsync_end, p->crtc_htotal);
583
-}
584
-
585
-/**
586
- * drm_mode_is_420_only - if a given videomode can be only supported in YCBCR420
587
- * output format
588
- *
589
- * @connector: drm connector under action.
590
- * @mode: video mode to be tested.
591
- *
592
- * Returns:
593
- * true if the mode can be supported in YCBCR420 format
594
- * false if not.
595
- */
596
-bool drm_mode_is_420_only(const struct drm_display_info *display,
597
- struct drm_display_mode *mode)
598
-{
599
- u8 vic = drm_match_cea_mode(mode);
600
-
601
- return test_bit(vic, display->hdmi.y420_vdb_modes);
602
-}
603
-
604
-/**
605
- * drm_mode_is_420_also - if a given videomode can be supported in YCBCR420
606
- * output format also (along with RGB/YCBCR444/422)
607
- *
608
- * @display: display under action.
609
- * @mode: video mode to be tested.
610
- *
611
- * Returns:
612
- * true if the mode can be support YCBCR420 format
613
- * false if not.
614
- */
615
-bool drm_mode_is_420_also(const struct drm_display_info *display,
616
- struct drm_display_mode *mode)
617
-{
618
- u8 vic = drm_match_cea_mode(mode);
619
-
620
- return test_bit(vic, display->hdmi.y420_cmdb_modes);
621
-}
622
-
623
-/**
624
- * drm_mode_is_420 - if a given videomode can be supported in YCBCR420
625
- * output format
626
- *
627
- * @display: display under action.
628
- * @mode: video mode to be tested.
629
- *
630
- * Returns:
631
- * true if the mode can be supported in YCBCR420 format
632
- * false if not.
633
- */
634
-bool drm_mode_is_420(const struct drm_display_info *display,
635
- struct drm_display_mode *mode)
636
-{
637
- return drm_mode_is_420_only(display, mode) ||
638
- drm_mode_is_420_also(display, mode);
639479 }
640480
641481 static int display_get_timing(struct display_state *state)
....@@ -649,7 +489,7 @@
649489 return panel->funcs->get_mode(panel, mode);
650490
651491 if (dev_of_valid(panel->dev) &&
652
- !display_get_timing_from_dts(panel, mode)) {
492
+ !display_get_timing_from_dts(panel, mode, &conn_state->bus_flags)) {
653493 printf("Using display timing dts\n");
654494 return 0;
655495 }
....@@ -730,6 +570,47 @@
730570 return ret;
731571 }
732572
573
+static int display_mode_valid(struct display_state *state)
574
+{
575
+ struct connector_state *conn_state = &state->conn_state;
576
+ struct rockchip_connector *conn = conn_state->connector;
577
+ const struct rockchip_connector_funcs *conn_funcs = conn->funcs;
578
+ struct crtc_state *crtc_state = &state->crtc_state;
579
+ const struct rockchip_crtc *crtc = crtc_state->crtc;
580
+ const struct rockchip_crtc_funcs *crtc_funcs = crtc->funcs;
581
+ int ret;
582
+
583
+ if (conn_funcs->mode_valid && state->enabled_at_spl == false) {
584
+ ret = conn_funcs->mode_valid(conn, state);
585
+ if (ret)
586
+ return ret;
587
+ }
588
+
589
+ if (crtc_funcs->mode_valid) {
590
+ ret = crtc_funcs->mode_valid(state);
591
+ if (ret)
592
+ return ret;
593
+ }
594
+
595
+ return 0;
596
+}
597
+
598
+static int display_mode_fixup(struct display_state *state)
599
+{
600
+ struct crtc_state *crtc_state = &state->crtc_state;
601
+ const struct rockchip_crtc *crtc = crtc_state->crtc;
602
+ const struct rockchip_crtc_funcs *crtc_funcs = crtc->funcs;
603
+ int ret;
604
+
605
+ if (crtc_funcs->mode_fixup) {
606
+ ret = crtc_funcs->mode_fixup(state);
607
+ if (ret)
608
+ return ret;
609
+ }
610
+
611
+ return 0;
612
+}
613
+
733614 static int display_init(struct display_state *state)
734615 {
735616 struct connector_state *conn_state = &state->conn_state;
....@@ -741,7 +622,9 @@
741622 const char *compatible;
742623 int ret = 0;
743624 static bool __print_once = false;
744
-
625
+#ifdef CONFIG_SPL_BUILD
626
+ struct spl_display_info *spl_disp_info = (struct spl_display_info *)CONFIG_SPL_VIDEO_BUF;
627
+#endif
745628 if (!__print_once) {
746629 __print_once = true;
747630 printf("Rockchip UBOOT DRM driver version: %s\n", DRIVER_VERSION);
....@@ -755,6 +638,12 @@
755638 return -ENXIO;
756639 }
757640
641
+#ifdef CONFIG_SPL_BUILD
642
+ if (state->conn_state.type == DRM_MODE_CONNECTOR_HDMIA)
643
+ state->enabled_at_spl = spl_disp_info->enabled == 1 ? true : false;
644
+ if (state->enabled_at_spl)
645
+ printf("HDMI enabled at SPL\n");
646
+#endif
758647 if (crtc_state->crtc->active && !crtc_state->ports_node &&
759648 memcmp(&crtc_state->crtc->active_mode, &conn_state->mode,
760649 sizeof(struct drm_display_mode))) {
....@@ -773,14 +662,16 @@
773662 return ret;
774663 }
775664
776
- ret = rockchip_connector_init(state);
777
- if (ret)
778
- goto deinit;
665
+ if (state->enabled_at_spl == false) {
666
+ ret = rockchip_connector_init(state);
667
+ if (ret)
668
+ goto deinit;
669
+ }
779670
780671 /*
781672 * support hotplug, but not connect;
782673 */
783
-#ifdef CONFIG_ROCKCHIP_DRM_TVE
674
+#ifdef CONFIG_DRM_ROCKCHIP_TVE
784675 if (crtc->hdmi_hpd && conn_state->type == DRM_MODE_CONNECTOR_TV) {
785676 printf("hdmi plugin ,skip tve\n");
786677 goto deinit;
....@@ -793,14 +684,27 @@
793684 #endif
794685
795686 ret = rockchip_connector_detect(state);
796
-#if defined(CONFIG_ROCKCHIP_DRM_TVE) || defined(CONFIG_DRM_ROCKCHIP_RK1000)
687
+#if defined(CONFIG_DRM_ROCKCHIP_TVE) || defined(CONFIG_DRM_ROCKCHIP_RK1000)
797688 if (conn_state->type == DRM_MODE_CONNECTOR_HDMIA)
798689 crtc->hdmi_hpd = ret;
690
+ if (state->enabled_at_spl)
691
+ crtc->hdmi_hpd = true;
799692 #endif
800693 if (!ret && !state->force_output)
801694 goto deinit;
802695
803
- if (conn->panel) {
696
+ ret = 0;
697
+ if (state->enabled_at_spl == true) {
698
+#ifdef CONFIG_SPL_BUILD
699
+ struct drm_display_mode *mode = &conn_state->mode;
700
+
701
+ memcpy(mode, &spl_disp_info->mode, sizeof(*mode));
702
+ conn_state->bus_format = spl_disp_info->bus_format;
703
+
704
+ printf("%s get display mode from spl:%dx%d, bus format:0x%x\n",
705
+ conn->dev->name, mode->hdisplay, mode->vdisplay, conn_state->bus_format);
706
+#endif
707
+ } else if (conn->panel) {
804708 ret = display_get_timing(state);
805709 if (!ret)
806710 conn_state->bpc = conn->panel->bpc;
....@@ -853,10 +757,15 @@
853757 if (state->force_output)
854758 display_use_force_mode(state);
855759
760
+ if (display_mode_valid(state))
761
+ goto deinit;
762
+
856763 /* rk356x series drive mipi pixdata on posedge */
857764 compatible = dev_read_string(conn->dev, "compatible");
858
- if (!strcmp(compatible, "rockchip,rk3568-mipi-dsi"))
859
- conn_state->mode.flags |= DRM_MODE_FLAG_PPIXDATA;
765
+ if (!strcmp(compatible, "rockchip,rk3568-mipi-dsi")) {
766
+ conn_state->bus_flags &= ~DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE;
767
+ conn_state->bus_flags |= DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE;
768
+ }
860769
861770 printf("%s: %s detailed mode clock %u kHz, flags[%x]\n"
862771 " H: %04d %04d %04d %04d\n"
....@@ -871,20 +780,13 @@
871780 mode->vsync_end, mode->vtotal,
872781 conn_state->bus_format);
873782
874
- drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
875
-
876
- if (conn_state->secondary) {
877
- mode->crtc_clock *= 2;
878
- mode->crtc_hdisplay *= 2;
879
- mode->crtc_hsync_start *= 2;
880
- mode->crtc_hsync_end *= 2;
881
- mode->crtc_htotal *= 2;
882
- }
783
+ if (display_mode_fixup(state))
784
+ goto deinit;
883785
884786 if (conn->bridge)
885787 rockchip_bridge_mode_set(conn->bridge, &conn_state->mode);
886788
887
- if (crtc_funcs->init) {
789
+ if (crtc_funcs->init && state->enabled_at_spl == false) {
888790 ret = crtc_funcs->init(state);
889791 if (ret)
890792 goto deinit;
....@@ -955,12 +857,17 @@
955857 if (crtc_funcs->prepare)
956858 crtc_funcs->prepare(state);
957859
958
- rockchip_connector_pre_enable(state);
860
+ if (state->enabled_at_spl == false)
861
+ rockchip_connector_pre_enable(state);
959862
960863 if (crtc_funcs->enable)
961864 crtc_funcs->enable(state);
962865
963
- rockchip_connector_enable(state);
866
+ if (state->enabled_at_spl == false)
867
+ rockchip_connector_enable(state);
868
+
869
+ if (crtc_state->soft_te)
870
+ crtc_funcs->apply_soft_te(state);
964871
965872 state->is_enable = true;
966873
....@@ -990,54 +897,6 @@
990897 state->is_init = 0;
991898
992899 return 0;
993
-}
994
-
995
-static int display_rect_calc_scale(int src, int dst)
996
-{
997
- int scale = 0;
998
-
999
- if (WARN_ON(src < 0 || dst < 0))
1000
- return -EINVAL;
1001
-
1002
- if (dst == 0)
1003
- return 0;
1004
-
1005
- src <<= 16;
1006
-
1007
- if (src > (dst << 16))
1008
- return DIV_ROUND_UP(src, dst);
1009
- else
1010
- scale = src / dst;
1011
-
1012
- return scale;
1013
-}
1014
-
1015
-int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst,
1016
- int min_hscale, int max_hscale)
1017
-{
1018
- int hscale = display_rect_calc_scale(src->w, dst->w);
1019
-
1020
- if (hscale < 0 || dst->w == 0)
1021
- return hscale;
1022
-
1023
- if (hscale < min_hscale || hscale > max_hscale)
1024
- return -ERANGE;
1025
-
1026
- return hscale;
1027
-}
1028
-
1029
-int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst,
1030
- int min_vscale, int max_vscale)
1031
-{
1032
- int vscale = display_rect_calc_scale(src->h, dst->h);
1033
-
1034
- if (vscale < 0 || dst->h == 0)
1035
- return vscale;
1036
-
1037
- if (vscale < min_vscale || vscale > max_vscale)
1038
- return -ERANGE;
1039
-
1040
- return vscale;
1041900 }
1042901
1043902 static int display_check(struct display_state *state)
....@@ -1074,38 +933,6 @@
1074933 return 0;
1075934
1076935 check_fail:
1077
- state->is_init = false;
1078
- return ret;
1079
-}
1080
-
1081
-static int display_mode_valid(struct display_state *state)
1082
-{
1083
- struct connector_state *conn_state = &state->conn_state;
1084
- struct rockchip_connector *conn = conn_state->connector;
1085
- const struct rockchip_connector_funcs *conn_funcs = conn->funcs;
1086
- struct crtc_state *crtc_state = &state->crtc_state;
1087
- const struct rockchip_crtc *crtc = crtc_state->crtc;
1088
- const struct rockchip_crtc_funcs *crtc_funcs = crtc->funcs;
1089
- int ret;
1090
-
1091
- if (!state->is_init)
1092
- return 0;
1093
-
1094
- if (conn_funcs->mode_valid) {
1095
- ret = conn_funcs->mode_valid(conn, state);
1096
- if (ret)
1097
- goto invalid_mode;
1098
- }
1099
-
1100
- if (crtc_funcs->mode_valid) {
1101
- ret = crtc_funcs->mode_valid(state);
1102
- if (ret)
1103
- goto invalid_mode;
1104
- }
1105
-
1106
- return 0;
1107
-
1108
-invalid_mode:
1109936 state->is_init = false;
1110937 return ret;
1111938 }
....@@ -1170,7 +997,6 @@
1170997 }
1171998 }
1172999
1173
- display_mode_valid(state);
11741000 display_check(state);
11751001 display_set_plane(state);
11761002 display_enable(state);
....@@ -1213,14 +1039,22 @@
12131039 return 0;
12141040 }
12151041
1216
-static int get_crtc_mcu_mode(struct crtc_state *crtc_state)
1042
+static int get_crtc_mcu_mode(struct crtc_state *crtc_state, struct device_node *port_node,
1043
+ bool is_ports_node)
12171044 {
1218
- ofnode mcu_node;
1045
+ ofnode mcu_node, vp_node;
12191046 int total_pixel, cs_pst, cs_pend, rw_pst, rw_pend;
12201047
1221
- mcu_node = dev_read_subnode(crtc_state->dev, "mcu-timing");
1222
- if (!ofnode_valid(mcu_node))
1223
- return -ENODEV;
1048
+ if (is_ports_node) {
1049
+ vp_node = np_to_ofnode(port_node);
1050
+ mcu_node = ofnode_find_subnode(vp_node, "mcu-timing");
1051
+ if (!ofnode_valid(mcu_node))
1052
+ return -ENODEV;
1053
+ } else {
1054
+ mcu_node = dev_read_subnode(crtc_state->dev, "mcu-timing");
1055
+ if (!ofnode_valid(mcu_node))
1056
+ return -ENODEV;
1057
+ }
12241058
12251059 #define FDT_GET_MCU_INT(val, name) \
12261060 do { \
....@@ -1464,6 +1298,35 @@
14641298 return ret;
14651299 }
14661300
1301
+int rockchip_vop_dump(const char *cmd)
1302
+{
1303
+ struct display_state *state;
1304
+ struct crtc_state *crtc_state;
1305
+ struct rockchip_crtc *crtc;
1306
+ const struct rockchip_crtc_funcs *crtc_funcs;
1307
+ int ret = -EINVAL;
1308
+
1309
+ list_for_each_entry(state, &rockchip_display_list, head) {
1310
+ if (!state->is_init)
1311
+ continue;
1312
+ crtc_state = &state->crtc_state;
1313
+ crtc = crtc_state->crtc;
1314
+ crtc_funcs = crtc->funcs;
1315
+
1316
+ if (!cmd)
1317
+ ret = crtc_funcs->active_regs_dump(state);
1318
+ else if (!strcmp(cmd, "a") || !strcmp(cmd, "all"))
1319
+ ret = crtc_funcs->regs_dump(state);
1320
+ if (!ret)
1321
+ break;
1322
+ }
1323
+
1324
+ if (ret)
1325
+ ret = CMD_RET_USAGE;
1326
+
1327
+ return ret;
1328
+}
1329
+
14671330 enum {
14681331 PORT_DIR_IN,
14691332 PORT_DIR_OUT,
....@@ -1505,13 +1368,12 @@
15051368 return ofnode_to_np(parent);
15061369 }
15071370
1508
-static const struct device_node *rockchip_of_graph_get_remote_node(ofnode node, int port,
1509
- int endpoint)
1371
+const struct device_node *
1372
+rockchip_of_graph_get_endpoint_by_regs(ofnode node, int port, int endpoint)
15101373 {
15111374 const struct device_node *port_node;
15121375 ofnode ep;
15131376 u32 reg;
1514
- uint phandle;
15151377
15161378 port_node = rockchip_of_graph_get_port_by_id(node, port);
15171379 if (!port_node)
....@@ -1527,7 +1389,21 @@
15271389 if (!ofnode_valid(ep))
15281390 return NULL;
15291391
1530
- if (ofnode_read_u32(ep, "remote-endpoint", &phandle))
1392
+ return ofnode_to_np(ep);
1393
+}
1394
+
1395
+static const struct device_node *
1396
+rockchip_of_graph_get_remote_node(ofnode node, int port, int endpoint)
1397
+{
1398
+ const struct device_node *ep_node;
1399
+ ofnode ep;
1400
+ uint phandle;
1401
+
1402
+ ep_node = rockchip_of_graph_get_endpoint_by_regs(node, port, endpoint);
1403
+ if (!ep_node)
1404
+ return NULL;
1405
+
1406
+ if (ofnode_read_u32(np_to_ofnode(ep_node), "remote-endpoint", &phandle))
15311407 return NULL;
15321408
15331409 ep = ofnode_get_by_phandle(phandle);
....@@ -1611,6 +1487,10 @@
16111487 struct rockchip_bridge **bridge)
16121488 {
16131489 int ret = 0;
1490
+
1491
+ if (*panel)
1492
+ return 0;
1493
+
16141494 *panel = NULL;
16151495 *bridge = NULL;
16161496
....@@ -1952,7 +1832,9 @@
19521832
19531833 if (s->force_output) {
19541834 timing_node = ofnode_find_subnode(node, "force_timing");
1955
- ret = display_get_force_timing_from_dts(timing_node, &s->force_mode);
1835
+ ret = display_get_force_timing_from_dts(timing_node,
1836
+ &s->force_mode,
1837
+ &s->conn_state.bus_flags);
19561838 if (ofnode_read_u32(node, "force-bus-format", &s->force_bus_format))
19571839 s->force_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
19581840 }
....@@ -2002,10 +1884,11 @@
20021884 s->crtc_state.crtc->vps[vp_id].plane_mask = ret;
20031885 s->crtc_state.crtc->assign_plane |= true;
20041886 s->crtc_state.crtc->vps[vp_id].primary_plane_id =
2005
- ofnode_read_u32_default(vp_node, "rockchip,primary-plane", -1);
1887
+ ofnode_read_u32_default(vp_node, "rockchip,primary-plane", U8_MAX);
20061888 printf("get vp%d plane mask:0x%x, primary id:%d, cursor_plane:%d, from dts\n",
20071889 vp_id,
20081890 s->crtc_state.crtc->vps[vp_id].plane_mask,
1891
+ s->crtc_state.crtc->vps[vp_id].primary_plane_id == U8_MAX ? -1 :
20091892 s->crtc_state.crtc->vps[vp_id].primary_plane_id,
20101893 cursor_plane);
20111894 }
....@@ -2020,7 +1903,7 @@
20201903 }
20211904 }
20221905
2023
- get_crtc_mcu_mode(&s->crtc_state);
1906
+ get_crtc_mcu_mode(&s->crtc_state, port_node, is_ports_node);
20241907
20251908 ret = ofnode_read_u32_default(s->crtc_state.node,
20261909 "rockchip,dual-channel-swap", 0);
....@@ -2061,27 +1944,41 @@
20611944 const struct rockchip_crtc *crtc;
20621945 struct display_state *s;
20631946 int offset;
1947
+ int ret;
20641948 const struct device_node *np;
20651949 const char *path;
1950
+ const char *cacm_header;
1951
+ u64 aligned_memory_size;
20661952
20671953 if (fdt_node_offset_by_compatible(blob, 0, "rockchip,drm-logo") >= 0) {
2068
- list_for_each_entry(s, &rockchip_display_list, head)
2069
- load_bmp_logo(&s->logo, s->klogo_name);
1954
+ list_for_each_entry(s, &rockchip_display_list, head) {
1955
+ ret = load_bmp_logo(&s->logo, s->klogo_name);
1956
+ if (ret < 0) {
1957
+ s->is_klogo_valid = false;
1958
+ printf("VP%d fail to load kernel logo\n", s->crtc_state.crtc_id);
1959
+ } else {
1960
+ s->is_klogo_valid = true;
1961
+ }
1962
+ }
20701963
20711964 if (!get_display_size())
20721965 return;
20731966
1967
+ aligned_memory_size = (u64)ALIGN(get_display_size(), align_size);
20741968 offset = fdt_update_reserved_memory(blob, "rockchip,drm-logo",
20751969 (u64)memory_start,
2076
- (u64)get_display_size());
1970
+ aligned_memory_size);
20771971 if (offset < 0)
20781972 printf("failed to reserve drm-loader-logo memory\n");
20791973
2080
- offset = fdt_update_reserved_memory(blob, "rockchip,drm-cubic-lut",
2081
- (u64)cubic_lut_memory_start,
2082
- (u64)get_cubic_memory_size());
2083
- if (offset < 0)
2084
- printf("failed to reserve drm-cubic-lut memory\n");
1974
+ if (get_cubic_memory_size()) {
1975
+ aligned_memory_size = (u64)ALIGN(get_cubic_memory_size(), align_size);
1976
+ offset = fdt_update_reserved_memory(blob, "rockchip,drm-cubic-lut",
1977
+ (u64)cubic_lut_memory_start,
1978
+ aligned_memory_size);
1979
+ if (offset < 0)
1980
+ printf("failed to reserve drm-cubic-lut memory\n");
1981
+ }
20851982 } else {
20861983 printf("can't found rockchip,drm-logo, use rockchip,fb-logo\n");
20871984 /* Compatible with rkfb display, only need reserve memory */
....@@ -2097,7 +1994,14 @@
20971994 }
20981995
20991996 list_for_each_entry(s, &rockchip_display_list, head) {
2100
- if (!s->is_init)
1997
+ /*
1998
+ * If plane mask is not set in dts, fixup dts to assign it
1999
+ * whether crtc is initialized or not.
2000
+ */
2001
+ if (s->crtc_state.crtc->funcs->fixup_dts && !s->crtc_state.crtc->assign_plane)
2002
+ s->crtc_state.crtc->funcs->fixup_dts(s, blob);
2003
+
2004
+ if (!s->is_init || !s->is_klogo_valid)
21012005 continue;
21022006
21032007 conn = s->conn_state.connector;
....@@ -2123,9 +2027,6 @@
21232027 printf("failed to get exist crtc\n");
21242028 continue;
21252029 }
2126
-
2127
- if (crtc_funcs->fixup_dts)
2128
- crtc_funcs->fixup_dts(s, blob);
21292030
21302031 np = ofnode_to_np(s->node);
21312032 path = np->full_name;
....@@ -2155,10 +2056,37 @@
21552056 FDT_SET_U32("overscan,bottom_margin", s->conn_state.overscan.bottom_margin);
21562057
21572058 if (s->conn_state.disp_info) {
2059
+ cacm_header = (const char*)&s->conn_state.disp_info->cacm_header;
2060
+
21582061 FDT_SET_U32("bcsh,brightness", s->conn_state.disp_info->bcsh_info.brightness);
21592062 FDT_SET_U32("bcsh,contrast", s->conn_state.disp_info->bcsh_info.contrast);
21602063 FDT_SET_U32("bcsh,saturation", s->conn_state.disp_info->bcsh_info.saturation);
21612064 FDT_SET_U32("bcsh,hue", s->conn_state.disp_info->bcsh_info.hue);
2065
+
2066
+ if (!strncasecmp(cacm_header, "CACM", 4)) {
2067
+ FDT_SET_U32("post_csc,hue",
2068
+ s->conn_state.disp_info->csc_info.hue);
2069
+ FDT_SET_U32("post_csc,saturation",
2070
+ s->conn_state.disp_info->csc_info.saturation);
2071
+ FDT_SET_U32("post_csc,contrast",
2072
+ s->conn_state.disp_info->csc_info.contrast);
2073
+ FDT_SET_U32("post_csc,brightness",
2074
+ s->conn_state.disp_info->csc_info.brightness);
2075
+ FDT_SET_U32("post_csc,r_gain",
2076
+ s->conn_state.disp_info->csc_info.r_gain);
2077
+ FDT_SET_U32("post_csc,g_gain",
2078
+ s->conn_state.disp_info->csc_info.g_gain);
2079
+ FDT_SET_U32("post_csc,b_gain",
2080
+ s->conn_state.disp_info->csc_info.b_gain);
2081
+ FDT_SET_U32("post_csc,r_offset",
2082
+ s->conn_state.disp_info->csc_info.r_offset);
2083
+ FDT_SET_U32("post_csc,g_offset",
2084
+ s->conn_state.disp_info->csc_info.g_offset);
2085
+ FDT_SET_U32("post_csc,b_offset",
2086
+ s->conn_state.disp_info->csc_info.b_offset);
2087
+ FDT_SET_U32("post_csc,csc_enable",
2088
+ s->conn_state.disp_info->csc_info.csc_enable);
2089
+ }
21622090 }
21632091
21642092 if (s->conn_state.disp_info->cubic_lut_data.size &&
....@@ -2213,6 +2141,19 @@
22132141 return 0;
22142142 }
22152143
2144
+static int do_rockchip_vop_dump(cmd_tbl_t *cmdtp, int flag, int argc,
2145
+ char *const argv[])
2146
+{
2147
+ int ret;
2148
+
2149
+ if (argc < 1 || argc > 2)
2150
+ return CMD_RET_USAGE;
2151
+
2152
+ ret = rockchip_vop_dump(argv[1]);
2153
+
2154
+ return ret;
2155
+}
2156
+
22162157 U_BOOT_CMD(
22172158 rockchip_show_logo, 1, 1, do_rockchip_logo_show,
22182159 "load and display log from resource partition",
....@@ -2224,3 +2165,9 @@
22242165 "load and display bmp from resource partition",
22252166 " <bmp_name>"
22262167 );
2168
+
2169
+U_BOOT_CMD(
2170
+ vop_dump, 2, 1, do_rockchip_vop_dump,
2171
+ "dump vop regs",
2172
+ " [a/all]"
2173
+);
u-boot/drivers/video/drm/rockchip_display.h
....@@ -7,22 +7,37 @@
77 #ifndef _ROCKCHIP_DISPLAY_H
88 #define _ROCKCHIP_DISPLAY_H
99
10
+#ifdef CONFIG_SPL_BUILD
11
+#include <linux/hdmi.h>
12
+#include <linux/media-bus-format.h>
13
+#else
1014 #include <bmp_layout.h>
11
-#include <drm_modes.h>
1215 #include <edid.h>
16
+#endif
17
+#include <drm_modes.h>
1318 #include <dm/ofnode.h>
1419 #include <drm/drm_dsc.h>
20
+#include <spl_display.h>
21
+#include <clk.h>
1522
1623 /*
17
- * major: IP major vertion, used for IP structure
24
+ * major: IP major version, used for IP structure
1825 * minor: big feature change under same structure
26
+ * build: RTL current SVN number
1927 */
20
-#define VOP_VERSION(major, minor) ((major) << 8 | (minor))
21
-#define VOP_MAJOR(version) ((version) >> 8)
22
-#define VOP_MINOR(version) ((version) & 0xff)
28
+#define VOP_VERSION(major, minor) ((major) << 8 | (minor))
29
+#define VOP_MAJOR(version) ((version) >> 8)
30
+#define VOP_MINOR(version) ((version) & 0xff)
2331
24
-#define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15)
25
-#define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17)
32
+#define VOP2_VERSION(major, minor, build) ((major) << 24 | (minor) << 16 | (build))
33
+#define VOP2_MAJOR(version) (((version) >> 24) & 0xff)
34
+#define VOP2_MINOR(version) (((version) >> 16) & 0xff)
35
+#define VOP2_BUILD(version) ((version) & 0xffff)
36
+
37
+#define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263)
38
+#define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350)
39
+#define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023)
40
+#define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
2641
2742 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
2843 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
....@@ -66,6 +81,7 @@
6681 #define ROCKCHIP_OUT_MODE_P565 2
6782 #define ROCKCHIP_OUT_MODE_BT656 5
6883 #define ROCKCHIP_OUT_MODE_S888 8
84
+#define ROCKCHIP_OUT_MODE_YUV422 9
6985 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12
7086 #define ROCKCHIP_OUT_MODE_YUV420 14
7187 /* for use special outface */
....@@ -141,6 +157,7 @@
141157 void *private;
142158 ofnode node;
143159 struct device_node *ports_node; /* if (ports_node) it's vop2; */
160
+ struct clk dclk;
144161 int crtc_id;
145162
146163 int format;
....@@ -160,6 +177,7 @@
160177 bool post_y2r_en;
161178 bool bcsh_en;
162179 bool splice_mode;
180
+ bool soft_te;
163181 u8 splice_crtc_id;
164182 u8 dsc_id;
165183 u8 dsc_enable;
....@@ -198,6 +216,7 @@
198216 struct overscan overscan;
199217 u8 edid[EDID_SIZE * 4];
200218 int bus_format;
219
+ u32 bus_flags;
201220 int output_mode;
202221 int type;
203222 int output_if;
....@@ -223,6 +242,8 @@
223242 u64 dsc_cds_clk;
224243 struct rockchip_dsc_sink_cap dsc_sink_cap;
225244 struct drm_dsc_picture_parameter_set pps;
245
+
246
+ struct gpio_desc *te_gpio;
226247
227248 struct {
228249 u32 *lut;
....@@ -268,7 +289,9 @@
268289 int enable;
269290 int is_init;
270291 int is_enable;
292
+ bool is_klogo_valid;
271293 bool force_output;
294
+ bool enabled_at_spl;
272295 struct drm_display_mode force_mode;
273296 u32 force_bus_format;
274297 };
....@@ -282,11 +305,22 @@
282305 void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data,
283306 struct vop_rect *max_output);
284307 unsigned long get_cubic_lut_buffer(int crtc_id);
285
-int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode);
308
+int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode,
309
+ u32 *bus_flags);
310
+void rockchip_display_make_crc32_table(void);
311
+uint32_t rockchip_display_crc32c_cal(unsigned char *data, int length);
312
+void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags);
286313
287314 int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst,
288315 int min_hscale, int max_hscale);
289316 int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst,
290317 int min_vscale, int max_vscale);
318
+const struct device_node *
319
+rockchip_of_graph_get_endpoint_by_regs(ofnode node, int port, int endpoint);
291320
321
+#ifdef CONFIG_SPL_BUILD
322
+int rockchip_spl_vop_probe(struct crtc_state *crtc_state);
323
+int rockchip_spl_dw_hdmi_probe(struct connector_state *conn_state);
324
+int inno_spl_hdmi_phy_probe(struct display_state *state);
325
+#endif
292326 #endif
u-boot/drivers/video/drm/rockchip_display_helper.c
....@@ -0,0 +1,279 @@
1
+/*
2
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+
7
+#include <linux/hdmi.h>
8
+#include <linux/compat.h>
9
+#include "rockchip_display.h"
10
+#include <spl_display.h>
11
+
12
+#define RK_BLK_SIZE 512
13
+#define BMP_PROCESSED_FLAG 8399
14
+
15
+static uint32_t crc32_table[256];
16
+
17
+void rockchip_display_make_crc32_table(void)
18
+{
19
+ uint32_t c;
20
+ int n, k;
21
+ unsigned long poly; /* polynomial exclusive-or pattern */
22
+ /* terms of polynomial defining this crc (except x^32): */
23
+ static const char p[] = {0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26};
24
+
25
+ /* make exclusive-or pattern from polynomial (0xedb88320L) */
26
+ poly = 0L;
27
+ for (n = 0; n < sizeof(p) / sizeof(char); n++)
28
+ poly |= 1L << (31 - p[n]);
29
+
30
+ for (n = 0; n < 256; n++) {
31
+ c = (unsigned long)n;
32
+ for (k = 0; k < 8; k++)
33
+ c = c & 1 ? poly ^ (c >> 1) : c >> 1;
34
+ crc32_table[n] = cpu_to_le32(c);
35
+ }
36
+}
37
+
38
+uint32_t rockchip_display_crc32c_cal(unsigned char *data, int length)
39
+{
40
+ int i;
41
+ uint32_t crc;
42
+ crc = 0xFFFFFFFF;
43
+
44
+ for (i = 0; i < length; i++) {
45
+ crc = crc32_table[(crc ^ *data) & 0xff] ^ (crc >> 8);
46
+ data++;
47
+ }
48
+
49
+ return crc ^ 0xffffffff;
50
+}
51
+
52
+/**
53
+ * drm_mode_max_resolution_filter - mark modes out of vop max resolution
54
+ * @edid_data: structure store mode list
55
+ * @max_output: vop max output resolution
56
+ */
57
+void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data,
58
+ struct vop_rect *max_output)
59
+{
60
+ int i;
61
+
62
+ for (i = 0; i < edid_data->modes; i++) {
63
+ if (edid_data->mode_buf[i].hdisplay > max_output->width ||
64
+ edid_data->mode_buf[i].vdisplay > max_output->height)
65
+ edid_data->mode_buf[i].invalid = true;
66
+ }
67
+}
68
+
69
+int drm_mode_vrefresh(const struct drm_display_mode *mode)
70
+{
71
+ int refresh = 0;
72
+ unsigned int calc_val;
73
+
74
+ if (mode->vrefresh > 0) {
75
+ refresh = mode->vrefresh;
76
+ } else if (mode->htotal > 0 && mode->vtotal > 0) {
77
+ int vtotal;
78
+
79
+ vtotal = mode->vtotal;
80
+ /* work out vrefresh the value will be x1000 */
81
+ calc_val = (mode->clock * 1000);
82
+ calc_val /= mode->htotal;
83
+ refresh = (calc_val + vtotal / 2) / vtotal;
84
+
85
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
86
+ refresh *= 2;
87
+ if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
88
+ refresh /= 2;
89
+ if (mode->vscan > 1)
90
+ refresh /= mode->vscan;
91
+ }
92
+ return refresh;
93
+}
94
+
95
+/**
96
+ * drm_mode_set_crtcinfo - set CRTC modesetting timing parameters
97
+ * @p: mode
98
+ * @adjust_flags: a combination of adjustment flags
99
+ *
100
+ * Setup the CRTC modesetting timing parameters for @p, adjusting if necessary.
101
+ *
102
+ * - The CRTC_INTERLACE_HALVE_V flag can be used to halve vertical timings of
103
+ * interlaced modes.
104
+ * - The CRTC_STEREO_DOUBLE flag can be used to compute the timings for
105
+ * buffers containing two eyes (only adjust the timings when needed, eg. for
106
+ * "frame packing" or "side by side full").
107
+ * - The CRTC_NO_DBLSCAN and CRTC_NO_VSCAN flags request that adjustment *not*
108
+ * be performed for doublescan and vscan > 1 modes respectively.
109
+ */
110
+void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags)
111
+{
112
+ if ((p == NULL) || ((p->type & DRM_MODE_TYPE_CRTC_C) == DRM_MODE_TYPE_BUILTIN))
113
+ return;
114
+
115
+ if (p->flags & DRM_MODE_FLAG_DBLCLK)
116
+ p->crtc_clock = 2 * p->clock;
117
+ else
118
+ p->crtc_clock = p->clock;
119
+ p->crtc_hdisplay = p->hdisplay;
120
+ p->crtc_hsync_start = p->hsync_start;
121
+ p->crtc_hsync_end = p->hsync_end;
122
+ p->crtc_htotal = p->htotal;
123
+ p->crtc_hskew = p->hskew;
124
+ p->crtc_vdisplay = p->vdisplay;
125
+ p->crtc_vsync_start = p->vsync_start;
126
+ p->crtc_vsync_end = p->vsync_end;
127
+ p->crtc_vtotal = p->vtotal;
128
+
129
+ if (p->flags & DRM_MODE_FLAG_INTERLACE) {
130
+ if (adjust_flags & CRTC_INTERLACE_HALVE_V) {
131
+ p->crtc_vdisplay /= 2;
132
+ p->crtc_vsync_start /= 2;
133
+ p->crtc_vsync_end /= 2;
134
+ p->crtc_vtotal /= 2;
135
+ }
136
+ }
137
+
138
+ if (!(adjust_flags & CRTC_NO_DBLSCAN)) {
139
+ if (p->flags & DRM_MODE_FLAG_DBLSCAN) {
140
+ p->crtc_vdisplay *= 2;
141
+ p->crtc_vsync_start *= 2;
142
+ p->crtc_vsync_end *= 2;
143
+ p->crtc_vtotal *= 2;
144
+ }
145
+ }
146
+
147
+ if (!(adjust_flags & CRTC_NO_VSCAN)) {
148
+ if (p->vscan > 1) {
149
+ p->crtc_vdisplay *= p->vscan;
150
+ p->crtc_vsync_start *= p->vscan;
151
+ p->crtc_vsync_end *= p->vscan;
152
+ p->crtc_vtotal *= p->vscan;
153
+ }
154
+ }
155
+
156
+ if (adjust_flags & CRTC_STEREO_DOUBLE) {
157
+ unsigned int layout = p->flags & DRM_MODE_FLAG_3D_MASK;
158
+
159
+ switch (layout) {
160
+ case DRM_MODE_FLAG_3D_FRAME_PACKING:
161
+ p->crtc_clock *= 2;
162
+ p->crtc_vdisplay += p->crtc_vtotal;
163
+ p->crtc_vsync_start += p->crtc_vtotal;
164
+ p->crtc_vsync_end += p->crtc_vtotal;
165
+ p->crtc_vtotal += p->crtc_vtotal;
166
+ break;
167
+ }
168
+ }
169
+
170
+ p->crtc_vblank_start = min(p->crtc_vsync_start, p->crtc_vdisplay);
171
+ p->crtc_vblank_end = max(p->crtc_vsync_end, p->crtc_vtotal);
172
+ p->crtc_hblank_start = min(p->crtc_hsync_start, p->crtc_hdisplay);
173
+ p->crtc_hblank_end = max(p->crtc_hsync_end, p->crtc_htotal);
174
+}
175
+
176
+/**
177
+ * drm_mode_is_420_only - if a given videomode can be only supported in YCBCR420
178
+ * output format
179
+ *
180
+ * @connector: drm connector under action.
181
+ * @mode: video mode to be tested.
182
+ *
183
+ * Returns:
184
+ * true if the mode can be supported in YCBCR420 format
185
+ * false if not.
186
+ */
187
+static bool drm_mode_is_420_only(const struct drm_display_info *display,
188
+ struct drm_display_mode *mode)
189
+{
190
+ u8 vic = drm_match_cea_mode(mode);
191
+
192
+ return test_bit(vic, display->hdmi.y420_vdb_modes);
193
+}
194
+
195
+/**
196
+ * drm_mode_is_420_also - if a given videomode can be supported in YCBCR420
197
+ * output format also (along with RGB/YCBCR444/422)
198
+ *
199
+ * @display: display under action.
200
+ * @mode: video mode to be tested.
201
+ *
202
+ * Returns:
203
+ * true if the mode can be support YCBCR420 format
204
+ * false if not.
205
+ */
206
+static bool drm_mode_is_420_also(const struct drm_display_info *display,
207
+ struct drm_display_mode *mode)
208
+{
209
+ u8 vic = drm_match_cea_mode(mode);
210
+
211
+ return test_bit(vic, display->hdmi.y420_cmdb_modes);
212
+}
213
+
214
+/**
215
+ * drm_mode_is_420 - if a given videomode can be supported in YCBCR420
216
+ * output format
217
+ *
218
+ * @display: display under action.
219
+ * @mode: video mode to be tested.
220
+ *
221
+ * Returns:
222
+ * true if the mode can be supported in YCBCR420 format
223
+ * false if not.
224
+ */
225
+bool drm_mode_is_420(const struct drm_display_info *display,
226
+ struct drm_display_mode *mode)
227
+{
228
+ return drm_mode_is_420_only(display, mode) ||
229
+ drm_mode_is_420_also(display, mode);
230
+}
231
+
232
+static int display_rect_calc_scale(int src, int dst)
233
+{
234
+ int scale = 0;
235
+
236
+ if (WARN_ON(src < 0 || dst < 0))
237
+ return -EINVAL;
238
+
239
+ if (dst == 0)
240
+ return 0;
241
+
242
+ src <<= 16;
243
+
244
+ if (src > (dst << 16))
245
+ return DIV_ROUND_UP(src, dst);
246
+ else
247
+ scale = src / dst;
248
+
249
+ return scale;
250
+}
251
+
252
+int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst,
253
+ int min_hscale, int max_hscale)
254
+{
255
+ int hscale = display_rect_calc_scale(src->w, dst->w);
256
+
257
+ if (hscale < 0 || dst->w == 0)
258
+ return hscale;
259
+
260
+ if (hscale < min_hscale || hscale > max_hscale)
261
+ return -ERANGE;
262
+
263
+ return hscale;
264
+}
265
+
266
+int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst,
267
+ int min_vscale, int max_vscale)
268
+{
269
+ int vscale = display_rect_calc_scale(src->h, dst->h);
270
+
271
+ if (vscale < 0 || dst->h == 0)
272
+ return vscale;
273
+
274
+ if (vscale < min_vscale || vscale > max_vscale)
275
+ return -ERANGE;
276
+
277
+ return vscale;
278
+}
279
+
u-boot/drivers/video/drm/rockchip_drm_tve.c
deleted file mode 100644
....@@ -1,578 +0,0 @@
1
-/*
2
- * SPDX-License-Identifier: GPL-2.0+
3
- * (C) Copyright 2008-2015 Fuzhou Rockchip Electronics Co., Ltd
4
- */
5
-#include <common.h>
6
-#include <malloc.h>
7
-#include <fdtdec.h>
8
-#include <fdt_support.h>
9
-#include <asm/io.h>
10
-#include <linux/media-bus-format.h>
11
-#include <asm/arch-rockchip/clock.h>
12
-#include <dm/device.h>
13
-#include <dm/read.h>
14
-#include <dm/uclass-internal.h>
15
-#include <linux/fb.h>
16
-#include <edid.h>
17
-#include <syscon.h>
18
-#include <boot_rkimg.h>
19
-#include <mapmem.h>
20
-#include <misc.h>
21
-#include "rockchip_drm_tve.h"
22
-#include "rockchip_display.h"
23
-#include "rockchip_crtc.h"
24
-#include "rockchip_connector.h"
25
-#include "rockchip_phy.h"
26
-
27
-DECLARE_GLOBAL_DATA_PTR;
28
-
29
-static struct drm_tve tve_s;
30
-
31
-#define tve_writel(offset, v) writel(v, tve_s.reg_phy_base + offset)
32
-#define tve_readl(offset) readl(tve_s.reg_phy_base + offset)
33
-
34
-#define tve_dac_writel(offset, v) writel(v, tve_s.vdacbase + offset)
35
-#define tve_dac_readl(offset) readl(tve_s.vdacbase + offset)
36
-
37
-#define RK322X_VDAC_STANDARD 0x15
38
-
39
-#define TVE_REG_NUM 0x28
40
-
41
-static const struct drm_display_mode tve_modes[] = {
42
- /* 0 - 720x576i@50Hz */
43
- { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 753,
44
- 816, 864, 576, 580, 586, 625, 0,
45
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
46
- DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
47
- .vrefresh = 50, },
48
- /* 1 - 720x480i@60Hz */
49
- { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 753,
50
- 815, 858, 480, 480, 486, 525, 0,
51
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
52
- DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
53
- .vrefresh = 60, },
54
-};
55
-
56
-static void dac_enable(int enable)
57
-{
58
- u32 mask, val = 0;
59
- u32 grfreg = 0;
60
-
61
-#if defined(CONFIG_ROCKCHIP_RK322X) || defined(CONFIG_ROCKCHIP_RK3328)
62
- tve_dac_writel(VDAC_VDAC2, v_CUR_CTR(tve_s.daclevel));
63
- tve_dac_writel(VDAC_VDAC3, v_CAB_EN(0));
64
-#endif
65
- if (enable) {
66
- mask = m_VBG_EN | m_DAC_EN | m_DAC_GAIN;
67
-#if defined(CONFIG_ROCKCHIP_RK3128)
68
- val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(tve_s.daclevel);
69
- grfreg = GRF_TVE_CON0;
70
-#elif defined(CONFIG_ROCKCHIP_RK3036)
71
- val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(tve_s.daclevel);
72
- grfreg = GRF_SOC_CON3;
73
-#endif
74
- val |= mask << 16;
75
-
76
-#if defined(CONFIG_ROCKCHIP_RK322X) || defined(CONFIG_ROCKCHIP_RK3328)
77
- val = v_CUR_REG(tve_s.dac1level) |
78
- v_DR_PWR_DOWN(0) | v_BG_PWR_DOWN(0);
79
-#endif
80
- } else {
81
- mask = m_VBG_EN | m_DAC_EN;
82
- val = 0;
83
-#if defined(CONFIG_ROCKCHIP_RK3128)
84
- grfreg = GRF_TVE_CON0;
85
-#elif defined(CONFIG_ROCKCHIP_RK3036)
86
- grfreg = GRF_SOC_CON3;
87
-#endif
88
- val |= mask << 16;
89
-
90
-#if defined(CONFIG_ROCKCHIP_RK322X) || defined(CONFIG_ROCKCHIP_RK3328)
91
- val = v_CUR_REG(tve_s.dac1level) |
92
- m_DR_PWR_DOWN | m_BG_PWR_DOWN;
93
- #endif
94
- }
95
-
96
- if (grfreg)
97
- writel(val, tve_s.grf + grfreg);
98
- else if (tve_s.vdacbase)
99
- tve_dac_writel(VDAC_VDAC1, val);
100
-}
101
-
102
-static void tve_set_mode(int mode)
103
-{
104
- if (tve_s.soctype != SOC_RK322X &&
105
- tve_s.soctype != SOC_RK322XH) {
106
- tve_writel(TV_RESET, v_RESET(1));
107
- udelay(100);
108
- tve_writel(TV_RESET, v_RESET(0));
109
- }
110
-
111
- if (tve_s.soctype == SOC_RK3036)
112
- tve_writel(TV_CTRL, v_CVBS_MODE(mode) | v_CLK_UPSTREAM_EN(2) |
113
- v_TIMING_EN(2) | v_LUMA_FILTER_GAIN(0) |
114
- v_LUMA_FILTER_UPSAMPLE(1) | v_CSC_PATH(0));
115
- else
116
- tve_writel(TV_CTRL, v_CVBS_MODE(mode) | v_CLK_UPSTREAM_EN(2) |
117
- v_TIMING_EN(2) | v_LUMA_FILTER_GAIN(0) |
118
- v_LUMA_FILTER_UPSAMPLE(1) | v_CSC_PATH(3));
119
-
120
- tve_writel(TV_LUMA_FILTER0, tve_s.lumafilter0);
121
- tve_writel(TV_LUMA_FILTER1, tve_s.lumafilter1);
122
- tve_writel(TV_LUMA_FILTER2, tve_s.lumafilter2);
123
-
124
- if (mode == TVOUT_CVBS_NTSC) {
125
- tve_writel(TV_ROUTING, v_DAC_SENSE_EN(0) | v_Y_IRE_7_5(1) |
126
- v_Y_AGC_PULSE_ON(1) | v_Y_VIDEO_ON(1) |
127
- v_Y_SYNC_ON(1) | v_PIC_MODE(mode));
128
- tve_writel(TV_BW_CTRL, v_CHROMA_BW(BP_FILTER_NTSC) |
129
- v_COLOR_DIFF_BW(COLOR_DIFF_FILTER_BW_1_3));
130
- tve_writel(TV_SATURATION, 0x0052543C);
131
- if (tve_s.test_mode)
132
- tve_writel(TV_BRIGHTNESS_CONTRAST, 0x00008300);
133
- else
134
- tve_writel(TV_BRIGHTNESS_CONTRAST, 0x00007900);
135
-
136
- tve_writel(TV_FREQ_SC, 0x21F07BD7);
137
- tve_writel(TV_SYNC_TIMING, 0x00C07a81);
138
- tve_writel(TV_ADJ_TIMING, 0x96B40000);
139
- tve_writel(TV_ACT_ST, 0x001500D6);
140
- tve_writel(TV_ACT_TIMING, 0x169800FC | (1 << 12) | (1 << 28));
141
-
142
- } else if (mode == TVOUT_CVBS_PAL) {
143
- tve_writel(TV_ROUTING, v_DAC_SENSE_EN(0) | v_Y_IRE_7_5(0) |
144
- v_Y_AGC_PULSE_ON(0) | v_Y_VIDEO_ON(1) |
145
- v_YPP_MODE(1) | v_Y_SYNC_ON(1) | v_PIC_MODE(mode));
146
- tve_writel(TV_BW_CTRL, v_CHROMA_BW(BP_FILTER_PAL) |
147
- v_COLOR_DIFF_BW(COLOR_DIFF_FILTER_BW_1_3));
148
-
149
- tve_writel(TV_SATURATION, tve_s.saturation);
150
- tve_writel(TV_BRIGHTNESS_CONTRAST, tve_s.brightcontrast);
151
-
152
- tve_writel(TV_FREQ_SC, 0x2A098ACB);
153
- tve_writel(TV_SYNC_TIMING, 0x00C28381);
154
- tve_writel(TV_ADJ_TIMING, (0xc << 28) | 0x06c00800 | 0x80);
155
- tve_writel(TV_ACT_ST, 0x001500F6);
156
- tve_writel(TV_ACT_TIMING, 0x0694011D | (1 << 12) | (2 << 28));
157
-
158
- tve_writel(TV_ADJ_TIMING, tve_s.adjtiming);
159
- tve_writel(TV_ACT_TIMING, 0x0694011D | (1 << 12) | (2 << 28));
160
- }
161
-}
162
-
163
-static u8 rk_get_vdac_value(void)
164
-{
165
- u8 value = 0;
166
-#ifdef CONFIG_ROCKCHIP_EFUSE
167
-#if defined(CONFIG_ROCKCHIP_RK322X)
168
- struct udevice *dev;
169
- u32 regs[2] = {0};
170
- u8 fuses[1];
171
- ofnode node;
172
- int ret;
173
-
174
- ret = uclass_get_device_by_driver(UCLASS_MISC,
175
- DM_GET_DRIVER(rockchip_efuse), &dev);
176
- if (ret) {
177
- printf("%s: no misc-device found\n", __func__);
178
- return -EINVAL;
179
- }
180
-
181
- node = dev_read_subnode(dev, "tve_dac");
182
- if (!ofnode_valid(node))
183
- return -EINVAL;
184
-
185
- ret = ofnode_read_u32_array(node, "reg", regs, 2);
186
- if (ret) {
187
- printf("Cannot get efuse reg\n");
188
- return -EINVAL;
189
- }
190
-
191
- ret = misc_read(dev, regs[0], &fuses, regs[1]);
192
- if (ret) {
193
- printf("%s: misc_read failed\n", __func__);
194
- return 0;
195
- }
196
-
197
- value = fuses[0];
198
- value = (value >> 3) & 0x1f;
199
-#endif
200
-#endif /* CONFIG_RK_EFUSE */
201
- if (value > 0)
202
- value += 5;
203
- TVEDBG("%s value = 0x%x\n", __func__, value);
204
-
205
- return value;
206
-}
207
-
208
-static int rockchip_drm_tve_init(struct rockchip_connector *conn, struct display_state *state)
209
-{
210
- int node = 0;
211
- int dac_value, getvdac;
212
- fdt_addr_t addr;
213
-
214
- tve_s.grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
215
- if (tve_s.grf <= 0) {
216
- printf("%s:Get syscon grf failed (ret=%p)\n",
217
- __func__, tve_s.grf);
218
- return -ENXIO;
219
- }
220
-
221
-#if defined(CONFIG_ROCKCHIP_RK3036)
222
- addr = dev_read_addr_index(conn->dev, 0);
223
- if (addr == FDT_ADDR_T_NONE)
224
- return -EINVAL;
225
-
226
- tve_s.reg_phy_base = (void *)addr;
227
- tve_s.soctype = SOC_RK3036;
228
- node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
229
- "rockchip,rk3036-tve");
230
- if (node < 0) {
231
- printf("can't find dts node for rk3036-tve\n");
232
- goto err;
233
- }
234
-#elif defined(CONFIG_ROCKCHIP_RK3128)
235
- addr = dev_read_addr_index(conn->dev, 0);
236
- if (addr == FDT_ADDR_T_NONE)
237
- return -EINVAL;
238
-
239
- tve_s.reg_phy_base = (void *)addr;
240
- tve_s.soctype = SOC_RK312X;
241
- tve_s.saturation = 0;
242
- node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
243
- "rockchip,rk312x-tve");
244
- if (node < 0) {
245
- printf("can't find dts node for rk312x-tve\n");
246
- goto err;
247
- }
248
-#elif defined(CONFIG_ROCKCHIP_RK322X)
249
- addr = dev_read_addr_index(conn->dev, 0);
250
- if (addr == FDT_ADDR_T_NONE)
251
- return -EINVAL;
252
-
253
- tve_s.reg_phy_base = (void *)addr;
254
- tve_s.soctype = SOC_RK322X;
255
- tve_s.saturation = 0;
256
-
257
- addr = dev_read_addr_index(conn->dev, 1);
258
- if (addr == FDT_ADDR_T_NONE)
259
- return -EINVAL;
260
- tve_s.vdacbase = (void *)addr;
261
- node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
262
- "rockchip,rk3328-tve");
263
- if (node < 0) {
264
- printf("can't find dts node for rk322x-tve\n");
265
- goto err;
266
- }
267
-#elif defined(CONFIG_ROCKCHIP_RK3328)
268
- addr = dev_read_addr_index(conn->dev, 0);
269
- if (addr == FDT_ADDR_T_NONE)
270
- return -EINVAL;
271
-
272
- tve_s.reg_phy_base = (void *)addr;
273
- tve_s.soctype = SOC_RK322XH;
274
-
275
- addr = dev_read_addr_index(conn->dev, 1);
276
- if (addr == FDT_ADDR_T_NONE)
277
- return -EINVAL;
278
- tve_s.vdacbase = (void *)addr;
279
-
280
- node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
281
- "rockchip,rk3328-tve");
282
- if (node < 0) {
283
- printf("can't find dts node for rk322xh-tve\n");
284
- goto err;
285
- }
286
-#endif
287
-
288
- if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) {
289
- printf("tve is disabled\n");
290
- goto err;
291
- }
292
-
293
- if (tve_s.soctype == SOC_RK312X)
294
- tve_s.test_mode = fdtdec_get_int(gd->fdt_blob, node,
295
- "test_mode", 0);
296
-
297
- tve_s.preferred_mode = fdtdec_get_int(gd->fdt_blob, node,
298
- "rockchip,tvemode", -1);
299
- if (tve_s.preferred_mode < 0) {
300
- tve_s.preferred_mode = 0;
301
- } else if (tve_s.preferred_mode > 1) {
302
- printf("tve mode value invalid\n");
303
- goto err;
304
- }
305
-
306
- tve_s.saturation = fdtdec_get_int(gd->fdt_blob, node,
307
- "rockchip,saturation", 0);
308
- if (tve_s.saturation == 0) {
309
- printf("tve saturation err\n");
310
- goto err;
311
- }
312
-
313
- tve_s.brightcontrast = fdtdec_get_int(gd->fdt_blob, node,
314
- "rockchip,brightcontrast", 0);
315
- if (tve_s.brightcontrast == 0) {
316
- printf("tve brightcontrast err\n");
317
- goto err;
318
- }
319
-
320
- tve_s.adjtiming = fdtdec_get_int(gd->fdt_blob, node,
321
- "rockchip,adjtiming", 0);
322
- if (tve_s.adjtiming == 0) {
323
- printf("tve adjtiming err\n");
324
- goto err;
325
- }
326
-
327
- tve_s.lumafilter0 = fdtdec_get_int(gd->fdt_blob, node,
328
- "rockchip,lumafilter0", 0);
329
- if (tve_s.lumafilter0 == 0) {
330
- printf("tve lumafilter0 err\n");
331
- goto err;
332
- }
333
-
334
- tve_s.lumafilter1 = fdtdec_get_int(gd->fdt_blob, node,
335
- "rockchip,lumafilter1", 0);
336
- if (tve_s.lumafilter1 == 0) {
337
- printf("tve lumafilter1 err\n");
338
- goto err;
339
- }
340
-
341
- tve_s.lumafilter2 = fdtdec_get_int(gd->fdt_blob, node,
342
- "rockchip,lumafilter2", 0);
343
- if (tve_s.lumafilter2 == 0) {
344
- printf("tve lumafilter2 err\n");
345
- goto err;
346
- }
347
-
348
- dac_value = fdtdec_get_int(gd->fdt_blob, node, "rockchip,daclevel", 0);
349
- if (dac_value == 0) {
350
- printf("tve dac_value err\n");
351
- goto err;
352
- }
353
-
354
- tve_s.daclevel = dac_value;
355
- if (tve_s.soctype == SOC_RK322X) {
356
- getvdac = rk_get_vdac_value();
357
- if (getvdac > 0) {
358
- tve_s.daclevel =
359
- dac_value + getvdac - RK322X_VDAC_STANDARD;
360
- if (tve_s.daclevel > 0x3f ||
361
- tve_s.daclevel < 0) {
362
- printf("rk322x daclevel error!\n");
363
- tve_s.daclevel = dac_value;
364
- }
365
- } else if (getvdac < 0) {
366
- printf("get rk322x daclevel error\n");
367
- goto err;
368
- }
369
- }
370
-
371
- if (tve_s.soctype == SOC_RK322X ||
372
- tve_s.soctype == SOC_RK322XH) {
373
- tve_s.dac1level = fdtdec_get_int(gd->fdt_blob, node,
374
- "rockchip,dac1level", 0);
375
- if (tve_s.dac1level == 0) {
376
- printf("rk322x dac1level error!\n");
377
- goto err;
378
- }
379
- }
380
- TVEDBG("tve_s.test_mode = 0x%x\n", tve_s.test_mode);
381
- TVEDBG("tve_s.saturation = 0x%x\n", tve_s.saturation);
382
- TVEDBG("tve_s.brightcontrast = 0x%x\n", tve_s.brightcontrast);
383
- TVEDBG("tve_s.adjtiming = 0x%x\n", tve_s.adjtiming);
384
- TVEDBG("tve_s.lumafilter0 = 0x%x\n", tve_s.lumafilter0);
385
- TVEDBG("tve_s.lumafilter1 = 0x%x\n", tve_s.lumafilter1);
386
- TVEDBG("tve_s.lumafilter2 = 0x%x\n", tve_s.lumafilter2);
387
- TVEDBG("tve_s.daclevel = 0x%x\n", tve_s.daclevel);
388
-
389
- return 0;
390
-
391
-err:
392
- dac_enable(0);
393
- return -ENODEV;
394
-}
395
-
396
-static int rockchip_drm_tve_enable(struct rockchip_connector *conn, struct display_state *state)
397
-{
398
- struct connector_state *conn_state = &state->conn_state;
399
- struct drm_display_mode *mode = &conn_state->mode;
400
- int tve_type;
401
-
402
-#ifdef CONFIG_ROCKCHIP_INNO_HDMI_PHY
403
- /* set inno hdmi phy clk. */
404
- rockchip_phy_set_pll(conn->phy, 27000000);
405
-#endif
406
- if (mode->vdisplay == 576)
407
- tve_type = TVOUT_CVBS_PAL;
408
- else
409
- tve_type = TVOUT_CVBS_NTSC;
410
- dac_enable(0);
411
- tve_set_mode(tve_type);
412
- dac_enable(1);
413
-
414
- return 0;
415
-}
416
-
417
-static void rockchip_drm_tve_deinit(struct rockchip_connector *conn, struct display_state *state)
418
-{
419
- dac_enable(0);
420
-}
421
-
422
-static int rockchip_drm_tve_prepare(struct rockchip_connector *conn, struct display_state *state)
423
-{
424
- return 0;
425
-}
426
-
427
-static int rockchip_drm_tve_disable(struct rockchip_connector *conn, struct display_state *state)
428
-{
429
- dac_enable(0);
430
- return 0;
431
-}
432
-
433
-static int rockchip_drm_tve_detect(struct rockchip_connector *conn, struct display_state *state)
434
-{
435
- return 1;
436
-}
437
-
438
-static void drm_tve_selete_output(struct overscan *overscan,
439
- struct drm_display_mode *mode)
440
-{
441
- int ret, i, screen_size;
442
- struct base_screen_info *screen_info = NULL;
443
- struct base_disp_info base_parameter;
444
- struct drm_display_mode modes[2];
445
- const struct base_overscan *scan;
446
- char baseparameter_buf[8 * RK_BLK_SIZE] __aligned(ARCH_DMA_MINALIGN);
447
- struct blk_desc *dev_desc;
448
- disk_partition_t part_info;
449
- int max_scan = 100;
450
- int min_scan = 50;
451
-
452
- overscan->left_margin = max_scan;
453
- overscan->right_margin = max_scan;
454
- overscan->top_margin = max_scan;
455
- overscan->bottom_margin = max_scan;
456
-
457
- for (i = 0; i < 2; i++) {
458
- modes[i] = tve_modes[i];
459
- if (i == tve_s.preferred_mode)
460
- modes[i].type |= DRM_MODE_TYPE_PREFERRED;
461
- }
462
- *mode = modes[tve_s.preferred_mode];
463
-
464
- dev_desc = rockchip_get_bootdev();
465
- if (!dev_desc) {
466
- printf("%s: Could not find device\n", __func__);
467
- return;
468
- }
469
-
470
- if (part_get_info_by_name(dev_desc, "baseparameter", &part_info) < 0) {
471
- printf("Could not find baseparameter partition\n");
472
- return;
473
- }
474
-
475
- ret = blk_dread(dev_desc, part_info.start, 1,
476
- (void *)baseparameter_buf);
477
- if (ret < 0) {
478
- printf("read baseparameter failed\n");
479
- return;
480
- }
481
-
482
- memcpy(&base_parameter, baseparameter_buf, sizeof(base_parameter));
483
- scan = &base_parameter.scan;
484
-
485
- screen_size = sizeof(base_parameter.screen_list) /
486
- sizeof(base_parameter.screen_list[0]);
487
-
488
- for (i = 0; i < screen_size; i++) {
489
- if (base_parameter.screen_list[i].type ==
490
- DRM_MODE_CONNECTOR_TV) {
491
- screen_info = &base_parameter.screen_list[i];
492
- break;
493
- }
494
- }
495
-
496
- if (scan->leftscale < min_scan && scan->leftscale > 0)
497
- overscan->left_margin = min_scan;
498
- else if (scan->leftscale < max_scan)
499
- overscan->left_margin = scan->leftscale;
500
-
501
- if (scan->rightscale < min_scan && scan->rightscale > 0)
502
- overscan->right_margin = min_scan;
503
- else if (scan->rightscale < max_scan)
504
- overscan->right_margin = scan->rightscale;
505
-
506
- if (scan->topscale < min_scan && scan->topscale > 0)
507
- overscan->top_margin = min_scan;
508
- else if (scan->topscale < max_scan)
509
- overscan->top_margin = scan->topscale;
510
-
511
- if (scan->bottomscale < min_scan && scan->bottomscale > 0)
512
- overscan->bottom_margin = min_scan;
513
- else if (scan->bottomscale < max_scan)
514
- overscan->bottom_margin = scan->bottomscale;
515
-
516
- if (screen_info &&
517
- (screen_info->mode.hdisplay == 720 &&
518
- screen_info->mode.vdisplay == 576 &&
519
- screen_info->mode.hsync_start == 753 &&
520
- screen_info->mode.hsync_end == 816))
521
- *mode = modes[0];
522
- else if (screen_info &&
523
- screen_info->mode.vdisplay == 480 &&
524
- screen_info->mode.vsync_start == 480 &&
525
- screen_info->mode.vsync_end == 486)
526
- *mode = modes[1];
527
-
528
- if (screen_info)
529
- printf("base_parameter.mode:%dx%d\n",
530
- screen_info->mode.hdisplay,
531
- screen_info->mode.vdisplay);
532
-}
533
-
534
-static int rockchip_drm_tve_get_timing(struct rockchip_connector *conn, struct display_state *state)
535
-{
536
- struct connector_state *conn_state = &state->conn_state;
537
- struct drm_display_mode *mode = &conn_state->mode;
538
-
539
- conn_state->output_mode = ROCKCHIP_OUT_MODE_P888;
540
- conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24;
541
- drm_tve_selete_output(&conn_state->overscan, mode);
542
-
543
- return 0;
544
-}
545
-
546
-const struct rockchip_connector_funcs rockchip_drm_tve_funcs = {
547
- .init = rockchip_drm_tve_init,
548
- .deinit = rockchip_drm_tve_deinit,
549
- .prepare = rockchip_drm_tve_prepare,
550
- .enable = rockchip_drm_tve_enable,
551
- .disable = rockchip_drm_tve_disable,
552
- .get_timing = rockchip_drm_tve_get_timing,
553
- .detect = rockchip_drm_tve_detect,
554
-};
555
-
556
-static int rockchip_drm_tve_probe(struct udevice *dev)
557
-{
558
- struct rockchip_connector *conn = dev_get_priv(dev);
559
-
560
- rockchip_connector_bind(conn, dev, 0, &rockchip_drm_tve_funcs, NULL,
561
- DRM_MODE_CONNECTOR_TV);
562
-
563
- return 0;
564
-}
565
-
566
-static const struct udevice_id rockchip_drm_tve_ids[] = {
567
- {
568
- .compatible = "rockchip,rk3328-tve",
569
- }, {}
570
-};
571
-
572
-U_BOOT_DRIVER(rockchip_drm_tve) = {
573
- .name = "rockchip_drm_tve",
574
- .id = UCLASS_DISPLAY,
575
- .of_match = rockchip_drm_tve_ids,
576
- .probe = rockchip_drm_tve_probe,
577
- .priv_auto_alloc_size = sizeof(struct rockchip_connector),
578
-};
u-boot/drivers/video/drm/rockchip_drm_tve.h
deleted file mode 100644
....@@ -1,153 +0,0 @@
1
-/*
2
- * SPDX-License-Identifier: GPL-2.0+
3
- * (C) Copyright 2008-2015 Fuzhou Rockchip Electronics Co., Ltd
4
- */
5
-#ifndef __ROCKCHIP_DRM_TVE_H__
6
-#define __ROCKCHIP_DRM_TVE_H__
7
-
8
-#include <lcd.h>
9
-
10
-#define TV_CTRL (0x00)
11
- #define m_CVBS_MODE BIT(24)
12
- #define m_CLK_UPSTREAM_EN (3 << 18)
13
- #define m_TIMING_EN (3 << 16)
14
- #define m_LUMA_FILTER_GAIN (3 << 9)
15
- #define m_LUMA_FILTER_BW BIT(8)
16
- #define m_CSC_PATH (3 << 1)
17
-
18
- #define v_CVBS_MODE(x) ((x & 1) << 24)
19
- #define v_CLK_UPSTREAM_EN(x) ((x & 3) << 18)
20
- #define v_TIMING_EN(x) ((x & 3) << 16)
21
- #define v_LUMA_FILTER_GAIN(x) ((x & 3) << 9)
22
- #define v_LUMA_FILTER_UPSAMPLE(x) ((x & 1) << 8)
23
- #define v_CSC_PATH(x) ((x & 3) << 1)
24
-
25
-#define TV_SYNC_TIMING (0x04)
26
-#define TV_ACT_TIMING (0x08)
27
-#define TV_ADJ_TIMING (0x0c)
28
-#define TV_FREQ_SC (0x10)
29
-#define TV_LUMA_FILTER0 (0x14)
30
-#define TV_LUMA_FILTER1 (0x18)
31
-#define TV_LUMA_FILTER2 (0x1C)
32
-#define TV_ACT_ST (0x34)
33
-#define TV_ROUTING (0x38)
34
- #define m_DAC_SENSE_EN BIT(27)
35
- #define m_Y_IRE_7_5 BIT(19)
36
- #define m_Y_AGC_PULSE_ON BIT(15)
37
- #define m_Y_VIDEO_ON BIT(11)
38
- #define m_Y_SYNC_ON BIT(7)
39
- #define m_YPP_MODE BIT(3)
40
- #define m_MONO_EN BIT(2)
41
- #define m_PIC_MODE BIT(1)
42
-
43
- #define v_DAC_SENSE_EN(x) ((x & 1) << 27)
44
- #define v_Y_IRE_7_5(x) ((x & 1) << 19)
45
- #define v_Y_AGC_PULSE_ON(x) ((x & 1) << 15)
46
- #define v_Y_VIDEO_ON(x) ((x & 1) << 11)
47
- #define v_Y_SYNC_ON(x) ((x & 1) << 7)
48
- #define v_YPP_MODE(x) ((x & 1) << 3)
49
- #define v_MONO_EN(x) ((x & 1) << 2)
50
- #define v_PIC_MODE(x) ((x & 1) << 1)
51
-
52
-#define TV_SYNC_ADJUST (0x50)
53
-#define TV_STATUS (0x54)
54
-#define TV_RESET (0x68)
55
- #define m_RESET BIT(1)
56
- #define v_RESET(x) ((x & 1) << 1)
57
-#define TV_SATURATION (0x78)
58
-#define TV_BW_CTRL (0x8C)
59
- #define m_CHROMA_BW (3 << 4)
60
- #define m_COLOR_DIFF_BW (0xf)
61
-
62
- enum {
63
- BP_FILTER_PASS = 0,
64
- BP_FILTER_NTSC,
65
- BP_FILTER_PAL,
66
- };
67
- enum {
68
- COLOR_DIFF_FILTER_OFF = 0,
69
- COLOR_DIFF_FILTER_BW_0_6,
70
- COLOR_DIFF_FILTER_BW_1_3,
71
- COLOR_DIFF_FILTER_BW_2_0
72
- };
73
-
74
- #define v_CHROMA_BW(x) ((3 & x) << 4)
75
- #define v_COLOR_DIFF_BW(x) (0xF & x)
76
-
77
-#define TV_BRIGHTNESS_CONTRAST (0x90)
78
-
79
-#define m_EXTREF_EN BIT(0)
80
-#define m_VBG_EN BIT(1)
81
-#define m_DAC_EN BIT(2)
82
-#define m_SENSE_EN BIT(3)
83
-#define m_BIAS_EN (7 << 4)
84
-#define m_DAC_GAIN (0x3f << 7)
85
-#define v_DAC_GAIN(x) ((x & 0x3f) << 7)
86
-
87
-#define VDAC_VDAC0 (0x00)
88
- #define m_RST_ANA BIT(7)
89
- #define m_RST_DIG BIT(6)
90
-
91
- #define v_RST_ANA(x) ((x & 1) << 7)
92
- #define v_RST_DIG(x) ((x & 1) << 6)
93
-#define VDAC_VDAC1 (0x280)
94
- #define m_CUR_REG (0xf << 4)
95
- #define m_DR_PWR_DOWN BIT(1)
96
- #define m_BG_PWR_DOWN BIT(0)
97
-
98
- #define v_CUR_REG(x) ((x & 0xf) << 4)
99
- #define v_DR_PWR_DOWN(x) ((x & 1) << 1)
100
- #define v_BG_PWR_DOWN(x) ((x & 1) << 0)
101
-#define VDAC_VDAC2 (0x284)
102
- #define m_CUR_CTR (0X3f)
103
-
104
- #define v_CUR_CTR(x) ((x & 0X3f))
105
-#define VDAC_VDAC3 (0x288)
106
- #define m_CAB_EN BIT(5)
107
- #define m_CAB_REF BIT(4)
108
- #define m_CAB_FLAG BIT(0)
109
-
110
- #define v_CAB_EN(x) ((x & 1) << 5)
111
- #define v_CAB_REF(x) ((x & 1) << 4)
112
- #define v_CAB_FLAG(x) ((x & 1) << 0)
113
-
114
-enum {
115
- TVOUT_CVBS_NTSC = 0,
116
- TVOUT_CVBS_PAL,
117
-};
118
-
119
-enum {
120
- SOC_RK3036 = 0,
121
- SOC_RK312X,
122
- SOC_RK322X,
123
- SOC_RK322XH
124
-};
125
-
126
-struct drm_tve {
127
- void *reg_phy_base;
128
- int soctype;
129
- int test_mode;
130
- int saturation;
131
- void *vdacbase;
132
- int brightcontrast;
133
- int adjtiming;
134
- int lumafilter0;
135
- int lumafilter1;
136
- int lumafilter2;
137
- int daclevel;
138
- int dac1level;
139
- int preferred_mode;
140
- void *grf;
141
-};
142
-
143
-#define RK30_TVE_REGBASE 0x10118000 + 0x200
144
-#define MAX_TVE_COUNT 2
145
-
146
-#ifdef TVEDEBUG
147
-#define TVEDBG(format, ...) \
148
- printf("TVE: " format, ## __VA_ARGS__)
149
-#else
150
-#define TVEDBG(format, ...)
151
-#endif
152
-
153
-#endif /* __ROCKCHIP_DRM_TVE_H__*/
u-boot/drivers/video/drm/rockchip_dw_hdmi.c
....@@ -7,6 +7,7 @@
77 #include <common.h>
88 #include <boot_rkimg.h>
99 #include <asm/io.h>
10
+#include <asm/gpio.h>
1011 #include <dm/of_access.h>
1112 #include <dm/device.h>
1213 #include <linux/dw_hdmi.h>
....@@ -35,6 +36,19 @@
3536 #define RK3328_GRF_SOC_CON2 0x0408
3637 #define RK3328_GRF_SOC_CON3 0x040c
3738 #define RK3328_GRF_SOC_CON4 0x0410
39
+
40
+#define RK3528_GPIO0A_IOMUX_SEL_H 0x4
41
+#define RK3528_GPIO0A_PULL 0x200
42
+#define RK3528_DDC_PULL (0xf00 << 16)
43
+#define RK3528_VO_GRF_HDMI_MASK 0x60014
44
+#define RK3528_HDMI_SNKDET_SEL ((BIT(6) << 16) | BIT(6))
45
+#define RK3528_HDMI_SNKDET BIT(21)
46
+#define RK3528_HDMI_CECIN_MSK ((BIT(2) << 16) | BIT(2))
47
+#define RK3528_HDMI_SDAIN_MSK ((BIT(1) << 16) | BIT(1))
48
+#define RK3528_HDMI_SCLIN_MSK ((BIT(0) << 16) | BIT(0))
49
+
50
+#define RK3528_GPIO_SWPORT_DR_L 0x0000
51
+#define RK3528_GPIO0_A2_DR ((BIT(2) << 16) | BIT(2))
3852
3953 #define RK3568_GRF_VO_CON1 0x0364
4054 #define RK3568_HDMI_SDAIN_MSK ((1 << 15) | (1 << (15 + 16)))
....@@ -177,7 +191,7 @@
177191 }
178192 };
179193
180
-static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
194
+static struct dw_hdmi_phy_config rockchip_phy_config[] = {
181195 /*pixelclk symbol term vlev*/
182196 { 74250000, 0x8009, 0x0004, 0x0272},
183197 { 165000000, 0x802b, 0x0004, 0x0209},
....@@ -334,19 +348,23 @@
334348 enum dw_hdmi_devtype dev_type,
335349 bool output_bus_format_rgb)
336350 {
337
- int ret, i, screen_size;
338
- struct base_disp_info base_parameter;
339351 struct base2_disp_info *base2_parameter = conn_state->disp_info;
340352 const struct base_overscan *scan;
341353 struct base_screen_info *screen_info = NULL;
342354 struct base2_screen_info *screen_info2 = NULL;
343355 int max_scan = 100;
344356 int min_scan = 51;
357
+#ifdef CONFIG_SPL_BUILD
358
+ int i, screen_size;
359
+#else
360
+ int ret, i, screen_size;
345361 int offset = 0;
346362 bool found = false;
347363 struct blk_desc *dev_desc;
348364 disk_partition_t part_info;
349365 char baseparameter_buf[8 * RK_BLK_SIZE] __aligned(ARCH_DMA_MINALIGN);
366
+ struct base_disp_info base_parameter;
367
+#endif
350368
351369 overscan->left_margin = max_scan;
352370 overscan->right_margin = max_scan;
....@@ -358,6 +376,27 @@
358376 else
359377 *bus_format = MEDIA_BUS_FMT_YUV8_1X24;
360378
379
+#ifdef CONFIG_SPL_BUILD
380
+ scan = &base2_parameter->overscan_info;
381
+ screen_size = sizeof(base2_parameter->screen_info) /
382
+ sizeof(base2_parameter->screen_info[0]);
383
+
384
+ for (i = 0; i < screen_size; i++) {
385
+ if (base2_parameter->screen_info[i].type ==
386
+ DRM_MODE_CONNECTOR_HDMIA) {
387
+ screen_info2 =
388
+ &base2_parameter->screen_info[i];
389
+ break;
390
+ }
391
+ }
392
+ screen_info = malloc(sizeof(*screen_info));
393
+
394
+ screen_info->type = screen_info2->type;
395
+ screen_info->mode = screen_info2->resolution;
396
+ screen_info->format = screen_info2->format;
397
+ screen_info->depth = screen_info2->depthc;
398
+ screen_info->feature = screen_info2->feature;
399
+#else
361400 if (!base2_parameter) {
362401 dev_desc = rockchip_get_bootdev();
363402 if (!dev_desc) {
....@@ -422,6 +461,7 @@
422461 screen_info->depth = screen_info2->depthc;
423462 screen_info->feature = screen_info2->feature;
424463 }
464
+#endif
425465
426466 if (scan->leftscale < min_scan && scan->leftscale > 0)
427467 overscan->left_margin = min_scan;
....@@ -443,7 +483,9 @@
443483 else if (scan->bottomscale < max_scan && scan->bottomscale > 0)
444484 overscan->bottom_margin = scan->bottomscale;
445485
486
+#ifndef CONFIG_SPL_BUILD
446487 null_basep:
488
+#endif
447489
448490 if (screen_info)
449491 printf("base_parameter.mode:%dx%d\n",
....@@ -463,8 +505,15 @@
463505 writel(RK3328_IO_3V_DOMAIN, grf + RK3328_GRF_SOC_CON4);
464506 }
465507
466
-void dw_hdmi_set_iomux(void *grf, int dev_type)
508
+void dw_hdmi_set_iomux(void *grf, void *gpio_base, struct gpio_desc *hpd_gpiod,
509
+ int dev_type)
467510 {
511
+ u32 val = 0;
512
+ int i = 400;
513
+#ifdef CONFIG_SPL_BUILD
514
+ void *gpio0_ioc = (void *)RK3528_GPIO0_IOC_BASE;
515
+#endif
516
+
468517 switch (dev_type) {
469518 case RK3328_HDMI:
470519 writel(RK3328_IO_DDC_IN_MSK, grf + RK3328_GRF_SOC_CON2);
....@@ -473,6 +522,49 @@
473522 case RK3228_HDMI:
474523 writel(RK3228_IO_3V_DOMAIN, grf + RK3228_GRF_SOC_CON6);
475524 writel(RK3228_IO_DDC_IN_MSK, grf + RK3228_GRF_SOC_CON2);
525
+ break;
526
+ case RK3528_HDMI:
527
+ writel(RK3528_HDMI_SDAIN_MSK | RK3528_HDMI_SCLIN_MSK |
528
+ RK3528_HDMI_SNKDET_SEL,
529
+ grf + RK3528_VO_GRF_HDMI_MASK);
530
+
531
+#ifdef CONFIG_SPL_BUILD
532
+ val = (0x11 << 16) | 0x11;
533
+ writel(val, gpio0_ioc + RK3528_GPIO0A_IOMUX_SEL_H);
534
+
535
+ writel(RK3528_DDC_PULL, gpio0_ioc + RK3528_GPIO0A_PULL);
536
+
537
+ /* gpio0_a2's input enable is controlled by gpio output data bit */
538
+ writel(RK3528_GPIO0_A2_DR, gpio_base + RK3528_GPIO_SWPORT_DR_L);
539
+
540
+ while (i--) {
541
+ val = readl(gpio_base + 0x70) & BIT(2);
542
+ if (val)
543
+ break;
544
+ mdelay(5);
545
+ }
546
+#else
547
+ writel(val, grf + RK3528_VO_GRF_HDMI_MASK);
548
+
549
+ /* gpio0_a2's input enable is controlled by gpio output data bit */
550
+ writel(RK3528_GPIO0_A2_DR, gpio_base + RK3528_GPIO_SWPORT_DR_L);
551
+
552
+ if (dm_gpio_is_valid(hpd_gpiod)) {
553
+ while (i--) {
554
+ val = dm_gpio_get_value(hpd_gpiod);
555
+ if (val)
556
+ break;
557
+ mdelay(5);
558
+ }
559
+ }
560
+#endif
561
+
562
+ if (val)
563
+ val = RK3528_HDMI_SNKDET | BIT(5);
564
+ else
565
+ val = RK3528_HDMI_SNKDET;
566
+ writel(val, grf + RK3528_VO_GRF_HDMI_MASK);
567
+
476568 break;
477569 case RK3568_HDMI:
478570 writel(RK3568_HDMI_SDAIN_MSK | RK3568_HDMI_SCLIN_MSK,
....@@ -544,6 +636,14 @@
544636 .dev_type = RK3399_HDMI,
545637 };
546638
639
+const struct dw_hdmi_plat_data rk3528_hdmi_drv_data = {
640
+ .vop_sel_bit = 0,
641
+ .grf_vop_sel_reg = 0,
642
+ .phy_ops = &inno_dw_hdmi_phy_ops,
643
+ .phy_name = "inno_dw_hdmi_phy2",
644
+ .dev_type = RK3528_HDMI,
645
+};
646
+
547647 const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
548648 .vop_sel_bit = 0,
549649 .grf_vop_sel_reg = 0,
....@@ -554,6 +654,19 @@
554654 .dev_type = RK3568_HDMI,
555655 };
556656
657
+#ifdef CONFIG_SPL_BUILD
658
+int rockchip_spl_dw_hdmi_probe(struct connector_state *conn_state)
659
+{
660
+ conn_state->connector = malloc(sizeof(struct rockchip_connector));
661
+
662
+ memset(conn_state->connector, 0, sizeof(*conn_state->connector));
663
+ rockchip_connector_bind(conn_state->connector, NULL, 0, &rockchip_dw_hdmi_funcs,
664
+ (void *)&rk3528_hdmi_drv_data,
665
+ DRM_MODE_CONNECTOR_HDMIA);
666
+
667
+ return 0;
668
+}
669
+#else
557670 static int rockchip_dw_hdmi_probe(struct udevice *dev)
558671 {
559672 int id;
....@@ -568,9 +681,13 @@
568681
569682 return 0;
570683 }
684
+#endif
571685
572686 static const struct udevice_id rockchip_dw_hdmi_ids[] = {
573687 {
688
+ .compatible = "rockchip,rk3528-dw-hdmi",
689
+ .data = (ulong)&rk3528_hdmi_drv_data,
690
+ }, {
574691 .compatible = "rockchip,rk3568-dw-hdmi",
575692 .data = (ulong)&rk3568_hdmi_drv_data,
576693 }, {
....@@ -598,6 +715,8 @@
598715 .name = "rockchip_dw_hdmi",
599716 .id = UCLASS_DISPLAY,
600717 .of_match = rockchip_dw_hdmi_ids,
718
+#ifndef CONFIG_SPL_BUILD
601719 .probe = rockchip_dw_hdmi_probe,
720
+#endif
602721 .priv_auto_alloc_size = sizeof(struct rockchip_connector),
603722 };
u-boot/drivers/video/drm/rockchip_dw_hdmi_qp.c
....@@ -50,6 +50,7 @@
5050
5151 #define RK3588_GRF_VO1_CON3 0x000c
5252 #define RK3588_COLOR_FORMAT_MASK 0xf
53
+#define RK3588_YUV422 0x1
5354 #define RK3588_YUV444 0x2
5455 #define RK3588_YUV420 0x3
5556 #define RK3588_COMPRESSED_DATA 0xb
....@@ -348,6 +349,9 @@
348349 case MEDIA_BUS_FMT_UYVY8_1X16:
349350 case MEDIA_BUS_FMT_UYVY10_1X20:
350351 case MEDIA_BUS_FMT_UYVY12_1X24:
352
+ case MEDIA_BUS_FMT_YUYV8_1X16:
353
+ case MEDIA_BUS_FMT_YUYV10_1X20:
354
+ case MEDIA_BUS_FMT_YUYV12_1X24:
351355 return true;
352356
353357 default:
....@@ -375,18 +379,21 @@
375379 case MEDIA_BUS_FMT_RGB888_1X24:
376380 case MEDIA_BUS_FMT_YUV8_1X24:
377381 case MEDIA_BUS_FMT_UYVY8_1X16:
382
+ case MEDIA_BUS_FMT_YUYV8_1X16:
378383 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
379384 return 8;
380385
381386 case MEDIA_BUS_FMT_RGB101010_1X30:
382387 case MEDIA_BUS_FMT_YUV10_1X30:
383388 case MEDIA_BUS_FMT_UYVY10_1X20:
389
+ case MEDIA_BUS_FMT_YUYV10_1X20:
384390 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
385391 return 10;
386392
387393 case MEDIA_BUS_FMT_RGB121212_1X36:
388394 case MEDIA_BUS_FMT_YUV12_1X36:
389395 case MEDIA_BUS_FMT_UYVY12_1X24:
396
+ case MEDIA_BUS_FMT_YUYV12_1X24:
390397 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
391398 return 12;
392399
....@@ -834,12 +841,8 @@
834841 if (screen_info && screen_info->depth == 10)
835842 color_depth = screen_info->depth;
836843
837
- if (mode->clock >= 600000) {
844
+ if (mode->clock >= 600000)
838845 color_format = DRM_HDMI_OUTPUT_YCBCR420;
839
- } else if (mode->clock >= 340000) {
840
- if (drm_mode_is_420(info, mode))
841
- color_format = DRM_HDMI_OUTPUT_YCBCR420;
842
- }
843846
844847 if (color_format == DRM_HDMI_OUTPUT_YCBCR422 || color_depth == 8)
845848 tmdsclock = pixclock;
....@@ -876,7 +879,7 @@
876879 case DRM_HDMI_OUTPUT_YCBCR444:
877880 return MEDIA_BUS_FMT_YUV10_1X30;
878881 case DRM_HDMI_OUTPUT_YCBCR422:
879
- return MEDIA_BUS_FMT_UYVY10_1X20;
882
+ return MEDIA_BUS_FMT_YUYV10_1X20;
880883 case DRM_HDMI_OUTPUT_YCBCR420:
881884 return MEDIA_BUS_FMT_UYYVYY10_0_5X30;
882885 default:
....@@ -887,7 +890,7 @@
887890 case DRM_HDMI_OUTPUT_YCBCR444:
888891 return MEDIA_BUS_FMT_YUV8_1X24;
889892 case DRM_HDMI_OUTPUT_YCBCR422:
890
- return MEDIA_BUS_FMT_UYVY8_1X16;
893
+ return MEDIA_BUS_FMT_YUYV8_1X16;
891894 case DRM_HDMI_OUTPUT_YCBCR420:
892895 return MEDIA_BUS_FMT_UYYVYY8_0_5X24;
893896 default:
....@@ -1081,7 +1084,7 @@
10811084 if (hdmi_bus_fmt_is_yuv420(*bus_format))
10821085 hdmi->bus_width /= 2;
10831086
1084
- if (color_depth == 10)
1087
+ if (color_depth == 10 && !hdmi_bus_fmt_is_yuv422(*bus_format))
10851088 hdmi->bus_width |= COLOR_DEPTH_10BIT;
10861089 }
10871090
....@@ -1154,6 +1157,10 @@
11541157 case MEDIA_BUS_FMT_YUV10_1X30:
11551158 val = HIWORD_UPDATE(RK3588_YUV444, RK3588_COLOR_FORMAT_MASK);
11561159 break;
1160
+ case MEDIA_BUS_FMT_YUYV10_1X20:
1161
+ case MEDIA_BUS_FMT_YUYV8_1X16:
1162
+ val = HIWORD_UPDATE(RK3588_YUV422, RK3588_COLOR_FORMAT_MASK);
1163
+ break;
11571164 default:
11581165 dev_err(hdmi->dev, "can't set correct color format\n");
11591166 return;
....@@ -1162,7 +1169,7 @@
11621169 if (hdmi->link_cfg.dsc_mode)
11631170 val = HIWORD_UPDATE(RK3588_COMPRESSED_DATA, RK3588_COLOR_FORMAT_MASK);
11641171
1165
- if (depth == 8)
1172
+ if (depth == 8 || bus_format == MEDIA_BUS_FMT_YUYV10_1X20)
11661173 val |= HIWORD_UPDATE(RK3588_8BPC, RK3588_COLOR_DEPTH_MASK);
11671174 else
11681175 val |= HIWORD_UPDATE(RK3588_10BPC, RK3588_COLOR_DEPTH_MASK);
u-boot/drivers/video/drm/rockchip_lvds.c
....@@ -59,6 +59,9 @@
5959 #define RK3368_LVDS_MSBSEL(x) HIWORD_UPDATE(x, 11, 11)
6060 #define RK3368_LVDS_P2S_EN(x) HIWORD_UPDATE(x, 6, 6)
6161
62
+#define RK3562_GRF_VO_CON0 0x05d0
63
+#define RK3562_GRF_VO_CON1 0x05d4
64
+
6265 #define RK3568_GRF_VO_CON0 0x0360
6366 #define RK3568_LVDS1_SELECT(x) HIWORD_UPDATE(x, 13, 12)
6467 #define RK3568_LVDS1_MSBSEL(x) HIWORD_UPDATE(x, 11, 11)
....@@ -307,6 +310,25 @@
307310 .disable = rk3368_lvds_disable,
308311 };
309312
313
+static void rk3562_lvds_enable(struct rockchip_lvds *lvds, int pipe)
314
+{
315
+ regmap_write(lvds->grf, RK3562_GRF_VO_CON1,
316
+ RK3568_LVDS0_MODE_EN(1) | RK3568_LVDS0_P2S_EN(1) |
317
+ RK3568_LVDS0_DCLK_INV_SEL(1));
318
+ regmap_write(lvds->grf, RK3562_GRF_VO_CON0,
319
+ RK3568_LVDS0_SELECT(lvds->format) | RK3568_LVDS0_MSBSEL(1));
320
+}
321
+
322
+static void rk3562_lvds_disable(struct rockchip_lvds *lvds)
323
+{
324
+ regmap_write(lvds->grf, RK3562_GRF_VO_CON1, RK3568_LVDS0_MODE_EN(0));
325
+}
326
+
327
+static const struct rockchip_lvds_funcs rk3562_lvds_funcs = {
328
+ .enable = rk3562_lvds_enable,
329
+ .disable = rk3562_lvds_disable,
330
+};
331
+
310332 static void rk3568_lvds_enable(struct rockchip_lvds *lvds, int pipe)
311333 {
312334 regmap_write(lvds->grf, RK3568_GRF_VO_CON2,
....@@ -344,6 +366,10 @@
344366 .data = (ulong)&rk3368_lvds_funcs,
345367 },
346368 {
369
+ .compatible = "rockchip,rk3562-lvds",
370
+ .data = (ulong)&rk3562_lvds_funcs,
371
+ },
372
+ {
347373 .compatible = "rockchip,rk3568-lvds",
348374 .data = (ulong)&rk3568_lvds_funcs,
349375 },
u-boot/drivers/video/drm/rockchip_panel.c
....@@ -12,6 +12,7 @@
1212 #include <malloc.h>
1313 #include <video.h>
1414 #include <backlight.h>
15
+#include <spi.h>
1516 #include <asm/gpio.h>
1617 #include <dm/device.h>
1718 #include <dm/read.h>
....@@ -65,6 +66,7 @@
6566 bool enabled;
6667 struct udevice *power_supply;
6768 struct udevice *backlight;
69
+ struct spi_slave *spi_slave;
6870 struct gpio_desc enable_gpio;
6971 struct gpio_desc reset_gpio;
7072 struct gpio_desc edp_bl_on;
....@@ -197,24 +199,48 @@
197199 {
198200 struct rockchip_panel_priv *priv = dev_get_priv(panel->dev);
199201 int i;
202
+ int ret;
200203
201204 if (!cmds)
202205 return -EINVAL;
203206
207
+ if (priv->spi_slave) {
208
+ ret = spi_claim_bus(priv->spi_slave);
209
+ if (ret) {
210
+ printf("%s: Failed to claim spi bus: %d\n", __func__, ret);
211
+ return -EINVAL;
212
+ }
213
+ }
214
+
204215 for (i = 0; i < cmds->cmd_cnt; i++) {
205216 struct rockchip_cmd_desc *desc = &cmds->cmds[i];
206217 int value = 0;
218
+ u16 mask = 0;
219
+ u16 data = 0;
207220
208
- if (desc->header.payload_length == 2)
209
- value = (desc->payload[0] << 8) | desc->payload[1];
210
- else
211
- value = desc->payload[0];
212
- rockchip_panel_write_spi_cmds(priv,
213
- desc->header.data_type, value);
221
+ if (priv->spi_slave) {
222
+ mask = desc->header.data_type ? 0x100 : 0;
223
+ data = (mask | desc->payload[0]) << 7;;
224
+ data = ((data & 0xff) << 8) | (data >> 8);
225
+ value = mask | desc->payload[0];
226
+ ret = spi_xfer(priv->spi_slave, 9, &data, NULL, SPI_XFER_ONCE);
227
+ if (ret)
228
+ printf("%s: Failed to xfer spi cmd 0x%x: %d\n",
229
+ __func__, desc->payload[0], ret);
230
+ } else {
231
+ if (desc->header.payload_length == 2)
232
+ value = (desc->payload[0] << 8) | desc->payload[1];
233
+ else
234
+ value = desc->payload[0];
235
+ rockchip_panel_write_spi_cmds(priv, desc->header.data_type, value);
236
+ }
214237
215238 if (desc->header.delay_ms)
216239 mdelay(desc->header.delay_ms);
217240 }
241
+
242
+ if (priv->spi_slave)
243
+ spi_release_bus(priv->spi_slave);
218244
219245 return 0;
220246 }
....@@ -336,21 +362,24 @@
336362
337363 if (dm_gpio_is_valid(&priv->edp_bl_en))
338364 dm_gpio_set_value(&priv->edp_bl_en, 1);
339
-
365
+
340366 if (dm_gpio_is_valid(&priv->enable_gpio))
341367 dm_gpio_set_value(&priv->enable_gpio, 1);
342
-
368
+
343369 if (plat->delay.prepare)
344370 mdelay(plat->delay.prepare);
345
-
371
+
346372 if (dm_gpio_is_valid(&priv->reset_gpio))
347373 dm_gpio_set_value(&priv->reset_gpio, 1);
374
+
375
+ if (plat->delay.reset)
376
+ mdelay(plat->delay.reset);
348377 mdelay(50);
349378 if (dm_gpio_is_valid(&priv->reset_gpio))
350379 dm_gpio_set_value(&priv->reset_gpio, 0);
351
-
352
- mdelay(200);
353380
381
+ mdelay(200);
382
+
354383 if (plat->delay.init)
355384 mdelay(plat->delay.init);
356385
....@@ -556,7 +585,7 @@
556585 printf("%s: Cannot get reset GPIO: %d\n", __func__, ret);
557586 return ret;
558587 }
559
-
588
+
560589 ret = gpio_request_by_name(dev, "lvds-gpio0", 0,
561590 &priv->lvds_gpio0, GPIOD_IS_OUT);
562591 if (ret && ret != -ENOENT) {
....@@ -584,7 +613,7 @@
584613 printf("%s: Cannot get lvds-gpio3: %d\n", __func__, ret);
585614 return ret;
586615 }
587
-
616
+
588617 ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
589618 "backlight", &priv->backlight);
590619 if (ret && ret != -ENOENT) {
....@@ -606,31 +635,47 @@
606635 priv->cmd_type = get_panel_cmd_type(cmd_type);
607636
608637 if (priv->cmd_type == CMD_TYPE_SPI) {
609
- ret = gpio_request_by_name(dev, "spi-sdi-gpios", 0,
610
- &priv->spi_sdi_gpio, GPIOD_IS_OUT);
611
- if (ret && ret != -ENOENT) {
612
- printf("%s: Cannot get spi sdi GPIO: %d\n",
613
- __func__, ret);
614
- return ret;
638
+ ofnode parent = ofnode_get_parent(dev->node);
639
+
640
+ if (ofnode_valid(parent)) {
641
+ struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
642
+ struct udevice *spi = dev_get_parent(dev);
643
+
644
+ if (spi->seq < 0) {
645
+ printf("%s: Failed to get spi bus num\n", __func__);
646
+ return -EINVAL;
647
+ }
648
+
649
+ priv->spi_slave = spi_setup_slave(spi->seq, plat->cs, plat->max_hz,
650
+ plat->mode);
651
+ if (!priv->spi_slave) {
652
+ printf("%s: Failed to setup spi slave: %d\n", __func__, ret);
653
+ return -EINVAL;
654
+ }
655
+ } else {
656
+ ret = gpio_request_by_name(dev, "spi-sdi-gpios", 0,
657
+ &priv->spi_sdi_gpio, GPIOD_IS_OUT);
658
+ if (ret && ret != -ENOENT) {
659
+ printf("%s: Cannot get spi sdi GPIO: %d\n", __func__, ret);
660
+ return ret;
661
+ }
662
+ ret = gpio_request_by_name(dev, "spi-scl-gpios", 0,
663
+ &priv->spi_scl_gpio, GPIOD_IS_OUT);
664
+ if (ret && ret != -ENOENT) {
665
+ printf("%s: Cannot get spi scl GPIO: %d\n", __func__, ret);
666
+ return ret;
667
+ }
668
+ ret = gpio_request_by_name(dev, "spi-cs-gpios", 0,
669
+ &priv->spi_cs_gpio, GPIOD_IS_OUT);
670
+ if (ret && ret != -ENOENT) {
671
+ printf("%s: Cannot get spi cs GPIO: %d\n", __func__, ret);
672
+ return ret;
673
+ }
674
+ dm_gpio_set_value(&priv->spi_sdi_gpio, 1);
675
+ dm_gpio_set_value(&priv->spi_scl_gpio, 1);
676
+ dm_gpio_set_value(&priv->spi_cs_gpio, 1);
677
+ dm_gpio_set_value(&priv->reset_gpio, 0);
615678 }
616
- ret = gpio_request_by_name(dev, "spi-scl-gpios", 0,
617
- &priv->spi_scl_gpio, GPIOD_IS_OUT);
618
- if (ret && ret != -ENOENT) {
619
- printf("%s: Cannot get spi scl GPIO: %d\n",
620
- __func__, ret);
621
- return ret;
622
- }
623
- ret = gpio_request_by_name(dev, "spi-cs-gpios", 0,
624
- &priv->spi_cs_gpio, GPIOD_IS_OUT);
625
- if (ret && ret != -ENOENT) {
626
- printf("%s: Cannot get spi cs GPIO: %d\n",
627
- __func__, ret);
628
- return ret;
629
- }
630
- dm_gpio_set_value(&priv->spi_sdi_gpio, 1);
631
- dm_gpio_set_value(&priv->spi_scl_gpio, 1);
632
- dm_gpio_set_value(&priv->spi_cs_gpio, 1);
633
- dm_gpio_set_value(&priv->reset_gpio, 0);
634679 }
635680
636681 panel = calloc(1, sizeof(*panel));
....@@ -649,6 +694,7 @@
649694 static const struct udevice_id rockchip_panel_ids[] = {
650695 { .compatible = "simple-panel", },
651696 { .compatible = "simple-panel-dsi", },
697
+ { .compatible = "simple-panel-spi", },
652698 {}
653699 };
654700
u-boot/drivers/video/drm/rockchip_post_csc.c
....@@ -0,0 +1,1587 @@
1
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
+/*
3
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4
+ * Author: Zhang yubing <yubing.zhang@rock-chips.com>
5
+ */
6
+
7
+#include <stdio.h>
8
+#include <linux/errno.h>
9
+
10
+#include "rockchip_post_csc.h"
11
+
12
+#define PQ_CSC_HUE_TABLE_NUM 256
13
+#define PQ_CSC_MODE_COEF_COMMENT_LEN 32
14
+#define PQ_CSC_SIMPLE_MAT_PARAM_FIX_BIT_WIDTH 10
15
+#define PQ_CSC_SIMPLE_MAT_PARAM_FIX_NUM (1 << PQ_CSC_SIMPLE_MAT_PARAM_FIX_BIT_WIDTH)
16
+
17
+#define PQ_CALC_ENHANCE_BIT 6
18
+/* csc convert coef fixed-point num bit width */
19
+#define PQ_CSC_PARAM_FIX_BIT_WIDTH 10
20
+/* csc convert coef half fixed-point num bit width */
21
+#define PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH (PQ_CSC_PARAM_FIX_BIT_WIDTH - 1)
22
+/* csc convert coef fixed-point num */
23
+#define PQ_CSC_PARAM_FIX_NUM (1 << PQ_CSC_PARAM_FIX_BIT_WIDTH)
24
+#define PQ_CSC_PARAM_HALF_FIX_NUM (1 << PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH)
25
+/* csc input param bit width */
26
+#define PQ_CSC_IN_PARAM_NORM_BIT_WIDTH 9
27
+/* csc input param normalization coef */
28
+#define PQ_CSC_IN_PARAM_NORM_COEF (1 << PQ_CSC_IN_PARAM_NORM_BIT_WIDTH)
29
+
30
+/* csc hue table range [0,255] */
31
+#define PQ_CSC_HUE_TABLE_DIV_COEF 2
32
+/* csc brightness offset */
33
+#define PQ_CSC_BRIGHTNESS_OFFSET 256
34
+
35
+/* dc coef base bit width */
36
+#define PQ_CSC_DC_COEF_BASE_BIT_WIDTH 10
37
+/* input dc coef offset for 10bit data */
38
+#define PQ_CSC_DC_IN_OFFSET 64
39
+/* input and output dc coef offset for 10bit data u,v */
40
+#define PQ_CSC_DC_IN_OUT_DEFAULT 512
41
+/* r,g,b color temp div coef, range [-128,128] for 10bit data */
42
+#define PQ_CSC_TEMP_OFFSET_DIV_COEF 2
43
+
44
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
45
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
46
+#define CLIP(x, min_v, max_v) MIN(MAX(x, min_v), max_v)
47
+
48
+enum rk_pq_csc_mode {
49
+ RK_PQ_CSC_YUV2RGB_601 = 0, /* YCbCr_601 LIMIT-> RGB FULL */
50
+ RK_PQ_CSC_YUV2RGB_709, /* YCbCr_709 LIMIT-> RGB FULL */
51
+ RK_PQ_CSC_RGB2YUV_601, /* RGB FULL->YCbCr_601 LIMIT */
52
+ RK_PQ_CSC_RGB2YUV_709, /* RGB FULL->YCbCr_709 LIMIT */
53
+ RK_PQ_CSC_YUV2YUV_709_601, /* YCbCr_709 LIMIT->YCbCr_601 LIMIT */
54
+ RK_PQ_CSC_YUV2YUV_601_709, /* YCbCr_601 LIMIT->YCbCr_709 LIMIT */
55
+ RK_PQ_CSC_YUV2YUV, /* YCbCr LIMIT->YCbCr LIMIT */
56
+ RK_PQ_CSC_YUV2RGB_601_FULL, /* YCbCr_601 FULL-> RGB FULL */
57
+ RK_PQ_CSC_YUV2RGB_709_FULL, /* YCbCr_709 FULL-> RGB FULL */
58
+ RK_PQ_CSC_RGB2YUV_601_FULL, /* RGB FULL->YCbCr_601 FULL */
59
+ RK_PQ_CSC_RGB2YUV_709_FULL, /* RGB FULL->YCbCr_709 FULL */
60
+ RK_PQ_CSC_YUV2YUV_709_601_FULL, /* YCbCr_709 FULL->YCbCr_601 FULL */
61
+ RK_PQ_CSC_YUV2YUV_601_709_FULL, /* YCbCr_601 FULL->YCbCr_709 FULL */
62
+ RK_PQ_CSC_YUV2YUV_FULL, /* YCbCr FULL->YCbCr FULL */
63
+ RK_PQ_CSC_YUV2YUV_LIMIT2FULL, /* YCbCr LIMIT->YCbCr FULL */
64
+ RK_PQ_CSC_YUV2YUV_601_709_LIMIT2FULL, /* YCbCr 601 LIMIT->YCbCr 709 FULL */
65
+ RK_PQ_CSC_YUV2YUV_709_601_LIMIT2FULL, /* YCbCr 709 LIMIT->YCbCr 601 FULL */
66
+ RK_PQ_CSC_YUV2YUV_FULL2LIMIT, /* YCbCr FULL->YCbCr LIMIT */
67
+ RK_PQ_CSC_YUV2YUV_601_709_FULL2LIMIT, /* YCbCr 601 FULL->YCbCr 709 LIMIT */
68
+ RK_PQ_CSC_YUV2YUV_709_601_FULL2LIMIT, /* YCbCr 709 FULL->YCbCr 601 LIMIT */
69
+ RK_PQ_CSC_YUV2RGBL_601, /* YCbCr_601 LIMIT-> RGB LIMIT */
70
+ RK_PQ_CSC_YUV2RGBL_709, /* YCbCr_709 LIMIT-> RGB LIMIT */
71
+ RK_PQ_CSC_RGBL2YUV_601, /* RGB LIMIT->YCbCr_601 LIMIT */
72
+ RK_PQ_CSC_RGBL2YUV_709, /* RGB LIMIT->YCbCr_709 LIMIT */
73
+ RK_PQ_CSC_YUV2RGBL_601_FULL, /* YCbCr_601 FULL-> RGB LIMIT */
74
+ RK_PQ_CSC_YUV2RGBL_709_FULL, /* YCbCr_709 FULL-> RGB LIMIT */
75
+ RK_PQ_CSC_RGBL2YUV_601_FULL, /* RGB LIMIT->YCbCr_601 FULL */
76
+ RK_PQ_CSC_RGBL2YUV_709_FULL, /* RGB LIMIT->YCbCr_709 FULL */
77
+ RK_PQ_CSC_RGB2RGBL, /* RGB FULL->RGB LIMIT */
78
+ RK_PQ_CSC_RGBL2RGB, /* RGB LIMIT->RGB FULL */
79
+ RK_PQ_CSC_RGBL2RGBL, /* RGB LIMIT->RGB LIMIT */
80
+ RK_PQ_CSC_RGB2RGB, /* RGB FULL->RGB FULL */
81
+ RK_PQ_CSC_YUV2RGB_2020, /* YUV 2020 FULL->RGB 2020 FULL */
82
+ RK_PQ_CSC_RGB2YUV2020_LIMIT2FULL, /* BT2020RGBLIMIT -> BT2020YUVFULL */
83
+ RK_PQ_CSC_RGB2YUV2020_LIMIT, /* BT2020RGBLIMIT -> BT2020YUVLIMIT */
84
+ RK_PQ_CSC_RGB2YUV2020_FULL2LIMIT, /* BT2020RGBFULL -> BT2020YUVLIMIT */
85
+ RK_PQ_CSC_RGB2YUV2020_FULL, /* BT2020RGBFULL -> BT2020YUVFULL */
86
+};
87
+
88
+enum color_space_type {
89
+ OPTM_CS_E_UNKNOWN = 0,
90
+ OPTM_CS_E_ITU_R_BT_709 = 1,
91
+ OPTM_CS_E_FCC = 4,
92
+ OPTM_CS_E_ITU_R_BT_470_2_BG = 5,
93
+ OPTM_CS_E_SMPTE_170_M = 6,
94
+ OPTM_CS_E_SMPTE_240_M = 7,
95
+ OPTM_CS_E_XV_YCC_709 = OPTM_CS_E_ITU_R_BT_709,
96
+ OPTM_CS_E_XV_YCC_601 = 8,
97
+ OPTM_CS_E_RGB = 9,
98
+ OPTM_CS_E_XV_YCC_2020 = 10,
99
+ OPTM_CS_E_RGB_2020 = 11,
100
+};
101
+
102
+enum vop_csc_format {
103
+ CSC_BT601L,
104
+ CSC_BT709L,
105
+ CSC_BT601F,
106
+ CSC_BT2020,
107
+ CSC_BT709L_13BIT,
108
+ CSC_BT709F_13BIT,
109
+ CSC_BT2020L_13BIT,
110
+ CSC_BT2020F_13BIT,
111
+};
112
+
113
+struct rk_pq_csc_coef {
114
+ s32 csc_coef00;
115
+ s32 csc_coef01;
116
+ s32 csc_coef02;
117
+ s32 csc_coef10;
118
+ s32 csc_coef11;
119
+ s32 csc_coef12;
120
+ s32 csc_coef20;
121
+ s32 csc_coef21;
122
+ s32 csc_coef22;
123
+};
124
+
125
+struct rk_pq_csc_ventor {
126
+ s32 csc_offset0;
127
+ s32 csc_offset1;
128
+ s32 csc_offset2;
129
+};
130
+
131
+struct rk_pq_csc_dc_coef {
132
+ s32 csc_in_dc0;
133
+ s32 csc_in_dc1;
134
+ s32 csc_in_dc2;
135
+ s32 csc_out_dc0;
136
+ s32 csc_out_dc1;
137
+ s32 csc_out_dc2;
138
+};
139
+
140
+/* color space param */
141
+struct rk_csc_colorspace_info {
142
+ enum color_space_type input_color_space;
143
+ enum color_space_type output_color_space;
144
+ bool in_full_range;
145
+ bool out_full_range;
146
+};
147
+
148
+struct rk_csc_mode_coef {
149
+ enum rk_pq_csc_mode csc_mode;
150
+ char c_csc_comment[PQ_CSC_MODE_COEF_COMMENT_LEN];
151
+ const struct rk_pq_csc_coef *pst_csc_coef;
152
+ const struct rk_pq_csc_dc_coef *pst_csc_dc_coef;
153
+ struct rk_csc_colorspace_info st_csc_color_info;
154
+};
155
+
156
+/*
157
+ *CSC matrix
158
+ */
159
+/* xv_ycc BT.601 limit(i.e. SD) -> RGB full */
160
+static const struct rk_pq_csc_coef rk_csc_table_xv_yccsdy_cb_cr_limit_to_rgb_full = {
161
+ 1196, 0, 1639,
162
+ 1196, -402, -835,
163
+ 1196, 2072, 0
164
+};
165
+
166
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_xv_yccsdy_cb_cr_limit_to_rgb_full = {
167
+ -64, -512, -512,
168
+ 0, 0, 0
169
+};
170
+
171
+/* BT.709 limit(i.e. HD) -> RGB full */
172
+static const struct rk_pq_csc_coef rk_csc_table_hdy_cb_cr_limit_to_rgb_full = {
173
+ 1196, 0, 1841,
174
+ 1196, -219, -547,
175
+ 1196, 2169, 0
176
+};
177
+
178
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_hdy_cb_cr_limit_to_rgb_full = {
179
+ -64, -512, -512,
180
+ 0, 0, 0
181
+};
182
+
183
+/* RGB full-> YUV601 (i.e. SD) limit */
184
+static const struct rk_pq_csc_coef rk_csc_table_rgb_to_xv_yccsdy_cb_cr = {
185
+ 262, 515, 100,
186
+ -151, -297, 448,
187
+ 448, -376, -73
188
+};
189
+
190
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_rgb_to_xv_yccsdy_cb_cr = {
191
+ 0, 0, 0,
192
+ 64, 512, 512
193
+};
194
+
195
+/* RGB full-> YUV709 (i.e. SD) limit */
196
+static const struct rk_pq_csc_coef rk_csc_table_rgb_to_hdy_cb_cr = {
197
+ 186, 627, 63,
198
+ -103, -346, 448,
199
+ 448, -407, -41
200
+};
201
+
202
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_rgb_to_hdy_cb_cr = {
203
+ 0, 0, 0,
204
+ 64, 512, 512
205
+};
206
+
207
+/* BT.709 (i.e. HD) -> to xv_ycc BT.601 (i.e. SD) */
208
+static const struct rk_pq_csc_coef rk_csc_table_hdy_cb_cr_to_xv_yccsdy_cb_cr = {
209
+ 1024, 104, 201,
210
+ 0, 1014, -113,
211
+ 0, -74, 1007
212
+};
213
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_hdy_cb_cr_to_xv_yccsdy_cb_cr = {
214
+ -64, -512, -512,
215
+ 64, 512, 512
216
+};
217
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_hdy_cb_cr_full_to_xv_yccsdy_cb_cr_full = {
218
+ 0, -512, -512,
219
+ 0, 512, 512
220
+};
221
+
222
+/* xv_ycc BT.601 (i.e. SD) -> to BT.709 (i.e. HD) */
223
+static const struct rk_pq_csc_coef rk_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr = {
224
+ 1024, -121, -218,
225
+ 0, 1043, 117,
226
+ 0, 77, 1050
227
+};
228
+
229
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr = {
230
+ -64, -512, -512,
231
+ 64, 512, 512
232
+};
233
+
234
+/* xv_ycc BT.601 full(i.e. SD) -> RGB full */
235
+static const struct rk_pq_csc_coef rk_csc_table_xv_yccsdy_cb_cr_to_rgb_full = {
236
+ 1024, 0, 1436,
237
+ 1024, -352, -731,
238
+ 1024, 1815, 0
239
+};
240
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_xv_yccsdy_cb_cr_to_rgb_full = {
241
+ 0, -512, -512,
242
+ 0, 0, 0
243
+};
244
+
245
+/* BT.709 full(i.e. HD) -> RGB full */
246
+static const struct rk_pq_csc_coef rk_csc_table_hdy_cb_cr_to_rgb_full = {
247
+ 1024, 0, 1613,
248
+ 1024, -192, -479,
249
+ 1024, 1900, 0
250
+};
251
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_hdy_cb_cr_to_rgb_full = {
252
+ 0, -512, -512,
253
+ 0, 0, 0
254
+};
255
+
256
+/* RGB full-> YUV601 full(i.e. SD) */
257
+static const struct rk_pq_csc_coef rk_csc_table_rgb_to_xv_yccsdy_cb_cr_full = {
258
+ 306, 601, 117,
259
+ -173, -339, 512,
260
+ 512, -429, -83
261
+};
262
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_rgb_to_xv_yccsdy_cb_cr_full = {
263
+ 0, 0, 0,
264
+ 0, 512, 512
265
+};
266
+
267
+/* RGB full-> YUV709 full (i.e. SD) */
268
+static const struct rk_pq_csc_coef rk_csc_table_rgb_to_hdy_cb_cr_full = {
269
+ 218, 732, 74,
270
+ -117, -395, 512,
271
+ 512, -465, -47
272
+};
273
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_rgb_to_hdy_cb_cr_full = {
274
+ 0, 0, 0,
275
+ 0, 512, 512
276
+};
277
+
278
+/* limit -> full */
279
+static const struct rk_pq_csc_coef rk_csc_table_identity_y_cb_cr_limit_to_y_cb_cr_full = {
280
+ 1196, 0, 0,
281
+ 0, 1169, 0,
282
+ 0, 0, 1169
283
+};
284
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_y_cb_cr_limit_to_y_cb_cr_full = {
285
+ -64, -512, -512,
286
+ 0, 512, 512
287
+};
288
+
289
+/* 601 limit -> 709 full */
290
+static const struct rk_pq_csc_coef rk_csc_table_identity_601_limit_to_709_full = {
291
+ 1196, -138, -249,
292
+ 0, 1191, 134,
293
+ 0, 88, 1199
294
+};
295
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_601_limit_to_709_full = {
296
+ -64, -512, -512,
297
+ 0, 512, 512
298
+};
299
+
300
+/* 709 limit -> 601 full */
301
+static const struct rk_pq_csc_coef rk_csc_table_identity_709_limit_to_601_full = {
302
+ 1196, 119, 229,
303
+ 0, 1157, -129,
304
+ 0, -85, 1150
305
+};
306
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_709_limit_to_601_full = {
307
+ -64, -512, -512,
308
+ 0, 512, 512
309
+};
310
+
311
+/* full -> limit */
312
+static const struct rk_pq_csc_coef rk_csc_table_identity_y_cb_cr_full_to_y_cb_cr_limit = {
313
+ 877, 0, 0,
314
+ 0, 897, 0,
315
+ 0, 0, 897
316
+};
317
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_y_cb_cr_full_to_y_cb_cr_limit = {
318
+ 0, -512, -512,
319
+ 64, 512, 512
320
+};
321
+
322
+/* 601 full -> 709 limit */
323
+static const struct rk_pq_csc_coef rk_csc_table_identity_y_cb_cr_601_full_to_y_cb_cr_709_limit = {
324
+ 877, -106, -191,
325
+ 0, 914, 103,
326
+ 0, 67, 920
327
+};
328
+static const struct rk_pq_csc_dc_coef
329
+rk_dc_csc_table_identity_y_cb_cr_601_full_to_y_cb_cr_709_limit = {
330
+ 0, -512, -512,
331
+ 64, 512, 512
332
+};
333
+
334
+/* 709 full -> 601 limit */
335
+static const struct rk_pq_csc_coef rk_csc_table_identity_y_cb_cr_709_full_to_y_cb_cr_601_limit = {
336
+ 877, 91, 176,
337
+ 0, 888, -99,
338
+ 0, -65, 882
339
+};
340
+static const struct rk_pq_csc_dc_coef
341
+rk_dc_csc_table_identity_y_cb_cr_709_full_to_y_cb_cr_601_limit = {
342
+ 0, -512, -512,
343
+ 64, 512, 512
344
+};
345
+
346
+/* xv_ycc BT.601 limit(i.e. SD) -> RGB limit */
347
+static const struct rk_pq_csc_coef rk_csc_table_xv_yccsdy_cb_cr_limit_to_rgb_limit = {
348
+ 1024, 0, 1404,
349
+ 1024, -344, -715,
350
+ 1024, 1774, 0
351
+};
352
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_xv_yccsdy_cb_cr_limit_to_rgb_limit = {
353
+ -64, -512, -512,
354
+ 64, 64, 64
355
+};
356
+
357
+/* BT.709 limit(i.e. HD) -> RGB limit */
358
+static const struct rk_pq_csc_coef rk_csc_table_hdy_cb_cr_limit_to_rgb_limit = {
359
+ 1024, 0, 1577,
360
+ 1024, -188, -469,
361
+ 1024, 1858, 0
362
+};
363
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_hdy_cb_cr_limit_to_rgb_limit = {
364
+ -64, -512, -512,
365
+ 64, 64, 64
366
+};
367
+
368
+/* RGB limit-> YUV601 (i.e. SD) limit */
369
+static const struct rk_pq_csc_coef rk_csc_table_rgb_limit_to_xv_yccsdy_cb_cr = {
370
+ 306, 601, 117,
371
+ -177, -347, 524,
372
+ 524, -439, -85
373
+};
374
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_rgb_limit_to_xv_yccsdy_cb_cr = {
375
+ -64, -64, -64,
376
+ 64, 512, 512
377
+};
378
+
379
+/* RGB limit -> YUV709 (i.e. SD) limit */
380
+static const struct rk_pq_csc_coef rk_csc_table_rgb_limit_to_hdy_cb_cr = {
381
+ 218, 732, 74,
382
+ -120, -404, 524,
383
+ 524, -476, -48
384
+};
385
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_rgb_limit_to_hdy_cb_cr = {
386
+ -64, -64, -64,
387
+ 64, 512, 512
388
+};
389
+
390
+/* xv_ycc BT.601 full(i.e. SD) -> RGB limit */
391
+static const struct rk_pq_csc_coef rk_csc_table_xv_yccsdy_cb_cr_to_rgb_limit = {
392
+ 877, 0, 1229,
393
+ 877, -302, -626,
394
+ 877, 1554, 0
395
+};
396
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_xv_yccsdy_cb_cr_to_rgb_limit = {
397
+ 0, -512, -512,
398
+ 64, 64, 64
399
+};
400
+
401
+/* BT.709 full(i.e. HD) -> RGB limit */
402
+static const struct rk_pq_csc_coef rk_csc_table_hdy_cb_cr_to_rgb_limit = {
403
+ 877, 0, 1381,
404
+ 877, -164, -410,
405
+ 877, 1627, 0
406
+};
407
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_hdy_cb_cr_to_rgb_limit = {
408
+ 0, -512, -512,
409
+ 64, 64, 64
410
+};
411
+
412
+/* RGB limit-> YUV601 full(i.e. SD) */
413
+static const struct rk_pq_csc_coef rk_csc_table_rgb_limit_to_xv_yccsdy_cb_cr_full = {
414
+ 358, 702, 136,
415
+ -202, -396, 598,
416
+ 598, -501, -97
417
+};
418
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_rgb_limit_to_xv_yccsdy_cb_cr_full = {
419
+ -64, -64, -64,
420
+ 0, 512, 512
421
+};
422
+
423
+/* RGB limit-> YUV709 full (i.e. SD) */
424
+static const struct rk_pq_csc_coef rk_csc_table_rgb_limit_to_hdy_cb_cr_full = {
425
+ 254, 855, 86,
426
+ -137, -461, 598,
427
+ 598, -543, -55
428
+};
429
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_rgb_limit_to_hdy_cb_cr_full = {
430
+ -64, -64, -64,
431
+ 0, 512, 512
432
+};
433
+
434
+/* RGB full -> RGB limit */
435
+static const struct rk_pq_csc_coef rk_csc_table_identity_rgb_to_rgb_limit = {
436
+ 877, 0, 0,
437
+ 0, 877, 0,
438
+ 0, 0, 877
439
+};
440
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_rgb_to_rgb_limit = {
441
+ 0, 0, 0,
442
+ 64, 64, 64
443
+};
444
+
445
+/* RGB limit -> RGB full */
446
+static const struct rk_pq_csc_coef rk_csc_table_identity_rgb_limit_to_rgb = {
447
+ 1196, 0, 0,
448
+ 0, 1196, 0,
449
+ 0, 0, 1196
450
+};
451
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_rgb_limit_to_rgb = {
452
+ -64, -64, -64,
453
+ 0, 0, 0
454
+};
455
+
456
+/* RGB limit/full -> RGB limit/full */
457
+static const struct rk_pq_csc_coef rk_csc_table_identity_rgb_to_rgb = {
458
+ 1024, 0, 0,
459
+ 0, 1024, 0,
460
+ 0, 0, 1024
461
+};
462
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_rgb_to_rgb1 = {
463
+ -64, -64, -64,
464
+ 64, 64, 64
465
+};
466
+
467
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_rgb_to_rgb2 = {
468
+ 0, 0, 0,
469
+ 0, 0, 0
470
+};
471
+
472
+static const struct rk_pq_csc_coef rk_csc_table_identity_yuv_to_rgb_2020 = {
473
+ 1024, 0, 1510,
474
+ 1024, -169, -585,
475
+ 1024, 1927, 0
476
+};
477
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_yuv_to_rgb_2020 = {
478
+ 0, -512, -512,
479
+ 0, 0, 0
480
+};
481
+
482
+/* 2020 RGB LIMIT ->YUV LIMIT */
483
+static const struct rk_pq_csc_coef rk_csc_table_identity_rgb_limit_to_yuv_limit_2020 = {
484
+ 269, 694, 61,
485
+ -146, -377, 524,
486
+ 524, -482, -42
487
+};
488
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_rgb_limit_to_yuv_limit_2020 = {
489
+ -64, -64, -64,
490
+ 64, 512, 512
491
+};
492
+
493
+/* 2020 RGB LIMIT ->YUV FULL */
494
+static const struct rk_pq_csc_coef rk_csc_table_identity_rgb_limit_to_yuv_full_2020 = {
495
+ 314, 811, 71,
496
+ -167, -431, 598,
497
+ 598, -550, -48
498
+};
499
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_rgb_limit_to_yuv_full_2020 = {
500
+ -64, -64, -64,
501
+ 0, 512, 512
502
+};
503
+
504
+/* 2020 RGB FULL ->YUV LIMIT */
505
+static const struct rk_pq_csc_coef rk_csc_table_identity_rgb_full_to_yuv_limit_2020 = {
506
+ 230, 595, 52,
507
+ -125, -323, 448,
508
+ 448, -412, -36
509
+};
510
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_rgb_full_to_yuv_limit_2020 = {
511
+ 0, 0, 0,
512
+ 64, 512, 512
513
+};
514
+
515
+/* 2020 RGB FULL ->YUV FULL */
516
+static const struct rk_pq_csc_coef rk_csc_table_identity_rgb_full_to_yuv_full_2020 = {
517
+ 269, 694, 61,
518
+ -143, -369, 512,
519
+ 512, -471, -41
520
+};
521
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_rgb_full_to_yuv_full_2020 = {
522
+ 0, 0, 0,
523
+ 0, 512, 512
524
+};
525
+
526
+/* identity matrix */
527
+static const struct rk_pq_csc_coef rk_csc_table_identity_y_cb_cr_to_y_cb_cr = {
528
+ 1024, 0, 0,
529
+ 0, 1024, 0,
530
+ 0, 0, 1024
531
+};
532
+
533
+/* 10bit Hue Sin Look Up Table -> range[-30, 30] */
534
+static const s32 g_hue_sin_table[PQ_CSC_HUE_TABLE_NUM] = {
535
+ 512, 508, 505, 501, 497, 494, 490, 486,
536
+ 483, 479, 475, 472, 468, 464, 460, 457,
537
+ 453, 449, 445, 442, 438, 434, 430, 426,
538
+ 423, 419, 415, 411, 407, 403, 400, 396,
539
+ 392, 388, 384, 380, 376, 372, 369, 365,
540
+ 361, 357, 353, 349, 345, 341, 337, 333,
541
+ 329, 325, 321, 317, 313, 309, 305, 301,
542
+ 297, 293, 289, 285, 281, 277, 273, 269,
543
+ 265, 261, 257, 253, 249, 245, 241, 237,
544
+ 233, 228, 224, 220, 216, 212, 208, 204,
545
+ 200, 196, 192, 187, 183, 179, 175, 171,
546
+ 167, 163, 159, 154, 150, 146, 142, 138,
547
+ 134, 130, 125, 121, 117, 113, 109, 105,
548
+ 100, 96, 92, 88, 84, 80, 75, 71,
549
+ 67, 63, 59, 54, 50, 46, 42, 38,
550
+ 34, 29, 25, 21, 17, 13, 8, 4,
551
+ 0, -4, -8, -13, -17, -21, -25, -29,
552
+ -34, -38, -42, -46, -50, -54, -59, -63,
553
+ -67, -71, -75, -80, -84, -88, -92, -96,
554
+ -100, -105, -109, -113, -117, -121, -125, -130,
555
+ -134, -138, -142, -146, -150, -154, -159, -163,
556
+ -167, -171, -175, -179, -183, -187, -192, -196,
557
+ -200, -204, -208, -212, -216, -220, -224, -228,
558
+ -233, -237, -241, -245, -249, -253, -257, -261,
559
+ -265, -269, -273, -277, -281, -285, -289, -293,
560
+ -297, -301, -305, -309, -313, -317, -321, -325,
561
+ -329, -333, -337, -341, -345, -349, -353, -357,
562
+ -361, -365, -369, -372, -376, -380, -384, -388,
563
+ -392, -396, -400, -403, -407, -411, -415, -419,
564
+ -423, -426, -430, -434, -438, -442, -445, -449,
565
+ -453, -457, -460, -464, -468, -472, -475, -479,
566
+ -483, -486, -490, -494, -497, -501, -505, -508,
567
+};
568
+
569
+/* 10bit Hue Cos Look Up Table -> range[-30, 30] */
570
+static const s32 g_hue_cos_table[PQ_CSC_HUE_TABLE_NUM] = {
571
+ 887, 889, 891, 893, 895, 897, 899, 901,
572
+ 903, 905, 907, 909, 911, 913, 915, 917,
573
+ 919, 920, 922, 924, 926, 928, 929, 931,
574
+ 933, 935, 936, 938, 940, 941, 943, 945,
575
+ 946, 948, 949, 951, 953, 954, 956, 957,
576
+ 959, 960, 962, 963, 964, 966, 967, 969,
577
+ 970, 971, 973, 974, 975, 976, 978, 979,
578
+ 980, 981, 983, 984, 985, 986, 987, 988,
579
+ 989, 990, 992, 993, 994, 995, 996, 997,
580
+ 998, 998, 999, 1000, 1001, 1002, 1003, 1004,
581
+ 1005, 1005, 1006, 1007, 1008, 1008, 1009, 1010,
582
+ 1011, 1011, 1012, 1013, 1013, 1014, 1014, 1015,
583
+ 1015, 1016, 1016, 1017, 1017, 1018, 1018, 1019,
584
+ 1019, 1020, 1020, 1020, 1021, 1021, 1021, 1022,
585
+ 1022, 1022, 1022, 1023, 1023, 1023, 1023, 1023,
586
+ 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024,
587
+ 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024,
588
+ 1023, 1023, 1023, 1023, 1023, 1022, 1022, 1022,
589
+ 1022, 1021, 1021, 1021, 1020, 1020, 1020, 1019,
590
+ 1019, 1018, 1018, 1017, 1017, 1016, 1016, 1015,
591
+ 1015, 1014, 1014, 1013, 1013, 1012, 1011, 1011,
592
+ 1010, 1009, 1008, 1008, 1007, 1006, 1005, 1005,
593
+ 1004, 1003, 1002, 1001, 1000, 999, 998, 998,
594
+ 997, 996, 995, 994, 993, 992, 990, 989,
595
+ 988, 987, 986, 985, 984, 983, 981, 980,
596
+ 979, 978, 976, 975, 974, 973, 971, 970,
597
+ 969, 967, 966, 964, 963, 962, 960, 959,
598
+ 957, 956, 954, 953, 951, 949, 948, 946,
599
+ 945, 943, 941, 940, 938, 936, 935, 933,
600
+ 931, 929, 928, 926, 924, 922, 920, 919,
601
+ 917, 915, 913, 911, 909, 907, 905, 903,
602
+ 901, 899, 897, 895, 893, 891, 889, 887
603
+};
604
+
605
+/*
606
+ *CSC Param Struct
607
+ */
608
+static const struct rk_csc_mode_coef g_mode_csc_coef[] = {
609
+ {
610
+ RK_PQ_CSC_YUV2RGB_601, "YUV601 L->RGB F",
611
+ &rk_csc_table_xv_yccsdy_cb_cr_limit_to_rgb_full,
612
+ &rk_dc_csc_table_xv_yccsdy_cb_cr_limit_to_rgb_full,
613
+ {
614
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_RGB, false, true
615
+ }
616
+ },
617
+ {
618
+ RK_PQ_CSC_YUV2RGB_709, "YUV709 L->RGB F",
619
+ &rk_csc_table_hdy_cb_cr_limit_to_rgb_full,
620
+ &rk_dc_csc_table_hdy_cb_cr_limit_to_rgb_full,
621
+ {
622
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_RGB, false, true
623
+ }
624
+ },
625
+ {
626
+ RK_PQ_CSC_RGB2YUV_601, "RGB F->YUV601 L",
627
+ &rk_csc_table_rgb_to_xv_yccsdy_cb_cr,
628
+ &rk_dc_csc_table_rgb_to_xv_yccsdy_cb_cr,
629
+ {
630
+ OPTM_CS_E_RGB, OPTM_CS_E_XV_YCC_601, true, false
631
+ }
632
+ },
633
+ {
634
+ RK_PQ_CSC_RGB2YUV_709, "RGB F->YUV709 L",
635
+ &rk_csc_table_rgb_to_hdy_cb_cr,
636
+ &rk_dc_csc_table_rgb_to_hdy_cb_cr,
637
+ {
638
+ OPTM_CS_E_RGB, OPTM_CS_E_ITU_R_BT_709, true, false
639
+ }
640
+ },
641
+ {
642
+ RK_PQ_CSC_YUV2YUV_709_601, "YUV709 L->YUV601 L",
643
+ &rk_csc_table_hdy_cb_cr_to_xv_yccsdy_cb_cr,
644
+ &rk_dc_csc_table_hdy_cb_cr_to_xv_yccsdy_cb_cr,
645
+ {
646
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_XV_YCC_601, false, false
647
+ }
648
+ },
649
+ {
650
+ RK_PQ_CSC_YUV2YUV_601_709, "YUV601 L->YUV709 L",
651
+ &rk_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
652
+ &rk_dc_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
653
+ {
654
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_ITU_R_BT_709, false, false
655
+ }
656
+ },
657
+ {
658
+ RK_PQ_CSC_YUV2YUV, "YUV L->YUV L",
659
+ &rk_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
660
+ &rk_dc_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
661
+ {
662
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_ITU_R_BT_709, false, false
663
+ }
664
+ },
665
+ {
666
+ RK_PQ_CSC_YUV2RGB_601_FULL, "YUV601 F->RGB F",
667
+ &rk_csc_table_xv_yccsdy_cb_cr_to_rgb_full,
668
+ &rk_dc_csc_table_xv_yccsdy_cb_cr_to_rgb_full,
669
+ {
670
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_RGB, true, true
671
+ }
672
+ },
673
+ {
674
+ RK_PQ_CSC_YUV2RGB_709_FULL, "YUV709 F->RGB F",
675
+ &rk_csc_table_hdy_cb_cr_to_rgb_full,
676
+ &rk_dc_csc_table_hdy_cb_cr_to_rgb_full,
677
+ {
678
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_RGB, true, true
679
+ }
680
+ },
681
+ {
682
+ RK_PQ_CSC_RGB2YUV_601_FULL, "RGB F->YUV601 F",
683
+ &rk_csc_table_rgb_to_xv_yccsdy_cb_cr_full,
684
+ &rk_dc_csc_table_rgb_to_xv_yccsdy_cb_cr_full,
685
+ {
686
+ OPTM_CS_E_RGB, OPTM_CS_E_XV_YCC_601, true, true
687
+ }
688
+ },
689
+ {
690
+ RK_PQ_CSC_RGB2YUV_709_FULL, "RGB F->YUV709 F",
691
+ &rk_csc_table_rgb_to_hdy_cb_cr_full,
692
+ &rk_dc_csc_table_rgb_to_hdy_cb_cr_full,
693
+ {
694
+ OPTM_CS_E_RGB, OPTM_CS_E_ITU_R_BT_709, true, true
695
+ }
696
+ },
697
+ {
698
+ RK_PQ_CSC_YUV2YUV_709_601_FULL, "YUV709 F->YUV601 F",
699
+ &rk_csc_table_hdy_cb_cr_to_xv_yccsdy_cb_cr,
700
+ &rk_dc_csc_table_hdy_cb_cr_full_to_xv_yccsdy_cb_cr_full,
701
+ {
702
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_XV_YCC_601, true, true
703
+ }
704
+ },
705
+ {
706
+ RK_PQ_CSC_YUV2YUV_601_709_FULL, "YUV601 F->YUV709 F",
707
+ &rk_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
708
+ &rk_dc_csc_table_hdy_cb_cr_full_to_xv_yccsdy_cb_cr_full,
709
+ {
710
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_ITU_R_BT_709, true, true
711
+ }
712
+ },
713
+ {
714
+ RK_PQ_CSC_YUV2YUV_FULL, "YUV F->YUV F",
715
+ &rk_csc_table_identity_y_cb_cr_to_y_cb_cr,
716
+ &rk_dc_csc_table_hdy_cb_cr_full_to_xv_yccsdy_cb_cr_full,
717
+ {
718
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_ITU_R_BT_709, true, true
719
+ }
720
+ },
721
+ {
722
+ RK_PQ_CSC_YUV2YUV_LIMIT2FULL, "YUV L->YUV F",
723
+ &rk_csc_table_identity_y_cb_cr_limit_to_y_cb_cr_full,
724
+ &rk_dc_csc_table_identity_y_cb_cr_limit_to_y_cb_cr_full,
725
+ {
726
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_ITU_R_BT_709, false, true
727
+ }
728
+ },
729
+ {
730
+ RK_PQ_CSC_YUV2YUV_601_709_LIMIT2FULL, "YUV601 L->YUV709 F",
731
+ &rk_csc_table_identity_601_limit_to_709_full,
732
+ &rk_dc_csc_table_identity_601_limit_to_709_full,
733
+ {
734
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_ITU_R_BT_709, false, true
735
+ }
736
+ },
737
+ {
738
+ RK_PQ_CSC_YUV2YUV_709_601_LIMIT2FULL, "YUV709 L->YUV601 F",
739
+ &rk_csc_table_identity_709_limit_to_601_full,
740
+ &rk_dc_csc_table_identity_709_limit_to_601_full,
741
+ {
742
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_XV_YCC_601, false, true
743
+ }
744
+ },
745
+ {
746
+ RK_PQ_CSC_YUV2YUV_FULL2LIMIT, "YUV F->YUV L",
747
+ &rk_csc_table_identity_y_cb_cr_full_to_y_cb_cr_limit,
748
+ &rk_dc_csc_table_identity_y_cb_cr_full_to_y_cb_cr_limit,
749
+ {
750
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_ITU_R_BT_709, true, false
751
+ }
752
+ },
753
+ {
754
+ RK_PQ_CSC_YUV2YUV_601_709_FULL2LIMIT, "YUV601 F->YUV709 L",
755
+ &rk_csc_table_identity_y_cb_cr_601_full_to_y_cb_cr_709_limit,
756
+ &rk_dc_csc_table_identity_y_cb_cr_601_full_to_y_cb_cr_709_limit,
757
+ {
758
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_ITU_R_BT_709, true, false
759
+ }
760
+ },
761
+ {
762
+ RK_PQ_CSC_YUV2YUV_709_601_FULL2LIMIT, "YUV709 F->YUV601 L",
763
+ &rk_csc_table_identity_y_cb_cr_709_full_to_y_cb_cr_601_limit,
764
+ &rk_dc_csc_table_identity_y_cb_cr_709_full_to_y_cb_cr_601_limit,
765
+ {
766
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_XV_YCC_601, true, false
767
+ }
768
+ },
769
+ {
770
+ RK_PQ_CSC_YUV2RGBL_601, "YUV601 L->RGB L",
771
+ &rk_csc_table_xv_yccsdy_cb_cr_limit_to_rgb_limit,
772
+ &rk_dc_csc_table_xv_yccsdy_cb_cr_limit_to_rgb_limit,
773
+ {
774
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_RGB, false, false
775
+ }
776
+ },
777
+ {
778
+ RK_PQ_CSC_YUV2RGBL_709, "YUV709 L->RGB L",
779
+ &rk_csc_table_hdy_cb_cr_limit_to_rgb_limit,
780
+ &rk_dc_csc_table_hdy_cb_cr_limit_to_rgb_limit,
781
+ {
782
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_RGB, false, false
783
+ }
784
+ },
785
+ {
786
+ RK_PQ_CSC_RGBL2YUV_601, "RGB L->YUV601 L",
787
+ &rk_csc_table_rgb_limit_to_xv_yccsdy_cb_cr,
788
+ &rk_dc_csc_table_rgb_limit_to_xv_yccsdy_cb_cr,
789
+ {
790
+ OPTM_CS_E_RGB, OPTM_CS_E_XV_YCC_601, false, false
791
+ }
792
+ },
793
+ {
794
+ RK_PQ_CSC_RGBL2YUV_709, "RGB L->YUV709 L",
795
+ &rk_csc_table_rgb_limit_to_hdy_cb_cr,
796
+ &rk_dc_csc_table_rgb_limit_to_hdy_cb_cr,
797
+ {
798
+ OPTM_CS_E_RGB, OPTM_CS_E_ITU_R_BT_709, false, false
799
+ }
800
+ },
801
+ {
802
+ RK_PQ_CSC_YUV2RGBL_601_FULL, "YUV601 F->RGB L",
803
+ &rk_csc_table_xv_yccsdy_cb_cr_to_rgb_limit,
804
+ &rk_dc_csc_table_xv_yccsdy_cb_cr_to_rgb_limit,
805
+ {
806
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_RGB, true, false
807
+ }
808
+ },
809
+ {
810
+ RK_PQ_CSC_YUV2RGBL_709_FULL, "YUV709 F->RGB L",
811
+ &rk_csc_table_hdy_cb_cr_to_rgb_limit,
812
+ &rk_dc_csc_table_hdy_cb_cr_to_rgb_limit,
813
+ {
814
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_RGB, true, false
815
+ }
816
+ },
817
+ {
818
+ RK_PQ_CSC_RGBL2YUV_601_FULL, "RGB L->YUV601 F",
819
+ &rk_csc_table_rgb_limit_to_xv_yccsdy_cb_cr_full,
820
+ &rk_dc_csc_table_rgb_limit_to_xv_yccsdy_cb_cr_full,
821
+ {
822
+ OPTM_CS_E_RGB, OPTM_CS_E_XV_YCC_601, false, true
823
+ }
824
+ },
825
+ {
826
+ RK_PQ_CSC_RGBL2YUV_709_FULL, "RGB L->YUV709 F",
827
+ &rk_csc_table_rgb_limit_to_hdy_cb_cr_full,
828
+ &rk_dc_csc_table_rgb_limit_to_hdy_cb_cr_full,
829
+ {
830
+ OPTM_CS_E_RGB, OPTM_CS_E_ITU_R_BT_709, false, true
831
+ }
832
+ },
833
+ {
834
+ RK_PQ_CSC_RGB2RGBL, "RGB F->RGB L",
835
+ &rk_csc_table_identity_rgb_to_rgb_limit,
836
+ &rk_dc_csc_table_identity_rgb_to_rgb_limit,
837
+ {
838
+ OPTM_CS_E_RGB, OPTM_CS_E_RGB, true, false
839
+ }
840
+ },
841
+ {
842
+ RK_PQ_CSC_RGBL2RGB, "RGB L->RGB F",
843
+ &rk_csc_table_identity_rgb_limit_to_rgb,
844
+ &rk_dc_csc_table_identity_rgb_limit_to_rgb,
845
+ {
846
+ OPTM_CS_E_RGB, OPTM_CS_E_RGB, false, true
847
+ }
848
+ },
849
+ {
850
+ RK_PQ_CSC_RGBL2RGBL, "RGB L->RGB L",
851
+ &rk_csc_table_identity_rgb_to_rgb,
852
+ &rk_dc_csc_table_identity_rgb_to_rgb1,
853
+ {
854
+ OPTM_CS_E_RGB, OPTM_CS_E_RGB, false, false
855
+ }
856
+ },
857
+ {
858
+ RK_PQ_CSC_RGB2RGB, "RGB F->RGB F",
859
+ &rk_csc_table_identity_rgb_to_rgb,
860
+ &rk_dc_csc_table_identity_rgb_to_rgb2,
861
+ {
862
+ OPTM_CS_E_RGB, OPTM_CS_E_RGB, true, true
863
+ }
864
+ },
865
+ {
866
+ RK_PQ_CSC_YUV2RGB_2020, "YUV2020 F->RGB2020 F",
867
+ &rk_csc_table_identity_yuv_to_rgb_2020,
868
+ &rk_dc_csc_table_identity_yuv_to_rgb_2020,
869
+ {
870
+ OPTM_CS_E_XV_YCC_2020, OPTM_CS_E_RGB_2020, true, true
871
+ }
872
+ },
873
+ {
874
+ RK_PQ_CSC_RGB2YUV2020_LIMIT2FULL, "RGB2020 L->YUV2020 F",
875
+ &rk_csc_table_identity_rgb_limit_to_yuv_full_2020,
876
+ &rk_dc_csc_table_identity_rgb_limit_to_yuv_full_2020,
877
+ {
878
+ OPTM_CS_E_RGB_2020, OPTM_CS_E_XV_YCC_2020, false, true
879
+ }
880
+ },
881
+ {
882
+ RK_PQ_CSC_RGB2YUV2020_LIMIT, "RGB2020 L->YUV2020 L",
883
+ &rk_csc_table_identity_rgb_limit_to_yuv_limit_2020,
884
+ &rk_dc_csc_table_identity_rgb_limit_to_yuv_limit_2020,
885
+ {
886
+ OPTM_CS_E_RGB_2020, OPTM_CS_E_XV_YCC_2020, false, false
887
+ }
888
+ },
889
+ {
890
+ RK_PQ_CSC_RGB2YUV2020_FULL2LIMIT, "RGB2020 F->YUV2020 L",
891
+ &rk_csc_table_identity_rgb_full_to_yuv_limit_2020,
892
+ &rk_dc_csc_table_identity_rgb_full_to_yuv_limit_2020,
893
+ {
894
+ OPTM_CS_E_RGB_2020, OPTM_CS_E_XV_YCC_2020, true, false
895
+ }
896
+ },
897
+ {
898
+ RK_PQ_CSC_RGB2YUV2020_FULL, "RGB2020 F->YUV2020 F",
899
+ &rk_csc_table_identity_rgb_full_to_yuv_full_2020,
900
+ &rk_dc_csc_table_identity_rgb_full_to_yuv_full_2020,
901
+ {
902
+ OPTM_CS_E_RGB_2020, OPTM_CS_E_XV_YCC_2020, true, true
903
+ }
904
+ },
905
+ {
906
+ RK_PQ_CSC_YUV2YUV, "YUV 601 L->YUV 601 L",
907
+ &rk_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
908
+ &rk_dc_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
909
+ {
910
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_XV_YCC_601, false, false
911
+ }
912
+ },
913
+ {
914
+ RK_PQ_CSC_YUV2YUV_FULL, "YUV 601 F->YUV 601 F",
915
+ &rk_csc_table_identity_y_cb_cr_to_y_cb_cr,
916
+ &rk_dc_csc_table_hdy_cb_cr_full_to_xv_yccsdy_cb_cr_full,
917
+ {
918
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_XV_YCC_601, true, true
919
+ }
920
+ },
921
+ {
922
+ RK_PQ_CSC_YUV2YUV_LIMIT2FULL, "YUV 601 L->YUV 601 F",
923
+ &rk_csc_table_identity_y_cb_cr_limit_to_y_cb_cr_full,
924
+ &rk_dc_csc_table_identity_y_cb_cr_limit_to_y_cb_cr_full,
925
+ {
926
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_XV_YCC_601, false, true
927
+ }
928
+ },
929
+ {
930
+ RK_PQ_CSC_YUV2YUV_FULL2LIMIT, "YUV 601 F->YUV 601 L",
931
+ &rk_csc_table_identity_y_cb_cr_full_to_y_cb_cr_limit,
932
+ &rk_dc_csc_table_identity_y_cb_cr_full_to_y_cb_cr_limit,
933
+ {
934
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_XV_YCC_601, true, false
935
+ }
936
+ },
937
+ {
938
+ RK_PQ_CSC_YUV2YUV, "YUV 2020 L->YUV 2020 L",
939
+ &rk_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
940
+ &rk_dc_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
941
+ {
942
+ OPTM_CS_E_XV_YCC_2020, OPTM_CS_E_XV_YCC_2020, false, false
943
+ }
944
+ },
945
+ {
946
+ RK_PQ_CSC_YUV2YUV_FULL, "YUV 2020 F->YUV 2020 F",
947
+ &rk_csc_table_identity_y_cb_cr_to_y_cb_cr,
948
+ &rk_dc_csc_table_hdy_cb_cr_full_to_xv_yccsdy_cb_cr_full,
949
+ {
950
+ OPTM_CS_E_XV_YCC_2020, OPTM_CS_E_XV_YCC_2020, true, true
951
+ }
952
+ },
953
+ {
954
+ RK_PQ_CSC_YUV2YUV_LIMIT2FULL, "YUV 2020 L->YUV 2020 F",
955
+ &rk_csc_table_identity_y_cb_cr_limit_to_y_cb_cr_full,
956
+ &rk_dc_csc_table_identity_y_cb_cr_limit_to_y_cb_cr_full,
957
+ {
958
+ OPTM_CS_E_XV_YCC_2020, OPTM_CS_E_XV_YCC_2020, false, true
959
+ }
960
+ },
961
+ {
962
+ RK_PQ_CSC_YUV2YUV_FULL2LIMIT, "YUV 2020 F->YUV 2020 L",
963
+ &rk_csc_table_identity_y_cb_cr_full_to_y_cb_cr_limit,
964
+ &rk_dc_csc_table_identity_y_cb_cr_full_to_y_cb_cr_limit,
965
+ {
966
+ OPTM_CS_E_XV_YCC_2020, OPTM_CS_E_XV_YCC_2020, true, false
967
+ }
968
+ },
969
+ {
970
+ RK_PQ_CSC_RGB2RGBL, "RGB 2020 F->RGB 2020 L",
971
+ &rk_csc_table_identity_rgb_to_rgb_limit,
972
+ &rk_dc_csc_table_identity_rgb_to_rgb_limit,
973
+ {
974
+ OPTM_CS_E_RGB_2020, OPTM_CS_E_RGB_2020, true, false
975
+ }
976
+ },
977
+ {
978
+ RK_PQ_CSC_RGBL2RGB, "RGB 2020 L->RGB 2020 F",
979
+ &rk_csc_table_identity_rgb_limit_to_rgb,
980
+ &rk_dc_csc_table_identity_rgb_limit_to_rgb,
981
+ {
982
+ OPTM_CS_E_RGB_2020, OPTM_CS_E_RGB_2020, false, true
983
+ }
984
+ },
985
+ {
986
+ RK_PQ_CSC_RGBL2RGBL, "RGB 2020 L->RGB 2020 L",
987
+ &rk_csc_table_identity_rgb_to_rgb,
988
+ &rk_dc_csc_table_identity_rgb_to_rgb1,
989
+ {
990
+ OPTM_CS_E_RGB_2020, OPTM_CS_E_RGB_2020, false, false
991
+ }
992
+ },
993
+ {
994
+ RK_PQ_CSC_RGB2RGB, "RGB 2020 F->RGB 2020 F",
995
+ &rk_csc_table_identity_rgb_to_rgb,
996
+ &rk_dc_csc_table_identity_rgb_to_rgb2,
997
+ {
998
+ OPTM_CS_E_RGB_2020, OPTM_CS_E_RGB_2020, true, true
999
+ }
1000
+ },
1001
+};
1002
+
1003
+struct csc_mapping {
1004
+ enum vop_csc_format csc_format;
1005
+ enum color_space_type rgb_color_space;
1006
+ enum color_space_type yuv_color_space;
1007
+ bool rgb_full_range;
1008
+ bool yuv_full_range;
1009
+};
1010
+
1011
+static const struct csc_mapping csc_mapping_table[] = {
1012
+ {
1013
+ CSC_BT601L,
1014
+ OPTM_CS_E_RGB,
1015
+ OPTM_CS_E_XV_YCC_601,
1016
+ true,
1017
+ false,
1018
+ },
1019
+ {
1020
+ CSC_BT709L,
1021
+ OPTM_CS_E_RGB,
1022
+ OPTM_CS_E_XV_YCC_709,
1023
+ true,
1024
+ false,
1025
+ },
1026
+ {
1027
+ CSC_BT601F,
1028
+ OPTM_CS_E_RGB,
1029
+ OPTM_CS_E_XV_YCC_601,
1030
+ true,
1031
+ true,
1032
+ },
1033
+ {
1034
+ CSC_BT2020,
1035
+ OPTM_CS_E_RGB_2020,
1036
+ OPTM_CS_E_XV_YCC_2020,
1037
+ true,
1038
+ true,
1039
+ },
1040
+ {
1041
+ CSC_BT709L_13BIT,
1042
+ OPTM_CS_E_RGB,
1043
+ OPTM_CS_E_XV_YCC_709,
1044
+ true,
1045
+ false,
1046
+ },
1047
+ {
1048
+ CSC_BT709F_13BIT,
1049
+ OPTM_CS_E_RGB,
1050
+ OPTM_CS_E_XV_YCC_709,
1051
+ true,
1052
+ true,
1053
+ },
1054
+ {
1055
+ CSC_BT2020L_13BIT,
1056
+ OPTM_CS_E_RGB_2020,
1057
+ OPTM_CS_E_XV_YCC_2020,
1058
+ true,
1059
+ false,
1060
+ },
1061
+ {
1062
+ CSC_BT2020F_13BIT,
1063
+ OPTM_CS_E_RGB_2020,
1064
+ OPTM_CS_E_XV_YCC_2020,
1065
+ true,
1066
+ true,
1067
+ },
1068
+};
1069
+
1070
+static const struct rk_pq_csc_coef r2y_for_y2y = {
1071
+ 306, 601, 117,
1072
+ -151, -296, 446,
1073
+ 630, -527, -102,
1074
+};
1075
+
1076
+static const struct rk_pq_csc_coef y2r_for_y2y = {
1077
+ 1024, -0, 1167,
1078
+ 1024, -404, -594,
1079
+ 1024, 2081, -1,
1080
+};
1081
+
1082
+static const struct rk_pq_csc_coef rgb_input_swap_matrix = {
1083
+ 0, 0, 1,
1084
+ 1, 0, 0,
1085
+ 0, 1, 0,
1086
+};
1087
+
1088
+static const struct rk_pq_csc_coef yuv_output_swap_matrix = {
1089
+ 0, 0, 1,
1090
+ 1, 0, 0,
1091
+ 0, 1, 0,
1092
+};
1093
+
1094
+static int csc_get_mode_index(int post_csc_mode, bool is_input_yuv, bool is_output_yuv)
1095
+{
1096
+ const struct rk_csc_colorspace_info *colorspace_info;
1097
+ enum color_space_type input_color_space;
1098
+ enum color_space_type output_color_space;
1099
+ bool is_input_full_range;
1100
+ bool is_output_full_range;
1101
+ int i;
1102
+
1103
+ for (i = 0; i < ARRAY_SIZE(csc_mapping_table); i++) {
1104
+ if (post_csc_mode == csc_mapping_table[i].csc_format) {
1105
+ input_color_space = is_input_yuv ? csc_mapping_table[i].yuv_color_space :
1106
+ csc_mapping_table[i].rgb_color_space;
1107
+ is_input_full_range = is_input_yuv ? csc_mapping_table[i].yuv_full_range :
1108
+ csc_mapping_table[i].rgb_full_range;
1109
+ output_color_space = is_output_yuv ? csc_mapping_table[i].yuv_color_space :
1110
+ csc_mapping_table[i].rgb_color_space;
1111
+ is_output_full_range = is_output_yuv ? csc_mapping_table[i].yuv_full_range :
1112
+ csc_mapping_table[i].rgb_full_range;
1113
+ break;
1114
+ }
1115
+ }
1116
+ if (i >= ARRAY_SIZE(csc_mapping_table))
1117
+ return -EINVAL;
1118
+
1119
+ for (i = 0; i < ARRAY_SIZE(g_mode_csc_coef); i++) {
1120
+ colorspace_info = &g_mode_csc_coef[i].st_csc_color_info;
1121
+ if (colorspace_info->input_color_space == input_color_space &&
1122
+ colorspace_info->output_color_space == output_color_space &&
1123
+ colorspace_info->in_full_range == is_input_full_range &&
1124
+ colorspace_info->out_full_range == is_output_full_range)
1125
+ return i;
1126
+ }
1127
+
1128
+ return -EINVAL;
1129
+}
1130
+
1131
+static void csc_matrix_multiply(struct rk_pq_csc_coef *dst, const struct rk_pq_csc_coef *m0,
1132
+ const struct rk_pq_csc_coef *m1)
1133
+{
1134
+ dst->csc_coef00 = m0->csc_coef00 * m1->csc_coef00 +
1135
+ m0->csc_coef01 * m1->csc_coef10 +
1136
+ m0->csc_coef02 * m1->csc_coef20;
1137
+
1138
+ dst->csc_coef01 = m0->csc_coef00 * m1->csc_coef01 +
1139
+ m0->csc_coef01 * m1->csc_coef11 +
1140
+ m0->csc_coef02 * m1->csc_coef21;
1141
+
1142
+ dst->csc_coef02 = m0->csc_coef00 * m1->csc_coef02 +
1143
+ m0->csc_coef01 * m1->csc_coef12 +
1144
+ m0->csc_coef02 * m1->csc_coef22;
1145
+
1146
+ dst->csc_coef10 = m0->csc_coef10 * m1->csc_coef00 +
1147
+ m0->csc_coef11 * m1->csc_coef10 +
1148
+ m0->csc_coef12 * m1->csc_coef20;
1149
+
1150
+ dst->csc_coef11 = m0->csc_coef10 * m1->csc_coef01 +
1151
+ m0->csc_coef11 * m1->csc_coef11 +
1152
+ m0->csc_coef12 * m1->csc_coef21;
1153
+
1154
+ dst->csc_coef12 = m0->csc_coef10 * m1->csc_coef02 +
1155
+ m0->csc_coef11 * m1->csc_coef12 +
1156
+ m0->csc_coef12 * m1->csc_coef22;
1157
+
1158
+ dst->csc_coef20 = m0->csc_coef20 * m1->csc_coef00 +
1159
+ m0->csc_coef21 * m1->csc_coef10 +
1160
+ m0->csc_coef22 * m1->csc_coef20;
1161
+
1162
+ dst->csc_coef21 = m0->csc_coef20 * m1->csc_coef01 +
1163
+ m0->csc_coef21 * m1->csc_coef11 +
1164
+ m0->csc_coef22 * m1->csc_coef21;
1165
+
1166
+ dst->csc_coef22 = m0->csc_coef20 * m1->csc_coef02 +
1167
+ m0->csc_coef21 * m1->csc_coef12 +
1168
+ m0->csc_coef22 * m1->csc_coef22;
1169
+}
1170
+
1171
+static void csc_matrix_ventor_multiply(struct rk_pq_csc_ventor *dst,
1172
+ const struct rk_pq_csc_coef *m0,
1173
+ const struct rk_pq_csc_ventor *v0)
1174
+{
1175
+ dst->csc_offset0 = m0->csc_coef00 * v0->csc_offset0 +
1176
+ m0->csc_coef01 * v0->csc_offset1 +
1177
+ m0->csc_coef02 * v0->csc_offset2;
1178
+
1179
+ dst->csc_offset1 = m0->csc_coef10 * v0->csc_offset0 +
1180
+ m0->csc_coef11 * v0->csc_offset1 +
1181
+ m0->csc_coef12 * v0->csc_offset2;
1182
+
1183
+ dst->csc_offset2 = m0->csc_coef20 * v0->csc_offset0 +
1184
+ m0->csc_coef21 * v0->csc_offset1 +
1185
+ m0->csc_coef22 * v0->csc_offset2;
1186
+}
1187
+
1188
+static void csc_matrix_element_left_shift(struct rk_pq_csc_coef *m, int n)
1189
+{
1190
+ m->csc_coef00 = m->csc_coef00 >> n;
1191
+ m->csc_coef01 = m->csc_coef01 >> n;
1192
+ m->csc_coef02 = m->csc_coef02 >> n;
1193
+ m->csc_coef10 = m->csc_coef10 >> n;
1194
+ m->csc_coef11 = m->csc_coef11 >> n;
1195
+ m->csc_coef12 = m->csc_coef12 >> n;
1196
+ m->csc_coef20 = m->csc_coef20 >> n;
1197
+ m->csc_coef21 = m->csc_coef21 >> n;
1198
+ m->csc_coef22 = m->csc_coef22 >> n;
1199
+}
1200
+
1201
+static struct rk_pq_csc_coef create_rgb_gain_matrix(s32 r_gain, s32 g_gain, s32 b_gain)
1202
+{
1203
+ struct rk_pq_csc_coef m;
1204
+
1205
+ m.csc_coef00 = r_gain;
1206
+ m.csc_coef01 = 0;
1207
+ m.csc_coef02 = 0;
1208
+
1209
+ m.csc_coef10 = 0;
1210
+ m.csc_coef11 = g_gain;
1211
+ m.csc_coef12 = 0;
1212
+
1213
+ m.csc_coef20 = 0;
1214
+ m.csc_coef21 = 0;
1215
+ m.csc_coef22 = b_gain;
1216
+
1217
+ return m;
1218
+}
1219
+
1220
+static struct rk_pq_csc_coef create_contrast_matrix(s32 contrast)
1221
+{
1222
+ struct rk_pq_csc_coef m;
1223
+
1224
+ m.csc_coef00 = contrast;
1225
+ m.csc_coef01 = 0;
1226
+ m.csc_coef02 = 0;
1227
+
1228
+ m.csc_coef10 = 0;
1229
+ m.csc_coef11 = contrast;
1230
+ m.csc_coef12 = 0;
1231
+
1232
+ m.csc_coef20 = 0;
1233
+ m.csc_coef21 = 0;
1234
+ m.csc_coef22 = contrast;
1235
+
1236
+ return m;
1237
+}
1238
+
1239
+static struct rk_pq_csc_coef create_hue_matrix(s32 hue)
1240
+{
1241
+ struct rk_pq_csc_coef m;
1242
+ s32 hue_idx;
1243
+ s32 sin_hue;
1244
+ s32 cos_hue;
1245
+
1246
+ hue_idx = CLIP(hue / PQ_CSC_HUE_TABLE_DIV_COEF, 0, PQ_CSC_HUE_TABLE_NUM - 1);
1247
+ sin_hue = g_hue_sin_table[hue_idx];
1248
+ cos_hue = g_hue_cos_table[hue_idx];
1249
+
1250
+ m.csc_coef00 = 1024;
1251
+ m.csc_coef01 = 0;
1252
+ m.csc_coef02 = 0;
1253
+
1254
+ m.csc_coef10 = 0;
1255
+ m.csc_coef11 = cos_hue;
1256
+ m.csc_coef12 = sin_hue;
1257
+
1258
+ m.csc_coef20 = 0;
1259
+ m.csc_coef21 = -sin_hue;
1260
+ m.csc_coef22 = cos_hue;
1261
+
1262
+ return m;
1263
+}
1264
+
1265
+static struct rk_pq_csc_coef create_saturation_matrix(s32 saturation)
1266
+{
1267
+ struct rk_pq_csc_coef m;
1268
+
1269
+ m.csc_coef00 = 512;
1270
+ m.csc_coef01 = 0;
1271
+ m.csc_coef02 = 0;
1272
+
1273
+ m.csc_coef10 = 0;
1274
+ m.csc_coef11 = saturation;
1275
+ m.csc_coef12 = 0;
1276
+
1277
+ m.csc_coef20 = 0;
1278
+ m.csc_coef21 = 0;
1279
+ m.csc_coef22 = saturation;
1280
+
1281
+ return m;
1282
+}
1283
+
1284
+static int csc_calc_adjust_output_coef(bool is_input_yuv, bool is_output_yuv,
1285
+ struct csc_info *csc_input_cfg,
1286
+ const struct rk_csc_mode_coef *csc_mode_cfg,
1287
+ struct rk_pq_csc_coef *out_matrix,
1288
+ struct rk_pq_csc_ventor *out_dc)
1289
+{
1290
+ struct rk_pq_csc_coef gain_matrix;
1291
+ struct rk_pq_csc_coef contrast_matrix;
1292
+ struct rk_pq_csc_coef hue_matrix;
1293
+ struct rk_pq_csc_coef saturation_matrix;
1294
+ struct rk_pq_csc_coef temp0, temp1;
1295
+ const struct rk_pq_csc_coef *r2y_matrix;
1296
+ const struct rk_pq_csc_coef *y2r_matrix;
1297
+ struct rk_pq_csc_ventor dc_in_ventor;
1298
+ struct rk_pq_csc_ventor dc_out_ventor;
1299
+ struct rk_pq_csc_ventor v;
1300
+ const struct rk_csc_colorspace_info *color_info;
1301
+ s32 contrast, saturation, brightness;
1302
+ s32 r_gain, g_gain, b_gain;
1303
+ s32 r_offset, g_offset, b_offset;
1304
+ s32 dc_in_offset, dc_out_offset;
1305
+
1306
+ contrast = csc_input_cfg->contrast * PQ_CSC_PARAM_FIX_NUM / PQ_CSC_IN_PARAM_NORM_COEF;
1307
+ saturation = csc_input_cfg->saturation * PQ_CSC_PARAM_FIX_NUM / PQ_CSC_IN_PARAM_NORM_COEF;
1308
+ r_gain = csc_input_cfg->r_gain * PQ_CSC_PARAM_FIX_NUM / PQ_CSC_IN_PARAM_NORM_COEF;
1309
+ g_gain = csc_input_cfg->g_gain * PQ_CSC_PARAM_FIX_NUM / PQ_CSC_IN_PARAM_NORM_COEF;
1310
+ b_gain = csc_input_cfg->b_gain * PQ_CSC_PARAM_FIX_NUM / PQ_CSC_IN_PARAM_NORM_COEF;
1311
+ r_offset = ((s32)csc_input_cfg->r_offset - PQ_CSC_BRIGHTNESS_OFFSET) /
1312
+ PQ_CSC_TEMP_OFFSET_DIV_COEF;
1313
+ g_offset = ((s32)csc_input_cfg->g_offset - PQ_CSC_BRIGHTNESS_OFFSET) /
1314
+ PQ_CSC_TEMP_OFFSET_DIV_COEF;
1315
+ b_offset = ((s32)csc_input_cfg->b_offset - PQ_CSC_BRIGHTNESS_OFFSET) /
1316
+ PQ_CSC_TEMP_OFFSET_DIV_COEF;
1317
+
1318
+ gain_matrix = create_rgb_gain_matrix(r_gain, g_gain, b_gain);
1319
+ contrast_matrix = create_contrast_matrix(contrast);
1320
+ hue_matrix = create_hue_matrix(csc_input_cfg->hue);
1321
+ saturation_matrix = create_saturation_matrix(saturation);
1322
+
1323
+ color_info = &csc_mode_cfg->st_csc_color_info;
1324
+ brightness = (s32)csc_input_cfg->brightness - PQ_CSC_BRIGHTNESS_OFFSET;
1325
+ dc_in_offset = color_info->in_full_range ? 0 : -PQ_CSC_DC_IN_OFFSET;
1326
+ dc_out_offset = color_info->out_full_range ? 0 : PQ_CSC_DC_IN_OFFSET;
1327
+
1328
+ /*
1329
+ * M0 = hue_matrix * saturation_matrix,
1330
+ * M1 = gain_matrix * constrast_matrix,
1331
+ */
1332
+
1333
+ if (is_input_yuv && is_output_yuv) {
1334
+ /*
1335
+ * yuv2yuv: output = T * M0 * N_r2y * M1 * N_y2r,
1336
+ * so output = T * hue_matrix * saturation_matrix *
1337
+ * N_r2y * gain_matrix * contrast_matrix * N_y2r
1338
+ */
1339
+ r2y_matrix = &r2y_for_y2y;
1340
+ y2r_matrix = &y2r_for_y2y;
1341
+ csc_matrix_multiply(&temp0, csc_mode_cfg->pst_csc_coef, &hue_matrix);
1342
+ /*
1343
+ * The value bits width is 32 bit, so every time 2 matirx multifly,
1344
+ * left shift is necessary to avoid overflow. For enhancing the
1345
+ * calculator precision, PQ_CALC_ENHANCE_BIT bits is reserved and
1346
+ * left shift before get the final result.
1347
+ */
1348
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_FIX_BIT_WIDTH -
1349
+ PQ_CALC_ENHANCE_BIT);
1350
+ csc_matrix_multiply(&temp1, &temp0, &saturation_matrix);
1351
+ csc_matrix_element_left_shift(&temp1, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
1352
+ csc_matrix_multiply(&temp0, &temp1, r2y_matrix);
1353
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_FIX_BIT_WIDTH);
1354
+ csc_matrix_multiply(&temp1, &temp0, &gain_matrix);
1355
+ csc_matrix_element_left_shift(&temp1, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
1356
+ csc_matrix_multiply(&temp0, &temp1, &contrast_matrix);
1357
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
1358
+ csc_matrix_multiply(out_matrix, &temp0, y2r_matrix);
1359
+ csc_matrix_element_left_shift(out_matrix, PQ_CSC_PARAM_FIX_BIT_WIDTH +
1360
+ PQ_CALC_ENHANCE_BIT);
1361
+
1362
+ dc_in_ventor.csc_offset0 = dc_in_offset;
1363
+ dc_in_ventor.csc_offset1 = -PQ_CSC_DC_IN_OUT_DEFAULT;
1364
+ dc_in_ventor.csc_offset2 = -PQ_CSC_DC_IN_OUT_DEFAULT;
1365
+ dc_out_ventor.csc_offset0 = brightness + dc_out_offset;
1366
+ dc_out_ventor.csc_offset1 = PQ_CSC_DC_IN_OUT_DEFAULT;
1367
+ dc_out_ventor.csc_offset2 = PQ_CSC_DC_IN_OUT_DEFAULT;
1368
+ } else if (is_input_yuv && !is_output_yuv) {
1369
+ /*
1370
+ * yuv2rgb: output = M1 * T * M0,
1371
+ * so output = gain_matrix * contrast_matrix * T *
1372
+ * hue_matrix * saturation_matrix
1373
+ */
1374
+ csc_matrix_multiply(&temp0, csc_mode_cfg->pst_csc_coef, &hue_matrix);
1375
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_FIX_BIT_WIDTH -
1376
+ PQ_CALC_ENHANCE_BIT);
1377
+ csc_matrix_multiply(&temp1, &temp0, &saturation_matrix);
1378
+ csc_matrix_element_left_shift(&temp1, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
1379
+ csc_matrix_multiply(&temp0, &contrast_matrix, &temp1);
1380
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
1381
+ csc_matrix_multiply(out_matrix, &gain_matrix, &temp0);
1382
+ csc_matrix_element_left_shift(out_matrix, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH +
1383
+ PQ_CALC_ENHANCE_BIT);
1384
+
1385
+ dc_in_ventor.csc_offset0 = dc_in_offset;
1386
+ dc_in_ventor.csc_offset1 = -PQ_CSC_DC_IN_OUT_DEFAULT;
1387
+ dc_in_ventor.csc_offset2 = -PQ_CSC_DC_IN_OUT_DEFAULT;
1388
+ dc_out_ventor.csc_offset0 = brightness + dc_out_offset + r_offset;
1389
+ dc_out_ventor.csc_offset1 = brightness + dc_out_offset + g_offset;
1390
+ dc_out_ventor.csc_offset2 = brightness + dc_out_offset + b_offset;
1391
+ } else if (!is_input_yuv && is_output_yuv) {
1392
+ /*
1393
+ * rgb2yuv: output = M0 * T * M1,
1394
+ * so output = hue_matrix * saturation_matrix * T *
1395
+ * gain_matrix * contrast_matrix
1396
+ */
1397
+ csc_matrix_multiply(&temp0, csc_mode_cfg->pst_csc_coef, &gain_matrix);
1398
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH -
1399
+ PQ_CALC_ENHANCE_BIT);
1400
+ csc_matrix_multiply(&temp1, &temp0, &contrast_matrix);
1401
+ csc_matrix_element_left_shift(&temp1, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
1402
+ csc_matrix_multiply(&temp0, &saturation_matrix, &temp1);
1403
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
1404
+ csc_matrix_multiply(out_matrix, &hue_matrix, &temp0);
1405
+ csc_matrix_element_left_shift(out_matrix, PQ_CSC_PARAM_FIX_BIT_WIDTH +
1406
+ PQ_CALC_ENHANCE_BIT);
1407
+
1408
+ dc_in_ventor.csc_offset0 = dc_in_offset;
1409
+ dc_in_ventor.csc_offset1 = dc_in_offset;
1410
+ dc_in_ventor.csc_offset2 = dc_in_offset;
1411
+ dc_out_ventor.csc_offset0 = brightness + dc_out_offset;
1412
+ dc_out_ventor.csc_offset1 = PQ_CSC_DC_IN_OUT_DEFAULT;
1413
+ dc_out_ventor.csc_offset2 = PQ_CSC_DC_IN_OUT_DEFAULT;
1414
+ } else {
1415
+ /*
1416
+ * rgb2rgb: output = T * M1 * N_y2r * M0 * N_r2y,
1417
+ * so output = T * gain_matrix * contrast_matrix *
1418
+ * N_y2r * hue_matrix * saturation_matrix * N_r2y
1419
+ */
1420
+ if (!color_info->in_full_range && color_info->out_full_range) {
1421
+ r2y_matrix = &rk_csc_table_rgb_limit_to_hdy_cb_cr;
1422
+ y2r_matrix = &rk_csc_table_hdy_cb_cr_limit_to_rgb_full;
1423
+ } else if (color_info->in_full_range && !color_info->out_full_range) {
1424
+ r2y_matrix = &rk_csc_table_rgb_to_hdy_cb_cr;
1425
+ y2r_matrix = &rk_csc_table_hdy_cb_cr_limit_to_rgb_limit;
1426
+ } else if (color_info->in_full_range && color_info->out_full_range) {
1427
+ r2y_matrix = &rk_csc_table_rgb_to_hdy_cb_cr_full;
1428
+ y2r_matrix = &rk_csc_table_hdy_cb_cr_to_rgb_full;
1429
+ } else {
1430
+ r2y_matrix = &rk_csc_table_rgb_limit_to_hdy_cb_cr;
1431
+ y2r_matrix = &rk_csc_table_hdy_cb_cr_limit_to_rgb_limit;
1432
+ }
1433
+
1434
+ csc_matrix_multiply(&temp0, &contrast_matrix, y2r_matrix);
1435
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH -
1436
+ PQ_CALC_ENHANCE_BIT);
1437
+ csc_matrix_multiply(&temp1, &gain_matrix, &temp0);
1438
+ csc_matrix_element_left_shift(&temp1, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
1439
+ csc_matrix_multiply(&temp0, &temp1, &hue_matrix);
1440
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_FIX_BIT_WIDTH);
1441
+ csc_matrix_multiply(&temp1, &temp0, &saturation_matrix);
1442
+ csc_matrix_element_left_shift(&temp1, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
1443
+ csc_matrix_multiply(out_matrix, &temp1, r2y_matrix);
1444
+ csc_matrix_element_left_shift(out_matrix, PQ_CSC_PARAM_FIX_BIT_WIDTH +
1445
+ PQ_CALC_ENHANCE_BIT);
1446
+
1447
+ if (color_info->in_full_range && color_info->out_full_range)
1448
+ out_matrix->csc_coef00 += 1;
1449
+
1450
+ dc_in_ventor.csc_offset0 = dc_in_offset;
1451
+ dc_in_ventor.csc_offset1 = dc_in_offset;
1452
+ dc_in_ventor.csc_offset2 = dc_in_offset;
1453
+ dc_out_ventor.csc_offset0 = brightness + dc_out_offset + r_offset;
1454
+ dc_out_ventor.csc_offset1 = brightness + dc_out_offset + g_offset;
1455
+ dc_out_ventor.csc_offset2 = brightness + dc_out_offset + b_offset;
1456
+ }
1457
+
1458
+ csc_matrix_ventor_multiply(&v, out_matrix, &dc_in_ventor);
1459
+ out_dc->csc_offset0 = v.csc_offset0 + dc_out_ventor.csc_offset0 *
1460
+ PQ_CSC_SIMPLE_MAT_PARAM_FIX_NUM;
1461
+ out_dc->csc_offset1 = v.csc_offset1 + dc_out_ventor.csc_offset1 *
1462
+ PQ_CSC_SIMPLE_MAT_PARAM_FIX_NUM;
1463
+ out_dc->csc_offset2 = v.csc_offset2 + dc_out_ventor.csc_offset2 *
1464
+ PQ_CSC_SIMPLE_MAT_PARAM_FIX_NUM;
1465
+
1466
+ return 0;
1467
+}
1468
+
1469
+static int csc_calc_default_output_coef(const struct rk_csc_mode_coef *csc_mode_cfg,
1470
+ struct rk_pq_csc_coef *out_matrix,
1471
+ struct rk_pq_csc_ventor *out_dc)
1472
+{
1473
+ const struct rk_pq_csc_coef *csc_coef;
1474
+ const struct rk_pq_csc_dc_coef *csc_dc_coef;
1475
+ struct rk_pq_csc_ventor dc_in_ventor;
1476
+ struct rk_pq_csc_ventor dc_out_ventor;
1477
+ struct rk_pq_csc_ventor v;
1478
+
1479
+ csc_coef = csc_mode_cfg->pst_csc_coef;
1480
+ csc_dc_coef = csc_mode_cfg->pst_csc_dc_coef;
1481
+
1482
+ out_matrix->csc_coef00 = csc_coef->csc_coef00;
1483
+ out_matrix->csc_coef01 = csc_coef->csc_coef01;
1484
+ out_matrix->csc_coef02 = csc_coef->csc_coef02;
1485
+ out_matrix->csc_coef10 = csc_coef->csc_coef10;
1486
+ out_matrix->csc_coef11 = csc_coef->csc_coef11;
1487
+ out_matrix->csc_coef12 = csc_coef->csc_coef12;
1488
+ out_matrix->csc_coef20 = csc_coef->csc_coef20;
1489
+ out_matrix->csc_coef21 = csc_coef->csc_coef21;
1490
+ out_matrix->csc_coef22 = csc_coef->csc_coef22;
1491
+
1492
+ dc_in_ventor.csc_offset0 = csc_dc_coef->csc_in_dc0;
1493
+ dc_in_ventor.csc_offset1 = csc_dc_coef->csc_in_dc1;
1494
+ dc_in_ventor.csc_offset2 = csc_dc_coef->csc_in_dc2;
1495
+ dc_out_ventor.csc_offset0 = csc_dc_coef->csc_out_dc0;
1496
+ dc_out_ventor.csc_offset1 = csc_dc_coef->csc_out_dc1;
1497
+ dc_out_ventor.csc_offset2 = csc_dc_coef->csc_out_dc2;
1498
+
1499
+ csc_matrix_ventor_multiply(&v, csc_coef, &dc_in_ventor);
1500
+ out_dc->csc_offset0 = v.csc_offset0 + dc_out_ventor.csc_offset0 *
1501
+ PQ_CSC_SIMPLE_MAT_PARAM_FIX_NUM;
1502
+ out_dc->csc_offset1 = v.csc_offset1 + dc_out_ventor.csc_offset1 *
1503
+ PQ_CSC_SIMPLE_MAT_PARAM_FIX_NUM;
1504
+ out_dc->csc_offset2 = v.csc_offset2 + dc_out_ventor.csc_offset2 *
1505
+ PQ_CSC_SIMPLE_MAT_PARAM_FIX_NUM;
1506
+
1507
+ return 0;
1508
+}
1509
+
1510
+static inline s32 pq_csc_simple_round(s32 x, s32 n)
1511
+{
1512
+ s32 value = 0;
1513
+
1514
+ if (n == 0)
1515
+ return x;
1516
+
1517
+ value = (abs(x) + (1 << (n - 1))) >> (n);
1518
+ return (((x) >= 0) ? value : -value);
1519
+}
1520
+
1521
+static void rockchip_swap_color_channel(bool is_input_yuv, bool is_output_yuv,
1522
+ struct post_csc_coef *csc_simple_coef,
1523
+ struct rk_pq_csc_coef *out_matrix,
1524
+ struct rk_pq_csc_ventor *out_dc)
1525
+{
1526
+ struct rk_pq_csc_coef tmp_matrix;
1527
+ struct rk_pq_csc_ventor tmp_v;
1528
+
1529
+ if (!is_input_yuv) {
1530
+ memcpy(&tmp_matrix, out_matrix, sizeof(struct rk_pq_csc_coef));
1531
+ csc_matrix_multiply(out_matrix, &tmp_matrix, &rgb_input_swap_matrix);
1532
+ }
1533
+
1534
+ if (is_output_yuv) {
1535
+ memcpy(&tmp_matrix, out_matrix, sizeof(struct rk_pq_csc_coef));
1536
+ memcpy(&tmp_v, out_dc, sizeof(struct rk_pq_csc_ventor));
1537
+ csc_matrix_multiply(out_matrix, &yuv_output_swap_matrix, &tmp_matrix);
1538
+ csc_matrix_ventor_multiply(out_dc, &yuv_output_swap_matrix, &tmp_v);
1539
+ }
1540
+
1541
+ csc_simple_coef->csc_coef00 = out_matrix->csc_coef00;
1542
+ csc_simple_coef->csc_coef01 = out_matrix->csc_coef01;
1543
+ csc_simple_coef->csc_coef02 = out_matrix->csc_coef02;
1544
+ csc_simple_coef->csc_coef10 = out_matrix->csc_coef10;
1545
+ csc_simple_coef->csc_coef11 = out_matrix->csc_coef11;
1546
+ csc_simple_coef->csc_coef12 = out_matrix->csc_coef12;
1547
+ csc_simple_coef->csc_coef20 = out_matrix->csc_coef20;
1548
+ csc_simple_coef->csc_coef21 = out_matrix->csc_coef21;
1549
+ csc_simple_coef->csc_coef22 = out_matrix->csc_coef22;
1550
+ csc_simple_coef->csc_dc0 = out_dc->csc_offset0;
1551
+ csc_simple_coef->csc_dc1 = out_dc->csc_offset1;
1552
+ csc_simple_coef->csc_dc2 = out_dc->csc_offset2;
1553
+}
1554
+
1555
+int rockchip_calc_post_csc(struct csc_info *csc_cfg, struct post_csc_coef *csc_simple_coef,
1556
+ int csc_mode, bool is_input_yuv, bool is_output_yuv)
1557
+{
1558
+ int ret = 0;
1559
+ struct rk_pq_csc_coef out_matrix;
1560
+ struct rk_pq_csc_ventor out_dc;
1561
+ const struct rk_csc_mode_coef *csc_mode_cfg;
1562
+ int bit_num = PQ_CSC_SIMPLE_MAT_PARAM_FIX_BIT_WIDTH;
1563
+
1564
+ ret = csc_get_mode_index(csc_mode, is_input_yuv, is_output_yuv);
1565
+ if (ret < 0) {
1566
+ printf("invalid csc_mode:%d\n", csc_mode);
1567
+ return ret;
1568
+ }
1569
+
1570
+ csc_mode_cfg = &g_mode_csc_coef[ret];
1571
+
1572
+ if (csc_cfg)
1573
+ ret = csc_calc_adjust_output_coef(is_input_yuv, is_output_yuv, csc_cfg,
1574
+ csc_mode_cfg, &out_matrix, &out_dc);
1575
+ else
1576
+ ret = csc_calc_default_output_coef(csc_mode_cfg, &out_matrix, &out_dc);
1577
+
1578
+ rockchip_swap_color_channel(is_input_yuv, is_output_yuv, csc_simple_coef, &out_matrix,
1579
+ &out_dc);
1580
+
1581
+ csc_simple_coef->csc_dc0 = pq_csc_simple_round(csc_simple_coef->csc_dc0, bit_num);
1582
+ csc_simple_coef->csc_dc1 = pq_csc_simple_round(csc_simple_coef->csc_dc1, bit_num);
1583
+ csc_simple_coef->csc_dc2 = pq_csc_simple_round(csc_simple_coef->csc_dc2, bit_num);
1584
+ csc_simple_coef->range_type = csc_mode_cfg->st_csc_color_info.out_full_range;
1585
+
1586
+ return ret;
1587
+}
u-boot/drivers/video/drm/rockchip_post_csc.h
....@@ -0,0 +1,35 @@
1
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2
+/*
3
+ * Copyright (C) Rockchip Electronics Co.Ltd
4
+ * Author:
5
+ * Zhang Yubing <yubing.zhang@rock-chips.com>
6
+ */
7
+
8
+#ifndef _ROCKCHIP_POST_CSC_H
9
+#define _ROCKCHIP_POST_CSC_H
10
+
11
+#include <linux/kernel.h>
12
+#include <edid.h>
13
+
14
+struct post_csc_coef {
15
+ s32 csc_coef00;
16
+ s32 csc_coef01;
17
+ s32 csc_coef02;
18
+ s32 csc_coef10;
19
+ s32 csc_coef11;
20
+ s32 csc_coef12;
21
+ s32 csc_coef20;
22
+ s32 csc_coef21;
23
+ s32 csc_coef22;
24
+
25
+ s32 csc_dc0;
26
+ s32 csc_dc1;
27
+ s32 csc_dc2;
28
+
29
+ u32 range_type;
30
+};
31
+
32
+int rockchip_calc_post_csc(struct csc_info *csc, struct post_csc_coef *csc_coef,
33
+ int csc_mode, bool is_input_yuv, bool is_output_yuv);
34
+
35
+#endif
u-boot/drivers/video/drm/rockchip_rgb.c
....@@ -13,11 +13,14 @@
1313 #include <dm/read.h>
1414 #include <dm/pinctrl.h>
1515 #include <linux/media-bus-format.h>
16
+#include <asm/gpio.h>
17
+#include <backlight.h>
1618
1719 #include "rockchip_display.h"
1820 #include "rockchip_crtc.h"
1921 #include "rockchip_connector.h"
2022 #include "rockchip_phy.h"
23
+#include "rockchip_panel.h"
2124
2225 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK(h, l) << 16))
2326
....@@ -48,6 +51,9 @@
4851 #define RK3368_GRF_SOC_CON15 0x043c
4952 #define RK3368_FORCE_JETAG(v) HIWORD_UPDATE(v, 13, 13)
5053
54
+#define RK3562_GRF_IOC_VO_IO_CON 0x10500
55
+#define RK3562_RGB_DATA_BYPASS(v) HIWORD_UPDATE(v, 6, 6)
56
+
5157 #define RK3568_GRF_VO_CON1 0X0364
5258 #define RK3568_RGB_DATA_BYPASS(v) HIWORD_UPDATE(v, 6, 6)
5359
....@@ -67,6 +73,64 @@
6773 struct rockchip_phy *phy;
6874 const struct rockchip_rgb_funcs *funcs;
6975 };
76
+
77
+struct mcu_cmd_header {
78
+ u8 data_type;
79
+ u8 delay;
80
+ u8 payload_length;
81
+} __packed;
82
+
83
+struct mcu_cmd_desc {
84
+ struct mcu_cmd_header header;
85
+ const u8 *payload;
86
+};
87
+
88
+struct mcu_cmd_seq {
89
+ struct mcu_cmd_desc *cmds;
90
+ unsigned int cmd_cnt;
91
+};
92
+
93
+struct rockchip_mcu_panel_desc {
94
+ struct mcu_cmd_seq *init_seq;
95
+ struct mcu_cmd_seq *exit_seq;
96
+
97
+ struct {
98
+ unsigned int width;
99
+ unsigned int height;
100
+ } size;
101
+
102
+ struct {
103
+ unsigned int prepare;
104
+ unsigned int enable;
105
+ unsigned int disable;
106
+ unsigned int unprepare;
107
+ unsigned int reset;
108
+ unsigned int init;
109
+ } delay;
110
+
111
+ unsigned int bpc;
112
+ u32 bus_format;
113
+ u32 bus_flags;
114
+ bool power_invert;
115
+};
116
+
117
+struct rockchip_mcu_panel {
118
+ struct rockchip_panel base;
119
+ struct rockchip_mcu_panel_desc *desc;
120
+ struct udevice *power_supply;
121
+ struct udevice *backlight;
122
+
123
+ struct gpio_desc enable_gpio;
124
+ struct gpio_desc reset_gpio;
125
+
126
+ bool prepared;
127
+ bool enabled;
128
+};
129
+
130
+static inline struct rockchip_mcu_panel *to_rockchip_mcu_panel(struct rockchip_panel *panel)
131
+{
132
+ return container_of(panel, struct rockchip_mcu_panel, base);
133
+}
70134
71135 static int rockchip_rgb_connector_prepare(struct rockchip_connector *conn,
72136 struct display_state *state)
....@@ -170,9 +234,254 @@
170234 .unprepare = rockchip_rgb_connector_unprepare,
171235 };
172236
237
+static int rockchip_mcu_panel_send_cmds(struct display_state *state,
238
+ struct mcu_cmd_seq *cmds)
239
+{
240
+ int i;
241
+
242
+ if (!cmds)
243
+ return -EINVAL;
244
+
245
+ display_send_mcu_cmd(state, MCU_SETBYPASS, 1);
246
+ for (i = 0; i < cmds->cmd_cnt; i++) {
247
+ struct mcu_cmd_desc *desc = &cmds->cmds[i];
248
+ int value = 0;
249
+
250
+ value = desc->payload[0];
251
+ display_send_mcu_cmd(state, desc->header.data_type, value);
252
+
253
+ if (desc->header.delay)
254
+ mdelay(desc->header.delay);
255
+ }
256
+ display_send_mcu_cmd(state, MCU_SETBYPASS, 0);
257
+
258
+ return 0;
259
+}
260
+
261
+static void rockchip_mcu_panel_prepare(struct rockchip_panel *panel)
262
+{
263
+ struct rockchip_mcu_panel *mcu_panel = to_rockchip_mcu_panel(panel);
264
+ int ret;
265
+
266
+ if (mcu_panel->prepared)
267
+ return;
268
+
269
+ if (dm_gpio_is_valid(&mcu_panel->enable_gpio))
270
+ dm_gpio_set_value(&mcu_panel->enable_gpio, 1);
271
+
272
+ if (mcu_panel->desc->delay.prepare)
273
+ mdelay(mcu_panel->desc->delay.prepare);
274
+
275
+ if (dm_gpio_is_valid(&mcu_panel->reset_gpio))
276
+ dm_gpio_set_value(&mcu_panel->reset_gpio, 1);
277
+
278
+ if (mcu_panel->desc->delay.reset)
279
+ mdelay(mcu_panel->desc->delay.reset);
280
+
281
+ if (dm_gpio_is_valid(&mcu_panel->reset_gpio))
282
+ dm_gpio_set_value(&mcu_panel->reset_gpio, 0);
283
+
284
+ if (mcu_panel->desc->delay.init)
285
+ mdelay(mcu_panel->desc->delay.init);
286
+
287
+ if (mcu_panel->desc->init_seq) {
288
+ ret = rockchip_mcu_panel_send_cmds(panel->state, mcu_panel->desc->init_seq);
289
+ if (ret)
290
+ printf("failed to send mcu panel init cmds: %d\n", ret);
291
+ }
292
+
293
+ mcu_panel->prepared = true;
294
+}
295
+
296
+static void rockchip_mcu_panel_unprepare(struct rockchip_panel *panel)
297
+{
298
+ struct rockchip_mcu_panel *mcu_panel = to_rockchip_mcu_panel(panel);
299
+ int ret;
300
+
301
+ if (!mcu_panel->prepared)
302
+ return;
303
+
304
+ if (mcu_panel->desc->exit_seq) {
305
+ ret = rockchip_mcu_panel_send_cmds(panel->state, mcu_panel->desc->exit_seq);
306
+ if (ret)
307
+ printf("failed to send mcu panel exit cmds: %d\n", ret);
308
+ }
309
+
310
+ if (dm_gpio_is_valid(&mcu_panel->reset_gpio))
311
+ dm_gpio_set_value(&mcu_panel->reset_gpio, 1);
312
+
313
+ if (dm_gpio_is_valid(&mcu_panel->enable_gpio))
314
+ dm_gpio_set_value(&mcu_panel->enable_gpio, 0);
315
+
316
+ if (mcu_panel->desc->delay.unprepare)
317
+ mdelay(mcu_panel->desc->delay.unprepare);
318
+
319
+ mcu_panel->prepared = false;
320
+}
321
+
322
+static void rockchip_mcu_panel_enable(struct rockchip_panel *panel)
323
+{
324
+ struct rockchip_mcu_panel *mcu_panel = to_rockchip_mcu_panel(panel);
325
+
326
+ if (mcu_panel->enabled)
327
+ return;
328
+
329
+ if (mcu_panel->desc->delay.enable)
330
+ mdelay(mcu_panel->desc->delay.enable);
331
+
332
+ if (mcu_panel->backlight)
333
+ backlight_enable(mcu_panel->backlight);
334
+
335
+ mcu_panel->enabled = true;
336
+}
337
+
338
+static void rockchip_mcu_panel_disable(struct rockchip_panel *panel)
339
+{
340
+ struct rockchip_mcu_panel *mcu_panel = to_rockchip_mcu_panel(panel);
341
+
342
+ if (!mcu_panel->enabled)
343
+ return;
344
+
345
+ if (mcu_panel->backlight)
346
+ backlight_disable(mcu_panel->backlight);
347
+
348
+ if (mcu_panel->desc->delay.disable)
349
+ mdelay(mcu_panel->desc->delay.disable);
350
+
351
+ mcu_panel->enabled = false;
352
+}
353
+
354
+static const struct rockchip_panel_funcs rockchip_mcu_panel_funcs = {
355
+ .prepare = rockchip_mcu_panel_prepare,
356
+ .unprepare = rockchip_mcu_panel_unprepare,
357
+ .enable = rockchip_mcu_panel_enable,
358
+ .disable = rockchip_mcu_panel_disable,
359
+};
360
+
361
+static int rockchip_mcu_panel_parse_cmds(const u8 *data, int length,
362
+ struct mcu_cmd_seq *pcmds)
363
+{
364
+ int len;
365
+ const u8 *buf;
366
+ const struct mcu_cmd_header *header;
367
+ int i, cnt = 0;
368
+
369
+ /* scan commands */
370
+ cnt = 0;
371
+ buf = data;
372
+ len = length;
373
+ while (len > sizeof(*header)) {
374
+ header = (const struct mcu_cmd_header *)buf;
375
+ buf += sizeof(*header) + header->payload_length;
376
+ len -= sizeof(*header) + header->payload_length;
377
+ cnt++;
378
+ }
379
+
380
+ pcmds->cmds = calloc(cnt, sizeof(struct mcu_cmd_desc));
381
+ if (!pcmds->cmds)
382
+ return -ENOMEM;
383
+
384
+ pcmds->cmd_cnt = cnt;
385
+
386
+ buf = data;
387
+ len = length;
388
+ for (i = 0; i < cnt; i++) {
389
+ struct mcu_cmd_desc *desc = &pcmds->cmds[i];
390
+
391
+ header = (const struct mcu_cmd_header *)buf;
392
+ length -= sizeof(*header);
393
+ buf += sizeof(*header);
394
+ desc->header.data_type = header->data_type;
395
+ desc->header.delay = header->delay;
396
+ desc->header.payload_length = header->payload_length;
397
+ desc->payload = buf;
398
+ buf += header->payload_length;
399
+ length -= header->payload_length;
400
+ }
401
+
402
+ return 0;
403
+}
404
+
405
+static int rockchip_mcu_panel_init(struct rockchip_mcu_panel *mcu_panel, ofnode mcu_panel_node)
406
+{
407
+ const void *data;
408
+ int len;
409
+ int ret;
410
+
411
+ ret = gpio_request_by_name_nodev(mcu_panel_node, "enable-gpios", 0,
412
+ &mcu_panel->enable_gpio, GPIOD_IS_OUT);
413
+ if (ret && ret != -ENOENT) {
414
+ printf("%s: Cannot get mcu panel enable GPIO: %d\n", __func__, ret);
415
+ return ret;
416
+ }
417
+
418
+ ret = gpio_request_by_name_nodev(mcu_panel_node, "reset-gpios", 0,
419
+ &mcu_panel->reset_gpio, GPIOD_IS_OUT);
420
+ if (ret && ret != -ENOENT) {
421
+ printf("%s: Cannot get mcu panel reset GPIO: %d\n", __func__, ret);
422
+ return ret;
423
+ }
424
+
425
+ mcu_panel->desc = malloc(sizeof(struct rockchip_mcu_panel_desc));
426
+ if (!mcu_panel->desc)
427
+ return -ENOMEM;
428
+
429
+ mcu_panel->desc->power_invert = ofnode_read_bool(mcu_panel_node, "power-invert");
430
+
431
+ mcu_panel->desc->delay.prepare = ofnode_read_u32_default(mcu_panel_node, "prepare-delay-ms", 0);
432
+ mcu_panel->desc->delay.unprepare = ofnode_read_u32_default(mcu_panel_node, "unprepare-delay-ms", 0);
433
+ mcu_panel->desc->delay.enable = ofnode_read_u32_default(mcu_panel_node, "enable-delay-ms", 0);
434
+ mcu_panel->desc->delay.disable = ofnode_read_u32_default(mcu_panel_node, "disable-delay-ms", 0);
435
+ mcu_panel->desc->delay.init = ofnode_read_u32_default(mcu_panel_node, "init-delay-ms", 0);
436
+ mcu_panel->desc->delay.reset = ofnode_read_u32_default(mcu_panel_node, "reset-delay-ms", 0);
437
+
438
+ mcu_panel->desc->bus_format = ofnode_read_u32_default(mcu_panel_node, "bus-format",
439
+ MEDIA_BUS_FMT_RBG888_1X24);
440
+ mcu_panel->desc->bpc = ofnode_read_u32_default(mcu_panel_node, "bpc", 8);
441
+
442
+ data = ofnode_get_property(mcu_panel_node, "panel-init-sequence", &len);
443
+ if (data) {
444
+ mcu_panel->desc->init_seq = calloc(1, sizeof(*mcu_panel->desc->init_seq));
445
+ if (!mcu_panel->desc->init_seq)
446
+ return -ENOMEM;
447
+
448
+ ret = rockchip_mcu_panel_parse_cmds(data, len, mcu_panel->desc->init_seq);
449
+ if (ret) {
450
+ printf("failed to parse panel init sequence\n");
451
+ goto free_on_cmds;
452
+ }
453
+ }
454
+
455
+ data = ofnode_get_property(mcu_panel_node, "panel-exit-sequence", &len);
456
+ if (data) {
457
+ mcu_panel->desc->exit_seq = calloc(1, sizeof(*mcu_panel->desc->exit_seq));
458
+ if (!mcu_panel->desc->exit_seq) {
459
+ ret = -ENOMEM;
460
+ goto free_on_cmds;
461
+ }
462
+
463
+ ret = rockchip_mcu_panel_parse_cmds(data, len, mcu_panel->desc->exit_seq);
464
+ if (ret) {
465
+ printf("failed to parse panel exit sequence\n");
466
+ goto free_cmds;
467
+ }
468
+ }
469
+
470
+ return 0;
471
+
472
+free_cmds:
473
+ free(mcu_panel->desc->exit_seq);
474
+free_on_cmds:
475
+ free(mcu_panel->desc->init_seq);
476
+ return ret;
477
+}
478
+
173479 static int rockchip_rgb_probe(struct udevice *dev)
174480 {
175481 struct rockchip_rgb *rgb = dev_get_priv(dev);
482
+ ofnode mcu_panel_node;
483
+ int phandle;
484
+ int ret;
176485
177486 rgb->dev = dev;
178487 rgb->funcs = (const struct rockchip_rgb_funcs *)dev_get_driver_data(dev);
....@@ -181,6 +490,45 @@
181490 rgb->id = of_alias_get_id(ofnode_to_np(dev->node), "rgb");
182491 if (rgb->id < 0)
183492 rgb->id = 0;
493
+
494
+ mcu_panel_node = dev_read_subnode(dev, "mcu-panel");
495
+ if (ofnode_valid(mcu_panel_node) && ofnode_is_available(mcu_panel_node)) {
496
+ struct rockchip_mcu_panel *mcu_panel;
497
+
498
+ mcu_panel = malloc(sizeof(struct rockchip_mcu_panel));
499
+ if (!mcu_panel) {
500
+ printf("failed to alloc mcu_panel data\n");
501
+ return -ENOMEM;
502
+ }
503
+
504
+ ret = rockchip_mcu_panel_init(mcu_panel, mcu_panel_node);
505
+ if (ret < 0) {
506
+ printf("failed to init mcu_panel: %d\n", ret);
507
+ return ret;
508
+ }
509
+
510
+ phandle = ofnode_read_u32_default(mcu_panel_node, "backlight", -1);
511
+ if (phandle < 0) {
512
+ printf("failed to find backlight phandle\n");
513
+ return -EINVAL;
514
+ }
515
+
516
+ ret = uclass_get_device_by_phandle_id(UCLASS_PANEL_BACKLIGHT, phandle,
517
+ &mcu_panel->backlight);
518
+ if (ret && ret != -ENOENT) {
519
+ printf("%s: failed to get backlight device: %d\n", __func__, ret);
520
+ return ret;
521
+ }
522
+
523
+ mcu_panel->base.dev = dev;
524
+ mcu_panel->base.bus_format = mcu_panel->desc->bus_format;
525
+ mcu_panel->base.bpc = mcu_panel->desc->bpc;
526
+ mcu_panel->base.funcs = &rockchip_mcu_panel_funcs;
527
+ mcu_panel->enabled = false;
528
+ mcu_panel->prepared = false;
529
+
530
+ rgb->connector.panel = &mcu_panel->base;
531
+ }
184532
185533 rockchip_connector_bind(&rgb->connector, dev, rgb->id, &rockchip_rgb_connector_funcs,
186534 NULL, DRM_MODE_CONNECTOR_LVDS);
....@@ -260,6 +608,16 @@
260608 .prepare = rk3368_rgb_prepare,
261609 };
262610
611
+static void rk3562_rgb_prepare(struct rockchip_rgb *rgb, int pipe)
612
+{
613
+ regmap_write(rgb->grf, RK3562_GRF_IOC_VO_IO_CON,
614
+ RK3562_RGB_DATA_BYPASS(rgb->data_sync_bypass));
615
+}
616
+
617
+static const struct rockchip_rgb_funcs rk3562_rgb_funcs = {
618
+ .prepare = rk3562_rgb_prepare,
619
+};
620
+
263621 static void rk3568_rgb_prepare(struct rockchip_rgb *rgb, int pipe)
264622 {
265623 regmap_write(rgb->grf, RK3568_GRF_VO_CON1, RK3568_RGB_DATA_BYPASS(rgb->data_sync_bypass));
....@@ -296,6 +654,10 @@
296654 .data = (ulong)&rk3368_rgb_funcs,
297655 },
298656 {
657
+ .compatible = "rockchip,rk3562-rgb",
658
+ .data = (ulong)&rk3562_rgb_funcs,
659
+ },
660
+ {
299661 .compatible = "rockchip,rk3568-rgb",
300662 .data = (ulong)&rk3568_rgb_funcs,
301663 },
u-boot/drivers/video/drm/rockchip_spl_display.c
....@@ -0,0 +1,265 @@
1
+/*
2
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+
7
+#include <common.h>
8
+#include <asm/io.h>
9
+#include <malloc.h>
10
+#include <mp_boot.h>
11
+#include <spl.h>
12
+#include <part.h>
13
+#include <drm_modes.h>
14
+#include <spl_display.h>
15
+#include <linux/hdmi.h>
16
+
17
+#include "rockchip_display.h"
18
+#include "rockchip_crtc.h"
19
+#include "rockchip_connector.h"
20
+#include "rockchip_phy.h"
21
+
22
+static struct base2_info base_parameter;
23
+
24
+struct display_state *rockchip_spl_display_drv_probe(void)
25
+{
26
+ struct display_state *state = malloc(sizeof(struct display_state));
27
+ if (!state)
28
+ return NULL;
29
+
30
+ memset(state, 0, sizeof(*state));
31
+
32
+ rockchip_spl_vop_probe(&state->crtc_state);
33
+ rockchip_spl_dw_hdmi_probe(&state->conn_state);
34
+ inno_spl_hdmi_phy_probe(state);
35
+
36
+ return state;
37
+}
38
+
39
+static int rockchip_spl_display_init(struct display_state *state)
40
+{
41
+ struct crtc_state *crtc_state = &state->crtc_state;
42
+ struct connector_state *conn_state = &state->conn_state;
43
+ struct rockchip_connector *conn = conn_state->connector;
44
+ const struct rockchip_crtc *crtc = crtc_state->crtc;
45
+ const struct rockchip_crtc_funcs *crtc_funcs = crtc->funcs;
46
+ const struct rockchip_connector_funcs *conn_funcs = conn->funcs;
47
+ struct drm_display_mode *mode = &state->conn_state.mode;
48
+ int ret = 0;
49
+
50
+ if (!crtc_funcs) {
51
+ printf("failed to find crtc functions\n");
52
+ return -ENXIO;
53
+ }
54
+
55
+ if (crtc_funcs->preinit) {
56
+ ret = crtc_funcs->preinit(state);
57
+ if (ret)
58
+ return ret;
59
+ }
60
+
61
+ rockchip_display_make_crc32_table();
62
+ if (conn_funcs->pre_init) {
63
+ ret = conn_funcs->pre_init(conn, state);
64
+ if (ret)
65
+ return ret;
66
+ }
67
+
68
+ if (conn_funcs->init) {
69
+ ret = conn_funcs->init(conn, state);
70
+ if (ret)
71
+ goto deinit;
72
+ }
73
+
74
+ if (conn->phy)
75
+ rockchip_phy_init(conn->phy);
76
+
77
+ if (conn_funcs->detect) {
78
+ conn->hpd = conn_funcs->detect(conn, state);
79
+ if (!conn->hpd)
80
+ goto deinit;
81
+ }
82
+
83
+ if (conn_funcs->get_timing) {
84
+ ret = conn_funcs->get_timing(conn, state);
85
+ if (ret)
86
+ goto deinit;
87
+ }
88
+
89
+ drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
90
+ if (crtc_funcs->init) {
91
+ ret = crtc_funcs->init(state);
92
+ if (ret)
93
+ goto deinit;
94
+ }
95
+
96
+ return 0;
97
+
98
+deinit:
99
+ rockchip_connector_deinit(state);
100
+ return ret;
101
+}
102
+
103
+static int rockchip_spl_display_post_enable(struct display_state *state)
104
+{
105
+ struct crtc_state *crtc_state = &state->crtc_state;
106
+ struct connector_state *conn_state = &state->conn_state;
107
+ struct rockchip_connector *conn = conn_state->connector;
108
+ const struct rockchip_crtc *crtc = crtc_state->crtc;
109
+ const struct rockchip_crtc_funcs *crtc_funcs = crtc->funcs;
110
+ const struct rockchip_connector_funcs *conn_funcs = conn->funcs;
111
+
112
+ if (crtc_funcs->enable)
113
+ crtc_funcs->enable(state);
114
+ state->crtc_state.crtc->active = true;
115
+
116
+ if (conn_funcs->enable)
117
+ conn_funcs->enable(conn, state);
118
+
119
+ return 0;
120
+}
121
+
122
+static void rockchip_spl_display_transmit_info_to_uboot(struct display_state *state)
123
+{
124
+ struct connector_state *conn_state = &state->conn_state;
125
+ struct spl_display_info *spl_disp_info = (struct spl_display_info *)CONFIG_SPL_VIDEO_BUF;
126
+
127
+ /* transmit mode and bus_format to uboot */
128
+ memcpy(&spl_disp_info->mode, &conn_state->mode, sizeof(conn_state->mode));
129
+ spl_disp_info->bus_format = state->conn_state.bus_format;
130
+ spl_disp_info->enabled = 1;
131
+ flush_dcache_all();
132
+}
133
+
134
+int spl_init_display(struct task_data *data)
135
+{
136
+ struct display_state *state = NULL;
137
+ struct drm_display_mode *mode;
138
+ int ret = 0;
139
+
140
+ state = rockchip_spl_display_drv_probe();
141
+ if (!state) {
142
+ printf("rockchip_spl_display_drv_probe failed\n");
143
+ return -1;
144
+ }
145
+
146
+ ret = rockchip_spl_display_init(state);
147
+ if (ret) {
148
+ printf("rockchip_spl_display_init failed ret:%d\n", ret);
149
+ return -1;
150
+ }
151
+
152
+ if (!state->conn_state.connector->hpd) {
153
+ printf("HDMI is unplug and exit\n");
154
+ return 0;
155
+ }
156
+
157
+ ret = rockchip_spl_display_post_enable(state);
158
+ if (ret) {
159
+ printf("rockchip_spl_display_post_enable failed ret:%d\n", ret);
160
+ return -1;
161
+ }
162
+
163
+ rockchip_spl_display_transmit_info_to_uboot(state);
164
+
165
+ mode = &state->conn_state.mode;
166
+ printf("SPL enable hdmi, detailed mode clock %u kHz, flags[%x]\n"
167
+ " H: %04d %04d %04d %04d\n"
168
+ " V: %04d %04d %04d %04d\n"
169
+ "bus_format: %x\n",
170
+ mode->clock, mode->flags,
171
+ mode->hdisplay, mode->hsync_start,
172
+ mode->hsync_end, mode->htotal,
173
+ mode->vdisplay, mode->vsync_start,
174
+ mode->vsync_end, mode->vtotal,
175
+ state->conn_state.bus_format);
176
+
177
+ return ret;
178
+}
179
+
180
+struct base2_disp_info *rockchip_get_disp_info(int type, int id)
181
+{
182
+ struct base2_disp_info *disp_info;
183
+ struct base2_disp_header *disp_header;
184
+ int i = 0, offset = -1;
185
+ u32 crc_val;
186
+ u32 base2_length;
187
+ void *base_parameter_addr = (void *)&base_parameter;
188
+#ifdef CONFIG_MP_BOOT
189
+ void *bp_addr = (void *)CONFIG_SPL_VIDEO_BUF;
190
+ ulong ret;
191
+
192
+ /* make sure the baseparameter is ready */
193
+ ret = mpb_post(6);
194
+ printf("SPL read baseparameter %s\n", ret < 0 ? "failed" : "success");
195
+ memcpy(&base_parameter, bp_addr, sizeof(base_parameter));
196
+#endif
197
+ for (i = 0; i < 8; i++) {
198
+ disp_header = &base_parameter.disp_header[i];
199
+ if (disp_header->connector_type == type &&
200
+ disp_header->connector_id == id) {
201
+ printf("disp info %d, type:%d, id:%d\n", i, type, id);
202
+ offset = disp_header->offset;
203
+ break;
204
+ }
205
+ }
206
+
207
+ if (offset < 0)
208
+ return NULL;
209
+ disp_info = base_parameter_addr + offset;
210
+ if (disp_info->screen_info[0].type != type ||
211
+ disp_info->screen_info[0].id != id) {
212
+ printf("base2_disp_info couldn't be found, screen_info type[%d] or id[%d] mismatched\n",
213
+ disp_info->screen_info[0].type,
214
+ disp_info->screen_info[0].id);
215
+ return NULL;
216
+ }
217
+
218
+ if (strncasecmp(disp_info->disp_head_flag, "DISP", 4))
219
+ return NULL;
220
+
221
+ if (base_parameter.major_version == 3 && base_parameter.minor_version == 0) {
222
+ crc_val = rockchip_display_crc32c_cal((unsigned char *)disp_info,
223
+ sizeof(struct base2_disp_info) - 4);
224
+ if (crc_val != disp_info->crc2) {
225
+ printf("error: connector type[%d], id[%d] disp info crc2 check error\n",
226
+ type, id);
227
+ return NULL;
228
+ }
229
+ } else {
230
+ base2_length = sizeof(struct base2_disp_info) - sizeof(struct csc_info) -
231
+ sizeof(struct acm_data) - 10 * 1024 - 4;
232
+ crc_val = rockchip_display_crc32c_cal((unsigned char *)disp_info, base2_length - 4);
233
+ if (crc_val != disp_info->crc) {
234
+ printf("error: connector type[%d], id[%d] disp info crc check error\n",
235
+ type, id);
236
+ return NULL;
237
+ }
238
+ }
239
+
240
+ return disp_info;
241
+}
242
+
243
+int spl_load_baseparamter(struct task_data *data)
244
+{
245
+ struct spl_load_info *info = &data->info;
246
+ ulong addr = CONFIG_SPL_VIDEO_BUF;
247
+ disk_partition_t part;
248
+
249
+ debug("== Baseparam: start\n");
250
+
251
+ if (part_get_info_by_name(info->dev, "baseparameter", &part) < 0) {
252
+ printf("No baseparameter partition\n");
253
+ return -ENOENT;
254
+ } else {
255
+ if (info->read(info, part.start, part.size, (void *)addr) != part.size)
256
+ return -EIO;
257
+ else
258
+ flush_dcache_range(addr, addr + part.size * info->bl_len);
259
+ }
260
+
261
+ debug("== Baseparam: load OK\n");
262
+
263
+ return 0;
264
+}
265
+
u-boot/drivers/video/drm/rockchip_tve.c
....@@ -0,0 +1,848 @@
1
+/*
2
+ * SPDX-License-Identifier: GPL-2.0+
3
+ * (C) Copyright 2008-2015 Fuzhou Rockchip Electronics Co., Ltd
4
+ */
5
+#include <common.h>
6
+#include <malloc.h>
7
+#include <fdtdec.h>
8
+#include <fdt_support.h>
9
+#include <asm/io.h>
10
+#include <linux/media-bus-format.h>
11
+#include <asm/arch-rockchip/clock.h>
12
+#include <dm/device.h>
13
+#include <dm/read.h>
14
+#include <dm/uclass-internal.h>
15
+#include <linux/fb.h>
16
+#include <edid.h>
17
+#include <syscon.h>
18
+#include <boot_rkimg.h>
19
+#include <mapmem.h>
20
+#include <misc.h>
21
+
22
+#include "rockchip_display.h"
23
+#include "rockchip_crtc.h"
24
+#include "rockchip_connector.h"
25
+#include "rockchip_phy.h"
26
+#include "rockchip_tve.h"
27
+
28
+#define RK322X_VDAC_STANDARD 0x15
29
+
30
+static const struct drm_display_mode tve_modes[] = {
31
+ /* 0 - 720x576i@50Hz */
32
+ { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 753,
33
+ 816, 864, 576, 580, 586, 625, 0,
34
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
35
+ DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
36
+ .vrefresh = 50, },
37
+ /* 1 - 720x480i@60Hz */
38
+ { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 753,
39
+ 815, 858, 480, 483, 486, 525, 0,
40
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
41
+ DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
42
+ .vrefresh = 60, },
43
+};
44
+
45
+struct env_config {
46
+ u32 offset;
47
+ u32 value;
48
+};
49
+
50
+static struct env_config ntsc_bt656_config[] = {
51
+ { BT656_DECODER_CROP, 0x00000000 },
52
+ { BT656_DECODER_SIZE, 0x01e002d0 },
53
+ { BT656_DECODER_HTOTAL_HS_END, 0x035a003e },
54
+ { BT656_DECODER_VACT_ST_HACT_ST, 0x00160069 },
55
+ { BT656_DECODER_VTOTAL_VS_END, 0x020d0003 },
56
+ { BT656_DECODER_VS_ST_END_F1, 0x01060109 },
57
+ { BT656_DECODER_DBG_REG, 0x024002d0 },
58
+ { BT656_DECODER_CTRL, 0x00000009 },
59
+};
60
+
61
+static struct env_config ntsc_tve_config[] = {
62
+ { TVE_MODE_CTRL, 0x000af906 },
63
+ { TVE_HOR_TIMING1, 0x00c07a81 },
64
+ { TVE_HOR_TIMING2, 0x169810fc },
65
+ { TVE_HOR_TIMING3, 0x96b40000 },
66
+ { TVE_SUB_CAR_FRQ, 0x21f07bd7 },
67
+ { TVE_IMAGE_POSITION, 0x001500d6 },
68
+ { TVE_ROUTING, 0x10088880 },
69
+ { TVE_SYNC_ADJUST, 0x00000000 },
70
+ { TVE_STATUS, 0x00000000 },
71
+ { TVE_CTRL, 0x00000000 },
72
+ { TVE_INTR_STATUS, 0x00000000 },
73
+ { TVE_INTR_EN, 0x00000000 },
74
+ { TVE_INTR_CLR, 0x00000000 },
75
+ { TVE_COLOR_BUSRT_SAT, 0x0052543c },
76
+ { TVE_CHROMA_BANDWIDTH, 0x00000002 },
77
+ { TVE_BRIGHTNESS_CONTRAST, 0x00008300 },
78
+ { TVE_CLAMP, 0x00000000 },
79
+};
80
+
81
+static struct env_config pal_bt656_config[] = {
82
+ { BT656_DECODER_CROP, 0x00000000 },
83
+ { BT656_DECODER_SIZE, 0x024002d0 },
84
+ { BT656_DECODER_HTOTAL_HS_END, 0x0360003f },
85
+ { BT656_DECODER_VACT_ST_HACT_ST, 0x0016006f },
86
+ { BT656_DECODER_VTOTAL_VS_END, 0x02710003 },
87
+ { BT656_DECODER_VS_ST_END_F1, 0x0138013b },
88
+ { BT656_DECODER_DBG_REG, 0x024002d0 },
89
+ { BT656_DECODER_CTRL, 0x00000009 },
90
+};
91
+
92
+static struct env_config pal_tve_config[] = {
93
+ { TVE_MODE_CTRL, 0x010ab906 },
94
+ { TVE_HOR_TIMING1, 0x00c28381 },
95
+ { TVE_HOR_TIMING2, 0x267d111d },
96
+ { TVE_HOR_TIMING3, 0x66c00880 },
97
+ { TVE_SUB_CAR_FRQ, 0x2a098acb },
98
+ { TVE_IMAGE_POSITION, 0x001500f6 },
99
+ { TVE_ROUTING, 0x10008882 },
100
+ { TVE_SYNC_ADJUST, 0x00000000 },
101
+ { TVE_STATUS, 0x000000b0 },
102
+ { TVE_CTRL, 0x00000000 },
103
+ { TVE_INTR_STATUS, 0x00000000 },
104
+ { TVE_INTR_EN, 0x00000000 },
105
+ { TVE_INTR_CLR, 0x00000000 },
106
+ { TVE_COLOR_BUSRT_SAT, 0x00356245 },
107
+ { TVE_CHROMA_BANDWIDTH, 0x00000022 },
108
+ { TVE_BRIGHTNESS_CONTRAST, 0x0000aa00 },
109
+ { TVE_CLAMP, 0x00000000 },
110
+};
111
+
112
+#define BT656_ENV_CONFIG_SIZE (sizeof(ntsc_bt656_config) / sizeof(struct env_config))
113
+#define TVE_ENV_CONFIG_SIZE (sizeof(ntsc_tve_config) / sizeof(struct env_config))
114
+
115
+#define tve_writel(offset, v) writel(v, tve->reg_base + offset)
116
+#define tve_readl(offset) readl(tve->reg_base + offset)
117
+
118
+#define tve_dac_writel(offset, v) writel(v, tve->vdac_base + offset)
119
+#define tve_dac_readl(offset) readl(tve->vdac_base + offset)
120
+
121
+#define tve_grf_writel(offset, v) writel(v, tve->grf + offset)
122
+#define tve_grf_readl(offset, v) readl(tve->grf + offset)
123
+
124
+struct rockchip_tve_data {
125
+ int input_format;
126
+ int soc_type;
127
+};
128
+
129
+struct rockchip_tve {
130
+ struct rockchip_connector connector;
131
+ struct udevice *dev;
132
+ void *reg_base;
133
+ void *vdac_base;
134
+ int soc_type;
135
+ int input_format;
136
+ int tv_format;
137
+ int test_mode;
138
+ int saturation;
139
+ int brightcontrast;
140
+ int adjtiming;
141
+ int lumafilter0;
142
+ int lumafilter1;
143
+ int lumafilter2;
144
+ int lumafilter3;
145
+ int lumafilter4;
146
+ int lumafilter5;
147
+ int lumafilter6;
148
+ int lumafilter7;
149
+ int daclevel;
150
+ int dac1level;
151
+ int preferred_mode;
152
+ int upsample_mode;
153
+ void *grf;
154
+};
155
+
156
+static void tve_write_block(struct rockchip_tve *tve, struct env_config *config, int len)
157
+{
158
+ int i;
159
+
160
+ for (i = 0; i < len; i++)
161
+ tve_writel(config[i].offset, config[i].value);
162
+}
163
+
164
+static void tve_set_mode(struct rockchip_tve *tve)
165
+{
166
+ struct env_config *bt656_cfg, *tve_cfg;
167
+ int mode = tve->tv_format;
168
+
169
+ if (tve->soc_type == SOC_RK3528) {
170
+ tve_writel(TVE_LUMA_FILTER1, tve->lumafilter0);
171
+ tve_writel(TVE_LUMA_FILTER2, tve->lumafilter1);
172
+ tve_writel(TVE_LUMA_FILTER3, tve->lumafilter2);
173
+ tve_writel(TVE_LUMA_FILTER4, tve->lumafilter3);
174
+ tve_writel(TVE_LUMA_FILTER5, tve->lumafilter4);
175
+ tve_writel(TVE_LUMA_FILTER6, tve->lumafilter5);
176
+ tve_writel(TVE_LUMA_FILTER7, tve->lumafilter6);
177
+ tve_writel(TVE_LUMA_FILTER8, tve->lumafilter7);
178
+ } else {
179
+ if (tve->input_format == INPUT_FORMAT_RGB)
180
+ tve_writel(TV_CTRL, v_CVBS_MODE(mode) | v_CLK_UPSTREAM_EN(2) |
181
+ v_TIMING_EN(2) | v_LUMA_FILTER_GAIN(0) |
182
+ v_LUMA_FILTER_UPSAMPLE(1) | v_CSC_PATH(0));
183
+ else
184
+ tve_writel(TV_CTRL, v_CVBS_MODE(mode) | v_CLK_UPSTREAM_EN(2) |
185
+ v_TIMING_EN(2) | v_LUMA_FILTER_GAIN(0) |
186
+ v_LUMA_FILTER_UPSAMPLE(1) | v_CSC_PATH(3));
187
+
188
+ tve_writel(TV_LUMA_FILTER0, tve->lumafilter0);
189
+ tve_writel(TV_LUMA_FILTER1, tve->lumafilter1);
190
+ tve_writel(TV_LUMA_FILTER2, tve->lumafilter2);
191
+ }
192
+
193
+ if (mode == TVOUT_CVBS_NTSC) {
194
+ TVEDBG("tve set ntsc mode\n");
195
+
196
+ if (tve->soc_type == SOC_RK3528) {
197
+ bt656_cfg = ntsc_bt656_config;
198
+ tve_cfg = ntsc_tve_config;
199
+
200
+ tve_write_block(tve, bt656_cfg, BT656_ENV_CONFIG_SIZE);
201
+ tve_write_block(tve, tve_cfg, TVE_ENV_CONFIG_SIZE);
202
+ } else {
203
+ tve_writel(TV_ROUTING, v_DAC_SENSE_EN(0) | v_Y_IRE_7_5(1) |
204
+ v_Y_AGC_PULSE_ON(0) | v_Y_VIDEO_ON(1) |
205
+ v_YPP_MODE(1) | v_Y_SYNC_ON(1) | v_PIC_MODE(mode));
206
+ tve_writel(TV_BW_CTRL, v_CHROMA_BW(BP_FILTER_NTSC) |
207
+ v_COLOR_DIFF_BW(COLOR_DIFF_FILTER_BW_1_3));
208
+ tve_writel(TV_SATURATION, 0x0042543C);
209
+ if (tve->test_mode)
210
+ tve_writel(TV_BRIGHTNESS_CONTRAST, 0x00008300);
211
+ else
212
+ tve_writel(TV_BRIGHTNESS_CONTRAST, 0x00007900);
213
+
214
+ tve_writel(TV_FREQ_SC, 0x21F07BD7);
215
+ tve_writel(TV_SYNC_TIMING, 0x00C07a81);
216
+ tve_writel(TV_ADJ_TIMING, 0x96B40000 | 0x70);
217
+ tve_writel(TV_ACT_ST, 0x001500D6);
218
+ tve_writel(TV_ACT_TIMING, 0x069800FC | (1 << 12) | (1 << 28));
219
+ }
220
+ } else if (mode == TVOUT_CVBS_PAL) {
221
+ TVEDBG("tve set pal mode\n");
222
+
223
+ if (tve->soc_type == SOC_RK3528) {
224
+ bt656_cfg = pal_bt656_config;
225
+ tve_cfg = pal_tve_config;
226
+
227
+ tve_write_block(tve, bt656_cfg, BT656_ENV_CONFIG_SIZE);
228
+ tve_write_block(tve, tve_cfg, TVE_ENV_CONFIG_SIZE);
229
+ } else {
230
+ tve_writel(TV_ROUTING, v_DAC_SENSE_EN(0) | v_Y_IRE_7_5(0) |
231
+ v_Y_AGC_PULSE_ON(0) | v_Y_VIDEO_ON(1) |
232
+ v_YPP_MODE(1) | v_Y_SYNC_ON(1) | v_PIC_MODE(mode));
233
+ tve_writel(TV_BW_CTRL, v_CHROMA_BW(BP_FILTER_PAL) |
234
+ v_COLOR_DIFF_BW(COLOR_DIFF_FILTER_BW_1_3));
235
+
236
+ tve_writel(TV_SATURATION, tve->saturation);
237
+ tve_writel(TV_BRIGHTNESS_CONTRAST, tve->brightcontrast);
238
+
239
+ tve_writel(TV_FREQ_SC, 0x2A098ACB);
240
+ tve_writel(TV_SYNC_TIMING, 0x00C28381);
241
+ tve_writel(TV_ADJ_TIMING, (0xc << 28) | 0x06c00800 | 0x80);
242
+ tve_writel(TV_ACT_ST, 0x001500F6);
243
+ tve_writel(TV_ACT_TIMING, 0x0694011D | (1 << 12) | (2 << 28));
244
+
245
+ tve_writel(TV_ADJ_TIMING, tve->adjtiming);
246
+ tve_writel(TV_ACT_TIMING, 0x0694011D | (1 << 12) | (2 << 28));
247
+ }
248
+ }
249
+
250
+ if (tve->soc_type == SOC_RK3528) {
251
+ u32 upsample_mode = 0;
252
+ u32 mask = 0;
253
+ u32 val = 0;
254
+ bool upsample_en;
255
+
256
+ upsample_en = tve->upsample_mode ? 1 : 0;
257
+ if (upsample_en)
258
+ upsample_mode = tve->upsample_mode - 1;
259
+ mask = m_TVE_DCLK_POL | m_TVE_DCLK_EN | m_DCLK_UPSAMPLE_2X4X |
260
+ m_DCLK_UPSAMPLE_EN | m_TVE_MODE | m_TVE_EN;
261
+ val = v_TVE_DCLK_POL(0) | v_TVE_DCLK_EN(1) | v_DCLK_UPSAMPLE_2X4X(upsample_mode) |
262
+ v_DCLK_UPSAMPLE_EN(upsample_en) | v_TVE_MODE(tve->tv_format) | v_TVE_EN(1);
263
+
264
+ tve_grf_writel(RK3528_VO_GRF_CVBS_CON, (mask << 16) | val);
265
+ }
266
+}
267
+
268
+static void dac_init(struct rockchip_tve *tve)
269
+{
270
+ tve_dac_writel(VDAC_VDAC1, v_CUR_REG(tve->dac1level) |
271
+ m_DR_PWR_DOWN | m_BG_PWR_DOWN);
272
+ tve_dac_writel(VDAC_VDAC2, v_CUR_CTR(tve->daclevel));
273
+ tve_dac_writel(VDAC_VDAC3, v_CAB_EN(0));
274
+}
275
+
276
+static void dac_enable(struct rockchip_tve *tve, bool enable)
277
+{
278
+ u32 mask = 0;
279
+ u32 val = 0;
280
+ u32 grfreg = 0;
281
+ u32 offset = 0;
282
+
283
+ if (enable) {
284
+ TVEDBG("tve enable\n");
285
+
286
+ if (tve->soc_type == SOC_RK3036) {
287
+ mask = m_VBG_EN | m_DAC_EN | m_DAC_GAIN;
288
+ val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(tve->daclevel);
289
+ grfreg = RK3036_GRF_SOC_CON3;
290
+ } else if (tve->soc_type == SOC_RK312X) {
291
+ mask = m_VBG_EN | m_DAC_EN | m_DAC_GAIN;
292
+ val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(tve->daclevel);
293
+ grfreg = RK312X_GRF_TVE_CON;
294
+ } else if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
295
+ val = v_CUR_REG(tve->dac1level) | v_DR_PWR_DOWN(0) | v_BG_PWR_DOWN(0);
296
+ } else if (tve->soc_type == SOC_RK3528) {
297
+ /*
298
+ * Reset the vdac
299
+ */
300
+ tve_dac_writel(VDAC_CLK_RST, v_ANALOG_RST(0) | v_DIGITAL_RST(0));
301
+ mdelay(20);
302
+ tve_dac_writel(VDAC_CLK_RST, v_ANALOG_RST(1) | v_DIGITAL_RST(1));
303
+
304
+ tve_dac_writel(VDAC_CURRENT_CTRL, v_OUT_CURRENT(0xd2));
305
+
306
+ val = v_REF_VOLTAGE(7) | v_DAC_PWN(1) | v_BIAS_PWN(1);
307
+ offset = VDAC_PWM_REF_CTRL;
308
+ }
309
+ } else {
310
+ TVEDBG("tve disable\n");
311
+
312
+ if (tve->soc_type == SOC_RK312X) {
313
+ mask = m_VBG_EN | m_DAC_EN;
314
+ grfreg = RK312X_GRF_TVE_CON;
315
+ } else if (tve->soc_type == SOC_RK3036) {
316
+ mask = m_VBG_EN | m_DAC_EN;
317
+ grfreg = RK3036_GRF_SOC_CON3;
318
+ } else if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
319
+ val = v_CUR_REG(tve->dac1level) | m_DR_PWR_DOWN | m_BG_PWR_DOWN;
320
+ offset = VDAC_VDAC1;
321
+ } else if (tve->soc_type == SOC_RK3528) {
322
+ val = v_DAC_PWN(0) | v_BIAS_PWN(0);
323
+ offset = VDAC_PWM_REF_CTRL;
324
+ }
325
+ }
326
+
327
+ if (grfreg)
328
+ tve_grf_writel(grfreg, (mask << 16) | val);
329
+ else if (tve->vdac_base)
330
+ tve_dac_writel(offset, val);
331
+}
332
+
333
+static u8 rk_get_vdac_value(void)
334
+{
335
+ u8 value = 0;
336
+#ifdef CONFIG_ROCKCHIP_EFUSE
337
+#if defined(CONFIG_ROCKCHIP_RK322X)
338
+ struct udevice *dev;
339
+ u32 regs[2] = {0};
340
+ u8 fuses[1];
341
+ ofnode node;
342
+ int ret;
343
+
344
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(rockchip_efuse), &dev);
345
+ if (ret) {
346
+ printf("%s: no misc-device found\n", __func__);
347
+ return -EINVAL;
348
+ }
349
+
350
+ node = dev_read_subnode(dev, "tve_dac");
351
+ if (!ofnode_valid(node))
352
+ return -EINVAL;
353
+
354
+ ret = ofnode_read_u32_array(node, "reg", regs, 2);
355
+ if (ret) {
356
+ printf("Cannot get efuse reg\n");
357
+ return -EINVAL;
358
+ }
359
+
360
+ ret = misc_read(dev, regs[0], &fuses, regs[1]);
361
+ if (ret) {
362
+ printf("%s: misc_read failed\n", __func__);
363
+ return 0;
364
+ }
365
+
366
+ value = fuses[0];
367
+ value = (value >> 3) & 0x1f;
368
+#endif
369
+#endif /* CONFIG_RK_EFUSE */
370
+ if (value > 0)
371
+ value += 5;
372
+ TVEDBG("%s value = 0x%x\n", __func__, value);
373
+
374
+ return value;
375
+}
376
+
377
+static int tve_parse_dt(struct rockchip_tve *tve)
378
+{
379
+ tve->preferred_mode = dev_read_u32_default(tve->dev, "rockchip,tvemode", -1);
380
+ if (tve->preferred_mode < 0) {
381
+ tve->preferred_mode = 0;
382
+ } else if (tve->preferred_mode > 1) {
383
+ printf("tve mode value invalid\n");
384
+ return -EINVAL;
385
+ }
386
+
387
+ tve->lumafilter0 = dev_read_u32_default(tve->dev, "rockchip,lumafilter0", 0);
388
+ if (tve->lumafilter0 == 0) {
389
+ printf("tve get lumafilter0 err\n");
390
+ return -EINVAL;
391
+ }
392
+
393
+ tve->lumafilter1 = dev_read_u32_default(tve->dev, "rockchip,lumafilter1", 0);
394
+ if (tve->lumafilter1 == 0) {
395
+ printf("tve get lumafilter1 err\n");
396
+ return -EINVAL;
397
+ }
398
+
399
+ tve->lumafilter2 = dev_read_u32_default(tve->dev, "rockchip,lumafilter2", 0);
400
+ if (tve->lumafilter2 == 0) {
401
+ printf("tve get lumafilter2 err\n");
402
+ return -EINVAL;
403
+ }
404
+
405
+ tve->lumafilter3 = dev_read_u32_default(tve->dev, "rockchip,lumafilter3", 0);
406
+ if (tve->lumafilter3 == 0) {
407
+ printf("tve get lumafilter3 err\n");
408
+ return -EINVAL;
409
+ }
410
+
411
+ tve->lumafilter4 = dev_read_u32_default(tve->dev, "rockchip,lumafilter4", 0);
412
+ if (tve->lumafilter4 == 0) {
413
+ printf("tve get lumafilter4 err\n");
414
+ return -EINVAL;
415
+ }
416
+
417
+ tve->lumafilter5 = dev_read_u32_default(tve->dev, "rockchip,lumafilter5", 0);
418
+ if (tve->lumafilter5 == 0) {
419
+ printf("tve get lumafilter5 err\n");
420
+ return -EINVAL;
421
+ }
422
+
423
+ tve->lumafilter6 = dev_read_u32_default(tve->dev, "rockchip,lumafilter6", 0);
424
+ if (tve->lumafilter6 == 0) {
425
+ printf("tve get lumafilter6 err\n");
426
+ return -EINVAL;
427
+ }
428
+
429
+ tve->lumafilter7 = dev_read_u32_default(tve->dev, "rockchip,lumafilter7", 0);
430
+ if (tve->lumafilter7 == 0) {
431
+ printf("tve get lumafilter7 err\n");
432
+ return -EINVAL;
433
+ }
434
+
435
+ tve->upsample_mode = dev_read_u32_default(tve->dev, "rockchip,tve-upsample", -1);
436
+ if (tve->upsample_mode < 0 || tve->upsample_mode > DCLK_UPSAMPLEx4) {
437
+ printf("tve get upsample_mode err\n");
438
+ return -EINVAL;
439
+ }
440
+
441
+ TVEDBG("tve->preferred_mode = 0x%x\n", tve->preferred_mode);
442
+ TVEDBG("tve->lumafilter0 = 0x%x\n", tve->lumafilter0);
443
+ TVEDBG("tve->lumafilter1 = 0x%x\n", tve->lumafilter1);
444
+ TVEDBG("tve->lumafilter2 = 0x%x\n", tve->lumafilter2);
445
+ TVEDBG("tve->lumafilter3 = 0x%x\n", tve->lumafilter3);
446
+ TVEDBG("tve->lumafilter4 = 0x%x\n", tve->lumafilter4);
447
+ TVEDBG("tve->lumafilter5 = 0x%x\n", tve->lumafilter5);
448
+ TVEDBG("tve->lumafilter6 = 0x%x\n", tve->lumafilter6);
449
+ TVEDBG("tve->lumafilter7 = 0x%x\n", tve->lumafilter7);
450
+ TVEDBG("tve->upsample_mode = 0x%x\n", tve->upsample_mode);
451
+
452
+ return 0;
453
+}
454
+
455
+static int tve_parse_dt_legacy(struct rockchip_tve *tve)
456
+{
457
+ int dac_value, getvdac;
458
+
459
+ if (tve->soc_type == SOC_RK312X)
460
+ tve->test_mode = dev_read_u32_default(tve->dev, "test_mode", 0);
461
+
462
+ tve->preferred_mode = dev_read_u32_default(tve->dev, "rockchip,tvemode", -1);
463
+ if (tve->preferred_mode < 0) {
464
+ tve->preferred_mode = 0;
465
+ } else if (tve->preferred_mode > 1) {
466
+ printf("tve mode value invalid\n");
467
+ return -EINVAL;
468
+ }
469
+
470
+ tve->saturation = dev_read_u32_default(tve->dev, "rockchip,saturation", 0);
471
+ if (tve->saturation == 0) {
472
+ printf("tve get saturation err\n");
473
+ return -EINVAL;
474
+ }
475
+
476
+ tve->brightcontrast = dev_read_u32_default(tve->dev, "rockchip,brightcontrast", 0);
477
+ if (tve->brightcontrast == 0) {
478
+ printf("tve get brightcontrast err\n");
479
+ return -EINVAL;
480
+ }
481
+
482
+ tve->adjtiming = dev_read_u32_default(tve->dev, "rockchip,adjtiming", 0);
483
+ if (tve->adjtiming == 0) {
484
+ printf("tve get adjtiming err\n");
485
+ return -EINVAL;
486
+ }
487
+
488
+ tve->lumafilter0 = dev_read_u32_default(tve->dev, "rockchip,lumafilter0", 0);
489
+ if (tve->lumafilter0 == 0) {
490
+ printf("tve get lumafilter0 err\n");
491
+ return -EINVAL;
492
+ }
493
+
494
+ tve->lumafilter1 = dev_read_u32_default(tve->dev, "rockchip,lumafilter1", 0);
495
+ if (tve->lumafilter1 == 0) {
496
+ printf("tve get lumafilter1 err\n");
497
+ return -EINVAL;
498
+ }
499
+
500
+ tve->lumafilter2 = dev_read_u32_default(tve->dev, "rockchip,lumafilter2", 0);
501
+ if (tve->lumafilter2 == 0) {
502
+ printf("tve get lumafilter2 err\n");
503
+ return -EINVAL;
504
+ }
505
+
506
+ dac_value = dev_read_u32_default(tve->dev, "rockchip,daclevel", 0);
507
+ if (dac_value == 0) {
508
+ printf("tve get dac_value err\n");
509
+ return -EINVAL;
510
+ }
511
+
512
+ tve->daclevel = dac_value;
513
+ if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
514
+ getvdac = rk_get_vdac_value();
515
+ if (getvdac > 0) {
516
+ tve->daclevel = dac_value + getvdac - RK322X_VDAC_STANDARD;
517
+ if (tve->daclevel > 0x3f || tve->daclevel < 0) {
518
+ printf("rk322x daclevel error!\n");
519
+ tve->daclevel = dac_value;
520
+ }
521
+ } else if (getvdac < 0) {
522
+ printf("get rk322x daclevel error\n");
523
+ return -EINVAL;
524
+ }
525
+ }
526
+
527
+ if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
528
+ tve->dac1level = dev_read_u32_default(tve->dev, "rockchip,dac1level", 0);
529
+ if (tve->dac1level == 0) {
530
+ printf("rk322x dac1level error!\n");
531
+ return -EINVAL;
532
+ }
533
+ }
534
+
535
+ TVEDBG("tve->test_mode = 0x%x\n", tve->test_mode);
536
+ TVEDBG("tve->saturation = 0x%x\n", tve->saturation);
537
+ TVEDBG("tve->brightcontrast = 0x%x\n", tve->brightcontrast);
538
+ TVEDBG("tve->adjtiming = 0x%x\n", tve->adjtiming);
539
+ TVEDBG("tve->lumafilter0 = 0x%x\n", tve->lumafilter0);
540
+ TVEDBG("tve->lumafilter1 = 0x%x\n", tve->lumafilter1);
541
+ TVEDBG("tve->lumafilter2 = 0x%x\n", tve->lumafilter2);
542
+ TVEDBG("tve->daclevel = 0x%x\n", tve->daclevel);
543
+
544
+ return 0;
545
+}
546
+
547
+static int rockchip_drm_tve_init(struct rockchip_connector *conn, struct display_state *state)
548
+{
549
+ struct rockchip_tve *tve = dev_get_priv(conn->dev);
550
+ struct connector_state *conn_state = &state->conn_state;
551
+ fdt_addr_t addr;
552
+ int ret;
553
+
554
+ conn_state->output_mode = ROCKCHIP_OUT_MODE_P888;
555
+ conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24;
556
+ if (tve->soc_type == SOC_RK3528)
557
+ conn_state->output_if |= VOP_OUTPUT_IF_BT656;
558
+ conn_state->color_space = V4L2_COLORSPACE_SMPTE170M;
559
+
560
+ conn_state->disp_info = rockchip_get_disp_info(conn_state->type, 0);
561
+
562
+ if (tve->soc_type == SOC_RK3528)
563
+ ret = tve_parse_dt(tve);
564
+ else
565
+ ret = tve_parse_dt_legacy(tve);
566
+ if (ret) {
567
+ printf("tve parse dts error\n");
568
+ return -EINVAL;
569
+ }
570
+
571
+ addr = dev_read_addr_index(conn->dev, 0);
572
+ if (addr == FDT_ADDR_T_NONE) {
573
+ printf("failed to get tve reg_base\n");
574
+ return -EINVAL;
575
+ }
576
+ tve->reg_base = (void *)addr;
577
+
578
+ if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328 ||
579
+ tve->soc_type == SOC_RK3528) {
580
+ addr = dev_read_addr_index(conn->dev, 1);
581
+ if (addr == FDT_ADDR_T_NONE) {
582
+ printf("failed to get tve vdac_base\n");
583
+ return -EINVAL;
584
+ }
585
+ tve->vdac_base = (void *)addr;
586
+ }
587
+
588
+ tve->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
589
+
590
+ if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328)
591
+ dac_init(tve);
592
+
593
+ return 0;
594
+}
595
+
596
+static int rockchip_drm_tve_enable(struct rockchip_connector *conn, struct display_state *state)
597
+{
598
+ struct rockchip_tve *tve = dev_get_priv(conn->dev);
599
+ struct connector_state *conn_state = &state->conn_state;
600
+ struct drm_display_mode *mode = &conn_state->mode;
601
+
602
+#ifdef CONFIG_ROCKCHIP_INNO_HDMI_PHY
603
+ /* set inno hdmi phy clk. */
604
+ if (tve->soc_type != SOC_RK3528)
605
+ rockchip_phy_set_pll(conn->phy, 27000000);
606
+#endif
607
+ if (mode->vdisplay == 576)
608
+ tve->tv_format = TVOUT_CVBS_PAL;
609
+ else
610
+ tve->tv_format = TVOUT_CVBS_NTSC;
611
+
612
+ tve_set_mode(tve);
613
+ mdelay(1000);
614
+ dac_enable(tve, true);
615
+
616
+ return 0;
617
+}
618
+
619
+static void rockchip_drm_tve_deinit(struct rockchip_connector *conn, struct display_state *state)
620
+{
621
+ struct rockchip_tve *tve = dev_get_priv(conn->dev);
622
+
623
+ dac_enable(tve, false);
624
+}
625
+
626
+static int rockchip_drm_tve_prepare(struct rockchip_connector *conn, struct display_state *state)
627
+{
628
+ return 0;
629
+}
630
+
631
+static int rockchip_drm_tve_disable(struct rockchip_connector *conn, struct display_state *state)
632
+{
633
+ struct rockchip_tve *tve = dev_get_priv(conn->dev);
634
+
635
+ dac_enable(tve, false);
636
+
637
+ return 0;
638
+}
639
+
640
+static int rockchip_drm_tve_detect(struct rockchip_connector *conn, struct display_state *state)
641
+{
642
+ return 1;
643
+}
644
+
645
+static void tve_select_output(struct rockchip_tve *tve, struct connector_state *conn_state,
646
+ struct drm_display_mode *mode)
647
+{
648
+ int ret, i, screen_size;
649
+ struct base_screen_info *screen_info = NULL;
650
+ struct base2_screen_info *screen_info2 = NULL;
651
+ struct base_disp_info base_parameter;
652
+ struct base2_disp_info *base2_parameter = conn_state->disp_info;
653
+ struct drm_display_mode modes[2];
654
+ const struct base_overscan *scan;
655
+ struct overscan *overscan = &conn_state->overscan;
656
+ char baseparameter_buf[8 * RK_BLK_SIZE] __aligned(ARCH_DMA_MINALIGN);
657
+ struct blk_desc *dev_desc;
658
+ disk_partition_t part_info;
659
+ int max_scan = 100;
660
+ int min_scan = 50;
661
+ int offset = 0;
662
+ bool found = false;
663
+
664
+ for (i = 0; i < 2; i++) {
665
+ modes[i] = tve_modes[i];
666
+ if (i == tve->preferred_mode)
667
+ modes[i].type |= DRM_MODE_TYPE_PREFERRED;
668
+ }
669
+ *mode = modes[tve->preferred_mode];
670
+
671
+ if (!base2_parameter) {
672
+ dev_desc = rockchip_get_bootdev();
673
+ if (!dev_desc) {
674
+ printf("%s: Could not find device\n", __func__);
675
+ goto null_basep;
676
+ }
677
+
678
+ ret = part_get_info_by_name(dev_desc, "baseparameter",
679
+ &part_info);
680
+ if (ret < 0) {
681
+ printf("Could not find baseparameter partition\n");
682
+ goto null_basep;
683
+ }
684
+
685
+read_aux:
686
+ ret = blk_dread(dev_desc, part_info.start + offset, 1,
687
+ (void *)baseparameter_buf);
688
+ if (ret < 0) {
689
+ printf("read baseparameter failed\n");
690
+ goto null_basep;
691
+ }
692
+
693
+ memcpy(&base_parameter, baseparameter_buf,
694
+ sizeof(base_parameter));
695
+ scan = &base_parameter.scan;
696
+
697
+ screen_size = sizeof(base_parameter.screen_list) /
698
+ sizeof(base_parameter.screen_list[0]);
699
+
700
+ for (i = 0; i < screen_size; i++) {
701
+ if (base_parameter.screen_list[i].type ==
702
+ DRM_MODE_CONNECTOR_TV) {
703
+ found = true;
704
+ screen_info = &base_parameter.screen_list[i];
705
+ break;
706
+ }
707
+ }
708
+
709
+ if (!found && !offset) {
710
+ printf("cvbs info isn't saved in main block\n");
711
+ offset += 16;
712
+ goto read_aux;
713
+ }
714
+ } else {
715
+ scan = &base2_parameter->overscan_info;
716
+ screen_size = sizeof(base2_parameter->screen_info) /
717
+ sizeof(base2_parameter->screen_info[0]);
718
+
719
+ for (i = 0; i < screen_size; i++) {
720
+ if (base2_parameter->screen_info[i].type ==
721
+ DRM_MODE_CONNECTOR_TV) {
722
+ screen_info2 =
723
+ &base2_parameter->screen_info[i];
724
+ break;
725
+ }
726
+ }
727
+ screen_info = malloc(sizeof(*screen_info));
728
+
729
+ screen_info->type = screen_info2->type;
730
+ screen_info->mode = screen_info2->resolution;
731
+ screen_info->format = screen_info2->format;
732
+ screen_info->depth = screen_info2->depthc;
733
+ screen_info->feature = screen_info2->feature;
734
+ }
735
+
736
+ if (scan->leftscale < min_scan && scan->leftscale > 0)
737
+ overscan->left_margin = min_scan;
738
+ else if (scan->leftscale < max_scan && scan->leftscale > 0)
739
+ overscan->left_margin = scan->leftscale;
740
+
741
+ if (scan->rightscale < min_scan && scan->rightscale > 0)
742
+ overscan->right_margin = min_scan;
743
+ else if (scan->rightscale < max_scan && scan->rightscale > 0)
744
+ overscan->right_margin = scan->rightscale;
745
+
746
+ if (scan->topscale < min_scan && scan->topscale > 0)
747
+ overscan->top_margin = min_scan;
748
+ else if (scan->topscale < max_scan && scan->topscale > 0)
749
+ overscan->top_margin = scan->topscale;
750
+
751
+ if (scan->bottomscale < min_scan && scan->bottomscale > 0)
752
+ overscan->bottom_margin = min_scan;
753
+ else if (scan->bottomscale < max_scan && scan->bottomscale > 0)
754
+ overscan->bottom_margin = scan->bottomscale;
755
+
756
+null_basep:
757
+
758
+ if (screen_info)
759
+ printf("cvbs base_parameter.mode:%dx%d\n",
760
+ screen_info->mode.hdisplay,
761
+ screen_info->mode.vdisplay);
762
+
763
+ if (screen_info &&
764
+ (screen_info->mode.hdisplay == 720 &&
765
+ screen_info->mode.vdisplay == 576))
766
+ *mode = modes[0];
767
+ else if (screen_info &&
768
+ (screen_info->mode.hdisplay == 720 &&
769
+ screen_info->mode.vdisplay == 480))
770
+ *mode = modes[1];
771
+}
772
+
773
+static int rockchip_drm_tve_get_timing(struct rockchip_connector *conn, struct display_state *state)
774
+{
775
+ struct rockchip_tve *tve = dev_get_priv(conn->dev);
776
+ struct connector_state *conn_state = &state->conn_state;
777
+ struct drm_display_mode *mode = &conn_state->mode;
778
+
779
+ tve_select_output(tve, conn_state, mode);
780
+
781
+ return 0;
782
+}
783
+
784
+const struct rockchip_connector_funcs rockchip_drm_tve_funcs = {
785
+ .init = rockchip_drm_tve_init,
786
+ .deinit = rockchip_drm_tve_deinit,
787
+ .prepare = rockchip_drm_tve_prepare,
788
+ .enable = rockchip_drm_tve_enable,
789
+ .disable = rockchip_drm_tve_disable,
790
+ .get_timing = rockchip_drm_tve_get_timing,
791
+ .detect = rockchip_drm_tve_detect,
792
+};
793
+
794
+static int rockchip_drm_tve_probe(struct udevice *dev)
795
+{
796
+ struct rockchip_tve *tve = dev_get_priv(dev);
797
+ const struct rockchip_tve_data *data;
798
+
799
+ tve->dev = dev;
800
+ data = (const struct rockchip_tve_data *)dev_get_driver_data(dev);
801
+ tve->soc_type = data->soc_type;
802
+ tve->input_format = data->input_format;
803
+
804
+ rockchip_connector_bind(&tve->connector, dev, 0, &rockchip_drm_tve_funcs, NULL, DRM_MODE_CONNECTOR_TV);
805
+
806
+ return 0;
807
+}
808
+
809
+static const struct rockchip_tve_data rk3036_tve = {
810
+ .soc_type = SOC_RK3036,
811
+ .input_format = INPUT_FORMAT_RGB,
812
+};
813
+
814
+static const struct rockchip_tve_data rk312x_tve = {
815
+ .soc_type = SOC_RK312X,
816
+ .input_format = INPUT_FORMAT_RGB,
817
+};
818
+
819
+static const struct rockchip_tve_data rk322x_tve = {
820
+ .soc_type = SOC_RK322X,
821
+ .input_format = INPUT_FORMAT_YUV,
822
+};
823
+
824
+static const struct rockchip_tve_data rk3328_tve = {
825
+ .soc_type = SOC_RK3328,
826
+ .input_format = INPUT_FORMAT_YUV,
827
+};
828
+
829
+static const struct rockchip_tve_data rk3528_tve = {
830
+ .soc_type = SOC_RK3528,
831
+ .input_format = INPUT_FORMAT_YUV,
832
+};
833
+
834
+static const struct udevice_id rockchip_drm_tve_ids[] = {
835
+ { .compatible = "rockchip,rk3036-tve", .data = (ulong)&rk3036_tve },
836
+ { .compatible = "rockchip,rk312x-tve", .data = (ulong)&rk312x_tve },
837
+ { .compatible = "rockchip,rk322x-tve", .data = (ulong)&rk322x_tve },
838
+ { .compatible = "rockchip,rk3328-tve", .data = (ulong)&rk3328_tve },
839
+ { .compatible = "rockchip,rk3528-tve", .data = (ulong)&rk3528_tve },
840
+};
841
+
842
+U_BOOT_DRIVER(rockchip_drm_tve) = {
843
+ .name = "rockchip_drm_tve",
844
+ .id = UCLASS_DISPLAY,
845
+ .of_match = rockchip_drm_tve_ids,
846
+ .probe = rockchip_drm_tve_probe,
847
+ .priv_auto_alloc_size = sizeof(struct rockchip_tve),
848
+};
u-boot/drivers/video/drm/rockchip_tve.h
....@@ -0,0 +1,253 @@
1
+/*
2
+ * SPDX-License-Identifier: GPL-2.0+
3
+ * (C) Copyright 2008-2015 Fuzhou Rockchip Electronics Co., Ltd
4
+ */
5
+#ifndef __ROCKCHIP_TVE_H__
6
+#define __ROCKCHIP_TVE_H__
7
+
8
+#define RK3036_GRF_SOC_CON3 0x0154
9
+#define RK312X_GRF_TVE_CON 0x0170
10
+ #define m_EXTREF_EN BIT(0)
11
+ #define m_VBG_EN BIT(1)
12
+ #define m_DAC_EN BIT(2)
13
+ #define m_SENSE_EN BIT(3)
14
+ #define m_BIAS_EN (7 << 4)
15
+ #define m_DAC_GAIN (0x3f << 7)
16
+ #define v_DAC_GAIN(x) (((x) & 0x3f) << 7)
17
+
18
+#define TV_CTRL (0x00)
19
+ #define m_CVBS_MODE BIT(24)
20
+ #define m_CLK_UPSTREAM_EN (3 << 18)
21
+ #define m_TIMING_EN (3 << 16)
22
+ #define m_LUMA_FILTER_GAIN (3 << 9)
23
+ #define m_LUMA_FILTER_BW BIT(8)
24
+ #define m_CSC_PATH (3 << 1)
25
+
26
+ #define v_CVBS_MODE(x) (((x) & 1) << 24)
27
+ #define v_CLK_UPSTREAM_EN(x) (((x) & 3) << 18)
28
+ #define v_TIMING_EN(x) (((x) & 3) << 16)
29
+ #define v_LUMA_FILTER_GAIN(x) (((x) & 3) << 9)
30
+ #define v_LUMA_FILTER_UPSAMPLE(x) (((x) & 1) << 8)
31
+ #define v_CSC_PATH(x) (((x) & 3) << 1)
32
+
33
+#define TV_SYNC_TIMING (0x04)
34
+#define TV_ACT_TIMING (0x08)
35
+#define TV_ADJ_TIMING (0x0c)
36
+#define TV_FREQ_SC (0x10)
37
+#define TV_LUMA_FILTER0 (0x14)
38
+#define TV_LUMA_FILTER1 (0x18)
39
+#define TV_LUMA_FILTER2 (0x1C)
40
+#define TV_ACT_ST (0x34)
41
+#define TV_ROUTING (0x38)
42
+ #define m_DAC_SENSE_EN BIT(27)
43
+ #define m_Y_IRE_7_5 BIT(19)
44
+ #define m_Y_AGC_PULSE_ON BIT(15)
45
+ #define m_Y_VIDEO_ON BIT(11)
46
+ #define m_Y_SYNC_ON BIT(7)
47
+ #define m_YPP_MODE BIT(3)
48
+ #define m_MONO_EN BIT(2)
49
+ #define m_PIC_MODE BIT(1)
50
+
51
+ #define v_DAC_SENSE_EN(x) (((x) & 1) << 27)
52
+ #define v_Y_IRE_7_5(x) (((x) & 1) << 19)
53
+ #define v_Y_AGC_PULSE_ON(x) (((x) & 1) << 15)
54
+ #define v_Y_VIDEO_ON(x) (((x) & 1) << 11)
55
+ #define v_Y_SYNC_ON(x) (((x) & 1) << 7)
56
+ #define v_YPP_MODE(x) (((x) & 1) << 3)
57
+ #define v_MONO_EN(x) (((x) & 1) << 2)
58
+ #define v_PIC_MODE(x) (((x) & 1) << 1)
59
+
60
+#define TV_SYNC_ADJUST (0x50)
61
+#define TV_STATUS (0x54)
62
+#define TV_RESET (0x68)
63
+ #define m_RESET BIT(1)
64
+ #define v_RESET(x) (((x) & 1) << 1)
65
+#define TV_SATURATION (0x78)
66
+#define TV_BW_CTRL (0x8C)
67
+ #define m_CHROMA_BW (3 << 4)
68
+ #define m_COLOR_DIFF_BW (0xf)
69
+
70
+ enum {
71
+ BP_FILTER_PASS = 0,
72
+ BP_FILTER_NTSC,
73
+ BP_FILTER_PAL,
74
+ };
75
+ enum {
76
+ COLOR_DIFF_FILTER_OFF = 0,
77
+ COLOR_DIFF_FILTER_BW_0_6,
78
+ COLOR_DIFF_FILTER_BW_1_3,
79
+ COLOR_DIFF_FILTER_BW_2_0
80
+ };
81
+
82
+ #define v_CHROMA_BW(x) ((3 & (x)) << 4)
83
+ #define v_COLOR_DIFF_BW(x) (0xF & (x))
84
+
85
+#define TV_BRIGHTNESS_CONTRAST (0x90)
86
+
87
+#define VDAC_VDAC0 (0x00)
88
+ #define m_RST_ANA BIT(7)
89
+ #define m_RST_DIG BIT(6)
90
+
91
+ #define v_RST_ANA(x) (((x) & 1) << 7)
92
+ #define v_RST_DIG(x) (((x) & 1) << 6)
93
+#define VDAC_VDAC1 (0x280)
94
+ #define m_CUR_REG (0xf << 4)
95
+ #define m_DR_PWR_DOWN BIT(1)
96
+ #define m_BG_PWR_DOWN BIT(0)
97
+
98
+ #define v_CUR_REG(x) (((x) & 0xf) << 4)
99
+ #define v_DR_PWR_DOWN(x) (((x) & 1) << 1)
100
+ #define v_BG_PWR_DOWN(x) (((x) & 1) << 0)
101
+#define VDAC_VDAC2 (0x284)
102
+ #define m_CUR_CTR (0X3f)
103
+
104
+ #define v_CUR_CTR(x) (((x) & 0x3f))
105
+#define VDAC_VDAC3 (0x288)
106
+ #define m_CAB_EN BIT(5)
107
+ #define m_CAB_REF BIT(4)
108
+ #define m_CAB_FLAG BIT(0)
109
+
110
+ #define v_CAB_EN(x) (((x) & 1) << 5)
111
+ #define v_CAB_REF(x) (((x) & 1) << 4)
112
+ #define v_CAB_FLAG(x) (((x) & 1) << 0)
113
+
114
+// RK3528 CVBS GRF
115
+#define RK3528_VO_GRF_VDAC_DIS 0x60000
116
+ #define m_VDAC_DIS_NEGE_ST BIT(2)
117
+ #define m_VDAC_DIS_POSE_ST BIT(1)
118
+ #define m_STAT_VDAC_DISDET BIT(0)
119
+
120
+ #define v_VDAC_DIS_NEGE_ST(x) (((x) & 1) << 2)
121
+ #define v_VDAC_DIS_POSE_ST(x) (((x) & 1) << 1)
122
+ #define v_STAT_VDAC_DISDET(x) (((x) & 1) << 0)
123
+
124
+#define RK3528_VO_GRF_CVBS_CON 0x60010
125
+ #define m_VDAC_DIS_INT_EN BIT(8)
126
+ #define m_VDAC_DIS_NEGE_MASK BIT(7)
127
+ #define m_VDAC_DIS_POSE_MASK BIT(6)
128
+ #define m_TVE_DCLK_POL BIT(5)
129
+ #define m_TVE_DCLK_EN BIT(4)
130
+ #define m_DCLK_UPSAMPLE_2X4X BIT(3)
131
+ #define m_DCLK_UPSAMPLE_EN BIT(2)
132
+ #define m_TVE_MODE BIT(1)
133
+ #define m_TVE_EN BIT(0)
134
+
135
+ #define v_VDAC_DIS_INT_EN(x) (((x) & 1) << 8)
136
+ #define v_VDAC_DIS_NEGE_MASK(x) (((x) & 1) << 7)
137
+ #define v_VDAC_DIS_POSE_MASK(x) (((x) & 1) << 6)
138
+ #define v_TVE_DCLK_POL(x) (((x) & 1) << 5)
139
+ #define v_TVE_DCLK_EN(x) (((x) & 1) << 4)
140
+ #define v_DCLK_UPSAMPLE_2X4X(x) (((x) & 1) << 3)
141
+ #define v_DCLK_UPSAMPLE_EN(x) (((x) & 1) << 2)
142
+ #define v_TVE_MODE(x) (((x) & 1) << 1)
143
+ #define v_TVE_EN(x) (((x) & 1) << 0)
144
+
145
+// RK3528 CVBS TVE
146
+#define BT656_DECODER_CTRL (0x3D00)
147
+#define BT656_DECODER_CROP (0x3D04)
148
+#define BT656_DECODER_SIZE (0x3D08)
149
+#define BT656_DECODER_HTOTAL_HS_END (0x3D0C)
150
+#define BT656_DECODER_VACT_ST_HACT_ST (0x3D10)
151
+#define BT656_DECODER_VTOTAL_VS_END (0x3D14)
152
+#define BT656_DECODER_VS_ST_END_F1 (0x3D18)
153
+#define BT656_DECODER_DBG_REG (0x3D1C)
154
+#define TVE_MODE_CTRL (0x3E00)
155
+#define TVE_HOR_TIMING1 (0x3E04)
156
+#define TVE_HOR_TIMING2 (0x3E08)
157
+#define TVE_HOR_TIMING3 (0x3E0C)
158
+#define TVE_SUB_CAR_FRQ (0x3E10)
159
+#define TVE_LUMA_FILTER1 (0x3E14)
160
+#define TVE_LUMA_FILTER2 (0x3E18)
161
+#define TVE_LUMA_FILTER3 (0x3E1C)
162
+#define TVE_LUMA_FILTER4 (0x3E20)
163
+#define TVE_LUMA_FILTER5 (0x3E24)
164
+#define TVE_LUMA_FILTER6 (0x3E28)
165
+#define TVE_LUMA_FILTER7 (0x3E2C)
166
+#define TVE_LUMA_FILTER8 (0x3E30)
167
+#define TVE_IMAGE_POSITION (0x3E34)
168
+#define TVE_ROUTING (0x3E38)
169
+#define TVE_SYNC_ADJUST (0x3E50)
170
+#define TVE_STATUS (0x3E54)
171
+#define TVE_CTRL (0x3E68)
172
+#define TVE_INTR_STATUS (0x3E6C)
173
+#define TVE_INTR_EN (0x3E70)
174
+#define TVE_INTR_CLR (0x3E74)
175
+#define TVE_COLOR_BUSRT_SAT (0x3E78)
176
+#define TVE_CHROMA_BANDWIDTH (0x3E8C)
177
+#define TVE_BRIGHTNESS_CONTRAST (0x3E90)
178
+#define TVE_ID (0x3E98)
179
+#define TVE_REVISION (0x3E9C)
180
+#define TVE_CLAMP (0x3EA0)
181
+
182
+// RK3528 CVBS VDAC
183
+#define VDAC_CLK_RST (0x0000)
184
+ #define m_ANALOG_RST BIT(7)
185
+ #define m_DIGITAL_RST BIT(6)
186
+ #define m_INPUT_CLK_INV BIT(0)
187
+
188
+ #define v_ANALOG_RST(x) (((x) & 1) << 7)
189
+ #define v_DIGITAL_RST(x) (((x) & 1) << 6)
190
+ #define v_INPUT_CLK_INV(x) (((x) & 1) << 0)
191
+#define VDAC_SINE_CTRL (0x0004)
192
+#define VDAC_SQUARE_CTRL (0x0008)
193
+#define VDAC_LEVEL_CTRL0 (0x0018)
194
+#define VDAC_LEVEL_CTRL1 (0x001C)
195
+#define VDAC_PWM_REF_CTRL (0x0280)
196
+ #define m_REF_VOLTAGE (0xf << 4)
197
+ #define m_REF_RESISTOR BIT(3)
198
+ #define m_SMP_CLK_INV BIT(2)
199
+ #define m_DAC_PWN BIT(1)
200
+ #define m_BIAS_PWN BIT(0)
201
+
202
+ #define v_REF_VOLTAGE(x) (((x) & 0xf) << 4)
203
+ #define v_SMP_CLK_INV(x) (((x) & 1) << 2)
204
+ #define v_REF_RESISTOR(x) (((x) & 1) << 3)
205
+ #define v_DAC_PWN(x) (((x) & 1) << 1)
206
+ #define v_BIAS_PWN(x) (((x) & 1) << 0)
207
+#define VDAC_CURRENT_CTRL (0x0284)
208
+ #define m_OUT_CURRENT (0xff << 0)
209
+
210
+ #define v_OUT_CURRENT(x) (((x) & 0xff) << 0)
211
+#define VDAC_CABLE_CTRL (0x0288)
212
+#define VDAC_VOLTAGE_CTRL (0x028C)
213
+#define VDAC_BIAS_CLK_CTRL0 (0x0290)
214
+#define VDAC_BIAS_CLK_CTRL1 (0x0294)
215
+#define VDAC_AUTO_CLK_CTRL0 (0x0298)
216
+#define VDAC_AUTO_CLK_CTRL1 (0x029C)
217
+
218
+enum {
219
+ TVOUT_CVBS_NTSC = 0,
220
+ TVOUT_CVBS_PAL,
221
+};
222
+
223
+enum {
224
+ INPUT_FORMAT_RGB = 0,
225
+ INPUT_FORMAT_YUV
226
+};
227
+
228
+enum {
229
+ SOC_RK3036 = 0,
230
+ SOC_RK312X,
231
+ SOC_RK322X,
232
+ SOC_RK3328,
233
+ SOC_RK3528
234
+};
235
+
236
+
237
+enum {
238
+ DCLK_UPSAMPLEx1 = 0,
239
+ DCLK_UPSAMPLEx2,
240
+ DCLK_UPSAMPLEx4
241
+};
242
+
243
+#define RK30_TVE_REGBASE 0x10118000 + 0x200
244
+#define MAX_TVE_COUNT 2
245
+
246
+#ifdef TVEDEBUG
247
+#define TVEDBG(format, ...) \
248
+ printf("TVE: " format, ## __VA_ARGS__)
249
+#else
250
+#define TVEDBG(format, ...)
251
+#endif
252
+
253
+#endif /* __ROCKCHIP_TVE_H__ */
u-boot/drivers/video/drm/rockchip_vop.c
....@@ -97,6 +97,19 @@
9797 return false;
9898 }
9999
100
+static bool is_rb_swap(uint32_t bus_format, uint32_t output_mode)
101
+{
102
+ /*
103
+ * The default component order of serial rgb3x8 formats
104
+ * is BGR. So it is needed to enable RB swap.
105
+ */
106
+ if (bus_format == MEDIA_BUS_FMT_SRGB888_3X8 ||
107
+ bus_format == MEDIA_BUS_FMT_SRGB888_DUMMY_4X8)
108
+ return true;
109
+ else
110
+ return false;
111
+}
112
+
100113 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state)
101114 {
102115 struct crtc_state *crtc_state = &state->crtc_state;
....@@ -298,7 +311,7 @@
298311 VOP_CTRL_SET(vop, win_channel[2], 0x56);
299312 VOP_CTRL_SET(vop, dsp_blank, 0);
300313
301
- dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1;
314
+ dclk_inv = (conn_state->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0;
302315 /* For improving signal quality, dclk need to be inverted by default on rv1106. */
303316 if ((VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) == 12))
304317 dclk_inv = !dclk_inv;
....@@ -403,8 +416,9 @@
403416 VOP_CTRL_SET(vop, hdmi_dclk_out_en,
404417 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
405418
406
- if (is_uv_swap(conn_state->bus_format, conn_state->output_mode))
407
- VOP_CTRL_SET(vop, dsp_data_swap, DSP_RB_SWAP);
419
+ if (is_uv_swap(conn_state->bus_format, conn_state->output_mode) ||
420
+ is_rb_swap(conn_state->bus_format, conn_state->output_mode))
421
+ VOP_CTRL_SET(vop, dsp_rb_swap, 1);
408422 else
409423 VOP_CTRL_SET(vop, dsp_data_swap, 0);
410424
....@@ -888,6 +902,16 @@
888902 return 0;
889903 }
890904
905
+static int rockchip_vop_mode_fixup(struct display_state *state)
906
+{
907
+ struct connector_state *conn_state = &state->conn_state;
908
+ struct drm_display_mode *mode = &conn_state->mode;
909
+
910
+ drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
911
+
912
+ return 0;
913
+}
914
+
891915 const struct rockchip_crtc_funcs rockchip_vop_funcs = {
892916 .preinit = rockchip_vop_preinit,
893917 .init = rockchip_vop_init,
....@@ -899,4 +923,5 @@
899923 .send_mcu_cmd = rockchip_vop_send_mcu_cmd,
900924 .mode_valid = rockchip_vop_mode_valid,
901925 .plane_check = rockchip_vop_plane_check,
926
+ .mode_fixup = rockchip_vop_mode_fixup,
902927 };
u-boot/drivers/video/drm/rockchip_vop.h
....@@ -298,6 +298,11 @@
298298
299299 struct vop_reg dsp_out_yuv;
300300 struct vop_reg dsp_data_swap;
301
+ struct vop_reg dsp_bg_swap;
302
+ struct vop_reg dsp_rb_swap;
303
+ struct vop_reg dsp_rg_swap;
304
+ struct vop_reg dsp_delta_swap;
305
+ struct vop_reg dsp_dummy_swap;
301306 struct vop_reg dsp_ccir656_avg;
302307 struct vop_reg dsp_black;
303308 struct vop_reg dsp_blank;
u-boot/drivers/video/drm/rockchip_vop2.c
....@@ -17,20 +17,24 @@
1717 #include <linux/list.h>
1818 #include <linux/log2.h>
1919 #include <linux/media-bus-format.h>
20
-#include <clk.h>
2120 #include <asm/arch/clock.h>
21
+#include <asm/gpio.h>
2222 #include <linux/err.h>
2323 #include <linux/ioport.h>
2424 #include <dm/device.h>
2525 #include <dm/read.h>
26
+#include <dm/ofnode.h>
2627 #include <fixp-arith.h>
2728 #include <syscon.h>
2829 #include <linux/iopoll.h>
2930 #include <dm/uclass-internal.h>
31
+#include <stdlib.h>
3032
3133 #include "rockchip_display.h"
3234 #include "rockchip_crtc.h"
3335 #include "rockchip_connector.h"
36
+#include "rockchip_phy.h"
37
+#include "rockchip_post_csc.h"
3438
3539 /* System registers definition */
3640 #define RK3568_REG_CFG_DONE 0x000
....@@ -40,9 +44,12 @@
4044 #define EN_MASK 1
4145
4246 #define RK3568_AUTO_GATING_CTRL 0x008
47
+#define AUTO_GATING_EN_SHIFT 31
48
+#define PORT_DCLK_AUTO_GATING_EN_SHIFT 14
4349
4450 #define RK3568_SYS_AXI_LUT_CTRL 0x024
4551 #define LUT_DMA_EN_SHIFT 0
52
+#define DSP_VS_T_SEL_SHIFT 16
4653
4754 #define RK3568_DSP_IF_EN 0x028
4855 #define RGB_EN_SHIFT 0
....@@ -81,6 +88,9 @@
8188 #define LVDS_DUAL_EN_SHIFT 0
8289 #define LVDS_DUAL_LEFT_RIGHT_EN_SHIFT 1
8390 #define LVDS_DUAL_SWAP_EN_SHIFT 2
91
+#define BT656_UV_SWAP 4
92
+#define BT656_YC_SWAP 5
93
+#define BT656_DCLK_POL 6
8494 #define RK3588_HDMI_DUAL_EN_SHIFT 8
8595 #define RK3588_EDP_DUAL_EN_SHIFT 8
8696 #define RK3588_DP_DUAL_EN_SHIFT 9
....@@ -93,15 +103,22 @@
93103 #define IF_CTRL_REG_DONE_IMD_SHIFT 28
94104 #define IF_CRTL_MIPI_DCLK_POL_SHIT 19
95105 #define IF_CRTL_EDP_DCLK_POL_SHIT 15
106
+#define IF_CTRL_EDP_PIN_POL_MASK 0x7
107
+#define IF_CTRL_EDP_PIN_POL_SHIFT 12
96108 #define IF_CRTL_HDMI_DCLK_POL_SHIT 7
97109 #define IF_CRTL_HDMI_PIN_POL_MASK 0x7
98110 #define IF_CRTL_HDMI_PIN_POL_SHIT 4
111
+#define IF_CTRL_RGB_LVDS_DCLK_POL_SHIFT 3
112
+#define IF_CTRL_RGB_LVDS_PIN_POL_MASK 0x7
113
+#define IF_CTRL_RGB_LVDS_PIN_POL_SHIFT 0
114
+
115
+#define RK3562_MIPI_DCLK_POL_SHIFT 15
116
+#define RK3562_MIPI_PIN_POL_SHIFT 12
117
+#define RK3562_IF_PIN_POL_MASK 0x7
99118
100119 #define RK3588_DP0_PIN_POL_SHIFT 8
101120 #define RK3588_DP1_PIN_POL_SHIFT 12
102121 #define RK3588_IF_PIN_POL_MASK 0x7
103
-
104
-#define IF_CRTL_RGB_LVDS_DCLK_POL_SHIT 3
105122
106123 #define HDMI_EDP0_DCLK_DIV_SHIFT 16
107124 #define HDMI_EDP0_PIXCLK_DIV_SHIFT 18
....@@ -118,6 +135,8 @@
118135 #define GAMMA_AHB_WRITE_SEL_MASK 0x3
119136 #define GAMMA_AHB_WRITE_SEL_SHIFT 12
120137 #define PORT_MERGE_EN_SHIFT 16
138
+#define ESMART_LB_MODE_SEL_MASK 0x3
139
+#define ESMART_LB_MODE_SEL_SHIFT 26
121140
122141 #define RK3568_SYS_PD_CTRL 0x034
123142 #define RK3568_VP0_LINE_FLAG 0x70
....@@ -145,6 +164,11 @@
145164 #define RK3588_DSC_8K_PD_EN_SHIFT 5
146165 #define RK3588_DSC_4K_PD_EN_SHIFT 6
147166 #define RK3588_ESMART_PD_EN_SHIFT 7
167
+
168
+#define RK3588_SYS_VAR_FREQ_CTRL 0x038
169
+#define RK3588_VP0_LINE_FLAG_OR_EN_SHIFT 20
170
+#define RK3588_VP0_DSP_HOLD_OR_EN_SHIFT 24
171
+#define RK3588_VP0_ALMOST_FULL_OR_EN_SHIFT 28
148172
149173 #define RK3568_SYS_STATUS0 0x60
150174 #define RK3588_CLUSTER0_PD_STATUS_SHIFT 8
....@@ -212,10 +236,27 @@
212236 #define RK3588_DSC_8K_STATUS 0x220
213237
214238 /* Overlay registers definition */
239
+#define RK3528_OVL_SYS 0x500
240
+#define RK3528_OVL_SYS_PORT_SEL_IMD 0x504
241
+#define RK3528_OVL_SYS_GATING_EN_IMD 0x508
242
+#define RK3528_OVL_SYS_CLUSTER0_CTRL 0x510
243
+#define RK3528_OVL_SYS_ESMART0_CTRL 0x520
244
+#define ESMART_DLY_NUM_MASK 0xff
245
+#define ESMART_DLY_NUM_SHIFT 0
246
+#define RK3528_OVL_SYS_ESMART1_CTRL 0x524
247
+#define RK3528_OVL_SYS_ESMART2_CTRL 0x528
248
+#define RK3528_OVL_SYS_ESMART3_CTRL 0x52C
249
+#define RK3528_CLUSTER0_MIX_SRC_COLOR_CTRL 0x530
250
+#define RK3528_CLUSTER0_MIX_DST_COLOR_CTRL 0x534
251
+#define RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x538
252
+#define RK3528_CLUSTER0_MIX_DST_ALPHA_CTRL 0x53c
253
+
254
+#define RK3528_OVL_PORT0_CTRL 0x600
215255 #define RK3568_OVL_CTRL 0x600
216256 #define OVL_MODE_SEL_MASK 0x1
217257 #define OVL_MODE_SEL_SHIFT 0
218258 #define OVL_PORT_MUX_REG_DONE_IMD_SHIFT 28
259
+#define RK3528_OVL_PORT0_LAYER_SEL 0x604
219260 #define RK3568_OVL_LAYER_SEL 0x604
220261 #define LAYER_SEL_MASK 0xf
221262
....@@ -229,10 +270,27 @@
229270 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614
230271 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618
231272 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C
273
+#define RK3528_OVL_PORT0_MIX0_SRC_COLOR_CTRL 0x620
274
+#define RK3528_OVL_PORT0_MIX0_DST_COLOR_CTRL 0x624
275
+#define RK3528_OVL_PORT0_MIX0_SRC_ALPHA_CTRL 0x628
276
+#define RK3528_OVL_PORT0_MIX0_DST_ALPHA_CTRL 0x62C
277
+#define RK3528_OVL_PORT0_MIX1_SRC_COLOR_CTRL 0x630
278
+#define RK3528_OVL_PORT0_MIX1_DST_COLOR_CTRL 0x634
279
+#define RK3528_OVL_PORT0_MIX1_SRC_ALPHA_CTRL 0x638
280
+#define RK3528_OVL_PORT0_MIX1_DST_ALPHA_CTRL 0x63C
281
+#define RK3528_OVL_PORT0_MIX2_SRC_COLOR_CTRL 0x640
282
+#define RK3528_OVL_PORT0_MIX2_DST_COLOR_CTRL 0x644
283
+#define RK3528_OVL_PORT0_MIX2_SRC_ALPHA_CTRL 0x648
284
+#define RK3528_OVL_PORT0_MIX2_DST_ALPHA_CTRL 0x64C
232285 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650
233286 #define RK3568_MIX0_DST_COLOR_CTRL 0x654
234287 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658
235288 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C
289
+#define RK3528_HDR_SRC_COLOR_CTRL 0x660
290
+#define RK3528_HDR_DST_COLOR_CTRL 0x664
291
+#define RK3528_HDR_SRC_ALPHA_CTRL 0x668
292
+#define RK3528_HDR_DST_ALPHA_CTRL 0x66C
293
+#define RK3528_OVL_PORT0_BG_MIX_CTRL 0x670
236294 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0
237295 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4
238296 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8
....@@ -244,6 +302,22 @@
244302 #define RK3568_VP2_BG_MIX_CTRL 0x6E8
245303 #define RK3568_CLUSTER_DLY_NUM 0x6F0
246304 #define RK3568_SMART_DLY_NUM 0x6F8
305
+
306
+#define RK3528_OVL_PORT1_CTRL 0x700
307
+#define RK3528_OVL_PORT1_LAYER_SEL 0x704
308
+#define RK3528_OVL_PORT1_MIX0_SRC_COLOR_CTRL 0x720
309
+#define RK3528_OVL_PORT1_MIX0_DST_COLOR_CTRL 0x724
310
+#define RK3528_OVL_PORT1_MIX0_SRC_ALPHA_CTRL 0x728
311
+#define RK3528_OVL_PORT1_MIX0_DST_ALPHA_CTRL 0x72C
312
+#define RK3528_OVL_PORT1_MIX1_SRC_COLOR_CTRL 0x730
313
+#define RK3528_OVL_PORT1_MIX1_DST_COLOR_CTRL 0x734
314
+#define RK3528_OVL_PORT1_MIX1_SRC_ALPHA_CTRL 0x738
315
+#define RK3528_OVL_PORT1_MIX1_DST_ALPHA_CTRL 0x73C
316
+#define RK3528_OVL_PORT1_MIX2_SRC_COLOR_CTRL 0x740
317
+#define RK3528_OVL_PORT1_MIX2_DST_COLOR_CTRL 0x744
318
+#define RK3528_OVL_PORT1_MIX2_SRC_ALPHA_CTRL 0x748
319
+#define RK3528_OVL_PORT1_MIX2_DST_ALPHA_CTRL 0x74C
320
+#define RK3528_OVL_PORT1_BG_MIX_CTRL 0x770
247321
248322 /* Video Port registers definition */
249323 #define RK3568_VP0_DSP_CTRL 0xC00
....@@ -263,6 +337,7 @@
263337 #define POST_DSP_OUT_R2Y_SHIFT 15
264338 #define PRE_DITHER_DOWN_EN_SHIFT 16
265339 #define DITHER_DOWN_EN_SHIFT 17
340
+#define DITHER_DOWN_MODE_SHIFT 20
266341 #define GAMMA_UPDATE_EN_SHIFT 22
267342 #define DSP_LUT_EN_SHIFT 28
268343
....@@ -279,6 +354,9 @@
279354
280355
281356 #define RK3568_VP0_COLOR_BAR_CTRL 0xC08
357
+
358
+#define RK3568_VP0_DCLK_SEL 0xC0C
359
+
282360 #define RK3568_VP0_3D_LUT_CTRL 0xC10
283361 #define VP0_3D_LUT_EN_SHIFT 0
284362 #define VP0_3D_LUT_UPDATE_SHIFT 2
....@@ -333,6 +411,50 @@
333411 #define BCSH_EN_SHIFT 31
334412 #define BCSH_EN_MASK 1
335413
414
+#define RK3528_VP0_ACM_CTRL 0xCD0
415
+#define POST_CSC_COE00_MASK 0xFFFF
416
+#define POST_CSC_COE00_SHIFT 16
417
+#define POST_R2Y_MODE_MASK 0x7
418
+#define POST_R2Y_MODE_SHIFT 8
419
+#define POST_CSC_MODE_MASK 0x7
420
+#define POST_CSC_MODE_SHIFT 3
421
+#define POST_R2Y_EN_MASK 0x1
422
+#define POST_R2Y_EN_SHIFT 2
423
+#define POST_CSC_EN_MASK 0x1
424
+#define POST_CSC_EN_SHIFT 1
425
+#define POST_ACM_BYPASS_EN_MASK 0x1
426
+#define POST_ACM_BYPASS_EN_SHIFT 0
427
+#define RK3528_VP0_CSC_COE01_02 0xCD4
428
+#define RK3528_VP0_CSC_COE10_11 0xCD8
429
+#define RK3528_VP0_CSC_COE12_20 0xCDC
430
+#define RK3528_VP0_CSC_COE21_22 0xCE0
431
+#define RK3528_VP0_CSC_OFFSET0 0xCE4
432
+#define RK3528_VP0_CSC_OFFSET1 0xCE8
433
+#define RK3528_VP0_CSC_OFFSET2 0xCEC
434
+
435
+#define RK3562_VP0_MCU_CTRL 0xCF8
436
+#define MCU_TYPE_SHIFT 31
437
+#define MCU_BYPASS_SHIFT 30
438
+#define MCU_RS_SHIFT 29
439
+#define MCU_FRAME_ST_SHIFT 28
440
+#define MCU_HOLD_MODE_SHIFT 27
441
+#define MCU_CLK_SEL_SHIFT 26
442
+#define MCU_CLK_SEL_MASK 0x1
443
+#define MCU_RW_PEND_SHIFT 20
444
+#define MCU_RW_PEND_MASK 0x3F
445
+#define MCU_RW_PST_SHIFT 16
446
+#define MCU_RW_PST_MASK 0xF
447
+#define MCU_CS_PEND_SHIFT 10
448
+#define MCU_CS_PEND_MASK 0x3F
449
+#define MCU_CS_PST_SHIFT 6
450
+#define MCU_CS_PST_MASK 0xF
451
+#define MCU_PIX_TOTAL_SHIFT 0
452
+#define MCU_PIX_TOTAL_MASK 0x3F
453
+
454
+#define RK3562_VP0_MCU_RW_BYPASS_PORT 0xCFC
455
+#define MCU_WRITE_DATA_BYPASS_SHIFT 0
456
+#define MCU_WRITE_DATA_BYPASS_MASK 0xFFFFFFFF
457
+
336458 #define RK3568_VP1_DSP_CTRL 0xD00
337459 #define RK3568_VP1_MIPI_CTRL 0xD04
338460 #define RK3568_VP1_COLOR_BAR_CTRL 0xD08
....@@ -374,9 +496,20 @@
374496 #define CLUSTER_YUV2RGB_EN_SHIFT 8
375497 #define CLUSTER_RGB2YUV_EN_SHIFT 9
376498 #define CLUSTER_CSC_MODE_SHIFT 10
377
-#define CLUSTER_YRGB_XSCL_MODE_SHIFT 12
378
-#define CLUSTER_YRGB_YSCL_MODE_SHIFT 14
499
+#define CLUSTER_DITHER_UP_EN_SHIFT 18
379500 #define RK3568_CLUSTER0_WIN0_CTRL1 0x1004
501
+#define RK3568_CLUSTER_YRGB_XSCL_MODE_SHIFT 12
502
+#define RK3568_CLUSTER_YRGB_YSCL_MODE_SHIFT 14
503
+#define RK3528_CLUSTER_YRGB_YSCL_MODE_SHIFT 14
504
+#define AVG2_MASK 0x1
505
+#define CLUSTER_AVG2_SHIFT 18
506
+#define AVG4_MASK 0x1
507
+#define CLUSTER_AVG4_SHIFT 19
508
+#define RK3528_CLUSTER_YRGB_XSCL_MODE_SHIFT 22
509
+#define CLUSTER_XGT_EN_SHIFT 24
510
+#define XGT_MODE_MASK 0x3
511
+#define CLUSTER_XGT_MODE_SHIFT 25
512
+#define CLUSTER_XAVG_EN_SHIFT 27
380513 #define CLUSTER_YRGB_GT2_SHIFT 28
381514 #define CLUSTER_YRGB_GT4_SHIFT 29
382515 #define RK3568_CLUSTER0_WIN0_CTRL2 0x1008
....@@ -399,6 +532,7 @@
399532 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064
400533 #define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068
401534 #define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C
535
+#define CLUSTER_AFBCD_HALF_BLOCK_SHIFT 7
402536
403537 #define RK3568_CLUSTER0_WIN1_CTRL0 0x1080
404538 #define RK3568_CLUSTER0_WIN1_CTRL1 0x1084
....@@ -463,6 +597,8 @@
463597 #define RGB2YUV_EN_SHIFT 1
464598 #define CSC_MODE_SHIFT 2
465599 #define CSC_MODE_MASK 0x3
600
+#define ESMART_LB_SELECT_SHIFT 12
601
+#define ESMART_LB_SELECT_MASK 0x3
466602
467603 #define RK3568_ESMART0_CTRL1 0x1804
468604 #define ESMART_AXI_YRGB_ID_MASK 0x1f
....@@ -476,10 +612,14 @@
476612 #define ESMART_AXI_ID_SHIFT 1
477613
478614 #define RK3568_ESMART0_REGION0_CTRL 0x1810
479
-#define REGION0_RB_SWAP_SHIFT 14
480615 #define WIN_EN_SHIFT 0
481616 #define WIN_FORMAT_MASK 0x1f
482617 #define WIN_FORMAT_SHIFT 1
618
+#define REGION0_DITHER_UP_EN_SHIFT 12
619
+#define REGION0_RB_SWAP_SHIFT 14
620
+#define ESMART_XAVG_EN_SHIFT 20
621
+#define ESMART_XGT_EN_SHIFT 21
622
+#define ESMART_XGT_MODE_SHIFT 22
483623
484624 #define RK3568_ESMART0_REGION0_YRGB_MST 0x1814
485625 #define RK3568_ESMART0_REGION0_CBR_MST 0x1818
....@@ -680,6 +820,13 @@
680820 #define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8
681821 #define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC
682822
823
+/* HDR register definition */
824
+#define RK3568_HDR_LUT_CTRL 0x2000
825
+
826
+#define RK3588_VP3_DSP_CTRL 0xF00
827
+#define RK3588_CLUSTER2_WIN0_CTRL0 0x1400
828
+#define RK3588_CLUSTER3_WIN0_CTRL0 0x1600
829
+
683830 /* DSC 8K/4K register definition */
684831 #define RK3588_DSC_8K_PPS0_3 0x4000
685832 #define RK3588_DSC_8K_CTRL0 0x40A0
....@@ -690,10 +837,14 @@
690837 #define DSC_MER_SHIFT 5
691838 #define DSC_EPB_SHIFT 6
692839 #define DSC_EPL_SHIFT 7
840
+#define DSC_NSLC_MASK 0x7
693841 #define DSC_NSLC_SHIFT 16
694842 #define DSC_SBO_SHIFT 28
695843 #define DSC_IFEP_SHIFT 29
696844 #define DSC_PPS_UPD_SHIFT 31
845
+#define DSC_CTRL0_DEF_CON ((1 << DSC_EN_SHIFT) | (1 << DSC_RBIT_SHIFT) | (0 << DSC_RBYT_SHIFT) | \
846
+ (1 << DSC_FLAL_SHIFT) | (1 << DSC_MER_SHIFT) | (0 << DSC_EPB_SHIFT) | \
847
+ (1 << DSC_EPL_SHIFT) | (1 << DSC_SBO_SHIFT))
697848
698849 #define RK3588_DSC_8K_CTRL1 0x40A4
699850 #define RK3588_DSC_8K_STS0 0x40A8
....@@ -705,8 +856,24 @@
705856 #define RK3588_DSC_4K_STS0 0x41A8
706857 #define RK3588_DSC_4K_ERS 0x41C4
707858
859
+/* RK3528 HDR register definition */
860
+#define RK3528_HDR_LUT_CTRL 0x2000
861
+
862
+/* RK3528 ACM register definition */
863
+#define RK3528_ACM_CTRL 0x6400
864
+#define RK3528_ACM_DELTA_RANGE 0x6404
865
+#define RK3528_ACM_FETCH_START 0x6408
866
+#define RK3528_ACM_FETCH_DONE 0x6420
867
+#define RK3528_ACM_YHS_DEL_HY_SEG0 0x6500
868
+#define RK3528_ACM_YHS_DEL_HY_SEG152 0x6760
869
+#define RK3528_ACM_YHS_DEL_HS_SEG0 0x6764
870
+#define RK3528_ACM_YHS_DEL_HS_SEG220 0x6ad4
871
+#define RK3528_ACM_YHS_DEL_HGAIN_SEG0 0x6ad8
872
+#define RK3528_ACM_YHS_DEL_HGAIN_SEG64 0x6bd8
873
+
708874 #define RK3568_MAX_REG 0x1ED0
709875
876
+#define RK3562_GRF_IOC_VO_IO_CON 0x10500
710877 #define RK3568_GRF_VO_CON1 0x0364
711878 #define GRF_BT656_CLK_INV_SHIFT 1
712879 #define GRF_BT1120_CLK_INV_SHIFT 2
....@@ -771,11 +938,52 @@
771938
772939 #define VOP2_PLANE_NO_SCALING BIT(16)
773940
774
-enum vop2_csc_format {
941
+#define VOP_FEATURE_OUTPUT_10BIT BIT(0)
942
+#define VOP_FEATURE_AFBDC BIT(1)
943
+#define VOP_FEATURE_ALPHA_SCALE BIT(2)
944
+#define VOP_FEATURE_HDR10 BIT(3)
945
+#define VOP_FEATURE_NEXT_HDR BIT(4)
946
+/* a feature to splice two windows and two vps to support resolution > 4096 */
947
+#define VOP_FEATURE_SPLICE BIT(5)
948
+#define VOP_FEATURE_OVERSCAN BIT(6)
949
+#define VOP_FEATURE_VIVID_HDR BIT(7)
950
+#define VOP_FEATURE_POST_ACM BIT(8)
951
+#define VOP_FEATURE_POST_CSC BIT(9)
952
+
953
+#define WIN_FEATURE_HDR2SDR BIT(0)
954
+#define WIN_FEATURE_SDR2HDR BIT(1)
955
+#define WIN_FEATURE_PRE_OVERLAY BIT(2)
956
+#define WIN_FEATURE_AFBDC BIT(3)
957
+#define WIN_FEATURE_CLUSTER_MAIN BIT(4)
958
+#define WIN_FEATURE_CLUSTER_SUB BIT(5)
959
+/* a mirror win can only get fb address
960
+ * from source win:
961
+ * Cluster1---->Cluster0
962
+ * Esmart1 ---->Esmart0
963
+ * Smart1 ---->Smart0
964
+ * This is a feather on rk3566
965
+ */
966
+#define WIN_FEATURE_MIRROR BIT(6)
967
+#define WIN_FEATURE_MULTI_AREA BIT(7)
968
+#define WIN_FEATURE_Y2R_13BIT_DEPTH BIT(8)
969
+
970
+#define V4L2_COLORSPACE_BT709F 0xfe
971
+#define V4L2_COLORSPACE_BT2020F 0xff
972
+
973
+enum vop_csc_format {
775974 CSC_BT601L,
776975 CSC_BT709L,
777976 CSC_BT601F,
778977 CSC_BT2020,
978
+ CSC_BT709L_13BIT,
979
+ CSC_BT709F_13BIT,
980
+ CSC_BT2020L_13BIT,
981
+ CSC_BT2020F_13BIT,
982
+};
983
+
984
+enum vop_csc_bit_depth {
985
+ CSC_10BIT_DEPTH,
986
+ CSC_13BIT_DEPTH,
779987 };
780988
781989 enum vop2_pol {
....@@ -861,6 +1069,19 @@
8611069 VOP_DSC_IF_MIPI_VIDEO_MODE = 3,
8621070 };
8631071
1072
+enum vop3_pre_scale_down_mode {
1073
+ VOP3_PRE_SCALE_UNSPPORT,
1074
+ VOP3_PRE_SCALE_DOWN_GT,
1075
+ VOP3_PRE_SCALE_DOWN_AVG,
1076
+};
1077
+
1078
+enum vop3_esmart_lb_mode {
1079
+ VOP3_ESMART_8K_MODE,
1080
+ VOP3_ESMART_4K_4K_MODE,
1081
+ VOP3_ESMART_4K_2K_2K_MODE,
1082
+ VOP3_ESMART_2K_2K_2K_2K_MODE,
1083
+};
1084
+
8641085 struct vop2_layer {
8651086 u8 id;
8661087 /**
....@@ -886,12 +1107,19 @@
8861107 u8 phys_id;
8871108 enum vop2_layer_type type;
8881109 u8 win_sel_port_offset;
889
- u8 layer_sel_win_id;
1110
+ u8 layer_sel_win_id[VOP2_VP_MAX];
8901111 u8 axi_id;
8911112 u8 axi_uv_id;
8921113 u8 axi_yrgb_id;
8931114 u8 splice_win_id;
8941115 u8 pd_id;
1116
+ u8 hsu_filter_mode;
1117
+ u8 hsd_filter_mode;
1118
+ u8 vsu_filter_mode;
1119
+ u8 vsd_filter_mode;
1120
+ u8 hsd_pre_filter_mode;
1121
+ u8 vsd_pre_filter_mode;
1122
+ u8 scale_engine_num;
8951123 u32 reg_offset;
8961124 u32 max_upscale_factor;
8971125 u32 max_downscale_factor;
....@@ -901,6 +1129,9 @@
9011129 struct vop2_vp_data {
9021130 u32 feature;
9031131 u8 pre_scan_max_dly;
1132
+ u8 layer_mix_dly;
1133
+ u8 hdr_mix_dly;
1134
+ u8 win_dly;
9041135 u8 splice_vp_id;
9051136 struct vop_rect max_output;
9061137 u32 max_dclk;
....@@ -936,8 +1167,18 @@
9361167 char dsc_error_info[50];
9371168 };
9381169
1170
+struct vop2_dump_regs {
1171
+ u32 offset;
1172
+ const char *name;
1173
+ u32 state_base;
1174
+ u32 state_mask;
1175
+ u32 state_shift;
1176
+ bool enable_state;
1177
+};
1178
+
9391179 struct vop2_data {
9401180 u32 version;
1181
+ u32 esmart_lb_mode;
9411182 struct vop2_vp_data *vp_data;
9421183 struct vop2_win_data *win_data;
9431184 struct vop2_vp_plane_mask *plane_mask;
....@@ -946,6 +1187,8 @@
9461187 struct vop2_dsc_data *dsc;
9471188 struct dsc_error_info *dsc_error_ecw;
9481189 struct dsc_error_info *dsc_error_buffer_flow;
1190
+ struct vop2_dump_regs *dump_regs;
1191
+ u8 *vp_primary_plane_order;
9491192 u8 nr_vps;
9501193 u8 nr_layers;
9511194 u8 nr_mixers;
....@@ -955,6 +1198,7 @@
9551198 u8 nr_dsc_ecw;
9561199 u8 nr_dsc_buffer_flow;
9571200 u32 reg_len;
1201
+ u32 dump_regs_size;
9581202 };
9591203
9601204 struct vop2 {
....@@ -966,12 +1210,22 @@
9661210 void *sys_pmu;
9671211 u32 reg_len;
9681212 u32 version;
1213
+ u32 esmart_lb_mode;
9691214 bool global_init;
9701215 const struct vop2_data *data;
9711216 struct vop2_vp_plane_mask vp_plane_mask[VOP2_VP_MAX];
9721217 };
9731218
9741219 static struct vop2 *rockchip_vop2;
1220
+
1221
+static inline bool is_vop3(struct vop2 *vop2)
1222
+{
1223
+ if (vop2->version == VOP_VERSION_RK3568 || vop2->version == VOP_VERSION_RK3588)
1224
+ return false;
1225
+ else
1226
+ return true;
1227
+}
1228
+
9751229 /*
9761230 * bli_sd_factor = (src - 1) / (dst - 1) << 12;
9771231 * avg_sd_factor:
....@@ -979,8 +1233,8 @@
9791233 * bic_su_factor:
9801234 * = (src - 1) / (dst - 1) << 16;
9811235 *
982
- * gt2 enable: dst get one line from two line of the src
983
- * gt4 enable: dst get one line from four line of the src.
1236
+ * ygt2 enable: dst get one line from two line of the src
1237
+ * ygt4 enable: dst get one line from four line of the src.
9841238 *
9851239 */
9861240 #define VOP2_BILI_SCL_DN(src, dst) (((src - 1) << 12) / (dst - 1))
....@@ -989,6 +1243,8 @@
9891243 #define VOP2_BILI_SCL_FAC_CHECK(src, dst, fac) \
9901244 (fac * (dst - 1) >> 12 < (src - 1))
9911245 #define VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac) \
1246
+ (fac * (dst - 1) >> 16 < (src - 1))
1247
+#define VOP3_COMMON_HOR_SCL_FAC_CHECK(src, dst, fac) \
9921248 (fac * (dst - 1) >> 16 < (src - 1))
9931249
9941250 static uint16_t vop2_scale_factor(enum scale_mode mode,
....@@ -1030,6 +1286,51 @@
10301286 return fac;
10311287 }
10321288
1289
+static bool vop3_scale_up_fac_check(uint32_t src, uint32_t dst, uint32_t fac, bool is_hor)
1290
+{
1291
+ if (is_hor)
1292
+ return VOP3_COMMON_HOR_SCL_FAC_CHECK(src, dst, fac);
1293
+ return VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac);
1294
+}
1295
+
1296
+static uint16_t vop3_scale_factor(enum scale_mode mode,
1297
+ uint32_t src, uint32_t dst, bool is_hor)
1298
+{
1299
+ uint32_t fac = 0;
1300
+ int i = 0;
1301
+
1302
+ if (mode == SCALE_NONE)
1303
+ return 0;
1304
+
1305
+ /*
1306
+ * A workaround to avoid zero div.
1307
+ */
1308
+ if ((dst == 1) || (src == 1)) {
1309
+ dst = dst + 1;
1310
+ src = src + 1;
1311
+ }
1312
+
1313
+ if (mode == SCALE_DOWN) {
1314
+ fac = VOP2_BILI_SCL_DN(src, dst);
1315
+ for (i = 0; i < 100; i++) {
1316
+ if (VOP2_BILI_SCL_FAC_CHECK(src, dst, fac))
1317
+ break;
1318
+ fac -= 1;
1319
+ printf("down fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac);
1320
+ }
1321
+ } else {
1322
+ fac = VOP2_COMMON_SCL(src, dst);
1323
+ for (i = 0; i < 100; i++) {
1324
+ if (vop3_scale_up_fac_check(src, dst, fac, is_hor))
1325
+ break;
1326
+ fac -= 1;
1327
+ printf("up fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac);
1328
+ }
1329
+ }
1330
+
1331
+ return fac;
1332
+}
1333
+
10331334 static inline enum scale_mode scl_get_scl_mode(int src, int dst)
10341335 {
10351336 if (src < dst)
....@@ -1040,19 +1341,6 @@
10401341 return SCALE_NONE;
10411342 }
10421343
1043
-static u8 rk3588_vop2_vp_primary_plane_order[VOP2_VP_MAX] = {
1044
- ROCKCHIP_VOP2_ESMART0,
1045
- ROCKCHIP_VOP2_ESMART1,
1046
- ROCKCHIP_VOP2_ESMART2,
1047
- ROCKCHIP_VOP2_ESMART3,
1048
-};
1049
-
1050
-static u8 rk3568_vop2_vp_primary_plane_order[VOP2_VP_MAX] = {
1051
- ROCKCHIP_VOP2_SMART0,
1052
- ROCKCHIP_VOP2_SMART1,
1053
- ROCKCHIP_VOP2_ESMART1,
1054
-};
1055
-
10561344 static inline int interpolate(int x1, int y1, int x2, int y2, int x)
10571345 {
10581346 return y1 + (y2 - y1) * (x - x1) / (x2 - x1);
....@@ -1061,23 +1349,13 @@
10611349 static int vop2_get_primary_plane(struct vop2 *vop2, u32 plane_mask)
10621350 {
10631351 int i = 0;
1064
- u8 *vop2_vp_primary_plane_order;
1065
- u8 default_primary_plane;
10661352
1067
- if (vop2->version == VOP_VERSION_RK3588) {
1068
- vop2_vp_primary_plane_order = rk3588_vop2_vp_primary_plane_order;
1069
- default_primary_plane = ROCKCHIP_VOP2_ESMART0;
1070
- } else {
1071
- vop2_vp_primary_plane_order = rk3568_vop2_vp_primary_plane_order;
1072
- default_primary_plane = ROCKCHIP_VOP2_SMART0;
1353
+ for (i = 0; i < vop2->data->nr_layers; i++) {
1354
+ if (plane_mask & BIT(vop2->data->vp_primary_plane_order[i]))
1355
+ return vop2->data->vp_primary_plane_order[i];
10731356 }
10741357
1075
- for (i = 0; i < vop2->data->nr_vps; i++) {
1076
- if (plane_mask & BIT(vop2_vp_primary_plane_order[i]))
1077
- return vop2_vp_primary_plane_order[i];
1078
- }
1079
-
1080
- return default_primary_plane;
1358
+ return vop2->data->vp_primary_plane_order[0];
10811359 }
10821360
10831361 static inline u16 scl_cal_scale(int src, int dst, int shift)
....@@ -1210,6 +1488,7 @@
12101488 switch (bus_format) {
12111489 case MEDIA_BUS_FMT_YUV8_1X24:
12121490 case MEDIA_BUS_FMT_YUV10_1X30:
1491
+ case MEDIA_BUS_FMT_YUYV10_1X20:
12131492 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
12141493 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
12151494 case MEDIA_BUS_FMT_YUYV8_2X8:
....@@ -1226,7 +1505,7 @@
12261505 }
12271506 }
12281507
1229
-static int vop2_convert_csc_mode(int csc_mode)
1508
+static int vop2_convert_csc_mode(int csc_mode, int bit_depth)
12301509 {
12311510 switch (csc_mode) {
12321511 case V4L2_COLORSPACE_SMPTE170M:
....@@ -1236,11 +1515,31 @@
12361515 case V4L2_COLORSPACE_REC709:
12371516 case V4L2_COLORSPACE_SMPTE240M:
12381517 case V4L2_COLORSPACE_DEFAULT:
1239
- return CSC_BT709L;
1518
+ if (bit_depth == CSC_13BIT_DEPTH)
1519
+ return CSC_BT709L_13BIT;
1520
+ else
1521
+ return CSC_BT709L;
12401522 case V4L2_COLORSPACE_JPEG:
12411523 return CSC_BT601F;
12421524 case V4L2_COLORSPACE_BT2020:
1243
- return CSC_BT2020;
1525
+ if (bit_depth == CSC_13BIT_DEPTH)
1526
+ return CSC_BT2020L_13BIT;
1527
+ else
1528
+ return CSC_BT2020;
1529
+ case V4L2_COLORSPACE_BT709F:
1530
+ if (bit_depth == CSC_10BIT_DEPTH) {
1531
+ printf("WARN: Unsupported bt709f at 10bit csc depth, use bt601f instead\n");
1532
+ return CSC_BT601F;
1533
+ } else {
1534
+ return CSC_BT709F_13BIT;
1535
+ }
1536
+ case V4L2_COLORSPACE_BT2020F:
1537
+ if (bit_depth == CSC_10BIT_DEPTH) {
1538
+ printf("WARN: Unsupported bt2020f at 10bit csc depth, use bt601f instead\n");
1539
+ return CSC_BT601F;
1540
+ } else {
1541
+ return CSC_BT2020F_13BIT;
1542
+ }
12441543 default:
12451544 return CSC_BT709L;
12461545 }
....@@ -1265,6 +1564,19 @@
12651564 bus_format == MEDIA_BUS_FMT_YUV10_1X30) &&
12661565 (output_mode == ROCKCHIP_OUT_MODE_AAAA ||
12671566 output_mode == ROCKCHIP_OUT_MODE_P888)))
1567
+ return true;
1568
+ else
1569
+ return false;
1570
+}
1571
+
1572
+static bool is_rb_swap(u32 bus_format, u32 output_mode)
1573
+{
1574
+ /*
1575
+ * The default component order of serial rgb3x8 formats
1576
+ * is BGR. So it is needed to enable RB swap.
1577
+ */
1578
+ if (bus_format == MEDIA_BUS_FMT_SRGB888_3X8 ||
1579
+ bus_format == MEDIA_BUS_FMT_SRGB888_DUMMY_4X8)
12681580 return true;
12691581 else
12701582 return false;
....@@ -1533,7 +1845,7 @@
15331845 cstate->post_y2r_en = 1;
15341846 }
15351847
1536
- cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_space);
1848
+ cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_space, CSC_10BIT_DEPTH);
15371849
15381850 if (cstate->feature & VOP_FEATURE_OUTPUT_10BIT)
15391851 brightness = interpolate(0, -128, 100, 127,
....@@ -1578,7 +1890,7 @@
15781890 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
15791891
15801892 bg_ovl_dly = cstate->crtc->vps[crtc_id].bg_ovl_dly;
1581
- bg_dly = vop2->data->vp_data[crtc_id].pre_scan_max_dly;
1893
+ bg_dly = vop2->data->vp_data[crtc_id].pre_scan_max_dly;
15821894 bg_dly -= bg_ovl_dly;
15831895
15841896 if (cstate->splice_mode)
....@@ -1590,6 +1902,33 @@
15901902 hsync_len = 8;
15911903 pre_scan_dly = (pre_scan_dly << 16) | hsync_len;
15921904 vop2_mask_write(vop2, RK3568_VP0_BG_MIX_CTRL + crtc_id * 4,
1905
+ BG_MIX_CTRL_MASK, BG_MIX_CTRL_SHIFT, bg_dly, false);
1906
+ vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly);
1907
+}
1908
+
1909
+static void vop3_setup_pipe_dly(struct display_state *state, struct vop2 *vop2, int crtc_id)
1910
+{
1911
+ struct connector_state *conn_state = &state->conn_state;
1912
+ struct drm_display_mode *mode = &conn_state->mode;
1913
+ struct crtc_state *cstate = &state->crtc_state;
1914
+ struct vop2_win_data *win_data;
1915
+ u32 bg_dly, pre_scan_dly;
1916
+ u16 hdisplay = mode->crtc_hdisplay;
1917
+ u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
1918
+ u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id;
1919
+ u8 win_id;
1920
+
1921
+ win_data = vop2_find_win_by_phys_id(vop2, primary_plane_id);
1922
+ win_id = atoi(&win_data->name[strlen(win_data->name) - 1]);
1923
+ vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART0_CTRL + win_id * 4,
1924
+ ESMART_DLY_NUM_MASK, ESMART_DLY_NUM_SHIFT, 0, false);
1925
+
1926
+ bg_dly = vop2->data->vp_data[crtc_id].win_dly +
1927
+ vop2->data->vp_data[crtc_id].layer_mix_dly +
1928
+ vop2->data->vp_data[crtc_id].hdr_mix_dly;
1929
+ pre_scan_dly = bg_dly + (hdisplay >> 1) - 1;
1930
+ pre_scan_dly = (pre_scan_dly << 16) | hsync_len;
1931
+ vop2_mask_write(vop2, RK3528_OVL_PORT0_BG_MIX_CTRL + crtc_id * 0x100,
15931932 BG_MIX_CTRL_MASK, BG_MIX_CTRL_SHIFT, bg_dly, false);
15941933 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly);
15951934 }
....@@ -1644,9 +1983,176 @@
16441983 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val);
16451984 }
16461985
1647
- vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id);
1648
- if (cstate->splice_mode)
1649
- vop2_setup_dly_for_vp(state, vop2, cstate->splice_crtc_id);
1986
+ if (is_vop3(vop2)) {
1987
+ vop3_setup_pipe_dly(state, vop2, cstate->crtc_id);
1988
+ } else {
1989
+ vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id);
1990
+ if (cstate->splice_mode)
1991
+ vop2_setup_dly_for_vp(state, vop2, cstate->splice_crtc_id);
1992
+ }
1993
+}
1994
+
1995
+static void vop3_post_acm_config(struct display_state *state, struct vop2 *vop2)
1996
+{
1997
+ struct connector_state *conn_state = &state->conn_state;
1998
+ struct crtc_state *cstate = &state->crtc_state;
1999
+ struct acm_data *acm = &conn_state->disp_info->acm_data;
2000
+ struct drm_display_mode *mode = &conn_state->mode;
2001
+ u32 vp_offset = (cstate->crtc_id * 0x100);
2002
+ s16 *lut_y;
2003
+ s16 *lut_h;
2004
+ s16 *lut_s;
2005
+ u32 value;
2006
+ int i;
2007
+
2008
+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
2009
+ POST_ACM_BYPASS_EN_MASK, POST_ACM_BYPASS_EN_SHIFT, 0, false);
2010
+ if (!acm->acm_enable) {
2011
+ writel(0, vop2->regs + RK3528_ACM_CTRL);
2012
+ return;
2013
+ }
2014
+
2015
+ printf("post acm enable\n");
2016
+
2017
+ writel(1, vop2->regs + RK3528_ACM_FETCH_START);
2018
+
2019
+ value = (acm->acm_enable & 0x1) + ((mode->hdisplay & 0xfff) << 8) +
2020
+ ((mode->vdisplay & 0xfff) << 20);
2021
+ writel(value, vop2->regs + RK3528_ACM_CTRL);
2022
+
2023
+ value = (acm->y_gain & 0x3ff) + ((acm->h_gain << 10) & 0xffc00) +
2024
+ ((acm->s_gain << 20) & 0x3ff00000);
2025
+ writel(value, vop2->regs + RK3528_ACM_DELTA_RANGE);
2026
+
2027
+ lut_y = &acm->gain_lut_hy[0];
2028
+ lut_h = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH];
2029
+ lut_s = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH * 2];
2030
+ for (i = 0; i < ACM_GAIN_LUT_HY_LENGTH; i++) {
2031
+ value = (lut_y[i] & 0xff) + ((lut_h[i] << 8) & 0xff00) +
2032
+ ((lut_s[i] << 16) & 0xff0000);
2033
+ writel(value, vop2->regs + RK3528_ACM_YHS_DEL_HY_SEG0 + (i << 2));
2034
+ }
2035
+
2036
+ lut_y = &acm->gain_lut_hs[0];
2037
+ lut_h = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH];
2038
+ lut_s = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH * 2];
2039
+ for (i = 0; i < ACM_GAIN_LUT_HS_LENGTH; i++) {
2040
+ value = (lut_y[i] & 0xff) + ((lut_h[i] << 8) & 0xff00) +
2041
+ ((lut_s[i] << 16) & 0xff0000);
2042
+ writel(value, vop2->regs + RK3528_ACM_YHS_DEL_HS_SEG0 + (i << 2));
2043
+ }
2044
+
2045
+ lut_y = &acm->delta_lut_h[0];
2046
+ lut_h = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH];
2047
+ lut_s = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH * 2];
2048
+ for (i = 0; i < ACM_DELTA_LUT_H_LENGTH; i++) {
2049
+ value = (lut_y[i] & 0x3ff) + ((lut_h[i] << 12) & 0xff000) +
2050
+ ((lut_s[i] << 20) & 0x3ff00000);
2051
+ writel(value, vop2->regs + RK3528_ACM_YHS_DEL_HGAIN_SEG0 + (i << 2));
2052
+ }
2053
+
2054
+ writel(1, vop2->regs + RK3528_ACM_FETCH_DONE);
2055
+}
2056
+
2057
+static void vop3_post_csc_config(struct display_state *state, struct vop2 *vop2)
2058
+{
2059
+ struct connector_state *conn_state = &state->conn_state;
2060
+ struct crtc_state *cstate = &state->crtc_state;
2061
+ struct acm_data *acm = &conn_state->disp_info->acm_data;
2062
+ struct csc_info *csc = &conn_state->disp_info->csc_info;
2063
+ struct post_csc_coef csc_coef;
2064
+ bool is_input_yuv = false;
2065
+ bool is_output_yuv = false;
2066
+ bool post_r2y_en = false;
2067
+ bool post_csc_en = false;
2068
+ u32 vp_offset = (cstate->crtc_id * 0x100);
2069
+ u32 value;
2070
+ int range_type;
2071
+
2072
+ printf("post csc enable\n");
2073
+
2074
+ if (acm->acm_enable) {
2075
+ if (!cstate->yuv_overlay)
2076
+ post_r2y_en = true;
2077
+
2078
+ /* do y2r in csc module */
2079
+ if (!is_yuv_output(conn_state->bus_format))
2080
+ post_csc_en = true;
2081
+ } else {
2082
+ if (!cstate->yuv_overlay && is_yuv_output(conn_state->bus_format))
2083
+ post_r2y_en = true;
2084
+
2085
+ /* do y2r in csc module */
2086
+ if (cstate->yuv_overlay && !is_yuv_output(conn_state->bus_format))
2087
+ post_csc_en = true;
2088
+ }
2089
+
2090
+ if (csc->csc_enable)
2091
+ post_csc_en = true;
2092
+
2093
+ if (cstate->yuv_overlay || post_r2y_en)
2094
+ is_input_yuv = true;
2095
+
2096
+ if (is_yuv_output(conn_state->bus_format))
2097
+ is_output_yuv = true;
2098
+
2099
+ cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_space, CSC_13BIT_DEPTH);
2100
+
2101
+ if (post_csc_en) {
2102
+ rockchip_calc_post_csc(csc, &csc_coef, cstate->post_csc_mode, is_input_yuv,
2103
+ is_output_yuv);
2104
+
2105
+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
2106
+ POST_CSC_COE00_MASK, POST_CSC_COE00_SHIFT,
2107
+ csc_coef.csc_coef00, false);
2108
+ value = csc_coef.csc_coef01 & 0xffff;
2109
+ value |= (csc_coef.csc_coef02 << 16) & 0xffff0000;
2110
+ writel(value, vop2->regs + RK3528_VP0_CSC_COE01_02);
2111
+ value = csc_coef.csc_coef10 & 0xffff;
2112
+ value |= (csc_coef.csc_coef11 << 16) & 0xffff0000;
2113
+ writel(value, vop2->regs + RK3528_VP0_CSC_COE10_11);
2114
+ value = csc_coef.csc_coef12 & 0xffff;
2115
+ value |= (csc_coef.csc_coef20 << 16) & 0xffff0000;
2116
+ writel(value, vop2->regs + RK3528_VP0_CSC_COE12_20);
2117
+ value = csc_coef.csc_coef21 & 0xffff;
2118
+ value |= (csc_coef.csc_coef22 << 16) & 0xffff0000;
2119
+ writel(value, vop2->regs + RK3528_VP0_CSC_COE21_22);
2120
+ writel(csc_coef.csc_dc0, vop2->regs + RK3528_VP0_CSC_OFFSET0);
2121
+ writel(csc_coef.csc_dc1, vop2->regs + RK3528_VP0_CSC_OFFSET1);
2122
+ writel(csc_coef.csc_dc2, vop2->regs + RK3528_VP0_CSC_OFFSET2);
2123
+
2124
+ range_type = csc_coef.range_type ? 0 : 1;
2125
+ range_type <<= is_input_yuv ? 0 : 1;
2126
+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
2127
+ POST_CSC_MODE_MASK, POST_CSC_MODE_SHIFT, range_type, false);
2128
+ }
2129
+
2130
+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
2131
+ POST_R2Y_EN_MASK, POST_R2Y_EN_SHIFT, post_r2y_en ? 1 : 0, false);
2132
+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
2133
+ POST_CSC_EN_MASK, POST_CSC_EN_SHIFT, post_csc_en ? 1 : 0, false);
2134
+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
2135
+ POST_R2Y_MODE_MASK, POST_R2Y_MODE_SHIFT, cstate->post_csc_mode, false);
2136
+}
2137
+
2138
+static void vop3_post_config(struct display_state *state, struct vop2 *vop2)
2139
+{
2140
+ struct connector_state *conn_state = &state->conn_state;
2141
+ struct base2_disp_info *disp_info = conn_state->disp_info;
2142
+ const char *enable_flag;
2143
+ if (!disp_info) {
2144
+ printf("disp_info is empty\n");
2145
+ return;
2146
+ }
2147
+
2148
+ enable_flag = (const char *)&disp_info->cacm_header;
2149
+ if (strncasecmp(enable_flag, "CACM", 4)) {
2150
+ printf("acm and csc is not support\n");
2151
+ return;
2152
+ }
2153
+
2154
+ vop3_post_acm_config(state, vop2);
2155
+ vop3_post_csc_config(state, vop2);
16502156 }
16512157
16522158 /*
....@@ -1731,112 +2237,55 @@
17312237 vop2->regsbak[i] = base[i];
17322238 }
17332239
1734
-static void vop2_global_initial(struct vop2 *vop2, struct display_state *state)
2240
+static void vop3_overlay_init(struct vop2 *vop2, struct display_state *state)
2241
+{
2242
+ struct vop2_win_data *win_data;
2243
+ int layer_phy_id = 0;
2244
+ int i, j;
2245
+ u32 ovl_port_offset = 0;
2246
+ u32 layer_nr = 0;
2247
+ u8 shift = 0;
2248
+
2249
+ /* layer sel win id */
2250
+ for (i = 0; i < vop2->data->nr_vps; i++) {
2251
+ shift = 0;
2252
+ ovl_port_offset = 0x100 * i;
2253
+ layer_nr = vop2->vp_plane_mask[i].attached_layers_nr;
2254
+ for (j = 0; j < layer_nr; j++) {
2255
+ layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j];
2256
+ win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id);
2257
+ vop2_mask_write(vop2, RK3528_OVL_PORT0_LAYER_SEL + ovl_port_offset, LAYER_SEL_MASK,
2258
+ shift, win_data->layer_sel_win_id[i], false);
2259
+ shift += 4;
2260
+ }
2261
+ }
2262
+
2263
+ /* win sel port */
2264
+ for (i = 0; i < vop2->data->nr_vps; i++) {
2265
+ layer_nr = vop2->vp_plane_mask[i].attached_layers_nr;
2266
+ for (j = 0; j < layer_nr; j++) {
2267
+ if (!vop2->vp_plane_mask[i].attached_layers[j])
2268
+ continue;
2269
+ layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j];
2270
+ win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id);
2271
+ shift = win_data->win_sel_port_offset * 2;
2272
+ vop2_mask_write(vop2, RK3528_OVL_SYS_PORT_SEL_IMD, LAYER_SEL_PORT_MASK,
2273
+ shift, i, false);
2274
+ }
2275
+ }
2276
+}
2277
+
2278
+static void vop2_overlay_init(struct vop2 *vop2, struct display_state *state)
17352279 {
17362280 struct crtc_state *cstate = &state->crtc_state;
1737
- int i, j, port_mux = 0, total_used_layer = 0;
1738
- u8 shift = 0;
1739
- int layer_phy_id = 0;
1740
- u32 layer_nr = 0;
17412281 struct vop2_win_data *win_data;
1742
- struct vop2_vp_plane_mask *plane_mask;
2282
+ int layer_phy_id = 0;
2283
+ int total_used_layer = 0;
2284
+ int port_mux = 0;
2285
+ int i, j;
2286
+ u32 layer_nr = 0;
2287
+ u8 shift = 0;
17432288
1744
- if (vop2->global_init)
1745
- return;
1746
-
1747
- /* OTP must enable at the first time, otherwise mirror layer register is error */
1748
- if (soc_is_rk3566())
1749
- vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK,
1750
- OTP_WIN_EN_SHIFT, 1, false);
1751
-
1752
- if (cstate->crtc->assign_plane) {/* dts assign plane */
1753
- u32 plane_mask;
1754
- int primary_plane_id;
1755
-
1756
- for (i = 0; i < vop2->data->nr_vps; i++) {
1757
- plane_mask = cstate->crtc->vps[i].plane_mask;
1758
- vop2->vp_plane_mask[i].plane_mask = plane_mask;
1759
- layer_nr = hweight32(plane_mask); /* use bitmap to store plane mask */
1760
- vop2->vp_plane_mask[i].attached_layers_nr = layer_nr;
1761
- primary_plane_id = cstate->crtc->vps[i].primary_plane_id;
1762
- if (primary_plane_id < 0)
1763
- primary_plane_id = vop2_get_primary_plane(vop2, plane_mask);
1764
- vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id;
1765
- vop2->vp_plane_mask[i].plane_mask = plane_mask;
1766
-
1767
- /* plane mask[bitmap] convert into layer phy id[enum vop2_layer_phy_id]*/
1768
- for (j = 0; j < layer_nr; j++) {
1769
- vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1;
1770
- plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]);
1771
- }
1772
- }
1773
- } else {/* need soft assign plane mask */
1774
- /* find the first unplug devices and set it as main display */
1775
- int main_vp_index = -1;
1776
- int active_vp_num = 0;
1777
-
1778
- for (i = 0; i < vop2->data->nr_vps; i++) {
1779
- if (cstate->crtc->vps[i].enable)
1780
- active_vp_num++;
1781
- }
1782
- printf("VOP have %d active VP\n", active_vp_num);
1783
-
1784
- if (soc_is_rk3566() && active_vp_num > 2)
1785
- printf("ERROR: rk3566 only support 2 display output!!\n");
1786
- plane_mask = vop2->data->plane_mask;
1787
- plane_mask += (active_vp_num - 1) * VOP2_VP_MAX;
1788
-
1789
- for (i = 0; i < vop2->data->nr_vps; i++) {
1790
- if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) {
1791
- vop2->vp_plane_mask[i] = plane_mask[0]; /* the first store main display plane mask*/
1792
- main_vp_index = i;
1793
- break;
1794
- }
1795
- }
1796
-
1797
- /* if no find unplug devices, use vp0 as main display */
1798
- if (main_vp_index < 0) {
1799
- main_vp_index = 0;
1800
- vop2->vp_plane_mask[0] = plane_mask[0];
1801
- }
1802
-
1803
- j = 1; /* plane_mask[0] store main display, so we from plane_mask[1] */
1804
-
1805
- /* init other display except main display */
1806
- for (i = 0; i < vop2->data->nr_vps; i++) {
1807
- if (i == main_vp_index || !cstate->crtc->vps[i].enable) /* main display or no connect devices */
1808
- continue;
1809
- vop2->vp_plane_mask[i] = plane_mask[j++];
1810
- }
1811
-
1812
- /* store plane mask for vop2_fixup_dts */
1813
- for (i = 0; i < vop2->data->nr_vps; i++) {
1814
- layer_nr = vop2->vp_plane_mask[i].attached_layers_nr;
1815
- for (j = 0; j < layer_nr; j++) {
1816
- layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j];
1817
- vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id);
1818
- }
1819
- }
1820
- }
1821
-
1822
- if (vop2->version == VOP_VERSION_RK3588)
1823
- rk3588_vop2_regsbak(vop2);
1824
- else
1825
- memcpy(vop2->regsbak, vop2->regs, vop2->reg_len);
1826
-
1827
- vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK,
1828
- OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false);
1829
- vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
1830
- IF_CTRL_REG_DONE_IMD_SHIFT, 1, false);
1831
-
1832
- for (i = 0; i < vop2->data->nr_vps; i++) {
1833
- printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr);
1834
- for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++)
1835
- printf("%d ", vop2->vp_plane_mask[i].attached_layers[j]);
1836
- printf("], primary plane: %d\n", vop2->vp_plane_mask[i].primary_plane_id);
1837
- }
1838
-
1839
- shift = 0;
18402289 /* layer sel win id */
18412290 for (i = 0; i < vop2->data->nr_vps; i++) {
18422291 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr;
....@@ -1844,7 +2293,7 @@
18442293 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j];
18452294 win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id);
18462295 vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK,
1847
- shift, win_data->layer_sel_win_id, false);
2296
+ shift, win_data->layer_sel_win_id[i], false);
18482297 shift += 4;
18492298 }
18502299 }
....@@ -1882,6 +2331,190 @@
18822331 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK,
18832332 PORT_MUX_SHIFT + shift, port_mux, false);
18842333 }
2334
+}
2335
+
2336
+static bool vop3_ignore_plane(struct vop2 *vop2, struct vop2_win_data *win)
2337
+{
2338
+ if (!is_vop3(vop2))
2339
+ return false;
2340
+
2341
+ if (vop2->esmart_lb_mode == VOP3_ESMART_8K_MODE &&
2342
+ win->phys_id != ROCKCHIP_VOP2_ESMART0)
2343
+ return true;
2344
+ else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_4K_MODE &&
2345
+ (win->phys_id == ROCKCHIP_VOP2_ESMART1 || win->phys_id == ROCKCHIP_VOP2_ESMART3))
2346
+ return true;
2347
+ else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_2K_2K_MODE &&
2348
+ win->phys_id == ROCKCHIP_VOP2_ESMART1)
2349
+ return true;
2350
+ else
2351
+ return false;
2352
+}
2353
+
2354
+static void vop3_init_esmart_scale_engine(struct vop2 *vop2)
2355
+{
2356
+ struct vop2_win_data *win_data;
2357
+ int i;
2358
+ u8 scale_engine_num = 0;
2359
+
2360
+ /* store plane mask for vop2_fixup_dts */
2361
+ for (i = 0; i < vop2->data->nr_layers; i++) {
2362
+ win_data = &vop2->data->win_data[i];
2363
+ if (win_data->type == CLUSTER_LAYER || vop3_ignore_plane(vop2, win_data))
2364
+ continue;
2365
+
2366
+ win_data->scale_engine_num = scale_engine_num++;
2367
+ }
2368
+}
2369
+
2370
+static void vop2_global_initial(struct vop2 *vop2, struct display_state *state)
2371
+{
2372
+ struct crtc_state *cstate = &state->crtc_state;
2373
+ struct vop2_vp_plane_mask *plane_mask;
2374
+ int layer_phy_id = 0;
2375
+ int i, j;
2376
+ int ret;
2377
+ u32 layer_nr = 0;
2378
+
2379
+ if (vop2->global_init)
2380
+ return;
2381
+
2382
+ /* OTP must enable at the first time, otherwise mirror layer register is error */
2383
+ if (soc_is_rk3566())
2384
+ vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK,
2385
+ OTP_WIN_EN_SHIFT, 1, false);
2386
+
2387
+ if (cstate->crtc->assign_plane) {/* dts assign plane */
2388
+ u32 plane_mask;
2389
+ int primary_plane_id;
2390
+
2391
+ for (i = 0; i < vop2->data->nr_vps; i++) {
2392
+ plane_mask = cstate->crtc->vps[i].plane_mask;
2393
+ vop2->vp_plane_mask[i].plane_mask = plane_mask;
2394
+ layer_nr = hweight32(plane_mask); /* use bitmap to store plane mask */
2395
+ vop2->vp_plane_mask[i].attached_layers_nr = layer_nr;
2396
+ primary_plane_id = cstate->crtc->vps[i].primary_plane_id;
2397
+ if (primary_plane_id >= ROCKCHIP_VOP2_LAYER_MAX)
2398
+ primary_plane_id = vop2_get_primary_plane(vop2, plane_mask);
2399
+ vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id;
2400
+ vop2->vp_plane_mask[i].plane_mask = plane_mask;
2401
+
2402
+ /* plane mask[bitmap] convert into layer phy id[enum vop2_layer_phy_id]*/
2403
+ for (j = 0; j < layer_nr; j++) {
2404
+ vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1;
2405
+ plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]);
2406
+ }
2407
+ }
2408
+ } else {/* need soft assign plane mask */
2409
+ /* find the first unplug devices and set it as main display */
2410
+ int main_vp_index = -1;
2411
+ int active_vp_num = 0;
2412
+
2413
+ for (i = 0; i < vop2->data->nr_vps; i++) {
2414
+ if (cstate->crtc->vps[i].enable)
2415
+ active_vp_num++;
2416
+ }
2417
+ printf("VOP have %d active VP\n", active_vp_num);
2418
+
2419
+ if (soc_is_rk3566() && active_vp_num > 2)
2420
+ printf("ERROR: rk3566 only support 2 display output!!\n");
2421
+ plane_mask = vop2->data->plane_mask;
2422
+ plane_mask += (active_vp_num - 1) * VOP2_VP_MAX;
2423
+ /*
2424
+ * For rk3528, one display policy for hdmi store in plane_mask[0], and the other
2425
+ * for cvbs store in plane_mask[2].
2426
+ */
2427
+ if (vop2->version == VOP_VERSION_RK3528 && active_vp_num == 1 &&
2428
+ cstate->crtc->vps[1].output_type == DRM_MODE_CONNECTOR_TV)
2429
+ plane_mask += 2 * VOP2_VP_MAX;
2430
+
2431
+ if (vop2->version == VOP_VERSION_RK3528) {
2432
+ /*
2433
+ * For rk3528, the plane mask of vp is limited, only esmart2 can be selected
2434
+ * by both vp0 and vp1.
2435
+ */
2436
+ j = 0;
2437
+ } else {
2438
+ for (i = 0; i < vop2->data->nr_vps; i++) {
2439
+ if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) {
2440
+ vop2->vp_plane_mask[i] = plane_mask[0]; /* the first store main display plane mask*/
2441
+ main_vp_index = i;
2442
+ break;
2443
+ }
2444
+ }
2445
+
2446
+ /* if no find unplug devices, use vp0 as main display */
2447
+ if (main_vp_index < 0) {
2448
+ main_vp_index = 0;
2449
+ vop2->vp_plane_mask[0] = plane_mask[0];
2450
+ }
2451
+
2452
+ j = 1; /* plane_mask[0] store main display, so we from plane_mask[1] */
2453
+ }
2454
+
2455
+ /* init other display except main display */
2456
+ for (i = 0; i < vop2->data->nr_vps; i++) {
2457
+ if (i == main_vp_index || !cstate->crtc->vps[i].enable) /* main display or no connect devices */
2458
+ continue;
2459
+ vop2->vp_plane_mask[i] = plane_mask[j++];
2460
+ }
2461
+
2462
+ /* store plane mask for vop2_fixup_dts */
2463
+ for (i = 0; i < vop2->data->nr_vps; i++) {
2464
+ layer_nr = vop2->vp_plane_mask[i].attached_layers_nr;
2465
+ for (j = 0; j < layer_nr; j++) {
2466
+ layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j];
2467
+ vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id);
2468
+ }
2469
+ }
2470
+ }
2471
+
2472
+ if (vop2->version == VOP_VERSION_RK3588)
2473
+ rk3588_vop2_regsbak(vop2);
2474
+ else
2475
+ memcpy(vop2->regsbak, vop2->regs, vop2->reg_len);
2476
+
2477
+ vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK,
2478
+ OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false);
2479
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
2480
+ IF_CTRL_REG_DONE_IMD_SHIFT, 1, false);
2481
+
2482
+ for (i = 0; i < vop2->data->nr_vps; i++) {
2483
+ printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr);
2484
+ for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++)
2485
+ printf("%d ", vop2->vp_plane_mask[i].attached_layers[j]);
2486
+ printf("], primary plane: %d\n", vop2->vp_plane_mask[i].primary_plane_id);
2487
+ }
2488
+
2489
+ if (is_vop3(vop2))
2490
+ vop3_overlay_init(vop2, state);
2491
+ else
2492
+ vop2_overlay_init(vop2, state);
2493
+
2494
+ if (is_vop3(vop2)) {
2495
+ /*
2496
+ * you can rewrite at dts vop node:
2497
+ *
2498
+ * VOP3_ESMART_8K_MODE = 0,
2499
+ * VOP3_ESMART_4K_4K_MODE = 1,
2500
+ * VOP3_ESMART_4K_2K_2K_MODE = 2,
2501
+ * VOP3_ESMART_2K_2K_2K_2K_MODE = 3,
2502
+ *
2503
+ * &vop {
2504
+ * esmart_lb_mode = /bits/ 8 <2>;
2505
+ * };
2506
+ */
2507
+ ret = ofnode_read_u32(cstate->node, "esmart_lb_mode", &vop2->esmart_lb_mode);
2508
+ if (ret < 0)
2509
+ vop2->esmart_lb_mode = vop2->data->esmart_lb_mode;
2510
+ vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, ESMART_LB_MODE_SEL_MASK,
2511
+ ESMART_LB_MODE_SEL_SHIFT, vop2->esmart_lb_mode, false);
2512
+
2513
+ vop3_init_esmart_scale_engine(vop2);
2514
+
2515
+ vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, EN_MASK,
2516
+ DSP_VS_T_SEL_SHIFT, 0, false);
2517
+ }
18852518
18862519 if (vop2->version == VOP_VERSION_RK3568)
18872520 vop2_writel(vop2, RK3568_AUTO_GATING_CTRL, 0);
....@@ -1891,14 +2524,6 @@
18912524
18922525 static int vop2_initial(struct vop2 *vop2, struct display_state *state)
18932526 {
1894
- struct crtc_state *cstate = &state->crtc_state;
1895
- int ret;
1896
-
1897
- /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
1898
- ret = clk_set_defaults(cstate->dev);
1899
- if (ret)
1900
- debug("%s clk_set_defaults failed %d\n", __func__, ret);
1901
-
19022527 rockchip_vop2_gamma_lut_init(vop2, state);
19032528 rockchip_vop2_cubic_lut_init(vop2, state);
19042529
....@@ -1918,12 +2543,17 @@
19182543 rockchip_vop2 = calloc(1, sizeof(struct vop2));
19192544 if (!rockchip_vop2)
19202545 return -ENOMEM;
1921
- rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev);
2546
+ memset(rockchip_vop2, 0, sizeof(struct vop2));
19222547 rockchip_vop2->regsbak = malloc(RK3568_MAX_REG);
19232548 rockchip_vop2->reg_len = RK3568_MAX_REG;
2549
+#ifdef CONFIG_SPL_BUILD
2550
+ rockchip_vop2->regs = (void *)RK3528_VOP_BASE;
2551
+#else
2552
+ rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev);
19242553 rockchip_vop2->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
19252554 if (rockchip_vop2->grf <= 0)
19262555 printf("%s: Get syscon grf failed (ret=%p)\n", __func__, rockchip_vop2->grf);
2556
+#endif
19272557 rockchip_vop2->version = vop2_data->version;
19282558 rockchip_vop2->data = vop2_data;
19292559 if (rockchip_vop2->version == VOP_VERSION_RK3588) {
....@@ -2021,11 +2651,12 @@
20212651 }
20222652
20232653 if (v_pixclk > VOP2_MAX_DCLK_RATE)
2024
- dclk_rate = vop2_calc_dclk(dclk_core_rate, vop2->data->vp_data->max_dclk);
2654
+ dclk_rate = vop2_calc_dclk(dclk_core_rate,
2655
+ vop2->data->vp_data[cstate->crtc_id].max_dclk);
20252656
20262657 if (!dclk_rate) {
20272658 printf("DP if_pixclk_rate out of range(max_dclk: %d KHZ, dclk_core: %lld KHZ)\n",
2028
- vop2->data->vp_data->max_dclk, if_pixclk_rate);
2659
+ vop2->data->vp_data[cstate->crtc_id].max_dclk, if_pixclk_rate);
20292660 return -EINVAL;
20302661 }
20312662 *if_pixclk_div = dclk_rate / if_pixclk_rate;
....@@ -2045,10 +2676,11 @@
20452676 dclk_out_rate = v_pixclk >> 2;
20462677 dclk_out_rate = dclk_out_rate / K;
20472678
2048
- dclk_rate = vop2_calc_dclk(dclk_out_rate, vop2->data->vp_data->max_dclk);
2679
+ dclk_rate = vop2_calc_dclk(dclk_out_rate,
2680
+ vop2->data->vp_data[cstate->crtc_id].max_dclk);
20492681 if (!dclk_rate) {
20502682 printf("DP dclk_core out of range(max_dclk: %d KHZ, dclk_core: %ld KHZ)\n",
2051
- vop2->data->vp_data->max_dclk, dclk_core_rate);
2683
+ vop2->data->vp_data[cstate->crtc_id].max_dclk, dclk_core_rate);
20522684 return -EINVAL;
20532685 }
20542686 *dclk_out_div = dclk_rate / dclk_out_rate;
....@@ -2064,21 +2696,22 @@
20642696 /* dclk_core = dclk_out * K = if_pixclk * K = v_pixclk / 4 */
20652697 dclk_out_rate = dclk_core_rate / K;
20662698 /* dclk_rate = N * dclk_core_rate N = (1,2,4 ), we get a little factor here */
2067
- dclk_rate = vop2_calc_dclk(dclk_out_rate, vop2->data->vp_data->max_dclk);
2699
+ dclk_rate = vop2_calc_dclk(dclk_out_rate,
2700
+ vop2->data->vp_data[cstate->crtc_id].max_dclk);
20682701 if (!dclk_rate) {
20692702 printf("MIPI dclk out of range(max_dclk: %d KHZ, dclk_rate: %ld KHZ)\n",
2070
- vop2->data->vp_data->max_dclk, dclk_rate);
2703
+ vop2->data->vp_data[cstate->crtc_id].max_dclk, dclk_rate);
20712704 return -EINVAL;
20722705 }
20732706
20742707 if (cstate->dsc_enable)
2075
- dclk_rate = dclk_rate >> 1;
2708
+ dclk_rate /= cstate->dsc_slice_num;
20762709
20772710 *dclk_out_div = dclk_rate / dclk_out_rate;
20782711 *dclk_core_div = dclk_rate / dclk_core_rate;
20792712 *if_pixclk_div = 1; /*mipi pixclk == dclk_out*/
20802713 if (cstate->dsc_enable)
2081
- *if_pixclk_div = dclk_out_rate / if_pixclk_rate;
2714
+ *if_pixclk_div = dclk_out_rate * 1000LL / if_pixclk_rate;
20822715
20832716 } else if (output_type == DRM_MODE_CONNECTOR_DPI) {
20842717 dclk_rate = v_pixclk;
....@@ -2098,7 +2731,7 @@
20982731 struct connector_state *conn_state = &state->conn_state;
20992732 struct drm_display_mode *mode = &conn_state->mode;
21002733 struct crtc_state *cstate = &state->crtc_state;
2101
- u64 v_pixclk = mode->clock; /* video timing pixclk */
2734
+ u64 v_pixclk = mode->crtc_clock * 1000LL; /* video timing pixclk */
21022735 u8 k = 1;
21032736
21042737 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
....@@ -2201,8 +2834,7 @@
22012834
22022835 if (conn_state->hold_mode) {
22032836 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
2204
- EN_MASK, EDPI_TE_EN, 1, false);
2205
-
2837
+ EN_MASK, EDPI_TE_EN, !cstate->soft_te, false);
22062838 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
22072839 EN_MASK, EDPI_WMS_HOLD_EN, 1, false);
22082840 }
....@@ -2227,14 +2859,8 @@
22272859 if_pixclk_div, false);
22282860
22292861 if (conn_state->hold_mode) {
2230
- /* UNDO: RK3588 VP1->DSC1->DSI1 only can support soft TE mode */
2231
- if (vop2->version == VOP_VERSION_RK3588 && val == 3)
2232
- vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
2233
- EN_MASK, EDPI_TE_EN, 0, false);
2234
- else
2235
- vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
2236
- EN_MASK, EDPI_TE_EN, 1, false);
2237
-
2862
+ vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
2863
+ EN_MASK, EDPI_TE_EN, !cstate->soft_te, false);
22382864 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
22392865 EN_MASK, EDPI_WMS_HOLD_EN, 1, false);
22402866 }
....@@ -2371,7 +2997,7 @@
23712997 bool dclk_inv;
23722998 u32 val;
23732999
2374
- dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1;
3000
+ dclk_inv = (conn_state->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0;
23753001 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
23763002 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
23773003
....@@ -2380,6 +3006,8 @@
23803006 1, false);
23813007 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
23823008 RGB_MUX_SHIFT, cstate->crtc_id, false);
3009
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK,
3010
+ IF_CTRL_RGB_LVDS_PIN_POL_SHIFT, val, false);
23833011 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK,
23843012 GRF_RGB_DCLK_INV_SHIFT, dclk_inv);
23853013 }
....@@ -2409,8 +3037,10 @@
24093037 1, false);
24103038 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
24113039 LVDS0_MUX_SHIFT, cstate->crtc_id, false);
3040
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK,
3041
+ IF_CTRL_RGB_LVDS_PIN_POL_SHIFT, val, false);
24123042 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
2413
- IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false);
3043
+ IF_CTRL_RGB_LVDS_DCLK_POL_SHIFT, dclk_inv, false);
24143044 }
24153045
24163046 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS1) {
....@@ -2418,8 +3048,10 @@
24183048 1, false);
24193049 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
24203050 LVDS1_MUX_SHIFT, cstate->crtc_id, false);
3051
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK,
3052
+ IF_CTRL_RGB_LVDS_PIN_POL_SHIFT, val, false);
24213053 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
2422
- IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false);
3054
+ IF_CTRL_RGB_LVDS_DCLK_POL_SHIFT, dclk_inv, false);
24233055 }
24243056
24253057 if (conn_state->output_flags &
....@@ -2472,6 +3104,8 @@
24723104 EDP0_MUX_SHIFT, cstate->crtc_id, false);
24733105 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
24743106 IF_CRTL_EDP_DCLK_POL_SHIT, dclk_inv, false);
3107
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_EDP_PIN_POL_MASK,
3108
+ IF_CTRL_EDP_PIN_POL_SHIFT, val, false);
24753109 }
24763110
24773111 if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) {
....@@ -2489,6 +3123,88 @@
24893123 return mode->clock;
24903124 }
24913125
3126
+static unsigned long rk3528_vop2_if_cfg(struct display_state *state)
3127
+{
3128
+ struct crtc_state *cstate = &state->crtc_state;
3129
+ struct connector_state *conn_state = &state->conn_state;
3130
+ struct drm_display_mode *mode = &conn_state->mode;
3131
+ struct vop2 *vop2 = cstate->private;
3132
+ u32 val;
3133
+
3134
+ val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
3135
+ val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
3136
+
3137
+ if (conn_state->output_if & VOP_OUTPUT_IF_BT656) {
3138
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT,
3139
+ 1, false);
3140
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
3141
+ RGB_MUX_SHIFT, cstate->crtc_id, false);
3142
+ }
3143
+
3144
+ if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) {
3145
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT,
3146
+ 1, false);
3147
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
3148
+ HDMI0_MUX_SHIFT, cstate->crtc_id, false);
3149
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
3150
+ IF_CRTL_HDMI_DCLK_POL_SHIT, 1, false);
3151
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL,
3152
+ IF_CRTL_HDMI_PIN_POL_MASK,
3153
+ IF_CRTL_HDMI_PIN_POL_SHIT, val, false);
3154
+ }
3155
+
3156
+ return mode->crtc_clock;
3157
+}
3158
+
3159
+static unsigned long rk3562_vop2_if_cfg(struct display_state *state)
3160
+{
3161
+ struct crtc_state *cstate = &state->crtc_state;
3162
+ struct connector_state *conn_state = &state->conn_state;
3163
+ struct drm_display_mode *mode = &conn_state->mode;
3164
+ struct vop2 *vop2 = cstate->private;
3165
+ bool dclk_inv;
3166
+ u32 val;
3167
+
3168
+ dclk_inv = (conn_state->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0;
3169
+ val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
3170
+ val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
3171
+
3172
+ if (conn_state->output_if & VOP_OUTPUT_IF_RGB) {
3173
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT,
3174
+ 1, false);
3175
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
3176
+ RGB_MUX_SHIFT, cstate->crtc_id, false);
3177
+ vop2_grf_writel(vop2, vop2->grf, RK3562_GRF_IOC_VO_IO_CON, EN_MASK,
3178
+ GRF_RGB_DCLK_INV_SHIFT, dclk_inv);
3179
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK,
3180
+ IF_CTRL_RGB_LVDS_PIN_POL_SHIFT, val, false);
3181
+ }
3182
+
3183
+ if (conn_state->output_if & VOP_OUTPUT_IF_LVDS0) {
3184
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT,
3185
+ 1, false);
3186
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
3187
+ LVDS0_MUX_SHIFT, cstate->crtc_id, false);
3188
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
3189
+ IF_CTRL_RGB_LVDS_DCLK_POL_SHIFT, dclk_inv, false);
3190
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK,
3191
+ IF_CTRL_RGB_LVDS_PIN_POL_SHIFT, val, false);
3192
+ }
3193
+
3194
+ if (conn_state->output_if & VOP_OUTPUT_IF_MIPI0) {
3195
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT,
3196
+ 1, false);
3197
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
3198
+ MIPI0_MUX_SHIFT, cstate->crtc_id, false);
3199
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
3200
+ RK3562_MIPI_DCLK_POL_SHIFT, dclk_inv, false);
3201
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK,
3202
+ RK3562_MIPI_PIN_POL_SHIFT, val, false);
3203
+ }
3204
+
3205
+ return mode->crtc_clock;
3206
+}
3207
+
24923208 static void vop2_post_color_swap(struct display_state *state)
24933209 {
24943210 struct crtc_state *cstate = &state->crtc_state;
....@@ -2498,7 +3214,8 @@
24983214 u32 output_type = conn_state->type;
24993215 u32 data_swap = 0;
25003216
2501
- if (is_uv_swap(conn_state->bus_format, conn_state->output_mode))
3217
+ if (is_uv_swap(conn_state->bus_format, conn_state->output_mode) ||
3218
+ is_rb_swap(conn_state->bus_format, conn_state->output_mode))
25023219 data_swap = DSP_RB_SWAP;
25033220
25043221 if (vop2->version == VOP_VERSION_RK3588 &&
....@@ -2603,10 +3320,10 @@
26033320 u16 vact_end = vact_st + vdisplay;
26043321 u32 ctrl_regs_offset = (dsc_id * 0x30);
26053322 u32 decoder_regs_offset = (dsc_id * 0x100);
2606
- u32 backup_regs_offset = 0;
26073323 int dsc_txp_clk_div = 0;
26083324 int dsc_pxl_clk_div = 0;
26093325 int dsc_cds_clk_div = 0;
3326
+ int val = 0;
26103327
26113328 if (!vop2->data->nr_dscs) {
26123329 printf("Unsupported DSC\n");
....@@ -2678,21 +3395,42 @@
26783395 * dly_num = delay_line_num * T(one-line) / T (dsc_cds)
26793396 * T (one-line) = 1/v_pixclk_mhz * htotal = htotal/v_pixclk_mhz
26803397 * T (dsc_cds) = 1 / dsc_cds_rate_mhz
3398
+ *
3399
+ * HDMI:
26813400 * delay_line_num: according the pps initial_xmit_delay to adjust vop dsc delay
26823401 * delay_line_num = 4 - BPP / 8
26833402 * = (64 - target_bpp / 8) / 16
2684
- *
26853403 * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
3404
+ *
3405
+ * MIPI DSI[4320 and 9216 is buffer size for DSC]:
3406
+ * DSC0:delay_line_num = 4320 * 8 / slince_num / chunk_size;
3407
+ * delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
3408
+ * DSC1:delay_line_num = 9216 * 2 / slince_num / chunk_size;
3409
+ * delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
3410
+ * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * delay_line_num
26863411 */
26873412 do_div(dsc_cds_rate, 1000000); /* hz to Mhz */
26883413 dsc_cds_rate_mhz = dsc_cds_rate;
2689
- dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
3414
+ dsc_hsync = hsync_len / 2;
3415
+ if (dsc_interface_mode == VOP_DSC_IF_HDMI) {
3416
+ dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
3417
+ } else {
3418
+ int dsc_buf_size = dsc_id == 0 ? 4320 * 8 : 9216 * 2;
3419
+ int delay_line_num = dsc_buf_size / cstate->dsc_slice_num /
3420
+ be16_to_cpu(cstate->pps.chunk_size);
3421
+
3422
+ delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
3423
+ dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * delay_line_num;
3424
+
3425
+ /* The dsc mipi video mode dsc_hsync minimum size is 8 pixels */
3426
+ if (dsc_hsync < 8)
3427
+ dsc_hsync = 8;
3428
+ }
26903429 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_MODE_MASK,
26913430 DSC_INIT_DLY_MODE_SHIFT, 0, false);
26923431 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_NUM_MASK,
26933432 DSC_INIT_DLY_NUM_SHIFT, dly_num, false);
26943433
2695
- dsc_hsync = hsync_len / 2;
26963434 /*
26973435 * htotal / dclk_core = dsc_htotal /cds_clk
26983436 *
....@@ -2724,34 +3462,15 @@
27243462 vop2_mask_write(vop2, RK3588_DSC_8K_RST + ctrl_regs_offset, RST_DEASSERT_MASK,
27253463 RST_DEASSERT_SHIFT, 1, false);
27263464 udelay(10);
2727
- /* read current dsc core register and backup to regsbak */
2728
- backup_regs_offset = RK3588_DSC_8K_CTRL0;
2729
- vop2->regsbak[backup_regs_offset >> 2] = vop2_readl(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset);
27303465
2731
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2732
- DSC_EN_SHIFT, 1, false);
3466
+ val |= DSC_CTRL0_DEF_CON | (ilog2(cstate->dsc_slice_num) << DSC_NSLC_SHIFT) |
3467
+ ((dsc_sink_cap->version_minor == 2 ? 1 : 0) << DSC_IFEP_SHIFT);
3468
+ vop2_writel(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, val);
3469
+
27333470 vop2_load_pps(state, vop2, dsc_id);
27343471
2735
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2736
- DSC_RBIT_SHIFT, 1, false);
2737
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2738
- DSC_RBYT_SHIFT, 0, false);
2739
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2740
- DSC_FLAL_SHIFT, 1, false);
2741
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2742
- DSC_MER_SHIFT, 1, false);
2743
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2744
- DSC_EPB_SHIFT, 0, false);
2745
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2746
- DSC_EPL_SHIFT, 1, false);
2747
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2748
- DSC_NSLC_SHIFT, ilog2(cstate->dsc_slice_num), false);
2749
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2750
- DSC_SBO_SHIFT, 1, false);
2751
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2752
- DSC_IFEP_SHIFT, dsc_sink_cap->version_minor == 2 ? 1 : 0, false);
2753
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
2754
- DSC_PPS_UPD_SHIFT, 1, false);
3472
+ val |= (1 << DSC_PPS_UPD_SHIFT);
3473
+ vop2_writel(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, val);
27553474
27563475 printf("DSC%d: txp:%lld div:%d, pxl:%lld div:%d, dsc:%lld div:%d\n",
27573476 dsc_id,
....@@ -2800,6 +3519,133 @@
28003519 return false;
28013520 }
28023521
3522
+static void vop3_mcu_mode_setup(struct display_state *state)
3523
+{
3524
+ struct crtc_state *cstate = &state->crtc_state;
3525
+ struct vop2 *vop2 = cstate->private;
3526
+ u32 vp_offset = (cstate->crtc_id * 0x100);
3527
+
3528
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
3529
+ MCU_TYPE_SHIFT, 1, false);
3530
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
3531
+ MCU_HOLD_MODE_SHIFT, 1, false);
3532
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK,
3533
+ MCU_PIX_TOTAL_SHIFT, cstate->mcu_timing.mcu_pix_total, false);
3534
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK,
3535
+ MCU_CS_PST_SHIFT, cstate->mcu_timing.mcu_cs_pst, false);
3536
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK,
3537
+ MCU_CS_PEND_SHIFT, cstate->mcu_timing.mcu_cs_pend, false);
3538
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK,
3539
+ MCU_RW_PST_SHIFT, cstate->mcu_timing.mcu_rw_pst, false);
3540
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK,
3541
+ MCU_RW_PEND_SHIFT, cstate->mcu_timing.mcu_rw_pend, false);
3542
+}
3543
+
3544
+static void vop3_mcu_bypass_mode_setup(struct display_state *state)
3545
+{
3546
+ struct crtc_state *cstate = &state->crtc_state;
3547
+ struct vop2 *vop2 = cstate->private;
3548
+ u32 vp_offset = (cstate->crtc_id * 0x100);
3549
+
3550
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
3551
+ MCU_TYPE_SHIFT, 1, false);
3552
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
3553
+ MCU_HOLD_MODE_SHIFT, 1, false);
3554
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK,
3555
+ MCU_PIX_TOTAL_SHIFT, 53, false);
3556
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK,
3557
+ MCU_CS_PST_SHIFT, 6, false);
3558
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK,
3559
+ MCU_CS_PEND_SHIFT, 48, false);
3560
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK,
3561
+ MCU_RW_PST_SHIFT, 12, false);
3562
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK,
3563
+ MCU_RW_PEND_SHIFT, 30, false);
3564
+}
3565
+
3566
+static int rockchip_vop2_send_mcu_cmd(struct display_state *state, u32 type, u32 value)
3567
+{
3568
+ struct crtc_state *cstate = &state->crtc_state;
3569
+ struct connector_state *conn_state = &state->conn_state;
3570
+ struct drm_display_mode *mode = &conn_state->mode;
3571
+ struct vop2 *vop2 = cstate->private;
3572
+ u32 vp_offset = (cstate->crtc_id * 0x100);
3573
+ u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16);
3574
+
3575
+ /*
3576
+ * 1.disable port dclk auto gating.
3577
+ * 2.set mcu bypass mode timing to adapt to the mode of sending cmds.
3578
+ * 3.make setting of output mode take effect.
3579
+ * 4.set dclk rate to 150M, in order to sync with hclk in sending cmds.
3580
+ */
3581
+ if (type == MCU_SETBYPASS && value) {
3582
+ vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK,
3583
+ AUTO_GATING_EN_SHIFT, 0, false);
3584
+ vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK,
3585
+ PORT_DCLK_AUTO_GATING_EN_SHIFT, 0, false);
3586
+ vop3_mcu_bypass_mode_setup(state);
3587
+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
3588
+ STANDBY_EN_SHIFT, 0, false);
3589
+ vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);
3590
+ vop2_clk_set_rate(&cstate->dclk, 150000000);
3591
+ }
3592
+
3593
+ switch (type) {
3594
+ case MCU_WRCMD:
3595
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
3596
+ MCU_RS_SHIFT, 0, false);
3597
+ vop2_mask_write(vop2, RK3562_VP0_MCU_RW_BYPASS_PORT + vp_offset,
3598
+ MCU_WRITE_DATA_BYPASS_MASK, MCU_WRITE_DATA_BYPASS_SHIFT,
3599
+ value, false);
3600
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
3601
+ MCU_RS_SHIFT, 1, false);
3602
+ break;
3603
+ case MCU_WRDATA:
3604
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
3605
+ MCU_RS_SHIFT, 1, false);
3606
+ vop2_mask_write(vop2, RK3562_VP0_MCU_RW_BYPASS_PORT + vp_offset,
3607
+ MCU_WRITE_DATA_BYPASS_MASK, MCU_WRITE_DATA_BYPASS_SHIFT,
3608
+ value, false);
3609
+ break;
3610
+ case MCU_SETBYPASS:
3611
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
3612
+ MCU_BYPASS_SHIFT, value ? 1 : 0, false);
3613
+ break;
3614
+ default:
3615
+ break;
3616
+ }
3617
+
3618
+ /*
3619
+ * 1.restore port dclk auto gating.
3620
+ * 2.restore mcu data mode timing.
3621
+ * 3.restore dclk rate to crtc_clock.
3622
+ */
3623
+ if (type == MCU_SETBYPASS && !value) {
3624
+ vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK,
3625
+ AUTO_GATING_EN_SHIFT, 1, false);
3626
+ vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK,
3627
+ PORT_DCLK_AUTO_GATING_EN_SHIFT, 1, false);
3628
+ vop3_mcu_mode_setup(state);
3629
+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
3630
+ STANDBY_EN_SHIFT, 1, false);
3631
+ vop2_clk_set_rate(&cstate->dclk, mode->crtc_clock * 1000);
3632
+ }
3633
+
3634
+ return 0;
3635
+}
3636
+
3637
+static int vop2_get_vrefresh(struct display_state *state)
3638
+{
3639
+ struct crtc_state *cstate = &state->crtc_state;
3640
+ struct connector_state *conn_state = &state->conn_state;
3641
+ struct drm_display_mode *mode = &conn_state->mode;
3642
+
3643
+ if (cstate->mcu_timing.mcu_pix_total)
3644
+ return mode->vrefresh / cstate->mcu_timing.mcu_pix_total;
3645
+ else
3646
+ return mode->vrefresh;
3647
+}
3648
+
28033649 static int rockchip_vop2_init(struct display_state *state)
28043650 {
28053651 struct crtc_state *cstate = &state->crtc_state;
....@@ -2822,22 +3668,24 @@
28223668 u32 line_flag_offset = (cstate->crtc_id * 4);
28233669 u32 val, act_end;
28243670 u8 dither_down_en = 0;
3671
+ u8 dither_down_mode = 0;
28253672 u8 pre_dither_down_en = 0;
28263673 u8 dclk_div_factor = 0;
28273674 char output_type_name[30] = {0};
3675
+#ifndef CONFIG_SPL_BUILD
28283676 char dclk_name[9];
2829
- struct clk dclk;
3677
+#endif
28303678 struct clk hdmi0_phy_pll;
28313679 struct clk hdmi1_phy_pll;
28323680 struct clk hdmi_phy_pll;
28333681 struct udevice *disp_dev;
2834
- unsigned long dclk_rate;
3682
+ unsigned long dclk_rate = 0;
28353683 int ret;
28363684
28373685 printf("VOP update mode to: %dx%d%s%d, type:%s for VP%d\n",
28383686 mode->crtc_hdisplay, mode->vdisplay,
28393687 mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p",
2840
- mode->vrefresh,
3688
+ vop2_get_vrefresh(state),
28413689 get_output_if_name(conn_state->output_if, output_type_name),
28423690 cstate->crtc_id);
28433691
....@@ -2854,11 +3702,20 @@
28543702 PORT_MERGE_EN_SHIFT, 1, false);
28553703 }
28563704
3705
+ vop2_mask_write(vop2, RK3588_SYS_VAR_FREQ_CTRL, EN_MASK,
3706
+ RK3588_VP0_LINE_FLAG_OR_EN_SHIFT + cstate->crtc_id, 1, false);
3707
+ vop2_mask_write(vop2, RK3588_SYS_VAR_FREQ_CTRL, EN_MASK,
3708
+ RK3588_VP0_ALMOST_FULL_OR_EN_SHIFT + cstate->crtc_id, 1, false);
3709
+
28573710 vop2_initial(vop2, state);
28583711 if (vop2->version == VOP_VERSION_RK3588)
28593712 dclk_rate = rk3588_vop2_if_cfg(state);
2860
- else
3713
+ else if (vop2->version == VOP_VERSION_RK3568)
28613714 dclk_rate = rk3568_vop2_if_cfg(state);
3715
+ else if (vop2->version == VOP_VERSION_RK3528)
3716
+ dclk_rate = rk3528_vop2_if_cfg(state);
3717
+ else if (vop2->version == VOP_VERSION_RK3562)
3718
+ dclk_rate = rk3562_vop2_if_cfg(state);
28623719
28633720 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
28643721 !(cstate->feature & VOP_FEATURE_OUTPUT_10BIT))
....@@ -2872,12 +3729,16 @@
28723729 switch (conn_state->bus_format) {
28733730 case MEDIA_BUS_FMT_RGB565_1X16:
28743731 dither_down_en = 1;
3732
+ dither_down_mode = RGB888_TO_RGB565;
3733
+ pre_dither_down_en = 1;
28753734 break;
28763735 case MEDIA_BUS_FMT_RGB666_1X18:
28773736 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
28783737 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
28793738 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA:
28803739 dither_down_en = 1;
3740
+ dither_down_mode = RGB888_TO_RGB666;
3741
+ pre_dither_down_en = 1;
28813742 break;
28823743 case MEDIA_BUS_FMT_YUV8_1X24:
28833744 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
....@@ -2886,23 +3747,28 @@
28863747 break;
28873748 case MEDIA_BUS_FMT_YUV10_1X30:
28883749 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
2889
- case MEDIA_BUS_FMT_RGB888_1X24:
2890
- case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
2891
- case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
2892
- default:
28933750 dither_down_en = 0;
28943751 pre_dither_down_en = 0;
28953752 break;
3753
+ case MEDIA_BUS_FMT_YUYV10_1X20:
3754
+ case MEDIA_BUS_FMT_RGB888_1X24:
3755
+ case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
3756
+ case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
3757
+ case MEDIA_BUS_FMT_RGB101010_1X30:
3758
+ default:
3759
+ dither_down_en = 0;
3760
+ pre_dither_down_en = 1;
3761
+ break;
28963762 }
28973763
2898
- if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA)
2899
- pre_dither_down_en = 0;
2900
- else
2901
- pre_dither_down_en = 1;
29023764 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
29033765 DITHER_DOWN_EN_SHIFT, dither_down_en, false);
29043766 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
3767
+ DITHER_DOWN_MODE_SHIFT, dither_down_mode, false);
3768
+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
29053769 PRE_DITHER_DOWN_EN_SHIFT, pre_dither_down_en, false);
3770
+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
3771
+ DITHER_DOWN_MODE_SHIFT, dither_down_mode, false);
29063772
29073773 yuv_overlay = is_yuv_output(conn_state->bus_format) ? 1 : 0;
29083774 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id,
....@@ -2946,15 +3812,13 @@
29463812 vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset,
29473813 (vtotal << 16) | vsync_len);
29483814
2949
- if (vop2->version == VOP_VERSION_RK3568) {
2950
- if (mode->flags & DRM_MODE_FLAG_DBLCLK ||
2951
- conn_state->output_if & VOP_OUTPUT_IF_BT656)
2952
- vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
2953
- CORE_DCLK_DIV_EN_SHIFT, 1, false);
2954
- else
2955
- vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
2956
- CORE_DCLK_DIV_EN_SHIFT, 0, false);
2957
- }
3815
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK ||
3816
+ conn_state->output_if & VOP_OUTPUT_IF_BT656)
3817
+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
3818
+ CORE_DCLK_DIV_EN_SHIFT, 1, false);
3819
+ else
3820
+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
3821
+ CORE_DCLK_DIV_EN_SHIFT, 0, false);
29583822
29593823 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420)
29603824 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
....@@ -2987,22 +3851,26 @@
29873851
29883852 vop2_tv_config_update(state, vop2);
29893853 vop2_post_config(state, vop2);
3854
+ if (cstate->feature & (VOP_FEATURE_POST_ACM | VOP_FEATURE_POST_CSC))
3855
+ vop3_post_config(state, vop2);
29903856
29913857 if (cstate->dsc_enable) {
29923858 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
2993
- vop2_dsc_enable(state, vop2, 0, dclk_rate);
2994
- vop2_dsc_enable(state, vop2, 1, dclk_rate);
3859
+ vop2_dsc_enable(state, vop2, 0, dclk_rate * 1000LL);
3860
+ vop2_dsc_enable(state, vop2, 1, dclk_rate * 1000LL);
29953861 } else {
2996
- vop2_dsc_enable(state, vop2, cstate->dsc_id, dclk_rate);
3862
+ vop2_dsc_enable(state, vop2, cstate->dsc_id, dclk_rate * 1000LL);
29973863 }
29983864 }
29993865
3866
+#ifndef CONFIG_SPL_BUILD
30003867 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id);
3001
- ret = clk_get_by_name(cstate->dev, dclk_name, &dclk);
3868
+ ret = clk_get_by_name(cstate->dev, dclk_name, &cstate->dclk);
30023869 if (ret) {
30033870 printf("%s: Failed to get dclk ret=%d\n", __func__, ret);
30043871 return ret;
30053872 }
3873
+#endif
30063874
30073875 ret = uclass_get_device_by_name(UCLASS_VIDEO, "display-subsystem", &disp_dev);
30083876 if (!ret) {
....@@ -3018,11 +3886,27 @@
30183886 debug("%s: Faile to find display-subsystem node\n", __func__);
30193887 }
30203888
3889
+ if (vop2->version == VOP_VERSION_RK3528) {
3890
+ struct ofnode_phandle_args args;
3891
+
3892
+ ret = dev_read_phandle_with_args(cstate->dev, "assigned-clock-parents",
3893
+ "#clock-cells", 0, 0, &args);
3894
+ if (!ret) {
3895
+ ret = uclass_find_device_by_ofnode(UCLASS_CLK, args.node, &hdmi0_phy_pll.dev);
3896
+ if (ret) {
3897
+ debug("warn: can't get clk device\n");
3898
+ return ret;
3899
+ }
3900
+ } else {
3901
+ debug("assigned-clock-parents's node not define\n");
3902
+ }
3903
+ }
3904
+
30213905 if (mode->crtc_clock < VOP2_MAX_DCLK_RATE) {
30223906 if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0)
3023
- vop2_clk_set_parent(&dclk, &hdmi0_phy_pll);
3907
+ vop2_clk_set_parent(&cstate->dclk, &hdmi0_phy_pll);
30243908 else if (conn_state->output_if & VOP_OUTPUT_IF_HDMI1)
3025
- vop2_clk_set_parent(&dclk, &hdmi1_phy_pll);
3909
+ vop2_clk_set_parent(&cstate->dclk, &hdmi1_phy_pll);
30263910
30273911 /*
30283912 * uboot clk driver won't set dclk parent's rate when use
....@@ -3035,16 +3919,28 @@
30353919 } else if ((conn_state->output_if & VOP_OUTPUT_IF_HDMI1) && hdmi1_phy_pll.dev) {
30363920 ret = vop2_clk_set_rate(&hdmi1_phy_pll, dclk_rate * 1000);
30373921 } else {
3038
- if (is_extend_pll(state, &hdmi_phy_pll.dev))
3922
+ if (is_extend_pll(state, &hdmi_phy_pll.dev)) {
30393923 ret = vop2_clk_set_rate(&hdmi_phy_pll, dclk_rate * 1000);
3040
- else
3041
- ret = vop2_clk_set_rate(&dclk, dclk_rate * 1000);
3924
+ } else {
3925
+#ifndef CONFIG_SPL_BUILD
3926
+ ret = vop2_clk_set_rate(&cstate->dclk, dclk_rate * 1000);
3927
+#else
3928
+ if (vop2->version == VOP_VERSION_RK3528) {
3929
+ void *cru_base = (void *)RK3528_CRU_BASE;
3930
+
3931
+ /* dclk src switch to hdmiphy pll */
3932
+ writel((BIT(0) << 16) | BIT(0), cru_base + 0x450);
3933
+ rockchip_phy_set_pll(conn_state->connector->phy, dclk_rate * 1000);
3934
+ ret = dclk_rate * 1000;
3935
+ }
3936
+#endif
3937
+ }
30423938 }
30433939 } else {
30443940 if (is_extend_pll(state, &hdmi_phy_pll.dev))
30453941 ret = vop2_clk_set_rate(&hdmi_phy_pll, dclk_rate * 1000);
30463942 else
3047
- ret = vop2_clk_set_rate(&dclk, dclk_rate * 1000);
3943
+ ret = vop2_clk_set_rate(&cstate->dclk, dclk_rate * 1000);
30483944 }
30493945
30503946 if (IS_ERR_VALUE(ret)) {
....@@ -3053,7 +3949,11 @@
30533949 return ret;
30543950 } else {
30553951 dclk_div_factor = mode->clock / dclk_rate;
3056
- mode->crtc_clock = ret * dclk_div_factor / 1000;
3952
+ if (vop2->version == VOP_VERSION_RK3528 &&
3953
+ conn_state->output_if & VOP_OUTPUT_IF_BT656)
3954
+ mode->crtc_clock = ret / 4 / 1000;
3955
+ else
3956
+ mode->crtc_clock = ret * dclk_div_factor / 1000;
30573957 printf("VP%d set crtc_clock to %dKHz\n", cstate->crtc_id, mode->crtc_clock);
30583958 }
30593959
....@@ -3061,6 +3961,9 @@
30613961 RK3568_DSP_LINE_FLAG_NUM0_SHIFT, act_end, false);
30623962 vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK,
30633963 RK3568_DSP_LINE_FLAG_NUM1_SHIFT, act_end, false);
3964
+
3965
+ if (cstate->mcu_timing.mcu_pix_total)
3966
+ vop3_mcu_mode_setup(state);
30643967
30653968 return 0;
30663969 }
....@@ -3071,71 +3974,129 @@
30713974 {
30723975 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
30733976 uint16_t hscl_filter_mode, vscl_filter_mode;
3074
- uint8_t gt2 = 0, gt4 = 0;
3977
+ uint8_t xgt2 = 0, xgt4 = 0;
3978
+ uint8_t ygt2 = 0, ygt4 = 0;
30753979 uint32_t xfac = 0, yfac = 0;
3076
- uint16_t hsu_filter_mode = VOP2_SCALE_UP_BIC;
3077
- uint16_t hsd_filter_mode = VOP2_SCALE_DOWN_BIL;
3078
- uint16_t vsu_filter_mode = VOP2_SCALE_UP_BIL;
3079
- uint16_t vsd_filter_mode = VOP2_SCALE_DOWN_BIL;
30803980 u32 win_offset = win->reg_offset;
3981
+ bool xgt_en = false;
3982
+ bool xavg_en = false;
30813983
3082
- if (src_h >= (4 * dst_h))
3083
- gt4 = 1;
3084
- else if (src_h >= (2 * dst_h))
3085
- gt2 = 1;
3984
+ if (is_vop3(vop2)) {
3985
+ if (src_w >= (4 * dst_w)) {
3986
+ xgt4 = 1;
3987
+ src_w >>= 2;
3988
+ } else if (src_w >= (2 * dst_w)) {
3989
+ xgt2 = 1;
3990
+ src_w >>= 1;
3991
+ }
3992
+ }
30863993
3087
- if (gt4)
3994
+ if (src_h >= (4 * dst_h)) {
3995
+ ygt4 = 1;
30883996 src_h >>= 2;
3089
- else if (gt2)
3997
+ } else if (src_h >= (2 * dst_h)) {
3998
+ ygt2 = 1;
30903999 src_h >>= 1;
4000
+ }
30914001
30924002 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
30934003 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
30944004
30954005 if (yrgb_hor_scl_mode == SCALE_UP)
3096
- hscl_filter_mode = hsu_filter_mode;
4006
+ hscl_filter_mode = win->hsu_filter_mode;
30974007 else
3098
- hscl_filter_mode = hsd_filter_mode;
4008
+ hscl_filter_mode = win->hsd_filter_mode;
30994009
31004010 if (yrgb_ver_scl_mode == SCALE_UP)
3101
- vscl_filter_mode = vsu_filter_mode;
4011
+ vscl_filter_mode = win->vsu_filter_mode;
31024012 else
3103
- vscl_filter_mode = vsd_filter_mode;
4013
+ vscl_filter_mode = win->vsd_filter_mode;
31044014
31054015 /*
31064016 * RK3568 VOP Esmart/Smart dsp_w should be even pixel
31074017 * at scale down mode
31084018 */
3109
- if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) {
4019
+ if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1) && !is_vop3(vop2)) {
31104020 printf("win dst_w[%d] should align as 2 pixel\n", dst_w);
31114021 dst_w += 1;
31124022 }
31134023
3114
- xfac = vop2_scale_factor(yrgb_hor_scl_mode, hscl_filter_mode, src_w, dst_w);
3115
- yfac = vop2_scale_factor(yrgb_ver_scl_mode, vscl_filter_mode, src_h, dst_h);
4024
+ if (is_vop3(vop2)) {
4025
+ xfac = vop3_scale_factor(yrgb_hor_scl_mode, src_w, dst_w, true);
4026
+ yfac = vop3_scale_factor(yrgb_ver_scl_mode, src_h, dst_h, false);
4027
+
4028
+ if (win->hsd_pre_filter_mode == VOP3_PRE_SCALE_DOWN_AVG)
4029
+ xavg_en = xgt2 || xgt4;
4030
+ else
4031
+ xgt_en = xgt2 || xgt4;
4032
+ } else {
4033
+ xfac = vop2_scale_factor(yrgb_hor_scl_mode, hscl_filter_mode, src_w, dst_w);
4034
+ yfac = vop2_scale_factor(yrgb_ver_scl_mode, vscl_filter_mode, src_h, dst_h);
4035
+ }
31164036
31174037 if (win->type == CLUSTER_LAYER) {
31184038 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB + win_offset,
31194039 yfac << 16 | xfac);
31204040
3121
- vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
3122
- YRGB_GT2_MASK, CLUSTER_YRGB_GT2_SHIFT, gt2, false);
3123
- vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
3124
- YRGB_GT4_MASK, CLUSTER_YRGB_GT4_SHIFT, gt4, false);
4041
+ if (is_vop3(vop2)) {
4042
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
4043
+ EN_MASK, CLUSTER_XGT_EN_SHIFT, xgt_en, false);
4044
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
4045
+ EN_MASK, CLUSTER_XAVG_EN_SHIFT, xavg_en, false);
4046
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
4047
+ XGT_MODE_MASK, CLUSTER_XGT_MODE_SHIFT, xgt2 ? 0 : 1, false);
31254048
3126
- vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
3127
- YRGB_XSCL_MODE_MASK, CLUSTER_YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false);
3128
- vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
3129
- YRGB_YSCL_MODE_MASK, CLUSTER_YRGB_YSCL_MODE_SHIFT, yrgb_ver_scl_mode, false);
4049
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
4050
+ YRGB_XSCL_MODE_MASK, RK3528_CLUSTER_YRGB_XSCL_MODE_SHIFT,
4051
+ yrgb_hor_scl_mode, false);
4052
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
4053
+ YRGB_YSCL_MODE_MASK, RK3528_CLUSTER_YRGB_YSCL_MODE_SHIFT,
4054
+ yrgb_ver_scl_mode, false);
4055
+ } else {
4056
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
4057
+ YRGB_XSCL_MODE_MASK, RK3568_CLUSTER_YRGB_XSCL_MODE_SHIFT,
4058
+ yrgb_hor_scl_mode, false);
4059
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
4060
+ YRGB_YSCL_MODE_MASK, RK3568_CLUSTER_YRGB_YSCL_MODE_SHIFT,
4061
+ yrgb_ver_scl_mode, false);
4062
+ }
31304063
4064
+ if (!is_vop3(vop2) || win->vsd_pre_filter_mode == VOP3_PRE_SCALE_DOWN_GT) {
4065
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
4066
+ YRGB_GT2_MASK, CLUSTER_YRGB_GT2_SHIFT, ygt2, false);
4067
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
4068
+ YRGB_GT4_MASK, CLUSTER_YRGB_GT4_SHIFT, ygt4, false);
4069
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
4070
+ AVG2_MASK, CLUSTER_AVG2_SHIFT, 0, false);
4071
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
4072
+ AVG4_MASK, CLUSTER_AVG4_SHIFT, 0, false);
4073
+ } else {
4074
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
4075
+ YRGB_GT2_MASK, CLUSTER_YRGB_GT2_SHIFT, 0, false);
4076
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
4077
+ YRGB_GT4_MASK, CLUSTER_YRGB_GT4_SHIFT, 0, false);
4078
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
4079
+ AVG2_MASK, CLUSTER_AVG2_SHIFT, ygt2, false);
4080
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
4081
+ AVG4_MASK, CLUSTER_AVG4_SHIFT, ygt4, false);
4082
+ }
31314083 } else {
31324084 vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset,
31334085 yfac << 16 | xfac);
31344086
4087
+ if (is_vop3(vop2)) {
4088
+ vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,
4089
+ EN_MASK, ESMART_XGT_EN_SHIFT, xgt_en, false);
4090
+ vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,
4091
+ EN_MASK, ESMART_XAVG_EN_SHIFT, xavg_en, false);
4092
+ vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,
4093
+ XGT_MODE_MASK, ESMART_XGT_MODE_SHIFT, xgt2 ? 0 : 1, false);
4094
+ }
4095
+
31354096 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,
3136
- YRGB_GT2_MASK, YRGB_GT2_SHIFT, gt2, false);
4097
+ YRGB_GT2_MASK, YRGB_GT2_SHIFT, ygt2, false);
31374098 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,
3138
- YRGB_GT4_MASK, YRGB_GT4_SHIFT, gt4, false);
4099
+ YRGB_GT4_MASK, YRGB_GT4_SHIFT, ygt4, false);
31394100
31404101 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset,
31414102 YRGB_XSCL_MODE_MASK, YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false);
....@@ -3172,6 +4133,16 @@
31724133 }
31734134 }
31744135
4136
+static bool vop2_win_dither_up(uint32_t format)
4137
+{
4138
+ switch (format) {
4139
+ case ROCKCHIP_FMT_RGB565:
4140
+ return true;
4141
+ default:
4142
+ return false;
4143
+ }
4144
+}
4145
+
31754146 static void vop2_set_cluster_win(struct display_state *state, struct vop2_win_data *win)
31764147 {
31774148 struct crtc_state *cstate = &state->crtc_state;
....@@ -3193,6 +4164,7 @@
31934164 u32 splice_yrgb_offset = 0;
31944165 u32 win_offset = win->reg_offset;
31954166 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16);
4167
+ bool dither_up;
31964168
31974169 if (win->splice_mode_right) {
31984170 src_w = cstate->right_src_rect.w;
....@@ -3223,11 +4195,17 @@
32234195
32244196 vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h);
32254197
3226
- if (vop2->version == VOP_VERSION_RK3588)
4198
+ if (vop2->version == VOP_VERSION_RK3588 || vop2->version == VOP_VERSION_RK3528 ||
4199
+ vop2->version == VOP_VERSION_RK3562)
32274200 vop2_axi_config(vop2, win);
32284201
32294202 if (y_mirror)
32304203 printf("WARN: y mirror is unsupported by cluster window\n");
4204
+
4205
+ /* rk3588 should set half_blocK_en to 1 in line and tile mode */
4206
+ if (vop2->version == VOP_VERSION_RK3588)
4207
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_AFBCD_CTRL + win_offset,
4208
+ EN_MASK, CLUSTER_AFBCD_HALF_BLOCK_SHIFT, 1, false);
32314209
32324210 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset,
32334211 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format,
....@@ -3242,12 +4220,17 @@
32424220
32434221 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, WIN_EN_SHIFT, 1, false);
32444222
3245
- csc_mode = vop2_convert_csc_mode(conn_state->color_space);
4223
+ csc_mode = vop2_convert_csc_mode(conn_state->color_space, CSC_10BIT_DEPTH);
32464224 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK,
32474225 CLUSTER_RGB2YUV_EN_SHIFT,
32484226 is_yuv_output(conn_state->bus_format), false);
32494227 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, CSC_MODE_MASK,
32504228 CLUSTER_CSC_MODE_SHIFT, csc_mode, false);
4229
+
4230
+ dither_up = vop2_win_dither_up(cstate->format);
4231
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK,
4232
+ CLUSTER_DITHER_UP_EN_SHIFT, dither_up, false);
4233
+
32514234 vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, EN_MASK, CLUSTER_EN_SHIFT, 1, false);
32524235
32534236 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);
....@@ -3274,6 +4257,7 @@
32744257 u32 splice_yrgb_offset = 0;
32754258 u32 win_offset = win->reg_offset;
32764259 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16);
4260
+ bool dither_up;
32774261
32784262 if (win->splice_mode_right) {
32794263 src_w = cstate->right_src_rect.w;
....@@ -3311,9 +4295,14 @@
33114295 else
33124296 y_mirror = 0;
33134297
4298
+ if (is_vop3(vop2))
4299
+ vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, ESMART_LB_SELECT_MASK,
4300
+ ESMART_LB_SELECT_SHIFT, win->scale_engine_num, false);
4301
+
33144302 vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h);
33154303
3316
- if (vop2->version == VOP_VERSION_RK3588)
4304
+ if (vop2->version == VOP_VERSION_RK3588 || vop2->version == VOP_VERSION_RK3528 ||
4305
+ vop2->version == VOP_VERSION_RK3562)
33174306 vop2_axi_config(vop2, win);
33184307
33194308 if (y_mirror)
....@@ -3337,12 +4326,16 @@
33374326 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK,
33384327 WIN_EN_SHIFT, 1, false);
33394328
3340
- csc_mode = vop2_convert_csc_mode(conn_state->color_space);
4329
+ csc_mode = vop2_convert_csc_mode(conn_state->color_space, CSC_10BIT_DEPTH);
33414330 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK,
33424331 RGB2YUV_EN_SHIFT,
33434332 is_yuv_output(conn_state->bus_format), false);
33444333 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK,
33454334 CSC_MODE_SHIFT, csc_mode, false);
4335
+
4336
+ dither_up = vop2_win_dither_up(cstate->format);
4337
+ vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK,
4338
+ REGION0_DITHER_UP_EN_SHIFT, dither_up, false);
33464339
33474340 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);
33484341 }
....@@ -3412,6 +4405,10 @@
34124405 printf("invalid win id %d\n", primary_plane_id);
34134406 return -ENODEV;
34144407 }
4408
+
4409
+ /* ignore some plane register according vop3 esmart lb mode */
4410
+ if (vop3_ignore_plane(vop2, win_data))
4411
+ return -EACCES;
34154412
34164413 if (vop2->version == VOP_VERSION_RK3588) {
34174414 if (vop2_power_domain_on(vop2, win_data->pd_id))
....@@ -3494,6 +4491,10 @@
34944491 if (cstate->dsc_enable)
34954492 vop2_dsc_cfg_done(state);
34964493
4494
+ if (cstate->mcu_timing.mcu_pix_total)
4495
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
4496
+ MCU_HOLD_MODE_SHIFT, 0, false);
4497
+
34974498 return 0;
34984499 }
34994500
....@@ -3570,7 +4571,7 @@
35704571 int vp_id = 0;
35714572 int cursor_plane_id = -1;
35724573
3573
- if (vop_fix_dts)
4574
+ if (vop_fix_dts || vop2->version == VOP_VERSION_RK3528)
35744575 return 0;
35754576
35764577 ofnode_for_each_subnode(vp_node, np_to_ofnode(port_parent_node)) {
....@@ -3638,6 +4639,53 @@
36384639 return 0;
36394640 }
36404641
4642
+static int rockchip_vop2_mode_fixup(struct display_state *state)
4643
+{
4644
+ struct connector_state *conn_state = &state->conn_state;
4645
+ struct drm_display_mode *mode = &conn_state->mode;
4646
+ struct crtc_state *cstate = &state->crtc_state;
4647
+ struct vop2 *vop2 = cstate->private;
4648
+
4649
+ drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
4650
+
4651
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK || conn_state->output_if & VOP_OUTPUT_IF_BT656)
4652
+ mode->crtc_clock *= 2;
4653
+
4654
+ /*
4655
+ * For RK3528, the path of CVBS output is like:
4656
+ * VOP BT656 ENCODER -> CVBS BT656 DECODER -> CVBS ENCODER -> CVBS VDAC
4657
+ * The vop2 dclk should be four times crtc_clock for CVBS sampling
4658
+ * clock needs.
4659
+ */
4660
+ if (vop2->version == VOP_VERSION_RK3528 && conn_state->output_if & VOP_OUTPUT_IF_BT656)
4661
+ mode->crtc_clock *= 4;
4662
+
4663
+ if (cstate->mcu_timing.mcu_pix_total) {
4664
+ if (conn_state->output_mode == ROCKCHIP_OUT_MODE_S888)
4665
+ /*
4666
+ * For serial output_mode rgb3x8, one pixel need 3 cycles.
4667
+ * So dclk should be three times mode clock.
4668
+ */
4669
+ mode->crtc_clock *= 3;
4670
+ else if (conn_state->output_mode == ROCKCHIP_OUT_MODE_S888_DUMMY)
4671
+ /*
4672
+ * For serial output_mode argb4x8, one pixel need 4 cycles.
4673
+ * So dclk should be four times mode clock.
4674
+ */
4675
+ mode->crtc_clock *= 4;
4676
+ }
4677
+
4678
+ if (conn_state->secondary) {
4679
+ mode->crtc_clock *= 2;
4680
+ mode->crtc_hdisplay *= 2;
4681
+ mode->crtc_hsync_start *= 2;
4682
+ mode->crtc_hsync_end *= 2;
4683
+ mode->crtc_htotal *= 2;
4684
+ }
4685
+
4686
+ return 0;
4687
+}
4688
+
36414689 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
36424690
36434691 static int rockchip_vop2_plane_check(struct display_state *state)
....@@ -3665,10 +4713,526 @@
36654713 if (hscale < 0 || vscale < 0) {
36664714 printf("ERROR: VP%d %s: scale factor is out of range\n", cstate->crtc_id, win_data->name);
36674715 return -ERANGE;
4716
+ }
4717
+
4718
+ return 0;
4719
+}
4720
+
4721
+static int rockchip_vop2_apply_soft_te(struct display_state *state)
4722
+{
4723
+ __maybe_unused struct connector_state *conn_state = &state->conn_state;
4724
+ struct crtc_state *cstate = &state->crtc_state;
4725
+ struct vop2 *vop2 = cstate->private;
4726
+ u32 vp_offset = (cstate->crtc_id * 0x100);
4727
+ int val = 0;
4728
+ int ret = 0;
4729
+
4730
+ ret = readl_poll_timeout(vop2->regs + RK3568_VP0_MIPI_CTRL + vp_offset, val,
4731
+ (val >> EDPI_WMS_FS) & 0x1, 50 * 1000);
4732
+ if (!ret) {
4733
+#ifndef CONFIG_SPL_BUILD
4734
+ ret = readx_poll_timeout(dm_gpio_get_value, conn_state->te_gpio, val,
4735
+ !val, 50 * 1000);
4736
+ if (!ret) {
4737
+ ret = readx_poll_timeout(dm_gpio_get_value, conn_state->te_gpio, val,
4738
+ val, 50 * 1000);
4739
+ if (!ret) {
4740
+ vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
4741
+ EN_MASK, EDPI_WMS_FS, 1, false);
4742
+ } else {
4743
+ printf("ERROR: vp%d wait for active TE signal timeout\n",
4744
+ cstate->crtc_id);
4745
+ return ret;
4746
+ }
4747
+ } else {
4748
+ printf("ERROR: vp%d TE signal maybe always high\n", cstate->crtc_id);
4749
+ return ret;
4750
+ }
4751
+#endif
4752
+ } else {
4753
+ printf("ERROR: vp%d wait vop2 frame start timeout in hold mode\n", cstate->crtc_id);
4754
+ return ret;
36684755 }
36694756
36704757 return 0;
36714758 }
4759
+
4760
+static int rockchip_vop2_regs_dump(struct display_state *state)
4761
+{
4762
+ struct crtc_state *cstate = &state->crtc_state;
4763
+ struct vop2 *vop2 = cstate->private;
4764
+ const struct vop2_data *vop2_data = vop2->data;
4765
+ const struct vop2_dump_regs *regs = vop2_data->dump_regs;
4766
+ u32 n, i, j;
4767
+ u32 base;
4768
+
4769
+ if (!cstate->crtc->active)
4770
+ return -EINVAL;
4771
+
4772
+ n = vop2_data->dump_regs_size;
4773
+ for (i = 0; i < n; i++) {
4774
+ base = regs[i].offset;
4775
+ printf("\n%s:\n", regs[i].name);
4776
+ for (j = 0; j < 68;) {
4777
+ printf("%08lx: %08x %08x %08x %08x\n", (uintptr_t)vop2->regs + base + j * 4,
4778
+ vop2_readl(vop2, base + (4 * j)),
4779
+ vop2_readl(vop2, base + (4 * (j + 1))),
4780
+ vop2_readl(vop2, base + (4 * (j + 2))),
4781
+ vop2_readl(vop2, base + (4 * (j + 3))));
4782
+ j += 4;
4783
+ }
4784
+ }
4785
+
4786
+ return 0;
4787
+}
4788
+
4789
+static int rockchip_vop2_active_regs_dump(struct display_state *state)
4790
+{
4791
+ struct crtc_state *cstate = &state->crtc_state;
4792
+ struct vop2 *vop2 = cstate->private;
4793
+ const struct vop2_data *vop2_data = vop2->data;
4794
+ const struct vop2_dump_regs *regs = vop2_data->dump_regs;
4795
+ u32 n, i, j;
4796
+ u32 base;
4797
+ bool enable_state;
4798
+
4799
+ if (!cstate->crtc->active)
4800
+ return -EINVAL;
4801
+
4802
+ n = vop2_data->dump_regs_size;
4803
+ for (i = 0; i < n; i++) {
4804
+ if (regs[i].state_mask) {
4805
+ enable_state = (vop2_readl(vop2, regs[i].state_base) >> regs[i].state_shift) &
4806
+ regs[i].state_mask;
4807
+ if (enable_state != regs[i].enable_state)
4808
+ continue;
4809
+ }
4810
+
4811
+ base = regs[i].offset;
4812
+ printf("\n%s:\n", regs[i].name);
4813
+ for (j = 0; j < 68;) {
4814
+ printf("%08lx: %08x %08x %08x %08x\n", (uintptr_t)vop2->regs + base + j * 4,
4815
+ vop2_readl(vop2, base + (4 * j)),
4816
+ vop2_readl(vop2, base + (4 * (j + 1))),
4817
+ vop2_readl(vop2, base + (4 * (j + 2))),
4818
+ vop2_readl(vop2, base + (4 * (j + 3))));
4819
+ j += 4;
4820
+ }
4821
+ }
4822
+
4823
+ return 0;
4824
+}
4825
+
4826
+static struct vop2_dump_regs rk3528_dump_regs[] = {
4827
+ { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
4828
+ { RK3528_OVL_SYS, "OVL_SYS", 0, 0, 0, 0 },
4829
+ { RK3528_OVL_PORT0_CTRL, "OVL_VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
4830
+ { RK3528_OVL_PORT1_CTRL, "OVL_VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
4831
+ { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
4832
+ { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
4833
+ { RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0, 1 },
4834
+ { RK3568_ESMART0_CTRL0, "Esmart0", RK3568_ESMART0_REGION0_CTRL, 0x1, 0, 1 },
4835
+ { RK3568_ESMART1_CTRL0, "Esmart1", RK3568_ESMART1_REGION0_CTRL, 0x1, 0, 1 },
4836
+ { RK3568_SMART0_CTRL0, "Esmart2", RK3568_SMART0_CTRL0, 0x1, 0, 1 },
4837
+ { RK3568_SMART1_CTRL0, "Esmart3", RK3568_SMART1_CTRL0, 0x1, 0, 1 },
4838
+ { RK3528_HDR_LUT_CTRL, "HDR", 0, 0, 0, 0 },
4839
+ { RK3528_ACM_CTRL, "ACM", RK3528_ACM_CTRL, 0x1, 0, 1},
4840
+};
4841
+
4842
+static u8 rk3528_vp_primary_plane_order[ROCKCHIP_VOP2_LAYER_MAX] = {
4843
+ ROCKCHIP_VOP2_ESMART0,
4844
+ ROCKCHIP_VOP2_ESMART1,
4845
+ ROCKCHIP_VOP2_ESMART2,
4846
+ ROCKCHIP_VOP2_ESMART3,
4847
+};
4848
+
4849
+static struct vop2_plane_table rk3528_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = {
4850
+ {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER},
4851
+ {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER},
4852
+ {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER},
4853
+ {ROCKCHIP_VOP2_ESMART2, ESMART_LAYER},
4854
+ {ROCKCHIP_VOP2_ESMART3, ESMART_LAYER},
4855
+};
4856
+
4857
+static struct vop2_vp_plane_mask rk3528_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = {
4858
+ { /* one display policy for hdmi */
4859
+ {/* main display */
4860
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
4861
+ .attached_layers_nr = 4,
4862
+ .attached_layers = {
4863
+ ROCKCHIP_VOP2_CLUSTER0,
4864
+ ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_ESMART2
4865
+ },
4866
+ },
4867
+ {/* second display */},
4868
+ {/* third display */},
4869
+ {/* fourth display */},
4870
+ },
4871
+
4872
+ { /* two display policy */
4873
+ {/* main display */
4874
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
4875
+ .attached_layers_nr = 3,
4876
+ .attached_layers = {
4877
+ ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART1
4878
+ },
4879
+ },
4880
+
4881
+ {/* second display */
4882
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART3,
4883
+ .attached_layers_nr = 2,
4884
+ .attached_layers = {
4885
+ ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3
4886
+ },
4887
+ },
4888
+ {/* third display */},
4889
+ {/* fourth display */},
4890
+ },
4891
+
4892
+ { /* one display policy for cvbs */
4893
+ {/* main display */
4894
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART3,
4895
+ .attached_layers_nr = 2,
4896
+ .attached_layers = {
4897
+ ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3
4898
+ },
4899
+ },
4900
+ {/* second display */},
4901
+ {/* third display */},
4902
+ {/* fourth display */},
4903
+ },
4904
+
4905
+ {/* reserved */},
4906
+};
4907
+
4908
+static struct vop2_win_data rk3528_win_data[5] = {
4909
+ {
4910
+ .name = "Esmart0",
4911
+ .phys_id = ROCKCHIP_VOP2_ESMART0,
4912
+ .type = ESMART_LAYER,
4913
+ .win_sel_port_offset = 8,
4914
+ .layer_sel_win_id = { 1, 0xff, 0xff, 0xff },
4915
+ .reg_offset = 0,
4916
+ .axi_id = 0,
4917
+ .axi_yrgb_id = 0x06,
4918
+ .axi_uv_id = 0x07,
4919
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
4920
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
4921
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
4922
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
4923
+ .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
4924
+ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT, /* gt only */
4925
+ .max_upscale_factor = 8,
4926
+ .max_downscale_factor = 8,
4927
+ },
4928
+
4929
+ {
4930
+ .name = "Esmart1",
4931
+ .phys_id = ROCKCHIP_VOP2_ESMART1,
4932
+ .type = ESMART_LAYER,
4933
+ .win_sel_port_offset = 10,
4934
+ .layer_sel_win_id = { 2, 0xff, 0xff, 0xff },
4935
+ .reg_offset = 0x200,
4936
+ .axi_id = 0,
4937
+ .axi_yrgb_id = 0x08,
4938
+ .axi_uv_id = 0x09,
4939
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
4940
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
4941
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
4942
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
4943
+ .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
4944
+ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT, /* gt only */
4945
+ .max_upscale_factor = 8,
4946
+ .max_downscale_factor = 8,
4947
+ },
4948
+
4949
+ {
4950
+ .name = "Esmart2",
4951
+ .phys_id = ROCKCHIP_VOP2_ESMART2,
4952
+ .type = ESMART_LAYER,
4953
+ .win_sel_port_offset = 12,
4954
+ .layer_sel_win_id = { 3, 0, 0xff, 0xff },
4955
+ .reg_offset = 0x400,
4956
+ .axi_id = 0,
4957
+ .axi_yrgb_id = 0x0a,
4958
+ .axi_uv_id = 0x0b,
4959
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
4960
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
4961
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
4962
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
4963
+ .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
4964
+ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT, /* gt only */
4965
+ .max_upscale_factor = 8,
4966
+ .max_downscale_factor = 8,
4967
+ },
4968
+
4969
+ {
4970
+ .name = "Esmart3",
4971
+ .phys_id = ROCKCHIP_VOP2_ESMART3,
4972
+ .type = ESMART_LAYER,
4973
+ .win_sel_port_offset = 14,
4974
+ .layer_sel_win_id = { 0xff, 1, 0xff, 0xff },
4975
+ .reg_offset = 0x600,
4976
+ .axi_id = 0,
4977
+ .axi_yrgb_id = 0x0c,
4978
+ .axi_uv_id = 0x0d,
4979
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
4980
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
4981
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
4982
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
4983
+ .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
4984
+ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT, /* gt only */
4985
+ .max_upscale_factor = 8,
4986
+ .max_downscale_factor = 8,
4987
+ },
4988
+
4989
+ {
4990
+ .name = "Cluster0",
4991
+ .phys_id = ROCKCHIP_VOP2_CLUSTER0,
4992
+ .type = CLUSTER_LAYER,
4993
+ .win_sel_port_offset = 0,
4994
+ .layer_sel_win_id = { 0, 0xff, 0xff, 0xff },
4995
+ .reg_offset = 0,
4996
+ .axi_id = 0,
4997
+ .axi_yrgb_id = 0x02,
4998
+ .axi_uv_id = 0x03,
4999
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5000
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5001
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5002
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5003
+ .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
5004
+ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
5005
+ .max_upscale_factor = 8,
5006
+ .max_downscale_factor = 8,
5007
+ },
5008
+};
5009
+
5010
+static struct vop2_vp_data rk3528_vp_data[2] = {
5011
+ {
5012
+ .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN | VOP_FEATURE_POST_ACM |
5013
+ VOP_FEATURE_POST_CSC,
5014
+ .max_output = {4096, 4096},
5015
+ .layer_mix_dly = 6,
5016
+ .hdr_mix_dly = 2,
5017
+ .win_dly = 8,
5018
+ },
5019
+ {
5020
+ .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
5021
+ .max_output = {1920, 1080},
5022
+ .layer_mix_dly = 2,
5023
+ .hdr_mix_dly = 0,
5024
+ .win_dly = 8,
5025
+ },
5026
+};
5027
+
5028
+const struct vop2_data rk3528_vop = {
5029
+ .version = VOP_VERSION_RK3528,
5030
+ .nr_vps = 2,
5031
+ .vp_data = rk3528_vp_data,
5032
+ .win_data = rk3528_win_data,
5033
+ .plane_mask = rk3528_vp_plane_mask[0],
5034
+ .plane_table = rk3528_plane_table,
5035
+ .vp_primary_plane_order = rk3528_vp_primary_plane_order,
5036
+ .nr_layers = 5,
5037
+ .nr_mixers = 3,
5038
+ .nr_gammas = 2,
5039
+ .esmart_lb_mode = VOP3_ESMART_4K_2K_2K_MODE,
5040
+ .dump_regs = rk3528_dump_regs,
5041
+ .dump_regs_size = ARRAY_SIZE(rk3528_dump_regs),
5042
+};
5043
+
5044
+static struct vop2_dump_regs rk3562_dump_regs[] = {
5045
+ { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
5046
+ { RK3528_OVL_SYS, "OVL_SYS", 0, 0, 0, 0 },
5047
+ { RK3528_OVL_PORT0_CTRL, "OVL_VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
5048
+ { RK3528_OVL_PORT1_CTRL, "OVL_VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
5049
+ { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
5050
+ { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
5051
+ { RK3568_ESMART0_CTRL0, "Esmart0", RK3568_ESMART0_REGION0_CTRL, 0x1, 0, 1 },
5052
+ { RK3568_ESMART1_CTRL0, "Esmart1", RK3568_ESMART1_REGION0_CTRL, 0x1, 0, 1 },
5053
+ { RK3568_SMART0_CTRL0, "Esmart2", RK3568_SMART0_CTRL0, 0x1, 0, 1 },
5054
+ { RK3568_SMART1_CTRL0, "Esmart3", RK3568_SMART1_CTRL0, 0x1, 0, 1 },
5055
+};
5056
+
5057
+static u8 rk3562_vp_primary_plane_order[ROCKCHIP_VOP2_LAYER_MAX] = {
5058
+ ROCKCHIP_VOP2_ESMART0,
5059
+ ROCKCHIP_VOP2_ESMART1,
5060
+ ROCKCHIP_VOP2_ESMART2,
5061
+ ROCKCHIP_VOP2_ESMART3,
5062
+};
5063
+
5064
+static struct vop2_plane_table rk3562_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = {
5065
+ {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER},
5066
+ {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER},
5067
+ {ROCKCHIP_VOP2_ESMART2, ESMART_LAYER},
5068
+ {ROCKCHIP_VOP2_ESMART3, ESMART_LAYER},
5069
+};
5070
+
5071
+static struct vop2_vp_plane_mask rk3562_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = {
5072
+ { /* one display policy for hdmi */
5073
+ {/* main display */
5074
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
5075
+ .attached_layers_nr = 4,
5076
+ .attached_layers = {
5077
+ ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART1,
5078
+ ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3
5079
+ },
5080
+ },
5081
+ {/* second display */},
5082
+ {/* third display */},
5083
+ {/* fourth display */},
5084
+ },
5085
+
5086
+ { /* two display policy */
5087
+ {/* main display */
5088
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
5089
+ .attached_layers_nr = 2,
5090
+ .attached_layers = {
5091
+ ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART1
5092
+ },
5093
+ },
5094
+
5095
+ {/* second display */
5096
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART2,
5097
+ .attached_layers_nr = 2,
5098
+ .attached_layers = {
5099
+ ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3
5100
+ },
5101
+ },
5102
+ {/* third display */},
5103
+ {/* fourth display */},
5104
+ },
5105
+
5106
+ {/* reserved */},
5107
+};
5108
+
5109
+static struct vop2_win_data rk3562_win_data[4] = {
5110
+ {
5111
+ .name = "Esmart0",
5112
+ .phys_id = ROCKCHIP_VOP2_ESMART0,
5113
+ .type = ESMART_LAYER,
5114
+ .win_sel_port_offset = 8,
5115
+ .layer_sel_win_id = { 0, 0, 0xff, 0xff },
5116
+ .reg_offset = 0,
5117
+ .axi_id = 0,
5118
+ .axi_yrgb_id = 0x02,
5119
+ .axi_uv_id = 0x03,
5120
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5121
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5122
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5123
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5124
+ .max_upscale_factor = 8,
5125
+ .max_downscale_factor = 8,
5126
+ },
5127
+
5128
+ {
5129
+ .name = "Esmart1",
5130
+ .phys_id = ROCKCHIP_VOP2_ESMART1,
5131
+ .type = ESMART_LAYER,
5132
+ .win_sel_port_offset = 10,
5133
+ .layer_sel_win_id = { 1, 1, 0xff, 0xff },
5134
+ .reg_offset = 0x200,
5135
+ .axi_id = 0,
5136
+ .axi_yrgb_id = 0x04,
5137
+ .axi_uv_id = 0x05,
5138
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5139
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5140
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5141
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5142
+ .max_upscale_factor = 8,
5143
+ .max_downscale_factor = 8,
5144
+ },
5145
+
5146
+ {
5147
+ .name = "Esmart2",
5148
+ .phys_id = ROCKCHIP_VOP2_ESMART2,
5149
+ .type = ESMART_LAYER,
5150
+ .win_sel_port_offset = 12,
5151
+ .layer_sel_win_id = { 2, 2, 0xff, 0xff },
5152
+ .reg_offset = 0x400,
5153
+ .axi_id = 0,
5154
+ .axi_yrgb_id = 0x06,
5155
+ .axi_uv_id = 0x07,
5156
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5157
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5158
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5159
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5160
+ .max_upscale_factor = 8,
5161
+ .max_downscale_factor = 8,
5162
+ },
5163
+
5164
+ {
5165
+ .name = "Esmart3",
5166
+ .phys_id = ROCKCHIP_VOP2_ESMART3,
5167
+ .type = ESMART_LAYER,
5168
+ .win_sel_port_offset = 14,
5169
+ .layer_sel_win_id = { 3, 3, 0xff, 0xff },
5170
+ .reg_offset = 0x600,
5171
+ .axi_id = 0,
5172
+ .axi_yrgb_id = 0x08,
5173
+ .axi_uv_id = 0x0d,
5174
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5175
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5176
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5177
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5178
+ .max_upscale_factor = 8,
5179
+ .max_downscale_factor = 8,
5180
+ },
5181
+};
5182
+
5183
+static struct vop2_vp_data rk3562_vp_data[2] = {
5184
+ {
5185
+ .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
5186
+ .max_output = {2048, 4096},
5187
+ .win_dly = 8,
5188
+ .layer_mix_dly = 8,
5189
+ },
5190
+ {
5191
+ .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
5192
+ .max_output = {2048, 1080},
5193
+ .win_dly = 8,
5194
+ .layer_mix_dly = 8,
5195
+ },
5196
+};
5197
+
5198
+const struct vop2_data rk3562_vop = {
5199
+ .version = VOP_VERSION_RK3562,
5200
+ .nr_vps = 2,
5201
+ .vp_data = rk3562_vp_data,
5202
+ .win_data = rk3562_win_data,
5203
+ .plane_mask = rk3562_vp_plane_mask[0],
5204
+ .plane_table = rk3562_plane_table,
5205
+ .vp_primary_plane_order = rk3562_vp_primary_plane_order,
5206
+ .nr_layers = 4,
5207
+ .nr_mixers = 3,
5208
+ .nr_gammas = 2,
5209
+ .esmart_lb_mode = VOP3_ESMART_2K_2K_2K_2K_MODE,
5210
+ .dump_regs = rk3562_dump_regs,
5211
+ .dump_regs_size = ARRAY_SIZE(rk3562_dump_regs),
5212
+};
5213
+
5214
+static struct vop2_dump_regs rk3568_dump_regs[] = {
5215
+ { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
5216
+ { RK3568_OVL_CTRL, "OVL", 0, 0, 0, 0 },
5217
+ { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
5218
+ { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
5219
+ { RK3568_VP2_DSP_CTRL, "VP2", RK3568_VP2_DSP_CTRL, 0x1, 31, 0 },
5220
+ { RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0, 1 },
5221
+ { RK3568_CLUSTER1_WIN0_CTRL0, "Cluster1", RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 0, 1 },
5222
+ { RK3568_ESMART0_CTRL0, "Esmart0", RK3568_ESMART0_REGION0_CTRL, 0x1, 0, 1 },
5223
+ { RK3568_ESMART1_CTRL0, "Esmart1", RK3568_ESMART1_REGION0_CTRL, 0x1, 0, 1 },
5224
+ { RK3568_SMART0_CTRL0, "Smart0", RK3568_SMART0_REGION0_CTRL, 0x1, 0, 1 },
5225
+ { RK3568_SMART1_CTRL0, "Smart1", RK3568_SMART1_REGION0_CTRL, 0x1, 0, 1 },
5226
+ { RK3568_HDR_LUT_CTRL, "HDR", 0, 0, 0, 0 },
5227
+};
5228
+
5229
+static u8 rk3568_vp_primary_plane_order[ROCKCHIP_VOP2_LAYER_MAX] = {
5230
+ ROCKCHIP_VOP2_SMART0,
5231
+ ROCKCHIP_VOP2_SMART1,
5232
+ ROCKCHIP_VOP2_ESMART0,
5233
+ ROCKCHIP_VOP2_ESMART1,
5234
+};
5235
+
36725236 static struct vop2_plane_table rk356x_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = {
36735237 {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER},
36745238 {ROCKCHIP_VOP2_CLUSTER1, CLUSTER_LAYER},
....@@ -3748,8 +5312,12 @@
37485312 .phys_id = ROCKCHIP_VOP2_CLUSTER0,
37495313 .type = CLUSTER_LAYER,
37505314 .win_sel_port_offset = 0,
3751
- .layer_sel_win_id = 0,
5315
+ .layer_sel_win_id = { 0, 0, 0, 0xff },
37525316 .reg_offset = 0,
5317
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5318
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5319
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5320
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
37535321 .max_upscale_factor = 4,
37545322 .max_downscale_factor = 4,
37555323 },
....@@ -3759,8 +5327,12 @@
37595327 .phys_id = ROCKCHIP_VOP2_CLUSTER1,
37605328 .type = CLUSTER_LAYER,
37615329 .win_sel_port_offset = 1,
3762
- .layer_sel_win_id = 1,
5330
+ .layer_sel_win_id = { 1, 1, 1, 0xff },
37635331 .reg_offset = 0x200,
5332
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5333
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5334
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5335
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
37645336 .max_upscale_factor = 4,
37655337 .max_downscale_factor = 4,
37665338 },
....@@ -3770,8 +5342,12 @@
37705342 .phys_id = ROCKCHIP_VOP2_ESMART0,
37715343 .type = ESMART_LAYER,
37725344 .win_sel_port_offset = 4,
3773
- .layer_sel_win_id = 2,
5345
+ .layer_sel_win_id = { 2, 2, 2, 0xff },
37745346 .reg_offset = 0,
5347
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5348
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5349
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5350
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
37755351 .max_upscale_factor = 8,
37765352 .max_downscale_factor = 8,
37775353 },
....@@ -3781,8 +5357,12 @@
37815357 .phys_id = ROCKCHIP_VOP2_ESMART1,
37825358 .type = ESMART_LAYER,
37835359 .win_sel_port_offset = 5,
3784
- .layer_sel_win_id = 6,
5360
+ .layer_sel_win_id = { 6, 6, 6, 0xff },
37855361 .reg_offset = 0x200,
5362
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5363
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5364
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5365
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
37865366 .max_upscale_factor = 8,
37875367 .max_downscale_factor = 8,
37885368 },
....@@ -3792,8 +5372,12 @@
37925372 .phys_id = ROCKCHIP_VOP2_SMART0,
37935373 .type = SMART_LAYER,
37945374 .win_sel_port_offset = 6,
3795
- .layer_sel_win_id = 3,
5375
+ .layer_sel_win_id = { 3, 3, 3, 0xff },
37965376 .reg_offset = 0x400,
5377
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5378
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5379
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5380
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
37975381 .max_upscale_factor = 8,
37985382 .max_downscale_factor = 8,
37995383 },
....@@ -3803,8 +5387,12 @@
38035387 .phys_id = ROCKCHIP_VOP2_SMART1,
38045388 .type = SMART_LAYER,
38055389 .win_sel_port_offset = 7,
3806
- .layer_sel_win_id = 7,
5390
+ .layer_sel_win_id = { 7, 7, 7, 0xff },
38075391 .reg_offset = 0x600,
5392
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5393
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5394
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5395
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
38085396 .max_upscale_factor = 8,
38095397 .max_downscale_factor = 8,
38105398 },
....@@ -3835,9 +5423,23 @@
38355423 .win_data = rk3568_win_data,
38365424 .plane_mask = rk356x_vp_plane_mask[0],
38375425 .plane_table = rk356x_plane_table,
5426
+ .vp_primary_plane_order = rk3568_vp_primary_plane_order,
38385427 .nr_layers = 6,
38395428 .nr_mixers = 5,
38405429 .nr_gammas = 1,
5430
+ .dump_regs = rk3568_dump_regs,
5431
+ .dump_regs_size = ARRAY_SIZE(rk3568_dump_regs),
5432
+};
5433
+
5434
+static u8 rk3588_vp_primary_plane_order[ROCKCHIP_VOP2_LAYER_MAX] = {
5435
+ ROCKCHIP_VOP2_ESMART0,
5436
+ ROCKCHIP_VOP2_ESMART1,
5437
+ ROCKCHIP_VOP2_ESMART2,
5438
+ ROCKCHIP_VOP2_ESMART3,
5439
+ ROCKCHIP_VOP2_CLUSTER0,
5440
+ ROCKCHIP_VOP2_CLUSTER1,
5441
+ ROCKCHIP_VOP2_CLUSTER2,
5442
+ ROCKCHIP_VOP2_CLUSTER3,
38415443 };
38425444
38435445 static struct vop2_plane_table rk3588_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = {
....@@ -3851,10 +5453,28 @@
38515453 {ROCKCHIP_VOP2_ESMART3, ESMART_LAYER},
38525454 };
38535455
5456
+static struct vop2_dump_regs rk3588_dump_regs[] = {
5457
+ { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
5458
+ { RK3568_OVL_CTRL, "OVL", 0, 0, 0, 0 },
5459
+ { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
5460
+ { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
5461
+ { RK3568_VP2_DSP_CTRL, "VP2", RK3568_VP2_DSP_CTRL, 0x1, 31, 0 },
5462
+ { RK3588_VP3_DSP_CTRL, "VP3", RK3588_VP3_DSP_CTRL, 0x1, 31, 0 },
5463
+ { RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0, 1 },
5464
+ { RK3568_CLUSTER1_WIN0_CTRL0, "Cluster1", RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 0, 1 },
5465
+ { RK3588_CLUSTER2_WIN0_CTRL0, "Cluster2", RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 0, 1 },
5466
+ { RK3588_CLUSTER3_WIN0_CTRL0, "Cluster3", RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 0, 1 },
5467
+ { RK3568_ESMART0_CTRL0, "Esmart0", RK3568_ESMART0_REGION0_CTRL, 0x1, 0, 1 },
5468
+ { RK3568_ESMART1_CTRL0, "Esmart1", RK3568_ESMART1_REGION0_CTRL, 0x1, 0, 1 },
5469
+ { RK3568_SMART0_CTRL0, "Esmart2", RK3568_SMART0_REGION0_CTRL, 0x1, 0, 1 },
5470
+ { RK3568_SMART1_CTRL0, "Esmart3", RK3568_SMART1_REGION0_CTRL, 0x1, 0, 1 },
5471
+ { RK3568_HDR_LUT_CTRL, "HDR", 0, 0, 0, 0 },
5472
+};
5473
+
38545474 static struct vop2_vp_plane_mask rk3588_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = {
38555475 { /* one display policy */
38565476 {/* main display */
3857
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0,
5477
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
38585478 .attached_layers_nr = 8,
38595479 .attached_layers = {
38605480 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART2,
....@@ -3869,7 +5489,7 @@
38695489
38705490 { /* two display policy */
38715491 {/* main display */
3872
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0,
5492
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
38735493 .attached_layers_nr = 4,
38745494 .attached_layers = {
38755495 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0,
....@@ -3878,7 +5498,7 @@
38785498 },
38795499
38805500 {/* second display */
3881
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2,
5501
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART2,
38825502 .attached_layers_nr = 4,
38835503 .attached_layers = {
38845504 ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2,
....@@ -3891,7 +5511,7 @@
38915511
38925512 { /* three display policy */
38935513 {/* main display */
3894
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0,
5514
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
38955515 .attached_layers_nr = 3,
38965516 .attached_layers = {
38975517 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART0
....@@ -3899,7 +5519,7 @@
38995519 },
39005520
39015521 {/* second display */
3902
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2,
5522
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART1,
39035523 .attached_layers_nr = 3,
39045524 .attached_layers = {
39055525 ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART1
....@@ -3917,25 +5537,25 @@
39175537
39185538 { /* four display policy */
39195539 {/* main display */
3920
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0,
5540
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
39215541 .attached_layers_nr = 2,
39225542 .attached_layers = { ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0 },
39235543 },
39245544
39255545 {/* second display */
3926
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER1,
5546
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART1,
39275547 .attached_layers_nr = 2,
39285548 .attached_layers = { ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1 },
39295549 },
39305550
39315551 {/* third display */
3932
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2,
5552
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART2,
39335553 .attached_layers_nr = 2,
39345554 .attached_layers = { ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2 },
39355555 },
39365556
39375557 {/* fourth display */
3938
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER3,
5558
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART3,
39395559 .attached_layers_nr = 2,
39405560 .attached_layers = { ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 },
39415561 },
....@@ -3950,12 +5570,16 @@
39505570 .splice_win_id = ROCKCHIP_VOP2_CLUSTER1,
39515571 .type = CLUSTER_LAYER,
39525572 .win_sel_port_offset = 0,
3953
- .layer_sel_win_id = 0,
5573
+ .layer_sel_win_id = { 0, 0, 0, 0 },
39545574 .reg_offset = 0,
39555575 .axi_id = 0,
39565576 .axi_yrgb_id = 2,
39575577 .axi_uv_id = 3,
39585578 .pd_id = VOP2_PD_CLUSTER0,
5579
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5580
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5581
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5582
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
39595583 .max_upscale_factor = 4,
39605584 .max_downscale_factor = 4,
39615585 },
....@@ -3965,12 +5589,16 @@
39655589 .phys_id = ROCKCHIP_VOP2_CLUSTER1,
39665590 .type = CLUSTER_LAYER,
39675591 .win_sel_port_offset = 1,
3968
- .layer_sel_win_id = 1,
5592
+ .layer_sel_win_id = { 1, 1, 1, 1 },
39695593 .reg_offset = 0x200,
39705594 .axi_id = 0,
39715595 .axi_yrgb_id = 6,
39725596 .axi_uv_id = 7,
39735597 .pd_id = VOP2_PD_CLUSTER1,
5598
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5599
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5600
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5601
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
39745602 .max_upscale_factor = 4,
39755603 .max_downscale_factor = 4,
39765604 },
....@@ -3981,12 +5609,16 @@
39815609 .splice_win_id = ROCKCHIP_VOP2_CLUSTER3,
39825610 .type = CLUSTER_LAYER,
39835611 .win_sel_port_offset = 2,
3984
- .layer_sel_win_id = 4,
5612
+ .layer_sel_win_id = { 4, 4, 4, 4 },
39855613 .reg_offset = 0x400,
39865614 .axi_id = 1,
39875615 .axi_yrgb_id = 2,
39885616 .axi_uv_id = 3,
39895617 .pd_id = VOP2_PD_CLUSTER2,
5618
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5619
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5620
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5621
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
39905622 .max_upscale_factor = 4,
39915623 .max_downscale_factor = 4,
39925624 },
....@@ -3996,12 +5628,16 @@
39965628 .phys_id = ROCKCHIP_VOP2_CLUSTER3,
39975629 .type = CLUSTER_LAYER,
39985630 .win_sel_port_offset = 3,
3999
- .layer_sel_win_id = 5,
5631
+ .layer_sel_win_id = { 5, 5, 5, 5 },
40005632 .reg_offset = 0x600,
40015633 .axi_id = 1,
40025634 .axi_yrgb_id = 6,
40035635 .axi_uv_id = 7,
40045636 .pd_id = VOP2_PD_CLUSTER3,
5637
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5638
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5639
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5640
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
40055641 .max_upscale_factor = 4,
40065642 .max_downscale_factor = 4,
40075643 },
....@@ -4012,11 +5648,15 @@
40125648 .splice_win_id = ROCKCHIP_VOP2_ESMART1,
40135649 .type = ESMART_LAYER,
40145650 .win_sel_port_offset = 4,
4015
- .layer_sel_win_id = 2,
5651
+ .layer_sel_win_id = { 2, 2, 2, 2 },
40165652 .reg_offset = 0,
40175653 .axi_id = 0,
40185654 .axi_yrgb_id = 0x0a,
40195655 .axi_uv_id = 0x0b,
5656
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5657
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5658
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5659
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
40205660 .max_upscale_factor = 8,
40215661 .max_downscale_factor = 8,
40225662 },
....@@ -4026,12 +5666,16 @@
40265666 .phys_id = ROCKCHIP_VOP2_ESMART1,
40275667 .type = ESMART_LAYER,
40285668 .win_sel_port_offset = 5,
4029
- .layer_sel_win_id = 3,
5669
+ .layer_sel_win_id = { 3, 3, 3, 3 },
40305670 .reg_offset = 0x200,
40315671 .axi_id = 0,
40325672 .axi_yrgb_id = 0x0c,
40335673 .axi_uv_id = 0x0d,
40345674 .pd_id = VOP2_PD_ESMART,
5675
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5676
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5677
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5678
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
40355679 .max_upscale_factor = 8,
40365680 .max_downscale_factor = 8,
40375681 },
....@@ -4042,12 +5686,16 @@
40425686 .splice_win_id = ROCKCHIP_VOP2_ESMART3,
40435687 .type = ESMART_LAYER,
40445688 .win_sel_port_offset = 6,
4045
- .layer_sel_win_id = 6,
5689
+ .layer_sel_win_id = { 6, 6, 6, 6 },
40465690 .reg_offset = 0x400,
40475691 .axi_id = 1,
40485692 .axi_yrgb_id = 0x0a,
40495693 .axi_uv_id = 0x0b,
40505694 .pd_id = VOP2_PD_ESMART,
5695
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5696
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5697
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5698
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
40515699 .max_upscale_factor = 8,
40525700 .max_downscale_factor = 8,
40535701 },
....@@ -4057,12 +5705,16 @@
40575705 .phys_id = ROCKCHIP_VOP2_ESMART3,
40585706 .type = ESMART_LAYER,
40595707 .win_sel_port_offset = 7,
4060
- .layer_sel_win_id = 7,
5708
+ .layer_sel_win_id = { 7, 7, 7, 7 },
40615709 .reg_offset = 0x600,
40625710 .axi_id = 1,
40635711 .axi_yrgb_id = 0x0c,
40645712 .axi_uv_id = 0x0d,
40655713 .pd_id = VOP2_PD_ESMART,
5714
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
5715
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
5716
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
5717
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
40665718 .max_upscale_factor = 8,
40675719 .max_downscale_factor = 8,
40685720 },
....@@ -4218,6 +5870,7 @@
42185870 .dsc = rk3588_dsc_data,
42195871 .dsc_error_ecw = dsc_ecw,
42205872 .dsc_error_buffer_flow = dsc_buffer_flow,
5873
+ .vp_primary_plane_order = rk3588_vp_primary_plane_order,
42215874 .nr_layers = 8,
42225875 .nr_mixers = 7,
42235876 .nr_gammas = 4,
....@@ -4225,6 +5878,8 @@
42255878 .nr_dscs = 2,
42265879 .nr_dsc_ecw = ARRAY_SIZE(dsc_ecw),
42275880 .nr_dsc_buffer_flow = ARRAY_SIZE(dsc_buffer_flow),
5881
+ .dump_regs = rk3588_dump_regs,
5882
+ .dump_regs_size = ARRAY_SIZE(rk3588_dump_regs),
42285883 };
42295884
42305885 const struct rockchip_crtc_funcs rockchip_vop2_funcs = {
....@@ -4235,7 +5890,12 @@
42355890 .enable = rockchip_vop2_enable,
42365891 .disable = rockchip_vop2_disable,
42375892 .fixup_dts = rockchip_vop2_fixup_dts,
5893
+ .send_mcu_cmd = rockchip_vop2_send_mcu_cmd,
42385894 .check = rockchip_vop2_check,
42395895 .mode_valid = rockchip_vop2_mode_valid,
5896
+ .mode_fixup = rockchip_vop2_mode_fixup,
42405897 .plane_check = rockchip_vop2_plane_check,
5898
+ .regs_dump = rockchip_vop2_regs_dump,
5899
+ .active_regs_dump = rockchip_vop2_active_regs_dump,
5900
+ .apply_soft_te = rockchip_vop2_apply_soft_te,
42415901 };
u-boot/drivers/video/drm/rockchip_vop_reg.c
....@@ -140,6 +140,11 @@
140140
141141 .dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1),
142142 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
143
+ .dsp_bg_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 12),
144
+ .dsp_rb_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 13),
145
+ .dsp_rg_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 14),
146
+ .dsp_delta_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 15),
147
+ .dsp_dummy_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 16),
143148 .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20),
144149 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
145150 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
....@@ -383,6 +388,11 @@
383388 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
384389
385390 .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
391
+ .dsp_bg_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 12),
392
+ .dsp_rb_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 13),
393
+ .dsp_rg_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 14),
394
+ .dsp_delta_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 15),
395
+ .dsp_dummy_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 16),
386396 .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20),
387397 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
388398 .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0),
....@@ -544,6 +554,9 @@
544554 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
545555 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
546556 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
557
+ .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9),
558
+ .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11),
559
+ .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12),
547560 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
548561 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
549562 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
....@@ -642,6 +655,9 @@
642655 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
643656 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
644657 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
658
+ .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9),
659
+ .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11),
660
+ .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12),
645661 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
646662 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
647663 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
....@@ -754,6 +770,9 @@
754770 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
755771 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
756772 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
773
+ .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9),
774
+ .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11),
775
+ .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12),
757776 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
758777 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
759778 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
....@@ -826,6 +845,9 @@
826845 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
827846 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
828847 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
848
+ .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9),
849
+ .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11),
850
+ .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12),
829851 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
830852 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
831853 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
u-boot/drivers/video/drm/rohm-bu18rl82.c
....@@ -47,6 +47,7 @@
4747 (BU18RL82_SWRST_REG | BU18RL82_SWRST_EXCREG | BU18RL82_SWRST_ALL));
4848 if (ret < 0)
4949 printf("failed to reset bu18rl82(%s) ret=%d\n", bus->name, ret);
50
+ mdelay(5);
5051 }
5152
5253 static int bu18rl82_serdes_init_sequence_write(struct bu18rl82_priv *priv)
u-boot/drivers/video/drm/rohm-bu18tl82.c
....@@ -7,6 +7,7 @@
77 #include <dm.h>
88 #include <errno.h>
99 #include <i2c.h>
10
+#include <drm/drm_mipi_dsi.h>
1011 #include <video_bridge.h>
1112 #include <asm/unaligned.h>
1213 #include <linux/media-bus-format.h>
....@@ -31,6 +32,7 @@
3132 struct udevice *power_supply;
3233 struct gpio_desc enable_gpio;
3334 struct serdes_init_seq *serdes_init_seq;
35
+ bool sel_mipi;
3436 };
3537
3638 static void bu18tl82_bridge_reset(struct rockchip_bridge *bridge)
....@@ -216,6 +218,20 @@
216218 return ret;
217219 }
218220
221
+ priv->sel_mipi = dev_read_bool(dev, "sel-mipi");
222
+ if (priv->sel_mipi) {
223
+ struct mipi_dsi_device *device = dev_get_platdata(dev);
224
+
225
+ device->dev = dev;
226
+ device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4);
227
+ device->format = dev_read_u32_default(dev, "dsi,format",
228
+ MIPI_DSI_FMT_RGB888);
229
+ device->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
230
+ MIPI_DSI_MODE_VIDEO_HBP | MIPI_DSI_MODE_LPM |
231
+ MIPI_DSI_MODE_EOT_PACKET;
232
+ device->channel = dev_read_u32_default(dev, "reg", 0);
233
+ }
234
+
219235 bridge = calloc(1, sizeof(*bridge));
220236 if (!bridge)
221237 return -ENOMEM;
....@@ -250,4 +266,5 @@
250266 .of_match = bu18tl82_of_match,
251267 .probe = bu18tl82_probe,
252268 .priv_auto_alloc_size = sizeof(struct bu18tl82_priv),
269
+ .platdata_auto_alloc_size = sizeof(struct mipi_dsi_device),
253270 };
u-boot/drivers/watchdog/rockchip_wdt.c
....@@ -86,7 +86,8 @@
8686
8787 printf("Rockchip watchdog timeout: %lld sec\n", timeout / 1000);
8888
89
- reset_deassert(&priv->rst);
89
+ if (priv->rst.dev)
90
+ reset_deassert(&priv->rst);
9091
9192 rockchip_wdt_reset(dev);
9293 rockchip_wdt_settimeout(timeout, priv);
....@@ -100,8 +101,10 @@
100101 {
101102 struct rockchip_wdt_priv *priv = dev_get_priv(dev);
102103
103
- reset_assert(&priv->rst);
104
- reset_deassert(&priv->rst);
104
+ if (priv->rst.dev) {
105
+ reset_assert(&priv->rst);
106
+ reset_deassert(&priv->rst);
107
+ }
105108
106109 printf("Rockchip watchdog stop\n");
107110
....@@ -133,7 +136,7 @@
133136 ret = reset_get_by_name(dev, "reset", &priv->rst);
134137 if (ret) {
135138 pr_err("reset_get_by_name(reset) failed: %d\n", ret);
136
- return ret;
139
+ priv->rst.dev = NULL;
137140 }
138141
139142 ret = clk_get_by_index(dev, 0, &priv->clk);
u-boot/env/envf.c
....@@ -44,16 +44,6 @@
4444 #endif
4545
4646 #ifdef CONFIG_DM_MMC
47
-static int pmbr_part_valid(struct partition *part)
48
-{
49
- if (part->sys_ind == EFI_PMBR_OSTYPE_EFI_GPT &&
50
- get_unaligned_le32(&part->start_sect) == 1UL) {
51
- return 1;
52
- }
53
-
54
- return 0;
55
-}
56
-
5747 static int is_pmbr_valid(legacy_mbr * mbr)
5848 {
5949 int i = 0;
....@@ -62,10 +52,10 @@
6252 return 0;
6353
6454 for (i = 0; i < 4; i++) {
65
- if (pmbr_part_valid(&mbr->partition_record[i])) {
55
+ if (mbr->partition_record[i].sys_ind == 0xc)
6656 return 1;
67
- }
6857 }
58
+
6959 return 0;
7060 }
7161
....@@ -76,10 +66,10 @@
7666 /* Read legacy MBR from block 0 and validate it */
7767 if ((blk_dread(dev_desc, 0, 1, (ulong *)legacymbr) != 1)
7868 || (is_pmbr_valid(legacymbr) != 1)) {
79
- return -1;
69
+ return 0;
8070 }
8171
82
- return 0;
72
+ return 1;
8373 }
8474 #endif
8575
....@@ -262,35 +252,6 @@
262252 return envf_num;
263253 }
264254
265
-#ifdef CONFIG_ENV_PARTITION
266
-static int envf_add_partition_bootargs(void)
267
-{
268
- char *part_list;
269
- char *bootargs;
270
- int i;
271
-
272
- for (i = 0; i < ARRAY_SIZE(part_type); i++) {
273
- part_list = env_get(part_type[i]);
274
- if (part_list)
275
- break;
276
- }
277
- if (!part_list)
278
- return -EINVAL;
279
-
280
- bootargs = calloc(1, strlen(part_list) + strlen(part_type[i]) + 2);
281
- if (!bootargs)
282
- return -ENOMEM;
283
-
284
- strcat(bootargs, part_type[i]);
285
- strcat(bootargs, "=");
286
- strcat(bootargs, part_list);
287
- env_update("bootargs", bootargs);
288
- free(bootargs);
289
-
290
- return 0;
291
-}
292
-#endif
293
-
294255 static int envf_load(void)
295256 {
296257 struct blk_desc *desc;
....@@ -313,10 +274,6 @@
313274 return -EINTR;
314275 }
315276 }
316
-
317
-#ifdef CONFIG_ENV_PARTITION
318
- envf_add_partition_bootargs();
319
-#endif
320277
321278 return 0;
322279 }
u-boot/examples/standalone/Makefile
....@@ -10,6 +10,7 @@
1010 extra-$(CONFIG_SMC911X) += smc911x_eeprom
1111 extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2
1212 extra-$(CONFIG_PPC) += sched
13
+extra-$(CONFIG_ROCKCHIP_SPI) += rkspi
1314
1415 #
1516 # Some versions of make do not handle trailing white spaces properly;
u-boot/examples/standalone/README_rkspi.md
....@@ -0,0 +1,126 @@
1
+# RK SPI Standalone Bin
2
+
3
+This is the readme for the Das U-Boot standalone program rkspi
4
+
5
+
6
+How To Use
7
+------------------------
8
+### Compile
9
+
10
+1.Define the standalone load address in includes/configs/rkxxxxx_common.h
11
+
12
+```shell
13
+#define CONFIG_STANDALONE_LOAD_ADDR 0x40000000
14
+```
15
+
16
+2.Enable rkspi in defconfig
17
+
18
+```
19
+CONFIG_ROCKCHIP_SPI=y
20
+```
21
+
22
+### Setting SPI hardware
23
+
24
+1.Setting the iomux and spiclk through:
25
+
26
+- u-boot shell command
27
+- define it in rkspi.c spi_hw_init
28
+
29
+Note:
30
+
31
+- spiclk is the clock for spi controller, output to IO after internal frequency division of the controller.
32
+
33
+### Load And Executable
34
+
35
+1. load the bin by serial or tftp, take tftp as example:
36
+
37
+```shell
38
+setenv ipaddr 172.16.12.157
39
+setenv serverip 172.16.12.167
40
+tftp 0x40000000 rkspi.bin # 0x40000000 is define by CONFIG_STANDALONE_LOAD_ADDR
41
+```
42
+
43
+2. execute it
44
+
45
+```shell
46
+go 0x40000000 # 0x40000000 is define by CONFIG_STANDALONE_LOAD_ADDR
47
+```
48
+
49
+## Abort Codes
50
+
51
+### Introduction
52
+
53
+```c
54
+int rockchip_spi_probe(u8 bus, uintptr_t base_addr, u32 rsd, u32 clock_div, u32 mode);
55
+```
56
+
57
+- bus: spi bus
58
+- base_addr: spi register base address
59
+- rsd: read sample clock shift with spiclk which is controller working rate
60
+- clock_div: internal frequency division of the controller
61
+- mode: spi mode, support:
62
+
63
+```c
64
+#define SPI_CPHA BIT(0) /* clock phase */
65
+#define SPI_CPOL BIT(1) /* clock polarity */
66
+#define SPI_MODE_0 (0 | 0) /* (original MicroWire) */
67
+#define SPI_MODE_1 (0 | SPI_CPHA)
68
+#define SPI_MODE_2 (SPI_CPOL | 0)
69
+#define SPI_MODE_3 (SPI_CPOL | SPI_CPHA)
70
+```
71
+
72
+
73
+
74
+```c
75
+int rockchip_spi_claim_bus(u8 bus);
76
+```
77
+
78
+- bus: spi bus
79
+
80
+
81
+
82
+```c
83
+void rockchip_spi_release_bus(u8 bus);
84
+```
85
+
86
+- bus: spi bus
87
+
88
+
89
+
90
+```c
91
+int rockchip_spi_xfer(u8 bus, u8 cs, unsigned int bitlen, const void *dout, void *din, unsigned long flags);
92
+```
93
+
94
+- bus: spi bus
95
+- cs: spi cs
96
+- bitlen: the transfer length in bits
97
+- dout: write buffer (if exits)
98
+- din: read buffer (if exits), if the dout and din both defined, spi work in duplex mode
99
+- flags: operation chip select, support:
100
+
101
+```c
102
+#define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */
103
+#define SPI_XFER_END BIT(1) /* Deassert CS after transfer */
104
+#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
105
+```
106
+
107
+
108
+
109
+```c
110
+int rockchip_spi_write_then_read(u8 bus, u8 cs,
111
+ const u8 *opcode, size_t n_opcode,
112
+ const u8 *txbuf, u8 *rxbuf, size_t n_buf);
113
+```
114
+
115
+- bus: spi bus
116
+- cs: spi cs
117
+- opcode: command code
118
+- n_opcode: the numbers of command code in bytes
119
+- txbuf: write buffer (if exits)
120
+- rxbuf: read buffer (if exits), if the dout and din both defined, spi work in duplex mode
121
+- n_buf: the transfer length in bytes
122
+
123
+### Demo
124
+
125
+Is right in the main function of rkspi.
126
+
u-boot/examples/standalone/rkspi.c
....@@ -0,0 +1,454 @@
1
+/*
2
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+
7
+#include <common.h>
8
+#include <exports.h>
9
+
10
+#include "rkspi.h"
11
+
12
+/* Change to 1 to output registers at the start of each transaction */
13
+#define DEBUG_RK_SPI 0
14
+
15
+struct rockchip_spi_priv {
16
+ struct rockchip_spi *regs;
17
+ unsigned int mode;
18
+ u8 bits_per_word; /* max 16 bits per word */
19
+ u8 n_bytes;
20
+ unsigned int clock_div;
21
+ uint cr0;
22
+ u32 rsd; /* Rx sample delay cycles */
23
+};
24
+
25
+#define RK_SPI_BUS_MAX 5
26
+static struct rockchip_spi_priv spi_bus[RK_SPI_BUS_MAX];
27
+
28
+static inline struct rockchip_spi_priv *get_spi_bus(u8 bus)
29
+{
30
+ return &spi_bus[bus];
31
+}
32
+
33
+#define SPI_FIFO_DEPTH 32
34
+#define SPI_CR0_RSD_MAX 0x3
35
+
36
+static inline void writel(u32 val, void *addr)
37
+{
38
+ *(volatile u32 *)addr = val;
39
+}
40
+
41
+static inline u32 readl(void *addr)
42
+{
43
+ return *(volatile u32 *)addr;
44
+}
45
+
46
+static void rkspi_dump_regs(struct rockchip_spi *regs)
47
+{
48
+ debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
49
+ debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
50
+ debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
51
+ debug("ser: \t\t0x%08x\n", readl(&regs->ser));
52
+ debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
53
+ debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
54
+ debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
55
+ debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
56
+ debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
57
+ debug("sr: \t\t0x%08x\n", readl(&regs->sr));
58
+ debug("imr: \t\t0x%08x\n", readl(&regs->imr));
59
+ debug("isr: \t\t0x%08x\n", readl(&regs->isr));
60
+ debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
61
+ debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
62
+ debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
63
+}
64
+
65
+static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
66
+{
67
+ writel(enable ? 1 : 0, &regs->enr);
68
+}
69
+
70
+static void rkspi_set_baudr(struct rockchip_spi_priv *priv, uint clk_div)
71
+{
72
+ writel(clk_div, &priv->regs->baudr);
73
+}
74
+
75
+static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
76
+{
77
+ unsigned long start;
78
+
79
+ start = get_timer(0);
80
+ while (readl(&regs->sr) & SR_BUSY) {
81
+ if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
82
+ debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
83
+ return -ETIMEDOUT;
84
+ }
85
+ }
86
+
87
+ return 0;
88
+}
89
+
90
+static void spi_cs_activate(u8 bus, u8 cs)
91
+{
92
+ struct rockchip_spi_priv *priv = get_spi_bus(bus);
93
+ struct rockchip_spi *regs = priv->regs;
94
+
95
+ debug("activate cs%u\n", cs);
96
+ writel(1 << cs, &regs->ser);
97
+}
98
+
99
+static void spi_cs_deactivate(u8 bus, u8 cs)
100
+{
101
+ struct rockchip_spi_priv *priv = get_spi_bus(bus);
102
+ struct rockchip_spi *regs = priv->regs;
103
+
104
+ debug("deactivate cs%u\n", cs);
105
+ writel(0, &regs->ser);
106
+}
107
+
108
+int rockchip_spi_probe(u8 bus, uintptr_t base_addr, u32 rsd, u32 clock_div, u32 mode)
109
+{
110
+ struct rockchip_spi_priv *priv;
111
+
112
+ if (bus >= RK_SPI_BUS_MAX) {
113
+ printf("%s bus %d is out of max num(%d)\n", __func__, bus, RK_SPI_BUS_MAX);
114
+ return -1;
115
+ }
116
+
117
+ debug("%s: probe\n", __func__);
118
+
119
+ priv = &spi_bus[bus];
120
+
121
+ priv->regs = (struct rockchip_spi *)base_addr;
122
+ priv->rsd = rsd;
123
+ priv->mode = mode;
124
+ if (clock_div % 2 || clock_div < 2) {
125
+ printf("%s div should be even num, and at least 2\n", __func__);
126
+
127
+ return -1;
128
+ }
129
+ priv->clock_div = clock_div;
130
+ priv->bits_per_word = 8;
131
+
132
+ return 0;
133
+}
134
+
135
+int rockchip_spi_claim_bus(u8 bus)
136
+{
137
+ struct rockchip_spi_priv *priv = get_spi_bus(bus);
138
+ struct rockchip_spi *regs = priv->regs;
139
+ u8 spi_dfs, spi_tf;
140
+ uint ctrlr0;
141
+
142
+ /* Disable the SPI hardware */
143
+ rkspi_enable_chip(regs, 0);
144
+
145
+ switch (priv->bits_per_word) {
146
+ case 8:
147
+ priv->n_bytes = 1;
148
+ spi_dfs = DFS_8BIT;
149
+ spi_tf = HALF_WORD_OFF;
150
+ break;
151
+ case 16:
152
+ priv->n_bytes = 2;
153
+ spi_dfs = DFS_16BIT;
154
+ spi_tf = HALF_WORD_ON;
155
+ break;
156
+ default:
157
+ debug("%s: unsupported bits: %dbits\n", __func__,
158
+ priv->bits_per_word);
159
+ return -EPROTONOSUPPORT;
160
+ }
161
+
162
+ rkspi_set_baudr(priv, priv->clock_div);
163
+
164
+ /* Operation Mode */
165
+ ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
166
+
167
+ /* Data Frame Size */
168
+ ctrlr0 |= spi_dfs << DFS_SHIFT;
169
+
170
+ /* set SPI mode 0..3 */
171
+ if (priv->mode & SPI_CPOL)
172
+ ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
173
+ if (priv->mode & SPI_CPHA)
174
+ ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
175
+
176
+ /* Chip Select Mode */
177
+ ctrlr0 |= CSM_KEEP << CSM_SHIFT;
178
+
179
+ /* SSN to Sclk_out delay */
180
+ ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
181
+
182
+ /* Serial Endian Mode */
183
+ ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
184
+
185
+ /* First Bit Mode */
186
+ ctrlr0 |= FBM_MSB << FBM_SHIFT;
187
+
188
+ /* Byte and Halfword Transform */
189
+ ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
190
+
191
+ /* Rxd Sample Delay */
192
+ ctrlr0 |= priv->rsd << RXDSD_SHIFT;
193
+
194
+ /* Frame Format */
195
+ ctrlr0 |= FRF_SPI << FRF_SHIFT;
196
+
197
+ /* Save static configuration */
198
+ priv->cr0 = ctrlr0;
199
+
200
+ writel(ctrlr0, &regs->ctrlr0);
201
+
202
+ return 0;
203
+}
204
+
205
+int rockchip_spi_config(struct rockchip_spi_priv *priv, const void *dout)
206
+{
207
+ struct rockchip_spi *regs = priv->regs;
208
+ uint ctrlr0 = priv->cr0;
209
+ u32 tmod;
210
+
211
+ if (dout)
212
+ tmod = TMOD_TR;
213
+ else
214
+ tmod = TMOD_RO;
215
+
216
+ ctrlr0 |= (tmod & TMOD_MASK) << TMOD_SHIFT;
217
+ writel(ctrlr0, &regs->ctrlr0);
218
+
219
+ return 0;
220
+}
221
+
222
+void rockchip_spi_release_bus(u8 bus)
223
+{
224
+ struct rockchip_spi_priv *priv = get_spi_bus(bus);
225
+
226
+ rkspi_enable_chip(priv->regs, false);
227
+}
228
+
229
+int rockchip_spi_xfer(u8 bus, u8 cs, unsigned int bitlen, const void *dout, void *din, unsigned long flags)
230
+{
231
+ struct rockchip_spi_priv *priv = get_spi_bus(bus);
232
+ struct rockchip_spi *regs = priv->regs;
233
+ int len = bitlen >> 3;
234
+ const u8 *out = dout;
235
+ u8 *in = din;
236
+ int toread, towrite;
237
+ int ret;
238
+
239
+ rockchip_spi_config(priv, dout);
240
+
241
+ debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
242
+ len, flags);
243
+ if (DEBUG_RK_SPI)
244
+ rkspi_dump_regs(regs);
245
+
246
+ /* Assert CS before transfer */
247
+ if (flags & SPI_XFER_BEGIN)
248
+ spi_cs_activate(bus, cs);
249
+
250
+ while (len > 0) {
251
+ int todo = min(len, 0xffff);
252
+
253
+ rkspi_enable_chip(regs, false);
254
+ writel(todo - 1, &regs->ctrlr1);
255
+ rkspi_enable_chip(regs, true);
256
+
257
+ toread = todo;
258
+ towrite = todo;
259
+ while (toread || towrite) {
260
+ u32 status = readl(&regs->sr);
261
+
262
+ if (towrite && !(status & SR_TF_FULL)) {
263
+ if (out)
264
+ writel(out ? *out++ : 0, regs->txdr);
265
+ towrite--;
266
+ }
267
+ if (toread && !(status & SR_RF_EMPT)) {
268
+ u32 byte = readl(regs->rxdr);
269
+
270
+ if (in)
271
+ *in++ = byte;
272
+ toread--;
273
+ }
274
+ }
275
+ ret = rkspi_wait_till_not_busy(regs);
276
+ if (ret)
277
+ break;
278
+ len -= todo;
279
+ }
280
+
281
+ /* Deassert CS after transfer */
282
+ if (flags & SPI_XFER_END)
283
+ spi_cs_deactivate(bus, cs);
284
+
285
+ rkspi_enable_chip(regs, false);
286
+
287
+ return ret;
288
+}
289
+
290
+int rockchip_spi_write_then_read(u8 bus, u8 cs, const u8 *opcode,
291
+ size_t n_opcode, const u8 *txbuf, u8 *rxbuf,
292
+ size_t n_buf)
293
+{
294
+ unsigned long flags = SPI_XFER_BEGIN;
295
+ int ret;
296
+
297
+ if (n_buf == 0)
298
+ flags |= SPI_XFER_END;
299
+
300
+ ret = rockchip_spi_xfer(bus, cs, n_opcode * 8, opcode, NULL, flags);
301
+ if (ret) {
302
+ debug("spi: failed to send command (%zu bytes): %d\n",
303
+ n_opcode, ret);
304
+ } else if (n_buf != 0) {
305
+ ret = rockchip_spi_xfer(bus, cs, n_buf * 8, txbuf, rxbuf, SPI_XFER_END);
306
+ if (ret)
307
+ debug("spi: failed to transfer %zu bytes of data: %d\n",
308
+ n_buf, ret);
309
+ }
310
+
311
+ return ret;
312
+}
313
+
314
+void dbg_print_hex(char *s, void *buf, u32 width, u32 len)
315
+{
316
+ u32 i, j;
317
+ unsigned char *p8 = (unsigned char *)buf;
318
+ unsigned short *p16 = (unsigned short *)buf;
319
+ u32 *p32 = (u32 *)buf;
320
+
321
+ j = 0;
322
+
323
+ for (i = 0; i < len; i++) {
324
+ if (j == 0)
325
+ printf("%s %p + 0x%x:", s, buf, i * width);
326
+
327
+ if (width == 4)
328
+ printf("0x%08x,", p32[i]);
329
+ else if (width == 2)
330
+ printf("0x%04x,", p16[i]);
331
+ else
332
+ printf("0x%02x,", p8[i]);
333
+
334
+ if (++j >= (16 / width)) {
335
+ j = 0;
336
+ printf("\n");
337
+ }
338
+ }
339
+
340
+ printf("\n");
341
+}
342
+
343
+static void spi_hw_init(void)
344
+{
345
+ /* Setting the clock and iomux */
346
+ /* todo */
347
+}
348
+
349
+int main(int argc, char * const argv[])
350
+{
351
+ int i;
352
+
353
+ /* Print the ABI version */
354
+ app_startup(argv);
355
+ printf("Example expects ABI version %d\n", XF_VERSION);
356
+ printf("Actual U-Boot ABI version %d\n", (int)get_version());
357
+
358
+ printf("rk_spi standalone version\n");
359
+
360
+ printf("argc = %d\n", argc);
361
+
362
+ for (i = 0; i <= argc; ++i) {
363
+ printf("argv[%d] = \"%s\"\n",
364
+ i,
365
+ argv[i] ? argv[i] : "<NULL>");
366
+ }
367
+
368
+ /*
369
+ * spi test demo
370
+ */
371
+#if 1
372
+ u8 bus, cs;
373
+ unsigned char *pread, *pwrite;
374
+ u32 test_size = 0x100;
375
+ int ret;
376
+
377
+ pread = malloc(test_size);
378
+ if (!pread)
379
+ printf("%s pread malloc fail\n", __func__);
380
+ pwrite = malloc(test_size);
381
+ if (!pwrite) {
382
+ printf("%s pwrite malloc fail\n", __func__);
383
+ free(pwrite);
384
+
385
+ return -1;
386
+ }
387
+
388
+ for (i = 0; i < test_size; i++)
389
+ pwrite[i] = i;
390
+
391
+ bus = 4;
392
+ cs = 0;
393
+
394
+ spi_hw_init();
395
+
396
+ rockchip_spi_probe(bus, 0xfecb0000, 0, 20, SPI_MODE_3);
397
+ rockchip_spi_claim_bus(bus);
398
+
399
+ /*
400
+ * SPI write
401
+ */
402
+ ret = rockchip_spi_xfer(bus, cs, test_size * 8, pwrite, NULL, SPI_XFER_ONCE);
403
+ if (ret) {
404
+ printf("rockchip_spi_xfer fail ret=%d\n", ret);
405
+
406
+ return ret;
407
+ }
408
+
409
+ /*
410
+ * SPI read
411
+ */
412
+ rockchip_spi_xfer(bus, cs, test_size * 8, NULL, pread, SPI_XFER_ONCE);
413
+ if (ret) {
414
+ printf("rockchip_spi_xfer fail ret=%d\n", ret);
415
+
416
+ return ret;
417
+ }
418
+ dbg_print_hex("spi_read:", pread, 4, test_size / 4);
419
+
420
+ /*
421
+ * SPI duplex
422
+ */
423
+ rockchip_spi_xfer(bus, cs, test_size * 8, pwrite, pread, SPI_XFER_ONCE);
424
+ if (ret) {
425
+ printf("rockchip_spi_xfer fail ret=%d\n", ret);
426
+
427
+ return ret;
428
+ }
429
+ dbg_print_hex("spi_duplex:", pread, 4, test_size / 4);
430
+
431
+ /*
432
+ * SPI write then read
433
+ */
434
+ rockchip_spi_write_then_read(bus, cs, pwrite, 1, NULL, pread, test_size);
435
+ if (ret) {
436
+ printf("rockchip_spi_xfer fail ret=%d\n", ret);
437
+
438
+ return ret;
439
+ }
440
+ dbg_print_hex("spi_write_then_read:", pread, 4, test_size / 4);
441
+
442
+ rockchip_spi_release_bus(bus);
443
+#endif
444
+
445
+ printf("Hit any key to exit ... ");
446
+ while (!tstc())
447
+ ;
448
+ /* consume input */
449
+ (void)getc();
450
+
451
+ printf("\n\n");
452
+
453
+ return 0;
454
+}
u-boot/examples/standalone/rkspi.h
....@@ -0,0 +1,138 @@
1
+/*
2
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+
7
+#ifndef _DRIVER_SPI_H_
8
+#define _DRIVER_SPI_H_
9
+
10
+struct rockchip_spi {
11
+ u32 ctrlr0;
12
+ u32 ctrlr1;
13
+ u32 enr;
14
+ u32 ser;
15
+ u32 baudr;
16
+ u32 txftlr;
17
+ u32 rxftlr;
18
+ u32 txflr;
19
+ u32 rxflr;
20
+ u32 sr;
21
+ u32 ipr;
22
+ u32 imr;
23
+ u32 isr;
24
+ u32 risr;
25
+ u32 icr;
26
+ u32 dmacr;
27
+ u32 dmatdlr;
28
+ u32 dmardlr; /* 0x44 */
29
+ u32 reserved[0xef];
30
+ u32 txdr[0x100]; /* 0x400 */
31
+ u32 rxdr[0x100]; /* 0x800 */
32
+};
33
+
34
+/* CTRLR0 */
35
+enum {
36
+ DFS_SHIFT = 0, /* Data Frame Size */
37
+ DFS_MASK = 3,
38
+ DFS_4BIT = 0,
39
+ DFS_8BIT,
40
+ DFS_16BIT,
41
+ DFS_RESV,
42
+
43
+ CFS_SHIFT = 2, /* Control Frame Size */
44
+ CFS_MASK = 0xf,
45
+
46
+ SCPH_SHIFT = 6, /* Serial Clock Phase */
47
+ SCPH_MASK = 1,
48
+ SCPH_TOGMID = 0, /* SCLK toggles in middle of first data bit */
49
+ SCPH_TOGSTA, /* SCLK toggles at start of first data bit */
50
+
51
+ SCOL_SHIFT = 7, /* Serial Clock Polarity */
52
+ SCOL_MASK = 1,
53
+ SCOL_LOW = 0, /* Inactive state of serial clock is low */
54
+ SCOL_HIGH, /* Inactive state of serial clock is high */
55
+
56
+ CSM_SHIFT = 8, /* Chip Select Mode */
57
+ CSM_MASK = 0x3,
58
+ CSM_KEEP = 0, /* ss_n stays low after each frame */
59
+ CSM_HALF, /* ss_n high for half sclk_out cycles */
60
+ CSM_ONE, /* ss_n high for one sclk_out cycle */
61
+ CSM_RESV,
62
+
63
+ SSN_DELAY_SHIFT = 10, /* SSN to Sclk_out delay */
64
+ SSN_DELAY_MASK = 1,
65
+ SSN_DELAY_HALF = 0, /* 1/2 sclk_out cycle */
66
+ SSN_DELAY_ONE = 1, /* 1 sclk_out cycle */
67
+
68
+ SEM_SHIFT = 11, /* Serial Endian Mode */
69
+ SEM_MASK = 1,
70
+ SEM_LITTLE = 0, /* little endian */
71
+ SEM_BIG, /* big endian */
72
+
73
+ FBM_SHIFT = 12, /* First Bit Mode */
74
+ FBM_MASK = 1,
75
+ FBM_MSB = 0, /* first bit is MSB */
76
+ FBM_LSB, /* first bit in LSB */
77
+
78
+ HALF_WORD_TX_SHIFT = 13, /* Byte and Halfword Transform */
79
+ HALF_WORD_MASK = 1,
80
+ HALF_WORD_ON = 0, /* apb 16bit write/read, spi 8bit write/read */
81
+ HALF_WORD_OFF, /* apb 8bit write/read, spi 8bit write/read */
82
+
83
+ RXDSD_SHIFT = 14, /* Rxd Sample Delay, in cycles */
84
+ RXDSD_MASK = 3,
85
+
86
+ FRF_SHIFT = 16, /* Frame Format */
87
+ FRF_MASK = 3,
88
+ FRF_SPI = 0, /* Motorola SPI */
89
+ FRF_SSP, /* Texas Instruments SSP*/
90
+ FRF_MICROWIRE, /* National Semiconductors Microwire */
91
+ FRF_RESV,
92
+
93
+ TMOD_SHIFT = 18, /* Transfer Mode */
94
+ TMOD_MASK = 3,
95
+ TMOD_TR = 0, /* xmit & recv */
96
+ TMOD_TO, /* xmit only */
97
+ TMOD_RO, /* recv only */
98
+ TMOD_RESV,
99
+
100
+ OMOD_SHIFT = 20, /* Operation Mode */
101
+ OMOD_MASK = 1,
102
+ OMOD_MASTER = 0, /* Master Mode */
103
+ OMOD_SLAVE, /* Slave Mode */
104
+};
105
+
106
+/* SR */
107
+enum {
108
+ SR_MASK = 0x7f,
109
+ SR_BUSY = 1 << 0,
110
+ SR_TF_FULL = 1 << 1,
111
+ SR_TF_EMPT = 1 << 2,
112
+ SR_RF_EMPT = 1 << 3,
113
+ SR_RF_FULL = 1 << 4,
114
+};
115
+
116
+#define ROCKCHIP_SPI_TIMEOUT_MS 1000
117
+
118
+#define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */
119
+#define SPI_XFER_END BIT(1) /* Deassert CS after transfer */
120
+#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
121
+
122
+/* SPI mode flags */
123
+#define SPI_CPHA BIT(0) /* clock phase */
124
+#define SPI_CPOL BIT(1) /* clock polarity */
125
+#define SPI_MODE_0 (0 | 0) /* (original MicroWire) */
126
+#define SPI_MODE_1 (0 | SPI_CPHA)
127
+#define SPI_MODE_2 (SPI_CPOL | 0)
128
+#define SPI_MODE_3 (SPI_CPOL | SPI_CPHA)
129
+
130
+int rockchip_spi_probe(u8 bus, uintptr_t base_addr, u32 rsd, u32 clock_div, u32 mode);
131
+int rockchip_spi_claim_bus(u8 bus);
132
+void rockchip_spi_release_bus(u8 bus);
133
+int rockchip_spi_xfer(u8 bus, u8 cs, unsigned int bitlen, const void *dout, void *din, unsigned long flags);
134
+int rockchip_spi_write_then_read(u8 bus, u8 cs,
135
+ const u8 *opcode, size_t n_opcode,
136
+ const u8 *txbuf, u8 *rxbuf, size_t n_buf);
137
+
138
+#endif
u-boot/fs/ubifs/debug.h
....@@ -166,40 +166,22 @@
166166 dbg_snprintf_key(c, key, __tmp_key_buf, DBG_KEY_BUF_LEN)); \
167167 } while (0)
168168 #else
169
-#define ubifs_assert(expr) do { \
170
- if (unlikely(!(expr))) { \
171
- pr_debug("UBIFS assert failed in %s at %u\n", \
172
- __func__, __LINE__); \
173
- dump_stack(); \
174
- } \
175
-} while (0)
176169
177
-#define ubifs_assert_cmt_locked(c) do { \
178
- if (unlikely(down_write_trylock(&(c)->commit_sem))) { \
179
- up_write(&(c)->commit_sem); \
180
- pr_debug("commit lock is not locked!\n"); \
181
- ubifs_assert(0); \
182
- } \
183
-} while (0)
170
+#include <log.h>
171
+#define ubifs_assert(expr) assert(expr)
172
+#define ubifs_assert_cmt_locked(c) do { } while (0)
184173
185174 #define ubifs_dbg_msg(type, fmt, ...) \
186175 pr_debug("UBIFS DBG " type ": " fmt "\n", \
187176 ##__VA_ARGS__)
188177
189178 #define DBG_KEY_BUF_LEN 48
190
-#if defined CONFIG_MTD_DEBUG
191179 #define ubifs_dbg_msg_key(type, key, fmt, ...) do { \
192180 char __tmp_key_buf[DBG_KEY_BUF_LEN]; \
193181 pr_debug("UBIFS DBG " type ": " fmt "%s\n", \
194182 ##__VA_ARGS__, \
195183 dbg_snprintf_key(c, key, __tmp_key_buf, DBG_KEY_BUF_LEN)); \
196184 } while (0)
197
-#else
198
-#define ubifs_dbg_msg_key(type, key, fmt, ...) do { \
199
- pr_debug("UBIFS DBG\n"); \
200
-} while (0)
201
-
202
-#endif
203185
204186 #endif
205187
u-boot/fs/ubifs/io.c
....@@ -111,7 +111,7 @@
111111 int ubifs_leb_write(struct ubifs_info *c, int lnum, const void *buf, int offs,
112112 int len)
113113 {
114
- int err;
114
+ int err = 0;
115115
116116 ubifs_assert(!c->ro_media && !c->ro_mount);
117117 if (c->ro_error)
....@@ -133,7 +133,7 @@
133133
134134 int ubifs_leb_change(struct ubifs_info *c, int lnum, const void *buf, int len)
135135 {
136
- int err;
136
+ int err = 0;
137137
138138 ubifs_assert(!c->ro_media && !c->ro_mount);
139139 if (c->ro_error)
....@@ -155,7 +155,7 @@
155155
156156 int ubifs_leb_unmap(struct ubifs_info *c, int lnum)
157157 {
158
- int err;
158
+ int err = 0;
159159
160160 ubifs_assert(!c->ro_media && !c->ro_mount);
161161 if (c->ro_error)
....@@ -176,7 +176,7 @@
176176
177177 int ubifs_leb_map(struct ubifs_info *c, int lnum)
178178 {
179
- int err;
179
+ int err = 0;
180180
181181 ubifs_assert(!c->ro_media && !c->ro_mount);
182182 if (c->ro_error)
u-boot/fs/ubifs/super.c
....@@ -1749,6 +1749,8 @@
17491749 kfree(c->bottom_up_buf);
17501750 ubifs_debugging_exit(c);
17511751 #ifdef __UBOOT__
1752
+ ubi_close_volume(c->ubi);
1753
+ mutex_unlock(&c->umount_mutex);
17521754 /* Finally free U-Boot's global copy of superblock */
17531755 if (ubifs_sb != NULL) {
17541756 free(ubifs_sb->s_fs_info);
....@@ -2050,9 +2052,9 @@
20502052 ubifs_umount(c);
20512053 #ifndef __UBOOT__
20522054 bdi_destroy(&c->bdi);
2053
-#endif
20542055 ubi_close_volume(c->ubi);
20552056 mutex_unlock(&c->umount_mutex);
2057
+#endif
20562058 }
20572059 #endif
20582060
....@@ -2319,6 +2321,9 @@
23192321
23202322 out_umount:
23212323 ubifs_umount(c);
2324
+#ifdef __UBOOT__
2325
+ goto out;
2326
+#endif
23222327 out_unlock:
23232328 mutex_unlock(&c->umount_mutex);
23242329 #ifndef __UBOOT__
....@@ -2356,7 +2361,9 @@
23562361 return ERR_PTR(err);
23572362 }
23582363
2364
+#ifndef __UBOOT__
23592365 INIT_HLIST_NODE(&s->s_instances);
2366
+#endif
23602367 INIT_LIST_HEAD(&s->s_inodes);
23612368 s->s_time_gran = 1000000000;
23622369 s->s_flags = flags;
....@@ -2425,14 +2432,12 @@
24252432 #ifndef __UBOOT__
24262433 strlcpy(s->s_id, type->name, sizeof(s->s_id));
24272434 list_add_tail(&s->s_list, &super_blocks);
2428
-#else
2429
- strncpy(s->s_id, type->name, sizeof(s->s_id));
2430
-#endif
24312435 hlist_add_head(&s->s_instances, &type->fs_supers);
2432
-#ifndef __UBOOT__
24332436 spin_unlock(&sb_lock);
24342437 get_filesystem(type);
24352438 register_shrinker(&s->s_shrink);
2439
+#else
2440
+ strncpy(s->s_id, type->name, sizeof(s->s_id));
24362441 #endif
24372442 return s;
24382443 }
....@@ -2457,7 +2462,7 @@
24572462 */
24582463 ubi = open_ubi(name, UBI_READONLY);
24592464 if (IS_ERR(ubi)) {
2460
- pr_err("UBIFS error (pid: %d): cannot open \"%s\", error %d",
2465
+ pr_err("UBIFS error (pid: %d): cannot open \"%s\", error %d\n",
24612466 current->pid, name, (int)PTR_ERR(ubi));
24622467 return ERR_CAST(ubi);
24632468 }
....@@ -2599,7 +2604,7 @@
25992604 * UBIFS_BLOCK_SIZE. It is assumed that both are powers of 2.
26002605 */
26012606 if (PAGE_CACHE_SIZE < UBIFS_BLOCK_SIZE) {
2602
- pr_err("UBIFS error (pid %d): VFS page cache size is %u bytes, but UBIFS requires at least 4096 bytes",
2607
+ pr_err("UBIFS error (pid %d): VFS page cache size is %u bytes, but UBIFS requires at least 4096 bytes\n",
26032608 current->pid, (unsigned int)PAGE_CACHE_SIZE);
26042609 return -EINVAL;
26052610 }
....@@ -2628,7 +2633,7 @@
26282633
26292634 err = register_filesystem(&ubifs_fs_type);
26302635 if (err) {
2631
- pr_err("UBIFS error (pid %d): cannot register file system, error %d",
2636
+ pr_err("UBIFS error (pid %d): cannot register file system, error %d\n",
26322637 current->pid, err);
26332638 goto out_dbg;
26342639 }
u-boot/fs/ubifs/tnc.c
....@@ -46,6 +46,11 @@
4646 NOT_ON_MEDIA = 3,
4747 };
4848
49
+static int try_read_node(const struct ubifs_info *c, void *buf, int type,
50
+ int len, int lnum, int offs);
51
+static int fallible_read_node(struct ubifs_info *c, const union ubifs_key *key,
52
+ struct ubifs_zbranch *zbr, void *node);
53
+
4954 /**
5055 * insert_old_idx - record an index node obsoleted since the last commit start.
5156 * @c: UBIFS file-system description object
....@@ -398,7 +403,19 @@
398403 return 0;
399404 }
400405
401
- err = ubifs_tnc_read_node(c, zbr, node);
406
+ if (c->replaying) {
407
+ err = fallible_read_node(c, &zbr->key, zbr, node);
408
+ /*
409
+ * When the node was not found, return -ENOENT, 0 otherwise.
410
+ * Negative return codes stay as-is.
411
+ */
412
+ if (err == 0)
413
+ err = -ENOENT;
414
+ else if (err == 1)
415
+ err = 0;
416
+ } else {
417
+ err = ubifs_tnc_read_node(c, zbr, node);
418
+ }
402419 if (err)
403420 return err;
404421
....@@ -2766,7 +2783,11 @@
27662783 if (nm->name) {
27672784 if (err) {
27682785 /* Handle collisions */
2769
- err = resolve_collision(c, key, &znode, &n, nm);
2786
+ if (c->replaying)
2787
+ err = fallible_resolve_collision(c, key, &znode, &n,
2788
+ nm, 0);
2789
+ else
2790
+ err = resolve_collision(c, key, &znode, &n, nm);
27702791 dbg_tnc("rc returned %d, znode %p, n %d",
27712792 err, znode, n);
27722793 if (unlikely(err < 0))
u-boot/fs/ubifs/ubifs.c
....@@ -126,6 +126,7 @@
126126 {
127127 struct ubifs_compressor *compr = ubifs_compressors[tfm->compressor];
128128 int err;
129
+ size_t tmp_len = *dlen;
129130
130131 if (compr->compr_type == UBIFS_COMPR_NONE) {
131132 memcpy(dst, src, slen);
....@@ -133,11 +134,12 @@
133134 return 0;
134135 }
135136
136
- err = compr->decompress(src, slen, dst, (size_t *)dlen);
137
+ err = compr->decompress(src, slen, dst, &tmp_len);
137138 if (err)
138139 ubifs_err(c, "cannot decompress %d bytes, compressor %s, "
139140 "error %d", slen, compr->name, err);
140141
142
+ *dlen = tmp_len;
141143 return err;
142144
143145 return 0;
....@@ -466,14 +468,10 @@
466468 dbg_gen("cannot find next direntry, error %d", err);
467469
468470 out_free:
469
- if (file->private_data)
470
- kfree(file->private_data);
471
- if (file)
472
- free(file);
473
- if (dentry)
474
- free(dentry);
475
- if (dir)
476
- free(dir);
471
+ kfree(file->private_data);
472
+ free(file);
473
+ free(dentry);
474
+ free(dir);
477475
478476 return ret;
479477 }
....@@ -801,6 +799,8 @@
801799
802800 if (last_block_size)
803801 dlen = last_block_size;
802
+ else if (ret)
803
+ dlen = UBIFS_BLOCK_SIZE;
804804 else
805805 dlen = le32_to_cpu(dn->size);
806806
u-boot/fs/ubifs/ubifs.h
....@@ -317,8 +317,8 @@
317317 struct backing_dev_info *s_bdi;
318318 #endif
319319 struct mtd_info *s_mtd;
320
- struct hlist_node s_instances;
321320 #ifndef __UBOOT__
321
+ struct hlist_node s_instances;
322322 struct quota_info s_dquot; /* Diskquota specific options */
323323 #endif
324324
....@@ -611,16 +611,20 @@
611611 /* misc.h */
612612 #define mutex_lock_nested(...)
613613 #define mutex_unlock_nested(...)
614
-#define mutex_is_locked(...) 0
614
+#define mutex_is_locked(...) 1
615615 #endif
616616
617617 /* Version of this UBIFS implementation */
618618 #define UBIFS_VERSION 1
619619
620620 /* Normal UBIFS messages */
621
+#ifdef CONFIG_UBIFS_SILENCE_MSG
622
+#define ubifs_msg(c, fmt, ...)
623
+#else
621624 #define ubifs_msg(c, fmt, ...) \
622625 pr_notice("UBIFS (ubi%d:%d): " fmt "\n", \
623626 (c)->vi.ubi_num, (c)->vi.vol_id, ##__VA_ARGS__)
627
+#endif
624628 /* UBIFS error messages */
625629 #ifndef __UBOOT__
626630 #define ubifs_err(c, fmt, ...) \
u-boot/include/android_ab.h
....@@ -47,7 +47,7 @@
4747 int read_misc_virtual_ab_message(struct misc_virtual_ab_message *message);
4848 int write_misc_virtual_ab_message(struct misc_virtual_ab_message *message);
4949
50
-void ab_update_root_uuid(void);
50
+void ab_update_root_partition(void);
5151 int ab_get_slot_suffix(char *slot_suffix);
5252 int ab_is_support_dynamic_partition(struct blk_desc *dev_desc);
5353 int ab_decrease_tries(void);
u-boot/include/android_avb/avb_ops_user.h
....@@ -63,6 +63,22 @@
6363 /* Frees an AvbOps instance previously allocated with avb_ops_device_new(). */
6464 void avb_ops_user_free(AvbOps* ops);
6565
66
+struct preloaded_partition {
67
+ uint8_t *addr;
68
+ size_t size; // 0 means the partition hasn't yet been preloaded
69
+};
70
+
71
+struct AvbOpsData {
72
+ struct AvbOps *ops;
73
+ const char *iface;
74
+ const char *devnum;
75
+ const char *slot_suffix;
76
+ struct preloaded_partition boot;
77
+ struct preloaded_partition vendor_boot;
78
+ struct preloaded_partition init_boot;
79
+ struct preloaded_partition resource;
80
+};
81
+
6682 #ifdef __cplusplus
6783 }
6884 #endif
u-boot/include/android_image.h
....@@ -13,8 +13,10 @@
1313
1414 #define ANDROID_PARTITION_BOOT "boot"
1515 #define ANDROID_PARTITION_VENDOR_BOOT "vendor_boot"
16
+#define ANDROID_PARTITION_INIT_BOOT "init_boot"
1617 #define ANDROID_PARTITION_MISC "misc"
1718 #define ANDROID_PARTITION_OEM "oem"
19
+#define ANDROID_PARTITION_RESOURCE "resource"
1820 #define ANDROID_PARTITION_RECOVERY "recovery"
1921 #define ANDROID_PARTITION_SYSTEM "system"
2022 #define ANDROID_PARTITION_VBMETA "vbmeta"
....@@ -117,7 +119,6 @@
117119 * we have to partly merge fields from boot_img_hdr_v34 and vendor_boot_img_hdr_v34
118120 * into this structure to compatible with boot_img_hdr_v012.
119121 */
120
- u32 boot_ramdisk_size; /* size in bytes */
121122 u32 vendor_ramdisk_size; /* size in bytes */
122123 u32 vendor_page_size;
123124 u32 vendor_header_version;
....@@ -135,6 +136,9 @@
135136 u32 vendor_ramdisk_table_entry_size;
136137 u32 vendor_bootconfig_size; /* size in bytes for bootconfig image */
137138
139
+ void *init_boot_buf;
140
+ void *vendor_boot_buf;
141
+
138142 /*
139143 * Don't define 'char total_cmdline[TOTAL_BOOT_ARGS_SIZE]' to avoid
140144 * this structrue is over size than page_size.
u-boot/include/asm-generic/atomic-long.h
....@@ -66,6 +66,7 @@
6666 atomic64_sub(i, v);
6767 }
6868
69
+#ifndef __UBOOT__
6970 static inline int atomic_long_sub_and_test(long i, atomic_long_t *l)
7071 {
7172 atomic64_t *v = (atomic64_t *)l;
....@@ -135,6 +136,7 @@
135136 (atomic64_cmpxchg((atomic64_t *)(l), (old), (new)))
136137 #define atomic_long_xchg(v, new) \
137138 (atomic64_xchg((atomic64_t *)(v), (new)))
139
+#endif /* __UBOOT__ */
138140
139141 #else /* BITS_PER_LONG == 64 */
140142
u-boot/include/asm-generic/u-boot.h
....@@ -87,8 +87,6 @@
8787 ulong bi_arch_number; /* unique id for this board */
8888 ulong bi_boot_params; /* where this board expects params */
8989
90
- /* same as android image header 'os_version' */
91
- unsigned int bi_andr_version;
9290 #ifdef CONFIG_NR_DRAM_BANKS
9391 struct { /* RAM configuration */
9492 u64 start;
u-boot/include/boot_rkimg.h
....@@ -19,6 +19,7 @@
1919 BOOT_MODE_PANIC,
2020 BOOT_MODE_WATCHDOG,
2121 BOOT_MODE_DFU,
22
+ BOOT_MODE_QUIESCENT,
2223 BOOT_MODE_UNDEFINE,
2324 };
2425
u-boot/include/charset.h
....@@ -9,6 +9,9 @@
99 #ifndef __CHARSET_H_
1010 #define __CHARSET_H_
1111
12
+#include <linux/kernel.h>
13
+#include <linux/types.h>
14
+
1215 #define MAX_UTF8_PER_UTF16 4
1316
1417 /**
u-boot/include/configs/evb_rk3528.h
....@@ -0,0 +1,26 @@
1
+/*
2
+ * SPDX-License-Identifier: GPL-2.0+
3
+ *
4
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd
5
+ */
6
+
7
+#ifndef __CONFIGS_RK3528_EVB_H
8
+#define __CONFIGS_RK3528_EVB_H
9
+
10
+#include <configs/rk3528_common.h>
11
+
12
+#ifndef CONFIG_SPL_BUILD
13
+
14
+#undef ROCKCHIP_DEVICE_SETTINGS
15
+#define ROCKCHIP_DEVICE_SETTINGS \
16
+ "stdin=serial,usbkbd\0" \
17
+ "stdout=serial,vidconsole\0" \
18
+ "stderr=serial,vidconsole\0"
19
+
20
+#define CONFIG_SYS_MMC_ENV_DEV 0
21
+
22
+#undef CONFIG_BOOTCOMMAND
23
+#define CONFIG_BOOTCOMMAND RKIMG_BOOTCOMMAND
24
+#endif
25
+
26
+#endif /* __CONFIGS_RK3528_EVB_H */
u-boot/include/configs/evb_rk3562.h
....@@ -0,0 +1,26 @@
1
+/*
2
+ * SPDX-License-Identifier: GPL-2.0+
3
+ *
4
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd
5
+ */
6
+
7
+#ifndef __CONFIGS_RK3562_EVB_H
8
+#define __CONFIGS_RK3562_EVB_H
9
+
10
+#include <configs/rk3562_common.h>
11
+
12
+#ifndef CONFIG_SPL_BUILD
13
+
14
+#undef ROCKCHIP_DEVICE_SETTINGS
15
+#define ROCKCHIP_DEVICE_SETTINGS \
16
+ "stdin=serial,usbkbd\0" \
17
+ "stdout=serial,vidconsole\0" \
18
+ "stderr=serial,vidconsole\0"
19
+
20
+#define CONFIG_SYS_MMC_ENV_DEV 0
21
+
22
+#undef CONFIG_BOOTCOMMAND
23
+#define CONFIG_BOOTCOMMAND RKIMG_BOOTCOMMAND
24
+#endif
25
+
26
+#endif /* __CONFIGS_RK3562_EVB_H */
u-boot/include/configs/rk3288_common.h
....@@ -59,7 +59,7 @@
5959 #define ENV_MEM_LAYOUT_SETTINGS \
6060 "scriptaddr=0x00000000\0" \
6161 "pxefile_addr_r=0x00100000\0" \
62
- "fdt_addr_r=0x08300000\0" \
62
+ "fdt_addr_r=0x08100000\0" \
6363 "kernel_addr_r=0x02008000\0" \
6464 "ramdisk_addr_r=0x0a200000\0"
6565
u-boot/include/configs/rk3528_common.h
....@@ -0,0 +1,109 @@
1
+/* SPDX-License-Identifier: GPL-2.0+ */
2
+/*
3
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
4
+ *
5
+ */
6
+
7
+#ifndef __CONFIG_RK3528_COMMON_H
8
+#define __CONFIG_RK3528_COMMON_H
9
+
10
+#include "rockchip-common.h"
11
+
12
+#define CONFIG_SPL_FRAMEWORK
13
+#define CONFIG_SPL_TEXT_BASE 0x00000000
14
+#define CONFIG_SPL_MAX_SIZE 0x00040000
15
+#define CONFIG_SPL_BSS_START_ADDR 0x03fe0000
16
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00010000
17
+#define CONFIG_SPL_STACK 0x03fe0000
18
+
19
+#define CONFIG_SYS_MALLOC_LEN (32 << 20)
20
+#define CONFIG_SYS_CBSIZE 1024
21
+#define CONFIG_SKIP_LOWLEVEL_INIT
22
+
23
+#ifdef CONFIG_SUPPORT_USBPLUG
24
+#define CONFIG_SYS_TEXT_BASE 0x00000000
25
+#else
26
+#define CONFIG_SYS_TEXT_BASE 0x00200000
27
+#endif
28
+
29
+#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
30
+#define CONFIG_SYS_LOAD_ADDR 0x00c00800
31
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
32
+#define COUNTER_FREQUENCY 24000000
33
+
34
+#define GICD_BASE 0xfed01000
35
+#define GICC_BASE 0xfed02000
36
+
37
+#ifdef CONFIG_SPL_DM_VIDEO
38
+#undef CONFIG_SPL_MAX_SIZE
39
+#undef CONFIG_SPL_BSS_MAX_SIZE
40
+#define CONFIG_SPL_MAX_SIZE 0x00140000
41
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
42
+#endif
43
+
44
+#ifdef CONFIG_ARM_SMP
45
+#define SMP_CPU1 0x1
46
+#define SMP_CPU1_STACK 0x04fe0000
47
+#define SMP_CPU2 0x2
48
+#define SMP_CPU2_STACK 0x05fe0000
49
+#endif
50
+
51
+/* secure otp */
52
+#define OTP_UBOOT_ROLLBACK_OFFSET 0x350
53
+#define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */
54
+#define OTP_ALL_ONES_NUM_BITS 32
55
+#define OTP_SECURE_BOOT_ENABLE_ADDR 0x20
56
+#define OTP_SECURE_BOOT_ENABLE_SIZE 1
57
+#define OTP_RSA_HASH_ADDR 0x180
58
+#define OTP_RSA_HASH_SIZE 32
59
+
60
+/* MMC/SD IP block */
61
+#define CONFIG_BOUNCE_BUFFER
62
+
63
+#define CONFIG_SYS_SDRAM_BASE 0
64
+#define SDRAM_MAX_SIZE 0xfc000000
65
+#define CONFIG_PREBOOT
66
+#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
67
+
68
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x2000000
69
+
70
+#ifndef CONFIG_SPL_BUILD
71
+/* usb mass storage */
72
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
73
+#define CONFIG_ROCKUSB_G_DNL_PID 0x350c
74
+
75
+#ifdef CONFIG_ARM64
76
+#define ENV_MEM_LAYOUT_SETTINGS \
77
+ "scriptaddr=0x00c00000\0" \
78
+ "pxefile_addr_r=0x00e00000\0" \
79
+ "fdt_addr_r=0x08300000\0" \
80
+ "kernel_addr_r=0x00280000\0" \
81
+ "kernel_addr_c=0x04080000\0" \
82
+ "ramdisk_addr_r=0x0a200000\0"
83
+#else
84
+#define ENV_MEM_LAYOUT_SETTINGS \
85
+ "scriptaddr=0x00000000\0" \
86
+ "pxefile_addr_r=0x00100000\0" \
87
+ "fdt_addr_r=0x08300000\0" \
88
+ "kernel_addr_c=0x02008000\0" \
89
+ "kernel_addr_r=0x00208000\0" \
90
+ "ramdisk_addr_r=0x0a200000\0"
91
+#endif
92
+
93
+#include <config_distro_bootcmd.h>
94
+
95
+#define CONFIG_EXTRA_ENV_SETTINGS \
96
+ ENV_MEM_LAYOUT_SETTINGS \
97
+ "partitions=" PARTS_RKIMG \
98
+ ROCKCHIP_DEVICE_SETTINGS \
99
+ RKIMG_DET_BOOTDEV \
100
+ BOOTENV
101
+#endif
102
+
103
+/* rockchip ohci host driver */
104
+#define CONFIG_USB_OHCI_NEW
105
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
106
+
107
+#define CONFIG_LIB_HW_RAND
108
+
109
+#endif
u-boot/include/configs/rk3562_common.h
....@@ -0,0 +1,84 @@
1
+/* SPDX-License-Identifier: GPL-2.0+ */
2
+/*
3
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
4
+ *
5
+ */
6
+
7
+#ifndef __CONFIG_RK3562_COMMON_H
8
+#define __CONFIG_RK3562_COMMON_H
9
+
10
+#include "rockchip-common.h"
11
+
12
+#define CONFIG_SPL_FRAMEWORK
13
+#define CONFIG_SPL_TEXT_BASE 0x00000000
14
+#define CONFIG_SPL_MAX_SIZE 0x00040000
15
+#define CONFIG_SPL_BSS_START_ADDR 0x03fe0000
16
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00010000
17
+#define CONFIG_SPL_STACK 0x03fe0000
18
+
19
+#define CONFIG_SYS_MALLOC_LEN (32 << 20)
20
+#define CONFIG_SYS_CBSIZE 1024
21
+#define CONFIG_SKIP_LOWLEVEL_INIT
22
+
23
+#ifdef CONFIG_SUPPORT_USBPLUG
24
+#define CONFIG_SYS_TEXT_BASE 0x00000000
25
+#else
26
+#define CONFIG_SYS_TEXT_BASE 0x00200000
27
+#endif
28
+
29
+#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
30
+#define CONFIG_SYS_LOAD_ADDR 0x00c00800
31
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
32
+#define COUNTER_FREQUENCY 24000000
33
+
34
+#define GICD_BASE 0xfe901000
35
+#define GICC_BASE 0xfe902000
36
+
37
+/* secure otp */
38
+#define OTP_UBOOT_ROLLBACK_OFFSET 0x350
39
+#define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */
40
+#define OTP_ALL_ONES_NUM_BITS 32
41
+#define OTP_SECURE_BOOT_ENABLE_ADDR 0x20
42
+#define OTP_SECURE_BOOT_ENABLE_SIZE 1
43
+#define OTP_RSA_HASH_ADDR 0x180
44
+#define OTP_RSA_HASH_SIZE 32
45
+
46
+/* MMC/SD IP block */
47
+#define CONFIG_BOUNCE_BUFFER
48
+
49
+#define CONFIG_SYS_SDRAM_BASE 0
50
+#define SDRAM_MAX_SIZE 0xfc000000
51
+#define CONFIG_PREBOOT
52
+#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
53
+
54
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x2000000
55
+
56
+#ifndef CONFIG_SPL_BUILD
57
+/* usb mass storage */
58
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
59
+#define CONFIG_ROCKUSB_G_DNL_PID 0x350d
60
+
61
+#define ENV_MEM_LAYOUT_SETTINGS \
62
+ "scriptaddr=0x00c00000\0" \
63
+ "pxefile_addr_r=0x00e00000\0" \
64
+ "fdt_addr_r=0x08300000\0" \
65
+ "kernel_addr_r=0x00400000\0" \
66
+ "kernel_addr_c=0x04080000\0" \
67
+ "ramdisk_addr_r=0x0a200000\0"
68
+
69
+#include <config_distro_bootcmd.h>
70
+
71
+#define CONFIG_EXTRA_ENV_SETTINGS \
72
+ ENV_MEM_LAYOUT_SETTINGS \
73
+ "partitions=" PARTS_RKIMG \
74
+ ROCKCHIP_DEVICE_SETTINGS \
75
+ RKIMG_DET_BOOTDEV \
76
+ BOOTENV
77
+#endif
78
+
79
+/* rockchip ohci host driver */
80
+#define CONFIG_USB_OHCI_NEW
81
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
82
+#define CONFIG_LIB_HW_RAND
83
+
84
+#endif
u-boot/include/configs/rk3588_common.h
....@@ -15,14 +15,18 @@
1515 #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000
1616 #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000
1717 #define CONFIG_SPL_STACK 0x03fe0000
18
+#ifdef CONFIG_SPL_LOAD_FIT_ADDRESS
19
+#undef CONFIG_SPL_LOAD_FIT_ADDRESS
20
+#endif
21
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000
1822
1923 #define CONFIG_SYS_MALLOC_LEN (32 << 20)
2024 #define CONFIG_SYS_CBSIZE 1024
2125 #define CONFIG_SKIP_LOWLEVEL_INIT
2226 #define CONFIG_SYS_TEXT_BASE 0x00200000
2327
24
-#define CONFIG_SYS_INIT_SP_ADDR 0x00400000
25
-#define CONFIG_SYS_LOAD_ADDR 0x00400800
28
+#define CONFIG_SYS_INIT_SP_ADDR 0x00600000
29
+#define CONFIG_SYS_LOAD_ADDR 0x00600800
2630 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
2731 #define COUNTER_FREQUENCY 24000000
2832
u-boot/include/configs/rockchip-common.h
....@@ -158,7 +158,7 @@
158158 "setenv devtype spinand; setenv devnum 0;" \
159159 "elif rksfc dev 1; then " \
160160 "setenv devtype spinor; setenv devnum 1;" \
161
- "else" \
161
+ "else;" \
162162 "setenv devtype ramdisk; setenv devnum 0;" \
163163 "fi; \0"
164164
u-boot/include/configs/rv1106_common.h
....@@ -12,7 +12,6 @@
1212 #define COUNTER_FREQUENCY 24000000
1313 #define CONFIG_SYS_MALLOC_LEN (16 << 20)
1414 #define CONFIG_SYS_CBSIZE 1024
15
-#define CONFIG_SKIP_LOWLEVEL_INIT
1615 #define CONFIG_SYS_NS16550_MEM32
1716
1817 #define CONFIG_SYS_TEXT_BASE 0x00200000
u-boot/include/configs/rv1126_common.h
....@@ -12,7 +12,6 @@
1212 #define COUNTER_FREQUENCY 24000000
1313 #define CONFIG_SYS_MALLOC_LEN (32 << 20)
1414 #define CONFIG_SYS_CBSIZE 1024
15
-#define CONFIG_SKIP_LOWLEVEL_INIT
1615 #define CONFIG_SYS_NS16550_MEM32
1716
1817 #ifdef CONFIG_SUPPORT_USBPLUG
....@@ -106,6 +105,7 @@
106105 #endif
107106 #endif
108107
108
+#define CONFIG_LIB_HW_RAND
109109 #define CONFIG_PREBOOT
110110
111111 #endif
u-boot/include/configs/woodburn_common.h
....@@ -168,10 +168,6 @@
168168 #define CONFIG_MXC_NAND_HWECC
169169 #define CONFIG_SYS_NAND_LARGEPAGE
170170
171
-#if 0
172
-#define CONFIG_MTD_DEBUG
173
-#define CONFIG_MTD_DEBUG_VERBOSE 7
174
-#endif
175171 #define CONFIG_SYS_NAND_ONFI_DETECTION
176172
177173 /*
u-boot/include/dm/fdtaddr.h
....@@ -35,6 +35,18 @@
3535 void *devfdt_get_addr_ptr(struct udevice *dev);
3636
3737 /**
38
+ * devfdt_remap_addr_index() - Return indexed pointer to the memory-mapped
39
+ * I/O address of the reg property of a device
40
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
41
+ * and @index is used to select which one is required
42
+ *
43
+ * @dev: Pointer to a device
44
+ *
45
+ * Return: Pointer to addr, or NULL if there is no such property
46
+ */
47
+void *devfdt_remap_addr_index(struct udevice *dev, int index);
48
+
49
+/**
3850 * devfdt_map_physmem() - Read device address from reg property of the
3951 * device node and map the address into CPU address
4052 * space.
u-boot/include/dm/read.h
....@@ -271,6 +271,18 @@
271271 int dev_read_addr_cells(struct udevice *dev);
272272
273273 /**
274
+ * dev_remap_addr_index() - Get the indexed reg property of a device
275
+ * as a memory-mapped I/O pointer
276
+ *
277
+ * @dev: Device to read from
278
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
279
+ * and @index is used to select which one is required
280
+ *
281
+ * Return: pointer or NULL if not found
282
+ */
283
+void *dev_remap_addr_index(struct udevice *dev, int index);
284
+
285
+/**
274286 * dev_read_size_cells() - Get the number of size cells for a device's node
275287 *
276288 * This walks back up the tree to find the closest #size-cells property
....@@ -588,6 +600,11 @@
588600 return fdt_address_cells(gd->fdt_blob, dev_of_offset(dev));
589601 }
590602
603
+static inline void *dev_remap_addr_index(struct udevice *dev, int index)
604
+{
605
+ return devfdt_remap_addr_index(dev, index);
606
+}
607
+
591608 static inline int dev_read_size_cells(struct udevice *dev)
592609 {
593610 /* NOTE: this call should walk up the parent stack */
u-boot/include/dm/uclass-id.h
....@@ -89,6 +89,7 @@
8989 UCLASS_THERMAL, /* Thermal sensor */
9090 UCLASS_TIMER, /* Timer device */
9191 UCLASS_TPM, /* Trusted Platform Module TIS interface */
92
+ UCLASS_UFS, /* Universal Flash Storage */
9293 UCLASS_USB, /* USB bus */
9394 UCLASS_USB_DEV_GENERIC, /* USB generic device */
9495 UCLASS_USB_HUB, /* USB hub */
u-boot/include/drm_modes.h
....@@ -38,7 +38,6 @@
3838 #define DRM_MODE_FLAG_PIXMUX (1 << 11)
3939 #define DRM_MODE_FLAG_DBLCLK (1 << 12)
4040 #define DRM_MODE_FLAG_CLKDIV2 (1 << 13)
41
-#define DRM_MODE_FLAG_PPIXDATA BIT(31)
4241 /*
4342 * When adding a new stereo mode don't forget to adjust DRM_MODE_FLAGS_3D_MAX
4443 * (define not exposed to user space).
....@@ -212,6 +211,95 @@
212211 bool invalid;
213212 };
214213
214
+/**
215
+ * enum drm_mode_status - hardware support status of a mode
216
+ * @MODE_OK: Mode OK
217
+ * @MODE_HSYNC: hsync out of range
218
+ * @MODE_VSYNC: vsync out of range
219
+ * @MODE_H_ILLEGAL: mode has illegal horizontal timings
220
+ * @MODE_V_ILLEGAL: mode has illegal vertical timings
221
+ * @MODE_BAD_WIDTH: requires an unsupported linepitch
222
+ * @MODE_NOMODE: no mode with a matching name
223
+ * @MODE_NO_INTERLACE: interlaced mode not supported
224
+ * @MODE_NO_DBLESCAN: doublescan mode not supported
225
+ * @MODE_NO_VSCAN: multiscan mode not supported
226
+ * @MODE_MEM: insufficient video memory
227
+ * @MODE_VIRTUAL_X: mode width too large for specified virtual size
228
+ * @MODE_VIRTUAL_Y: mode height too large for specified virtual size
229
+ * @MODE_MEM_VIRT: insufficient video memory given virtual size
230
+ * @MODE_NOCLOCK: no fixed clock available
231
+ * @MODE_CLOCK_HIGH: clock required is too high
232
+ * @MODE_CLOCK_LOW: clock required is too low
233
+ * @MODE_CLOCK_RANGE: clock/mode isn't in a ClockRange
234
+ * @MODE_BAD_HVALUE: horizontal timing was out of range
235
+ * @MODE_BAD_VVALUE: vertical timing was out of range
236
+ * @MODE_BAD_VSCAN: VScan value out of range
237
+ * @MODE_HSYNC_NARROW: horizontal sync too narrow
238
+ * @MODE_HSYNC_WIDE: horizontal sync too wide
239
+ * @MODE_HBLANK_NARROW: horizontal blanking too narrow
240
+ * @MODE_HBLANK_WIDE: horizontal blanking too wide
241
+ * @MODE_VSYNC_NARROW: vertical sync too narrow
242
+ * @MODE_VSYNC_WIDE: vertical sync too wide
243
+ * @MODE_VBLANK_NARROW: vertical blanking too narrow
244
+ * @MODE_VBLANK_WIDE: vertical blanking too wide
245
+ * @MODE_PANEL: exceeds panel dimensions
246
+ * @MODE_INTERLACE_WIDTH: width too large for interlaced mode
247
+ * @MODE_ONE_WIDTH: only one width is supported
248
+ * @MODE_ONE_HEIGHT: only one height is supported
249
+ * @MODE_ONE_SIZE: only one resolution is supported
250
+ * @MODE_NO_REDUCED: monitor doesn't accept reduced blanking
251
+ * @MODE_NO_STEREO: stereo modes not supported
252
+ * @MODE_NO_420: ycbcr 420 modes not supported
253
+ * @MODE_STALE: mode has become stale
254
+ * @MODE_BAD: unspecified reason
255
+ * @MODE_ERROR: error condition
256
+ *
257
+ * This enum is used to filter out modes not supported by the driver/hardware
258
+ * combination.
259
+ */
260
+enum drm_mode_status {
261
+ MODE_OK = 0,
262
+ MODE_HSYNC,
263
+ MODE_VSYNC,
264
+ MODE_H_ILLEGAL,
265
+ MODE_V_ILLEGAL,
266
+ MODE_BAD_WIDTH,
267
+ MODE_NOMODE,
268
+ MODE_NO_INTERLACE,
269
+ MODE_NO_DBLESCAN,
270
+ MODE_NO_VSCAN,
271
+ MODE_MEM,
272
+ MODE_VIRTUAL_X,
273
+ MODE_VIRTUAL_Y,
274
+ MODE_MEM_VIRT,
275
+ MODE_NOCLOCK,
276
+ MODE_CLOCK_HIGH,
277
+ MODE_CLOCK_LOW,
278
+ MODE_CLOCK_RANGE,
279
+ MODE_BAD_HVALUE,
280
+ MODE_BAD_VVALUE,
281
+ MODE_BAD_VSCAN,
282
+ MODE_HSYNC_NARROW,
283
+ MODE_HSYNC_WIDE,
284
+ MODE_HBLANK_NARROW,
285
+ MODE_HBLANK_WIDE,
286
+ MODE_VSYNC_NARROW,
287
+ MODE_VSYNC_WIDE,
288
+ MODE_VBLANK_NARROW,
289
+ MODE_VBLANK_WIDE,
290
+ MODE_PANEL,
291
+ MODE_INTERLACE_WIDTH,
292
+ MODE_ONE_WIDTH,
293
+ MODE_ONE_HEIGHT,
294
+ MODE_ONE_SIZE,
295
+ MODE_NO_REDUCED,
296
+ MODE_NO_STEREO,
297
+ MODE_NO_420,
298
+ MODE_STALE = -3,
299
+ MODE_BAD = -2,
300
+ MODE_ERROR = -1
301
+};
302
+
215303 /*
216304 * Subsystem independent description of a videomode.
217305 * Can be generated from struct display_timing.
....@@ -233,12 +321,16 @@
233321 };
234322
235323 struct drm_display_mode *drm_mode_create(void);
324
+void drm_mode_copy(struct drm_display_mode *dst,
325
+ const struct drm_display_mode *src);
236326 void drm_mode_destroy(struct drm_display_mode *mode);
237327 bool drm_mode_match(const struct drm_display_mode *mode1,
238328 const struct drm_display_mode *mode2,
239329 unsigned int match_flags);
240330 bool drm_mode_equal(const struct drm_display_mode *mode1,
241331 const struct drm_display_mode *mode2);
332
+void drm_display_mode_from_videomode(const struct videomode *vm,
333
+ struct drm_display_mode *dmode);
242334 void drm_display_mode_to_videomode(const struct drm_display_mode *dmode,
243335 struct videomode *vm);
244336
u-boot/include/dt-bindings/clock/rk3528-cru.h
....@@ -0,0 +1,754 @@
1
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2
+/*
3
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
4
+ * Author: Joseph Chen <chenjh@rock-chips.com>
5
+ */
6
+
7
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
8
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
9
+
10
+/* cru-clocks indices */
11
+
12
+/* core clocks */
13
+#define PLL_APLL 1
14
+#define PLL_CPLL 2
15
+#define PLL_GPLL 3
16
+#define PLL_PPLL 4
17
+#define PLL_DPLL 5
18
+#define ARMCLK 6
19
+
20
+#define XIN_OSC0_HALF 8
21
+#define CLK_MATRIX_50M_SRC 9
22
+#define CLK_MATRIX_100M_SRC 10
23
+#define CLK_MATRIX_150M_SRC 11
24
+#define CLK_MATRIX_200M_SRC 12
25
+#define CLK_MATRIX_250M_SRC 13
26
+#define CLK_MATRIX_300M_SRC 14
27
+#define CLK_MATRIX_339M_SRC 15
28
+#define CLK_MATRIX_400M_SRC 16
29
+#define CLK_MATRIX_500M_SRC 17
30
+#define CLK_MATRIX_600M_SRC 18
31
+#define CLK_UART0_SRC 19
32
+#define CLK_UART0_FRAC 20
33
+#define SCLK_UART0 21
34
+#define CLK_UART1_SRC 22
35
+#define CLK_UART1_FRAC 23
36
+#define SCLK_UART1 24
37
+#define CLK_UART2_SRC 25
38
+#define CLK_UART2_FRAC 26
39
+#define SCLK_UART2 27
40
+#define CLK_UART3_SRC 28
41
+#define CLK_UART3_FRAC 29
42
+#define SCLK_UART3 30
43
+#define CLK_UART4_SRC 31
44
+#define CLK_UART4_FRAC 32
45
+#define SCLK_UART4 33
46
+#define CLK_UART5_SRC 34
47
+#define CLK_UART5_FRAC 35
48
+#define SCLK_UART5 36
49
+#define CLK_UART6_SRC 37
50
+#define CLK_UART6_FRAC 38
51
+#define SCLK_UART6 39
52
+#define CLK_UART7_SRC 40
53
+#define CLK_UART7_FRAC 41
54
+#define SCLK_UART7 42
55
+#define CLK_I2S0_2CH_SRC 43
56
+#define CLK_I2S0_2CH_FRAC 44
57
+#define MCLK_I2S0_2CH_SAI_SRC 45
58
+#define CLK_I2S3_8CH_SRC 46
59
+#define CLK_I2S3_8CH_FRAC 47
60
+#define MCLK_I2S3_8CH_SAI_SRC 48
61
+#define CLK_I2S1_8CH_SRC 49
62
+#define CLK_I2S1_8CH_FRAC 50
63
+#define MCLK_I2S1_8CH_SAI_SRC 51
64
+#define CLK_I2S2_2CH_SRC 52
65
+#define CLK_I2S2_2CH_FRAC 53
66
+#define MCLK_I2S2_2CH_SAI_SRC 54
67
+#define CLK_SPDIF_SRC 55
68
+#define CLK_SPDIF_FRAC 56
69
+#define MCLK_SPDIF_SRC 57
70
+#define DCLK_VOP_SRC0 58
71
+#define DCLK_VOP_SRC1 59
72
+#define CLK_HSM 60
73
+#define CLK_CORE_SRC_ACS 63
74
+#define CLK_CORE_SRC_PVTMUX 65
75
+#define CLK_CORE_SRC 66
76
+#define CLK_CORE 67
77
+#define ACLK_M_CORE_BIU 68
78
+#define CLK_CORE_PVTPLL_SRC 69
79
+#define PCLK_DBG 70
80
+#define SWCLKTCK 71
81
+#define CLK_SCANHS_CORE 72
82
+#define CLK_SCANHS_ACLKM_CORE 73
83
+#define CLK_SCANHS_PCLK_DBG 74
84
+#define CLK_SCANHS_PCLK_CPU_BIU 76
85
+#define PCLK_CPU_ROOT 77
86
+#define PCLK_CORE_GRF 78
87
+#define PCLK_DAPLITE_BIU 79
88
+#define PCLK_CPU_BIU 80
89
+#define CLK_REF_PVTPLL_CORE 81
90
+#define ACLK_BUS_VOPGL_ROOT 85
91
+#define ACLK_BUS_VOPGL_BIU 86
92
+#define ACLK_BUS_H_ROOT 87
93
+#define ACLK_BUS_H_BIU 88
94
+#define ACLK_BUS_ROOT 89
95
+#define HCLK_BUS_ROOT 90
96
+#define PCLK_BUS_ROOT 91
97
+#define ACLK_BUS_M_ROOT 92
98
+#define ACLK_SYSMEM_BIU 93
99
+#define CLK_TIMER_ROOT 95
100
+#define ACLK_BUS_BIU 96
101
+#define HCLK_BUS_BIU 97
102
+#define PCLK_BUS_BIU 98
103
+#define PCLK_DFT2APB 99
104
+#define PCLK_BUS_GRF 100
105
+#define ACLK_BUS_M_BIU 101
106
+#define ACLK_GIC 102
107
+#define ACLK_SPINLOCK 103
108
+#define ACLK_DMAC 104
109
+#define PCLK_TIMER 105
110
+#define CLK_TIMER0 106
111
+#define CLK_TIMER1 107
112
+#define CLK_TIMER2 108
113
+#define CLK_TIMER3 109
114
+#define CLK_TIMER4 110
115
+#define CLK_TIMER5 111
116
+#define PCLK_JDBCK_DAP 112
117
+#define CLK_JDBCK_DAP 113
118
+#define PCLK_WDT_NS 114
119
+#define TCLK_WDT_NS 115
120
+#define HCLK_TRNG_NS 116
121
+#define PCLK_UART0 117
122
+#define CLK_CORE_CRYPTO 119
123
+#define CLK_PKA_CRYPTO 120
124
+#define ACLK_CRYPTO 121
125
+#define HCLK_CRYPTO 122
126
+#define PCLK_DMA2DDR 123
127
+#define ACLK_DMA2DDR 124
128
+#define PCLK_PWM0 126
129
+#define CLK_PWM0 127
130
+#define CLK_CAPTURE_PWM0 128
131
+#define PCLK_PWM1 129
132
+#define CLK_PWM1 130
133
+#define CLK_CAPTURE_PWM1 131
134
+#define PCLK_SCR 134
135
+#define ACLK_DCF 135
136
+#define PCLK_INTMUX 138
137
+#define CLK_PPLL_I 141
138
+#define CLK_PPLL_MUX 142
139
+#define CLK_PPLL_100M_MATRIX 143
140
+#define CLK_PPLL_50M_MATRIX 144
141
+#define CLK_REF_PCIE_INNER_PHY 145
142
+#define CLK_REF_PCIE_100M_PHY 146
143
+#define ACLK_VPU_L_ROOT 147
144
+#define CLK_GMAC1_VPU_25M 148
145
+#define CLK_PPLL_125M_MATRIX 149
146
+#define ACLK_VPU_ROOT 150
147
+#define HCLK_VPU_ROOT 151
148
+#define PCLK_VPU_ROOT 152
149
+#define ACLK_VPU_BIU 153
150
+#define HCLK_VPU_BIU 154
151
+#define PCLK_VPU_BIU 155
152
+#define ACLK_VPU 156
153
+#define HCLK_VPU 157
154
+#define PCLK_CRU_PCIE 158
155
+#define PCLK_VPU_GRF 159
156
+#define HCLK_SFC 160
157
+#define SCLK_SFC 161
158
+#define CCLK_SRC_EMMC 163
159
+#define HCLK_EMMC 164
160
+#define ACLK_EMMC 165
161
+#define BCLK_EMMC 166
162
+#define TCLK_EMMC 167
163
+#define PCLK_GPIO1 168
164
+#define DBCLK_GPIO1 169
165
+#define ACLK_VPU_L_BIU 172
166
+#define PCLK_VPU_IOC 173
167
+#define HCLK_SAI_I2S0 174
168
+#define MCLK_SAI_I2S0 175
169
+#define HCLK_SAI_I2S2 176
170
+#define MCLK_SAI_I2S2 177
171
+#define PCLK_ACODEC 178
172
+#define MCLK_ACODEC_TX 179
173
+#define PCLK_GPIO3 186
174
+#define DBCLK_GPIO3 187
175
+#define PCLK_SPI1 189
176
+#define CLK_SPI1 190
177
+#define SCLK_IN_SPI1 191
178
+#define PCLK_UART2 192
179
+#define PCLK_UART5 194
180
+#define PCLK_UART6 196
181
+#define PCLK_UART7 198
182
+#define PCLK_I2C3 200
183
+#define CLK_I2C3 201
184
+#define PCLK_I2C5 202
185
+#define CLK_I2C5 203
186
+#define PCLK_I2C6 204
187
+#define CLK_I2C6 205
188
+#define ACLK_MAC_VPU 206
189
+#define PCLK_MAC_VPU 207
190
+#define CLK_GMAC1_RMII_VPU 209
191
+#define CLK_GMAC1_SRC_VPU 210
192
+#define PCLK_PCIE 215
193
+#define CLK_PCIE_AUX 216
194
+#define ACLK_PCIE 217
195
+#define HCLK_PCIE_SLV 218
196
+#define HCLK_PCIE_DBI 219
197
+#define PCLK_PCIE_PHY 220
198
+#define PCLK_PIPE_GRF 221
199
+#define CLK_PIPE_USB3OTG_COMBO 230
200
+#define CLK_UTMI_USB3OTG 232
201
+#define CLK_PCIE_PIPE_PHY 235
202
+#define CCLK_SRC_SDIO0 240
203
+#define HCLK_SDIO0 241
204
+#define CCLK_SRC_SDIO1 244
205
+#define HCLK_SDIO1 245
206
+#define CLK_TS_0 246
207
+#define CLK_TS_1 247
208
+#define PCLK_CAN2 250
209
+#define CLK_CAN2 251
210
+#define PCLK_CAN3 252
211
+#define CLK_CAN3 253
212
+#define PCLK_SARADC 256
213
+#define CLK_SARADC 257
214
+#define PCLK_TSADC 258
215
+#define CLK_TSADC 259
216
+#define CLK_TSADC_TSEN 260
217
+#define ACLK_USB3OTG 261
218
+#define CLK_REF_USB3OTG 262
219
+#define CLK_SUSPEND_USB3OTG 263
220
+#define ACLK_GPU_ROOT 269
221
+#define PCLK_GPU_ROOT 270
222
+#define ACLK_GPU_BIU 271
223
+#define PCLK_GPU_BIU 272
224
+#define ACLK_GPU 273
225
+#define CLK_GPU_PVTPLL_SRC 274
226
+#define ACLK_GPU_MALI 275
227
+#define HCLK_RKVENC_ROOT 281
228
+#define ACLK_RKVENC_ROOT 282
229
+#define PCLK_RKVENC_ROOT 283
230
+#define HCLK_RKVENC_BIU 284
231
+#define ACLK_RKVENC_BIU 285
232
+#define PCLK_RKVENC_BIU 286
233
+#define HCLK_RKVENC 287
234
+#define ACLK_RKVENC 288
235
+#define CLK_CORE_RKVENC 289
236
+#define HCLK_SAI_I2S1 290
237
+#define MCLK_SAI_I2S1 291
238
+#define PCLK_I2C1 292
239
+#define CLK_I2C1 293
240
+#define PCLK_I2C0 294
241
+#define CLK_I2C0 295
242
+#define CLK_UART_JTAG 296
243
+#define PCLK_SPI0 297
244
+#define CLK_SPI0 298
245
+#define SCLK_IN_SPI0 299
246
+#define PCLK_GPIO4 300
247
+#define DBCLK_GPIO4 301
248
+#define PCLK_RKVENC_IOC 302
249
+#define HCLK_SPDIF 308
250
+#define MCLK_SPDIF 309
251
+#define HCLK_PDM 310
252
+#define MCLK_PDM 311
253
+#define PCLK_UART1 315
254
+#define PCLK_UART3 317
255
+#define PCLK_RKVENC_GRF 319
256
+#define PCLK_CAN0 320
257
+#define CLK_CAN0 321
258
+#define PCLK_CAN1 322
259
+#define CLK_CAN1 323
260
+#define ACLK_VO_ROOT 324
261
+#define HCLK_VO_ROOT 325
262
+#define PCLK_VO_ROOT 326
263
+#define ACLK_VO_BIU 327
264
+#define HCLK_VO_BIU 328
265
+#define PCLK_VO_BIU 329
266
+#define HCLK_RGA2E 330
267
+#define ACLK_RGA2E 331
268
+#define CLK_CORE_RGA2E 332
269
+#define HCLK_VDPP 333
270
+#define ACLK_VDPP 334
271
+#define CLK_CORE_VDPP 335
272
+#define PCLK_VO_GRF 336
273
+#define PCLK_CRU 337
274
+#define ACLK_VOP_ROOT 338
275
+#define ACLK_VOP_BIU 339
276
+#define HCLK_VOP 340
277
+#define DCLK_VOP0 341
278
+#define DCLK_VOP1 342
279
+#define ACLK_VOP 343
280
+#define PCLK_HDMI 344
281
+#define CLK_SFR_HDMI 345
282
+#define CLK_CEC_HDMI 346
283
+#define CLK_SPDIF_HDMI 347
284
+#define CLK_HDMIPHY_TMDSSRC 348
285
+#define CLK_HDMIPHY_PREP 349
286
+#define PCLK_HDMIPHY 352
287
+#define HCLK_HDCP_KEY 354
288
+#define ACLK_HDCP 355
289
+#define HCLK_HDCP 356
290
+#define PCLK_HDCP 357
291
+#define HCLK_CVBS 358
292
+#define DCLK_CVBS 359
293
+#define DCLK_4X_CVBS 360
294
+#define ACLK_JPEG_DECODER 361
295
+#define HCLK_JPEG_DECODER 362
296
+#define ACLK_VO_L_ROOT 375
297
+#define ACLK_VO_L_BIU 376
298
+#define ACLK_MAC_VO 377
299
+#define PCLK_MAC_VO 378
300
+#define CLK_GMAC0_SRC 379
301
+#define CLK_GMAC0_RMII_50M 380
302
+#define CLK_GMAC0_TX 381
303
+#define CLK_GMAC0_RX 382
304
+#define ACLK_JPEG_ROOT 385
305
+#define ACLK_JPEG_BIU 386
306
+#define HCLK_SAI_I2S3 387
307
+#define MCLK_SAI_I2S3 388
308
+#define CLK_MACPHY 398
309
+#define PCLK_VCDCPHY 399
310
+#define PCLK_GPIO2 404
311
+#define DBCLK_GPIO2 405
312
+#define PCLK_VO_IOC 406
313
+#define CCLK_SRC_SDMMC0 407
314
+#define HCLK_SDMMC0 408
315
+#define PCLK_OTPC_NS 411
316
+#define CLK_SBPI_OTPC_NS 412
317
+#define CLK_USER_OTPC_NS 413
318
+#define CLK_HDMIHDP0 415
319
+#define HCLK_USBHOST 416
320
+#define HCLK_USBHOST_ARB 417
321
+#define CLK_USBHOST_OHCI 418
322
+#define CLK_USBHOST_UTMI 419
323
+#define PCLK_UART4 420
324
+#define PCLK_I2C4 422
325
+#define CLK_I2C4 423
326
+#define PCLK_I2C7 424
327
+#define CLK_I2C7 425
328
+#define PCLK_USBPHY 426
329
+#define CLK_REF_USBPHY 427
330
+#define HCLK_RKVDEC_ROOT 433
331
+#define ACLK_RKVDEC_ROOT_NDFT 434
332
+#define PCLK_DDRPHY_CRU 435
333
+#define HCLK_RKVDEC_BIU 436
334
+#define ACLK_RKVDEC_BIU 437
335
+#define ACLK_RKVDEC 439
336
+#define HCLK_RKVDEC 440
337
+#define CLK_HEVC_CA_RKVDEC 441
338
+#define ACLK_RKVDEC_PVTMUX_ROOT 442
339
+#define CLK_RKVDEC_PVTPLL_SRC 443
340
+#define PCLK_DDR_ROOT 449
341
+#define PCLK_DDR_BIU 450
342
+#define PCLK_DDRC 451
343
+#define PCLK_DDRMON 452
344
+#define CLK_TIMER_DDRMON 453
345
+#define PCLK_MSCH_BIU 454
346
+#define PCLK_DDR_GRF 455
347
+#define PCLK_DDR_HWLP 456
348
+#define PCLK_DDRPHY 457
349
+#define CLK_MSCH_BIU 463
350
+#define ACLK_DDR_UPCTL 464
351
+#define CLK_DDR_UPCTL 465
352
+#define CLK_DDRMON 466
353
+#define ACLK_DDR_SCRAMBLE 467
354
+#define ACLK_SPLIT 468
355
+#define CLK_DDRC_SRC 470
356
+#define CLK_DDR_PHY 471
357
+#define PCLK_OTPC_S 472
358
+#define CLK_SBPI_OTPC_S 473
359
+#define CLK_USER_OTPC_S 474
360
+#define PCLK_KEYREADER 475
361
+#define PCLK_BUS_SGRF 476
362
+#define PCLK_STIMER 477
363
+#define CLK_STIMER0 478
364
+#define CLK_STIMER1 479
365
+#define PCLK_WDT_S 480
366
+#define TCLK_WDT_S 481
367
+#define HCLK_TRNG_S 482
368
+#define PCLK_KLAD 483
369
+#define HCLK_CRYPTO_S 484
370
+#define HCLK_KLAD 485
371
+#define HCLK_BOOTROM 486
372
+#define PCLK_DCF 487
373
+#define ACLK_SYSMEM 488
374
+#define HCLK_TSP 489
375
+#define ACLK_TSP 490
376
+#define CLK_CORE_TSP 491
377
+#define CLK_OTPC_ARB 492
378
+#define PCLK_OTP_MASK 493
379
+#define CLK_PMC_OTP 494
380
+#define PCLK_PMU_ROOT 495
381
+#define HCLK_PMU_ROOT 496
382
+#define PCLK_I2C2 497
383
+#define CLK_I2C2 498
384
+#define HCLK_PMU_BIU 500
385
+#define PCLK_PMU_BIU 501
386
+#define FCLK_MCU 502
387
+#define RTC_CLK_MCU 504
388
+#define PCLK_OSCCHK 505
389
+#define CLK_PMU_MCU_JTAG 506
390
+#define PCLK_PMU 508
391
+#define PCLK_GPIO0 509
392
+#define DBCLK_GPIO0 510
393
+#define XIN_OSC0_DIV 511
394
+#define CLK_DEEPSLOW 512
395
+#define CLK_DDR_FAIL_SAFE 513
396
+#define PCLK_PMU_HP_TIMER 514
397
+#define CLK_PMU_HP_TIMER 515
398
+#define CLK_PMU_32K_HP_TIMER 516
399
+#define PCLK_PMU_IOC 517
400
+#define PCLK_PMU_CRU 518
401
+#define PCLK_PMU_GRF 519
402
+#define PCLK_PMU_WDT 520
403
+#define TCLK_PMU_WDT 521
404
+#define PCLK_PMU_MAILBOX 522
405
+#define PCLK_SCRKEYGEN 524
406
+#define CLK_SCRKEYGEN 525
407
+#define CLK_PVTM_OSCCHK 526
408
+#define CLK_REFOUT 530
409
+#define CLK_PVTM_PMU 532
410
+#define PCLK_PVTM_PMU 533
411
+#define PCLK_PMU_SGRF 534
412
+#define HCLK_PMU_SRAM 535
413
+#define CLK_UART0 536
414
+#define CLK_UART1 537
415
+#define CLK_UART2 538
416
+#define CLK_UART3 539
417
+#define CLK_UART4 540
418
+#define CLK_UART5 541
419
+#define CLK_UART6 542
420
+#define CLK_UART7 543
421
+#define MCLK_I2S0_2CH_SAI_SRC_PRE 544
422
+#define MCLK_I2S1_8CH_SAI_SRC_PRE 545
423
+#define MCLK_I2S2_2CH_SAI_SRC_PRE 546
424
+#define MCLK_I2S3_8CH_SAI_SRC_PRE 547
425
+#define MCLK_SDPDIF_SRC_PRE 548
426
+#define CLK_NR_CLKS (MCLK_SDPDIF_SRC_PRE + 1)
427
+
428
+/* grf-clocks indices */
429
+#define SCLK_SDMMC_DRV 1
430
+#define SCLK_SDMMC_SAMPLE 2
431
+#define SCLK_SDIO0_DRV 3
432
+#define SCLK_SDIO0_SAMPLE 4
433
+#define SCLK_SDIO1_DRV 5
434
+#define SCLK_SDIO1_SAMPLE 6
435
+#define CLK_NR_GRF_CLKS (SCLK_SDIO1_SAMPLE + 1)
436
+
437
+/* scmi-clocks indices */
438
+#define SCMI_PCLK_KEYREADER 0
439
+#define SCMI_HCLK_KLAD 1
440
+#define SCMI_PCLK_KLAD 2
441
+#define SCMI_HCLK_TRNG_S 3
442
+#define SCMI_HCLK_CRYPTO_S 4
443
+#define SCMI_PCLK_WDT_S 5
444
+#define SCMI_TCLK_WDT_S 6
445
+#define SCMI_PCLK_STIMER 7
446
+#define SCMI_CLK_STIMER0 8
447
+#define SCMI_CLK_STIMER1 9
448
+#define SCMI_PCLK_OTP_MASK 10
449
+#define SCMI_PCLK_OTPC_S 11
450
+#define SCMI_CLK_SBPI_OTPC_S 12
451
+#define SCMI_CLK_USER_OTPC_S 13
452
+#define SCMI_CLK_PMC_OTP 14
453
+#define SCMI_CLK_OTPC_ARB 15
454
+#define SCMI_CLK_CORE_TSP 16
455
+#define SCMI_ACLK_TSP 17
456
+#define SCMI_HCLK_TSP 18
457
+#define SCMI_PCLK_DCF 19
458
+#define SCMI_CLK_DDR 20
459
+#define SCMI_CLK_CPU 21
460
+#define SCMI_CLK_GPU 22
461
+#define SCMI_CORE_CRYPTO 23
462
+#define SCMI_ACLK_CRYPTO 24
463
+#define SCMI_PKA_CRYPTO 25
464
+#define SCMI_HCLK_CRYPTO 26
465
+#define SCMI_CORE_CRYPTO_S 27
466
+#define SCMI_ACLK_CRYPTO_S 28
467
+#define SCMI_PKA_CRYPTO_S 29
468
+#define SCMI_CORE_KLAD 30
469
+#define SCMI_ACLK_KLAD 31
470
+#define SCMI_HCLK_TRNG 32
471
+
472
+// CRU_SOFTRST_CON03(Offset:0xA0C)
473
+#define SRST_NCOREPORESET0 0x00000030
474
+#define SRST_NCOREPORESET1 0x00000031
475
+#define SRST_NCOREPORESET2 0x00000032
476
+#define SRST_NCOREPORESET3 0x00000033
477
+#define SRST_NCORESET0 0x00000034
478
+#define SRST_NCORESET1 0x00000035
479
+#define SRST_NCORESET2 0x00000036
480
+#define SRST_NCORESET3 0x00000037
481
+#define SRST_NL2RESET 0x00000038
482
+#define SRST_ARESETN_M_CORE_BIU 0x00000039
483
+#define SRST_RESETN_CORE_CRYPTO 0x0000003A
484
+
485
+// CRU_SOFTRST_CON05(Offset:0xA14)
486
+#define SRST_PRESETN_DBG 0x0000005D
487
+#define SRST_POTRESETN_DBG 0x0000005E
488
+#define SRST_NTRESETN_DBG 0x0000005F
489
+
490
+// CRU_SOFTRST_CON06(Offset:0xA18)
491
+#define SRST_PRESETN_CORE_GRF 0x00000062
492
+#define SRST_PRESETN_DAPLITE_BIU 0x00000063
493
+#define SRST_PRESETN_CPU_BIU 0x00000064
494
+#define SRST_RESETN_REF_PVTPLL_CORE 0x00000067
495
+
496
+// CRU_SOFTRST_CON08(Offset:0xA20)
497
+#define SRST_ARESETN_BUS_VOPGL_BIU 0x00000081
498
+#define SRST_ARESETN_BUS_H_BIU 0x00000083
499
+#define SRST_ARESETN_SYSMEM_BIU 0x00000088
500
+#define SRST_ARESETN_BUS_BIU 0x0000008A
501
+#define SRST_HRESETN_BUS_BIU 0x0000008B
502
+#define SRST_PRESETN_BUS_BIU 0x0000008C
503
+#define SRST_PRESETN_DFT2APB 0x0000008D
504
+#define SRST_PRESETN_BUS_GRF 0x0000008F
505
+
506
+// CRU_SOFTRST_CON09(Offset:0xA24)
507
+#define SRST_ARESETN_BUS_M_BIU 0x00000090
508
+#define SRST_ARESETN_GIC 0x00000091
509
+#define SRST_ARESETN_SPINLOCK 0x00000092
510
+#define SRST_ARESETN_DMAC 0x00000094
511
+#define SRST_PRESETN_TIMER 0x00000095
512
+#define SRST_RESETN_TIMER0 0x00000096
513
+#define SRST_RESETN_TIMER1 0x00000097
514
+#define SRST_RESETN_TIMER2 0x00000098
515
+#define SRST_RESETN_TIMER3 0x00000099
516
+#define SRST_RESETN_TIMER4 0x0000009A
517
+#define SRST_RESETN_TIMER5 0x0000009B
518
+#define SRST_PRESETN_JDBCK_DAP 0x0000009C
519
+#define SRST_RESETN_JDBCK_DAP 0x0000009D
520
+#define SRST_PRESETN_WDT_NS 0x0000009F
521
+
522
+// CRU_SOFTRST_CON10(Offset:0xA28)
523
+#define SRST_TRESETN_WDT_NS 0x000000A0
524
+#define SRST_HRESETN_TRNG_NS 0x000000A3
525
+#define SRST_PRESETN_UART0 0x000000A7
526
+#define SRST_SRESETN_UART0 0x000000A8
527
+#define SRST_RESETN_PKA_CRYPTO 0x000000AA
528
+#define SRST_ARESETN_CRYPTO 0x000000AB
529
+#define SRST_HRESETN_CRYPTO 0x000000AC
530
+#define SRST_PRESETN_DMA2DDR 0x000000AD
531
+#define SRST_ARESETN_DMA2DDR 0x000000AE
532
+
533
+// CRU_SOFTRST_CON11(Offset:0xA2C)
534
+#define SRST_PRESETN_PWM0 0x000000B4
535
+#define SRST_RESETN_PWM0 0x000000B5
536
+#define SRST_PRESETN_PWM1 0x000000B7
537
+#define SRST_RESETN_PWM1 0x000000B8
538
+#define SRST_PRESETN_SCR 0x000000BA
539
+#define SRST_ARESETN_DCF 0x000000BB
540
+#define SRST_PRESETN_INTMUX 0x000000BC
541
+
542
+// CRU_SOFTRST_CON25(Offset:0xA64)
543
+#define SRST_ARESETN_VPU_BIU 0x00000196
544
+#define SRST_HRESETN_VPU_BIU 0x00000197
545
+#define SRST_PRESETN_VPU_BIU 0x00000198
546
+#define SRST_ARESETN_VPU 0x00000199
547
+#define SRST_HRESETN_VPU 0x0000019A
548
+#define SRST_PRESETN_CRU_PCIE 0x0000019B
549
+#define SRST_PRESETN_VPU_GRF 0x0000019C
550
+#define SRST_HRESETN_SFC 0x0000019D
551
+#define SRST_SRESETN_SFC 0x0000019E
552
+#define SRST_CRESETN_EMMC 0x0000019F
553
+
554
+// CRU_SOFTRST_CON26(Offset:0xA68)
555
+#define SRST_HRESETN_EMMC 0x000001A0
556
+#define SRST_ARESETN_EMMC 0x000001A1
557
+#define SRST_BRESETN_EMMC 0x000001A2
558
+#define SRST_TRESETN_EMMC 0x000001A3
559
+#define SRST_PRESETN_GPIO1 0x000001A4
560
+#define SRST_DBRESETN_GPIO1 0x000001A5
561
+#define SRST_ARESETN_VPU_L_BIU 0x000001A6
562
+#define SRST_PRESETN_VPU_IOC 0x000001A8
563
+#define SRST_HRESETN_SAI_I2S0 0x000001A9
564
+#define SRST_MRESETN_SAI_I2S0 0x000001AA
565
+#define SRST_HRESETN_SAI_I2S2 0x000001AB
566
+#define SRST_MRESETN_SAI_I2S2 0x000001AC
567
+#define SRST_PRESETN_ACODEC 0x000001AD
568
+
569
+// CRU_SOFTRST_CON27(Offset:0xA6C)
570
+#define SRST_PRESETN_GPIO3 0x000001B0
571
+#define SRST_DBRESETN_GPIO3 0x000001B1
572
+#define SRST_PRESETN_SPI1 0x000001B4
573
+#define SRST_RESETN_SPI1 0x000001B5
574
+#define SRST_PRESETN_UART2 0x000001B7
575
+#define SRST_SRESETN_UART2 0x000001B8
576
+#define SRST_PRESETN_UART5 0x000001B9
577
+#define SRST_SRESETN_UART5 0x000001BA
578
+#define SRST_PRESETN_UART6 0x000001BB
579
+#define SRST_SRESETN_UART6 0x000001BC
580
+#define SRST_PRESETN_UART7 0x000001BD
581
+#define SRST_SRESETN_UART7 0x000001BE
582
+#define SRST_PRESETN_I2C3 0x000001BF
583
+
584
+// CRU_SOFTRST_CON28(Offset:0xA70)
585
+#define SRST_RESETN_I2C3 0x000001C0
586
+#define SRST_PRESETN_I2C5 0x000001C1
587
+#define SRST_RESETN_I2C5 0x000001C2
588
+#define SRST_PRESETN_I2C6 0x000001C3
589
+#define SRST_RESETN_I2C6 0x000001C4
590
+#define SRST_ARESETN_MAC 0x000001C5
591
+
592
+// CRU_SOFTRST_CON30(Offset:0xA78)
593
+#define SRST_PRESETN_PCIE 0x000001E1
594
+#define SRST_RESETN_PCIE_PIPE_PHY 0x000001E2
595
+#define SRST_RESETN_PCIE_POWER_UP 0x000001E3
596
+#define SRST_PRESETN_PCIE_PHY 0x000001E6
597
+#define SRST_PRESETN_PIPE_GRF 0x000001E7
598
+
599
+// CRU_SOFTRST_CON32(Offset:0xA80)
600
+#define SRST_HRESETN_SDIO0 0x00000202
601
+#define SRST_HRESETN_SDIO1 0x00000204
602
+#define SRST_RESETN_TS_0 0x00000205
603
+#define SRST_RESETN_TS_1 0x00000206
604
+#define SRST_PRESETN_CAN2 0x00000207
605
+#define SRST_RESETN_CAN2 0x00000208
606
+#define SRST_PRESETN_CAN3 0x00000209
607
+#define SRST_RESETN_CAN3 0x0000020A
608
+#define SRST_PRESETN_SARADC 0x0000020B
609
+#define SRST_RESETN_SARADC 0x0000020C
610
+#define SRST_RESETN_SARADC_PHY 0x0000020D
611
+#define SRST_PRESETN_TSADC 0x0000020E
612
+#define SRST_RESETN_TSADC 0x0000020F
613
+
614
+// CRU_SOFTRST_CON33(Offset:0xA84)
615
+#define SRST_ARESETN_USB3OTG 0x00000211
616
+
617
+// CRU_SOFTRST_CON34(Offset:0xA88)
618
+#define SRST_ARESETN_GPU_BIU 0x00000223
619
+#define SRST_PRESETN_GPU_BIU 0x00000225
620
+#define SRST_ARESETN_GPU 0x00000228
621
+#define SRST_RESETN_REF_PVTPLL_GPU 0x00000229
622
+
623
+// CRU_SOFTRST_CON36(Offset:0xA90)
624
+#define SRST_HRESETN_RKVENC_BIU 0x00000243
625
+#define SRST_ARESETN_RKVENC_BIU 0x00000244
626
+#define SRST_PRESETN_RKVENC_BIU 0x00000245
627
+#define SRST_HRESETN_RKVENC 0x00000246
628
+#define SRST_ARESETN_RKVENC 0x00000247
629
+#define SRST_RESETN_CORE_RKVENC 0x00000248
630
+#define SRST_HRESETN_SAI_I2S1 0x00000249
631
+#define SRST_MRESETN_SAI_I2S1 0x0000024A
632
+#define SRST_PRESETN_I2C1 0x0000024B
633
+#define SRST_RESETN_I2C1 0x0000024C
634
+#define SRST_PRESETN_I2C0 0x0000024D
635
+#define SRST_RESETN_I2C0 0x0000024E
636
+
637
+// CRU_SOFTRST_CON37(Offset:0xA94)
638
+#define SRST_PRESETN_SPI0 0x00000252
639
+#define SRST_RESETN_SPI0 0x00000253
640
+#define SRST_PRESETN_GPIO4 0x00000258
641
+#define SRST_DBRESETN_GPIO4 0x00000259
642
+#define SRST_PRESETN_RKVENC_IOC 0x0000025A
643
+#define SRST_HRESETN_SPDIF 0x0000025E
644
+#define SRST_MRESETN_SPDIF 0x0000025F
645
+
646
+// CRU_SOFTRST_CON38(Offset:0xA98)
647
+#define SRST_HRESETN_PDM 0x00000260
648
+#define SRST_MRESETN_PDM 0x00000261
649
+#define SRST_PRESETN_UART1 0x00000262
650
+#define SRST_SRESETN_UART1 0x00000263
651
+#define SRST_PRESETN_UART3 0x00000264
652
+#define SRST_SRESETN_UART3 0x00000265
653
+#define SRST_PRESETN_RKVENC_GRF 0x00000266
654
+#define SRST_PRESETN_CAN0 0x00000267
655
+#define SRST_RESETN_CAN0 0x00000268
656
+#define SRST_PRESETN_CAN1 0x00000269
657
+#define SRST_RESETN_CAN1 0x0000026A
658
+
659
+// CRU_SOFTRST_CON39(Offset:0xA9C)
660
+#define SRST_ARESETN_VO_BIU 0x00000273
661
+#define SRST_HRESETN_VO_BIU 0x00000274
662
+#define SRST_PRESETN_VO_BIU 0x00000275
663
+#define SRST_HRESETN_RGA2E 0x00000277
664
+#define SRST_ARESETN_RGA2E 0x00000278
665
+#define SRST_RESETN_CORE_RGA2E 0x00000279
666
+#define SRST_HRESETN_VDPP 0x0000027A
667
+#define SRST_ARESETN_VDPP 0x0000027B
668
+#define SRST_RESETN_CORE_VDPP 0x0000027C
669
+#define SRST_PRESETN_VO_GRF 0x0000027D
670
+#define SRST_PRESETN_CRU 0x0000027F
671
+
672
+// CRU_SOFTRST_CON40(Offset:0xAA0)
673
+#define SRST_ARESETN_VOP_BIU 0x00000281
674
+#define SRST_HRESETN_VOP 0x00000282
675
+#define SRST_DRESETN_VOP0 0x00000283
676
+#define SRST_DRESETN_VOP1 0x00000284
677
+#define SRST_ARESETN_VOP 0x00000285
678
+#define SRST_PRESETN_HDMI 0x00000286
679
+#define SRST_HDMI_RESETN 0x00000287
680
+#define SRST_PRESETN_HDMIPHY 0x0000028E
681
+#define SRST_HRESETN_HDCP_KEY 0x0000028F
682
+
683
+// CRU_SOFTRST_CON41(Offset:0xAA4)
684
+#define SRST_ARESETN_HDCP 0x00000290
685
+#define SRST_HRESETN_HDCP 0x00000291
686
+#define SRST_PRESETN_HDCP 0x00000292
687
+#define SRST_HRESETN_CVBS 0x00000293
688
+#define SRST_DRESETN_CVBS_VOP 0x00000294
689
+#define SRST_DRESETN_4X_CVBS_VOP 0x00000295
690
+#define SRST_ARESETN_JPEG_DECODER 0x00000296
691
+#define SRST_HRESETN_JPEG_DECODER 0x00000297
692
+#define SRST_ARESETN_VO_L_BIU 0x00000299
693
+#define SRST_ARESETN_MAC_VO 0x0000029A
694
+
695
+// CRU_SOFTRST_CON42(Offset:0xAA8)
696
+#define SRST_ARESETN_JPEG_BIU 0x000002A0
697
+#define SRST_HRESETN_SAI_I2S3 0x000002A1
698
+#define SRST_MRESETN_SAI_I2S3 0x000002A2
699
+#define SRST_RESETN_MACPHY 0x000002A3
700
+#define SRST_PRESETN_VCDCPHY 0x000002A4
701
+#define SRST_PRESETN_GPIO2 0x000002A5
702
+#define SRST_DBRESETN_GPIO2 0x000002A6
703
+#define SRST_PRESETN_VO_IOC 0x000002A7
704
+#define SRST_HRESETN_SDMMC0 0x000002A9
705
+#define SRST_PRESETN_OTPC_NS 0x000002AB
706
+#define SRST_RESETN_SBPI_OTPC_NS 0x000002AC
707
+#define SRST_RESETN_USER_OTPC_NS 0x000002AD
708
+
709
+// CRU_SOFTRST_CON43(Offset:0xAAC)
710
+#define SRST_RESETN_HDMIHDP0 0x000002B2
711
+#define SRST_HRESETN_USBHOST 0x000002B3
712
+#define SRST_HRESETN_USBHOST_ARB 0x000002B4
713
+#define SRST_RESETN_HOST_UTMI 0x000002B6
714
+#define SRST_PRESETN_UART4 0x000002B7
715
+#define SRST_SRESETN_UART4 0x000002B8
716
+#define SRST_PRESETN_I2C4 0x000002B9
717
+#define SRST_RESETN_I2C4 0x000002BA
718
+#define SRST_PRESETN_I2C7 0x000002BB
719
+#define SRST_RESETN_I2C7 0x000002BC
720
+#define SRST_PRESETN_USBPHY 0x000002BD
721
+#define SRST_RESETN_USBPHY_POR 0x000002BE
722
+#define SRST_RESETN_USBPHY_OTG 0x000002BF
723
+
724
+// CRU_SOFTRST_CON44(Offset:0xAB0)
725
+#define SRST_RESETN_USBPHY_HOST 0x000002C0
726
+#define SRST_PRESETN_DDRPHY_CRU 0x000002C4
727
+#define SRST_HRESETN_RKVDEC_BIU 0x000002C6
728
+#define SRST_ARESETN_RKVDEC_BIU 0x000002C7
729
+#define SRST_ARESETN_RKVDEC 0x000002C8
730
+#define SRST_HRESETN_RKVDEC 0x000002C9
731
+#define SRST_RESETN_HEVC_CA_RKVDEC 0x000002CB
732
+#define SRST_RESETN_REF_PVTPLL_RKVDEC 0x000002CC
733
+
734
+// CRU_SOFTRST_CON45(Offset:0xAB4)
735
+#define SRST_PRESETN_DDR_BIU 0x000002D1
736
+#define SRST_PRESETN_DDRC 0x000002D2
737
+#define SRST_PRESETN_DDRMON 0x000002D3
738
+#define SRST_RESETN_TIMER_DDRMON 0x000002D4
739
+#define SRST_PRESETN_MSCH_BIU 0x000002D5
740
+#define SRST_PRESETN_DDR_GRF 0x000002D6
741
+#define SRST_PRESETN_DDR_HWLP 0x000002D8
742
+#define SRST_PRESETN_DDRPHY 0x000002D9
743
+#define SRST_RESETN_MSCH_BIU 0x000002DA
744
+#define SRST_ARESETN_DDR_UPCTL 0x000002DB
745
+#define SRST_RESETN_DDR_UPCTL 0x000002DC
746
+#define SRST_RESETN_DDRMON 0x000002DD
747
+#define SRST_ARESETN_DDR_SCRAMBLE 0x000002DE
748
+#define SRST_ARESETN_SPLIT 0x000002DF
749
+
750
+// CRU_SOFTRST_CON46(Offset:0xAB8)
751
+#define SRST_RESETN_DDR_PHY 0x000002E0
752
+
753
+#endif
754
+
u-boot/include/dt-bindings/clock/rk3562-cru.h
....@@ -0,0 +1,733 @@
1
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2
+/*
3
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
4
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
5
+ */
6
+
7
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
8
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
9
+
10
+/* cru-clocks indices */
11
+
12
+/* cru plls */
13
+#define PLL_APLL 1
14
+#define PLL_GPLL 2
15
+#define PLL_VPLL 3
16
+#define PLL_HPLL 4
17
+#define PLL_CPLL 5
18
+#define PLL_DPLL 6
19
+
20
+/* cru clocks */
21
+#define ARMCLK 8
22
+#define CLK_GPU 9
23
+#define ACLK_RKNN 10
24
+#define CLK_DDR 11
25
+#define CLK_MATRIX_50M_SRC 12
26
+#define CLK_MATRIX_100M_SRC 13
27
+#define CLK_MATRIX_125M_SRC 14
28
+#define CLK_MATRIX_200M_SRC 15
29
+#define CLK_MATRIX_300M_SRC 16
30
+#define ACLK_TOP 17
31
+#define ACLK_TOP_VIO 18
32
+#define CLK_CAM0_OUT2IO 19
33
+#define CLK_CAM1_OUT2IO 20
34
+#define CLK_CAM2_OUT2IO 21
35
+#define CLK_CAM3_OUT2IO 22
36
+#define ACLK_BUS 23
37
+#define HCLK_BUS 24
38
+#define PCLK_BUS 25
39
+#define PCLK_I2C1 26
40
+#define PCLK_I2C2 27
41
+#define PCLK_I2C3 28
42
+#define PCLK_I2C4 29
43
+#define PCLK_I2C5 30
44
+#define CLK_I2C 31
45
+#define CLK_I2C1 32
46
+#define CLK_I2C2 33
47
+#define CLK_I2C3 34
48
+#define CLK_I2C4 35
49
+#define CLK_I2C5 36
50
+#define DCLK_BUS_GPIO 37
51
+#define DCLK_BUS_GPIO3 38
52
+#define DCLK_BUS_GPIO4 39
53
+#define PCLK_TIMER 40
54
+#define CLK_TIMER0 41
55
+#define CLK_TIMER1 42
56
+#define CLK_TIMER2 43
57
+#define CLK_TIMER3 44
58
+#define CLK_TIMER4 45
59
+#define CLK_TIMER5 46
60
+#define PCLK_STIMER 47
61
+#define CLK_STIMER0 48
62
+#define CLK_STIMER1 49
63
+#define PCLK_WDTNS 50
64
+#define CLK_WDTNS 51
65
+#define PCLK_GRF 52
66
+#define PCLK_SGRF 53
67
+#define PCLK_MAILBOX 54
68
+#define PCLK_INTC 55
69
+#define ACLK_BUS_GIC400 56
70
+#define ACLK_BUS_SPINLOCK 57
71
+#define ACLK_DCF 58
72
+#define PCLK_DCF 59
73
+#define FCLK_BUS_CM0_CORE 60
74
+#define CLK_BUS_CM0_RTC 61
75
+#define HCLK_ICACHE 62
76
+#define HCLK_DCACHE 63
77
+#define PCLK_TSADC 64
78
+#define CLK_TSADC 65
79
+#define CLK_TSADC_TSEN 66
80
+#define PCLK_DFT2APB 67
81
+#define CLK_SARADC_VCCIO156 68
82
+#define PCLK_GMAC 69
83
+#define ACLK_GMAC 70
84
+#define CLK_GMAC_125M_CRU_I 71
85
+#define CLK_GMAC_50M_CRU_I 72
86
+#define CLK_GMAC_50M_O 73
87
+#define CLK_GMAC_ETH_OUT2IO 74
88
+#define PCLK_APB2ASB_VCCIO156 75
89
+#define PCLK_TO_VCCIO156 76
90
+#define PCLK_DSIPHY 77
91
+#define PCLK_DSITX 78
92
+#define PCLK_CPU_EMA_DET 79
93
+#define PCLK_HASH 80
94
+#define PCLK_TOPCRU 81
95
+#define PCLK_ASB2APB_VCCIO156 82
96
+#define PCLK_IOC_VCCIO156 83
97
+#define PCLK_GPIO3_VCCIO156 84
98
+#define PCLK_GPIO4_VCCIO156 85
99
+#define PCLK_SARADC_VCCIO156 86
100
+#define PCLK_MAC100 87
101
+#define ACLK_MAC100 89
102
+#define CLK_MAC100_50M_MATRIX 90
103
+#define HCLK_CORE 91
104
+#define PCLK_DDR 92
105
+#define CLK_MSCH_BRG_BIU 93
106
+#define PCLK_DDR_HWLP 94
107
+#define PCLK_DDR_UPCTL 95
108
+#define PCLK_DDR_PHY 96
109
+#define PCLK_DDR_DFICTL 97
110
+#define PCLK_DDR_DMA2DDR 98
111
+#define PCLK_DDR_MON 99
112
+#define TMCLK_DDR_MON 100
113
+#define PCLK_DDR_GRF 101
114
+#define PCLK_DDR_CRU 102
115
+#define PCLK_SUBDDR_CRU 103
116
+#define CLK_GPU_PRE 104
117
+#define ACLK_GPU_PRE 105
118
+#define CLK_GPU_BRG 107
119
+#define CLK_NPU_PRE 108
120
+#define HCLK_NPU_PRE 109
121
+#define HCLK_RKNN 111
122
+#define ACLK_PERI 112
123
+#define HCLK_PERI 113
124
+#define PCLK_PERI 114
125
+#define PCLK_PERICRU 115
126
+#define HCLK_SAI0 116
127
+#define CLK_SAI0_SRC 117
128
+#define CLK_SAI0_FRAC 118
129
+#define CLK_SAI0 119
130
+#define MCLK_SAI0 120
131
+#define MCLK_SAI0_OUT2IO 121
132
+#define HCLK_SAI1 122
133
+#define CLK_SAI1_SRC 123
134
+#define CLK_SAI1_FRAC 124
135
+#define CLK_SAI1 125
136
+#define MCLK_SAI1 126
137
+#define MCLK_SAI1_OUT2IO 127
138
+#define HCLK_SAI2 128
139
+#define CLK_SAI2_SRC 129
140
+#define CLK_SAI2_FRAC 130
141
+#define CLK_SAI2 131
142
+#define MCLK_SAI2 132
143
+#define MCLK_SAI2_OUT2IO 133
144
+#define HCLK_DSM 134
145
+#define CLK_DSM 135
146
+#define HCLK_PDM 136
147
+#define MCLK_PDM 137
148
+#define HCLK_SPDIF 138
149
+#define CLK_SPDIF_SRC 139
150
+#define CLK_SPDIF_FRAC 140
151
+#define CLK_SPDIF 141
152
+#define MCLK_SPDIF 142
153
+#define HCLK_SDMMC0 143
154
+#define CCLK_SDMMC0 144
155
+#define HCLK_SDMMC1 145
156
+#define CCLK_SDMMC1 146
157
+#define SCLK_SDMMC0_DRV 147
158
+#define SCLK_SDMMC0_SAMPLE 148
159
+#define SCLK_SDMMC1_DRV 149
160
+#define SCLK_SDMMC1_SAMPLE 150
161
+#define HCLK_EMMC 151
162
+#define ACLK_EMMC 152
163
+#define CCLK_EMMC 153
164
+#define BCLK_EMMC 154
165
+#define TMCLK_EMMC 155
166
+#define SCLK_SFC 156
167
+#define HCLK_SFC 157
168
+#define HCLK_USB2HOST 158
169
+#define HCLK_USB2HOST_ARB 159
170
+#define PCLK_SPI1 160
171
+#define CLK_SPI1 161
172
+#define SCLK_IN_SPI1 162
173
+#define PCLK_SPI2 163
174
+#define CLK_SPI2 164
175
+#define SCLK_IN_SPI2 165
176
+#define PCLK_UART1 166
177
+#define PCLK_UART2 167
178
+#define PCLK_UART3 168
179
+#define PCLK_UART4 169
180
+#define PCLK_UART5 170
181
+#define PCLK_UART6 171
182
+#define PCLK_UART7 172
183
+#define PCLK_UART8 173
184
+#define PCLK_UART9 174
185
+#define CLK_UART1_SRC 175
186
+#define CLK_UART1_FRAC 176
187
+#define CLK_UART1 177
188
+#define SCLK_UART1 178
189
+#define CLK_UART2_SRC 179
190
+#define CLK_UART2_FRAC 180
191
+#define CLK_UART2 181
192
+#define SCLK_UART2 182
193
+#define CLK_UART3_SRC 183
194
+#define CLK_UART3_FRAC 184
195
+#define CLK_UART3 185
196
+#define SCLK_UART3 186
197
+#define CLK_UART4_SRC 187
198
+#define CLK_UART4_FRAC 188
199
+#define CLK_UART4 189
200
+#define SCLK_UART4 190
201
+#define CLK_UART5_SRC 191
202
+#define CLK_UART5_FRAC 192
203
+#define CLK_UART5 193
204
+#define SCLK_UART5 194
205
+#define CLK_UART6_SRC 195
206
+#define CLK_UART6_FRAC 196
207
+#define CLK_UART6 197
208
+#define SCLK_UART6 198
209
+#define CLK_UART7_SRC 199
210
+#define CLK_UART7_FRAC 200
211
+#define CLK_UART7 201
212
+#define SCLK_UART7 202
213
+#define CLK_UART8_SRC 203
214
+#define CLK_UART8_FRAC 204
215
+#define CLK_UART8 205
216
+#define SCLK_UART8 206
217
+#define CLK_UART9_SRC 207
218
+#define CLK_UART9_FRAC 208
219
+#define CLK_UART9 209
220
+#define SCLK_UART9 210
221
+#define PCLK_PWM1_PERI 211
222
+#define CLK_PWM1_PERI 212
223
+#define CLK_CAPTURE_PWM1_PERI 213
224
+#define PCLK_PWM2_PERI 214
225
+#define CLK_PWM2_PERI 215
226
+#define CLK_CAPTURE_PWM2_PERI 216
227
+#define PCLK_PWM3_PERI 217
228
+#define CLK_PWM3_PERI 218
229
+#define CLK_CAPTURE_PWM3_PERI 219
230
+#define PCLK_CAN0 220
231
+#define CLK_CAN0 221
232
+#define PCLK_CAN1 222
233
+#define CLK_CAN1 223
234
+#define ACLK_CRYPTO 224
235
+#define HCLK_CRYPTO 225
236
+#define PCLK_CRYPTO 226
237
+#define CLK_CORE_CRYPTO 227
238
+#define CLK_PKA_CRYPTO 228
239
+#define HCLK_KLAD 229
240
+#define PCLK_KEY_READER 230
241
+#define HCLK_RK_RNG_NS 231
242
+#define HCLK_RK_RNG_S 232
243
+#define HCLK_TRNG_NS 233
244
+#define HCLK_TRNG_S 234
245
+#define HCLK_CRYPTO_S 235
246
+#define PCLK_PERI_WDT 236
247
+#define TCLK_PERI_WDT 237
248
+#define ACLK_SYSMEM 238
249
+#define HCLK_BOOTROM 239
250
+#define PCLK_PERI_GRF 240
251
+#define ACLK_DMAC 241
252
+#define ACLK_RKDMAC 242
253
+#define PCLK_OTPC_NS 243
254
+#define CLK_SBPI_OTPC_NS 244
255
+#define CLK_USER_OTPC_NS 245
256
+#define PCLK_OTPC_S 246
257
+#define CLK_SBPI_OTPC_S 247
258
+#define CLK_USER_OTPC_S 248
259
+#define CLK_OTPC_ARB 249
260
+#define PCLK_OTPPHY 250
261
+#define PCLK_USB2PHY 251
262
+#define PCLK_PIPEPHY 252
263
+#define PCLK_SARADC 253
264
+#define CLK_SARADC 254
265
+#define PCLK_IOC_VCCIO234 255
266
+#define PCLK_PERI_GPIO1 256
267
+#define PCLK_PERI_GPIO2 257
268
+#define DCLK_PERI_GPIO 258
269
+#define DCLK_PERI_GPIO1 259
270
+#define DCLK_PERI_GPIO2 260
271
+#define ACLK_PHP 261
272
+#define PCLK_PHP 262
273
+#define ACLK_PCIE20_MST 263
274
+#define ACLK_PCIE20_SLV 264
275
+#define ACLK_PCIE20_DBI 265
276
+#define PCLK_PCIE20 266
277
+#define CLK_PCIE20_AUX 267
278
+#define ACLK_USB3OTG 268
279
+#define CLK_USB3OTG_SUSPEND 269
280
+#define CLK_USB3OTG_REF 270
281
+#define CLK_PIPEPHY_REF_FUNC 271
282
+#define CLK_200M_PMU 272
283
+#define CLK_RTC_32K 273
284
+#define CLK_RTC32K_FRAC 274
285
+#define BUSCLK_PDPMU0 275
286
+#define PCLK_PMU0_CRU 276
287
+#define PCLK_PMU0_PMU 277
288
+#define CLK_PMU0_PMU 278
289
+#define PCLK_PMU0_HP_TIMER 279
290
+#define CLK_PMU0_HP_TIMER 280
291
+#define CLK_PMU0_32K_HP_TIMER 281
292
+#define PCLK_PMU0_PVTM 282
293
+#define CLK_PMU0_PVTM 283
294
+#define PCLK_IOC_PMUIO 284
295
+#define PCLK_PMU0_GPIO0 285
296
+#define DBCLK_PMU0_GPIO0 286
297
+#define PCLK_PMU0_GRF 287
298
+#define PCLK_PMU0_SGRF 288
299
+#define CLK_DDR_FAIL_SAFE 289
300
+#define PCLK_PMU0_SCRKEYGEN 290
301
+#define PCLK_PMU1_CRU 291
302
+#define HCLK_PMU1_MEM 292
303
+#define PCLK_PMU0_I2C0 293
304
+#define CLK_PMU0_I2C0 294
305
+#define PCLK_PMU1_UART0 295
306
+#define CLK_PMU1_UART0_SRC 296
307
+#define CLK_PMU1_UART0_FRAC 297
308
+#define CLK_PMU1_UART0 298
309
+#define SCLK_PMU1_UART0 299
310
+#define PCLK_PMU1_SPI0 300
311
+#define CLK_PMU1_SPI0 301
312
+#define SCLK_IN_PMU1_SPI0 302
313
+#define PCLK_PMU1_PWM0 303
314
+#define CLK_PMU1_PWM0 304
315
+#define CLK_CAPTURE_PMU1_PWM0 305
316
+#define CLK_PMU1_WIFI 306
317
+#define FCLK_PMU1_CM0_CORE 307
318
+#define CLK_PMU1_CM0_RTC 308
319
+#define PCLK_PMU1_WDTNS 309
320
+#define CLK_PMU1_WDTNS 310
321
+#define PCLK_PMU1_MAILBOX 311
322
+#define CLK_PIPEPHY_DIV 312
323
+#define CLK_PIPEPHY_XIN24M 313
324
+#define CLK_PIPEPHY_REF 314
325
+#define CLK_24M_SSCSRC 315
326
+#define CLK_USB2PHY_XIN24M 316
327
+#define CLK_USB2PHY_REF 317
328
+#define CLK_MIPIDSIPHY_XIN24M 318
329
+#define CLK_MIPIDSIPHY_REF 319
330
+#define ACLK_RGA_PRE 320
331
+#define HCLK_RGA_PRE 321
332
+#define ACLK_RGA 322
333
+#define HCLK_RGA 323
334
+#define CLK_RGA_CORE 324
335
+#define ACLK_JDEC 325
336
+#define HCLK_JDEC 326
337
+#define ACLK_VDPU_PRE 327
338
+#define CLK_RKVDEC_HEVC_CA 328
339
+#define HCLK_VDPU_PRE 329
340
+#define ACLK_RKVDEC 330
341
+#define HCLK_RKVDEC 331
342
+#define CLK_RKVENC_CORE 332
343
+#define ACLK_VEPU_PRE 333
344
+#define HCLK_VEPU_PRE 334
345
+#define ACLK_RKVENC 335
346
+#define HCLK_RKVENC 336
347
+#define ACLK_VI 337
348
+#define HCLK_VI 338
349
+#define PCLK_VI 339
350
+#define ACLK_ISP 340
351
+#define HCLK_ISP 341
352
+#define CLK_ISP 342
353
+#define ACLK_VICAP 343
354
+#define HCLK_VICAP 344
355
+#define DCLK_VICAP 345
356
+#define CSIRX0_CLK_DATA 346
357
+#define CSIRX1_CLK_DATA 347
358
+#define CSIRX2_CLK_DATA 348
359
+#define CSIRX3_CLK_DATA 349
360
+#define PCLK_CSIHOST0 350
361
+#define PCLK_CSIHOST1 351
362
+#define PCLK_CSIHOST2 352
363
+#define PCLK_CSIHOST3 353
364
+#define PCLK_CSIPHY0 354
365
+#define PCLK_CSIPHY1 355
366
+#define ACLK_VO_PRE 356
367
+#define HCLK_VO_PRE 357
368
+#define ACLK_VOP 358
369
+#define HCLK_VOP 359
370
+#define DCLK_VOP 360
371
+#define DCLK_VOP1 361
372
+#define ACLK_CRYPTO_S 362
373
+#define PCLK_CRYPTO_S 363
374
+#define CLK_CORE_CRYPTO_S 364
375
+#define CLK_PKA_CRYPTO_S 365
376
+
377
+#define CLK_NR_CLKS (CLK_PKA_CRYPTO_S + 1)
378
+
379
+/* soft-reset indices */
380
+
381
+/********Name=SOFTRST_CON01,Offset=0x404********/
382
+#define SRST_A_TOP_BIU 16
383
+#define SRST_A_TOP_VIO_BIU 17
384
+#define SRST_REF_PVTPLL_LOGIC 18
385
+/********Name=SOFTRST_CON03,Offset=0x40C********/
386
+#define SRST_NCOREPORESET0 48
387
+#define SRST_NCOREPORESET1 49
388
+#define SRST_NCOREPORESET2 50
389
+#define SRST_NCOREPORESET3 51
390
+#define SRST_NCORESET0 52
391
+#define SRST_NCORESET1 53
392
+#define SRST_NCORESET2 54
393
+#define SRST_NCORESET3 55
394
+#define SRST_NL2RESET 56
395
+/********Name=SOFTRST_CON04,Offset=0x410********/
396
+#define SRST_DAP 73
397
+#define SRST_P_DBG_DAPLITE 74
398
+#define SRST_REF_PVTPLL_CORE 77
399
+/********Name=SOFTRST_CON05,Offset=0x414********/
400
+#define SRST_A_CORE_BIU 80
401
+#define SRST_P_CORE_BIU 81
402
+#define SRST_H_CORE_BIU 82
403
+/********Name=SOFTRST_CON06,Offset=0x418********/
404
+#define SRST_A_NPU_BIU 98
405
+#define SRST_H_NPU_BIU 99
406
+#define SRST_A_RKNN 100
407
+#define SRST_H_RKNN 101
408
+#define SRST_REF_PVTPLL_NPU 102
409
+/********Name=SOFTRST_CON08,Offset=0x420********/
410
+#define SRST_A_GPU_BIU 131
411
+#define SRST_GPU 132
412
+#define SRST_REF_PVTPLL_GPU 133
413
+#define SRST_GPU_BRG_BIU 134
414
+/********Name=SOFTRST_CON09,Offset=0x424********/
415
+#define SRST_RKVENC_CORE 144
416
+#define SRST_A_VEPU_BIU 147
417
+#define SRST_H_VEPU_BIU 148
418
+#define SRST_A_RKVENC 149
419
+#define SRST_H_RKVENC 150
420
+/********Name=SOFTRST_CON10,Offset=0x428********/
421
+#define SRST_RKVDEC_HEVC_CA 162
422
+#define SRST_A_VDPU_BIU 165
423
+#define SRST_H_VDPU_BIU 166
424
+#define SRST_A_RKVDEC 167
425
+#define SRST_H_RKVDEC 168
426
+/********Name=SOFTRST_CON11,Offset=0x42C********/
427
+#define SRST_A_VI_BIU 179
428
+#define SRST_H_VI_BIU 180
429
+#define SRST_P_VI_BIU 181
430
+#define SRST_ISP 184
431
+#define SRST_A_VICAP 185
432
+#define SRST_H_VICAP 186
433
+#define SRST_D_VICAP 187
434
+#define SRST_I0_VICAP 188
435
+#define SRST_I1_VICAP 189
436
+#define SRST_I2_VICAP 190
437
+#define SRST_I3_VICAP 191
438
+/********Name=SOFTRST_CON12,Offset=0x430********/
439
+#define SRST_P_CSIHOST0 192
440
+#define SRST_P_CSIHOST1 193
441
+#define SRST_P_CSIHOST2 194
442
+#define SRST_P_CSIHOST3 195
443
+#define SRST_P_CSIPHY0 196
444
+#define SRST_P_CSIPHY1 197
445
+/********Name=SOFTRST_CON13,Offset=0x434********/
446
+#define SRST_A_VO_BIU 211
447
+#define SRST_H_VO_BIU 212
448
+#define SRST_A_VOP 214
449
+#define SRST_H_VOP 215
450
+#define SRST_D_VOP 216
451
+#define SRST_D_VOP1 217
452
+/********Name=SOFTRST_CON14,Offset=0x438********/
453
+#define SRST_A_RGA_BIU 227
454
+#define SRST_H_RGA_BIU 228
455
+#define SRST_A_RGA 230
456
+#define SRST_H_RGA 231
457
+#define SRST_RGA_CORE 232
458
+#define SRST_A_JDEC 233
459
+#define SRST_H_JDEC 234
460
+/********Name=SOFTRST_CON15,Offset=0x43C********/
461
+#define SRST_B_EBK_BIU 242
462
+#define SRST_P_EBK_BIU 243
463
+#define SRST_AHB2AXI_EBC 244
464
+#define SRST_H_EBC 245
465
+#define SRST_D_EBC 246
466
+#define SRST_H_EINK 247
467
+#define SRST_P_EINK 248
468
+/********Name=SOFTRST_CON16,Offset=0x440********/
469
+#define SRST_P_PHP_BIU 258
470
+#define SRST_A_PHP_BIU 259
471
+#define SRST_P_PCIE20 263
472
+#define SRST_PCIE20_POWERUP 264
473
+#define SRST_USB3OTG 266
474
+/********Name=SOFTRST_CON17,Offset=0x444********/
475
+#define SRST_PIPEPHY 275
476
+/********Name=SOFTRST_CON18,Offset=0x448********/
477
+#define SRST_A_BUS_BIU 291
478
+#define SRST_H_BUS_BIU 292
479
+#define SRST_P_BUS_BIU 293
480
+/********Name=SOFTRST_CON19,Offset=0x44C********/
481
+#define SRST_P_I2C1 304
482
+#define SRST_P_I2C2 305
483
+#define SRST_P_I2C3 306
484
+#define SRST_P_I2C4 307
485
+#define SRST_P_I2C5 308
486
+#define SRST_I2C1 310
487
+#define SRST_I2C2 311
488
+#define SRST_I2C3 312
489
+#define SRST_I2C4 313
490
+#define SRST_I2C5 314
491
+/********Name=SOFTRST_CON20,Offset=0x450********/
492
+#define SRST_BUS_GPIO3 325
493
+#define SRST_BUS_GPIO4 326
494
+/********Name=SOFTRST_CON21,Offset=0x454********/
495
+#define SRST_P_TIMER 336
496
+#define SRST_TIMER0 337
497
+#define SRST_TIMER1 338
498
+#define SRST_TIMER2 339
499
+#define SRST_TIMER3 340
500
+#define SRST_TIMER4 341
501
+#define SRST_TIMER5 342
502
+#define SRST_P_STIMER 343
503
+#define SRST_STIMER0 344
504
+#define SRST_STIMER1 345
505
+/********Name=SOFTRST_CON22,Offset=0x458********/
506
+#define SRST_P_WDTNS 352
507
+#define SRST_WDTNS 353
508
+#define SRST_P_GRF 354
509
+#define SRST_P_SGRF 355
510
+#define SRST_P_MAILBOX 356
511
+#define SRST_P_INTC 357
512
+#define SRST_A_BUS_GIC400 358
513
+#define SRST_A_BUS_GIC400_DEBUG 359
514
+/********Name=SOFTRST_CON23,Offset=0x45C********/
515
+#define SRST_A_BUS_SPINLOCK 368
516
+#define SRST_A_DCF 369
517
+#define SRST_P_DCF 370
518
+#define SRST_F_BUS_CM0_CORE 371
519
+#define SRST_T_BUS_CM0_JTAG 373
520
+#define SRST_H_ICACHE 376
521
+#define SRST_H_DCACHE 377
522
+/********Name=SOFTRST_CON24,Offset=0x460********/
523
+#define SRST_P_TSADC 384
524
+#define SRST_TSADC 385
525
+#define SRST_TSADCPHY 386
526
+#define SRST_P_DFT2APB 388
527
+/********Name=SOFTRST_CON25,Offset=0x464********/
528
+#define SRST_A_GMAC 401
529
+#define SRST_P_APB2ASB_VCCIO156 405
530
+#define SRST_P_DSIPHY 408
531
+#define SRST_P_DSITX 409
532
+#define SRST_P_CPU_EMA_DET 410
533
+#define SRST_P_HASH 411
534
+#define SRST_P_TOPCRU 415
535
+/********Name=SOFTRST_CON26,Offset=0x468********/
536
+#define SRST_P_ASB2APB_VCCIO156 416
537
+#define SRST_P_IOC_VCCIO156 417
538
+#define SRST_P_GPIO3_VCCIO156 418
539
+#define SRST_P_GPIO4_VCCIO156 419
540
+#define SRST_P_SARADC_VCCIO156 420
541
+#define SRST_SARADC_VCCIO156 421
542
+#define SRST_SARADC_VCCIO156_PHY 422
543
+/********Name=SOFTRST_CON27,Offset=0x46c********/
544
+#define SRST_A_MAC100 433
545
+
546
+/* (0x10200 - 0x400) / 4 * 16 = 260096 */
547
+/********Name=PMU0SOFTRST_CON00,Offset=0x10200********/
548
+#define SRST_P_PMU0_CRU 260096
549
+#define SRST_P_PMU0_PMU 260097
550
+#define SRST_PMU0_PMU 260098
551
+#define SRST_P_PMU0_HP_TIMER 260099
552
+#define SRST_PMU0_HP_TIMER 260100
553
+#define SRST_PMU0_32K_HP_TIMER 260101
554
+#define SRST_P_PMU0_PVTM 260102
555
+#define SRST_PMU0_PVTM 260103
556
+#define SRST_P_IOC_PMUIO 260104
557
+#define SRST_P_PMU0_GPIO0 260105
558
+#define SRST_PMU0_GPIO0 260106
559
+#define SRST_P_PMU0_GRF 260107
560
+#define SRST_P_PMU0_SGRF 260108
561
+/********Name=PMU0SOFTRST_CON01,Offset=0x10204********/
562
+#define SRST_DDR_FAIL_SAFE 260112
563
+#define SRST_P_PMU0_SCRKEYGEN 260113
564
+/********Name=PMU0SOFTRST_CON02,Offset=0x10208********/
565
+#define SRST_P_PMU0_I2C0 260136
566
+#define SRST_PMU0_I2C0 260137
567
+
568
+/* (0x18200 - 0x400) / 4 * 16 = 391168 */
569
+/********Name=PMU1SOFTRST_CON00,Offset=0x18200********/
570
+#define SRST_P_PMU1_CRU 391168
571
+#define SRST_H_PMU1_MEM 391170
572
+#define SRST_H_PMU1_BIU 391171
573
+#define SRST_P_PMU1_BIU 391172
574
+#define SRST_P_PMU1_UART0 391175
575
+#define SRST_S_PMU1_UART0 391178
576
+/********Name=PMU1SOFTRST_CON01,Offset=0x18204********/
577
+#define SRST_P_PMU1_SPI0 391184
578
+#define SRST_PMU1_SPI0 391185
579
+#define SRST_P_PMU1_PWM0 391187
580
+#define SRST_PMU1_PWM0 391188
581
+/********Name=PMU1SOFTRST_CON02,Offset=0x18208********/
582
+#define SRST_F_PMU1_CM0_CORE 391200
583
+#define SRST_T_PMU1_CM0_JTAG 391202
584
+#define SRST_P_PMU1_WDTNS 391203
585
+#define SRST_PMU1_WDTNS 391204
586
+#define SRST_PMU1_MAILBOX 391208
587
+
588
+/* (0x20200 - 0x400) / 4 * 16 = 522240 */
589
+/********Name=DDRSOFTRST_CON00,Offset=0x20200********/
590
+#define SRST_MSCH_BRG_BIU 522244
591
+#define SRST_P_MSCH_BIU 522245
592
+#define SRST_P_DDR_HWLP 522246
593
+#define SRST_P_DDR_PHY 522248
594
+#define SRST_P_DDR_DFICTL 522249
595
+#define SRST_P_DDR_DMA2DDR 522250
596
+/********Name=DDRSOFTRST_CON01,Offset=0x20204********/
597
+#define SRST_P_DDR_MON 522256
598
+#define SRST_TM_DDR_MON 522257
599
+#define SRST_P_DDR_GRF 522258
600
+#define SRST_P_DDR_CRU 522259
601
+#define SRST_P_SUBDDR_CRU 522260
602
+
603
+/* (0x28200 - 0x400) / 4 * 16 = 653312 */
604
+/********Name=SUBDDRSOFTRST_CON00,Offset=0x28200********/
605
+#define SRST_MSCH_BIU 653313
606
+#define SRST_DDR_PHY 653316
607
+#define SRST_DDR_DFICTL 653317
608
+#define SRST_DDR_SCRAMBLE 653318
609
+#define SRST_DDR_MON 653319
610
+#define SRST_A_DDR_SPLIT 653320
611
+#define SRST_DDR_DMA2DDR 653321
612
+
613
+/* (0x30400 - 0x400) / 4 * 16 = 786432 */
614
+/********Name=PERISOFTRST_CON01,Offset=0x30404********/
615
+#define SRST_A_PERI_BIU 786451
616
+#define SRST_H_PERI_BIU 786452
617
+#define SRST_P_PERI_BIU 786453
618
+#define SRST_P_PERICRU 786454
619
+/********Name=PERISOFTRST_CON02,Offset=0x30408********/
620
+#define SRST_H_SAI0_8CH 786464
621
+#define SRST_M_SAI0_8CH 786467
622
+#define SRST_H_SAI1_8CH 786469
623
+#define SRST_M_SAI1_8CH 786472
624
+#define SRST_H_SAI2_2CH 786474
625
+#define SRST_M_SAI2_2CH 786477
626
+/********Name=PERISOFTRST_CON03,Offset=0x3040C********/
627
+#define SRST_H_DSM 786481
628
+#define SRST_DSM 786482
629
+#define SRST_H_PDM 786484
630
+#define SRST_M_PDM 786485
631
+#define SRST_H_SPDIF 786488
632
+#define SRST_M_SPDIF 786491
633
+/********Name=PERISOFTRST_CON04,Offset=0x30410********/
634
+#define SRST_H_SDMMC0 786496
635
+#define SRST_H_SDMMC1 786498
636
+#define SRST_H_EMMC 786504
637
+#define SRST_A_EMMC 786505
638
+#define SRST_C_EMMC 786506
639
+#define SRST_B_EMMC 786507
640
+#define SRST_T_EMMC 786508
641
+#define SRST_S_SFC 786509
642
+#define SRST_H_SFC 786510
643
+/********Name=PERISOFTRST_CON05,Offset=0x30414********/
644
+#define SRST_H_USB2HOST 786512
645
+#define SRST_H_USB2HOST_ARB 786513
646
+#define SRST_USB2HOST_UTMI 786514
647
+/********Name=PERISOFTRST_CON06,Offset=0x30418********/
648
+#define SRST_P_SPI1 786528
649
+#define SRST_SPI1 786529
650
+#define SRST_P_SPI2 786531
651
+#define SRST_SPI2 786532
652
+/********Name=PERISOFTRST_CON07,Offset=0x3041C********/
653
+#define SRST_P_UART1 786544
654
+#define SRST_P_UART2 786545
655
+#define SRST_P_UART3 786546
656
+#define SRST_P_UART4 786547
657
+#define SRST_P_UART5 786548
658
+#define SRST_P_UART6 786549
659
+#define SRST_P_UART7 786550
660
+#define SRST_P_UART8 786551
661
+#define SRST_P_UART9 786552
662
+#define SRST_S_UART1 786555
663
+#define SRST_S_UART2 786558
664
+/********Name=PERISOFTRST_CON08,Offset=0x30420********/
665
+#define SRST_S_UART3 786561
666
+#define SRST_S_UART4 786564
667
+#define SRST_S_UART5 786567
668
+#define SRST_S_UART6 786570
669
+#define SRST_S_UART7 786573
670
+/********Name=PERISOFTRST_CON09,Offset=0x30424********/
671
+#define SRST_S_UART8 786576
672
+#define SRST_S_UART9 786579
673
+/********Name=PERISOFTRST_CON10,Offset=0x30428********/
674
+#define SRST_P_PWM1_PERI 786592
675
+#define SRST_PWM1_PERI 786593
676
+#define SRST_P_PWM2_PERI 786595
677
+#define SRST_PWM2_PERI 786596
678
+#define SRST_P_PWM3_PERI 786598
679
+#define SRST_PWM3_PERI 786599
680
+/********Name=PERISOFTRST_CON11,Offset=0x3042C********/
681
+#define SRST_P_CAN0 786608
682
+#define SRST_CAN0 786609
683
+#define SRST_P_CAN1 786610
684
+#define SRST_CAN1 786611
685
+/********Name=PERISOFTRST_CON12,Offset=0x30430********/
686
+#define SRST_A_CRYPTO 786624
687
+#define SRST_H_CRYPTO 786625
688
+#define SRST_P_CRYPTO 786626
689
+#define SRST_CORE_CRYPTO 786627
690
+#define SRST_PKA_CRYPTO 786628
691
+#define SRST_H_KLAD 786629
692
+#define SRST_P_KEY_READER 786630
693
+#define SRST_H_RK_RNG_NS 786631
694
+#define SRST_H_RK_RNG_S 786632
695
+#define SRST_H_TRNG_NS 786633
696
+#define SRST_H_TRNG_S 786634
697
+#define SRST_H_CRYPTO_S 786635
698
+/********Name=PERISOFTRST_CON13,Offset=0x30434********/
699
+#define SRST_P_PERI_WDT 786640
700
+#define SRST_T_PERI_WDT 786641
701
+#define SRST_A_SYSMEM 786642
702
+#define SRST_H_BOOTROM 786643
703
+#define SRST_P_PERI_GRF 786644
704
+#define SRST_A_DMAC 786645
705
+#define SRST_A_RKDMAC 786646
706
+/********Name=PERISOFTRST_CON14,Offset=0x30438********/
707
+#define SRST_P_OTPC_NS 786656
708
+#define SRST_SBPI_OTPC_NS 786657
709
+#define SRST_USER_OTPC_NS 786658
710
+#define SRST_P_OTPC_S 786659
711
+#define SRST_SBPI_OTPC_S 786660
712
+#define SRST_USER_OTPC_S 786661
713
+#define SRST_OTPC_ARB 786662
714
+#define SRST_P_OTPPHY 786663
715
+#define SRST_OTP_NPOR 786664
716
+/********Name=PERISOFTRST_CON15,Offset=0x3043C********/
717
+#define SRST_P_USB2PHY 786672
718
+#define SRST_USB2PHY_POR 786676
719
+#define SRST_USB2PHY_OTG 786677
720
+#define SRST_USB2PHY_HOST 786678
721
+#define SRST_P_PIPEPHY 786679
722
+/********Name=PERISOFTRST_CON16,Offset=0x30440********/
723
+#define SRST_P_SARADC 786692
724
+#define SRST_SARADC 786693
725
+#define SRST_SARADC_PHY 786694
726
+#define SRST_P_IOC_VCCIO234 786700
727
+/********Name=PERISOFTRST_CON17,Offset=0x30444********/
728
+#define SRST_P_PERI_GPIO1 786704
729
+#define SRST_P_PERI_GPIO2 786705
730
+#define SRST_PERI_GPIO1 786706
731
+#define SRST_PERI_GPIO2 786707
732
+
733
+#endif
u-boot/include/dt-bindings/display/rockchip-tve.h
....@@ -0,0 +1,15 @@
1
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2
+/*
3
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4
+ */
5
+
6
+
7
+#ifndef _DT_BINDINGS_ROCKCHIP_TVE_H
8
+#define _DT_BINDINGS_ROCKCHIP_TVE_H
9
+
10
+/* tve dclk upsample mode */
11
+#define DCLK_UPSAMPLEx1 0
12
+#define DCLK_UPSAMPLEx2 1
13
+#define DCLK_UPSAMPLEx4 2
14
+
15
+#endif
u-boot/include/dt-bindings/power/rk3528-power.h
....@@ -0,0 +1,18 @@
1
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2
+#ifndef __DT_BINDINGS_POWER_RK3528_POWER_H__
3
+#define __DT_BINDINGS_POWER_RK3528_POWER_H__
4
+
5
+/*
6
+ * RK3528 idle id Summary.
7
+ */
8
+#define RK3528_PD_PMU 0
9
+#define RK3528_PD_BUS 1
10
+#define RK3528_PD_DDR 2
11
+#define RK3528_PD_MSCH 3
12
+#define RK3528_PD_GPU 4
13
+#define RK3528_PD_RKVDEC 5
14
+#define RK3528_PD_RKVENC 6
15
+#define RK3528_PD_VO 7
16
+#define RK3528_PD_VPU 8
17
+
18
+#endif
u-boot/include/dt-bindings/power/rk3562-power.h
....@@ -0,0 +1,33 @@
1
+/* SPDX-License-Identifier: GPL-2.0 */
2
+#ifndef __DT_BINDINGS_POWER_RK3562_POWER_H__
3
+#define __DT_BINDINGS_POWER_RK3562_POWER_H__
4
+
5
+/* VD_CORE */
6
+#define RK3562_PD_CPU_0 0
7
+#define RK3562_PD_CPU_1 1
8
+#define RK3562_PD_CPU_2 2
9
+#define RK3562_PD_CPU_3 3
10
+#define RK3562_PD_CORE_ALIVE 4
11
+
12
+/* VD_PMU */
13
+#define RK3562_PD_PMU 5
14
+#define RK3562_PD_PMU_ALIVE 6
15
+
16
+/* VD_NPU */
17
+#define RK3562_PD_NPU 7
18
+
19
+/* VD_GPU */
20
+#define RK3562_PD_GPU 8
21
+
22
+/* VD_LOGIC */
23
+#define RK3562_PD_DDR 9
24
+#define RK3562_PD_VEPU 10
25
+#define RK3562_PD_VDPU 11
26
+#define RK3562_PD_VI 12
27
+#define RK3562_PD_VO 13
28
+#define RK3562_PD_RGA 14
29
+#define RK3562_PD_EBK 15
30
+#define RK3562_PD_PHP 16
31
+#define RK3562_PD_LOGIC_ALIVE 17
32
+
33
+#endif
u-boot/include/dt-bindings/soc/rockchip,boot-mode.h
....@@ -20,5 +20,7 @@
2020 #define BOOT_CHARGING (REBOOT_FLAG + 11)
2121 /* enter usb mass storage mode */
2222 #define BOOT_UMS (REBOOT_FLAG + 12)
23
+/* reboot system quiescent */
24
+#define BOOT_QUIESCENT (REBOOT_FLAG + 14)
2325
2426 #endif
u-boot/include/dt-bindings/suspend/rockchip-rk3528.h
....@@ -0,0 +1,54 @@
1
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2
+/*
3
+ * Header providing constants for Rockchip suspend bindings.
4
+ *
5
+ * Copyright (C) 2022, Rockchip Electronics Co., Ltd
6
+ * Author: XiaoDong.Huang
7
+ */
8
+
9
+#ifndef __DT_BINDINGS_RK3528_PM_H__
10
+#define __DT_BINDINGS_RK3528_PM_H__
11
+/******************************bits ops************************************/
12
+
13
+#ifndef BIT
14
+#define BIT(nr) (1 << (nr))
15
+#endif
16
+
17
+#define RKPM_SLP_ARMPD BIT(0)
18
+#define RKPM_SLP_ARMOFF BIT(1)
19
+#define RKPM_SLP_ARMOFF_DDRPD BIT(2)
20
+#define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
21
+
22
+/* all plls except ddr's pll*/
23
+#define RKPM_SLP_PMU_HW_PLLS_PD BIT(8)
24
+#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9)
25
+#define RKPM_SLP_PMU_DIS_OSC BIT(10)
26
+
27
+#define RKPM_SLP_CLK_GT BIT(16)
28
+#define RKPM_SLP_PMIC_LP BIT(17)
29
+
30
+#define RKPM_SLP_32K_EXT BIT(24)
31
+#define RKPM_SLP_TIME_OUT_WKUP BIT(25)
32
+#define RKPM_SLP_PMU_DBG BIT(26)
33
+
34
+/* the wake up source */
35
+#define RKPM_CPU0_WKUP_EN BIT(0)
36
+#define RKPM_CPU1_WKUP_EN BIT(1)
37
+#define RKPM_CPU2_WKUP_EN BIT(2)
38
+#define RKPM_CPU3_WKUP_EN BIT(3)
39
+#define RKPM_GPIO_WKUP_EN BIT(4)
40
+#define RKPM_HDMI_HDP_WKUP_EN BIT(5)
41
+#define RKPM_HDMI_CEC_WKUP_EN BIT(6)
42
+#define RKPM_PWMIR_WKUP_EN BIT(7)
43
+#define RKPM_GMAC_WKUP_EN BIT(8)
44
+#define RKPM_TIMER_WKUP_EN BIT(9)
45
+#define RKPM_USBDEV_WKUP_EN BIT(10)
46
+#define RKPM_SYSINT_WKUP_EN BIT(11)
47
+#define RKPM_TIME_OUT_WKUP_EN BIT(12)
48
+
49
+/* the pwm regulator */
50
+#define RKPM_PWM0_M0_REGULATOR_EN BIT(0)
51
+#define RKPM_PWM1_M0_REGULATOR_EN BIT(1)
52
+#define RKPM_PWM2_M0_REGULATOR_EN BIT(2)
53
+
54
+#endif
u-boot/include/edid.h
....@@ -882,6 +882,38 @@
882882 u32 fps;
883883 };
884884
885
+struct csc_info {
886
+ u16 hue;
887
+ u16 saturation;
888
+ u16 contrast;
889
+ u16 brightness;
890
+ u16 r_gain;
891
+ u16 g_gain;
892
+ u16 b_gain;
893
+ u16 r_offset;
894
+ u16 g_offset;
895
+ u16 b_offset;
896
+ u16 csc_enable;
897
+};
898
+
899
+
900
+#define ACM_GAIN_LUT_HY_LENGTH (9*17)
901
+#define ACM_GAIN_LUT_HY_TOTAL_LENGTH (ACM_GAIN_LUT_HY_LENGTH * 3)
902
+#define ACM_GAIN_LUT_HS_LENGTH (13*17)
903
+#define ACM_GAIN_LUT_HS_TOTAL_LENGTH (ACM_GAIN_LUT_HS_LENGTH * 3)
904
+#define ACM_DELTA_LUT_H_LENGTH 65
905
+#define ACM_DELTA_LUT_H_TOTAL_LENGTH (ACM_DELTA_LUT_H_LENGTH * 3)
906
+
907
+struct acm_data {
908
+ s16 delta_lut_h[ACM_DELTA_LUT_H_TOTAL_LENGTH];
909
+ s16 gain_lut_hy[ACM_GAIN_LUT_HY_TOTAL_LENGTH];
910
+ s16 gain_lut_hs[ACM_GAIN_LUT_HS_TOTAL_LENGTH];
911
+ u16 y_gain;
912
+ u16 h_gain;
913
+ u16 s_gain;
914
+ u16 acm_enable;
915
+};
916
+
885917 struct base2_disp_info {
886918 char disp_head_flag[6];
887919 struct base2_screen_info screen_info[4];
....@@ -890,8 +922,15 @@
890922 struct base2_gamma_lut_data gamma_lut_data;
891923 struct base2_cubic_lut_data cubic_lut_data;
892924 struct framebuffer_info framebuffer_info;
893
- u32 reserved[244];
925
+ u32 cacm_header;
926
+ u32 reserved[243];
894927 u32 crc;
928
+ /* baseparameter version 3.0 add */
929
+ struct csc_info csc_info;
930
+ struct acm_data acm_data;
931
+ u8 resv2[10*1024]; /* */
932
+ u32 crc2;
933
+ /* baseparameter version 3.0 add */
895934 };
896935
897936 struct base2_disp_header {
u-boot/include/image.h
....@@ -703,6 +703,7 @@
703703 bootm_headers_t *images,
704704 char **of_flat_tree, ulong *of_size);
705705 void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob);
706
+void boot_mem_rsv_regions(struct lmb *lmb, void *fdt_blob);
706707 #ifdef CONFIG_SYSMEM
707708 int boot_fdt_add_sysmem_rsv_regions(void *fdt_blob);
708709 #else
....@@ -1347,9 +1348,13 @@
13471348 #endif /* CONFIG_FIT */
13481349
13491350 #if defined(CONFIG_ANDROID_BOOT_IMAGE)
1351
+#include <android_image.h>
1352
+
13501353 struct andr_img_hdr;
13511354 u32 android_bcb_msg_sector_offset(void);
1352
-u32 android_image_major_version(void);
1355
+int android_image_init_resource(struct blk_desc *desc,
1356
+ disk_partition_t *out_part,
1357
+ ulong *out_blk_offset);
13531358 int android_image_check_header(const struct andr_img_hdr *hdr);
13541359 int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
13551360 ulong *os_data, ulong *os_len);
....@@ -1368,6 +1373,10 @@
13681373
13691374 struct andr_img_hdr *populate_andr_img_hdr(struct blk_desc *dev_desc,
13701375 disk_partition_t *part_boot);
1376
+int populate_boot_info(const struct boot_img_hdr_v34 *boot_hdr,
1377
+ const struct vendor_boot_img_hdr_v34 *vendor_boot_hdr,
1378
+ const struct boot_img_hdr_v34 *init_boot_hdr,
1379
+ struct andr_img_hdr *hdr, bool save_hdr);
13711380
13721381 /** android_image_load - Load an Android Image from storage.
13731382 *
....@@ -1392,6 +1401,9 @@
13921401 int android_image_load_by_partname(struct blk_desc *dev_desc,
13931402 const char *boot_partname,
13941403 unsigned long *load_address);
1404
+
1405
+int android_image_verify_resource(const char *boot_part, ulong *resc_buf);
1406
+
13951407 #endif /* CONFIG_ANDROID_BOOT_IMAGE */
13961408
13971409 int bootm_parse_comp(const unsigned char *hdr);
u-boot/include/irq-platform.h
....@@ -241,6 +241,46 @@
241241 #define IRQ_GPIO3 69
242242 #define IRQ_GPIO4 70
243243
244
+#elif defined(CONFIG_ROCKCHIP_RK3528)
245
+#define GPIO0_PHYS 0xff610000
246
+#define GPIO1_PHYS 0xffaf0000
247
+#define GPIO2_PHYS 0xffb00000
248
+#define GPIO3_PHYS 0xffb10000
249
+#define GPIO4_PHYS 0xffb20000
250
+
251
+#define GIC_IRQS_NR (5 * 32)
252
+#define GPIO_IRQS_NR (5 * 32)
253
+
254
+#define GPIO_BANK_NUM 5
255
+#define GPIO_BANK_PINS 32
256
+
257
+#define IRQ_TIMER0 63
258
+#define IRQ_GPIO0 103
259
+#define IRQ_GPIO1 105
260
+#define IRQ_GPIO2 107
261
+#define IRQ_GPIO3 108
262
+#define IRQ_GPIO4 110
263
+
264
+#elif defined(CONFIG_ROCKCHIP_RK3562)
265
+#define GPIO0_PHYS 0xff260000
266
+#define GPIO1_PHYS 0xff620000
267
+#define GPIO2_PHYS 0xff630000
268
+#define GPIO3_PHYS 0xffac0000
269
+#define GPIO4_PHYS 0xffad0000
270
+
271
+#define GIC_IRQS_NR (5 * 32)
272
+#define GPIO_IRQS_NR (5 * 32)
273
+
274
+#define GPIO_BANK_NUM 5
275
+#define GPIO_BANK_PINS 32
276
+
277
+#define IRQ_TIMER0 77
278
+#define IRQ_GPIO0 32
279
+#define IRQ_GPIO1 34
280
+#define IRQ_GPIO2 36
281
+#define IRQ_GPIO3 38
282
+#define IRQ_GPIO4 40
283
+
244284 #elif defined(CONFIG_ROCKCHIP_RK3568)
245285 #define GPIO0_PHYS 0xfdd60000
246286 #define GPIO1_PHYS 0xfe740000
u-boot/include/key.h
....@@ -33,9 +33,10 @@
3333
3434 /* ADC key */
3535 u8 channel;
36
- u32 adcval;
37
- u32 min;
38
- u32 max;
36
+ int in_volt;
37
+ int center;
38
+ int min;
39
+ int max;
3940
4041 /* GPIO key */
4142 u32 irq;
u-boot/include/linux/dw_hdmi.h
....@@ -92,6 +92,7 @@
9292 RK3366_HDMI,
9393 RK3368_HDMI,
9494 RK3399_HDMI,
95
+ RK3528_HDMI,
9596 RK3568_HDMI,
9697 };
9798
....@@ -177,7 +178,7 @@
177178 const struct dw_hdmi_mpll_config *mpll_cfg;
178179 const struct dw_hdmi_mpll_config *mpll_cfg_420;
179180 const struct dw_hdmi_curr_ctrl *cur_ctr;
180
- const struct dw_hdmi_phy_config *phy_config;
181
+ struct dw_hdmi_phy_config *phy_config;
181182 int (*configure_phy)(struct dw_hdmi *hdmi,
182183 const struct dw_hdmi_plat_data *pdata,
183184 unsigned long mpixelclock);
u-boot/include/linux/mtd/mtd.h
....@@ -551,30 +551,6 @@
551551 }
552552 #endif
553553
554
-#ifdef __UBOOT__
555
-/*
556
- * Debugging macro and defines
557
- */
558
-#define MTD_DEBUG_LEVEL0 (0) /* Quiet */
559
-#define MTD_DEBUG_LEVEL1 (1) /* Audible */
560
-#define MTD_DEBUG_LEVEL2 (2) /* Loud */
561
-#define MTD_DEBUG_LEVEL3 (3) /* Noisy */
562
-
563
-#ifdef CONFIG_MTD_DEBUG
564
-#define MTDDEBUG(n, args...) \
565
- do { \
566
- if (n <= CONFIG_MTD_DEBUG_VERBOSE) \
567
- printk(KERN_INFO args); \
568
- } while(0)
569
-#else /* CONFIG_MTD_DEBUG */
570
-#define MTDDEBUG(n, args...) \
571
- do { \
572
- if (0) \
573
- printk(KERN_INFO args); \
574
- } while(0)
575
-#endif /* CONFIG_MTD_DEBUG */
576
-#endif
577
-
578554 static inline int mtd_is_bitflip(int err) {
579555 return err == -EUCLEAN;
580556 }
u-boot/include/linux/mtd/spinand.h
....@@ -252,6 +252,7 @@
252252 extern const struct spinand_manufacturer winbond_spinand_manufacturer;
253253 extern const struct spinand_manufacturer dosilicon_spinand_manufacturer;
254254 extern const struct spinand_manufacturer esmt_spinand_manufacturer;
255
+extern const struct spinand_manufacturer xincun_spinand_manufacturer;
255256 extern const struct spinand_manufacturer xtx_spinand_manufacturer;
256257 extern const struct spinand_manufacturer hyf_spinand_manufacturer;
257258 extern const struct spinand_manufacturer fmsh_spinand_manufacturer;
....@@ -262,6 +263,7 @@
262263 extern const struct spinand_manufacturer silicongo_spinand_manufacturer;
263264 extern const struct spinand_manufacturer unim_spinand_manufacturer;
264265 extern const struct spinand_manufacturer skyhigh_spinand_manufacturer;
266
+extern const struct spinand_manufacturer gsto_spinand_manufacturer;
265267
266268 /**
267269 * struct spinand_op_variants - SPI NAND operation variants
u-boot/include/max96745.h
....@@ -17,6 +17,21 @@
1717 #define RESET_ALL BIT(7)
1818 #define SLEEP BIT(3)
1919
20
+/* 0011h */
21
+#define CXTP_B BIT(2)
22
+#define CXTP_A BIT(0)
23
+
24
+/* 0028h, 0032h */
25
+#define LINK_EN BIT(7)
26
+#define TX_RATE GENMASK(3, 2)
27
+
28
+/* 0029h, 0033h */
29
+#define RESET_LINK BIT(0)
30
+#define RESET_ONESHOT BIT(1)
31
+
32
+/* 002Ah, 0034h */
33
+#define LINK_LOCKED BIT(0)
34
+
2035 /* 0076h, 0086h */
2136 #define DIS_REM_CC BIT(7)
2237
u-boot/include/max96752f.h
deleted file mode 100644
....@@ -1,66 +0,0 @@
1
-/* SPDX-License-Identifier: GPL-2.0 */
2
-/*
3
- * (C) Copyright 2022 Rockchip Electronics Co., Ltd
4
- */
5
-
6
-#ifndef _MAX96752F_H_
7
-#define _MAX96752F_H_
8
-
9
-#include <linux/bitfield.h>
10
-
11
-#define GPIO_A_REG(gpio) (0x0200 + ((gpio) * 3))
12
-#define GPIO_B_REG(gpio) (0x0201 + ((gpio) * 3))
13
-#define GPIO_C_REG(gpio) (0x0202 + ((gpio) * 3))
14
-#define OLDI_REG(x) (0x01cd + (x))
15
-
16
-/* 0002h */
17
-#define AUD_TX_EN BIT(2)
18
-
19
-/* 0010h */
20
-#define RESET_ALL BIT(7)
21
-#define RESET_LINK BIT(6)
22
-#define RESET_ONESHOT BIT(5)
23
-#define AUTO_LINK BIT(4)
24
-#define SLEEP BIT(3)
25
-#define LINK_CFG GENMASK(1, 0)
26
-
27
-/* 0050h */
28
-#define STR_SEL GENMASK(1, 0)
29
-
30
-/* 0073h */
31
-#define TX_SRC_ID GENMASK(2, 0)
32
-
33
-/* 0140h */
34
-#define AUD_RX_EN BIT(0)
35
-
36
-/* 0200h */
37
-#define RES_CFG BIT(7)
38
-#define TX_PRIO BIT(6)
39
-#define TX_COMP_EN BIT(5)
40
-#define GPIO_OUT BIT(4)
41
-#define GPIO_IN BIT(3)
42
-#define GPIO_RX_EN BIT(2)
43
-#define GPIO_TX_EN BIT(1)
44
-#define GPIO_OUT_DIS BIT(0)
45
-
46
-/* 0201h */
47
-#define PULL_UPDN_SEL GENMASK(7, 6)
48
-#define OUT_TYPE BIT(5)
49
-#define GPIO_TX_ID GENMASK(4, 0)
50
-
51
-/* 0202h */
52
-#define OVR_RES_CFG BIT(7)
53
-#define GPIO_RX_ID GENMASK(4, 0)
54
-
55
-/* 01CEh */
56
-#define OLDI_OUTSEL BIT(7)
57
-#define OLDI_FORMAT BIT(6)
58
-#define OLDI_4TH_LANE BIT(5)
59
-#define OLDI_SWAP_AB BIT(4)
60
-#define OLDI_SPL_EN BIT(3)
61
-#define OLDI_SPL_MODE GENMASK(2, 1)
62
-#define OLDI_SPL_POL BIT(0)
63
-
64
-void max96752f_init(struct udevice *dev);
65
-
66
-#endif
u-boot/include/max96755f.h
....@@ -181,6 +181,7 @@
181181 struct drm_display_mode mode;
182182 u32 num_lanes;
183183 struct gpio_desc lock_gpio;
184
+ u32 dsi_lane_map[4];
184185 };
185186
186187 #endif
u-boot/include/mmc.h
....@@ -192,6 +192,8 @@
192192 #define EXT_CSD_HS_TIMING 185 /* R/W */
193193 #define EXT_CSD_REV 192 /* RO */
194194 #define EXT_CSD_CARD_TYPE 196 /* RO */
195
+#define EXT_CSD_CARD_TYPE 196 /* RO */
196
+#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */
195197 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
196198 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
197199 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
....@@ -231,6 +233,7 @@
231233 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
232234 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
233235 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
236
+#define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
234237
235238 #define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
236239 #define EXT_CSD_TIMING_HS 1 /* High speed */
....@@ -470,6 +473,8 @@
470473 * @return 0 if write-enabled, 1 if write-protected, -ve on error
471474 */
472475 int (*execute_tuning)(struct udevice *dev, u32 opcode);
476
+ /* set_enhanced_strobe() - set HS400 enhanced strobe */
477
+ int (*set_enhanced_strobe)(struct udevice *dev);
473478 };
474479
475480 #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
....@@ -487,6 +492,7 @@
487492 int mmc_getcd(struct mmc *mmc);
488493 int mmc_getwp(struct mmc *mmc);
489494
495
+int mmc_set_enhanced_strobe(struct mmc *mmc);
490496 #else
491497 struct mmc_ops {
492498 bool (*card_busy)(struct mmc *mmc);
....@@ -511,6 +517,7 @@
511517 uint f_max;
512518 uint b_max;
513519 unsigned char part_type;
520
+ u8 fixed_drv_type;
514521 };
515522
516523 struct sd_ssr {
....@@ -598,6 +605,7 @@
598605 #if CONFIG_IS_ENABLED(DM_MMC)
599606 struct udevice *dev; /* Device for this MMC controller */
600607 #endif
608
+ u8 raw_driver_strength;
601609 };
602610
603611 struct mmc_hwpart_conf {
....@@ -785,5 +793,7 @@
785793 */
786794 void mmc_gpio_init_direct(void);
787795
796
+#define mmc_driver_type_mask(n) (1 << (n))
797
+
788798 #endif /* _MMC_H_ */
789799
u-boot/include/mp_boot.h
....@@ -0,0 +1,25 @@
1
+/*
2
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
3
+ *
4
+ * SPDX-License-Identifier: GPL-2.0+
5
+ */
6
+
7
+#ifndef _MP_BOOT_H_
8
+#define _MP_BOOT_H_
9
+
10
+#include <spl.h>
11
+
12
+struct task_data {
13
+ struct spl_load_info info;
14
+
15
+ /* to be filled by smp task */
16
+ void *boot_addr;
17
+ ulong boot_size;
18
+};
19
+
20
+void mpb_init_1(struct spl_load_info info);
21
+void mpb_init_x(int evt);
22
+ulong mpb_post(int evt);
23
+
24
+#endif
25
+
u-boot/include/power/rk8xx_pmic.h
....@@ -206,6 +206,7 @@
206206 #define RK817_ID_LSB 0xee
207207 #define RK8XX_ID_MSK 0xfff0
208208
209
+#define RK817_PMIC_CHRG_TERM 0xe6
209210 #define RK817_PMIC_SYS_CFG1 0xf1
210211 #define RK817_PMIC_SYS_CFG3 0xf4
211212 #define RK817_GPIO_INT_CFG 0xfe
....@@ -287,6 +288,7 @@
287288 uint8_t sleep_pin;
288289 uint8_t rst_fun;
289290 int not_save_power_en;
291
+ int sys_can_sd;
290292 };
291293
292294 int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt);
u-boot/include/rk_timer_irq.h
....@@ -66,6 +66,12 @@
6666 #elif defined(CONFIG_ROCKCHIP_RV1126)
6767 #define TIMER_BASE (0xFF660000 + 0x20) /* TIMER 1 */
6868 #define TIMER_IRQ IRQ_TIMER1
69
+#elif defined(CONFIG_ROCKCHIP_RK3528)
70
+#define TIMER_BASE (0xFFAB0000 + 0x00) /* TIMER 0 */
71
+#define TIMER_IRQ IRQ_TIMER0
72
+#elif defined(CONFIG_ROCKCHIP_RK3562)
73
+#define TIMER_BASE (0xFFA50000 + 0x00) /* TIMER 0 */
74
+#define TIMER_IRQ IRQ_TIMER0
6975 #elif defined(CONFIG_ROCKCHIP_RK3568)
7076 /* Only timer0 can wakeup system suspend */
7177 #define TIMER_BASE (0xFE5F0000 + 0x00) /* TIMER 1 */
u-boot/include/rockchip/crypto_v2.h
....@@ -564,7 +564,7 @@
564564 #define LLI_DMA_CTRL_DST_DONE _BIT(9)
565565 #define LLI_DMA_CTRL_SRC_DONE _BIT(10)
566566
567
-#define LLI_USER_CPIHER_START _BIT(0)
567
+#define LLI_USER_CIPHER_START _BIT(0)
568568 #define LLI_USER_STRING_START _BIT(1)
569569 #define LLI_USER_STRING_LAST _BIT(2)
570570 #define LLI_USER_STRING_AAD _BIT(3)
u-boot/include/scsi.h
....@@ -7,6 +7,9 @@
77 #ifndef _SCSI_H
88 #define _SCSI_H
99
10
+#include <asm/cache.h>
11
+#include <linux/dma-direction.h>
12
+
1013 struct scsi_cmd {
1114 unsigned char cmd[16]; /* command */
1215 /* for request sense */
....@@ -27,6 +30,7 @@
2730 unsigned long trans_bytes; /* tranfered bytes */
2831
2932 unsigned int priv;
33
+ enum dma_data_direction dma_dir;
3034 };
3135
3236 /*-----------------------------------------------------------
u-boot/include/sdhci.h
....@@ -256,6 +256,18 @@
256256 void (*set_ios_post)(struct sdhci_host *host);
257257 int (*set_clock)(struct sdhci_host *host, unsigned int clock);
258258 void (*set_clock_ext)(struct sdhci_host *host, u32 div);
259
+
260
+ /**
261
+ * set_enhanced_strobe() - Set HS400 Enhanced Strobe config
262
+ *
263
+ * This is called after setting the card speed and mode to
264
+ * HS400 ES, and should set any host-specific configuration
265
+ * necessary for it.
266
+ *
267
+ * @host: SDHCI host structure
268
+ * Return: 0 if successful, -ve on error
269
+ */
270
+ int (*set_enhanced_strobe)(struct sdhci_host *host);
259271 };
260272
261273 struct sdhci_host {
....@@ -280,6 +292,7 @@
280292 struct mmc_config cfg;
281293 };
282294
295
+void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
283296 int sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
284297
285298 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
u-boot/include/spl_ab.h
....@@ -6,6 +6,7 @@
66 #ifndef _SPL_AB_H_
77 #define _SPL_AB_H_
88
9
+#include <spl.h>
910 #include <android_avb/libavb_ab.h>
1011 #include <android_avb/avb_ab_flow.h>
1112
....@@ -45,4 +46,13 @@
4546 */
4647 int spl_ab_decrease_tries(struct blk_desc *dev_desc);
4748
49
+/*
50
+ * spl_ab_decrease_reset
51
+ *
52
+ * @dev_desc: block description
53
+ *
54
+ * return: 0 success, others fail.
55
+ */
56
+int spl_ab_decrease_reset(struct blk_desc *dev_desc);
57
+
4858 #endif
u-boot/include/spl_display.h
....@@ -0,0 +1,28 @@
1
+/* SPDX-License-Identifier: GPL-2.0+ */
2
+/*
3
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
4
+ *
5
+ */
6
+
7
+#ifndef _SPL_DISPLAY_H_
8
+#define _SPL_DISPLAY_H_
9
+
10
+#include <common.h>
11
+#include <drm_modes.h>
12
+#include <mp_boot.h>
13
+
14
+/* SPL display */
15
+#define RK3528_VOP_BASE 0xff840000
16
+#define RK3528_HDMI_BASE 0xff8d0000
17
+#define RK3528_HDMIPHY_BASE 0xffe00000
18
+#define RK3528_CRU_BASE 0xff4a0000
19
+#define RK3528_GPIO0_IOC_BASE 0xff540000
20
+#define RK3528_GPIO_BASE 0xff610000
21
+
22
+struct spl_display_info {
23
+ struct drm_display_mode mode;
24
+ u32 bus_format;
25
+ u32 enabled;
26
+};
27
+#endif
28
+
u-boot/include/u-boot/sha1.h
....@@ -31,7 +31,7 @@
3131 typedef struct
3232 {
3333 unsigned long total[2]; /*!< number of bytes processed */
34
- unsigned long state[5]; /*!< intermediate digest state */
34
+ uint32_t state[5]; /*!< intermediate digest state */
3535 unsigned char buffer[64]; /*!< data block being processed */
3636 }
3737 sha1_context;
u-boot/lib/avb/libavb/avb_sha512.c
....@@ -38,33 +38,6 @@
3838 #include <android_avb/avb_sha.h>
3939 #include <android_avb/avb_util.h>
4040
41
-/* Crypto-v1 is not support sha512 */
42
-#ifdef CONFIG_ROCKCHIP_CRYPTO_V2
43
-void avb_sha512_init(AvbSHA512Ctx* ctx) {
44
- ctx->crypto_ctx.algo = CRYPTO_SHA512;
45
- ctx->crypto_ctx.length = ctx->tot_len;
46
- memset(ctx->buf, 0, sizeof(ctx->buf));
47
-
48
- ctx->crypto_dev = crypto_get_device(ctx->crypto_ctx.algo);
49
- if (!ctx->crypto_dev)
50
- avb_error("Can't get sha512 crypto device\n");
51
- else
52
- crypto_sha_init(ctx->crypto_dev, &ctx->crypto_ctx);
53
-}
54
-
55
-void avb_sha512_update(AvbSHA512Ctx* ctx, const uint8_t* data, size_t len) {
56
- if (ctx->crypto_dev)
57
- crypto_sha_update(ctx->crypto_dev, (u32 *)data, len);
58
-}
59
-
60
-uint8_t* avb_sha512_final(AvbSHA512Ctx* ctx) {
61
- if (ctx->crypto_dev)
62
- crypto_sha_final(ctx->crypto_dev, &ctx->crypto_ctx, ctx->buf);
63
-
64
- return ctx->buf;
65
-}
66
-
67
-#else
6841 #define SHFR(x, n) (x >> n)
6942 #define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n)))
7043 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
....@@ -160,6 +133,19 @@
160133 /* SHA-512 implementation */
161134
162135 void avb_sha512_init(AvbSHA512Ctx* ctx) {
136
+/* Crypto-v1 is not support sha512 */
137
+#ifdef CONFIG_ROCKCHIP_CRYPTO_V2
138
+ ctx->crypto_ctx.algo = CRYPTO_SHA512;
139
+ ctx->crypto_ctx.length = ctx->tot_len;
140
+ memset(ctx->buf, 0, sizeof(ctx->buf));
141
+
142
+ ctx->crypto_dev = crypto_get_device(ctx->crypto_ctx.algo);
143
+ /* If there is no available crypto device, calculate in software instead. */
144
+ if (ctx->crypto_dev) {
145
+ crypto_sha_init(ctx->crypto_dev, &ctx->crypto_ctx);
146
+ return;
147
+ }
148
+#endif
163149 #ifdef UNROLL_LOOPS_SHA512
164150 ctx->h[0] = sha512_h0[0];
165151 ctx->h[1] = sha512_h0[1];
....@@ -347,6 +333,15 @@
347333 }
348334
349335 void avb_sha512_update(AvbSHA512Ctx* ctx, const uint8_t* data, size_t len) {
336
+/* Crypto-v1 is not support sha512 */
337
+#ifdef CONFIG_ROCKCHIP_CRYPTO_V2
338
+ /* If there is no available crypto device, calculate in software instead. */
339
+ if (ctx->crypto_dev) {
340
+ crypto_sha_update(ctx->crypto_dev, (u32 *)data, len);
341
+ return;
342
+ }
343
+#endif
344
+
350345 size_t block_nb;
351346 size_t new_len, rem_len, tmp_len;
352347 const uint8_t* shifted_data;
....@@ -378,6 +373,15 @@
378373 }
379374
380375 uint8_t* avb_sha512_final(AvbSHA512Ctx* ctx) {
376
+/* Crypto-v1 is not support sha512 */
377
+#ifdef CONFIG_ROCKCHIP_CRYPTO_V2
378
+ /* If there is no available crypto device, calculate in software instead. */
379
+ if (ctx->crypto_dev) {
380
+ crypto_sha_final(ctx->crypto_dev, &ctx->crypto_ctx, ctx->buf);
381
+ return ctx->buf;
382
+ }
383
+#endif
384
+
381385 size_t block_nb;
382386 size_t pm_len;
383387 uint64_t len_b;
....@@ -414,4 +418,3 @@
414418
415419 return ctx->buf;
416420 }
417
-#endif
u-boot/lib/avb/libavb/avb_slot_verify.c
....@@ -22,7 +22,7 @@
2222 * SOFTWARE.
2323 */
2424 #include <common.h>
25
-#include <sysmem.h>
25
+#include <android_image.h>
2626 #include <android_avb/avb_slot_verify.h>
2727 #include <android_avb/avb_chain_partition_descriptor.h>
2828 #include <android_avb/avb_cmdline.h>
....@@ -30,6 +30,7 @@
3030 #include <android_avb/avb_hash_descriptor.h>
3131 #include <android_avb/avb_hashtree_descriptor.h>
3232 #include <android_avb/avb_kernel_cmdline_descriptor.h>
33
+#include <android_avb/avb_ops_user.h>
3334 #include <android_avb/avb_sha.h>
3435 #include <android_avb/avb_util.h>
3536 #include <android_avb/avb_vbmeta_image.h>
....@@ -118,7 +119,7 @@
118119
119120 /* Allocate and copy the partition. */
120121 if (!*out_image_preloaded) {
121
- *out_image_buf = sysmem_alloc(MEM_AVB_ANDROID, image_size);
122
+ *out_image_buf = avb_malloc(image_size);
122123 if (*out_image_buf == NULL) {
123124 return AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
124125 }
....@@ -296,7 +297,7 @@
296297 bool image_preloaded = false;
297298 uint8_t* digest;
298299 size_t digest_len;
299
- const char* found;
300
+ const char* found = NULL;
300301 uint64_t image_size;
301302 size_t expected_digest_len = 0;
302303 uint8_t expected_digest_buf[AVB_SHA512_DIGEST_SIZE];
....@@ -388,7 +389,7 @@
388389 allow_verification_error);
389390 if (ret != AVB_SLOT_VERIFY_RESULT_OK) {
390391 goto out;
391
- } else if (image_preloaded) {
392
+ } else if (allow_verification_error) {
392393 goto out;
393394 }
394395
....@@ -482,7 +483,7 @@
482483
483484 fail:
484485 if (image_buf != NULL && !image_preloaded) {
485
- sysmem_free((phys_addr_t)image_buf);
486
+ avb_free(image_buf);
486487 }
487488 return ret;
488489 }
....@@ -556,7 +557,7 @@
556557 out:
557558 /* Free the current buffer if any. */
558559 if (image_buf != NULL && !image_preloaded) {
559
- sysmem_free((phys_addr_t)image_buf);
560
+ avb_free(image_buf);
560561 }
561562 /* Buffers that are already saved in slot_data will be handled by the caller
562563 * even on failure. */
....@@ -1662,7 +1663,7 @@
16621663 avb_free(loaded_partition->partition_name);
16631664 }
16641665 if (loaded_partition->data != NULL && !loaded_partition->preloaded) {
1665
- sysmem_free((phys_addr_t)loaded_partition->data);
1666
+ avb_free(loaded_partition->data);
16661667 }
16671668 }
16681669 avb_free(data->loaded_partitions);
u-boot/lib/avb/libavb_user/Kconfig
....@@ -16,7 +16,6 @@
1616 - only allow "boot_android" as bootcmd;
1717 - enter rockusb or fastboot when boot failed;
1818 - not allow ctrl+c to enter hush;
19
- only the CONFIG_BOOTDELAY can interrupt the bootflow.
2019
2120 config SPL_AVB_LIBAVB_USER
2221 bool "Android AVB read/write hardware for spl"
u-boot/lib/avb/libavb_user/avb_ops_user.c
....@@ -81,10 +81,9 @@
8181 return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
8282 }
8383
84
- if (part_get_info_by_name(dev_desc, partition, &part_info) < 0) {
85
- printf("Could not find \"%s\" partition\n", partition);
84
+ if (part_get_info_by_name(dev_desc, partition, &part_info) < 0)
8685 return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
87
- }
86
+
8887 *out_size_in_bytes = (part_info.size) * 512;
8988 return AVB_IO_RESULT_OK;
9089 }
....@@ -281,6 +280,7 @@
281280 {
282281 if (out_is_unlocked) {
283282 #ifdef CONFIG_OPTEE_CLIENT
283
+ uint8_t vboot_flag = 0;
284284 int ret;
285285
286286 ret = trusty_read_lock_state((uint8_t *)out_is_unlocked);
....@@ -291,7 +291,16 @@
291291 case TEE_ERROR_GENERIC:
292292 case TEE_ERROR_NO_DATA:
293293 case TEE_ERROR_ITEM_NOT_FOUND:
294
- *out_is_unlocked = 1;
294
+ if (trusty_read_vbootkey_enable_flag(&vboot_flag)) {
295
+ printf("Can't read vboot flag\n");
296
+ return AVB_IO_RESULT_ERROR_IO;
297
+ }
298
+
299
+ if (vboot_flag)
300
+ *out_is_unlocked = 0;
301
+ else
302
+ *out_is_unlocked = 1;
303
+
295304 if (trusty_write_lock_state(*out_is_unlocked)) {
296305 printf("%s: init lock state error\n", __FILE__);
297306 ret = AVB_IO_RESULT_ERROR_IO;
....@@ -429,30 +438,111 @@
429438 size_t* out_num_bytes_preloaded,
430439 int allow_verification_error)
431440 {
441
+ struct preloaded_partition *preload_info = NULL;
442
+ struct AvbOpsData *data = ops->user_data;
432443 struct blk_desc *dev_desc;
444
+ disk_partition_t part_info;
433445 ulong load_addr;
434
- int ret;
446
+ AvbIOResult ret;
447
+ int full_preload = 0;
435448
436
- /* no need go further */
437
- if (!allow_verification_error)
438
- return AVB_IO_RESULT_OK;
439
-
440
- printf("get image from preloaded partition...\n");
441449 dev_desc = rockchip_get_bootdev();
442450 if (!dev_desc)
443
- return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
451
+ return AVB_IO_RESULT_ERROR_IO;
444452
445
- load_addr = env_get_ulong("kernel_addr_r", 16, 0);
446
- if (!load_addr)
447
- return AVB_IO_RESULT_ERROR_NO_SUCH_VALUE;
453
+ if (part_get_info_by_name(dev_desc, partition, &part_info) < 0) {
454
+ printf("Could not find \"%s\" partition\n", partition);
455
+ return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
456
+ }
448457
449
- ret = android_image_load_by_partname(dev_desc, partition, &load_addr);
450
- if (!ret) {
451
- *out_pointer = (u8 *)load_addr;
452
- *out_num_bytes_preloaded = num_bytes; /* return what it expects */
458
+ if (!allow_verification_error) {
459
+ if (!strncmp(partition, ANDROID_PARTITION_BOOT, 4) ||
460
+ !strncmp(partition, ANDROID_PARTITION_RECOVERY, 8))
461
+ preload_info = &data->boot;
462
+ else if (!strncmp(partition, ANDROID_PARTITION_VENDOR_BOOT, 11))
463
+ preload_info = &data->vendor_boot;
464
+ else if (!strncmp(partition, ANDROID_PARTITION_INIT_BOOT, 9))
465
+ preload_info = &data->init_boot;
466
+ else if (!strncmp(partition, ANDROID_PARTITION_RESOURCE, 8))
467
+ preload_info = &data->resource;
468
+
469
+ if (!preload_info) {
470
+ printf("Error: unknown full load partition '%s'\n", partition);
471
+ return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
472
+ }
473
+
474
+ printf("preloaded(s): %sfull image from '%s' at 0x%08lx - 0x%08lx\n",
475
+ preload_info->size ? "pre-" : "", partition,
476
+ (ulong)preload_info->addr,
477
+ (ulong)preload_info->addr + num_bytes);
478
+
479
+ /* If the partition hasn't yet been preloaded, do it now.*/
480
+ if (preload_info->size == 0) {
481
+ ret = ops->read_from_partition(ops, partition,
482
+ 0, num_bytes,
483
+ preload_info->addr,
484
+ &preload_info->size);
485
+ if (ret != AVB_IO_RESULT_OK)
486
+ return ret;
487
+ }
488
+ *out_pointer = preload_info->addr;
489
+ *out_num_bytes_preloaded = preload_info->size;
453490 ret = AVB_IO_RESULT_OK;
454491 } else {
455
- ret = AVB_IO_RESULT_ERROR_IO;
492
+ if (!strncmp(partition, ANDROID_PARTITION_INIT_BOOT, 9) ||
493
+ !strncmp(partition, ANDROID_PARTITION_VENDOR_BOOT, 11) ||
494
+ !strncmp(partition, ANDROID_PARTITION_BOOT, 4) ||
495
+ !strncmp(partition, ANDROID_PARTITION_RECOVERY, 8) ||
496
+ !strncmp(partition, ANDROID_PARTITION_RESOURCE, 8)) {
497
+ /* If already full preloaded, just use it */
498
+ if (!strncmp(partition, ANDROID_PARTITION_BOOT, 4) ||
499
+ !strncmp(partition, ANDROID_PARTITION_RECOVERY, 8)) {
500
+ preload_info = &data->boot;
501
+ if (preload_info->size) {
502
+ *out_pointer = preload_info->addr;
503
+ *out_num_bytes_preloaded = num_bytes;
504
+ full_preload = 1;
505
+ }
506
+ }
507
+ printf("preloaded: %s image from '%s\n",
508
+ full_preload ? "pre-full" : "distribute", partition);
509
+ } else {
510
+ printf("Error: unknown preloaded partition '%s'\n", partition);
511
+ return AVB_IO_RESULT_ERROR_OOM;
512
+ }
513
+
514
+ /*
515
+ * Already preloaded during boot/recovery loading,
516
+ * here we just return a dummy buffer.
517
+ */
518
+ if (!strncmp(partition, ANDROID_PARTITION_INIT_BOOT, 9) ||
519
+ !strncmp(partition, ANDROID_PARTITION_VENDOR_BOOT, 11) ||
520
+ !strncmp(partition, ANDROID_PARTITION_RESOURCE, 8)) {
521
+ *out_pointer = (u8 *)avb_malloc(ARCH_DMA_MINALIGN);
522
+ *out_num_bytes_preloaded = num_bytes; /* return what it expects */
523
+ return AVB_IO_RESULT_OK;
524
+ }
525
+
526
+ /* If already full preloaded, there is nothing to do and just return */
527
+ if (full_preload)
528
+ return AVB_IO_RESULT_OK;
529
+
530
+ /*
531
+ * only boot/recovery partition can reach here
532
+ * and init/vendor_boot are loaded at this round.
533
+ */
534
+ load_addr = env_get_ulong("kernel_addr_r", 16, 0);
535
+ if (!load_addr)
536
+ return AVB_IO_RESULT_ERROR_NO_SUCH_VALUE;
537
+
538
+ ret = android_image_load_by_partname(dev_desc, partition, &load_addr);
539
+ if (!ret) {
540
+ *out_pointer = (u8 *)load_addr;
541
+ *out_num_bytes_preloaded = num_bytes; /* return what it expects */
542
+ ret = AVB_IO_RESULT_OK;
543
+ } else {
544
+ ret = AVB_IO_RESULT_ERROR_IO;
545
+ }
456546 }
457547
458548 return ret;
....@@ -489,7 +579,8 @@
489579
490580 AvbOps *avb_ops_user_new(void)
491581 {
492
- AvbOps *ops;
582
+ AvbOps *ops = NULL;
583
+ struct AvbOpsData *ops_data = NULL;
493584
494585 ops = calloc(1, sizeof(AvbOps));
495586 if (!ops) {
....@@ -510,8 +601,20 @@
510601 free(ops);
511602 goto out;
512603 }
604
+
605
+ ops_data = calloc(1, sizeof(struct AvbOpsData));
606
+ if (!ops_data) {
607
+ printf("Error allocating memory for AvbOpsData.\n");
608
+ free(ops->atx_ops);
609
+ free(ops->ab_ops);
610
+ free(ops);
611
+ goto out;
612
+ }
613
+
513614 ops->ab_ops->ops = ops;
514615 ops->atx_ops->ops = ops;
616
+ ops_data->ops = ops;
617
+ ops->user_data = ops_data;
515618
516619 ops->read_from_partition = read_from_partition;
517620 ops->write_to_partition = write_to_partition;
....@@ -533,12 +636,14 @@
533636 ops->atx_ops->set_key_version = avb_set_key_version;
534637 ops->atx_ops->get_random = rk_get_random;
535638
536
-out:
537639 return ops;
640
+out:
641
+ return NULL;
538642 }
539643
540644 void avb_ops_user_free(AvbOps *ops)
541645 {
646
+ free(ops->user_data);
542647 free(ops->ab_ops);
543648 free(ops->atx_ops);
544649 free(ops);
u-boot/lib/avb/rk_avb_user/rk_avb_ops_user.c
....@@ -158,6 +158,7 @@
158158 int rk_avb_read_lock_state(uint8_t *lock_state)
159159 {
160160 #ifdef CONFIG_OPTEE_CLIENT
161
+ uint8_t vboot_flag = 0;
161162 int ret;
162163
163164 ret = trusty_read_lock_state(lock_state);
....@@ -167,7 +168,16 @@
167168 case TEE_ERROR_GENERIC:
168169 case TEE_ERROR_NO_DATA:
169170 case TEE_ERROR_ITEM_NOT_FOUND:
170
- *lock_state = 1;
171
+ if (trusty_read_vbootkey_enable_flag(&vboot_flag)) {
172
+ printf("Can't read vboot flag\n");
173
+ return -1;
174
+ }
175
+
176
+ if (vboot_flag)
177
+ *lock_state = 0;
178
+ else
179
+ *lock_state = 1;
180
+
171181 if (rk_avb_write_lock_state(*lock_state)) {
172182 printf("avb_write_lock_state error!");
173183 ret = -1;
u-boot/lib/optee_clientApi/OpteeClientInterface.c
....@@ -73,6 +73,20 @@
7373 flush_cache(aligned_input, aligned_len);
7474 }
7575
76
+static void crypto_invalidate_cacheline(uint32_t addr, uint32_t size)
77
+{
78
+ ulong alignment = CONFIG_SYS_CACHELINE_SIZE;
79
+ ulong aligned_input, aligned_len;
80
+
81
+ if (!addr || !size)
82
+ return;
83
+
84
+ /* Must invalidate dcache after crypto DMA write data region */
85
+ aligned_input = round_down(addr, alignment);
86
+ aligned_len = round_up(size + (addr - aligned_input), alignment);
87
+ invalidate_dcache_range(aligned_input, aligned_input + aligned_len);
88
+}
89
+
7690 static uint32_t trusty_base_write_security_data(char *filename,
7791 uint32_t filename_size,
7892 uint8_t *data,
....@@ -1014,6 +1028,8 @@
10141028 &TeecOperation,
10151029 &ErrorOrigin);
10161030
1031
+ crypto_invalidate_cacheline(dst_phys_addr, len);
1032
+
10171033 exit:
10181034 TEEC_ReleaseSharedMemory(&SharedMem_config);
10191035 TEEC_CloseSession(&TeecSession);
u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v1.c
....@@ -528,7 +528,7 @@
528528 {
529529 unsigned char *cp, *vp;
530530 struct rkss_file_verification *verify;
531
- int ret, i;
531
+ int ret, i, write_table_flag = 0;
532532
533533 for (i = 0; i < RKSS_PARTITION_TABLE_COUNT; i++) {
534534 cp = table_data + (i * RKSS_DATA_SECTION_LEN);
....@@ -541,12 +541,15 @@
541541 memset(cp, 0, RKSS_DATA_SECTION_LEN);
542542 verify->checkstr = RKSS_CHECK_STR;
543543 verify->version = RKSS_VERSION_V1;
544
+ write_table_flag = 1;
544545 }
545546 }
546
- ret = rkss_write_multi_sections(table_data, 0, RKSS_PARTITION_TABLE_COUNT);
547
- if (ret < 0) {
548
- printf("TEEC: rkss_write_multi_sections failed!!! ret: %d.\n", ret);
549
- return TEEC_ERROR_GENERIC;
547
+ if (write_table_flag == 1) {
548
+ ret = rkss_write_multi_sections(table_data, 0, RKSS_PARTITION_TABLE_COUNT);
549
+ if (ret < 0) {
550
+ printf("TEEC: rkss_write_multi_sections failed!!! ret: %d.\n", ret);
551
+ return TEEC_ERROR_GENERIC;
552
+ }
550553 }
551554 debug("TEEC: verify ptable success.\n");
552555 return TEEC_SUCCESS;
u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v2.c
....@@ -1384,7 +1384,6 @@
13841384 case OPTEE_MRF_CLOSE:
13851385 debug(">>>>>>> [%d] OPTEE_MRF_CLOSE!\n", rkss_step++);
13861386 ret = ree_fs_new_close(num_params, params);
1387
- rkss_storage_write();
13881387 break;
13891388 case OPTEE_MRF_READ:
13901389 debug(">>>>>>> [%d] OPTEE_MRF_READ!\n", rkss_step++);
....@@ -1401,12 +1400,10 @@
14011400 case OPTEE_MRF_REMOVE:
14021401 debug(">>>>>>> [%d] OPTEE_MRF_REMOVE!\n", rkss_step++);
14031402 ret = ree_fs_new_remove(num_params, params);
1404
- rkss_storage_write();
14051403 break;
14061404 case OPTEE_MRF_RENAME:
14071405 debug(">>>>>>> [%d] OPTEE_MRF_RENAME!\n", rkss_step++);
14081406 ret = ree_fs_new_rename(num_params, params);
1409
- rkss_storage_write();
14101407 break;
14111408 case OPTEE_MRF_OPENDIR:
14121409 debug(">>>>>>> [%d] OPTEE_MRF_OPENDIR!\n", rkss_step++);
....@@ -1424,5 +1421,6 @@
14241421 ret = TEEC_ERROR_BAD_PARAMETERS;
14251422 break;
14261423 }
1424
+ rkss_storage_write();
14271425 return ret;
14281426 }
u-boot/lib/rsa/rsa-sign.c
....@@ -610,7 +610,7 @@
610610 BIGNUM **modulusp, BIGNUM **exponent_BN, BIGNUM **r_squaredp,
611611 BIGNUM **c_factorp, BIGNUM **np_factorp)
612612 {
613
- BIGNUM *big1, *big2, *big32, *big2_32, *big4100, *big2180;
613
+ BIGNUM *big1, *big2, *big32, *big2_32, *big4100, *big2180, *big4228;
614614 BIGNUM *n, *e, *r, *r_squared, *tmp, *c_factor, *np_factor;
615615 const BIGNUM *key_n, *key_e;
616616 BN_CTX *bn_ctx = BN_CTX_new();
....@@ -622,6 +622,7 @@
622622 big32 = BN_new();
623623 big4100 = BN_new();
624624 big2180 = BN_new();
625
+ big4228 = BN_new();
625626
626627 r = BN_new();
627628 r_squared = BN_new();
....@@ -631,7 +632,7 @@
631632 big2_32 = BN_new();
632633 n = BN_new();
633634 e = BN_new();
634
- if (!big1 || !big2 || !big32 || !big4100 || !big2180 || !r ||
635
+ if (!big1 || !big2 || !big32 || !big4100 || !big2180 || !big4228 || !r ||
635636 !r_squared || !tmp || !big2_32 || !n || !e ||
636637 !c_factor || !np_factor) {
637638 fprintf(stderr, "Out of memory (bignum)\n");
....@@ -645,7 +646,8 @@
645646 if (!BN_copy(n, key_n) || !BN_copy(e, key_e) ||
646647 !BN_set_word(big1, 1L) ||
647648 !BN_set_word(big2, 2L) || !BN_set_word(big32, 32L) ||
648
- !BN_set_word(big4100, 4100L) || !BN_set_word(big2180, 2180L))
649
+ !BN_set_word(big4100, 4100L) || !BN_set_word(big2180, 2180L) ||
650
+ !BN_set_word(big4228, 4228L))
649651 ret = -1;
650652
651653 /* big2_32 = 2^32 */
....@@ -675,9 +677,15 @@
675677 ret = -1;
676678
677679 /* Calculate np_factor = 2^2180 div n */
678
- if (!BN_exp(tmp, big2, big2180, bn_ctx) ||
679
- !BN_div(np_factor, NULL, tmp, n, bn_ctx))
680
- ret = -1;
680
+ if (BN_num_bits(n) == 2048) {
681
+ if (!BN_exp(tmp, big2, big2180, bn_ctx) ||
682
+ !BN_div(np_factor, NULL, tmp, n, bn_ctx))
683
+ ret = -1;
684
+ } else {/* Calculate 4096 np_factor = 2^4228 div n */
685
+ if (!BN_exp(tmp, big2, big4228, bn_ctx) ||
686
+ !BN_div(np_factor, NULL, tmp, n, bn_ctx))
687
+ ret = -1;
688
+ }
681689
682690 *modulusp = n;
683691 *exponent_BN = e;
....@@ -690,6 +698,7 @@
690698 BN_free(big32);
691699 BN_free(big4100);
692700 BN_free(big2180);
701
+ BN_free(big4228);
693702 BN_free(r);
694703 BN_free(tmp);
695704 BN_free(big2_32);
u-boot/lib/rsa/rsa-verify.c
....@@ -86,11 +86,17 @@
8686 uint8_t buf[sig_len];
8787 rsa_key rsa_key;
8888 int i, ret;
89
+#ifdef CONFIG_FIT_ENABLE_RSA4096_SUPPORT
90
+ if (key_len != RSA4096_BYTES)
91
+ return -EINVAL;
8992
93
+ rsa_key.algo = CRYPTO_RSA4096;
94
+#else
9095 if (key_len != RSA2048_BYTES)
9196 return -EINVAL;
9297
9398 rsa_key.algo = CRYPTO_RSA2048;
99
+#endif
94100 rsa_key.n = malloc(key_len);
95101 rsa_key.e = malloc(key_len);
96102 rsa_key.c = malloc(key_len);
....@@ -599,7 +605,7 @@
599605 struct udevice *dev;
600606 struct key_prop prop;
601607 char name[100] = {0};
602
- u16 secure_boot_enable = 0;
608
+ u16 secure_flags = 0;
603609 const void *blob = info->fdt_blob;
604610 uint8_t digest[FIT_MAX_HASH_LEN];
605611 uint8_t digest_read[FIT_MAX_HASH_LEN];
....@@ -610,11 +616,11 @@
610616 return -ENODEV;
611617
612618 ret = misc_otp_read(dev, OTP_SECURE_BOOT_ENABLE_ADDR,
613
- &secure_boot_enable, OTP_SECURE_BOOT_ENABLE_SIZE);
619
+ &secure_flags, OTP_SECURE_BOOT_ENABLE_SIZE);
614620 if (ret)
615621 return ret;
616622
617
- if (secure_boot_enable)
623
+ if (secure_flags == 0xff)
618624 return 0;
619625
620626 sig_node = fdt_subnode_offset(blob, 0, FIT_SIG_NODENAME);
....@@ -701,9 +707,9 @@
701707 goto error;
702708 }
703709
704
- secure_boot_enable = 0xff;
710
+ secure_flags = 0xff;
705711 ret = misc_otp_write(dev, OTP_SECURE_BOOT_ENABLE_ADDR,
706
- &secure_boot_enable, OTP_SECURE_BOOT_ENABLE_SIZE);
712
+ &secure_flags, OTP_SECURE_BOOT_ENABLE_SIZE);
707713 if (ret)
708714 goto error;
709715
u-boot/lib/sha1.c
....@@ -26,6 +26,15 @@
2626 #include <watchdog.h>
2727 #include <u-boot/sha1.h>
2828
29
+#include <linux/compiler.h>
30
+
31
+#ifdef USE_HOSTCC
32
+#undef __weak
33
+#define __weak
34
+#undef __maybe_unused
35
+#define __maybe_unused
36
+#endif
37
+
2938 const uint8_t sha1_der_prefix[SHA1_DER_LEN] = {
3039 0x30, 0x21, 0x30, 0x09, 0x06, 0x05, 0x2b, 0x0e,
3140 0x03, 0x02, 0x1a, 0x05, 0x00, 0x04, 0x14
....@@ -66,7 +75,7 @@
6675 ctx->state[4] = 0xC3D2E1F0;
6776 }
6877
69
-static void sha1_process(sha1_context *ctx, const unsigned char data[64])
78
+static void __maybe_unused sha1_process_one(sha1_context *ctx, const unsigned char data[64])
7079 {
7180 unsigned long temp, W[16], A, B, C, D, E;
7281
....@@ -220,6 +229,18 @@
220229 ctx->state[4] += E;
221230 }
222231
232
+__weak void sha1_process(sha1_context *ctx, const unsigned char *data,
233
+ unsigned int blocks)
234
+{
235
+ if (!blocks)
236
+ return;
237
+
238
+ while (blocks--) {
239
+ sha1_process_one(ctx, data);
240
+ data += 64;
241
+ }
242
+}
243
+
223244 /*
224245 * SHA-1 process buffer
225246 */
....@@ -243,17 +264,15 @@
243264
244265 if (left && ilen >= fill) {
245266 memcpy ((void *) (ctx->buffer + left), (void *) input, fill);
246
- sha1_process (ctx, ctx->buffer);
267
+ sha1_process(ctx, ctx->buffer, 1);
247268 input += fill;
248269 ilen -= fill;
249270 left = 0;
250271 }
251272
252
- while (ilen >= 64) {
253
- sha1_process (ctx, input);
254
- input += 64;
255
- ilen -= 64;
256
- }
273
+ sha1_process(ctx, input, ilen / 64);
274
+ input += ilen / 64 * 64;
275
+ ilen = ilen % 64;
257276
258277 if (ilen > 0) {
259278 memcpy ((void *) (ctx->buffer + left), (void *) input, ilen);
u-boot/lib/sha256.c
....@@ -15,6 +15,13 @@
1515 #include <watchdog.h>
1616 #include <u-boot/sha256.h>
1717
18
+#include <linux/compiler.h>
19
+
20
+#ifdef USE_HOSTCC
21
+#undef __weak
22
+#define __weak
23
+#endif
24
+
1825 const uint8_t sha256_der_prefix[SHA256_DER_LEN] = {
1926 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86,
2027 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05,
....@@ -56,7 +63,7 @@
5663 ctx->state[7] = 0x5BE0CD19;
5764 }
5865
59
-static void sha256_process(sha256_context *ctx, const uint8_t data[64])
66
+static void sha256_process_one(sha256_context *ctx, const uint8_t data[64])
6067 {
6168 uint32_t temp1, temp2;
6269 uint32_t W[64];
....@@ -187,6 +194,18 @@
187194 ctx->state[7] += H;
188195 }
189196
197
+__weak void sha256_process(sha256_context *ctx, const unsigned char *data,
198
+ unsigned int blocks)
199
+{
200
+ if (!blocks)
201
+ return;
202
+
203
+ while (blocks--) {
204
+ sha256_process_one(ctx, data);
205
+ data += 64;
206
+ }
207
+}
208
+
190209 void sha256_update(sha256_context *ctx, const uint8_t *input, uint32_t length)
191210 {
192211 uint32_t left, fill;
....@@ -205,17 +224,15 @@
205224
206225 if (left && length >= fill) {
207226 memcpy((void *) (ctx->buffer + left), (void *) input, fill);
208
- sha256_process(ctx, ctx->buffer);
227
+ sha256_process(ctx, ctx->buffer, 1);
209228 length -= fill;
210229 input += fill;
211230 left = 0;
212231 }
213232
214
- while (length >= 64) {
215
- sha256_process(ctx, input);
216
- length -= 64;
217
- input += 64;
218
- }
233
+ sha256_process(ctx, input, length / 64);
234
+ input += length / 64 * 64;
235
+ length = length % 64;
219236
220237 if (length)
221238 memcpy((void *) (ctx->buffer + left), (void *) input, length);
u-boot/make.sh
....@@ -13,7 +13,7 @@
1313 ########################################### User can modify #############################################
1414 RKBIN_TOOLS=../rkbin/tools
1515 CROSS_COMPILE_ARM32=../prebuilts/gcc/linux-x86/arm/gcc-linaro-6.3.1-2017.05-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-
16
-CROSS_COMPILE_ARM64=../prebuilts/gcc/linux-x86/aarch64/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
16
+CROSS_COMPILE_ARM64=../prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu-
1717 ########################################### User not touch #############################################
1818 # Declare global INI file searching index name for every chip, update in select_chip_info()
1919 RKCHIP=
....@@ -48,6 +48,7 @@
4848 SCRIPT_UBOOT="${SRCTREE}/scripts/uboot.sh"
4949 SCRIPT_LOADER="${SRCTREE}/scripts/loader.sh"
5050 SCRIPT_DECOMP="${SRCTREE}/scripts/decomp.sh"
51
+SCRIPT_CHECKCONFIG="${SRCTREE}/scripts/check-rkconfig.sh"
5152 CC_FILE=".cc"
5253 REP_DIR="./rep"
5354 #########################################################################################################
....@@ -268,7 +269,7 @@
268269 CROSS_COMPILE_ARM64=`cat ${CC_FILE}`
269270 else
270271 if grep -q '^CONFIG_ARM64=y' .config ; then
271
- CROSS_COMPILE_ARM64=$(cd `dirname ${CROSS_COMPILE_ARM64}`; pwd)"/aarch64-linux-gnu-"
272
+ CROSS_COMPILE_ARM64=$(cd `dirname ${CROSS_COMPILE_ARM64}`; pwd)"/aarch64-none-linux-gnu-"
272273 else
273274 CROSS_COMPILE_ARM32=$(cd `dirname ${CROSS_COMPILE_ARM32}`; pwd)"/arm-linux-gnueabihf-"
274275 fi
....@@ -768,6 +769,9 @@
768769
769770 function finish()
770771 {
772
+ # check special config
773
+ ${SCRIPT_CHECKCONFIG}
774
+
771775 echo
772776 if [ "${ARG_BOARD}" == "" ]; then
773777 echo "Platform ${RKCHIP_LABEL} is build OK, with exist .config"
u-boot/scripts/README.rockchip
....@@ -33,7 +33,7 @@
3333 ./scripts/stacktrace.sh dump.txt tpl
3434
3535 # avbtool.py
36
- ./avbtool.py info_image --image vbmeta.img
36
+ ./scripts/avbtool.py info_image --image vbmeta.img
3737
3838 [tools]
3939 # resource_tool
u-boot/scripts/android2fit.sh
....@@ -61,9 +61,9 @@
6161
6262 rm images/ -rf && mkdir -p images/
6363 cp ${OUT}/kernel images/
64
- cp ${OUT}/resource images/
64
+ cp ${OUT}/resource images/second
6565 cp ${OUT}/ramdisk images/
66
- cp ${OUT}/rk-kernel.dtb images/
66
+ cp ${OUT}/rk-kernel.dtb images/dtb
6767 rm ${OUT}/ -rf
6868
6969 ./make.sh fit
u-boot/scripts/check-rkconfig.sh
....@@ -0,0 +1,23 @@
1
+#!/bin/bash
2
+#
3
+# Copyright (c) 2023 Rockchip Electronics Co., Ltd
4
+#
5
+# SPDX-License-Identifier: GPL-2.0
6
+#
7
+
8
+set -e
9
+
10
+if [ -f dts/kern.dtb ]; then
11
+ if ! grep -Eq 'CONFIG_EMBED_KERNEL_DTB=y' .config ; then
12
+ echo "ERROR: dts/kern.dtb was found, but CONFIG_EMBED_KERNEL_DTB is disabled."
13
+ exit 1
14
+ fi
15
+fi
16
+
17
+if grep -Eq 'CONFIG_EMBED_KERNEL_DTB=y' .config ; then
18
+ KDTB=`sed -n "/CONFIG_EMBED_KERNEL_DTB_PATH=/s/CONFIG_EMBED_KERNEL_DTB_PATH=//p" .config | tr -d '\r' | tr -d '"'`
19
+ if [ ! -f ${KDTB} ]; then
20
+ echo "ERROR: '${KDTB}' was not found assigned by CONFIG_EMBED_KERNEL_DTB_PATH."
21
+ exit 1
22
+ fi
23
+fi
u-boot/scripts/fit-core.sh
....@@ -18,9 +18,11 @@
1818 SIG_BOOT="${FIT_DIR}/boot.data2sign"
1919 SIG_RECOVERY="${FIT_DIR}/recovery.data2sign"
2020 # offs
21
-OFFS_DATA="0x1000"
22
-# file
23
-CHIP_FILE="arch/arm/lib/.asm-offsets.s.cmd"
21
+if grep -q '^CONFIG_FIT_ENABLE_RSA4096_SUPPORT=y' .config ; then
22
+ OFFS_DATA="0x1200"
23
+else
24
+ OFFS_DATA="0x1000"
25
+fi
2426 # placeholder address
2527 FDT_ADDR_PLACEHOLDER="0xffffff00"
2628 KERNEL_ADDR_PLACEHOLDER="0xffffff01"
....@@ -94,6 +96,19 @@
9496 exit 1
9597 fi
9698 done
99
+}
100
+
101
+function check_rsa_algo()
102
+{
103
+ if grep -q '^CONFIG_FIT_ENABLE_RSA4096_SUPPORT=y' .config ; then
104
+ rsa_algo="rsa4096"
105
+ else
106
+ rsa_algo="rsa2048"
107
+ fi
108
+ if ! grep -qr ${rsa_algo} $1 ; then
109
+ echo "ERROR: Wrong rsa_algo in its file. It should be ${rsa_algo}."
110
+ exit 1
111
+ fi
97112 }
98113
99114 function check_rsa_keys()
....@@ -378,6 +393,8 @@
378393 else
379394 check_rsa_keys
380395
396
+ check_rsa_algo ${ITS_BOOT}
397
+
381398 if ! grep -q '^CONFIG_FIT_SIGNATURE=y' .config ; then
382399 echo "ERROR: CONFIG_FIT_SIGNATURE is disabled"
383400 exit 1
....@@ -396,10 +413,9 @@
396413 fi
397414
398415 # fixup
399
- COMMON_FILE=`sed -n "/_common.h/p" ${CHIP_FILE} | awk '{ print $1 }'`
400
- FDT_ADDR_R=`awk /fdt_addr_r/ ${COMMON_FILE} | awk -F '=' '{ print $2 }' | awk -F '\\' '{ print $1 }'`
401
- KERNEL_ADDR_R=`awk /kernel_addr_r/ ${COMMON_FILE} | awk -F '=' '{ print $2 }' | awk -F '\\' '{ print $1 }'`
402
- RMADISK_ADDR_R=`awk /ramdisk_addr_r/ ${COMMON_FILE} | awk -F '=' '{ print $2 }' | awk -F '\\' '{ print $1 }'`
416
+ FDT_ADDR_R=`strings env/built-in.o | grep 'fdt_addr_r=' | awk -F "=" '{ print $2 }'`
417
+ KERNEL_ADDR_R=`strings env/built-in.o | grep 'kernel_addr_r=' | awk -F "=" '{ print $2 }'`
418
+ RMADISK_ADDR_R=`strings env/built-in.o | grep 'ramdisk_addr_r=' | awk -F "=" '{ print $2 }'`
403419 sed -i "s/${FDT_ADDR_PLACEHOLDER}/${FDT_ADDR_R}/g" ${ITS_BOOT}
404420 sed -i "s/${KERNEL_ADDR_PLACEHOLDER}/${KERNEL_ADDR_R}/g" ${ITS_BOOT}
405421 sed -i "s/${RAMDISK_ADDR_PLACEHOLDER}/${RMADISK_ADDR_R}/g" ${ITS_BOOT}
....@@ -464,6 +480,8 @@
464480 else
465481 check_rsa_keys
466482
483
+ check_rsa_algo ${ITS_RECOVERY}
484
+
467485 if ! grep -q '^CONFIG_FIT_SIGNATURE=y' .config ; then
468486 echo "ERROR: CONFIG_FIT_SIGNATURE is disabled"
469487 exit 1
....@@ -482,10 +500,9 @@
482500 fi
483501
484502 # fixup
485
- COMMON_FILE=`sed -n "/_common.h/p" ${CHIP_FILE} | awk '{ print $1 }'`
486
- FDT_ADDR_R=`awk /fdt_addr_r/ ${COMMON_FILE} | awk -F '=' '{ print $2 }' | awk -F '\\' '{ print $1 }'`
487
- KERNEL_ADDR_R=`awk /kernel_addr_r/ ${COMMON_FILE} | awk -F '=' '{ print $2 }' | awk -F '\\' '{ print $1 }'`
488
- RMADISK_ADDR_R=`awk /ramdisk_addr_r/ ${COMMON_FILE} | awk -F '=' '{ print $2 }' | awk -F '\\' '{ print $1 }'`
503
+ FDT_ADDR_R=`strings env/built-in.o | grep 'fdt_addr_r=' | awk -F "=" '{ print $2 }'`
504
+ KERNEL_ADDR_R=`strings env/built-in.o | grep 'kernel_addr_r=' | awk -F "=" '{ print $2 }'`
505
+ RMADISK_ADDR_R=`strings env/built-in.o | grep 'ramdisk_addr_r=' | awk -F "=" '{ print $2 }'`
489506 sed -i "s/${FDT_ADDR_PLACEHOLDER}/${FDT_ADDR_R}/g" ${ITS_RECOVERY}
490507 sed -i "s/${KERNEL_ADDR_PLACEHOLDER}/${KERNEL_ADDR_R}/g" ${ITS_RECOVERY}
491508 sed -i "s/${RAMDISK_ADDR_PLACEHOLDER}/${RMADISK_ADDR_R}/g" ${ITS_RECOVERY}
u-boot/scripts/setlocalversion
....@@ -60,8 +60,6 @@
6060 # "v2.6.30-rc5-302-g72357d5"), we pretty print it.
6161 if atag="`git describe 2>/dev/null`"; then
6262 echo "$atag" | awk -F- '{printf("-%s", $(NF))}'
63
- date=`git log -1 --author='@rock-chips' --date=format:%y%m%d | sed -n '/Date:/p' | awk '{ print "-"$2 }'`
64
- printf '%s' $date
6563
6664 # If we don't have a tag at all we print -g{commitish}.
6765 else
....@@ -74,11 +72,16 @@
7472 printf -- '-svn%s' "`git svn find-rev $head`"
7573 fi
7674
75
+ # Check submit date of the last rockchip commit
76
+ date=`git log -1 --author='@rock-chips' --date=format:%y%m%d | sed -n '/Date:/p' | awk '{ print "-"$2 }'`
77
+ printf '%s' $date
78
+
7779 # Check for uncommitted changes
7880 if git diff-index --name-only HEAD | grep -qv "^scripts/package"; then
7981 printf '%s' -dirty
8082 fi
8183
84
+ # Print build user
8285 printf ' \#%s' $USER
8386
8487 # All done with git
u-boot/tools/Makefile
....@@ -59,15 +59,9 @@
5959
6060 # Rockchip pack tools
6161 ifdef CONFIG_ARCH_ROCKCHIP
62
-hostprogs-y += boot_merger
63
-hostprogs-y += trust_merger
64
-hostprogs-y += loaderimage
6562 hostprogs-y += resource_tool
6663 hostprogs-y += bmp2gray16
6764
68
-boot_merger-objs := rockchip/boot_merger.o rockchip/sha2.o lib/sha256.o
69
-trust_merger-objs := rockchip/trust_merger.o rockchip/sha2.o lib/sha256.o
70
-loaderimage-objs := rockchip/loaderimage.o rockchip/sha.o lib/sha256.o rockchip/crc32_rk.o
7165 resource_tool-objs := rockchip/resource_tool.o
7266 bmp2gray16-objs := rockchip/bmp2gray16.o
7367 endif
u-boot/tools/rkcommon.c
....@@ -138,6 +138,8 @@
138138 { "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
139139 { "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
140140 { "rk1808", "RK18", 0x200000 - 0x2000, false, RK_HEADER_V1 },
141
+ { "rk3528", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
142
+ { "rk3562", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
141143 { "rk3568", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
142144 { "rk3588", "RK35", 0x100000 - 0x1000, false, RK_HEADER_V2 },
143145 };
u-boot/usb_update.txt
....@@ -0,0 +1,4 @@
1
+# script file start
2
+echo "this is usb update script!"
3
+
4
+% script file end