old mode 100644new mode 100755| .. | .. |
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| 16 | 16 | #include "reg_access.h" |
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| 17 | 17 | #include "hal_desc.h" |
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| 18 | 18 | #include "rwnx_main.h" |
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| 19 | | -#include "rwnx_pci.h" |
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| 20 | 19 | #ifndef CONFIG_RWNX_FHOST |
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| 21 | 20 | #include "ipc_host.h" |
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| 22 | 21 | #endif /* !CONFIG_RWNX_FHOST */ |
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| .. | .. |
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| 30 | 29 | #include "aicwf_usb.h" |
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| 31 | 30 | #endif |
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| 32 | 31 | |
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| 33 | | -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0) |
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| 34 | | -MODULE_IMPORT_NS(VFS_internal_I_am_really_a_filesystem_and_am_NOT_a_driver); |
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| 32 | +#ifdef AICWF_PCIE_SUPPORT |
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| 33 | +#include "rwnx_pci.h" |
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| 35 | 34 | #endif |
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| 36 | 35 | |
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| 37 | 36 | struct rwnx_plat *g_rwnx_plat; |
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| .. | .. |
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| 225 | 224 | return err; |
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| 226 | 225 | } |
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| 227 | 226 | #endif |
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| 228 | | -#endif /* !CONFIG_ROM_PATCH_EN */ |
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| 229 | 227 | |
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| 230 | | -#if 0 |
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| 231 | | -#ifndef CONFIG_RWNX_TL4 |
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| 232 | | -#define IHEX_REC_DATA 0 |
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| 233 | | -#define IHEX_REC_EOF 1 |
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| 234 | | -#define IHEX_REC_EXT_SEG_ADD 2 |
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| 235 | | -#define IHEX_REC_START_SEG_ADD 3 |
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| 236 | | -#define IHEX_REC_EXT_LIN_ADD 4 |
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| 237 | | -#define IHEX_REC_START_LIN_ADD 5 |
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| 228 | +typedef struct { |
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| 229 | + txpwr_idx_conf_t txpwr_idx; |
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| 230 | + txpwr_ofst_conf_t txpwr_ofst; |
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| 231 | +} nvram_info_t; |
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| 238 | 232 | |
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| 239 | | -/** |
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| 240 | | - * rwnx_plat_ihex_fw_upload() - Load the requested intel hex 8 FW into embedded side. |
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| 241 | | - * |
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| 242 | | - * @rwnx_plat: pointer to platform structure |
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| 243 | | - * @fw_addr: Virtual address where the fw must be loaded |
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| 244 | | - * @filename: Name of the fw. |
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| 245 | | - * |
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| 246 | | - * Load a fw, stored as a ihex file, into the specified address. |
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| 247 | | - */ |
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| 248 | | -static int rwnx_plat_ihex_fw_upload(struct rwnx_plat *rwnx_plat, u8 *fw_addr, |
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| 249 | | - char *filename) |
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| 233 | +nvram_info_t nvram_info = { |
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| 234 | + .txpwr_idx = { |
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| 235 | + .enable = 1, |
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| 236 | + .dsss = 9, |
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| 237 | + .ofdmlowrate_2g4 = 8, |
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| 238 | + .ofdm64qam_2g4 = 8, |
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| 239 | + .ofdm256qam_2g4 = 8, |
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| 240 | + .ofdm1024qam_2g4 = 8, |
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| 241 | + .ofdmlowrate_5g = 11, |
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| 242 | + .ofdm64qam_5g = 10, |
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| 243 | + .ofdm256qam_5g = 9, |
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| 244 | + .ofdm1024qam_5g = 9 |
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| 245 | + }, |
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| 246 | + .txpwr_ofst = { |
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| 247 | + .enable = 1, |
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| 248 | + .chan_1_4 = 0, |
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| 249 | + .chan_5_9 = 0, |
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| 250 | + .chan_10_13 = 0, |
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| 251 | + .chan_36_64 = 0, |
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| 252 | + .chan_100_120 = 0, |
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| 253 | + .chan_122_140 = 0, |
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| 254 | + .chan_142_165 = 0, |
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| 255 | + }, |
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| 256 | +}; |
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| 257 | + |
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| 258 | +void get_userconfig_txpwr_idx(txpwr_idx_conf_t *txpwr_idx) |
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| 250 | 259 | { |
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| 251 | | - const struct firmware *fw; |
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| 252 | | - struct device *dev = rwnx_platform_get_dev(rwnx_plat); |
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| 253 | | - u8 const *src, *end; |
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| 254 | | - u32 *dst; |
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| 255 | | - u16 haddr, segaddr, addr; |
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| 256 | | - u32 hwaddr; |
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| 257 | | - u8 load_fw, byte_count, checksum, csum, rec_type; |
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| 258 | | - int err, rec_idx; |
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| 259 | | - char hex_buff[9]; |
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| 260 | | - |
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| 261 | | - err = request_firmware(&fw, filename, dev); |
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| 262 | | - if (err) { |
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| 263 | | - return err; |
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| 264 | | - } |
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| 265 | | - |
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| 266 | | - /* Copy the file on the Embedded side */ |
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| 267 | | - dev_dbg(dev, "\n### Now copy %s firmware, @ = %p\n", filename, fw_addr); |
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| 268 | | - |
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| 269 | | - src = fw->data; |
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| 270 | | - end = src + (unsigned int)fw->size; |
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| 271 | | - haddr = 0; |
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| 272 | | - segaddr = 0; |
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| 273 | | - load_fw = 1; |
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| 274 | | - err = -EINVAL; |
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| 275 | | - rec_idx = 0; |
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| 276 | | - hwaddr = 0; |
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| 277 | | - |
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| 278 | | -#define IHEX_READ8(_val, _cs) { \ |
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| 279 | | - hex_buff[2] = 0; \ |
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| 280 | | - strncpy(hex_buff, src, 2); \ |
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| 281 | | - if (kstrtou8(hex_buff, 16, &_val)) \ |
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| 282 | | - goto end; \ |
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| 283 | | - src += 2; \ |
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| 284 | | - if (_cs) \ |
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| 285 | | - csum += _val; \ |
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| 286 | | - } |
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| 287 | | - |
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| 288 | | -#define IHEX_READ16(_val) { \ |
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| 289 | | - hex_buff[4] = 0; \ |
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| 290 | | - strncpy(hex_buff, src, 4); \ |
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| 291 | | - if (kstrtou16(hex_buff, 16, &_val)) \ |
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| 292 | | - goto end; \ |
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| 293 | | - src += 4; \ |
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| 294 | | - csum += (_val & 0xff) + (_val >> 8); \ |
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| 295 | | - } |
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| 296 | | - |
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| 297 | | -#define IHEX_READ32(_val) { \ |
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| 298 | | - hex_buff[8] = 0; \ |
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| 299 | | - strncpy(hex_buff, src, 8); \ |
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| 300 | | - if (kstrtouint(hex_buff, 16, &_val)) \ |
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| 301 | | - goto end; \ |
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| 302 | | - src += 8; \ |
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| 303 | | - csum += (_val & 0xff) + ((_val >> 8) & 0xff) + \ |
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| 304 | | - ((_val >> 16) & 0xff) + (_val >> 24); \ |
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| 305 | | - } |
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| 306 | | - |
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| 307 | | -#define IHEX_READ32_PAD(_val, _nb) { \ |
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| 308 | | - memset(hex_buff, '0', 8); \ |
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| 309 | | - hex_buff[8] = 0; \ |
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| 310 | | - strncpy(hex_buff, src, (2 * _nb)); \ |
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| 311 | | - if (kstrtouint(hex_buff, 16, &_val)) \ |
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| 312 | | - goto end; \ |
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| 313 | | - src += (2 * _nb); \ |
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| 314 | | - csum += (_val & 0xff) + ((_val >> 8) & 0xff) + \ |
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| 315 | | - ((_val >> 16) & 0xff) + (_val >> 24); \ |
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| 260 | + memcpy(txpwr_idx, &(nvram_info.txpwr_idx), sizeof(txpwr_idx_conf_t)); |
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| 316 | 261 | } |
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| 317 | 262 | |
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| 318 | | - /* loop until end of file is read*/ |
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| 319 | | - while (load_fw) { |
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| 320 | | - rec_idx++; |
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| 321 | | - csum = 0; |
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| 263 | +void get_userconfig_txpwr_ofst(txpwr_ofst_conf_t *txpwr_ofst) |
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| 264 | +{ |
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| 265 | + memcpy(txpwr_ofst, &(nvram_info.txpwr_ofst), sizeof(txpwr_ofst_conf_t)); |
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| 266 | +} |
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| 322 | 267 | |
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| 323 | | - /* Find next colon start code */ |
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| 324 | | - while (*src != ':') { |
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| 325 | | - src++; |
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| 326 | | - if ((src + 3) >= end) /* 3 = : + rec_len */ |
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| 327 | | - goto end; |
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| 328 | | - } |
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| 329 | | - src++; |
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| 268 | +#define MATCH_NODE(type, node, cfg_key) {cfg_key, offsetof(type, node)} |
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| 330 | 269 | |
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| 331 | | - /* Read record len */ |
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| 332 | | - IHEX_READ8(byte_count, 1); |
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| 333 | | - if ((src + (byte_count * 2) + 8) >= end) /* 8 = rec_addr + rec_type + chksum */ |
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| 334 | | - goto end; |
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| 270 | +struct parse_match_t { |
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| 271 | + char keyname[64]; |
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| 272 | + int offset; |
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| 273 | +}; |
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| 335 | 274 | |
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| 336 | | - /* Read record addr */ |
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| 337 | | - IHEX_READ16(addr); |
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| 275 | +static const char *parse_key_prefix[] = { |
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| 276 | + [0x01] = "module0_", |
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| 277 | + [0x21] = "module1_", |
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| 278 | +}; |
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| 338 | 279 | |
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| 339 | | - /* Read record type */ |
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| 340 | | - IHEX_READ8(rec_type, 1); |
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| 280 | +static const struct parse_match_t parse_match_tab[] = { |
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| 281 | + MATCH_NODE(nvram_info_t, txpwr_idx.enable, "enable"), |
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| 282 | + MATCH_NODE(nvram_info_t, txpwr_idx.dsss, "dsss"), |
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| 283 | + MATCH_NODE(nvram_info_t, txpwr_idx.ofdmlowrate_2g4, "ofdmlowrate_2g4"), |
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| 284 | + MATCH_NODE(nvram_info_t, txpwr_idx.ofdm64qam_2g4, "ofdm64qam_2g4"), |
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| 285 | + MATCH_NODE(nvram_info_t, txpwr_idx.ofdm256qam_2g4, "ofdm256qam_2g4"), |
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| 286 | + MATCH_NODE(nvram_info_t, txpwr_idx.ofdm1024qam_2g4, "ofdm1024qam_2g4"), |
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| 287 | + MATCH_NODE(nvram_info_t, txpwr_idx.ofdmlowrate_5g, "ofdmlowrate_5g"), |
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| 288 | + MATCH_NODE(nvram_info_t, txpwr_idx.ofdm64qam_5g, "ofdm64qam_5g"), |
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| 289 | + MATCH_NODE(nvram_info_t, txpwr_idx.ofdm256qam_5g, "ofdm256qam_5g"), |
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| 290 | + MATCH_NODE(nvram_info_t, txpwr_idx.ofdm1024qam_5g, "ofdm1024qam_5g"), |
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| 341 | 291 | |
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| 342 | | - switch (rec_type) { |
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| 343 | | - case IHEX_REC_DATA: |
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| 344 | | - { |
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| 345 | | - /* Update destination address */ |
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| 346 | | - dst = (u32 *) (fw_addr + hwaddr + addr); |
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| 292 | + MATCH_NODE(nvram_info_t, txpwr_ofst.enable, "ofst_enable"), |
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| 293 | + MATCH_NODE(nvram_info_t, txpwr_ofst.chan_1_4, "ofst_chan_1_4"), |
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| 294 | + MATCH_NODE(nvram_info_t, txpwr_ofst.chan_5_9, "ofst_chan_5_9"), |
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| 295 | + MATCH_NODE(nvram_info_t, txpwr_ofst.chan_10_13, "ofst_chan_10_13"), |
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| 296 | + MATCH_NODE(nvram_info_t, txpwr_ofst.chan_36_64, "ofst_chan_36_64"), |
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| 297 | + MATCH_NODE(nvram_info_t, txpwr_ofst.chan_100_120, "ofst_chan_100_120"), |
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| 298 | + MATCH_NODE(nvram_info_t, txpwr_ofst.chan_122_140, "ofst_chan_122_140"), |
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| 299 | + MATCH_NODE(nvram_info_t, txpwr_ofst.chan_142_165, "ofst_chan_142_165"), |
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| 300 | +}; |
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| 347 | 301 | |
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| 348 | | - while (byte_count) { |
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| 349 | | - u32 val; |
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| 350 | | - if (byte_count >= 4) { |
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| 351 | | - IHEX_READ32(val); |
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| 352 | | - byte_count -= 4; |
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| 353 | | - } else { |
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| 354 | | - IHEX_READ32_PAD(val, byte_count); |
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| 355 | | - byte_count = 0; |
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| 356 | | - } |
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| 357 | | - *dst++ = __swab32(val); |
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| 302 | +static int parse_key_val(const char *str, const char *key, char *val) |
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| 303 | +{ |
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| 304 | + const char *p = NULL; |
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| 305 | + const char *dst = NULL; |
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| 306 | + int keysize = 0; |
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| 307 | + int bufsize = 0; |
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| 308 | + |
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| 309 | + if (str == NULL || key == NULL || val == NULL) |
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| 310 | + return -1; |
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| 311 | + |
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| 312 | + keysize = strlen(key); |
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| 313 | + bufsize = strlen(str); |
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| 314 | + if (bufsize <= keysize) |
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| 315 | + return -1; |
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| 316 | + |
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| 317 | + p = str; |
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| 318 | + while (*p != 0 && *p == ' ') |
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| 319 | + p++; |
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| 320 | + |
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| 321 | + if (*p == '#') |
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| 322 | + return -1; |
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| 323 | + |
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| 324 | + if (str + bufsize - p <= keysize) |
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| 325 | + return -1; |
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| 326 | + |
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| 327 | + if (strncmp(p, key, keysize) != 0) |
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| 328 | + return -1; |
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| 329 | + |
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| 330 | + p += keysize; |
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| 331 | + |
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| 332 | + while (*p != 0 && *p == ' ') |
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| 333 | + p++; |
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| 334 | + |
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| 335 | + if (*p != '=') |
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| 336 | + return -1; |
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| 337 | + |
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| 338 | + p++; |
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| 339 | + while (*p != 0 && *p == ' ') |
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| 340 | + p++; |
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| 341 | + |
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| 342 | + if (*p == '"') |
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| 343 | + p++; |
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| 344 | + |
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| 345 | + dst = p; |
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| 346 | + while (*p != 0) |
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| 347 | + p++; |
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| 348 | + |
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| 349 | + p--; |
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| 350 | + while (*p == ' ') |
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| 351 | + p--; |
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| 352 | + |
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| 353 | + if (*p == '"') |
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| 354 | + p--; |
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| 355 | + |
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| 356 | + while (*p == '\r' || *p == '\n') |
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| 357 | + p--; |
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| 358 | + |
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| 359 | + p++; |
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| 360 | + strncpy(val, dst, p -dst); |
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| 361 | + val[p - dst] = 0; |
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| 362 | + return 0; |
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| 363 | +} |
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| 364 | + |
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| 365 | +void rwnx_plat_userconfig_parsing(struct rwnx_hw *rwnx_hw, char *buffer, int size) |
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| 366 | +{ |
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| 367 | + char conf[100], keyname[64]; |
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| 368 | + char *line; |
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| 369 | + char *data; |
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| 370 | + int i = 0, err, len = 0; |
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| 371 | + long val; |
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| 372 | + |
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| 373 | + if (size <= 0) { |
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| 374 | + pr_err("Config buffer size %d error\n", size); |
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| 375 | + return; |
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| 376 | + } |
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| 377 | + |
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| 378 | + if (rwnx_hw->vendor_info > (sizeof(parse_key_prefix) / sizeof(parse_key_prefix[0]) - 1)) { |
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| 379 | + pr_err("Unsuppor vendor info config\n"); |
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| 380 | + return; |
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| 381 | + } |
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| 382 | + |
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| 383 | + data = vmalloc(size + 1); |
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| 384 | + if (!data) { |
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| 385 | + pr_err("vmalloc fail\n"); |
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| 386 | + return; |
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| 387 | + } |
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| 388 | + |
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| 389 | + memcpy(data, buffer, size); |
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| 390 | + buffer = data; |
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| 391 | + |
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| 392 | + while (1) { |
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| 393 | + line = buffer; |
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| 394 | + if (*line == 0) |
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| 395 | + break; |
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| 396 | + |
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| 397 | + while (*buffer != '\r' && *buffer != '\n' && *buffer != 0 && len++ < size) |
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| 398 | + buffer++; |
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| 399 | + |
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| 400 | + while ((*buffer == '\r' || *buffer == '\n') && len++ < size) |
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| 401 | + *buffer++ = 0; |
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| 402 | + |
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| 403 | + if (len >= size) |
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| 404 | + *buffer = 0; |
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| 405 | + |
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| 406 | + // store value to data struct |
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| 407 | + for (i = 0; i < sizeof(parse_match_tab) / sizeof(parse_match_tab[0]); i++) { |
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| 408 | + sprintf(&keyname[0], "%s%s", parse_key_prefix[rwnx_hw->vendor_info], parse_match_tab[i].keyname); |
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| 409 | + if (parse_key_val(line, keyname, conf) == 0) { |
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| 410 | + err = kstrtol(conf, 0, &val); |
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| 411 | + *(unsigned char *)((unsigned long)&nvram_info + parse_match_tab[i].offset) = val; |
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| 412 | + printk("%s, %s = %ld\n", __func__, parse_match_tab[i].keyname, val); |
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| 413 | + break; |
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| 358 | 414 | } |
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| 359 | | - break; |
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| 360 | 415 | } |
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| 361 | | - case IHEX_REC_EOF: |
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| 362 | | - { |
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| 363 | | - load_fw = 0; |
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| 364 | | - err = 0; |
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| 365 | | - break; |
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| 366 | | - } |
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| 367 | | - case IHEX_REC_EXT_SEG_ADD: /* Extended Segment Address */ |
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| 368 | | - { |
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| 369 | | - IHEX_READ16(segaddr); |
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| 370 | | - hwaddr = (haddr << 16) + (segaddr << 4); |
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| 371 | | - break; |
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| 372 | | - } |
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| 373 | | - case IHEX_REC_EXT_LIN_ADD: /* Extended Linear Address */ |
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| 374 | | - { |
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| 375 | | - IHEX_READ16(haddr); |
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| 376 | | - hwaddr = (haddr << 16) + (segaddr << 4); |
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| 377 | | - break; |
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| 378 | | - } |
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| 379 | | - case IHEX_REC_START_LIN_ADD: /* Start Linear Address */ |
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| 380 | | - { |
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| 381 | | - u32 val; |
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| 382 | | - IHEX_READ32(val); /* need to read for checksum */ |
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| 383 | | - break; |
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| 384 | | - } |
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| 385 | | - case IHEX_REC_START_SEG_ADD: |
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| 386 | | - default: |
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| 387 | | - { |
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| 388 | | - dev_err(dev, "ihex: record type %d not supported\n", rec_type); |
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| 389 | | - load_fw = 0; |
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| 390 | | - } |
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| 391 | | - } |
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| 416 | + } |
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| 417 | + vfree(data); |
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| 418 | +} |
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| 392 | 419 | |
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| 393 | | - /* Read and compare checksum */ |
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| 394 | | - IHEX_READ8(checksum, 0); |
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| 395 | | - if (checksum != (u8)(~csum + 1)) |
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| 396 | | - goto end; |
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| 420 | +#define FW_USERCONFIG_NAME "aic_userconfig.txt" |
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| 421 | + |
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| 422 | +int rwnx_plat_userconfig_upload_android(struct rwnx_hw *rwnx_hw, char *filename) |
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| 423 | +{ |
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| 424 | + int size; |
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| 425 | + char *dst = NULL; |
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| 426 | + |
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| 427 | + const struct firmware *fw = NULL; |
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| 428 | + int ret = request_firmware(&fw, filename, NULL); |
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| 429 | + |
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| 430 | + printk("userconfig file path:%s \r\n", filename); |
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| 431 | + |
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| 432 | + if (ret < 0) { |
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| 433 | + printk("Load %s fail\n", filename); |
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| 434 | + return ret; |
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| 397 | 435 | } |
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| 398 | 436 | |
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| 399 | | -#undef IHEX_READ8 |
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| 400 | | -#undef IHEX_READ16 |
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| 401 | | -#undef IHEX_READ32 |
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| 402 | | -#undef IHEX_READ32_PAD |
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| 437 | + size = fw->size; |
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| 438 | + dst = (char *)fw->data; |
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| 403 | 439 | |
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| 404 | | -end: |
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| 405 | | - release_firmware(fw); |
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| 406 | | - |
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| 407 | | - if (err) |
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| 408 | | - dev_err(dev, "%s: Invalid ihex record around line %d\n", filename, rec_idx); |
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| 409 | | - |
|---|
| 410 | | - return err; |
|---|
| 411 | | -} |
|---|
| 412 | | -#endif /* CONFIG_RWNX_TL4 */ |
|---|
| 413 | | - |
|---|
| 414 | | -#ifndef CONFIG_RWNX_SDM |
|---|
| 415 | | -/** |
|---|
| 416 | | - * rwnx_plat_get_rf() - Retrun the RF used in the platform |
|---|
| 417 | | - * |
|---|
| 418 | | - * @rwnx_plat: pointer to platform structure |
|---|
| 419 | | - */ |
|---|
| 420 | | -static u32 rwnx_plat_get_rf(struct rwnx_plat *rwnx_plat) |
|---|
| 421 | | -{ |
|---|
| 422 | | - u32 ver; |
|---|
| 423 | | - ver = RWNX_REG_READ(rwnx_plat, RWNX_ADDR_SYSTEM, MDM_HDMCONFIG_ADDR); |
|---|
| 424 | | - |
|---|
| 425 | | - ver = __MDM_PHYCFG_FROM_VERS(ver); |
|---|
| 426 | | - WARN(((ver != MDM_PHY_CONFIG_TRIDENT) && |
|---|
| 427 | | - (ver != MDM_PHY_CONFIG_ELMA) && |
|---|
| 428 | | - (ver != MDM_PHY_CONFIG_KARST)), |
|---|
| 429 | | - "bad phy version 0x%08x\n", ver); |
|---|
| 430 | | - |
|---|
| 431 | | - return ver; |
|---|
| 432 | | -} |
|---|
| 433 | | - |
|---|
| 434 | | -/** |
|---|
| 435 | | - * rwnx_plat_stop_agcfsm() - Stop a AGC state machine |
|---|
| 436 | | - * |
|---|
| 437 | | - * @rwnx_plat: pointer to platform structure |
|---|
| 438 | | - * @agg_reg: Address of the agccntl register (within RWNX_ADDR_SYSTEM) |
|---|
| 439 | | - * @agcctl: Updated with value of the agccntl rgister before stop |
|---|
| 440 | | - * @memclk: Updated with value of the clock register before stop |
|---|
| 441 | | - * @agc_ver: Version of the AGC load procedure |
|---|
| 442 | | - * @clkctrladdr: Indicates which AGC clock register should be accessed |
|---|
| 443 | | - */ |
|---|
| 444 | | -static void rwnx_plat_stop_agcfsm(struct rwnx_plat *rwnx_plat, int agc_reg, |
|---|
| 445 | | - u32 *agcctl, u32 *memclk, u8 agc_ver, |
|---|
| 446 | | - u32 clkctrladdr) |
|---|
| 447 | | -{ |
|---|
| 448 | | - /* First read agcctnl and clock registers */ |
|---|
| 449 | | - *memclk = RWNX_REG_READ(rwnx_plat, RWNX_ADDR_SYSTEM, clkctrladdr); |
|---|
| 450 | | - |
|---|
| 451 | | - /* Stop state machine : xxAGCCNTL0[AGCFSMRESET]=1 */ |
|---|
| 452 | | - *agcctl = RWNX_REG_READ(rwnx_plat, RWNX_ADDR_SYSTEM, agc_reg); |
|---|
| 453 | | - RWNX_REG_WRITE((*agcctl) | BIT(12), rwnx_plat, RWNX_ADDR_SYSTEM, agc_reg); |
|---|
| 454 | | - |
|---|
| 455 | | - /* Force clock */ |
|---|
| 456 | | - if (agc_ver > 0) { |
|---|
| 457 | | - /* CLKGATEFCTRL0[AGCCLKFORCE]=1 */ |
|---|
| 458 | | - RWNX_REG_WRITE((*memclk) | BIT(29), rwnx_plat, RWNX_ADDR_SYSTEM, |
|---|
| 459 | | - clkctrladdr); |
|---|
| 460 | | - } else { |
|---|
| 461 | | - /* MEMCLKCTRL0[AGCMEMCLKCTRL]=0 */ |
|---|
| 462 | | - RWNX_REG_WRITE((*memclk) & ~BIT(3), rwnx_plat, RWNX_ADDR_SYSTEM, |
|---|
| 463 | | - clkctrladdr); |
|---|
| 464 | | - } |
|---|
| 465 | | -} |
|---|
| 466 | | - |
|---|
| 467 | | - |
|---|
| 468 | | -/** |
|---|
| 469 | | - * rwnx_plat_start_agcfsm() - Restart a AGC state machine |
|---|
| 470 | | - * |
|---|
| 471 | | - * @rwnx_plat: pointer to platform structure |
|---|
| 472 | | - * @agg_reg: Address of the agccntl register (within RWNX_ADDR_SYSTEM) |
|---|
| 473 | | - * @agcctl: value of the agccntl register to restore |
|---|
| 474 | | - * @memclk: value of the clock register to restore |
|---|
| 475 | | - * @agc_ver: Version of the AGC load procedure |
|---|
| 476 | | - * @clkctrladdr: Indicates which AGC clock register should be accessed |
|---|
| 477 | | - */ |
|---|
| 478 | | -static void rwnx_plat_start_agcfsm(struct rwnx_plat *rwnx_plat, int agc_reg, |
|---|
| 479 | | - u32 agcctl, u32 memclk, u8 agc_ver, |
|---|
| 480 | | - u32 clkctrladdr) |
|---|
| 481 | | -{ |
|---|
| 482 | | - |
|---|
| 483 | | - /* Release clock */ |
|---|
| 484 | | - if (agc_ver > 0) |
|---|
| 485 | | - /* CLKGATEFCTRL0[AGCCLKFORCE]=0 */ |
|---|
| 486 | | - RWNX_REG_WRITE(memclk & ~BIT(29), rwnx_plat, RWNX_ADDR_SYSTEM, |
|---|
| 487 | | - clkctrladdr); |
|---|
| 488 | | - else |
|---|
| 489 | | - /* MEMCLKCTRL0[AGCMEMCLKCTRL]=1 */ |
|---|
| 490 | | - RWNX_REG_WRITE(memclk | BIT(3), rwnx_plat, RWNX_ADDR_SYSTEM, |
|---|
| 491 | | - clkctrladdr); |
|---|
| 492 | | - |
|---|
| 493 | | - /* Restart state machine: xxAGCCNTL0[AGCFSMRESET]=0 */ |
|---|
| 494 | | - RWNX_REG_WRITE(agcctl & ~BIT(12), rwnx_plat, RWNX_ADDR_SYSTEM, agc_reg); |
|---|
| 495 | | -} |
|---|
| 496 | | -#endif |
|---|
| 497 | | - |
|---|
| 498 | | -/** |
|---|
| 499 | | - * rwnx_plat_fcu_load() - Load FCU (Fith Chain Unit) ucode |
|---|
| 500 | | - * |
|---|
| 501 | | - * @rwnx_hw: main driver data |
|---|
| 502 | | - * |
|---|
| 503 | | - * c.f Modem UM (AGC/CCA initialization) |
|---|
| 504 | | - */ |
|---|
| 505 | | -static int rwnx_plat_fcu_load(struct rwnx_hw *rwnx_hw) |
|---|
| 506 | | -{ |
|---|
| 507 | | - int ret = 0; |
|---|
| 508 | | -#ifndef CONFIG_RWNX_SDM |
|---|
| 509 | | - struct rwnx_plat *rwnx_plat = rwnx_hw->plat; |
|---|
| 510 | | - u32 agcctl, memclk; |
|---|
| 511 | | - |
|---|
| 512 | | -#ifndef CONFIG_RWNX_FHOST |
|---|
| 513 | | - /* By default, we consider that there is only one RF in the system */ |
|---|
| 514 | | - rwnx_hw->phy.cnt = 1; |
|---|
| 515 | | -#endif // CONFIG_RWNX_FHOST |
|---|
| 516 | | - |
|---|
| 517 | | - if (rwnx_plat_get_rf(rwnx_plat) != MDM_PHY_CONFIG_ELMA) |
|---|
| 518 | | - /* No FCU for PHYs other than Elma */ |
|---|
| 519 | | - return 0; |
|---|
| 520 | | - |
|---|
| 521 | | - agcctl = RWNX_REG_READ(rwnx_plat, RWNX_ADDR_SYSTEM, RIU_RWNXAGCCNTL_ADDR); |
|---|
| 522 | | - if (!__RIU_FCU_PRESENT(agcctl)) |
|---|
| 523 | | - /* No FCU present in this version */ |
|---|
| 524 | | - return 0; |
|---|
| 525 | | - |
|---|
| 526 | | -#ifndef CONFIG_RWNX_FHOST |
|---|
| 527 | | - /* FCU is present */ |
|---|
| 528 | | - if (rwnx_hw->band_5g_support) { |
|---|
| 529 | | - rwnx_hw->phy.cnt = 2; |
|---|
| 530 | | - rwnx_hw->phy.sec_chan.band = NL80211_BAND_5GHZ; |
|---|
| 531 | | - rwnx_hw->phy.sec_chan.type = PHY_CHNL_BW_20; |
|---|
| 532 | | - rwnx_hw->phy.sec_chan.prim20_freq = 5500; |
|---|
| 533 | | - rwnx_hw->phy.sec_chan.center_freq1 = 5500; |
|---|
| 534 | | - rwnx_hw->phy.sec_chan.center_freq2 = 0; |
|---|
| 535 | | - } |
|---|
| 536 | | -#endif // CONFIG_RWNX_FHOST |
|---|
| 537 | | - |
|---|
| 538 | | - rwnx_plat_stop_agcfsm(rwnx_plat, FCU_RWNXFCAGCCNTL_ADDR, &agcctl, &memclk, 0, |
|---|
| 539 | | - MDM_MEMCLKCTRL0_ADDR); |
|---|
| 540 | | - |
|---|
| 541 | | - ret = rwnx_plat_bin_fw_upload(rwnx_plat, |
|---|
| 542 | | - RWNX_ADDR(rwnx_plat, RWNX_ADDR_SYSTEM, PHY_FCU_UCODE_ADDR), |
|---|
| 543 | | - RWNX_FCU_FW_NAME); |
|---|
| 544 | | - |
|---|
| 545 | | - rwnx_plat_start_agcfsm(rwnx_plat, FCU_RWNXFCAGCCNTL_ADDR, agcctl, memclk, 0, |
|---|
| 546 | | - MDM_MEMCLKCTRL0_ADDR); |
|---|
| 547 | | -#endif |
|---|
| 548 | | - |
|---|
| 549 | | - return ret; |
|---|
| 550 | | -} |
|---|
| 551 | | - |
|---|
| 552 | | -/** |
|---|
| 553 | | - * rwnx_is_new_agc_load() - Return is new agc clock register should be used |
|---|
| 554 | | - * |
|---|
| 555 | | - * @rwnx_plat: platform data |
|---|
| 556 | | - * @rf: rf in used |
|---|
| 557 | | - * |
|---|
| 558 | | - * c.f Modem UM (AGC/CCA initialization) |
|---|
| 559 | | - */ |
|---|
| 560 | | -#ifndef CONFIG_RWNX_SDM |
|---|
| 561 | | -static u8 rwnx_get_agc_load_version(struct rwnx_plat *rwnx_plat, u32 rf, u32 *clkctrladdr) |
|---|
| 562 | | -{ |
|---|
| 563 | | - u8 agc_load_ver = 0; |
|---|
| 564 | | - u32 agc_ver; |
|---|
| 565 | | - u32 regval; |
|---|
| 566 | | - |
|---|
| 567 | | - /* Trident and Elma PHY use old method */ |
|---|
| 568 | | - if (rf != MDM_PHY_CONFIG_KARST) { |
|---|
| 569 | | - *clkctrladdr = MDM_MEMCLKCTRL0_ADDR; |
|---|
| 570 | | - return 0; |
|---|
| 571 | | - } |
|---|
| 572 | | - |
|---|
| 573 | | - /* Get the FPGA signature */ |
|---|
| 574 | | - regval = RWNX_REG_READ(rwnx_plat, RWNX_ADDR_SYSTEM, SYSCTRL_SIGNATURE_ADDR); |
|---|
| 575 | | - |
|---|
| 576 | | - if (__FPGA_TYPE(regval) == 0xC0CA) |
|---|
| 577 | | - *clkctrladdr = CRM_CLKGATEFCTRL0_ADDR; |
|---|
| 578 | | - else |
|---|
| 579 | | - *clkctrladdr = MDM_CLKGATEFCTRL0_ADDR; |
|---|
| 580 | | - |
|---|
| 581 | | - /* Read RIU version register */ |
|---|
| 582 | | - agc_ver = RWNX_REG_READ(rwnx_plat, RWNX_ADDR_SYSTEM, RIU_RWNXVERSION_ADDR); |
|---|
| 583 | | - agc_load_ver = __RIU_AGCLOAD_FROM_VERS(agc_ver); |
|---|
| 584 | | - |
|---|
| 585 | | - return agc_load_ver; |
|---|
| 586 | | -} |
|---|
| 587 | | -#endif /* CONFIG_RWNX_SDM */ |
|---|
| 588 | | - |
|---|
| 589 | | -/** |
|---|
| 590 | | - * rwnx_plat_agc_load() - Load AGC ucode |
|---|
| 591 | | - * |
|---|
| 592 | | - * @rwnx_plat: platform data |
|---|
| 593 | | - * c.f Modem UM (AGC/CCA initialization) |
|---|
| 594 | | - */ |
|---|
| 595 | | -static int rwnx_plat_agc_load(struct rwnx_plat *rwnx_plat) |
|---|
| 596 | | -{ |
|---|
| 597 | | - int ret = 0; |
|---|
| 598 | | -#ifndef CONFIG_RWNX_SDM |
|---|
| 599 | | - u32 agc = 0, agcctl, memclk; |
|---|
| 600 | | - u32 clkctrladdr; |
|---|
| 601 | | - u32 rf = rwnx_plat_get_rf(rwnx_plat); |
|---|
| 602 | | - u8 agc_ver; |
|---|
| 603 | | - |
|---|
| 604 | | - switch (rf) { |
|---|
| 605 | | - case MDM_PHY_CONFIG_TRIDENT: |
|---|
| 606 | | - agc = AGC_RWNXAGCCNTL_ADDR; |
|---|
| 607 | | - break; |
|---|
| 608 | | - case MDM_PHY_CONFIG_ELMA: |
|---|
| 609 | | - case MDM_PHY_CONFIG_KARST: |
|---|
| 610 | | - agc = RIU_RWNXAGCCNTL_ADDR; |
|---|
| 611 | | - break; |
|---|
| 612 | | - default: |
|---|
| 440 | + if (size <= 0) { |
|---|
| 441 | + printk("wrong size of firmware file\n"); |
|---|
| 442 | + release_firmware(fw); |
|---|
| 613 | 443 | return -1; |
|---|
| 614 | 444 | } |
|---|
| 615 | 445 | |
|---|
| 616 | | - agc_ver = rwnx_get_agc_load_version(rwnx_plat, rf, &clkctrladdr); |
|---|
| 446 | + rwnx_plat_userconfig_parsing(rwnx_hw, (char *)dst, size); |
|---|
| 617 | 447 | |
|---|
| 618 | | - rwnx_plat_stop_agcfsm(rwnx_plat, agc, &agcctl, &memclk, agc_ver, clkctrladdr); |
|---|
| 619 | | - |
|---|
| 620 | | - ret = rwnx_plat_bin_fw_upload(rwnx_plat, |
|---|
| 621 | | - RWNX_ADDR(rwnx_plat, RWNX_ADDR_SYSTEM, PHY_AGC_UCODE_ADDR), |
|---|
| 622 | | - RWNX_AGC_FW_NAME); |
|---|
| 623 | | - |
|---|
| 624 | | - if (!ret && (agc_ver == 1)) { |
|---|
| 625 | | - /* Run BIST to ensure that the AGC RAM was correctly loaded */ |
|---|
| 626 | | - RWNX_REG_WRITE(BIT(28), rwnx_plat, RWNX_ADDR_SYSTEM, |
|---|
| 627 | | - RIU_RWNXDYNAMICCONFIG_ADDR); |
|---|
| 628 | | - while (RWNX_REG_READ(rwnx_plat, RWNX_ADDR_SYSTEM, RIU_RWNXDYNAMICCONFIG_ADDR) & BIT(28)) { |
|---|
| 629 | | - ; |
|---|
| 630 | | - } |
|---|
| 631 | | - |
|---|
| 632 | | - if (!(RWNX_REG_READ(rwnx_plat, RWNX_ADDR_SYSTEM, |
|---|
| 633 | | - RIU_AGCMEMBISTSTAT_ADDR) & BIT(0))) { |
|---|
| 634 | | - dev_err(rwnx_platform_get_dev(rwnx_plat), |
|---|
| 635 | | - "AGC RAM not loaded correctly 0x%08x\n", |
|---|
| 636 | | - RWNX_REG_READ(rwnx_plat, RWNX_ADDR_SYSTEM, |
|---|
| 637 | | - RIU_AGCMEMSIGNATURESTAT_ADDR)); |
|---|
| 638 | | - ret = -EIO; |
|---|
| 639 | | - } |
|---|
| 640 | | - } |
|---|
| 641 | | - |
|---|
| 642 | | - rwnx_plat_start_agcfsm(rwnx_plat, agc, agcctl, memclk, agc_ver, clkctrladdr); |
|---|
| 643 | | - |
|---|
| 644 | | -#endif |
|---|
| 645 | | - return ret; |
|---|
| 646 | | -} |
|---|
| 647 | | - |
|---|
| 648 | | -/** |
|---|
| 649 | | - * rwnx_ldpc_load() - Load LDPC RAM |
|---|
| 650 | | - * |
|---|
| 651 | | - * @rwnx_hw: Main driver data |
|---|
| 652 | | - * c.f Modem UM (LDPC initialization) |
|---|
| 653 | | - */ |
|---|
| 654 | | -static int rwnx_ldpc_load(struct rwnx_hw *rwnx_hw) |
|---|
| 655 | | -{ |
|---|
| 656 | | -#ifndef CONFIG_RWNX_SDM |
|---|
| 657 | | - struct rwnx_plat *rwnx_plat = rwnx_hw->plat; |
|---|
| 658 | | - u32 rf = rwnx_plat_get_rf(rwnx_plat); |
|---|
| 659 | | - u32 phy_feat = RWNX_REG_READ(rwnx_plat, RWNX_ADDR_SYSTEM, MDM_HDMCONFIG_ADDR); |
|---|
| 660 | | - |
|---|
| 661 | | - if ((rf != MDM_PHY_CONFIG_KARST) || |
|---|
| 662 | | - (phy_feat & (MDM_LDPCDEC_BIT | MDM_LDPCENC_BIT)) != |
|---|
| 663 | | - (MDM_LDPCDEC_BIT | MDM_LDPCENC_BIT)) { |
|---|
| 664 | | - goto disable_ldpc; |
|---|
| 665 | | - } |
|---|
| 666 | | - |
|---|
| 667 | | - if (rwnx_plat_bin_fw_upload(rwnx_plat, |
|---|
| 668 | | - RWNX_ADDR(rwnx_plat, RWNX_ADDR_SYSTEM, PHY_LDPC_RAM_ADDR), |
|---|
| 669 | | - RWNX_LDPC_RAM_NAME)) { |
|---|
| 670 | | - goto disable_ldpc; |
|---|
| 671 | | - } |
|---|
| 448 | + release_firmware(fw); |
|---|
| 672 | 449 | |
|---|
| 673 | 450 | return 0; |
|---|
| 674 | | - |
|---|
| 675 | | -disable_ldpc: |
|---|
| 676 | | - rwnx_hw->mod_params->ldpc_on = false; |
|---|
| 677 | | - |
|---|
| 678 | | -#endif /* CONFIG_RWNX_SDM */ |
|---|
| 679 | | - return 0; |
|---|
| 680 | 451 | } |
|---|
| 681 | 452 | |
|---|
| 682 | | -/** |
|---|
| 683 | | - * rwnx_plat_lmac_load() - Load FW code |
|---|
| 684 | | - * |
|---|
| 685 | | - * @rwnx_plat: platform data |
|---|
| 686 | | - */ |
|---|
| 687 | | -static int rwnx_plat_lmac_load(struct rwnx_plat *rwnx_plat) |
|---|
| 688 | | -{ |
|---|
| 689 | | - int ret; |
|---|
| 690 | | - |
|---|
| 691 | | - #ifdef CONFIG_RWNX_TL4 |
|---|
| 692 | | - ret = rwnx_plat_tl4_fw_upload(rwnx_plat, |
|---|
| 693 | | - RWNX_ADDR(rwnx_plat, RWNX_ADDR_CPU, RAM_LMAC_FW_ADDR), |
|---|
| 694 | | - RWNX_MAC_FW_NAME); |
|---|
| 695 | | - #else |
|---|
| 696 | | - ret = rwnx_plat_ihex_fw_upload(rwnx_plat, |
|---|
| 697 | | - RWNX_ADDR(rwnx_plat, RWNX_ADDR_CPU, RAM_LMAC_FW_ADDR), |
|---|
| 698 | | - RWNX_MAC_FW_NAME); |
|---|
| 699 | | - if (ret == -ENOENT) { |
|---|
| 700 | | - ret = rwnx_plat_bin_fw_upload(rwnx_plat, |
|---|
| 701 | | - RWNX_ADDR(rwnx_plat, RWNX_ADDR_CPU, RAM_LMAC_FW_ADDR), |
|---|
| 702 | | - RWNX_MAC_FW_NAME2); |
|---|
| 703 | | - } |
|---|
| 704 | | - #endif |
|---|
| 705 | | - |
|---|
| 706 | | - return ret; |
|---|
| 707 | | -} |
|---|
| 708 | | -#endif |
|---|
| 709 | | - |
|---|
| 710 | | -#ifndef CONFIG_ROM_PATCH_EN |
|---|
| 711 | 453 | /** |
|---|
| 712 | 454 | * rwnx_plat_fmac_load() - Load FW code |
|---|
| 713 | 455 | * |
|---|
| .. | .. |
|---|
| 718 | 460 | int ret = 0; |
|---|
| 719 | 461 | |
|---|
| 720 | 462 | RWNX_DBG(RWNX_FN_ENTRY_STR); |
|---|
| 721 | | - #if defined(CONFIG_NANOPI_M4) || defined(CONFIG_PLATFORM_ALLWINNER) |
|---|
| 722 | | - //ret = rwnx_plat_bin_fw_upload_android(rwnx_hw, RAM_FMAC_FW_ADDR, RWNX_MAC_FW_NAME2); |
|---|
| 723 | | - #else |
|---|
| 724 | | - ret = rwnx_plat_bin_fw_upload_2(rwnx_hw, |
|---|
| 725 | | - RAM_FMAC_FW_ADDR, |
|---|
| 726 | | - RWNX_MAC_FW_NAME2); |
|---|
| 727 | | - #endif |
|---|
| 463 | + ret = rwnx_plat_userconfig_upload_android(rwnx_hw, FW_USERCONFIG_NAME); |
|---|
| 728 | 464 | return ret; |
|---|
| 729 | 465 | } |
|---|
| 730 | 466 | #endif /* !CONFIG_ROM_PATCH_EN */ |
|---|
| 731 | | - |
|---|
| 732 | | -#if 0 |
|---|
| 733 | | -/** |
|---|
| 734 | | - * rwnx_plat_mpif_sel() - Select the MPIF according to the FPGA signature |
|---|
| 735 | | - * |
|---|
| 736 | | - * @rwnx_plat: platform data |
|---|
| 737 | | - */ |
|---|
| 738 | | -static void rwnx_plat_mpif_sel(struct rwnx_plat *rwnx_plat) |
|---|
| 739 | | -{ |
|---|
| 740 | | -#ifndef CONFIG_RWNX_SDM |
|---|
| 741 | | - u32 regval; |
|---|
| 742 | | - u32 type; |
|---|
| 743 | | - |
|---|
| 744 | | - /* Get the FPGA signature */ |
|---|
| 745 | | - regval = RWNX_REG_READ(rwnx_plat, RWNX_ADDR_SYSTEM, SYSCTRL_SIGNATURE_ADDR); |
|---|
| 746 | | - type = __FPGA_TYPE(regval); |
|---|
| 747 | | - |
|---|
| 748 | | - /* Check if we need to switch to the old MPIF or not */ |
|---|
| 749 | | - if ((type != 0xCAFE) && (type != 0XC0CA) && (regval & 0xF) < 0x3) { |
|---|
| 750 | | - /* A old FPGA A is used, so configure the FPGA B to use the old MPIF */ |
|---|
| 751 | | - RWNX_REG_WRITE(0x3, rwnx_plat, RWNX_ADDR_SYSTEM, FPGAB_MPIF_SEL_ADDR); |
|---|
| 752 | | - } |
|---|
| 753 | | -#endif |
|---|
| 754 | | -} |
|---|
| 755 | | -#endif |
|---|
| 756 | | - |
|---|
| 757 | 467 | |
|---|
| 758 | 468 | /** |
|---|
| 759 | 469 | * rwnx_platform_reset() - Reset the platform |
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| .. | .. |
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| 982 | 692 | */ |
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| 983 | 693 | int rwnx_platform_on(struct rwnx_hw *rwnx_hw, void *config) |
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| 984 | 694 | { |
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| 985 | | - #ifndef CONFIG_ROM_PATCH_EN |
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| 986 | | - #ifdef CONFIG_DOWNLOAD_FW |
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| 987 | 695 | int ret; |
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| 988 | | - #endif |
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| 989 | | - #endif |
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| 990 | 696 | struct rwnx_plat *rwnx_plat = rwnx_hw->plat; |
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| 697 | + (void)ret; |
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| 991 | 698 | |
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| 992 | 699 | RWNX_DBG(RWNX_FN_ENTRY_STR); |
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| 993 | 700 | |
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| 994 | 701 | if (rwnx_plat->enabled) |
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| 995 | 702 | return 0; |
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| 996 | 703 | |
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| 997 | | - #if 0 |
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| 998 | | - if (rwnx_platform_reset(rwnx_plat)) |
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| 999 | | - return -1; |
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| 1000 | | - |
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| 1001 | | - rwnx_plat_mpif_sel(rwnx_plat); |
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| 1002 | | - |
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| 1003 | | - ret = rwnx_plat_fcu_load(rwnx_hw); |
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| 1004 | | - if (ret) |
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| 1005 | | - return ret; |
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| 1006 | | - ret = rwnx_plat_agc_load(rwnx_plat); |
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| 1007 | | - if (ret) |
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| 1008 | | - return ret; |
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| 1009 | | - ret = rwnx_ldpc_load(rwnx_hw); |
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| 1010 | | - if (ret) |
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| 1011 | | - return ret; |
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| 1012 | | - ret = rwnx_plat_lmac_load(rwnx_plat); |
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| 1013 | | - if (ret) |
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| 1014 | | - return ret; |
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| 1015 | | - |
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| 1016 | | - shared_ram = RWNX_ADDR(rwnx_plat, RWNX_ADDR_SYSTEM, SHARED_RAM_START_ADDR); |
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| 1017 | | - ret = rwnx_ipc_init(rwnx_hw, shared_ram); |
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| 1018 | | - if (ret) |
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| 1019 | | - return ret; |
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| 1020 | | - |
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| 1021 | | - ret = rwnx_plat->enable(rwnx_hw); |
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| 1022 | | - if (ret) |
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| 1023 | | - return ret; |
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| 1024 | | - RWNX_REG_WRITE(BOOTROM_ENABLE, rwnx_plat, |
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| 1025 | | - RWNX_ADDR_SYSTEM, SYSCTRL_MISC_CNTL_ADDR); |
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| 1026 | | - |
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| 1027 | | - #if 0 |
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| 1028 | | - ret = rwnx_fw_trace_config_filters(rwnx_get_shared_trace_buf(rwnx_hw), |
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| 1029 | | - rwnx_ipc_fw_trace_desc_get(rwnx_hw), |
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| 1030 | | - rwnx_hw->mod_params->ftl); |
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| 1031 | | - if (ret) |
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| 1032 | | - #endif |
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| 1033 | | - |
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| 1034 | | - #ifndef CONFIG_RWNX_FHOST |
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| 1035 | | - { |
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| 1036 | | - ret = rwnx_check_fw_compatibility(rwnx_hw); |
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| 1037 | | - if (ret) { |
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| 1038 | | - rwnx_hw->plat->disable(rwnx_hw); |
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| 1039 | | - tasklet_kill(&rwnx_hw->task); |
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| 1040 | | - rwnx_ipc_deinit(rwnx_hw); |
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| 1041 | | - return ret; |
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| 1042 | | - } |
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| 1043 | | - } |
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| 1044 | | - #endif /* !CONFIG_RWNX_FHOST */ |
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| 1045 | | - |
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| 1046 | | - if (config) |
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| 1047 | | - rwnx_term_restore_config(rwnx_plat, config); |
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| 1048 | | - |
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| 1049 | | - rwnx_ipc_start(rwnx_hw); |
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| 1050 | | - #else |
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| 1051 | 704 | #ifndef CONFIG_ROM_PATCH_EN |
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| 1052 | 705 | #ifdef CONFIG_DOWNLOAD_FW |
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| 1053 | 706 | ret = rwnx_plat_fmac_load(rwnx_hw); |
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| 1054 | 707 | if (ret) |
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| 1055 | 708 | return ret; |
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| 1056 | 709 | #endif /* !CONFIG_ROM_PATCH_EN */ |
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| 1057 | | - #endif |
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| 1058 | 710 | #endif |
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| 1059 | 711 | |
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| 1060 | 712 | rwnx_plat->enabled = true; |
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| .. | .. |
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| 1075 | 727 | void rwnx_platform_off(struct rwnx_hw *rwnx_hw, void **config) |
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| 1076 | 728 | { |
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| 1077 | 729 | #if defined(AICWF_USB_SUPPORT) || defined(AICWF_SDIO_SUPPORT) |
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| 730 | + tasklet_kill(&rwnx_hw->task); |
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| 1078 | 731 | rwnx_hw->plat->enabled = false; |
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| 1079 | 732 | return ; |
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| 1080 | 733 | #endif |
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| .. | .. |
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| 1085 | 738 | return; |
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| 1086 | 739 | } |
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| 1087 | 740 | |
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| 1088 | | -#ifdef AICWF_PCIE_SUPPORT |
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| 1089 | | - rwnx_ipc_stop(rwnx_hw); |
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| 1090 | | -#endif |
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| 1091 | | - |
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| 1092 | 741 | if (config) |
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| 1093 | 742 | *config = rwnx_term_save_config(rwnx_hw->plat); |
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| 1094 | 743 | |
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| 1095 | 744 | rwnx_hw->plat->disable(rwnx_hw); |
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| 1096 | 745 | |
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| 1097 | 746 | tasklet_kill(&rwnx_hw->task); |
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| 1098 | | - |
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| 1099 | | -#ifdef AICWF_PCIE_SUPPORT |
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| 1100 | | - rwnx_ipc_deinit(rwnx_hw); |
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| 1101 | | -#endif |
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| 1102 | | - |
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| 1103 | | - |
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| 1104 | 747 | rwnx_platform_reset(rwnx_hw->plat); |
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| 1105 | 748 | |
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| 1106 | 749 | rwnx_hw->plat->enabled = false; |
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| .. | .. |
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| 1148 | 791 | #endif |
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| 1149 | 792 | } |
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| 1150 | 793 | |
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| 794 | +#ifdef AICWF_PCIE_SUPPORT |
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| 1151 | 795 | /** |
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| 1152 | 796 | * rwnx_platform_register_drv() - Register all possible platform drivers |
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| 1153 | 797 | */ |
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| .. | .. |
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| 1164 | 808 | { |
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| 1165 | 809 | return rwnx_pci_unregister_drv(); |
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| 1166 | 810 | } |
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| 811 | +#endif |
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| 1167 | 812 | |
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| 1168 | 813 | struct device *rwnx_platform_get_dev(struct rwnx_plat *rwnx_plat) |
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| 1169 | 814 | { |
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| .. | .. |
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| 1173 | 818 | #ifdef AICWF_USB_SUPPORT |
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| 1174 | 819 | return rwnx_plat->usbdev->dev; |
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| 1175 | 820 | #endif |
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| 821 | +#ifdef AICWF_PCIE_SUPPORT |
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| 1176 | 822 | return &(rwnx_plat->pci_dev->dev); |
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| 823 | +#endif |
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| 1177 | 824 | } |
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| 1178 | 825 | |
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| 1179 | 826 | |
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