feat(wfit/bt): update aic8800 wifi/bt drive and hal

tzh

2024-08-15 d4a1bd480003f3e1a0590bc46fbcb24f05652ca7

 longan/kernel/linux-4.9/drivers/net/wireless/aic8800/aic8800_bsp/aic_bsp_driver.h
old mode 100644new mode 100755
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@@ -190,6 +190,13 @@
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 	DBG_MEM_MASK_WRITE_REQ,
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 	/// Memory mask write confirm
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 	DBG_MEM_MASK_WRITE_CFM,
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+
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+	DBG_RFTEST_CMD_REQ,
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+	DBG_RFTEST_CMD_CFM,
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+	DBG_BINDING_REQ,
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+	DBG_BINDING_CFM,
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+	DBG_BINDING_IND,
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+
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 	/// Max number of Debug messages
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 	DBG_MAX,
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 };
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@@ -257,6 +264,14 @@
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 	u32 bootstatus;
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 };
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+struct dbg_binding_ind {
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+	u8 enc_data[16];
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+};
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+
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+struct dbg_binding_req {
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+	u8 driver_data[16];
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+};
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+
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 int rwnx_send_dbg_mem_read_req(struct aic_sdio_dev *sdiodev, u32 mem_addr,
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 							   struct dbg_mem_read_cfm *cfm);
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 int rwnx_send_dbg_mem_block_write_req(struct aic_sdio_dev *sdiodev, u32 mem_addr,
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@@ -264,23 +279,21 @@
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 int rwnx_send_dbg_mem_write_req(struct aic_sdio_dev *sdiodev, u32 mem_addr, u32 mem_data);
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 int rwnx_send_dbg_mem_mask_write_req(struct aic_sdio_dev *sdiodev, u32 mem_addr,
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 									 u32 mem_mask, u32 mem_data);
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-int rwnx_send_dbg_start_app_req(struct aic_sdio_dev *sdiodev, u32 boot_addr, u32 boot_type);
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+int rwnx_send_dbg_start_app_req(struct aic_sdio_dev *sdiodev, u32 boot_addr, u32 boot_type, struct dbg_start_app_cfm *start_app_cfm);
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+int rwnx_send_dbg_binding_req(struct aic_sdio_dev *sdiodev, u8 *dout, u8 *binding_status);
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 void rwnx_rx_handle_msg(struct aic_sdio_dev *sdiodev, struct ipc_e2a_msg *msg);
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 int aicbsp_platform_init(struct aic_sdio_dev *sdiodev);
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 void aicbsp_platform_deinit(struct aic_sdio_dev *sdiodev);
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-void aicbsp_driver_fw_init(struct aic_sdio_dev *sdiodev);
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+int aicbsp_driver_fw_init(struct aic_sdio_dev *sdiodev);
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+int aicbsp_resv_mem_init(void);
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+int aicbsp_resv_mem_deinit(void);
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292
 
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-#define AICBSP_FW_PATH              "/vendor/etc/firmware"
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-#define AICBSP_FW_PATH_MAX          200
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-
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-#define RAM_FW_ADDR                 0x00100000
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-#define RAM_FMAC_FW_ADDR            0x00110000
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+#define RAM_FMAC_FW_ADDR            0x00120000
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 #define FW_RAM_ADID_BASE_ADDR       0x00161928
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-#define FW_RAM_PATCH_BASE_ADDR      0x0016ad64
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-#define FW_PATCH_TEST_BASE_ADDR     0x00100000
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-#define FW_WIFI_RAM_ADDR            0x00110000
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+#define FW_RAM_ADID_BASE_ADDR_U03   0x00161928
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+#define FW_RAM_PATCH_BASE_ADDR      0x00100000
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 #define AICBT_PT_TAG                "AICBT_PT_TAG"
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..
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@@ -290,19 +303,70 @@
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 	AICBT_PT_BTMODE,
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 	AICBT_PT_PWRON,
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 	AICBT_PT_AF,
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+	AICBT_PT_VER,
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 };
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-enum aicbsp_mode_num {
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-	AICBSP_MODE_BT_ONLY_SW = 0x0,   // bt only mode with switch
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-	AICBSP_MODE_BT_WIFI_COMBO,      // wifi/bt combo mode
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-	AICBSP_MODE_BT_ONLY,            // bt only mode without switch
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-	AICBSP_MODE_BT_ONLY_TEST,       // bt only test mode
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-	AICBSP_MODE_COMBO_TEST,         // wifi/bt combo test mode
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+enum aicbt_btport_type {
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+	AICBT_BTPORT_NULL,
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+	AICBT_BTPORT_MB,
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+	AICBT_BTPORT_UART,
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 };
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-#define AICBSP_MODE_DEFAULT         AICBSP_MODE_BT_WIFI_COMBO
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+/*  btmode
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+ * used for force bt mode,if not AICBSP_MODE_NULL
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+ * efuse valid and vendor_info will be invalid, even has beed set valid
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+*/
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+enum aicbt_btmode_type {
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+	AICBT_BTMODE_BT_ONLY_SW = 0x0,    // bt only mode with switch
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+	AICBT_BTMODE_BT_WIFI_COMBO,       // wifi/bt combo mode
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+	AICBT_BTMODE_BT_ONLY,             // bt only mode without switch
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+	AICBT_BTMODE_BT_ONLY_TEST,        // bt only test mode
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+	AICBT_BTMODE_BT_WIFI_COMBO_TEST,  // wifi/bt combo test mode
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+	AICBT_MODE_NULL = 0xFF,           // invalid value
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+};
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-#define FEATURE_5G_SUPPORT          0x01
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+/*  uart_baud
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+ * used for config uart baud when btport set to uart,
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+ * otherwise meaningless
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+*/
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+enum aicbt_uart_baud_type {
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+	AICBT_UART_BAUD_115200     = 115200,
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+	AICBT_UART_BAUD_921600     = 921600,
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+	AICBT_UART_BAUD_1_5M       = 1500000,
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+	AICBT_UART_BAUD_3_25M      = 3250000,
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+};
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+
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+enum aicbt_uart_flowctrl_type {
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+	AICBT_UART_FLOWCTRL_DISABLE = 0x0,    // uart without flow ctrl
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+	AICBT_UART_FLOWCTRL_ENABLE,           // uart with flow ctrl
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+};
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+
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+enum aicbsp_cpmode_type {
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+	AICBSP_CPMODE_WORK,
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+	AICBSP_CPMODE_TEST,
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+	AICBSP_CPMODE_MAX,
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+};
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+
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+enum chip_rev {
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+	CHIP_REV_U02 = 3,
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+	CHIP_REV_U03 = 7,
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+	CHIP_REV_U04 = 7,
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+};
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+
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+///aic bt tx pwr lvl :lsb->msb: first byte, min pwr lvl; second byte, max pwr lvl;
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+///pwr lvl:20(min), 30 , 40 , 50 , 60(max)
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+#define AICBT_TXPWR_LVL             0x00006020
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+
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+#define AICBSP_HWINFO_DEFAULT       (-1)
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+#define AICBSP_CPMODE_DEFAULT       AICBSP_CPMODE_WORK
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+
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+#define AICBT_BTMODE_DEFAULT        AICBT_MODE_NULL
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+#define AICBT_BTPORT_DEFAULT        AICBT_BTPORT_UART
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+#define AICBT_UART_BAUD_DEFAULT     AICBT_UART_BAUD_1_5M
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+#define AICBT_UART_FC_DEFAULT       AICBT_UART_FLOWCTRL_ENABLE
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+#define AICBT_LPM_ENABLE_DEFAULT    1
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+#define AICBT_TXPWR_LVL_DEFAULT     AICBT_TXPWR_LVL
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+
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 #define FEATURE_SDIO_CLOCK          70000000 // 0: default, other: target clock rate
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 #define FEATURE_SDIO_PHASE          2        // 0: default, 2: 180°
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..
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@@ -314,17 +378,35 @@
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 	struct aicbt_patch_table *next;
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 };
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+struct aicbt_info_t {
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+	uint32_t btmode;
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+	uint32_t btport;
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+	uint32_t uart_baud;
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+	uint32_t uart_flowctrl;
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+	uint32_t lpm_enable;
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+	uint32_t txpwr_lvl;
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+};
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+
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 struct aicbsp_firmware {
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 	const char *desc;
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 	const char *bt_adid;
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 	const char *bt_patch;
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 	const char *bt_table;
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-	const char *bt_patch_test;
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 	const char *wl_fw;
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 };
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-extern uint32_t aicbsp_mode_index;
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+struct aicbsp_info_t {
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+	int hwinfo;
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+	int hwinfo_r;
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+	uint32_t cpmode;
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+	uint32_t chip_rev;
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+	bool fwlog_en;
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+};
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+
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+extern struct aicbsp_info_t aicbsp_info;
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 extern struct mutex aicbsp_power_lock;
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-extern const struct aicbsp_firmware aicbsp_firmware_list[];
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+extern const struct aicbsp_firmware *aicbsp_firmware_list;
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+extern const struct aicbsp_firmware fw_u02[];
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+extern const struct aicbsp_firmware fw_u03[];
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 #endif