固定GMAC1 网卡名为 eth3

hc

2024-11-15 a46a1ad097419aeea7350987dd95230f50d90392

 kernel/arch/x86/kernel/process_64.c
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@@ -272,9 +272,9 @@
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 	unsigned long flags;
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 	/* Interrupts need to be off for FSGSBASE */
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-	local_irq_save(flags);
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+	local_irq_save_full(flags);
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 	save_fsgs(current);
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-	local_irq_restore(flags);
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+	local_irq_restore_full(flags);
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 }
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 #if IS_ENABLED(CONFIG_KVM)
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 EXPORT_SYMBOL_GPL(current_save_fsgs);
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@@ -410,9 +410,9 @@
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 	if (boot_cpu_has(X86_FEATURE_FSGSBASE)) {
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 		unsigned long flags;
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-		local_irq_save(flags);
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+		local_irq_save_full(flags);
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 		gsbase = __rdgsbase_inactive();
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-		local_irq_restore(flags);
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+		local_irq_restore_full(flags);
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 	} else {
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 		rdmsrl(MSR_KERNEL_GS_BASE, gsbase);
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 	}
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@@ -425,9 +425,9 @@
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 	if (boot_cpu_has(X86_FEATURE_FSGSBASE)) {
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 		unsigned long flags;
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-		local_irq_save(flags);
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+		local_irq_save_full(flags);
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 		__wrgsbase_inactive(gsbase);
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-		local_irq_restore(flags);
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+		local_irq_restore_full(flags);
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 	} else {
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 		wrmsrl(MSR_KERNEL_GS_BASE, gsbase);
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 	}
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@@ -537,8 +537,17 @@
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 	struct thread_struct *next = &next_p->thread;
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 	int cpu = smp_processor_id();
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539
 
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+	/*
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+	 * Dovetail: Switching context on the out-of-band stage is
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+	 * legit, and we may have preempted an in-band (soft)irq
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+	 * handler earlier. Since oob handlers never switch stack,
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+	 * make sure to restrict the following test to in-band
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+	 * callers.
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+	 */
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 	WARN_ON_ONCE(IS_ENABLED(CONFIG_DEBUG_ENTRY) &&
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-		     this_cpu_read(irq_count) != -1);
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+		     running_inband() && this_cpu_read(irq_count) != -1);
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+
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+	WARN_ON_ONCE(dovetail_debug() && !hard_irqs_disabled());
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 	if (!test_thread_flag(TIF_NEED_FPU_LOAD))
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 		switch_fpu_prepare(prev_p, cpu);
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@@ -719,6 +728,7 @@
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728
 
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 long do_arch_prctl_64(struct task_struct *task, int option, unsigned long arg2)
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 {
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+	unsigned long flags;
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 	int ret = 0;
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733
 
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 	switch (option) {
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@@ -726,7 +736,7 @@
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 		if (unlikely(arg2 >= TASK_SIZE_MAX))
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 			return -EPERM;
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738
 
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-		preempt_disable();
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+		flags = hard_preempt_disable();
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 		/*
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 		 * ARCH_SET_GS has always overwritten the index
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 		 * and the base. Zero is the most sensible value
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@@ -747,7 +757,7 @@
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 			task->thread.gsindex = 0;
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 			x86_gsbase_write_task(task, arg2);
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 		}
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-		preempt_enable();
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+		hard_preempt_enable(flags);
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 		break;
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 	}
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 	case ARCH_SET_FS: {
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@@ -758,7 +768,7 @@
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 		if (unlikely(arg2 >= TASK_SIZE_MAX))
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 			return -EPERM;
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-		preempt_disable();
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+		flags = hard_preempt_disable();
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 		/*
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 		 * Set the selector to 0 for the same reason
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 		 * as %gs above.
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@@ -776,7 +786,7 @@
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 			task->thread.fsindex = 0;
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 			x86_fsbase_write_task(task, arg2);
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 		}
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-		preempt_enable();
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+		hard_preempt_enable(flags);
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 		break;
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 	}
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 	case ARCH_GET_FS: {