| .. | .. |
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| 450 | 450 | { |
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| 451 | 451 | unsigned long flags; |
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| 452 | 452 | |
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| 453 | | - local_irq_save(flags); |
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| 453 | + flags = hard_local_irq_save(); |
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| 454 | 454 | prepare_set(); |
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| 455 | 455 | |
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| 456 | 456 | pat_init(); |
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| 457 | 457 | |
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| 458 | 458 | post_set(); |
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| 459 | | - local_irq_restore(flags); |
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| 459 | + hard_local_irq_restore(flags); |
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| 460 | 460 | } |
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| 461 | 461 | |
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| 462 | 462 | /* Grab all of the MTRR state for this CPU into *state */ |
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| .. | .. |
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| 797 | 797 | unsigned long mask, count; |
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| 798 | 798 | unsigned long flags; |
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| 799 | 799 | |
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| 800 | | - local_irq_save(flags); |
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| 800 | + flags = hard_local_irq_save(); |
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| 801 | 801 | prepare_set(); |
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| 802 | 802 | |
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| 803 | 803 | /* Actually set the state */ |
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| .. | .. |
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| 807 | 807 | pat_init(); |
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| 808 | 808 | |
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| 809 | 809 | post_set(); |
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| 810 | | - local_irq_restore(flags); |
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| 810 | + hard_local_irq_restore(flags); |
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| 811 | 811 | |
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| 812 | 812 | /* Use the atomic bitops to update the global mask */ |
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| 813 | 813 | for (count = 0; count < sizeof(mask) * 8; ++count) { |
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| .. | .. |
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| 836 | 836 | |
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| 837 | 837 | vr = &mtrr_state.var_ranges[reg]; |
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| 838 | 838 | |
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| 839 | | - local_irq_save(flags); |
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| 839 | + flags = hard_local_irq_save(); |
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| 840 | 840 | prepare_set(); |
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| 841 | 841 | |
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| 842 | 842 | if (size == 0) { |
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| .. | .. |
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| 857 | 857 | } |
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| 858 | 858 | |
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| 859 | 859 | post_set(); |
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| 860 | | - local_irq_restore(flags); |
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| 860 | + hard_local_irq_restore(flags); |
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| 861 | 861 | } |
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| 862 | 862 | |
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| 863 | 863 | int generic_validate_add_page(unsigned long base, unsigned long size, |
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