| .. | .. |
|---|
| 62 | 62 | void imx_gpc_pre_suspend(bool arm_power_off) |
|---|
| 63 | 63 | { |
|---|
| 64 | 64 | void __iomem *reg_imr1 = gpc_base + GPC_IMR1; |
|---|
| 65 | + unsigned long flags; |
|---|
| 65 | 66 | int i; |
|---|
| 66 | 67 | |
|---|
| 67 | 68 | /* Tell GPC to power off ARM core when suspend */ |
|---|
| 68 | 69 | if (arm_power_off) |
|---|
| 69 | 70 | imx_gpc_set_arm_power_in_lpm(arm_power_off); |
|---|
| 70 | 71 | |
|---|
| 72 | + flags = hard_cond_local_irq_save(); |
|---|
| 73 | + |
|---|
| 71 | 74 | for (i = 0; i < IMR_NUM; i++) { |
|---|
| 72 | 75 | gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); |
|---|
| 73 | 76 | writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4); |
|---|
| 74 | 77 | } |
|---|
| 78 | + |
|---|
| 79 | + hard_cond_local_irq_restore(flags); |
|---|
| 75 | 80 | } |
|---|
| 76 | 81 | |
|---|
| 77 | 82 | void imx_gpc_post_resume(void) |
|---|
| 78 | 83 | { |
|---|
| 79 | 84 | void __iomem *reg_imr1 = gpc_base + GPC_IMR1; |
|---|
| 85 | + unsigned long flags; |
|---|
| 80 | 86 | int i; |
|---|
| 81 | 87 | |
|---|
| 82 | 88 | /* Keep ARM core powered on for other low-power modes */ |
|---|
| 83 | 89 | imx_gpc_set_arm_power_in_lpm(false); |
|---|
| 84 | 90 | |
|---|
| 91 | + flags = hard_cond_local_irq_save(); |
|---|
| 92 | + |
|---|
| 85 | 93 | for (i = 0; i < IMR_NUM; i++) |
|---|
| 86 | 94 | writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); |
|---|
| 95 | + |
|---|
| 96 | + hard_cond_local_irq_restore(flags); |
|---|
| 87 | 97 | } |
|---|
| 88 | 98 | |
|---|
| 89 | 99 | static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on) |
|---|
| .. | .. |
|---|
| 105 | 115 | void imx_gpc_mask_all(void) |
|---|
| 106 | 116 | { |
|---|
| 107 | 117 | void __iomem *reg_imr1 = gpc_base + GPC_IMR1; |
|---|
| 118 | + unsigned long flags; |
|---|
| 108 | 119 | int i; |
|---|
| 120 | + |
|---|
| 121 | + flags = hard_cond_local_irq_save(); |
|---|
| 109 | 122 | |
|---|
| 110 | 123 | for (i = 0; i < IMR_NUM; i++) { |
|---|
| 111 | 124 | gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); |
|---|
| 112 | 125 | writel_relaxed(~0, reg_imr1 + i * 4); |
|---|
| 113 | 126 | } |
|---|
| 127 | + |
|---|
| 128 | + hard_cond_local_irq_restore(flags); |
|---|
| 114 | 129 | } |
|---|
| 115 | 130 | |
|---|
| 116 | 131 | void imx_gpc_restore_all(void) |
|---|
| 117 | 132 | { |
|---|
| 118 | 133 | void __iomem *reg_imr1 = gpc_base + GPC_IMR1; |
|---|
| 134 | + unsigned long flags; |
|---|
| 119 | 135 | int i; |
|---|
| 136 | + |
|---|
| 137 | + flags = hard_cond_local_irq_save(); |
|---|
| 120 | 138 | |
|---|
| 121 | 139 | for (i = 0; i < IMR_NUM; i++) |
|---|
| 122 | 140 | writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4); |
|---|
| 141 | + |
|---|
| 142 | + hard_cond_local_irq_restore(flags); |
|---|
| 123 | 143 | } |
|---|
| 124 | 144 | |
|---|
| 125 | 145 | void imx_gpc_hwirq_unmask(unsigned int hwirq) |
|---|
| .. | .. |
|---|
| 167 | 187 | #ifdef CONFIG_SMP |
|---|
| 168 | 188 | .irq_set_affinity = irq_chip_set_affinity_parent, |
|---|
| 169 | 189 | #endif |
|---|
| 190 | + .flags = IRQCHIP_PIPELINE_SAFE, |
|---|
| 170 | 191 | }; |
|---|
| 171 | 192 | |
|---|
| 172 | 193 | static int imx_gpc_domain_translate(struct irq_domain *d, |
|---|