gpio config

hc

2024-11-01 830ce1f69238136c0197858242f16cf44e0d6cb9

 kernel/lib/atomic64.c
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@@ -25,15 +25,15 @@
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  * Ensure each lock is in a separate cacheline.
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  */
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 static union {
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-	raw_spinlock_t lock;
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+	hard_spinlock_t lock;
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 	char pad[L1_CACHE_BYTES];
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 } atomic64_lock[NR_LOCKS] __cacheline_aligned_in_smp = {
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 	[0 ... (NR_LOCKS - 1)] = {
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-		.lock =  __RAW_SPIN_LOCK_UNLOCKED(atomic64_lock.lock),
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+		.lock =  __HARD_SPIN_LOCK_INITIALIZER(atomic64_lock.lock),
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 	},
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 };
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-static inline raw_spinlock_t *lock_addr(const atomic64_t *v)
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+static inline hard_spinlock_t *lock_addr(const atomic64_t *v)
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 {
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 	unsigned long addr = (unsigned long) v;
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@@ -45,7 +45,7 @@
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 s64 atomic64_read(const atomic64_t *v)
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 {
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 	unsigned long flags;
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-	raw_spinlock_t *lock = lock_addr(v);
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+	hard_spinlock_t *lock = lock_addr(v);
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 	s64 val;
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 	raw_spin_lock_irqsave(lock, flags);
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@@ -58,7 +58,7 @@
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 void atomic64_set(atomic64_t *v, s64 i)
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 {
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 	unsigned long flags;
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-	raw_spinlock_t *lock = lock_addr(v);
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+	hard_spinlock_t *lock = lock_addr(v);
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 	raw_spin_lock_irqsave(lock, flags);
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 	v->counter = i;
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@@ -70,7 +70,7 @@
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 void atomic64_##op(s64 a, atomic64_t *v)				\
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 {									\
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 	unsigned long flags;						\
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-	raw_spinlock_t *lock = lock_addr(v);				\
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+	hard_spinlock_t *lock = lock_addr(v);				\
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 									\
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 	raw_spin_lock_irqsave(lock, flags);				\
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 	v->counter c_op a;						\
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@@ -82,7 +82,7 @@
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 s64 atomic64_##op##_return(s64 a, atomic64_t *v)			\
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 {									\
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 	unsigned long flags;						\
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-	raw_spinlock_t *lock = lock_addr(v);				\
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+	hard_spinlock_t *lock = lock_addr(v);				\
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 	s64 val;							\
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 									\
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 	raw_spin_lock_irqsave(lock, flags);				\
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@@ -96,7 +96,7 @@
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 s64 atomic64_fetch_##op(s64 a, atomic64_t *v)				\
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 {									\
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 	unsigned long flags;						\
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-	raw_spinlock_t *lock = lock_addr(v);				\
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+	hard_spinlock_t *lock = lock_addr(v);				\
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 	s64 val;							\
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 									\
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 	raw_spin_lock_irqsave(lock, flags);				\
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@@ -133,7 +133,7 @@
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 s64 atomic64_dec_if_positive(atomic64_t *v)
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 {
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 	unsigned long flags;
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-	raw_spinlock_t *lock = lock_addr(v);
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+	hard_spinlock_t *lock = lock_addr(v);
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 	s64 val;
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 	raw_spin_lock_irqsave(lock, flags);
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@@ -148,7 +148,7 @@
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 s64 atomic64_cmpxchg(atomic64_t *v, s64 o, s64 n)
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 {
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 	unsigned long flags;
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-	raw_spinlock_t *lock = lock_addr(v);
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+	hard_spinlock_t *lock = lock_addr(v);
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 	s64 val;
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 	raw_spin_lock_irqsave(lock, flags);
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@@ -163,7 +163,7 @@
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 s64 atomic64_xchg(atomic64_t *v, s64 new)
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 {
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 	unsigned long flags;
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-	raw_spinlock_t *lock = lock_addr(v);
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+	hard_spinlock_t *lock = lock_addr(v);
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 	s64 val;
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 	raw_spin_lock_irqsave(lock, flags);
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@@ -177,7 +177,7 @@
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 s64 atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
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 {
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 	unsigned long flags;
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-	raw_spinlock_t *lock = lock_addr(v);
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+	hard_spinlock_t *lock = lock_addr(v);
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 	s64 val;
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 	raw_spin_lock_irqsave(lock, flags);