gpio config

hc

2024-11-01 830ce1f69238136c0197858242f16cf44e0d6cb9

 kernel/drivers/pinctrl/samsung/pinctrl-exynos.c
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@@ -58,13 +58,13 @@
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 	unsigned int mask;
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 	unsigned long flags;
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-	spin_lock_irqsave(&bank->slock, flags);
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+	raw_spin_lock_irqsave(&bank->slock, flags);
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 	mask = readl(bank->eint_base + reg_mask);
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 	mask |= 1 << irqd->hwirq;
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 	writel(mask, bank->eint_base + reg_mask);
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-	spin_unlock_irqrestore(&bank->slock, flags);
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+	raw_spin_unlock_irqrestore(&bank->slock, flags);
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 }
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 static void exynos_irq_ack(struct irq_data *irqd)
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@@ -97,13 +97,13 @@
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 	if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
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 		exynos_irq_ack(irqd);
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-	spin_lock_irqsave(&bank->slock, flags);
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+	raw_spin_lock_irqsave(&bank->slock, flags);
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 	mask = readl(bank->eint_base + reg_mask);
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 	mask &= ~(1 << irqd->hwirq);
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 	writel(mask, bank->eint_base + reg_mask);
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-	spin_unlock_irqrestore(&bank->slock, flags);
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+	raw_spin_unlock_irqrestore(&bank->slock, flags);
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 }
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 static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
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@@ -169,14 +169,14 @@
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 	shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
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 	mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
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-	spin_lock_irqsave(&bank->slock, flags);
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+	raw_spin_lock_irqsave(&bank->slock, flags);
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 	con = readl(bank->pctl_base + reg_con);
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 	con &= ~(mask << shift);
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 	con |= EXYNOS_PIN_FUNC_EINT << shift;
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 	writel(con, bank->pctl_base + reg_con);
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-	spin_unlock_irqrestore(&bank->slock, flags);
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+	raw_spin_unlock_irqrestore(&bank->slock, flags);
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 	return 0;
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 }
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@@ -192,14 +192,14 @@
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 	shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
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 	mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
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-	spin_lock_irqsave(&bank->slock, flags);
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+	raw_spin_lock_irqsave(&bank->slock, flags);
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 	con = readl(bank->pctl_base + reg_con);
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 	con &= ~(mask << shift);
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 	con |= EXYNOS_PIN_FUNC_INPUT << shift;
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 	writel(con, bank->pctl_base + reg_con);
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-	spin_unlock_irqrestore(&bank->slock, flags);
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+	raw_spin_unlock_irqrestore(&bank->slock, flags);
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 	gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
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 }
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@@ -216,6 +216,7 @@
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 		.irq_set_type = exynos_irq_set_type,
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 		.irq_request_resources = exynos_irq_request_resources,
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 		.irq_release_resources = exynos_irq_release_resources,
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+		.flags = IRQCHIP_PIPELINE_SAFE,
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 	},
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 	.eint_con = EXYNOS_GPIO_ECON_OFFSET,
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 	.eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
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@@ -287,7 +288,7 @@
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 	}
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 	ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
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-					0, dev_name(dev), d);
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+					IRQF_OOB, dev_name(dev), d);
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 	if (ret) {
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 		dev_err(dev, "irq request failed\n");
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 		return -ENXIO;
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@@ -305,6 +306,7 @@
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 			goto err_domains;
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 		}
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 		bank->irq_chip->chip.name = bank->name;
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+		bank->irq_chip->chip.flags |= IRQCHIP_PIPELINE_SAFE;
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 		bank->irq_domain = irq_domain_add_linear(bank->of_node,
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 				bank->nr_pins, &exynos_eint_irqd_ops, bank);
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@@ -408,6 +410,7 @@
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 		.irq_set_wake = exynos_wkup_irq_set_wake,
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 		.irq_request_resources = exynos_irq_request_resources,
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 		.irq_release_resources = exynos_irq_release_resources,
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+		.flags = IRQCHIP_PIPELINE_SAFE,
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 	},
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 	.eint_con = EXYNOS_WKUP_ECON_OFFSET,
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 	.eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
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@@ -428,6 +431,7 @@
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 		.irq_set_wake = exynos_wkup_irq_set_wake,
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 		.irq_request_resources = exynos_irq_request_resources,
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 		.irq_release_resources = exynos_irq_release_resources,
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+		.flags = IRQCHIP_PIPELINE_SAFE,
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 	},
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 	.eint_con = EXYNOS_WKUP_ECON_OFFSET,
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 	.eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
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@@ -447,6 +451,7 @@
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 		.irq_set_wake = exynos_wkup_irq_set_wake,
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 		.irq_request_resources = exynos_irq_request_resources,
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 		.irq_release_resources = exynos_irq_release_resources,
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+		.flags = IRQCHIP_PIPELINE_SAFE,
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 	},
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 	.eint_con = EXYNOS7_WKUP_ECON_OFFSET,
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 	.eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,