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| 562 | 562 | * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), |
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| 563 | 563 | * errata #CHT34, for further information. |
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| 564 | 564 | */ |
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| 565 | | -static DEFINE_RAW_SPINLOCK(chv_lock); |
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| 565 | +static DEFINE_HARD_SPINLOCK(chv_lock); |
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| 566 | 566 | |
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| 567 | 567 | static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset) |
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| 568 | 568 | { |
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| .. | .. |
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| 1554 | 1554 | pctrl->irqchip.irq_mask = chv_gpio_irq_mask; |
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| 1555 | 1555 | pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask; |
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| 1556 | 1556 | pctrl->irqchip.irq_set_type = chv_gpio_irq_type; |
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| 1557 | | - pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE; |
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| 1557 | + pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE | |
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| 1558 | + IRQCHIP_PIPELINE_SAFE; |
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| 1558 | 1559 | |
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| 1559 | 1560 | chip->irq.chip = &pctrl->irqchip; |
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| 1560 | 1561 | chip->irq.init_hw = chv_gpio_irq_init_hw; |
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