gpio config

hc

2024-11-01 830ce1f69238136c0197858242f16cf44e0d6cb9

 kernel/arch/arm/mm/context.c
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@@ -39,7 +39,7 @@
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 #define ASID_FIRST_VERSION	(1ULL << ASID_BITS)
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 #define NUM_USER_ASIDS		ASID_FIRST_VERSION
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-static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
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+static DEFINE_HARD_SPINLOCK(cpu_asid_lock);
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 static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION);
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 static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS);
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@@ -237,8 +237,11 @@
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 void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk)
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 {
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 	unsigned long flags;
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-	unsigned int cpu = smp_processor_id();
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+	unsigned int cpu = raw_smp_processor_id();
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+	bool need_flush;
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 	u64 asid;
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+
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+	WARN_ON_ONCE(dovetail_debug() && !hard_irqs_disabled());
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 	if (unlikely(mm->context.vmalloc_seq != init_mm.context.vmalloc_seq))
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 		__check_vmalloc_seq(mm);
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@@ -263,15 +266,16 @@
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 		atomic64_set(&mm->context.id, asid);
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 	}
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-	if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending)) {
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-		local_flush_bp_all();
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-		local_flush_tlb_all();
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-	}
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-
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+	need_flush = cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending);
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 	atomic64_set(&per_cpu(active_asids, cpu), asid);
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 	cpumask_set_cpu(cpu, mm_cpumask(mm));
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 	raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
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+	if (need_flush) {
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+		local_flush_bp_all();
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+		local_flush_tlb_all();
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+	}
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+
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 switch_mm_fastpath:
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 	cpu_switch_mm(mm->pgd, mm);
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 }