.. | .. |
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89 | 89 | .irq_unmask = gicv2m_unmask_msi_irq, |
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90 | 90 | .irq_eoi = irq_chip_eoi_parent, |
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91 | 91 | .irq_write_msi_msg = pci_msi_domain_write_msg, |
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| 92 | + .flags = IRQCHIP_PIPELINE_SAFE, |
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92 | 93 | }; |
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93 | 94 | |
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94 | 95 | static struct msi_domain_info gicv2m_msi_domain_info = { |
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.. | .. |
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130 | 131 | .irq_eoi = irq_chip_eoi_parent, |
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131 | 132 | .irq_set_affinity = irq_chip_set_affinity_parent, |
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132 | 133 | .irq_compose_msi_msg = gicv2m_compose_msi_msg, |
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| 134 | + .flags = IRQCHIP_PIPELINE_SAFE, |
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133 | 135 | }; |
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134 | 136 | |
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135 | 137 | static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain, |
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.. | .. |
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252 | 254 | |
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253 | 255 | static struct irq_chip gicv2m_pmsi_irq_chip = { |
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254 | 256 | .name = "pMSI", |
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| 257 | + .flags = IRQCHIP_PIPELINE_SAFE, |
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255 | 258 | }; |
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256 | 259 | |
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257 | 260 | static struct msi_domain_ops gicv2m_pmsi_ops = { |
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