.. | .. |
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24 | 24 | |
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25 | 25 | #define IRQ_IN_COMBINER 8 |
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26 | 26 | |
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27 | | -static DEFINE_SPINLOCK(irq_controller_lock); |
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| 27 | +static DEFINE_HARD_SPINLOCK(irq_controller_lock); |
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28 | 28 | |
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29 | 29 | struct combiner_chip_data { |
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30 | 30 | unsigned int hwirq_offset; |
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.. | .. |
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71 | 71 | |
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72 | 72 | chained_irq_enter(chip, desc); |
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73 | 73 | |
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74 | | - spin_lock(&irq_controller_lock); |
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| 74 | + raw_spin_lock(&irq_controller_lock); |
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75 | 75 | status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS); |
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76 | | - spin_unlock(&irq_controller_lock); |
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| 76 | + raw_spin_unlock(&irq_controller_lock); |
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77 | 77 | status &= chip_data->irq_mask; |
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78 | 78 | |
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79 | 79 | if (status == 0) |
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.. | .. |
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113 | 113 | #ifdef CONFIG_SMP |
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114 | 114 | .irq_set_affinity = combiner_set_affinity, |
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115 | 115 | #endif |
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| 116 | + .flags = IRQCHIP_PIPELINE_SAFE, |
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116 | 117 | }; |
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117 | 118 | |
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118 | 119 | static void __init combiner_cascade_irq(struct combiner_chip_data *combiner_data, |
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