add xenomai

hc

2024-11-01 2f529f9b558ca1c1bd74be7437a84e4711743404

 kernel/drivers/clocksource/exynos_mct.c
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@@ -194,23 +194,20 @@
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 	return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
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 }
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-static u64 exynos4_frc_read(struct clocksource *cs)
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-{
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-	return exynos4_read_count_32();
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-}
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-
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 static void exynos4_frc_resume(struct clocksource *cs)
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 {
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 	exynos4_mct_frc_start();
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 }
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-static struct clocksource mct_frc = {
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-	.name		= "mct-frc",
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-	.rating		= 450,	/* use value higher than ARM arch timer */
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-	.read		= exynos4_frc_read,
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-	.mask		= CLOCKSOURCE_MASK(32),
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-	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
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-	.resume		= exynos4_frc_resume,
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+static struct clocksource_user_mmio mct_frc = {
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+	.mmio.clksrc = {
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+		.name		= "mct-frc",
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+		.rating		= 450,	/* use value higher than ARM arch timer */
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+		.read		= clocksource_mmio_readl_up,
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+		.mask		= CLOCKSOURCE_MASK(32),
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+		.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
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+		.resume		= exynos4_frc_resume,
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+	},
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 };
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 static u64 notrace exynos4_read_sched_clock(void)
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@@ -231,6 +228,8 @@
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 static int __init exynos4_clocksource_init(void)
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 {
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+	struct clocksource_mmio_regs mmr;
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+
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 	exynos4_mct_frc_start();
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 #if defined(CONFIG_ARM)
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@@ -239,8 +238,13 @@
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 	register_current_timer_delay(&exynos4_delay_timer);
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 #endif
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-	if (clocksource_register_hz(&mct_frc, clk_rate))
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-		panic("%s: can't register clocksource\n", mct_frc.name);
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+	mmr.reg_upper = NULL;
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+	mmr.reg_lower = reg_base + EXYNOS4_MCT_G_CNT_L;
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+	mmr.bits_upper = 0;
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+	mmr.bits_lower = 32;
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+	mmr.revmap = NULL;
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+	if (clocksource_user_mmio_init(&mct_frc, &mmr, clk_rate))
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+		panic("%s: can't register clocksource\n", mct_frc.mmio.clksrc.name);
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 	sched_clock_register(exynos4_read_sched_clock, 32, clk_rate);
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@@ -308,7 +312,8 @@
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 static struct clock_event_device mct_comp_device = {
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 	.name			= "mct-comp",
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 	.features		= CLOCK_EVT_FEAT_PERIODIC |
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-				  CLOCK_EVT_FEAT_ONESHOT,
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+				  CLOCK_EVT_FEAT_ONESHOT |
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+				  CLOCK_EVT_FEAT_PIPELINE,
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 	.rating			= 250,
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 	.set_next_event		= exynos4_comp_set_next_event,
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 	.set_state_periodic	= mct_set_state_periodic,
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@@ -324,7 +329,7 @@
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 	exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
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-	evt->event_handler(evt);
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+	clockevents_handle_event(evt);
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 	return IRQ_HANDLED;
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 }
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@@ -335,7 +340,7 @@
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 	clockevents_config_and_register(&mct_comp_device, clk_rate,
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 					0xf, 0xffffffff);
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 	if (request_irq(mct_irqs[MCT_G0_IRQ], exynos4_mct_comp_isr,
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-			IRQF_TIMER | IRQF_IRQPOLL, "mct_comp_irq",
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+			IRQF_TIMER | IRQF_IRQPOLL | IRQF_OOB, "mct_comp_irq",
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 			&mct_comp_device))
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 		pr_err("%s: request_irq() failed\n", "mct_comp_irq");
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@@ -434,7 +439,7 @@
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 	exynos4_mct_tick_clear(mevt);
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-	evt->event_handler(evt);
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+	clockevents_handle_event(evt);
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 	return IRQ_HANDLED;
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 }
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@@ -456,7 +461,8 @@
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 	evt->set_state_oneshot = set_state_shutdown;
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 	evt->set_state_oneshot_stopped = set_state_shutdown;
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 	evt->tick_resume = set_state_shutdown;
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-	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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+	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | \
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+		CLOCK_EVT_FEAT_PIPELINE;
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 	evt->rating = 500;	/* use value higher than ARM arch timer */
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 	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
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@@ -541,9 +547,9 @@
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 	if (mct_int_type == MCT_INT_PPI) {
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-		err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
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-					 exynos4_mct_tick_isr, "MCT",
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-					 &percpu_mct_tick);
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+		err = __request_percpu_irq(mct_irqs[MCT_L0_IRQ],
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+					exynos4_mct_tick_isr, IRQF_TIMER,
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+					"MCT", &percpu_mct_tick);
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 		WARN(err, "MCT: can't request IRQ %d (%d)\n",
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 		     mct_irqs[MCT_L0_IRQ], err);
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 	} else {