add xenomai

hc

2024-11-01 2f529f9b558ca1c1bd74be7437a84e4711743404

 kernel/drivers/clocksource/dw_apb_timer.c
..
..
@@ -43,7 +43,7 @@
43
43
 static inline struct dw_apb_clocksource *
44
44
 clocksource_to_dw_apb_clocksource(struct clocksource *cs)
45
45
 {
46
-	return container_of(cs, struct dw_apb_clocksource, cs);
46
+	return container_of(cs, struct dw_apb_clocksource, ummio.mmio.clksrc);
47
47
 }
48
48
 
49
49
 static inline u32 apbt_readl(struct dw_apb_timer *timer, unsigned long offs)
..
..
@@ -343,18 +343,6 @@
343
343
 	dw_apb_clocksource_read(dw_cs);
344
344
 }
345
345
 
346
-static u64 __apbt_read_clocksource(struct clocksource *cs)
347
-{
348
-	u32 current_count;
349
-	struct dw_apb_clocksource *dw_cs =
350
-		clocksource_to_dw_apb_clocksource(cs);
351
-
352
-	current_count = apbt_readl_relaxed(&dw_cs->timer,
353
-					APBTMR_N_CURRENT_VALUE);
354
-
355
-	return (u64)~current_count;
356
-}
357
-
358
346
 static void apbt_restart_clocksource(struct clocksource *cs)
359
347
 {
360
348
 	struct dw_apb_clocksource *dw_cs =
..
..
@@ -376,7 +364,7 @@
376
364
  * dw_apb_clocksource_register() as the next step.
377
365
  */
378
366
 struct dw_apb_clocksource *
379
-dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base,
367
+__init dw_apb_clocksource_init(unsigned rating, const char *name, void __iomem *base,
380
368
 			unsigned long freq)
381
369
 {
382
370
 	struct dw_apb_clocksource *dw_cs = kzalloc(sizeof(*dw_cs), GFP_KERNEL);
..
..
@@ -386,12 +374,12 @@
386
374
 
387
375
 	dw_cs->timer.base = base;
388
376
 	dw_cs->timer.freq = freq;
389
-	dw_cs->cs.name = name;
390
-	dw_cs->cs.rating = rating;
391
-	dw_cs->cs.read = __apbt_read_clocksource;
392
-	dw_cs->cs.mask = CLOCKSOURCE_MASK(32);
393
-	dw_cs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
394
-	dw_cs->cs.resume = apbt_restart_clocksource;
377
+	dw_cs->ummio.mmio.clksrc.name = name;
378
+	dw_cs->ummio.mmio.clksrc.rating = rating;
379
+	dw_cs->ummio.mmio.clksrc.read = clocksource_mmio_readl_down;
380
+	dw_cs->ummio.mmio.clksrc.mask = CLOCKSOURCE_MASK(32);
381
+	dw_cs->ummio.mmio.clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
382
+	dw_cs->ummio.mmio.clksrc.resume = apbt_restart_clocksource;
395
383
 
396
384
 	return dw_cs;
397
385
 }
..
..
@@ -401,9 +389,17 @@
401
389
  *
402
390
  * @dw_cs:	The clocksource to register.
403
391
  */
404
-void dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs)
392
+void __init dw_apb_clocksource_register(struct dw_apb_clocksource *dw_cs)
405
393
 {
406
-	clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq);
394
+	struct clocksource_mmio_regs mmr;
395
+
396
+	mmr.reg_lower = dw_cs->timer.base + APBTMR_N_CURRENT_VALUE;
397
+	mmr.bits_lower = 32;
398
+	mmr.reg_upper = 0;
399
+	mmr.bits_upper = 0;
400
+	mmr.revmap = NULL;
401
+
402
+	clocksource_user_mmio_init(&dw_cs->ummio, &mmr, dw_cs->timer.freq);
407
403
 }
408
404
 
409
405
 /**