.. | .. |
---|
181 | 181 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
---|
182 | 182 | .irq_set_affinity = msi_set_affinity, |
---|
183 | 183 | .flags = IRQCHIP_SKIP_SET_WAKE | |
---|
184 | | - IRQCHIP_AFFINITY_PRE_STARTUP, |
---|
| 184 | + IRQCHIP_AFFINITY_PRE_STARTUP | |
---|
| 185 | + IRQCHIP_PIPELINE_SAFE, |
---|
185 | 186 | }; |
---|
186 | 187 | |
---|
187 | 188 | int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec, |
---|
.. | .. |
---|
251 | 252 | .irq_ack = irq_chip_ack_parent, |
---|
252 | 253 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
---|
253 | 254 | .flags = IRQCHIP_SKIP_SET_WAKE | |
---|
254 | | - IRQCHIP_AFFINITY_PRE_STARTUP, |
---|
| 255 | + IRQCHIP_AFFINITY_PRE_STARTUP | |
---|
| 256 | + IRQCHIP_PIPELINE_SAFE, |
---|
255 | 257 | }; |
---|
256 | 258 | |
---|
257 | 259 | static struct msi_domain_info pci_msi_ir_domain_info = { |
---|
.. | .. |
---|
294 | 296 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
---|
295 | 297 | .irq_write_msi_msg = dmar_msi_write_msg, |
---|
296 | 298 | .flags = IRQCHIP_SKIP_SET_WAKE | |
---|
297 | | - IRQCHIP_AFFINITY_PRE_STARTUP, |
---|
| 299 | + IRQCHIP_AFFINITY_PRE_STARTUP | |
---|
| 300 | + IRQCHIP_PIPELINE_SAFE, |
---|
298 | 301 | }; |
---|
299 | 302 | |
---|
300 | 303 | static int dmar_msi_init(struct irq_domain *domain, |
---|
.. | .. |
---|
386 | 389 | .irq_set_affinity = msi_domain_set_affinity, |
---|
387 | 390 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
---|
388 | 391 | .irq_write_msi_msg = hpet_msi_write_msg, |
---|
389 | | - .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_AFFINITY_PRE_STARTUP, |
---|
| 392 | + .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_AFFINITY_PRE_STARTUP | |
---|
| 393 | + IRQCHIP_PIPELINE_SAFE, |
---|
390 | 394 | }; |
---|
391 | 395 | |
---|
392 | 396 | static int hpet_msi_init(struct irq_domain *domain, |
---|