| .. | .. |
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| 12 | 12 | #include <asm/cpufeature.h> |
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| 13 | 13 | #include <asm/ptrace.h> |
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| 14 | 14 | |
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| 15 | +/* |
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| 16 | + * irq_pipeline: DAIF masking is only used in contexts where hard |
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| 17 | + * interrupt masking applies, so no need to virtualize for the inband |
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| 18 | + * stage here (the pipeline core does assume this). |
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| 19 | + */ |
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| 20 | + |
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| 15 | 21 | #define DAIF_PROCCTX 0 |
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| 16 | 22 | #define DAIF_PROCCTX_NOIRQ PSR_I_BIT |
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| 17 | 23 | #define DAIF_ERRCTX (PSR_I_BIT | PSR_A_BIT) |
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| .. | .. |
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| 35 | 41 | if (system_uses_irq_prio_masking()) |
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| 36 | 42 | gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET); |
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| 37 | 43 | |
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| 38 | | - trace_hardirqs_off(); |
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| 44 | + trace_hardirqs_off_pipelined(); |
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| 39 | 45 | } |
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| 40 | 46 | |
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| 41 | 47 | static inline unsigned long local_daif_save_flags(void) |
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| .. | .. |
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| 72 | 78 | !(read_sysreg(daif) & PSR_I_BIT)); |
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| 73 | 79 | |
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| 74 | 80 | if (!irq_disabled) { |
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| 75 | | - trace_hardirqs_on(); |
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| 81 | + trace_hardirqs_on_pipelined(); |
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| 76 | 82 | |
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| 77 | 83 | if (system_uses_irq_prio_masking()) { |
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| 78 | 84 | gic_write_pmr(GIC_PRIO_IRQON); |
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| .. | .. |
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| 117 | 123 | write_sysreg(flags, daif); |
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| 118 | 124 | |
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| 119 | 125 | if (irq_disabled) |
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| 120 | | - trace_hardirqs_off(); |
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| 126 | + trace_hardirqs_off_pipelined(); |
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| 121 | 127 | } |
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| 122 | 128 | |
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| 123 | 129 | /* |
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| .. | .. |
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| 129 | 135 | unsigned long flags = regs->pstate & DAIF_MASK; |
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| 130 | 136 | |
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| 131 | 137 | if (interrupts_enabled(regs)) |
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| 132 | | - trace_hardirqs_on(); |
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| 138 | + trace_hardirqs_on_pipelined(); |
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| 133 | 139 | |
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| 134 | 140 | if (system_uses_irq_prio_masking()) |
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| 135 | 141 | gic_write_pmr(regs->pmr_save); |
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