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2024-11-01 2f529f9b558ca1c1bd74be7437a84e4711743404

 kernel/arch/arm/mm/cache-l2x0.c
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@@ -38,7 +38,7 @@
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 static void __iomem *l2x0_base;
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 static const struct l2c_init_data *l2x0_data;
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-static DEFINE_RAW_SPINLOCK(l2x0_lock);
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+static DEFINE_HARD_SPINLOCK(l2x0_lock);
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 static u32 l2x0_way_mask;	/* Bitmask of active ways */
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 static u32 l2x0_size;
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 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
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@@ -47,6 +47,19 @@
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 static bool l2x0_bresp_disable;
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 static bool l2x0_flz_disable;
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+
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+#ifdef CONFIG_IRQ_PIPELINE
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+#define CACHE_RANGE_ATOMIC_MAX	512UL
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+static int l2x0_wa = -1;
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+static int __init l2x0_setup_wa(char *str)
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+{
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+	l2x0_wa = !!simple_strtol(str, NULL, 0);
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+	return 0;
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+}
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+early_param("l2x0_write_allocate", l2x0_setup_wa);
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+#else
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+#define CACHE_RANGE_ATOMIC_MAX	4096UL
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+#endif
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63
 
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 /*
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  * Common code for all cache controllers.
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@@ -120,11 +133,11 @@
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 	l2x0_data->unlock(base, num_lock);
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-	local_irq_save(flags);
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+	flags = hard_local_irq_save();
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 	__l2c_op_way(base + L2X0_INV_WAY);
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 	writel_relaxed(0, base + sync_reg_offset);
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 	l2c_wait_mask(base + sync_reg_offset, 1);
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-	local_irq_restore(flags);
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+	hard_local_irq_restore(flags);
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 	l2c_write_sec(L2X0_CTRL_EN, base, L2X0_CTRL);
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 }
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@@ -225,7 +238,7 @@
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 {
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 	void __iomem *base = l2x0_base;
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-	BUG_ON(!irqs_disabled());
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+	BUG_ON(!hard_irqs_disabled());
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 	__l2c_op_way(base + L2X0_CLEAN_INV_WAY);
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 	__l2c210_cache_sync(base);
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@@ -284,10 +297,10 @@
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 static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start,
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 	unsigned long end, unsigned long flags)
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 {
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-	raw_spinlock_t *lock = &l2x0_lock;
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+	typeof(l2x0_lock) *lock = &l2x0_lock;
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 	while (start < end) {
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-		unsigned long blk_end = start + min(end - start, 4096UL);
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+		unsigned long blk_end = start + min(end - start, CACHE_RANGE_ATOMIC_MAX);
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 		while (start < blk_end) {
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 			l2c_wait_mask(reg, 1);
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@@ -498,13 +511,13 @@
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 static void l2c310_flush_range_erratum(unsigned long start, unsigned long end)
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 {
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-	raw_spinlock_t *lock = &l2x0_lock;
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+	typeof(l2x0_lock) *lock = &l2x0_lock;
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 	unsigned long flags;
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 	void __iomem *base = l2x0_base;
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 	raw_spin_lock_irqsave(lock, flags);
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 	while (start < end) {
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-		unsigned long blk_end = start + min(end - start, 4096UL);
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+		unsigned long blk_end = start + min(end - start, CACHE_RANGE_ATOMIC_MAX);
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 		l2c_set_debug(base, 0x03);
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 		while (start < blk_end) {
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@@ -800,6 +813,24 @@
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 	if (aux_val & aux_mask)
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 		pr_alert("L2C: platform provided aux values permit register corruption.\n");
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815
 
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+#ifdef CONFIG_IRQ_PIPELINE
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+	if (!l2x0_wa) {
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+		/*
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+		 * Disable WA by setting bit 23 in the auxiliary
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+		 * control register.
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+		 */
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+		aux_mask &= ~L220_AUX_CTRL_FWA_MASK;
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+		aux_val &= ~L220_AUX_CTRL_FWA_MASK;
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+		aux_val |= 1 << L220_AUX_CTRL_FWA_SHIFT;
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+		pr_warn("%s: irq_pipeline: write-allocate disabled via command line\n",
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+			data->type);
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+	} else if ((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L220 ||
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+		   ((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L310 &&
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+		    (cache_id & L2X0_CACHE_ID_RTL_MASK) < L310_CACHE_ID_RTL_R3P2))
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+		pr_alert("%s: irq_pipeline: write-allocate enabled, may induce high latency\n",
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+			 data->type);
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+#endif
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+
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 	old_aux = aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
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 	aux &= aux_mask;
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 	aux |= aux_val;