add xenomai

hc

2024-11-01 2f529f9b558ca1c1bd74be7437a84e4711743404

 kernel/arch/arm/mach-imx/gpc.c
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@@ -62,28 +62,38 @@
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 void imx_gpc_pre_suspend(bool arm_power_off)
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 {
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 	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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+	unsigned long flags;
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 	int i;
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 	/* Tell GPC to power off ARM core when suspend */
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 	if (arm_power_off)
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 		imx_gpc_set_arm_power_in_lpm(arm_power_off);
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+	flags = hard_cond_local_irq_save();
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+
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 	for (i = 0; i < IMR_NUM; i++) {
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 		gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
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 		writel_relaxed(~gpc_wake_irqs[i], reg_imr1 + i * 4);
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 	}
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+
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+	hard_cond_local_irq_restore(flags);
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 }
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 void imx_gpc_post_resume(void)
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 {
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 	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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+	unsigned long flags;
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 	int i;
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 	/* Keep ARM core powered on for other low-power modes */
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 	imx_gpc_set_arm_power_in_lpm(false);
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+	flags = hard_cond_local_irq_save();
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+
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 	for (i = 0; i < IMR_NUM; i++)
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 		writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
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+
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+	hard_cond_local_irq_restore(flags);
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 }
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 static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
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@@ -105,21 +115,31 @@
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 void imx_gpc_mask_all(void)
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 {
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 	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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+	unsigned long flags;
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 	int i;
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+
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+	flags = hard_cond_local_irq_save();
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 	for (i = 0; i < IMR_NUM; i++) {
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 		gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
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 		writel_relaxed(~0, reg_imr1 + i * 4);
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 	}
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+
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+	hard_cond_local_irq_restore(flags);
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 }
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 void imx_gpc_restore_all(void)
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 {
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 	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
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+	unsigned long flags;
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 	int i;
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+
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+	flags = hard_cond_local_irq_save();
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 	for (i = 0; i < IMR_NUM; i++)
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 		writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
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+
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+	hard_cond_local_irq_restore(flags);
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 }
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 void imx_gpc_hwirq_unmask(unsigned int hwirq)
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@@ -167,6 +187,7 @@
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 #ifdef CONFIG_SMP
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 	.irq_set_affinity	= irq_chip_set_affinity_parent,
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 #endif
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+	.flags			= IRQCHIP_PIPELINE_SAFE,
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 };
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 static int imx_gpc_domain_translate(struct irq_domain *d,